1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_LIMITS_H__ 7 #define __INTEL_DISPLAY_LIMITS_H__ 8 9 /* 10 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 11 * rest have consecutive values and match the enum values of transcoders 12 * with a 1:1 transcoder -> pipe mapping. 13 */ 14 enum pipe { 15 INVALID_PIPE = -1, 16 17 PIPE_A = 0, 18 PIPE_B, 19 PIPE_C, 20 PIPE_D, 21 _PIPE_EDP, 22 23 I915_MAX_PIPES = _PIPE_EDP 24 }; 25 26 enum transcoder { 27 INVALID_TRANSCODER = -1, 28 /* 29 * The following transcoders have a 1:1 transcoder -> pipe mapping, 30 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 31 * rest have consecutive values and match the enum values of the pipes 32 * they map to. 33 */ 34 TRANSCODER_A = PIPE_A, 35 TRANSCODER_B = PIPE_B, 36 TRANSCODER_C = PIPE_C, 37 TRANSCODER_D = PIPE_D, 38 39 /* 40 * The following transcoders can map to any pipe, their enum value 41 * doesn't need to stay fixed. 42 */ 43 TRANSCODER_EDP, 44 TRANSCODER_DSI_0, 45 TRANSCODER_DSI_1, 46 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 47 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 48 49 I915_MAX_TRANSCODERS 50 }; 51 52 /* 53 * Global legacy plane identifier. Valid only for primary/sprite 54 * planes on pre-g4x, and only for primary planes on g4x-bdw. 55 */ 56 enum i9xx_plane_id { 57 PLANE_A, 58 PLANE_B, 59 PLANE_C, 60 }; 61 62 /* 63 * Per-pipe plane identifier. 64 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 65 * number of planes per CRTC. Not all platforms really have this many planes, 66 * which means some arrays of size I915_MAX_PLANES may have unused entries 67 * between the topmost sprite plane and the cursor plane. 68 * 69 * This is expected to be passed to various register macros 70 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 71 */ 72 enum plane_id { 73 /* skl+ universal plane names */ 74 PLANE_1, 75 PLANE_2, 76 PLANE_3, 77 PLANE_4, 78 PLANE_5, 79 PLANE_6, 80 PLANE_7, 81 82 PLANE_CURSOR, 83 84 I915_MAX_PLANES, 85 86 /* pre-skl plane names */ 87 PLANE_PRIMARY = PLANE_1, 88 PLANE_SPRITE0, 89 PLANE_SPRITE1, 90 }; 91 92 enum port { 93 PORT_NONE = -1, 94 95 PORT_A = 0, 96 PORT_B, 97 PORT_C, 98 PORT_D, 99 PORT_E, 100 PORT_F, 101 PORT_G, 102 PORT_H, 103 PORT_I, 104 105 /* tgl+ */ 106 PORT_TC1 = PORT_D, 107 PORT_TC2, 108 PORT_TC3, 109 PORT_TC4, 110 PORT_TC5, 111 PORT_TC6, 112 113 /* XE_LPD repositions D/E offsets and bitfields */ 114 PORT_D_XELPD = PORT_TC5, 115 PORT_E_XELPD, 116 117 I915_MAX_PORTS 118 }; 119 120 enum hpd_pin { 121 HPD_NONE = 0, 122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 123 HPD_CRT, 124 HPD_SDVO_B, 125 HPD_SDVO_C, 126 HPD_PORT_A, 127 HPD_PORT_B, 128 HPD_PORT_C, 129 HPD_PORT_D, 130 HPD_PORT_E, 131 HPD_PORT_TC1, 132 HPD_PORT_TC2, 133 HPD_PORT_TC3, 134 HPD_PORT_TC4, 135 HPD_PORT_TC5, 136 HPD_PORT_TC6, 137 138 HPD_NUM_PINS 139 }; 140 141 #endif /* __INTEL_DISPLAY_LIMITS_H__ */ 142