1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_LIMITS_H__ 7 #define __INTEL_DISPLAY_LIMITS_H__ 8 9 /* 10 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 11 * rest have consecutive values and match the enum values of transcoders 12 * with a 1:1 transcoder -> pipe mapping. 13 */ 14 enum pipe { 15 INVALID_PIPE = -1, 16 17 PIPE_A = 0, 18 PIPE_B, 19 PIPE_C, 20 PIPE_D, 21 _PIPE_EDP, 22 23 I915_MAX_PIPES = _PIPE_EDP 24 }; 25 26 enum transcoder { 27 INVALID_TRANSCODER = -1, 28 /* 29 * The following transcoders have a 1:1 transcoder -> pipe mapping, 30 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 31 * rest have consecutive values and match the enum values of the pipes 32 * they map to. 33 */ 34 TRANSCODER_A = PIPE_A, 35 TRANSCODER_B = PIPE_B, 36 TRANSCODER_C = PIPE_C, 37 TRANSCODER_D = PIPE_D, 38 39 /* 40 * The following transcoders can map to any pipe, their enum value 41 * doesn't need to stay fixed. 42 */ 43 TRANSCODER_EDP, 44 TRANSCODER_DSI_0, 45 TRANSCODER_DSI_1, 46 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 47 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 48 TRANSCODER_CMTG0, 49 TRANSCODER_CMTG1, 50 51 I915_MAX_TRANSCODERS 52 }; 53 54 /* 55 * Global legacy plane identifier. Valid only for primary/sprite 56 * planes on pre-g4x, and only for primary planes on g4x-bdw. 57 */ 58 enum i9xx_plane_id { 59 PLANE_A, 60 PLANE_B, 61 PLANE_C, 62 }; 63 64 /* 65 * Per-pipe plane identifier. 66 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 67 * number of planes per CRTC. Not all platforms really have this many planes, 68 * which means some arrays of size I915_MAX_PLANES may have unused entries 69 * between the topmost sprite plane and the cursor plane. 70 * 71 * This is expected to be passed to various register macros 72 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 73 */ 74 enum plane_id { 75 /* skl+ universal plane names */ 76 PLANE_1, 77 PLANE_2, 78 PLANE_3, 79 PLANE_4, 80 PLANE_5, 81 PLANE_6, 82 PLANE_7, 83 84 PLANE_CURSOR, 85 86 I915_MAX_PLANES, 87 88 /* pre-skl plane names */ 89 PLANE_PRIMARY = PLANE_1, 90 PLANE_SPRITE0, 91 PLANE_SPRITE1, 92 }; 93 94 enum port { 95 PORT_NONE = -1, 96 97 PORT_A = 0, 98 PORT_B, 99 PORT_C, 100 PORT_D, 101 PORT_E, 102 PORT_F, 103 PORT_G, 104 PORT_H, 105 PORT_I, 106 107 /* tgl+ */ 108 PORT_TC1 = PORT_D, 109 PORT_TC2, 110 PORT_TC3, 111 PORT_TC4, 112 PORT_TC5, 113 PORT_TC6, 114 115 /* XE_LPD repositions D/E offsets and bitfields */ 116 PORT_D_XELPD = PORT_TC5, 117 PORT_E_XELPD, 118 119 I915_MAX_PORTS 120 }; 121 122 enum hpd_pin { 123 HPD_NONE = 0, 124 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 125 HPD_CRT, 126 HPD_SDVO_B, 127 HPD_SDVO_C, 128 HPD_PORT_A, 129 HPD_PORT_B, 130 HPD_PORT_C, 131 HPD_PORT_D, 132 HPD_PORT_E, 133 HPD_PORT_TC1, 134 HPD_PORT_TC2, 135 HPD_PORT_TC3, 136 HPD_PORT_TC4, 137 HPD_PORT_TC5, 138 HPD_PORT_TC6, 139 140 HPD_NUM_PINS 141 }; 142 143 enum aux_ch { 144 AUX_CH_NONE = -1, 145 146 AUX_CH_A, 147 AUX_CH_B, 148 AUX_CH_C, 149 AUX_CH_D, 150 AUX_CH_E, /* ICL+ */ 151 AUX_CH_F, 152 AUX_CH_G, 153 AUX_CH_H, 154 AUX_CH_I, 155 156 /* tgl+ */ 157 AUX_CH_USBC1 = AUX_CH_D, 158 AUX_CH_USBC2, 159 AUX_CH_USBC3, 160 AUX_CH_USBC4, 161 AUX_CH_USBC5, 162 AUX_CH_USBC6, 163 164 /* XE_LPD repositions D/E offsets and bitfields */ 165 AUX_CH_D_XELPD = AUX_CH_USBC5, 166 AUX_CH_E_XELPD, 167 }; 168 169 enum intel_color_block { 170 INTEL_PLANE_CB_PRE_CSC_LUT, 171 INTEL_PLANE_CB_CSC, 172 INTEL_PLANE_CB_POST_CSC_LUT, 173 INTEL_PLANE_CB_3DLUT, 174 175 INTEL_CB_MAX 176 }; 177 178 #endif /* __INTEL_DISPLAY_LIMITS_H__ */ 179