1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_IRQ_H__ 7 #define __INTEL_DISPLAY_IRQ_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 13 enum pipe; 14 struct drm_crtc; 15 struct intel_display; 16 17 void valleyview_enable_display_irqs(struct intel_display *display); 18 void valleyview_disable_display_irqs(struct intel_display *display); 19 20 void ilk_update_display_irq(struct intel_display *display, 21 u32 interrupt_mask, u32 enabled_irq_mask); 22 void ilk_enable_display_irq(struct intel_display *display, u32 bits); 23 void ilk_disable_display_irq(struct intel_display *display, u32 bits); 24 25 void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask); 26 void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); 27 void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); 28 29 void ibx_display_interrupt_update(struct intel_display *display, 30 u32 interrupt_mask, u32 enabled_irq_mask); 31 void ibx_enable_display_interrupt(struct intel_display *display, u32 bits); 32 void ibx_disable_display_interrupt(struct intel_display *display, u32 bits); 33 34 void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask); 35 void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask); 36 37 int i8xx_enable_vblank(struct drm_crtc *crtc); 38 int i915gm_enable_vblank(struct drm_crtc *crtc); 39 int i965_enable_vblank(struct drm_crtc *crtc); 40 int ilk_enable_vblank(struct drm_crtc *crtc); 41 int bdw_enable_vblank(struct drm_crtc *crtc); 42 void i8xx_disable_vblank(struct drm_crtc *crtc); 43 void i915gm_disable_vblank(struct drm_crtc *crtc); 44 void i965_disable_vblank(struct drm_crtc *crtc); 45 void ilk_disable_vblank(struct drm_crtc *crtc); 46 void bdw_disable_vblank(struct drm_crtc *crtc); 47 48 void ivb_display_irq_handler(struct intel_display *display, u32 de_iir); 49 void ilk_display_irq_handler(struct intel_display *display, u32 de_iir); 50 void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl); 51 void gen11_display_irq_handler(struct intel_display *display); 52 53 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl); 54 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir); 55 56 void i9xx_display_irq_reset(struct intel_display *display); 57 void vlv_display_irq_reset(struct intel_display *display); 58 void gen8_display_irq_reset(struct intel_display *display); 59 void gen11_display_irq_reset(struct intel_display *display); 60 61 void vlv_display_irq_postinstall(struct intel_display *display); 62 void ilk_de_irq_postinstall(struct intel_display *display); 63 void gen8_de_irq_postinstall(struct intel_display *display); 64 void gen11_de_irq_postinstall(struct intel_display *display); 65 void dg1_de_irq_postinstall(struct intel_display *display); 66 67 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); 68 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); 69 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); 70 void i915_enable_asle_pipestat(struct intel_display *display); 71 72 void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 73 74 void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 75 void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 76 void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]); 77 78 void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); 79 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt); 80 81 void intel_display_irq_init(struct intel_display *display); 82 83 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable); 84 85 #endif /* __INTEL_DISPLAY_IRQ_H__ */ 86