1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_IRQ_H__ 7 #define __INTEL_DISPLAY_IRQ_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 13 enum pipe; 14 struct drm_crtc; 15 struct drm_printer; 16 struct intel_display; 17 struct intel_display_irq_snapshot; 18 19 void valleyview_enable_display_irqs(struct intel_display *display); 20 void valleyview_disable_display_irqs(struct intel_display *display); 21 22 void ilk_update_display_irq(struct intel_display *display, 23 u32 interrupt_mask, u32 enabled_irq_mask); 24 void ilk_enable_display_irq(struct intel_display *display, u32 bits); 25 void ilk_disable_display_irq(struct intel_display *display, u32 bits); 26 27 void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask); 28 void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); 29 void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); 30 31 void ibx_display_interrupt_update(struct intel_display *display, 32 u32 interrupt_mask, u32 enabled_irq_mask); 33 void ibx_enable_display_interrupt(struct intel_display *display, u32 bits); 34 void ibx_disable_display_interrupt(struct intel_display *display, u32 bits); 35 36 void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask); 37 void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask); 38 39 int i8xx_enable_vblank(struct drm_crtc *crtc); 40 int i915gm_enable_vblank(struct drm_crtc *crtc); 41 int i965_enable_vblank(struct drm_crtc *crtc); 42 int ilk_enable_vblank(struct drm_crtc *crtc); 43 int bdw_enable_vblank(struct drm_crtc *crtc); 44 void i8xx_disable_vblank(struct drm_crtc *crtc); 45 void i915gm_disable_vblank(struct drm_crtc *crtc); 46 void i965_disable_vblank(struct drm_crtc *crtc); 47 void ilk_disable_vblank(struct drm_crtc *crtc); 48 void bdw_disable_vblank(struct drm_crtc *crtc); 49 50 void ivb_display_irq_handler(struct intel_display *display, u32 de_iir); 51 void ilk_display_irq_handler(struct intel_display *display, u32 de_iir); 52 void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl); 53 void gen11_display_irq_handler(struct intel_display *display); 54 55 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl); 56 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir); 57 58 void i9xx_display_irq_reset(struct intel_display *display); 59 void ibx_display_irq_reset(struct intel_display *display); 60 void vlv_display_irq_reset(struct intel_display *display); 61 void gen8_display_irq_reset(struct intel_display *display); 62 void gen11_display_irq_reset(struct intel_display *display); 63 64 void i915_display_irq_postinstall(struct intel_display *display); 65 void i965_display_irq_postinstall(struct intel_display *display); 66 void vlv_display_irq_postinstall(struct intel_display *display); 67 void ilk_de_irq_postinstall(struct intel_display *display); 68 void gen8_de_irq_postinstall(struct intel_display *display); 69 void gen11_de_irq_postinstall(struct intel_display *display); 70 void dg1_de_irq_postinstall(struct intel_display *display); 71 72 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); 73 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); 74 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); 75 76 void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 77 78 void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 79 void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 80 void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]); 81 82 void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); 83 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt); 84 85 void intel_display_irq_init(struct intel_display *display); 86 87 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable); 88 89 struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display); 90 void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, struct drm_printer *p); 91 92 #endif /* __INTEL_DISPLAY_IRQ_H__ */ 93