1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_IRQ_H__ 7 #define __INTEL_DISPLAY_IRQ_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 13 enum pipe; 14 struct drm_crtc; 15 struct drm_printer; 16 struct intel_display; 17 struct intel_display_irq_snapshot; 18 19 u32 xelpdp_pica_aux_mask(struct intel_display *display); 20 21 void valleyview_enable_display_irqs(struct intel_display *display); 22 void valleyview_disable_display_irqs(struct intel_display *display); 23 24 void ilk_update_display_irq(struct intel_display *display, 25 u32 interrupt_mask, u32 enabled_irq_mask); 26 void ilk_enable_display_irq(struct intel_display *display, u32 bits); 27 void ilk_disable_display_irq(struct intel_display *display, u32 bits); 28 29 void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask); 30 void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); 31 void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); 32 33 void ibx_display_interrupt_update(struct intel_display *display, 34 u32 interrupt_mask, u32 enabled_irq_mask); 35 void ibx_enable_display_interrupt(struct intel_display *display, u32 bits); 36 void ibx_disable_display_interrupt(struct intel_display *display, u32 bits); 37 38 void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask); 39 void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask); 40 41 int i8xx_enable_vblank(struct drm_crtc *crtc); 42 int i915gm_enable_vblank(struct drm_crtc *crtc); 43 int i965_enable_vblank(struct drm_crtc *crtc); 44 int ilk_enable_vblank(struct drm_crtc *crtc); 45 int bdw_enable_vblank(struct drm_crtc *crtc); 46 void i8xx_disable_vblank(struct drm_crtc *crtc); 47 void i915gm_disable_vblank(struct drm_crtc *crtc); 48 void i965_disable_vblank(struct drm_crtc *crtc); 49 void ilk_disable_vblank(struct drm_crtc *crtc); 50 void bdw_disable_vblank(struct drm_crtc *crtc); 51 52 void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier); 53 void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier); 54 bool ilk_display_irq_handler(struct intel_display *display); 55 void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl); 56 void gen11_display_irq_handler(struct intel_display *display); 57 58 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl); 59 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir); 60 61 void i9xx_display_irq_reset(struct intel_display *display); 62 void ilk_display_irq_reset(struct intel_display *display); 63 void vlv_display_irq_reset(struct intel_display *display); 64 void gen8_display_irq_reset(struct intel_display *display); 65 void gen11_display_irq_reset(struct intel_display *display); 66 67 u32 i9xx_display_irq_enable_mask(struct intel_display *display); 68 void i915_display_irq_postinstall(struct intel_display *display); 69 void i965_display_irq_postinstall(struct intel_display *display); 70 void vlv_display_irq_postinstall(struct intel_display *display); 71 void ilk_de_irq_postinstall(struct intel_display *display); 72 void gen8_de_irq_postinstall(struct intel_display *display); 73 void gen11_de_irq_postinstall(struct intel_display *display); 74 void dg1_de_irq_postinstall(struct intel_display *display); 75 76 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); 77 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); 78 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); 79 80 void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 81 82 void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 83 void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 84 void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]); 85 86 void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); 87 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt); 88 89 void intel_display_irq_init(struct intel_display *display); 90 91 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable); 92 93 struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display); 94 void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, struct drm_printer *p); 95 96 #endif /* __INTEL_DISPLAY_IRQ_H__ */ 97