1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 #include <drm/drm_vblank.h> 8 9 #include "i915_drv.h" 10 #include "i915_irq.h" 11 #include "i915_reg.h" 12 #include "icl_dsi_regs.h" 13 #include "intel_crtc.h" 14 #include "intel_de.h" 15 #include "intel_display_irq.h" 16 #include "intel_display_regs.h" 17 #include "intel_display_rpm.h" 18 #include "intel_display_rps.h" 19 #include "intel_display_trace.h" 20 #include "intel_display_types.h" 21 #include "intel_dmc.h" 22 #include "intel_dmc_wl.h" 23 #include "intel_dp_aux.h" 24 #include "intel_dsb.h" 25 #include "intel_fdi_regs.h" 26 #include "intel_fifo_underrun.h" 27 #include "intel_gmbus.h" 28 #include "intel_hotplug_irq.h" 29 #include "intel_pipe_crc_regs.h" 30 #include "intel_plane.h" 31 #include "intel_pmdemand.h" 32 #include "intel_psr.h" 33 #include "intel_psr_regs.h" 34 #include "intel_uncore.h" 35 36 static void 37 intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, 38 u32 imr_val, u32 ier_val) 39 { 40 intel_dmc_wl_get(display, regs.imr); 41 intel_dmc_wl_get(display, regs.ier); 42 intel_dmc_wl_get(display, regs.iir); 43 44 gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); 45 46 intel_dmc_wl_put(display, regs.iir); 47 intel_dmc_wl_put(display, regs.ier); 48 intel_dmc_wl_put(display, regs.imr); 49 } 50 51 static void 52 intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) 53 { 54 intel_dmc_wl_get(display, regs.imr); 55 intel_dmc_wl_get(display, regs.ier); 56 intel_dmc_wl_get(display, regs.iir); 57 58 gen2_irq_reset(to_intel_uncore(display->drm), regs); 59 60 intel_dmc_wl_put(display, regs.iir); 61 intel_dmc_wl_put(display, regs.ier); 62 intel_dmc_wl_put(display, regs.imr); 63 } 64 65 static void 66 intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg) 67 { 68 intel_dmc_wl_get(display, reg); 69 70 gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg); 71 72 intel_dmc_wl_put(display, reg); 73 } 74 75 struct pipe_fault_handler { 76 bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id); 77 u32 fault; 78 enum plane_id plane_id; 79 }; 80 81 static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) 82 { 83 struct intel_display *display = to_intel_display(crtc); 84 struct intel_plane_error error = {}; 85 struct intel_plane *plane; 86 87 plane = intel_crtc_get_plane(crtc, plane_id); 88 if (!plane || !plane->capture_error) 89 return false; 90 91 plane->capture_error(crtc, plane, &error); 92 93 drm_err_ratelimited(display->drm, 94 "[CRTC:%d:%s][PLANE:%d:%s] fault (CTL=0x%x, SURF=0x%x, SURFLIVE=0x%x)\n", 95 crtc->base.base.id, crtc->base.name, 96 plane->base.base.id, plane->base.name, 97 error.ctl, error.surf, error.surflive); 98 99 return true; 100 } 101 102 static void intel_pipe_fault_irq_handler(struct intel_display *display, 103 const struct pipe_fault_handler *handlers, 104 enum pipe pipe, u32 fault_errors) 105 { 106 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 107 const struct pipe_fault_handler *handler; 108 109 for (handler = handlers; handler && handler->fault; handler++) { 110 if ((fault_errors & handler->fault) == 0) 111 continue; 112 113 if (handler->handle(crtc, handler->plane_id)) 114 fault_errors &= ~handler->fault; 115 } 116 117 WARN_ONCE(fault_errors, "[CRTC:%d:%s] unreported faults 0x%x\n", 118 crtc->base.base.id, crtc->base.name, fault_errors); 119 } 120 121 static void 122 intel_handle_vblank(struct intel_display *display, enum pipe pipe) 123 { 124 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 125 126 drm_crtc_handle_vblank(&crtc->base); 127 } 128 129 /** 130 * ilk_update_display_irq - update DEIMR 131 * @display: display device 132 * @interrupt_mask: mask of interrupt bits to update 133 * @enabled_irq_mask: mask of interrupt bits to enable 134 */ 135 void ilk_update_display_irq(struct intel_display *display, 136 u32 interrupt_mask, u32 enabled_irq_mask) 137 { 138 struct drm_i915_private *dev_priv = to_i915(display->drm); 139 u32 new_val; 140 141 lockdep_assert_held(&display->irq.lock); 142 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 143 144 new_val = dev_priv->irq_mask; 145 new_val &= ~interrupt_mask; 146 new_val |= (~enabled_irq_mask & interrupt_mask); 147 148 if (new_val != dev_priv->irq_mask && 149 !drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) { 150 dev_priv->irq_mask = new_val; 151 intel_de_write(display, DEIMR, dev_priv->irq_mask); 152 intel_de_posting_read(display, DEIMR); 153 } 154 } 155 156 void ilk_enable_display_irq(struct intel_display *display, u32 bits) 157 { 158 ilk_update_display_irq(display, bits, bits); 159 } 160 161 void ilk_disable_display_irq(struct intel_display *display, u32 bits) 162 { 163 ilk_update_display_irq(display, bits, 0); 164 } 165 166 /** 167 * bdw_update_port_irq - update DE port interrupt 168 * @display: display device 169 * @interrupt_mask: mask of interrupt bits to update 170 * @enabled_irq_mask: mask of interrupt bits to enable 171 */ 172 void bdw_update_port_irq(struct intel_display *display, 173 u32 interrupt_mask, u32 enabled_irq_mask) 174 { 175 struct drm_i915_private *dev_priv = to_i915(display->drm); 176 u32 new_val; 177 u32 old_val; 178 179 lockdep_assert_held(&display->irq.lock); 180 181 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 182 183 if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) 184 return; 185 186 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); 187 188 new_val = old_val; 189 new_val &= ~interrupt_mask; 190 new_val |= (~enabled_irq_mask & interrupt_mask); 191 192 if (new_val != old_val) { 193 intel_de_write(display, GEN8_DE_PORT_IMR, new_val); 194 intel_de_posting_read(display, GEN8_DE_PORT_IMR); 195 } 196 } 197 198 /** 199 * bdw_update_pipe_irq - update DE pipe interrupt 200 * @display: display device 201 * @pipe: pipe whose interrupt to update 202 * @interrupt_mask: mask of interrupt bits to update 203 * @enabled_irq_mask: mask of interrupt bits to enable 204 */ 205 static void bdw_update_pipe_irq(struct intel_display *display, 206 enum pipe pipe, u32 interrupt_mask, 207 u32 enabled_irq_mask) 208 { 209 struct drm_i915_private *dev_priv = to_i915(display->drm); 210 u32 new_val; 211 212 lockdep_assert_held(&display->irq.lock); 213 214 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 215 216 if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) 217 return; 218 219 new_val = display->irq.de_irq_mask[pipe]; 220 new_val &= ~interrupt_mask; 221 new_val |= (~enabled_irq_mask & interrupt_mask); 222 223 if (new_val != display->irq.de_irq_mask[pipe]) { 224 display->irq.de_irq_mask[pipe] = new_val; 225 intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]); 226 intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); 227 } 228 } 229 230 void bdw_enable_pipe_irq(struct intel_display *display, 231 enum pipe pipe, u32 bits) 232 { 233 bdw_update_pipe_irq(display, pipe, bits, bits); 234 } 235 236 void bdw_disable_pipe_irq(struct intel_display *display, 237 enum pipe pipe, u32 bits) 238 { 239 bdw_update_pipe_irq(display, pipe, bits, 0); 240 } 241 242 /** 243 * ibx_display_interrupt_update - update SDEIMR 244 * @display: display device 245 * @interrupt_mask: mask of interrupt bits to update 246 * @enabled_irq_mask: mask of interrupt bits to enable 247 */ 248 void ibx_display_interrupt_update(struct intel_display *display, 249 u32 interrupt_mask, 250 u32 enabled_irq_mask) 251 { 252 struct drm_i915_private *dev_priv = to_i915(display->drm); 253 u32 sdeimr = intel_de_read(display, SDEIMR); 254 255 sdeimr &= ~interrupt_mask; 256 sdeimr |= (~enabled_irq_mask & interrupt_mask); 257 258 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 259 260 lockdep_assert_held(&display->irq.lock); 261 262 if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) 263 return; 264 265 intel_de_write(display, SDEIMR, sdeimr); 266 intel_de_posting_read(display, SDEIMR); 267 } 268 269 void ibx_enable_display_interrupt(struct intel_display *display, u32 bits) 270 { 271 ibx_display_interrupt_update(display, bits, bits); 272 } 273 274 void ibx_disable_display_interrupt(struct intel_display *display, u32 bits) 275 { 276 ibx_display_interrupt_update(display, bits, 0); 277 } 278 279 u32 i915_pipestat_enable_mask(struct intel_display *display, 280 enum pipe pipe) 281 { 282 u32 status_mask = display->irq.pipestat_irq_mask[pipe]; 283 u32 enable_mask = status_mask << 16; 284 285 lockdep_assert_held(&display->irq.lock); 286 287 if (DISPLAY_VER(display) < 5) 288 goto out; 289 290 /* 291 * On pipe A we don't support the PSR interrupt yet, 292 * on pipe B and C the same bit MBZ. 293 */ 294 if (drm_WARN_ON_ONCE(display->drm, 295 status_mask & PIPE_A_PSR_STATUS_VLV)) 296 return 0; 297 /* 298 * On pipe B and C we don't support the PSR interrupt yet, on pipe 299 * A the same bit is for perf counters which we don't use either. 300 */ 301 if (drm_WARN_ON_ONCE(display->drm, 302 status_mask & PIPE_B_PSR_STATUS_VLV)) 303 return 0; 304 305 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 306 SPRITE0_FLIP_DONE_INT_EN_VLV | 307 SPRITE1_FLIP_DONE_INT_EN_VLV); 308 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 309 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 310 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 311 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 312 313 out: 314 drm_WARN_ONCE(display->drm, 315 enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 316 status_mask & ~PIPESTAT_INT_STATUS_MASK, 317 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 318 pipe_name(pipe), enable_mask, status_mask); 319 320 return enable_mask; 321 } 322 323 void i915_enable_pipestat(struct intel_display *display, 324 enum pipe pipe, u32 status_mask) 325 { 326 struct drm_i915_private *dev_priv = to_i915(display->drm); 327 i915_reg_t reg = PIPESTAT(display, pipe); 328 u32 enable_mask; 329 330 drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 331 "pipe %c: status_mask=0x%x\n", 332 pipe_name(pipe), status_mask); 333 334 lockdep_assert_held(&display->irq.lock); 335 drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); 336 337 if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) 338 return; 339 340 display->irq.pipestat_irq_mask[pipe] |= status_mask; 341 enable_mask = i915_pipestat_enable_mask(display, pipe); 342 343 intel_de_write(display, reg, enable_mask | status_mask); 344 intel_de_posting_read(display, reg); 345 } 346 347 void i915_disable_pipestat(struct intel_display *display, 348 enum pipe pipe, u32 status_mask) 349 { 350 struct drm_i915_private *dev_priv = to_i915(display->drm); 351 i915_reg_t reg = PIPESTAT(display, pipe); 352 u32 enable_mask; 353 354 drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 355 "pipe %c: status_mask=0x%x\n", 356 pipe_name(pipe), status_mask); 357 358 lockdep_assert_held(&display->irq.lock); 359 drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); 360 361 if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0) 362 return; 363 364 display->irq.pipestat_irq_mask[pipe] &= ~status_mask; 365 enable_mask = i915_pipestat_enable_mask(display, pipe); 366 367 intel_de_write(display, reg, enable_mask | status_mask); 368 intel_de_posting_read(display, reg); 369 } 370 371 static bool i915_has_legacy_blc_interrupt(struct intel_display *display) 372 { 373 if (display->platform.i85x) 374 return true; 375 376 if (display->platform.pineview) 377 return true; 378 379 return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile; 380 } 381 382 /* enable ASLE pipestat for OpRegion */ 383 static void i915_enable_asle_pipestat(struct intel_display *display) 384 { 385 if (!intel_opregion_asle_present(display)) 386 return; 387 388 if (!i915_has_legacy_blc_interrupt(display)) 389 return; 390 391 spin_lock_irq(&display->irq.lock); 392 393 i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 394 if (DISPLAY_VER(display) >= 4) 395 i915_enable_pipestat(display, PIPE_A, 396 PIPE_LEGACY_BLC_EVENT_STATUS); 397 398 spin_unlock_irq(&display->irq.lock); 399 } 400 401 #if IS_ENABLED(CONFIG_DEBUG_FS) 402 static void display_pipe_crc_irq_handler(struct intel_display *display, 403 enum pipe pipe, 404 u32 crc0, u32 crc1, 405 u32 crc2, u32 crc3, 406 u32 crc4) 407 { 408 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 409 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 410 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 411 412 trace_intel_pipe_crc(crtc, crcs); 413 414 spin_lock(&pipe_crc->lock); 415 /* 416 * For some not yet identified reason, the first CRC is 417 * bonkers. So let's just wait for the next vblank and read 418 * out the buggy result. 419 * 420 * On GEN8+ sometimes the second CRC is bonkers as well, so 421 * don't trust that one either. 422 */ 423 if (pipe_crc->skipped <= 0 || 424 (DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) { 425 pipe_crc->skipped++; 426 spin_unlock(&pipe_crc->lock); 427 return; 428 } 429 spin_unlock(&pipe_crc->lock); 430 431 drm_crtc_add_crc_entry(&crtc->base, true, 432 drm_crtc_accurate_vblank_count(&crtc->base), 433 crcs); 434 } 435 #else 436 static inline void 437 display_pipe_crc_irq_handler(struct intel_display *display, 438 enum pipe pipe, 439 u32 crc0, u32 crc1, 440 u32 crc2, u32 crc3, 441 u32 crc4) {} 442 #endif 443 444 static void flip_done_handler(struct intel_display *display, 445 enum pipe pipe) 446 { 447 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 448 449 spin_lock(&display->drm->event_lock); 450 451 if (crtc->flip_done_event) { 452 trace_intel_crtc_flip_done(crtc); 453 drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event); 454 crtc->flip_done_event = NULL; 455 } 456 457 spin_unlock(&display->drm->event_lock); 458 } 459 460 static void hsw_pipe_crc_irq_handler(struct intel_display *display, 461 enum pipe pipe) 462 { 463 display_pipe_crc_irq_handler(display, pipe, 464 intel_de_read(display, PIPE_CRC_RES_HSW(pipe)), 465 0, 0, 0, 0); 466 } 467 468 static void ivb_pipe_crc_irq_handler(struct intel_display *display, 469 enum pipe pipe) 470 { 471 display_pipe_crc_irq_handler(display, pipe, 472 intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)), 473 intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)), 474 intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)), 475 intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)), 476 intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe))); 477 } 478 479 static void i9xx_pipe_crc_irq_handler(struct intel_display *display, 480 enum pipe pipe) 481 { 482 u32 res1, res2; 483 484 if (DISPLAY_VER(display) >= 3) 485 res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe)); 486 else 487 res1 = 0; 488 489 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 490 res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe)); 491 else 492 res2 = 0; 493 494 display_pipe_crc_irq_handler(display, pipe, 495 intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)), 496 intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)), 497 intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)), 498 res1, res2); 499 } 500 501 static void i9xx_pipestat_irq_reset(struct intel_display *display) 502 { 503 enum pipe pipe; 504 505 for_each_pipe(display, pipe) { 506 intel_de_write(display, 507 PIPESTAT(display, pipe), 508 PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS); 509 510 display->irq.pipestat_irq_mask[pipe] = 0; 511 } 512 } 513 514 void i9xx_pipestat_irq_ack(struct intel_display *display, 515 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 516 { 517 enum pipe pipe; 518 519 spin_lock(&display->irq.lock); 520 521 if ((display->platform.valleyview || display->platform.cherryview) && 522 !display->irq.vlv_display_irqs_enabled) { 523 spin_unlock(&display->irq.lock); 524 return; 525 } 526 527 for_each_pipe(display, pipe) { 528 i915_reg_t reg; 529 u32 status_mask, enable_mask, iir_bit = 0; 530 531 /* 532 * PIPESTAT bits get signalled even when the interrupt is 533 * disabled with the mask bits, and some of the status bits do 534 * not generate interrupts at all (like the underrun bit). Hence 535 * we need to be careful that we only handle what we want to 536 * handle. 537 */ 538 539 /* fifo underruns are filterered in the underrun handler. */ 540 status_mask = PIPE_FIFO_UNDERRUN_STATUS; 541 542 switch (pipe) { 543 default: 544 case PIPE_A: 545 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 546 break; 547 case PIPE_B: 548 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 549 break; 550 case PIPE_C: 551 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 552 break; 553 } 554 if (iir & iir_bit) 555 status_mask |= display->irq.pipestat_irq_mask[pipe]; 556 557 if (!status_mask) 558 continue; 559 560 reg = PIPESTAT(display, pipe); 561 pipe_stats[pipe] = intel_de_read(display, reg) & status_mask; 562 enable_mask = i915_pipestat_enable_mask(display, pipe); 563 564 /* 565 * Clear the PIPE*STAT regs before the IIR 566 * 567 * Toggle the enable bits to make sure we get an 568 * edge in the ISR pipe event bit if we don't clear 569 * all the enabled status bits. Otherwise the edge 570 * triggered IIR on i965/g4x wouldn't notice that 571 * an interrupt is still pending. 572 */ 573 if (pipe_stats[pipe]) { 574 intel_de_write(display, reg, pipe_stats[pipe]); 575 intel_de_write(display, reg, enable_mask); 576 } 577 } 578 spin_unlock(&display->irq.lock); 579 } 580 581 void i915_pipestat_irq_handler(struct intel_display *display, 582 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 583 { 584 bool blc_event = false; 585 enum pipe pipe; 586 587 for_each_pipe(display, pipe) { 588 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 589 intel_handle_vblank(display, pipe); 590 591 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 592 blc_event = true; 593 594 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 595 i9xx_pipe_crc_irq_handler(display, pipe); 596 597 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 598 intel_cpu_fifo_underrun_irq_handler(display, pipe); 599 } 600 601 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 602 intel_opregion_asle_intr(display); 603 } 604 605 void i965_pipestat_irq_handler(struct intel_display *display, 606 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 607 { 608 bool blc_event = false; 609 enum pipe pipe; 610 611 for_each_pipe(display, pipe) { 612 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 613 intel_handle_vblank(display, pipe); 614 615 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 616 blc_event = true; 617 618 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 619 i9xx_pipe_crc_irq_handler(display, pipe); 620 621 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 622 intel_cpu_fifo_underrun_irq_handler(display, pipe); 623 } 624 625 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 626 intel_opregion_asle_intr(display); 627 628 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 629 intel_gmbus_irq_handler(display); 630 } 631 632 void valleyview_pipestat_irq_handler(struct intel_display *display, 633 u32 pipe_stats[I915_MAX_PIPES]) 634 { 635 enum pipe pipe; 636 637 for_each_pipe(display, pipe) { 638 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 639 intel_handle_vblank(display, pipe); 640 641 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) 642 flip_done_handler(display, pipe); 643 644 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 645 i9xx_pipe_crc_irq_handler(display, pipe); 646 647 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 648 intel_cpu_fifo_underrun_irq_handler(display, pipe); 649 } 650 651 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 652 intel_gmbus_irq_handler(display); 653 } 654 655 static void ibx_irq_handler(struct intel_display *display, u32 pch_iir) 656 { 657 enum pipe pipe; 658 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 659 660 ibx_hpd_irq_handler(display, hotplug_trigger); 661 662 if (pch_iir & SDE_AUDIO_POWER_MASK) { 663 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 664 SDE_AUDIO_POWER_SHIFT); 665 drm_dbg(display->drm, "PCH audio power change on port %d\n", 666 port_name(port)); 667 } 668 669 if (pch_iir & SDE_AUX_MASK) 670 intel_dp_aux_irq_handler(display); 671 672 if (pch_iir & SDE_GMBUS) 673 intel_gmbus_irq_handler(display); 674 675 if (pch_iir & SDE_AUDIO_HDCP_MASK) 676 drm_dbg(display->drm, "PCH HDCP audio interrupt\n"); 677 678 if (pch_iir & SDE_AUDIO_TRANS_MASK) 679 drm_dbg(display->drm, "PCH transcoder audio interrupt\n"); 680 681 if (pch_iir & SDE_POISON) 682 drm_err(display->drm, "PCH poison interrupt\n"); 683 684 if (pch_iir & SDE_FDI_MASK) { 685 for_each_pipe(display, pipe) 686 drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n", 687 pipe_name(pipe), 688 intel_de_read(display, FDI_RX_IIR(pipe))); 689 } 690 691 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 692 drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n"); 693 694 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 695 drm_dbg(display->drm, 696 "PCH transcoder CRC error interrupt\n"); 697 698 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 699 intel_pch_fifo_underrun_irq_handler(display, PIPE_A); 700 701 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 702 intel_pch_fifo_underrun_irq_handler(display, PIPE_B); 703 } 704 705 static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe) 706 { 707 switch (pipe) { 708 case PIPE_A: 709 return ERR_INT_SPRITE_A_FAULT | 710 ERR_INT_PRIMARY_A_FAULT | 711 ERR_INT_CURSOR_A_FAULT; 712 case PIPE_B: 713 return ERR_INT_SPRITE_B_FAULT | 714 ERR_INT_PRIMARY_B_FAULT | 715 ERR_INT_CURSOR_B_FAULT; 716 case PIPE_C: 717 return ERR_INT_SPRITE_C_FAULT | 718 ERR_INT_PRIMARY_C_FAULT | 719 ERR_INT_CURSOR_C_FAULT; 720 default: 721 return 0; 722 } 723 } 724 725 static const struct pipe_fault_handler ivb_pipe_fault_handlers[] = { 726 { .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 727 { .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 728 { .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 729 { .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 730 { .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 731 { .fault = ERR_INT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 732 { .fault = ERR_INT_SPRITE_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 733 { .fault = ERR_INT_PRIMARY_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 734 { .fault = ERR_INT_CURSOR_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 735 {} 736 }; 737 738 static void ivb_err_int_handler(struct intel_display *display) 739 { 740 u32 err_int = intel_de_read(display, GEN7_ERR_INT); 741 enum pipe pipe; 742 743 if (err_int & ERR_INT_POISON) 744 drm_err(display->drm, "Poison interrupt\n"); 745 746 if (err_int & ERR_INT_INVALID_GTT_PTE) 747 drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); 748 749 if (err_int & ERR_INT_INVALID_PTE_DATA) 750 drm_err_ratelimited(display->drm, "Invalid PTE data\n"); 751 752 for_each_pipe(display, pipe) { 753 u32 fault_errors; 754 755 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 756 intel_cpu_fifo_underrun_irq_handler(display, pipe); 757 758 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 759 if (display->platform.ivybridge) 760 ivb_pipe_crc_irq_handler(display, pipe); 761 else 762 hsw_pipe_crc_irq_handler(display, pipe); 763 } 764 765 fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe); 766 if (fault_errors) 767 intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers, 768 pipe, fault_errors); 769 } 770 771 intel_de_write(display, GEN7_ERR_INT, err_int); 772 } 773 774 static void cpt_serr_int_handler(struct intel_display *display) 775 { 776 u32 serr_int = intel_de_read(display, SERR_INT); 777 enum pipe pipe; 778 779 if (serr_int & SERR_INT_POISON) 780 drm_err(display->drm, "PCH poison interrupt\n"); 781 782 for_each_pipe(display, pipe) 783 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 784 intel_pch_fifo_underrun_irq_handler(display, pipe); 785 786 intel_de_write(display, SERR_INT, serr_int); 787 } 788 789 static void cpt_irq_handler(struct intel_display *display, u32 pch_iir) 790 { 791 enum pipe pipe; 792 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 793 794 ibx_hpd_irq_handler(display, hotplug_trigger); 795 796 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 797 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 798 SDE_AUDIO_POWER_SHIFT_CPT); 799 drm_dbg(display->drm, "PCH audio power change on port %c\n", 800 port_name(port)); 801 } 802 803 if (pch_iir & SDE_AUX_MASK_CPT) 804 intel_dp_aux_irq_handler(display); 805 806 if (pch_iir & SDE_GMBUS_CPT) 807 intel_gmbus_irq_handler(display); 808 809 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 810 drm_dbg(display->drm, "Audio CP request interrupt\n"); 811 812 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 813 drm_dbg(display->drm, "Audio CP change interrupt\n"); 814 815 if (pch_iir & SDE_FDI_MASK_CPT) { 816 for_each_pipe(display, pipe) 817 drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n", 818 pipe_name(pipe), 819 intel_de_read(display, FDI_RX_IIR(pipe))); 820 } 821 822 if (pch_iir & SDE_ERROR_CPT) 823 cpt_serr_int_handler(display); 824 } 825 826 static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe) 827 { 828 switch (pipe) { 829 case PIPE_A: 830 return GTT_FAULT_SPRITE_A_FAULT | 831 GTT_FAULT_PRIMARY_A_FAULT | 832 GTT_FAULT_CURSOR_A_FAULT; 833 case PIPE_B: 834 return GTT_FAULT_SPRITE_B_FAULT | 835 GTT_FAULT_PRIMARY_B_FAULT | 836 GTT_FAULT_CURSOR_B_FAULT; 837 default: 838 return 0; 839 } 840 } 841 842 static const struct pipe_fault_handler ilk_pipe_fault_handlers[] = { 843 { .fault = GTT_FAULT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 844 { .fault = GTT_FAULT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 845 { .fault = GTT_FAULT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 846 { .fault = GTT_FAULT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 847 { .fault = GTT_FAULT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 848 { .fault = GTT_FAULT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 849 {} 850 }; 851 852 static void ilk_gtt_fault_irq_handler(struct intel_display *display) 853 { 854 enum pipe pipe; 855 u32 gtt_fault; 856 857 gtt_fault = intel_de_read(display, ILK_GTT_FAULT); 858 intel_de_write(display, ILK_GTT_FAULT, gtt_fault); 859 860 if (gtt_fault & GTT_FAULT_INVALID_GTT_PTE) 861 drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); 862 863 if (gtt_fault & GTT_FAULT_INVALID_PTE_DATA) 864 drm_err_ratelimited(display->drm, "Invalid PTE data\n"); 865 866 for_each_pipe(display, pipe) { 867 u32 fault_errors; 868 869 fault_errors = gtt_fault & ilk_gtt_fault_pipe_fault_mask(pipe); 870 if (fault_errors) 871 intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers, 872 pipe, fault_errors); 873 } 874 } 875 876 void ilk_display_irq_handler(struct intel_display *display, u32 de_iir) 877 { 878 enum pipe pipe; 879 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 880 881 if (hotplug_trigger) 882 ilk_hpd_irq_handler(display, hotplug_trigger); 883 884 if (de_iir & DE_AUX_CHANNEL_A) 885 intel_dp_aux_irq_handler(display); 886 887 if (de_iir & DE_GSE) 888 intel_opregion_asle_intr(display); 889 890 if (de_iir & DE_POISON) 891 drm_err(display->drm, "Poison interrupt\n"); 892 893 if (de_iir & DE_GTT_FAULT) 894 ilk_gtt_fault_irq_handler(display); 895 896 for_each_pipe(display, pipe) { 897 if (de_iir & DE_PIPE_VBLANK(pipe)) 898 intel_handle_vblank(display, pipe); 899 900 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) 901 flip_done_handler(display, pipe); 902 903 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 904 intel_cpu_fifo_underrun_irq_handler(display, pipe); 905 906 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 907 i9xx_pipe_crc_irq_handler(display, pipe); 908 } 909 910 /* check event from PCH */ 911 if (de_iir & DE_PCH_EVENT) { 912 u32 pch_iir = intel_de_read(display, SDEIIR); 913 914 if (HAS_PCH_CPT(display)) 915 cpt_irq_handler(display, pch_iir); 916 else 917 ibx_irq_handler(display, pch_iir); 918 919 /* should clear PCH hotplug event before clear CPU irq */ 920 intel_de_write(display, SDEIIR, pch_iir); 921 } 922 923 if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT) 924 ilk_display_rps_irq_handler(display); 925 } 926 927 void ivb_display_irq_handler(struct intel_display *display, u32 de_iir) 928 { 929 enum pipe pipe; 930 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 931 932 if (hotplug_trigger) 933 ilk_hpd_irq_handler(display, hotplug_trigger); 934 935 if (de_iir & DE_ERR_INT_IVB) 936 ivb_err_int_handler(display); 937 938 if (de_iir & DE_EDP_PSR_INT_HSW) { 939 struct intel_encoder *encoder; 940 941 for_each_intel_encoder_with_psr(display->drm, encoder) { 942 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 943 u32 psr_iir; 944 945 psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0); 946 intel_psr_irq_handler(intel_dp, psr_iir); 947 break; 948 } 949 } 950 951 if (de_iir & DE_AUX_CHANNEL_A_IVB) 952 intel_dp_aux_irq_handler(display); 953 954 if (de_iir & DE_GSE_IVB) 955 intel_opregion_asle_intr(display); 956 957 for_each_pipe(display, pipe) { 958 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 959 intel_handle_vblank(display, pipe); 960 961 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) 962 flip_done_handler(display, pipe); 963 } 964 965 /* check event from PCH */ 966 if (!HAS_PCH_NOP(display) && (de_iir & DE_PCH_EVENT_IVB)) { 967 u32 pch_iir = intel_de_read(display, SDEIIR); 968 969 cpt_irq_handler(display, pch_iir); 970 971 /* clear PCH hotplug event before clear CPU irq */ 972 intel_de_write(display, SDEIIR, pch_iir); 973 } 974 } 975 976 static u32 gen8_de_port_aux_mask(struct intel_display *display) 977 { 978 u32 mask; 979 980 if (DISPLAY_VER(display) >= 20) 981 return 0; 982 else if (DISPLAY_VER(display) >= 14) 983 return TGL_DE_PORT_AUX_DDIA | 984 TGL_DE_PORT_AUX_DDIB; 985 else if (DISPLAY_VER(display) >= 13) 986 return TGL_DE_PORT_AUX_DDIA | 987 TGL_DE_PORT_AUX_DDIB | 988 TGL_DE_PORT_AUX_DDIC | 989 XELPD_DE_PORT_AUX_DDID | 990 XELPD_DE_PORT_AUX_DDIE | 991 TGL_DE_PORT_AUX_USBC1 | 992 TGL_DE_PORT_AUX_USBC2 | 993 TGL_DE_PORT_AUX_USBC3 | 994 TGL_DE_PORT_AUX_USBC4; 995 else if (DISPLAY_VER(display) >= 12) 996 return TGL_DE_PORT_AUX_DDIA | 997 TGL_DE_PORT_AUX_DDIB | 998 TGL_DE_PORT_AUX_DDIC | 999 TGL_DE_PORT_AUX_USBC1 | 1000 TGL_DE_PORT_AUX_USBC2 | 1001 TGL_DE_PORT_AUX_USBC3 | 1002 TGL_DE_PORT_AUX_USBC4 | 1003 TGL_DE_PORT_AUX_USBC5 | 1004 TGL_DE_PORT_AUX_USBC6; 1005 1006 mask = GEN8_AUX_CHANNEL_A; 1007 if (DISPLAY_VER(display) >= 9) 1008 mask |= GEN9_AUX_CHANNEL_B | 1009 GEN9_AUX_CHANNEL_C | 1010 GEN9_AUX_CHANNEL_D; 1011 1012 if (DISPLAY_VER(display) == 11) { 1013 mask |= ICL_AUX_CHANNEL_F; 1014 mask |= ICL_AUX_CHANNEL_E; 1015 } 1016 1017 return mask; 1018 } 1019 1020 static u32 gen8_de_pipe_fault_mask(struct intel_display *display) 1021 { 1022 if (DISPLAY_VER(display) >= 20) 1023 return MTL_PLANE_ATS_FAULT | 1024 GEN9_PIPE_CURSOR_FAULT | 1025 GEN11_PIPE_PLANE5_FAULT | 1026 GEN9_PIPE_PLANE4_FAULT | 1027 GEN9_PIPE_PLANE3_FAULT | 1028 GEN9_PIPE_PLANE2_FAULT | 1029 GEN9_PIPE_PLANE1_FAULT; 1030 else if (DISPLAY_VER(display) >= 14) 1031 return MTL_PIPEDMC_ATS_FAULT | 1032 MTL_PLANE_ATS_FAULT | 1033 GEN12_PIPEDMC_FAULT | 1034 GEN9_PIPE_CURSOR_FAULT | 1035 GEN11_PIPE_PLANE5_FAULT | 1036 GEN9_PIPE_PLANE4_FAULT | 1037 GEN9_PIPE_PLANE3_FAULT | 1038 GEN9_PIPE_PLANE2_FAULT | 1039 GEN9_PIPE_PLANE1_FAULT; 1040 else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 1041 return GEN12_PIPEDMC_FAULT | 1042 GEN9_PIPE_CURSOR_FAULT | 1043 GEN11_PIPE_PLANE5_FAULT | 1044 GEN9_PIPE_PLANE4_FAULT | 1045 GEN9_PIPE_PLANE3_FAULT | 1046 GEN9_PIPE_PLANE2_FAULT | 1047 GEN9_PIPE_PLANE1_FAULT; 1048 else if (DISPLAY_VER(display) == 12) 1049 return GEN12_PIPEDMC_FAULT | 1050 GEN9_PIPE_CURSOR_FAULT | 1051 GEN11_PIPE_PLANE7_FAULT | 1052 GEN11_PIPE_PLANE6_FAULT | 1053 GEN11_PIPE_PLANE5_FAULT | 1054 GEN9_PIPE_PLANE4_FAULT | 1055 GEN9_PIPE_PLANE3_FAULT | 1056 GEN9_PIPE_PLANE2_FAULT | 1057 GEN9_PIPE_PLANE1_FAULT; 1058 else if (DISPLAY_VER(display) == 11) 1059 return GEN9_PIPE_CURSOR_FAULT | 1060 GEN11_PIPE_PLANE7_FAULT | 1061 GEN11_PIPE_PLANE6_FAULT | 1062 GEN11_PIPE_PLANE5_FAULT | 1063 GEN9_PIPE_PLANE4_FAULT | 1064 GEN9_PIPE_PLANE3_FAULT | 1065 GEN9_PIPE_PLANE2_FAULT | 1066 GEN9_PIPE_PLANE1_FAULT; 1067 else if (DISPLAY_VER(display) >= 9) 1068 return GEN9_PIPE_CURSOR_FAULT | 1069 GEN9_PIPE_PLANE4_FAULT | 1070 GEN9_PIPE_PLANE3_FAULT | 1071 GEN9_PIPE_PLANE2_FAULT | 1072 GEN9_PIPE_PLANE1_FAULT; 1073 else 1074 return GEN8_PIPE_CURSOR_FAULT | 1075 GEN8_PIPE_SPRITE_FAULT | 1076 GEN8_PIPE_PRIMARY_FAULT; 1077 } 1078 1079 static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) 1080 { 1081 struct intel_display *display = to_intel_display(crtc); 1082 1083 drm_err_ratelimited(display->drm, 1084 "[CRTC:%d:%s] PLANE ATS fault\n", 1085 crtc->base.base.id, crtc->base.name); 1086 1087 return true; 1088 } 1089 1090 static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) 1091 { 1092 struct intel_display *display = to_intel_display(crtc); 1093 1094 drm_err_ratelimited(display->drm, 1095 "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1096 crtc->base.base.id, crtc->base.name); 1097 1098 return true; 1099 } 1100 1101 static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id) 1102 { 1103 struct intel_display *display = to_intel_display(crtc); 1104 1105 drm_err_ratelimited(display->drm, 1106 "[CRTC:%d:%s] PIPEDMC fault\n", 1107 crtc->base.base.id, crtc->base.name); 1108 1109 return true; 1110 } 1111 1112 static const struct pipe_fault_handler mtl_pipe_fault_handlers[] = { 1113 { .fault = MTL_PLANE_ATS_FAULT, .handle = handle_plane_ats_fault, }, 1114 { .fault = MTL_PIPEDMC_ATS_FAULT, .handle = handle_pipedmc_ats_fault, }, 1115 { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, 1116 { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, 1117 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1118 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1119 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1120 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1121 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1122 {} 1123 }; 1124 1125 static const struct pipe_fault_handler tgl_pipe_fault_handlers[] = { 1126 { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, 1127 { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, 1128 { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, 1129 { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, 1130 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1131 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1132 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1133 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1134 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1135 {} 1136 }; 1137 1138 static const struct pipe_fault_handler icl_pipe_fault_handlers[] = { 1139 { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, 1140 { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, 1141 { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, 1142 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1143 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1144 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1145 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1146 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1147 {} 1148 }; 1149 1150 static const struct pipe_fault_handler skl_pipe_fault_handlers[] = { 1151 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1152 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1153 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1154 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1155 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1156 {} 1157 }; 1158 1159 static const struct pipe_fault_handler bdw_pipe_fault_handlers[] = { 1160 { .fault = GEN8_PIPE_SPRITE_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1161 { .fault = GEN8_PIPE_PRIMARY_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1162 { .fault = GEN8_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1163 {} 1164 }; 1165 1166 static const struct pipe_fault_handler * 1167 gen8_pipe_fault_handlers(struct intel_display *display) 1168 { 1169 if (DISPLAY_VER(display) >= 14) 1170 return mtl_pipe_fault_handlers; 1171 else if (DISPLAY_VER(display) >= 12) 1172 return tgl_pipe_fault_handlers; 1173 else if (DISPLAY_VER(display) >= 11) 1174 return icl_pipe_fault_handlers; 1175 else if (DISPLAY_VER(display) >= 9) 1176 return skl_pipe_fault_handlers; 1177 else 1178 return bdw_pipe_fault_handlers; 1179 } 1180 1181 static void intel_pmdemand_irq_handler(struct intel_display *display) 1182 { 1183 wake_up_all(&display->pmdemand.waitqueue); 1184 } 1185 1186 static void 1187 gen8_de_misc_irq_handler(struct intel_display *display, u32 iir) 1188 { 1189 bool found = false; 1190 1191 if (HAS_DBUF_OVERLAP_DETECTION(display)) { 1192 if (iir & XE2LPD_DBUF_OVERLAP_DETECTED) { 1193 drm_warn(display->drm, "DBuf overlap detected\n"); 1194 found = true; 1195 } 1196 } 1197 1198 if (DISPLAY_VER(display) >= 14) { 1199 if (iir & (XELPDP_PMDEMAND_RSP | 1200 XELPDP_PMDEMAND_RSPTOUT_ERR)) { 1201 if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) 1202 drm_dbg(display->drm, 1203 "Error waiting for Punit PM Demand Response\n"); 1204 1205 intel_pmdemand_irq_handler(display); 1206 found = true; 1207 } 1208 1209 if (iir & XELPDP_RM_TIMEOUT) { 1210 u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE); 1211 drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val); 1212 found = true; 1213 } 1214 } else if (iir & GEN8_DE_MISC_GSE) { 1215 intel_opregion_asle_intr(display); 1216 found = true; 1217 } 1218 1219 if (iir & GEN8_DE_EDP_PSR) { 1220 struct intel_encoder *encoder; 1221 u32 psr_iir; 1222 i915_reg_t iir_reg; 1223 1224 for_each_intel_encoder_with_psr(display->drm, encoder) { 1225 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1226 1227 if (DISPLAY_VER(display) >= 12) 1228 iir_reg = TRANS_PSR_IIR(display, 1229 intel_dp->psr.transcoder); 1230 else 1231 iir_reg = EDP_PSR_IIR; 1232 1233 psr_iir = intel_de_rmw(display, iir_reg, 0, 0); 1234 1235 if (psr_iir) 1236 found = true; 1237 1238 intel_psr_irq_handler(intel_dp, psr_iir); 1239 1240 /* prior GEN12 only have one EDP PSR */ 1241 if (DISPLAY_VER(display) < 12) 1242 break; 1243 } 1244 } 1245 1246 if (!found) 1247 drm_err(display->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir); 1248 } 1249 1250 static void gen11_dsi_te_interrupt_handler(struct intel_display *display, 1251 u32 te_trigger) 1252 { 1253 enum pipe pipe = INVALID_PIPE; 1254 enum transcoder dsi_trans; 1255 enum port port; 1256 u32 val; 1257 1258 /* 1259 * Incase of dual link, TE comes from DSI_1 1260 * this is to check if dual link is enabled 1261 */ 1262 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0)); 1263 val &= PORT_SYNC_MODE_ENABLE; 1264 1265 /* 1266 * if dual link is enabled, then read DSI_0 1267 * transcoder registers 1268 */ 1269 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 1270 PORT_A : PORT_B; 1271 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 1272 1273 /* Check if DSI configured in command mode */ 1274 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1275 val = val & OP_MODE_MASK; 1276 1277 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 1278 drm_err(display->drm, "DSI trancoder not configured in command mode\n"); 1279 return; 1280 } 1281 1282 /* Get PIPE for handling VBLANK event */ 1283 val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1284 switch (val & TRANS_DDI_EDP_INPUT_MASK) { 1285 case TRANS_DDI_EDP_INPUT_A_ON: 1286 pipe = PIPE_A; 1287 break; 1288 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1289 pipe = PIPE_B; 1290 break; 1291 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1292 pipe = PIPE_C; 1293 break; 1294 default: 1295 drm_err(display->drm, "Invalid PIPE\n"); 1296 return; 1297 } 1298 1299 intel_handle_vblank(display, pipe); 1300 1301 /* clear TE in dsi IIR */ 1302 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 1303 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); 1304 } 1305 1306 static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display) 1307 { 1308 if (DISPLAY_VER(display) >= 9) 1309 return GEN9_PIPE_PLANE1_FLIP_DONE; 1310 else 1311 return GEN8_PIPE_PRIMARY_FLIP_DONE; 1312 } 1313 1314 static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir) 1315 { 1316 u32 pica_ier = 0; 1317 1318 *pica_iir = 0; 1319 *pch_iir = intel_de_read(display, SDEIIR); 1320 if (!*pch_iir) 1321 return; 1322 1323 /** 1324 * PICA IER must be disabled/re-enabled around clearing PICA IIR and 1325 * SDEIIR, to avoid losing PICA IRQs and to ensure that such IRQs set 1326 * their flags both in the PICA and SDE IIR. 1327 */ 1328 if (*pch_iir & SDE_PICAINTERRUPT) { 1329 drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL); 1330 1331 pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0); 1332 *pica_iir = intel_de_read(display, PICAINTERRUPT_IIR); 1333 intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir); 1334 } 1335 1336 intel_de_write(display, SDEIIR, *pch_iir); 1337 1338 if (pica_ier) 1339 intel_de_write(display, PICAINTERRUPT_IER, pica_ier); 1340 } 1341 1342 void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) 1343 { 1344 u32 iir; 1345 enum pipe pipe; 1346 1347 drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display)); 1348 1349 if (master_ctl & GEN8_DE_MISC_IRQ) { 1350 iir = intel_de_read(display, GEN8_DE_MISC_IIR); 1351 if (iir) { 1352 intel_de_write(display, GEN8_DE_MISC_IIR, iir); 1353 gen8_de_misc_irq_handler(display, iir); 1354 } else { 1355 drm_err_ratelimited(display->drm, 1356 "The master control interrupt lied (DE MISC)!\n"); 1357 } 1358 } 1359 1360 if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 1361 iir = intel_de_read(display, GEN11_DE_HPD_IIR); 1362 if (iir) { 1363 intel_de_write(display, GEN11_DE_HPD_IIR, iir); 1364 gen11_hpd_irq_handler(display, iir); 1365 } else { 1366 drm_err_ratelimited(display->drm, 1367 "The master control interrupt lied, (DE HPD)!\n"); 1368 } 1369 } 1370 1371 if (master_ctl & GEN8_DE_PORT_IRQ) { 1372 iir = intel_de_read(display, GEN8_DE_PORT_IIR); 1373 if (iir) { 1374 bool found = false; 1375 1376 intel_de_write(display, GEN8_DE_PORT_IIR, iir); 1377 1378 if (iir & gen8_de_port_aux_mask(display)) { 1379 intel_dp_aux_irq_handler(display); 1380 found = true; 1381 } 1382 1383 if (display->platform.geminilake || display->platform.broxton) { 1384 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 1385 1386 if (hotplug_trigger) { 1387 bxt_hpd_irq_handler(display, hotplug_trigger); 1388 found = true; 1389 } 1390 } else if (display->platform.broadwell) { 1391 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 1392 1393 if (hotplug_trigger) { 1394 ilk_hpd_irq_handler(display, hotplug_trigger); 1395 found = true; 1396 } 1397 } 1398 1399 if ((display->platform.geminilake || display->platform.broxton) && 1400 (iir & BXT_DE_PORT_GMBUS)) { 1401 intel_gmbus_irq_handler(display); 1402 found = true; 1403 } 1404 1405 if (DISPLAY_VER(display) >= 11) { 1406 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 1407 1408 if (te_trigger) { 1409 gen11_dsi_te_interrupt_handler(display, te_trigger); 1410 found = true; 1411 } 1412 } 1413 1414 if (!found) 1415 drm_err_ratelimited(display->drm, 1416 "Unexpected DE Port interrupt\n"); 1417 } else { 1418 drm_err_ratelimited(display->drm, 1419 "The master control interrupt lied (DE PORT)!\n"); 1420 } 1421 } 1422 1423 for_each_pipe(display, pipe) { 1424 u32 fault_errors; 1425 1426 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1427 continue; 1428 1429 iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe)); 1430 if (!iir) { 1431 drm_err_ratelimited(display->drm, 1432 "The master control interrupt lied (DE PIPE %c)!\n", 1433 pipe_name(pipe)); 1434 continue; 1435 } 1436 1437 intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir); 1438 1439 if (iir & GEN8_PIPE_VBLANK) 1440 intel_handle_vblank(display, pipe); 1441 1442 if (iir & gen8_de_pipe_flip_done_mask(display)) 1443 flip_done_handler(display, pipe); 1444 1445 if (HAS_DSB(display)) { 1446 if (iir & GEN12_DSB_INT(INTEL_DSB_0)) 1447 intel_dsb_irq_handler(display, pipe, INTEL_DSB_0); 1448 1449 if (iir & GEN12_DSB_INT(INTEL_DSB_1)) 1450 intel_dsb_irq_handler(display, pipe, INTEL_DSB_1); 1451 1452 if (iir & GEN12_DSB_INT(INTEL_DSB_2)) 1453 intel_dsb_irq_handler(display, pipe, INTEL_DSB_2); 1454 } 1455 1456 if (HAS_PIPEDMC(display) && iir & GEN12_PIPEDMC_INTERRUPT) 1457 intel_pipedmc_irq_handler(display, pipe); 1458 1459 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 1460 hsw_pipe_crc_irq_handler(display, pipe); 1461 1462 if (iir & GEN8_PIPE_FIFO_UNDERRUN) 1463 intel_cpu_fifo_underrun_irq_handler(display, pipe); 1464 1465 fault_errors = iir & gen8_de_pipe_fault_mask(display); 1466 if (fault_errors) 1467 intel_pipe_fault_irq_handler(display, 1468 gen8_pipe_fault_handlers(display), 1469 pipe, fault_errors); 1470 } 1471 1472 if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) && 1473 master_ctl & GEN8_DE_PCH_IRQ) { 1474 u32 pica_iir; 1475 1476 /* 1477 * FIXME(BDW): Assume for now that the new interrupt handling 1478 * scheme also closed the SDE interrupt handling race we've seen 1479 * on older pch-split platforms. But this needs testing. 1480 */ 1481 gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir); 1482 if (iir) { 1483 if (pica_iir) 1484 xelpdp_pica_irq_handler(display, pica_iir); 1485 1486 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 1487 icp_irq_handler(display, iir); 1488 else if (INTEL_PCH_TYPE(display) >= PCH_SPT) 1489 spt_irq_handler(display, iir); 1490 else 1491 cpt_irq_handler(display, iir); 1492 } else { 1493 /* 1494 * Like on previous PCH there seems to be something 1495 * fishy going on with forwarding PCH interrupts. 1496 */ 1497 drm_dbg(display->drm, 1498 "The master control interrupt lied (SDE)!\n"); 1499 } 1500 } 1501 } 1502 1503 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl) 1504 { 1505 u32 iir; 1506 1507 if (!(master_ctl & GEN11_GU_MISC_IRQ)) 1508 return 0; 1509 1510 intel_display_rpm_assert_block(display); 1511 1512 iir = intel_de_read(display, GEN11_GU_MISC_IIR); 1513 if (likely(iir)) 1514 intel_de_write(display, GEN11_GU_MISC_IIR, iir); 1515 1516 intel_display_rpm_assert_unblock(display); 1517 1518 return iir; 1519 } 1520 1521 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir) 1522 { 1523 if (iir & GEN11_GU_MISC_GSE) 1524 intel_opregion_asle_intr(display); 1525 } 1526 1527 void gen11_display_irq_handler(struct intel_display *display) 1528 { 1529 u32 disp_ctl; 1530 1531 intel_display_rpm_assert_block(display); 1532 /* 1533 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 1534 * for the display related bits. 1535 */ 1536 disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL); 1537 1538 intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); 1539 gen8_de_irq_handler(display, disp_ctl); 1540 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 1541 1542 intel_display_rpm_assert_unblock(display); 1543 } 1544 1545 static void i915gm_irq_cstate_wa_enable(struct intel_display *display) 1546 { 1547 lockdep_assert_held(&display->drm->vblank_time_lock); 1548 1549 /* 1550 * Vblank/CRC interrupts fail to wake the device up from C2+. 1551 * Disabling render clock gating during C-states avoids 1552 * the problem. There is a small power cost so we do this 1553 * only when vblank/CRC interrupts are actually enabled. 1554 */ 1555 if (display->irq.vblank_enabled++ == 0) 1556 intel_de_write(display, SCPD0, 1557 _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1558 } 1559 1560 static void i915gm_irq_cstate_wa_disable(struct intel_display *display) 1561 { 1562 lockdep_assert_held(&display->drm->vblank_time_lock); 1563 1564 if (--display->irq.vblank_enabled == 0) 1565 intel_de_write(display, SCPD0, 1566 _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1567 } 1568 1569 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable) 1570 { 1571 spin_lock_irq(&display->drm->vblank_time_lock); 1572 1573 if (enable) 1574 i915gm_irq_cstate_wa_enable(display); 1575 else 1576 i915gm_irq_cstate_wa_disable(display); 1577 1578 spin_unlock_irq(&display->drm->vblank_time_lock); 1579 } 1580 1581 int i8xx_enable_vblank(struct drm_crtc *crtc) 1582 { 1583 struct intel_display *display = to_intel_display(crtc->dev); 1584 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1585 unsigned long irqflags; 1586 1587 spin_lock_irqsave(&display->irq.lock, irqflags); 1588 i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1589 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1590 1591 return 0; 1592 } 1593 1594 void i8xx_disable_vblank(struct drm_crtc *crtc) 1595 { 1596 struct intel_display *display = to_intel_display(crtc->dev); 1597 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1598 unsigned long irqflags; 1599 1600 spin_lock_irqsave(&display->irq.lock, irqflags); 1601 i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1602 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1603 } 1604 1605 int i915gm_enable_vblank(struct drm_crtc *crtc) 1606 { 1607 struct intel_display *display = to_intel_display(crtc->dev); 1608 1609 i915gm_irq_cstate_wa_enable(display); 1610 1611 return i8xx_enable_vblank(crtc); 1612 } 1613 1614 void i915gm_disable_vblank(struct drm_crtc *crtc) 1615 { 1616 struct intel_display *display = to_intel_display(crtc->dev); 1617 1618 i8xx_disable_vblank(crtc); 1619 1620 i915gm_irq_cstate_wa_disable(display); 1621 } 1622 1623 int i965_enable_vblank(struct drm_crtc *crtc) 1624 { 1625 struct intel_display *display = to_intel_display(crtc->dev); 1626 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1627 unsigned long irqflags; 1628 1629 spin_lock_irqsave(&display->irq.lock, irqflags); 1630 i915_enable_pipestat(display, pipe, 1631 PIPE_START_VBLANK_INTERRUPT_STATUS); 1632 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1633 1634 return 0; 1635 } 1636 1637 void i965_disable_vblank(struct drm_crtc *crtc) 1638 { 1639 struct intel_display *display = to_intel_display(crtc->dev); 1640 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1641 unsigned long irqflags; 1642 1643 spin_lock_irqsave(&display->irq.lock, irqflags); 1644 i915_disable_pipestat(display, pipe, 1645 PIPE_START_VBLANK_INTERRUPT_STATUS); 1646 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1647 } 1648 1649 int ilk_enable_vblank(struct drm_crtc *crtc) 1650 { 1651 struct intel_display *display = to_intel_display(crtc->dev); 1652 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1653 unsigned long irqflags; 1654 u32 bit = DISPLAY_VER(display) >= 7 ? 1655 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1656 1657 spin_lock_irqsave(&display->irq.lock, irqflags); 1658 ilk_enable_display_irq(display, bit); 1659 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1660 1661 /* Even though there is no DMC, frame counter can get stuck when 1662 * PSR is active as no frames are generated. 1663 */ 1664 if (HAS_PSR(display)) 1665 drm_crtc_vblank_restore(crtc); 1666 1667 return 0; 1668 } 1669 1670 void ilk_disable_vblank(struct drm_crtc *crtc) 1671 { 1672 struct intel_display *display = to_intel_display(crtc->dev); 1673 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1674 unsigned long irqflags; 1675 u32 bit = DISPLAY_VER(display) >= 7 ? 1676 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1677 1678 spin_lock_irqsave(&display->irq.lock, irqflags); 1679 ilk_disable_display_irq(display, bit); 1680 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1681 } 1682 1683 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 1684 bool enable) 1685 { 1686 struct intel_display *display = to_intel_display(intel_crtc); 1687 enum port port; 1688 1689 if (!(intel_crtc->mode_flags & 1690 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 1691 return false; 1692 1693 /* for dual link cases we consider TE from slave */ 1694 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 1695 port = PORT_B; 1696 else 1697 port = PORT_A; 1698 1699 intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT); 1700 1701 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); 1702 1703 return true; 1704 } 1705 1706 static void intel_display_vblank_notify_work(struct work_struct *work) 1707 { 1708 struct intel_display *display = 1709 container_of(work, typeof(*display), irq.vblank_notify_work); 1710 int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count); 1711 1712 intel_psr_notify_vblank_enable_disable(display, vblank_enable_count); 1713 } 1714 1715 int bdw_enable_vblank(struct drm_crtc *_crtc) 1716 { 1717 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1718 struct intel_display *display = to_intel_display(crtc); 1719 enum pipe pipe = crtc->pipe; 1720 unsigned long irqflags; 1721 1722 if (gen11_dsi_configure_te(crtc, true)) 1723 return 0; 1724 1725 if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0) 1726 schedule_work(&display->irq.vblank_notify_work); 1727 1728 spin_lock_irqsave(&display->irq.lock, irqflags); 1729 bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK); 1730 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1731 1732 /* Even if there is no DMC, frame counter can get stuck when 1733 * PSR is active as no frames are generated, so check only for PSR. 1734 */ 1735 if (HAS_PSR(display)) 1736 drm_crtc_vblank_restore(&crtc->base); 1737 1738 return 0; 1739 } 1740 1741 void bdw_disable_vblank(struct drm_crtc *_crtc) 1742 { 1743 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1744 struct intel_display *display = to_intel_display(crtc); 1745 enum pipe pipe = crtc->pipe; 1746 unsigned long irqflags; 1747 1748 if (gen11_dsi_configure_te(crtc, false)) 1749 return; 1750 1751 spin_lock_irqsave(&display->irq.lock, irqflags); 1752 bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK); 1753 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1754 1755 if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0) 1756 schedule_work(&display->irq.vblank_notify_work); 1757 } 1758 1759 static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) 1760 { 1761 switch (pipe) { 1762 case PIPE_A: 1763 return SPRITEB_INVALID_GTT_STATUS | 1764 SPRITEA_INVALID_GTT_STATUS | 1765 PLANEA_INVALID_GTT_STATUS | 1766 CURSORA_INVALID_GTT_STATUS; 1767 case PIPE_B: 1768 return SPRITED_INVALID_GTT_STATUS | 1769 SPRITEC_INVALID_GTT_STATUS | 1770 PLANEB_INVALID_GTT_STATUS | 1771 CURSORB_INVALID_GTT_STATUS; 1772 case PIPE_C: 1773 return SPRITEF_INVALID_GTT_STATUS | 1774 SPRITEE_INVALID_GTT_STATUS | 1775 PLANEC_INVALID_GTT_STATUS | 1776 CURSORC_INVALID_GTT_STATUS; 1777 default: 1778 return 0; 1779 } 1780 } 1781 1782 static const struct pipe_fault_handler vlv_pipe_fault_handlers[] = { 1783 { .fault = SPRITEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, 1784 { .fault = SPRITEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1785 { .fault = PLANEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1786 { .fault = CURSORA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1787 { .fault = SPRITED_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, 1788 { .fault = SPRITEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1789 { .fault = PLANEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1790 { .fault = CURSORB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1791 { .fault = SPRITEF_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, 1792 { .fault = SPRITEE_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1793 { .fault = PLANEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1794 { .fault = CURSORC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1795 {} 1796 }; 1797 1798 static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt) 1799 { 1800 u32 status, enable, tmp; 1801 1802 tmp = intel_de_read(display, DPINVGTT); 1803 1804 enable = tmp >> 16; 1805 status = tmp & 0xffff; 1806 1807 /* 1808 * Despite what the docs claim, the status bits seem to get 1809 * stuck permanently (similar the old PGTBL_ER register), so 1810 * we have to disable and ignore them once set. They do get 1811 * reset if the display power well goes down, so no need to 1812 * track the enable mask explicitly. 1813 */ 1814 *dpinvgtt = status & enable; 1815 enable &= ~status; 1816 1817 /* customary ack+disable then re-enable to guarantee an edge */ 1818 intel_de_write(display, DPINVGTT, status); 1819 intel_de_write(display, DPINVGTT, enable << 16); 1820 } 1821 1822 static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt) 1823 { 1824 enum pipe pipe; 1825 1826 for_each_pipe(display, pipe) { 1827 u32 fault_errors; 1828 1829 fault_errors = dpinvgtt & vlv_dpinvgtt_pipe_fault_mask(pipe); 1830 if (fault_errors) 1831 intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers, 1832 pipe, fault_errors); 1833 } 1834 } 1835 1836 void vlv_display_error_irq_ack(struct intel_display *display, 1837 u32 *eir, u32 *dpinvgtt) 1838 { 1839 u32 emr; 1840 1841 *eir = intel_de_read(display, VLV_EIR); 1842 1843 if (*eir & VLV_ERROR_PAGE_TABLE) 1844 vlv_page_table_error_irq_ack(display, dpinvgtt); 1845 1846 intel_de_write(display, VLV_EIR, *eir); 1847 1848 /* 1849 * Toggle all EMR bits to make sure we get an edge 1850 * in the ISR master error bit if we don't clear 1851 * all the EIR bits. 1852 */ 1853 emr = intel_de_read(display, VLV_EMR); 1854 intel_de_write(display, VLV_EMR, 0xffffffff); 1855 intel_de_write(display, VLV_EMR, emr); 1856 } 1857 1858 void vlv_display_error_irq_handler(struct intel_display *display, 1859 u32 eir, u32 dpinvgtt) 1860 { 1861 drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir); 1862 1863 if (eir & VLV_ERROR_PAGE_TABLE) 1864 vlv_page_table_error_irq_handler(display, dpinvgtt); 1865 } 1866 1867 static void _vlv_display_irq_reset(struct intel_display *display) 1868 { 1869 struct drm_i915_private *dev_priv = to_i915(display->drm); 1870 1871 if (display->platform.cherryview) 1872 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 1873 else 1874 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1875 1876 gen2_error_reset(to_intel_uncore(display->drm), 1877 VLV_ERROR_REGS); 1878 1879 i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0); 1880 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); 1881 1882 i9xx_pipestat_irq_reset(display); 1883 1884 intel_display_irq_regs_reset(display, VLV_IRQ_REGS); 1885 dev_priv->irq_mask = ~0u; 1886 } 1887 1888 void vlv_display_irq_reset(struct intel_display *display) 1889 { 1890 spin_lock_irq(&display->irq.lock); 1891 if (display->irq.vlv_display_irqs_enabled) 1892 _vlv_display_irq_reset(display); 1893 spin_unlock_irq(&display->irq.lock); 1894 } 1895 1896 void i9xx_display_irq_reset(struct intel_display *display) 1897 { 1898 if (HAS_HOTPLUG(display)) { 1899 i915_hotplug_interrupt_update(display, 0xffffffff, 0); 1900 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); 1901 } 1902 1903 i9xx_pipestat_irq_reset(display); 1904 } 1905 1906 void i915_display_irq_postinstall(struct intel_display *display) 1907 { 1908 /* 1909 * Interrupt setup is already guaranteed to be single-threaded, this is 1910 * just to make the assert_spin_locked check happy. 1911 */ 1912 spin_lock_irq(&display->irq.lock); 1913 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 1914 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 1915 spin_unlock_irq(&display->irq.lock); 1916 1917 i915_enable_asle_pipestat(display); 1918 } 1919 1920 void i965_display_irq_postinstall(struct intel_display *display) 1921 { 1922 /* 1923 * Interrupt setup is already guaranteed to be single-threaded, this is 1924 * just to make the assert_spin_locked check happy. 1925 */ 1926 spin_lock_irq(&display->irq.lock); 1927 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1928 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 1929 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 1930 spin_unlock_irq(&display->irq.lock); 1931 1932 i915_enable_asle_pipestat(display); 1933 } 1934 1935 static u32 vlv_error_mask(void) 1936 { 1937 /* TODO enable other errors too? */ 1938 return VLV_ERROR_PAGE_TABLE; 1939 } 1940 1941 static void _vlv_display_irq_postinstall(struct intel_display *display) 1942 { 1943 struct drm_i915_private *dev_priv = to_i915(display->drm); 1944 u32 pipestat_mask; 1945 u32 enable_mask; 1946 enum pipe pipe; 1947 1948 if (display->platform.cherryview) 1949 intel_de_write(display, DPINVGTT, 1950 DPINVGTT_STATUS_MASK_CHV | 1951 DPINVGTT_EN_MASK_CHV); 1952 else 1953 intel_de_write(display, DPINVGTT, 1954 DPINVGTT_STATUS_MASK_VLV | 1955 DPINVGTT_EN_MASK_VLV); 1956 1957 gen2_error_init(to_intel_uncore(display->drm), 1958 VLV_ERROR_REGS, ~vlv_error_mask()); 1959 1960 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 1961 1962 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1963 for_each_pipe(display, pipe) 1964 i915_enable_pipestat(display, pipe, pipestat_mask); 1965 1966 enable_mask = I915_DISPLAY_PORT_INTERRUPT | 1967 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1968 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1969 I915_LPE_PIPE_A_INTERRUPT | 1970 I915_LPE_PIPE_B_INTERRUPT | 1971 I915_MASTER_ERROR_INTERRUPT; 1972 1973 if (display->platform.cherryview) 1974 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 1975 I915_LPE_PIPE_C_INTERRUPT; 1976 1977 drm_WARN_ON(display->drm, dev_priv->irq_mask != ~0u); 1978 1979 dev_priv->irq_mask = ~enable_mask; 1980 1981 intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask); 1982 } 1983 1984 void vlv_display_irq_postinstall(struct intel_display *display) 1985 { 1986 spin_lock_irq(&display->irq.lock); 1987 if (display->irq.vlv_display_irqs_enabled) 1988 _vlv_display_irq_postinstall(display); 1989 spin_unlock_irq(&display->irq.lock); 1990 } 1991 1992 void ibx_display_irq_reset(struct intel_display *display) 1993 { 1994 if (HAS_PCH_NOP(display)) 1995 return; 1996 1997 gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS); 1998 1999 if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) 2000 intel_de_write(display, SERR_INT, 0xffffffff); 2001 } 2002 2003 void gen8_display_irq_reset(struct intel_display *display) 2004 { 2005 enum pipe pipe; 2006 2007 if (!HAS_DISPLAY(display)) 2008 return; 2009 2010 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); 2011 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); 2012 2013 for_each_pipe(display, pipe) 2014 if (intel_display_power_is_enabled(display, 2015 POWER_DOMAIN_PIPE(pipe))) 2016 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2017 2018 intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); 2019 intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); 2020 2021 if (HAS_PCH_SPLIT(display)) 2022 ibx_display_irq_reset(display); 2023 } 2024 2025 void gen11_display_irq_reset(struct intel_display *display) 2026 { 2027 enum pipe pipe; 2028 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 2029 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 2030 2031 if (!HAS_DISPLAY(display)) 2032 return; 2033 2034 intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); 2035 2036 if (DISPLAY_VER(display) >= 12) { 2037 enum transcoder trans; 2038 2039 for_each_cpu_transcoder_masked(display, trans, trans_mask) { 2040 enum intel_display_power_domain domain; 2041 2042 domain = POWER_DOMAIN_TRANSCODER(trans); 2043 if (!intel_display_power_is_enabled(display, domain)) 2044 continue; 2045 2046 intel_de_write(display, 2047 TRANS_PSR_IMR(display, trans), 2048 0xffffffff); 2049 intel_de_write(display, 2050 TRANS_PSR_IIR(display, trans), 2051 0xffffffff); 2052 } 2053 } else { 2054 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); 2055 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); 2056 } 2057 2058 for_each_pipe(display, pipe) 2059 if (intel_display_power_is_enabled(display, 2060 POWER_DOMAIN_PIPE(pipe))) 2061 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2062 2063 intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); 2064 intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); 2065 2066 if (DISPLAY_VER(display) >= 14) 2067 intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS); 2068 else 2069 intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); 2070 2071 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2072 intel_display_irq_regs_reset(display, SDE_IRQ_REGS); 2073 } 2074 2075 void gen8_irq_power_well_post_enable(struct intel_display *display, 2076 u8 pipe_mask) 2077 { 2078 struct drm_i915_private *dev_priv = to_i915(display->drm); 2079 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 2080 gen8_de_pipe_flip_done_mask(display); 2081 enum pipe pipe; 2082 2083 spin_lock_irq(&display->irq.lock); 2084 2085 if (!intel_irqs_enabled(dev_priv)) { 2086 spin_unlock_irq(&display->irq.lock); 2087 return; 2088 } 2089 2090 for_each_pipe_masked(display, pipe, pipe_mask) 2091 intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2092 display->irq.de_irq_mask[pipe], 2093 ~display->irq.de_irq_mask[pipe] | extra_ier); 2094 2095 spin_unlock_irq(&display->irq.lock); 2096 } 2097 2098 void gen8_irq_power_well_pre_disable(struct intel_display *display, 2099 u8 pipe_mask) 2100 { 2101 struct drm_i915_private *dev_priv = to_i915(display->drm); 2102 enum pipe pipe; 2103 2104 spin_lock_irq(&display->irq.lock); 2105 2106 if (!intel_irqs_enabled(dev_priv)) { 2107 spin_unlock_irq(&display->irq.lock); 2108 return; 2109 } 2110 2111 for_each_pipe_masked(display, pipe, pipe_mask) 2112 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2113 2114 spin_unlock_irq(&display->irq.lock); 2115 2116 /* make sure we're done processing display irqs */ 2117 intel_synchronize_irq(dev_priv); 2118 } 2119 2120 /* 2121 * SDEIER is also touched by the interrupt handler to work around missed PCH 2122 * interrupts. Hence we can't update it after the interrupt handler is enabled - 2123 * instead we unconditionally enable all PCH interrupt sources here, but then 2124 * only unmask them as needed with SDEIMR. 2125 * 2126 * Note that we currently do this after installing the interrupt handler, 2127 * but before we enable the master interrupt. That should be sufficient 2128 * to avoid races with the irq handler, assuming we have MSI. Shared legacy 2129 * interrupts could still race. 2130 */ 2131 static void ibx_irq_postinstall(struct intel_display *display) 2132 { 2133 u32 mask; 2134 2135 if (HAS_PCH_NOP(display)) 2136 return; 2137 2138 if (HAS_PCH_IBX(display)) 2139 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 2140 else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) 2141 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 2142 else 2143 mask = SDE_GMBUS_CPT; 2144 2145 intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2146 } 2147 2148 void valleyview_enable_display_irqs(struct intel_display *display) 2149 { 2150 struct drm_i915_private *dev_priv = to_i915(display->drm); 2151 2152 spin_lock_irq(&display->irq.lock); 2153 2154 if (display->irq.vlv_display_irqs_enabled) 2155 goto out; 2156 2157 display->irq.vlv_display_irqs_enabled = true; 2158 2159 if (intel_irqs_enabled(dev_priv)) { 2160 _vlv_display_irq_reset(display); 2161 _vlv_display_irq_postinstall(display); 2162 } 2163 2164 out: 2165 spin_unlock_irq(&display->irq.lock); 2166 } 2167 2168 void valleyview_disable_display_irqs(struct intel_display *display) 2169 { 2170 struct drm_i915_private *dev_priv = to_i915(display->drm); 2171 2172 spin_lock_irq(&display->irq.lock); 2173 2174 if (!display->irq.vlv_display_irqs_enabled) 2175 goto out; 2176 2177 display->irq.vlv_display_irqs_enabled = false; 2178 2179 if (intel_irqs_enabled(dev_priv)) 2180 _vlv_display_irq_reset(display); 2181 out: 2182 spin_unlock_irq(&display->irq.lock); 2183 } 2184 2185 void ilk_de_irq_postinstall(struct intel_display *display) 2186 { 2187 struct drm_i915_private *i915 = to_i915(display->drm); 2188 2189 u32 display_mask, extra_mask; 2190 2191 if (DISPLAY_VER(display) >= 7) { 2192 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 2193 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 2194 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 2195 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 2196 DE_PLANE_FLIP_DONE_IVB(PLANE_C) | 2197 DE_PLANE_FLIP_DONE_IVB(PLANE_B) | 2198 DE_PLANE_FLIP_DONE_IVB(PLANE_A) | 2199 DE_DP_A_HOTPLUG_IVB); 2200 } else { 2201 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | 2202 DE_PCH_EVENT | DE_GTT_FAULT | 2203 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 2204 DE_PIPEA_CRC_DONE | DE_POISON); 2205 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 2206 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 2207 DE_PLANE_FLIP_DONE(PLANE_A) | 2208 DE_PLANE_FLIP_DONE(PLANE_B) | 2209 DE_DP_A_HOTPLUG); 2210 } 2211 2212 if (display->platform.haswell) { 2213 intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); 2214 display_mask |= DE_EDP_PSR_INT_HSW; 2215 } 2216 2217 if (display->platform.ironlake && display->platform.mobile) 2218 extra_mask |= DE_PCU_EVENT; 2219 2220 i915->irq_mask = ~display_mask; 2221 2222 ibx_irq_postinstall(display); 2223 2224 intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask, 2225 display_mask | extra_mask); 2226 } 2227 2228 static void mtp_irq_postinstall(struct intel_display *display); 2229 static void icp_irq_postinstall(struct intel_display *display); 2230 2231 void gen8_de_irq_postinstall(struct intel_display *display) 2232 { 2233 u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) | 2234 GEN8_PIPE_CDCLK_CRC_DONE; 2235 u32 de_pipe_enables; 2236 u32 de_port_masked = gen8_de_port_aux_mask(display); 2237 u32 de_port_enables; 2238 u32 de_misc_masked = GEN8_DE_EDP_PSR; 2239 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 2240 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 2241 enum pipe pipe; 2242 2243 if (!HAS_DISPLAY(display)) 2244 return; 2245 2246 if (DISPLAY_VER(display) >= 14) 2247 mtp_irq_postinstall(display); 2248 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2249 icp_irq_postinstall(display); 2250 else if (HAS_PCH_SPLIT(display)) 2251 ibx_irq_postinstall(display); 2252 2253 if (DISPLAY_VER(display) < 11) 2254 de_misc_masked |= GEN8_DE_MISC_GSE; 2255 2256 if (display->platform.geminilake || display->platform.broxton) 2257 de_port_masked |= BXT_DE_PORT_GMBUS; 2258 2259 if (DISPLAY_VER(display) >= 14) { 2260 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR | 2261 XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT; 2262 } else if (DISPLAY_VER(display) >= 11) { 2263 enum port port; 2264 2265 if (intel_bios_is_dsi_present(display, &port)) 2266 de_port_masked |= DSI0_TE | DSI1_TE; 2267 } 2268 2269 if (HAS_DBUF_OVERLAP_DETECTION(display)) 2270 de_misc_masked |= XE2LPD_DBUF_OVERLAP_DETECTED; 2271 2272 if (HAS_DSB(display)) 2273 de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) | 2274 GEN12_DSB_INT(INTEL_DSB_1) | 2275 GEN12_DSB_INT(INTEL_DSB_2); 2276 2277 /* TODO figure PIPEDMC interrupts for pre-LNL */ 2278 if (DISPLAY_VER(display) >= 20) 2279 de_pipe_masked |= GEN12_PIPEDMC_INTERRUPT; 2280 2281 de_pipe_enables = de_pipe_masked | 2282 GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 2283 gen8_de_pipe_flip_done_mask(display); 2284 2285 de_port_enables = de_port_masked; 2286 if (display->platform.geminilake || display->platform.broxton) 2287 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 2288 else if (display->platform.broadwell) 2289 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 2290 2291 if (DISPLAY_VER(display) >= 12) { 2292 enum transcoder trans; 2293 2294 for_each_cpu_transcoder_masked(display, trans, trans_mask) { 2295 enum intel_display_power_domain domain; 2296 2297 domain = POWER_DOMAIN_TRANSCODER(trans); 2298 if (!intel_display_power_is_enabled(display, domain)) 2299 continue; 2300 2301 intel_display_irq_regs_assert_irr_is_zero(display, 2302 TRANS_PSR_IIR(display, trans)); 2303 } 2304 } else { 2305 intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); 2306 } 2307 2308 for_each_pipe(display, pipe) { 2309 display->irq.de_irq_mask[pipe] = ~de_pipe_masked; 2310 2311 if (intel_display_power_is_enabled(display, 2312 POWER_DOMAIN_PIPE(pipe))) 2313 intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2314 display->irq.de_irq_mask[pipe], 2315 de_pipe_enables); 2316 } 2317 2318 intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, 2319 de_port_enables); 2320 intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, 2321 de_misc_masked); 2322 2323 if (IS_DISPLAY_VER(display, 11, 13)) { 2324 u32 de_hpd_masked = 0; 2325 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 2326 GEN11_DE_TBT_HOTPLUG_MASK; 2327 2328 intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, 2329 de_hpd_enables); 2330 } 2331 } 2332 2333 static void mtp_irq_postinstall(struct intel_display *display) 2334 { 2335 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; 2336 u32 de_hpd_mask = XELPDP_AUX_TC_MASK; 2337 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 2338 XELPDP_TBT_HOTPLUG_MASK; 2339 2340 intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, 2341 de_hpd_enables); 2342 2343 intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); 2344 } 2345 2346 static void icp_irq_postinstall(struct intel_display *display) 2347 { 2348 u32 mask = SDE_GMBUS_ICP; 2349 2350 intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2351 } 2352 2353 void gen11_de_irq_postinstall(struct intel_display *display) 2354 { 2355 if (!HAS_DISPLAY(display)) 2356 return; 2357 2358 gen8_de_irq_postinstall(display); 2359 2360 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 2361 } 2362 2363 void dg1_de_irq_postinstall(struct intel_display *display) 2364 { 2365 if (!HAS_DISPLAY(display)) 2366 return; 2367 2368 gen8_de_irq_postinstall(display); 2369 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 2370 } 2371 2372 void intel_display_irq_init(struct intel_display *display) 2373 { 2374 spin_lock_init(&display->irq.lock); 2375 2376 display->drm->vblank_disable_immediate = true; 2377 2378 intel_hotplug_irq_init(display); 2379 2380 INIT_WORK(&display->irq.vblank_notify_work, 2381 intel_display_vblank_notify_work); 2382 } 2383 2384 struct intel_display_irq_snapshot { 2385 u32 derrmr; 2386 }; 2387 2388 struct intel_display_irq_snapshot * 2389 intel_display_irq_snapshot_capture(struct intel_display *display) 2390 { 2391 struct intel_display_irq_snapshot *snapshot; 2392 2393 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 2394 if (!snapshot) 2395 return NULL; 2396 2397 if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display)) 2398 snapshot->derrmr = intel_de_read(display, DERRMR); 2399 2400 return snapshot; 2401 } 2402 2403 void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, 2404 struct drm_printer *p) 2405 { 2406 if (!snapshot) 2407 return; 2408 2409 drm_printf(p, "DERRMR: 0x%08x\n", snapshot->derrmr); 2410 } 2411