1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 #include <drm/drm_vblank.h> 8 #include <drm/intel/intel_gmd_interrupt_regs.h> 9 10 #include "icl_dsi_regs.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_irq.h" 14 #include "intel_display_regs.h" 15 #include "intel_display_rpm.h" 16 #include "intel_display_rps.h" 17 #include "intel_display_trace.h" 18 #include "intel_display_types.h" 19 #include "intel_dmc.h" 20 #include "intel_dp_aux.h" 21 #include "intel_dsb.h" 22 #include "intel_fdi_regs.h" 23 #include "intel_fifo_underrun.h" 24 #include "intel_gmbus.h" 25 #include "intel_hotplug_irq.h" 26 #include "intel_lpe_audio.h" 27 #include "intel_parent.h" 28 #include "intel_pipe_crc_regs.h" 29 #include "intel_plane.h" 30 #include "intel_pmdemand.h" 31 #include "intel_psr.h" 32 #include "intel_psr_regs.h" 33 34 static void irq_reset(struct intel_display *display, struct intel_irq_regs regs) 35 { 36 intel_de_write(display, regs.imr, 0xffffffff); 37 intel_de_posting_read(display, regs.imr); 38 39 intel_de_write(display, regs.ier, 0); 40 41 /* IIR can theoretically queue up two events. Be paranoid. */ 42 intel_de_write(display, regs.iir, 0xffffffff); 43 intel_de_posting_read(display, regs.iir); 44 intel_de_write(display, regs.iir, 0xffffffff); 45 intel_de_posting_read(display, regs.iir); 46 } 47 48 /* 49 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 50 */ 51 static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) 52 { 53 u32 val = intel_de_read(display, reg); 54 55 if (val == 0) 56 return; 57 58 drm_WARN(display->drm, 1, 59 "Interrupt register 0x%x is not zero: 0x%08x\n", 60 intel_reg_offset(reg), val); 61 intel_de_write(display, reg, 0xffffffff); 62 intel_de_posting_read(display, reg); 63 intel_de_write(display, reg, 0xffffffff); 64 intel_de_posting_read(display, reg); 65 } 66 67 static void irq_init(struct intel_display *display, struct intel_irq_regs regs, 68 u32 imr_val, u32 ier_val) 69 { 70 assert_iir_is_zero(display, regs.iir); 71 72 intel_de_write(display, regs.ier, ier_val); 73 intel_de_write(display, regs.imr, imr_val); 74 intel_de_posting_read(display, regs.imr); 75 } 76 77 static void error_reset(struct intel_display *display, struct intel_error_regs regs) 78 { 79 intel_de_write(display, regs.emr, 0xffffffff); 80 intel_de_posting_read(display, regs.emr); 81 82 intel_de_write(display, regs.eir, 0xffffffff); 83 intel_de_posting_read(display, regs.eir); 84 intel_de_write(display, regs.eir, 0xffffffff); 85 intel_de_posting_read(display, regs.eir); 86 } 87 88 static void error_init(struct intel_display *display, struct intel_error_regs regs, 89 u32 emr_val) 90 { 91 intel_de_write(display, regs.eir, 0xffffffff); 92 intel_de_posting_read(display, regs.eir); 93 intel_de_write(display, regs.eir, 0xffffffff); 94 intel_de_posting_read(display, regs.eir); 95 96 intel_de_write(display, regs.emr, emr_val); 97 intel_de_posting_read(display, regs.emr); 98 } 99 100 struct pipe_fault_handler { 101 bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id); 102 u32 fault; 103 enum plane_id plane_id; 104 }; 105 106 static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) 107 { 108 struct intel_display *display = to_intel_display(crtc); 109 struct intel_plane_error error = {}; 110 struct intel_plane *plane; 111 112 plane = intel_crtc_get_plane(crtc, plane_id); 113 if (!plane || !plane->capture_error) 114 return false; 115 116 plane->capture_error(crtc, plane, &error); 117 118 drm_err_ratelimited(display->drm, 119 "[CRTC:%d:%s][PLANE:%d:%s] fault (CTL=0x%x, SURF=0x%x, SURFLIVE=0x%x)\n", 120 crtc->base.base.id, crtc->base.name, 121 plane->base.base.id, plane->base.name, 122 error.ctl, error.surf, error.surflive); 123 124 return true; 125 } 126 127 static void intel_pipe_fault_irq_handler(struct intel_display *display, 128 const struct pipe_fault_handler *handlers, 129 enum pipe pipe, u32 fault_errors) 130 { 131 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 132 const struct pipe_fault_handler *handler; 133 134 for (handler = handlers; handler && handler->fault; handler++) { 135 if ((fault_errors & handler->fault) == 0) 136 continue; 137 138 if (handler->handle(crtc, handler->plane_id)) 139 fault_errors &= ~handler->fault; 140 } 141 142 WARN_ONCE(fault_errors, "[CRTC:%d:%s] unreported faults 0x%x\n", 143 crtc->base.base.id, crtc->base.name, fault_errors); 144 } 145 146 static void 147 intel_handle_vblank(struct intel_display *display, enum pipe pipe) 148 { 149 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 150 151 drm_crtc_handle_vblank(&crtc->base); 152 } 153 154 /** 155 * ilk_update_display_irq - update DEIMR 156 * @display: display device 157 * @interrupt_mask: mask of interrupt bits to update 158 * @enabled_irq_mask: mask of interrupt bits to enable 159 */ 160 void ilk_update_display_irq(struct intel_display *display, 161 u32 interrupt_mask, u32 enabled_irq_mask) 162 { 163 u32 new_val; 164 165 lockdep_assert_held(&display->irq.lock); 166 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 167 168 new_val = display->irq.ilk_de_imr_mask; 169 new_val &= ~interrupt_mask; 170 new_val |= (~enabled_irq_mask & interrupt_mask); 171 172 if (new_val != display->irq.ilk_de_imr_mask && 173 !drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) { 174 display->irq.ilk_de_imr_mask = new_val; 175 intel_de_write(display, DEIMR, display->irq.ilk_de_imr_mask); 176 intel_de_posting_read(display, DEIMR); 177 } 178 } 179 180 void ilk_enable_display_irq(struct intel_display *display, u32 bits) 181 { 182 ilk_update_display_irq(display, bits, bits); 183 } 184 185 void ilk_disable_display_irq(struct intel_display *display, u32 bits) 186 { 187 ilk_update_display_irq(display, bits, 0); 188 } 189 190 /** 191 * bdw_update_port_irq - update DE port interrupt 192 * @display: display device 193 * @interrupt_mask: mask of interrupt bits to update 194 * @enabled_irq_mask: mask of interrupt bits to enable 195 */ 196 void bdw_update_port_irq(struct intel_display *display, 197 u32 interrupt_mask, u32 enabled_irq_mask) 198 { 199 u32 new_val; 200 u32 old_val; 201 202 lockdep_assert_held(&display->irq.lock); 203 204 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 205 206 if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) 207 return; 208 209 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); 210 211 new_val = old_val; 212 new_val &= ~interrupt_mask; 213 new_val |= (~enabled_irq_mask & interrupt_mask); 214 215 if (new_val != old_val) { 216 intel_de_write(display, GEN8_DE_PORT_IMR, new_val); 217 intel_de_posting_read(display, GEN8_DE_PORT_IMR); 218 } 219 } 220 221 /** 222 * bdw_update_pipe_irq - update DE pipe interrupt 223 * @display: display device 224 * @pipe: pipe whose interrupt to update 225 * @interrupt_mask: mask of interrupt bits to update 226 * @enabled_irq_mask: mask of interrupt bits to enable 227 */ 228 static void bdw_update_pipe_irq(struct intel_display *display, 229 enum pipe pipe, u32 interrupt_mask, 230 u32 enabled_irq_mask) 231 { 232 u32 new_val; 233 234 lockdep_assert_held(&display->irq.lock); 235 236 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 237 238 if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) 239 return; 240 241 new_val = display->irq.de_pipe_imr_mask[pipe]; 242 new_val &= ~interrupt_mask; 243 new_val |= (~enabled_irq_mask & interrupt_mask); 244 245 if (new_val != display->irq.de_pipe_imr_mask[pipe]) { 246 display->irq.de_pipe_imr_mask[pipe] = new_val; 247 intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_pipe_imr_mask[pipe]); 248 intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); 249 } 250 } 251 252 void bdw_enable_pipe_irq(struct intel_display *display, 253 enum pipe pipe, u32 bits) 254 { 255 bdw_update_pipe_irq(display, pipe, bits, bits); 256 } 257 258 void bdw_disable_pipe_irq(struct intel_display *display, 259 enum pipe pipe, u32 bits) 260 { 261 bdw_update_pipe_irq(display, pipe, bits, 0); 262 } 263 264 /** 265 * ibx_display_interrupt_update - update SDEIMR 266 * @display: display device 267 * @interrupt_mask: mask of interrupt bits to update 268 * @enabled_irq_mask: mask of interrupt bits to enable 269 */ 270 void ibx_display_interrupt_update(struct intel_display *display, 271 u32 interrupt_mask, 272 u32 enabled_irq_mask) 273 { 274 u32 sdeimr = intel_de_read(display, SDEIMR); 275 276 sdeimr &= ~interrupt_mask; 277 sdeimr |= (~enabled_irq_mask & interrupt_mask); 278 279 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 280 281 lockdep_assert_held(&display->irq.lock); 282 283 if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) 284 return; 285 286 intel_de_write(display, SDEIMR, sdeimr); 287 intel_de_posting_read(display, SDEIMR); 288 } 289 290 void ibx_enable_display_interrupt(struct intel_display *display, u32 bits) 291 { 292 ibx_display_interrupt_update(display, bits, bits); 293 } 294 295 void ibx_disable_display_interrupt(struct intel_display *display, u32 bits) 296 { 297 ibx_display_interrupt_update(display, bits, 0); 298 } 299 300 u32 i915_pipestat_enable_mask(struct intel_display *display, 301 enum pipe pipe) 302 { 303 u32 status_mask = display->irq.pipestat_irq_mask[pipe]; 304 u32 enable_mask = status_mask << 16; 305 306 lockdep_assert_held(&display->irq.lock); 307 308 if (DISPLAY_VER(display) < 5) 309 goto out; 310 311 /* 312 * On pipe A we don't support the PSR interrupt yet, 313 * on pipe B and C the same bit MBZ. 314 */ 315 if (drm_WARN_ON_ONCE(display->drm, 316 status_mask & PIPE_A_PSR_STATUS_VLV)) 317 return 0; 318 /* 319 * On pipe B and C we don't support the PSR interrupt yet, on pipe 320 * A the same bit is for perf counters which we don't use either. 321 */ 322 if (drm_WARN_ON_ONCE(display->drm, 323 status_mask & PIPE_B_PSR_STATUS_VLV)) 324 return 0; 325 326 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 327 SPRITE0_FLIP_DONE_INT_EN_VLV | 328 SPRITE1_FLIP_DONE_INT_EN_VLV); 329 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 330 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 331 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 332 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 333 334 out: 335 drm_WARN_ONCE(display->drm, 336 enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 337 status_mask & ~PIPESTAT_INT_STATUS_MASK, 338 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 339 pipe_name(pipe), enable_mask, status_mask); 340 341 return enable_mask; 342 } 343 344 void i915_enable_pipestat(struct intel_display *display, 345 enum pipe pipe, u32 status_mask) 346 { 347 intel_reg_t reg = PIPESTAT(display, pipe); 348 u32 enable_mask; 349 350 drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 351 "pipe %c: status_mask=0x%x\n", 352 pipe_name(pipe), status_mask); 353 354 lockdep_assert_held(&display->irq.lock); 355 drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)); 356 357 if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) 358 return; 359 360 display->irq.pipestat_irq_mask[pipe] |= status_mask; 361 enable_mask = i915_pipestat_enable_mask(display, pipe); 362 363 intel_de_write(display, reg, enable_mask | status_mask); 364 intel_de_posting_read(display, reg); 365 } 366 367 void i915_disable_pipestat(struct intel_display *display, 368 enum pipe pipe, u32 status_mask) 369 { 370 intel_reg_t reg = PIPESTAT(display, pipe); 371 u32 enable_mask; 372 373 drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 374 "pipe %c: status_mask=0x%x\n", 375 pipe_name(pipe), status_mask); 376 377 lockdep_assert_held(&display->irq.lock); 378 drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)); 379 380 if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0) 381 return; 382 383 display->irq.pipestat_irq_mask[pipe] &= ~status_mask; 384 enable_mask = i915_pipestat_enable_mask(display, pipe); 385 386 intel_de_write(display, reg, enable_mask | status_mask); 387 intel_de_posting_read(display, reg); 388 } 389 390 static bool i915_has_legacy_blc_interrupt(struct intel_display *display) 391 { 392 if (display->platform.i85x) 393 return true; 394 395 if (display->platform.pineview) 396 return true; 397 398 return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile; 399 } 400 401 /* enable ASLE pipestat for OpRegion */ 402 static void i915_enable_asle_pipestat(struct intel_display *display) 403 { 404 if (!intel_opregion_asle_present(display)) 405 return; 406 407 if (!i915_has_legacy_blc_interrupt(display)) 408 return; 409 410 spin_lock_irq(&display->irq.lock); 411 412 i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 413 if (DISPLAY_VER(display) >= 4) 414 i915_enable_pipestat(display, PIPE_A, 415 PIPE_LEGACY_BLC_EVENT_STATUS); 416 417 spin_unlock_irq(&display->irq.lock); 418 } 419 420 #if IS_ENABLED(CONFIG_DEBUG_FS) 421 static void display_pipe_crc_irq_handler(struct intel_display *display, 422 enum pipe pipe, 423 u32 crc0, u32 crc1, 424 u32 crc2, u32 crc3, 425 u32 crc4) 426 { 427 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 428 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 429 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 430 431 trace_intel_pipe_crc(crtc, crcs); 432 433 spin_lock(&pipe_crc->lock); 434 /* 435 * For some not yet identified reason, the first CRC is 436 * bonkers. So let's just wait for the next vblank and read 437 * out the buggy result. 438 * 439 * On GEN8+ sometimes the second CRC is bonkers as well, so 440 * don't trust that one either. 441 */ 442 if (pipe_crc->skipped <= 0 || 443 (DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) { 444 pipe_crc->skipped++; 445 spin_unlock(&pipe_crc->lock); 446 return; 447 } 448 spin_unlock(&pipe_crc->lock); 449 450 drm_crtc_add_crc_entry(&crtc->base, true, 451 drm_crtc_accurate_vblank_count(&crtc->base), 452 crcs); 453 } 454 #else 455 static inline void 456 display_pipe_crc_irq_handler(struct intel_display *display, 457 enum pipe pipe, 458 u32 crc0, u32 crc1, 459 u32 crc2, u32 crc3, 460 u32 crc4) {} 461 #endif 462 463 static void flip_done_handler(struct intel_display *display, 464 enum pipe pipe) 465 { 466 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 467 468 spin_lock(&display->drm->event_lock); 469 470 if (crtc->flip_done_event) { 471 trace_intel_crtc_flip_done(crtc); 472 drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event); 473 crtc->flip_done_event = NULL; 474 } 475 476 spin_unlock(&display->drm->event_lock); 477 } 478 479 static void hsw_pipe_crc_irq_handler(struct intel_display *display, 480 enum pipe pipe) 481 { 482 display_pipe_crc_irq_handler(display, pipe, 483 intel_de_read(display, PIPE_CRC_RES_HSW(pipe)), 484 0, 0, 0, 0); 485 } 486 487 static void ivb_pipe_crc_irq_handler(struct intel_display *display, 488 enum pipe pipe) 489 { 490 display_pipe_crc_irq_handler(display, pipe, 491 intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)), 492 intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)), 493 intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)), 494 intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)), 495 intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe))); 496 } 497 498 static void i9xx_pipe_crc_irq_handler(struct intel_display *display, 499 enum pipe pipe) 500 { 501 u32 res1, res2; 502 503 if (DISPLAY_VER(display) >= 3) 504 res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe)); 505 else 506 res1 = 0; 507 508 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 509 res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe)); 510 else 511 res2 = 0; 512 513 display_pipe_crc_irq_handler(display, pipe, 514 intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)), 515 intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)), 516 intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)), 517 res1, res2); 518 } 519 520 static void i9xx_pipestat_irq_reset(struct intel_display *display) 521 { 522 enum pipe pipe; 523 524 for_each_pipe(display, pipe) { 525 intel_de_write(display, 526 PIPESTAT(display, pipe), 527 PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS); 528 529 display->irq.pipestat_irq_mask[pipe] = 0; 530 } 531 } 532 533 static void i9xx_pipestat_irq_ack(struct intel_display *display, 534 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 535 { 536 enum pipe pipe; 537 538 spin_lock(&display->irq.lock); 539 540 if ((display->platform.valleyview || display->platform.cherryview) && 541 !display->irq.vlv_display_irqs_enabled) { 542 spin_unlock(&display->irq.lock); 543 return; 544 } 545 546 for_each_pipe(display, pipe) { 547 intel_reg_t reg; 548 u32 status_mask, enable_mask, iir_bit = 0; 549 550 /* 551 * PIPESTAT bits get signalled even when the interrupt is 552 * disabled with the mask bits, and some of the status bits do 553 * not generate interrupts at all (like the underrun bit). Hence 554 * we need to be careful that we only handle what we want to 555 * handle. 556 */ 557 558 /* fifo underruns are filterered in the underrun handler. */ 559 status_mask = PIPE_FIFO_UNDERRUN_STATUS; 560 561 switch (pipe) { 562 default: 563 case PIPE_A: 564 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 565 break; 566 case PIPE_B: 567 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 568 break; 569 case PIPE_C: 570 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 571 break; 572 } 573 if (iir & iir_bit) 574 status_mask |= display->irq.pipestat_irq_mask[pipe]; 575 576 if (!status_mask) 577 continue; 578 579 reg = PIPESTAT(display, pipe); 580 pipe_stats[pipe] = intel_de_read(display, reg) & status_mask; 581 enable_mask = i915_pipestat_enable_mask(display, pipe); 582 583 /* 584 * Clear the PIPE*STAT regs before the IIR 585 * 586 * Toggle the enable bits to make sure we get an 587 * edge in the ISR pipe event bit if we don't clear 588 * all the enabled status bits. Otherwise the edge 589 * triggered IIR on i965/g4x wouldn't notice that 590 * an interrupt is still pending. 591 */ 592 if (pipe_stats[pipe]) { 593 intel_de_write(display, reg, pipe_stats[pipe]); 594 intel_de_write(display, reg, enable_mask); 595 } 596 } 597 spin_unlock(&display->irq.lock); 598 } 599 600 static void i915_pipestat_irq_handler(struct intel_display *display, 601 u32 iir, const u32 pipe_stats[I915_MAX_PIPES]) 602 { 603 bool blc_event = false; 604 enum pipe pipe; 605 606 for_each_pipe(display, pipe) { 607 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 608 intel_handle_vblank(display, pipe); 609 610 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 611 blc_event = true; 612 613 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 614 i9xx_pipe_crc_irq_handler(display, pipe); 615 616 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 617 intel_cpu_fifo_underrun_irq_handler(display, pipe); 618 } 619 620 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 621 intel_opregion_asle_intr(display); 622 } 623 624 static void i965_pipestat_irq_handler(struct intel_display *display, 625 u32 iir, const u32 pipe_stats[I915_MAX_PIPES]) 626 { 627 bool blc_event = false; 628 enum pipe pipe; 629 630 for_each_pipe(display, pipe) { 631 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 632 intel_handle_vblank(display, pipe); 633 634 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 635 blc_event = true; 636 637 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 638 i9xx_pipe_crc_irq_handler(display, pipe); 639 640 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 641 intel_cpu_fifo_underrun_irq_handler(display, pipe); 642 } 643 644 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 645 intel_opregion_asle_intr(display); 646 647 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 648 intel_gmbus_irq_handler(display); 649 } 650 651 static void valleyview_pipestat_irq_handler(struct intel_display *display, 652 const u32 pipe_stats[I915_MAX_PIPES]) 653 { 654 enum pipe pipe; 655 656 for_each_pipe(display, pipe) { 657 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 658 intel_handle_vblank(display, pipe); 659 660 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) 661 flip_done_handler(display, pipe); 662 663 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 664 i9xx_pipe_crc_irq_handler(display, pipe); 665 666 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 667 intel_cpu_fifo_underrun_irq_handler(display, pipe); 668 } 669 670 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 671 intel_gmbus_irq_handler(display); 672 } 673 674 static void ibx_irq_handler(struct intel_display *display, u32 pch_iir) 675 { 676 enum pipe pipe; 677 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 678 679 ibx_hpd_irq_handler(display, hotplug_trigger); 680 681 if (pch_iir & SDE_AUDIO_POWER_MASK) { 682 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 683 SDE_AUDIO_POWER_SHIFT); 684 drm_dbg(display->drm, "PCH audio power change on port %d\n", 685 port_name(port)); 686 } 687 688 if (pch_iir & SDE_AUX_MASK) 689 intel_dp_aux_irq_handler(display); 690 691 if (pch_iir & SDE_GMBUS) 692 intel_gmbus_irq_handler(display); 693 694 if (pch_iir & SDE_AUDIO_HDCP_MASK) 695 drm_dbg(display->drm, "PCH HDCP audio interrupt\n"); 696 697 if (pch_iir & SDE_AUDIO_TRANS_MASK) 698 drm_dbg(display->drm, "PCH transcoder audio interrupt\n"); 699 700 if (pch_iir & SDE_POISON) 701 drm_err(display->drm, "PCH poison interrupt\n"); 702 703 if (pch_iir & SDE_FDI_MASK) { 704 for_each_pipe(display, pipe) 705 drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n", 706 pipe_name(pipe), 707 intel_de_read(display, FDI_RX_IIR(pipe))); 708 } 709 710 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 711 drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n"); 712 713 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 714 drm_dbg(display->drm, 715 "PCH transcoder CRC error interrupt\n"); 716 717 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 718 intel_pch_fifo_underrun_irq_handler(display, PIPE_A); 719 720 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 721 intel_pch_fifo_underrun_irq_handler(display, PIPE_B); 722 } 723 724 static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe) 725 { 726 switch (pipe) { 727 case PIPE_A: 728 return ERR_INT_SPRITE_A_FAULT | 729 ERR_INT_PRIMARY_A_FAULT | 730 ERR_INT_CURSOR_A_FAULT; 731 case PIPE_B: 732 return ERR_INT_SPRITE_B_FAULT | 733 ERR_INT_PRIMARY_B_FAULT | 734 ERR_INT_CURSOR_B_FAULT; 735 case PIPE_C: 736 return ERR_INT_SPRITE_C_FAULT | 737 ERR_INT_PRIMARY_C_FAULT | 738 ERR_INT_CURSOR_C_FAULT; 739 default: 740 return 0; 741 } 742 } 743 744 static const struct pipe_fault_handler ivb_pipe_fault_handlers[] = { 745 { .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 746 { .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 747 { .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 748 { .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 749 { .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 750 { .fault = ERR_INT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 751 { .fault = ERR_INT_SPRITE_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 752 { .fault = ERR_INT_PRIMARY_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 753 { .fault = ERR_INT_CURSOR_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 754 {} 755 }; 756 757 static void ivb_err_int_handler(struct intel_display *display) 758 { 759 u32 err_int = intel_de_read(display, GEN7_ERR_INT); 760 enum pipe pipe; 761 762 if (err_int & ERR_INT_POISON) 763 drm_err(display->drm, "Poison interrupt\n"); 764 765 if (err_int & ERR_INT_INVALID_GTT_PTE) 766 drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); 767 768 if (err_int & ERR_INT_INVALID_PTE_DATA) 769 drm_err_ratelimited(display->drm, "Invalid PTE data\n"); 770 771 for_each_pipe(display, pipe) { 772 u32 fault_errors; 773 774 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 775 intel_cpu_fifo_underrun_irq_handler(display, pipe); 776 777 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 778 if (display->platform.ivybridge) 779 ivb_pipe_crc_irq_handler(display, pipe); 780 else 781 hsw_pipe_crc_irq_handler(display, pipe); 782 } 783 784 fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe); 785 if (fault_errors) 786 intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers, 787 pipe, fault_errors); 788 } 789 790 intel_de_write(display, GEN7_ERR_INT, err_int); 791 } 792 793 static void cpt_serr_int_handler(struct intel_display *display) 794 { 795 u32 serr_int = intel_de_read(display, SERR_INT); 796 enum pipe pipe; 797 798 if (serr_int & SERR_INT_POISON) 799 drm_err(display->drm, "PCH poison interrupt\n"); 800 801 for_each_pipe(display, pipe) 802 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 803 intel_pch_fifo_underrun_irq_handler(display, pipe); 804 805 intel_de_write(display, SERR_INT, serr_int); 806 } 807 808 static void cpt_irq_handler(struct intel_display *display, u32 pch_iir) 809 { 810 enum pipe pipe; 811 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 812 813 ibx_hpd_irq_handler(display, hotplug_trigger); 814 815 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 816 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 817 SDE_AUDIO_POWER_SHIFT_CPT); 818 drm_dbg(display->drm, "PCH audio power change on port %c\n", 819 port_name(port)); 820 } 821 822 if (pch_iir & SDE_AUX_MASK_CPT) 823 intel_dp_aux_irq_handler(display); 824 825 if (pch_iir & SDE_GMBUS_CPT) 826 intel_gmbus_irq_handler(display); 827 828 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 829 drm_dbg(display->drm, "Audio CP request interrupt\n"); 830 831 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 832 drm_dbg(display->drm, "Audio CP change interrupt\n"); 833 834 if (pch_iir & SDE_FDI_MASK_CPT) { 835 for_each_pipe(display, pipe) 836 drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n", 837 pipe_name(pipe), 838 intel_de_read(display, FDI_RX_IIR(pipe))); 839 } 840 841 if (pch_iir & SDE_ERROR_CPT) 842 cpt_serr_int_handler(display); 843 } 844 845 static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe) 846 { 847 switch (pipe) { 848 case PIPE_A: 849 return GTT_FAULT_SPRITE_A_FAULT | 850 GTT_FAULT_PRIMARY_A_FAULT | 851 GTT_FAULT_CURSOR_A_FAULT; 852 case PIPE_B: 853 return GTT_FAULT_SPRITE_B_FAULT | 854 GTT_FAULT_PRIMARY_B_FAULT | 855 GTT_FAULT_CURSOR_B_FAULT; 856 default: 857 return 0; 858 } 859 } 860 861 static const struct pipe_fault_handler ilk_pipe_fault_handlers[] = { 862 { .fault = GTT_FAULT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 863 { .fault = GTT_FAULT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 864 { .fault = GTT_FAULT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 865 { .fault = GTT_FAULT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 866 { .fault = GTT_FAULT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 867 { .fault = GTT_FAULT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 868 {} 869 }; 870 871 static void ilk_gtt_fault_irq_handler(struct intel_display *display) 872 { 873 enum pipe pipe; 874 u32 gtt_fault; 875 876 gtt_fault = intel_de_read(display, ILK_GTT_FAULT); 877 intel_de_write(display, ILK_GTT_FAULT, gtt_fault); 878 879 if (gtt_fault & GTT_FAULT_INVALID_GTT_PTE) 880 drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); 881 882 if (gtt_fault & GTT_FAULT_INVALID_PTE_DATA) 883 drm_err_ratelimited(display->drm, "Invalid PTE data\n"); 884 885 for_each_pipe(display, pipe) { 886 u32 fault_errors; 887 888 fault_errors = gtt_fault & ilk_gtt_fault_pipe_fault_mask(pipe); 889 if (fault_errors) 890 intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers, 891 pipe, fault_errors); 892 } 893 } 894 895 static void _ilk_display_irq_handler(struct intel_display *display, u32 de_iir) 896 { 897 enum pipe pipe; 898 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 899 900 if (hotplug_trigger) 901 ilk_hpd_irq_handler(display, hotplug_trigger); 902 903 if (de_iir & DE_AUX_CHANNEL_A) 904 intel_dp_aux_irq_handler(display); 905 906 if (de_iir & DE_GSE) 907 intel_opregion_asle_intr(display); 908 909 if (de_iir & DE_POISON) 910 drm_err(display->drm, "Poison interrupt\n"); 911 912 if (de_iir & DE_GTT_FAULT) 913 ilk_gtt_fault_irq_handler(display); 914 915 for_each_pipe(display, pipe) { 916 if (de_iir & DE_PIPE_VBLANK(pipe)) 917 intel_handle_vblank(display, pipe); 918 919 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) 920 flip_done_handler(display, pipe); 921 922 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 923 intel_cpu_fifo_underrun_irq_handler(display, pipe); 924 925 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 926 i9xx_pipe_crc_irq_handler(display, pipe); 927 } 928 929 /* check event from PCH */ 930 if (de_iir & DE_PCH_EVENT) { 931 u32 pch_iir = intel_de_read(display, SDEIIR); 932 933 if (HAS_PCH_CPT(display)) 934 cpt_irq_handler(display, pch_iir); 935 else 936 ibx_irq_handler(display, pch_iir); 937 938 /* should clear PCH hotplug event before clear CPU irq */ 939 intel_de_write(display, SDEIIR, pch_iir); 940 } 941 942 if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT) 943 ilk_display_rps_irq_handler(display); 944 } 945 946 static void _ivb_display_irq_handler(struct intel_display *display, u32 de_iir) 947 { 948 enum pipe pipe; 949 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 950 951 if (hotplug_trigger) 952 ilk_hpd_irq_handler(display, hotplug_trigger); 953 954 if (de_iir & DE_ERR_INT_IVB) 955 ivb_err_int_handler(display); 956 957 if (de_iir & DE_EDP_PSR_INT_HSW) { 958 struct intel_encoder *encoder; 959 960 for_each_intel_encoder_with_psr(display->drm, encoder) { 961 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 962 u32 psr_iir; 963 964 psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0); 965 intel_psr_irq_handler(intel_dp, psr_iir); 966 break; 967 } 968 } 969 970 if (de_iir & DE_AUX_CHANNEL_A_IVB) 971 intel_dp_aux_irq_handler(display); 972 973 if (de_iir & DE_GSE_IVB) 974 intel_opregion_asle_intr(display); 975 976 for_each_pipe(display, pipe) { 977 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 978 intel_handle_vblank(display, pipe); 979 980 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) 981 flip_done_handler(display, pipe); 982 } 983 984 /* check event from PCH */ 985 if (!HAS_PCH_NOP(display) && (de_iir & DE_PCH_EVENT_IVB)) { 986 u32 pch_iir = intel_de_read(display, SDEIIR); 987 988 cpt_irq_handler(display, pch_iir); 989 990 /* clear PCH hotplug event before clear CPU irq */ 991 intel_de_write(display, SDEIIR, pch_iir); 992 } 993 } 994 995 void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier) 996 { 997 /* disable master interrupt before clearing iir */ 998 *de_ier = intel_de_read_fw(display, DEIER); 999 intel_de_write_fw(display, DEIER, *de_ier & ~DE_MASTER_IRQ_CONTROL); 1000 1001 /* 1002 * Disable south interrupts. We'll only write to SDEIIR once, so further 1003 * interrupts will be stored on its back queue, and then we'll be able 1004 * to process them after we restore SDEIER (as soon as we restore it, 1005 * we'll get an interrupt if SDEIIR still has something to process due 1006 * to its back queue). 1007 */ 1008 if (!HAS_PCH_NOP(display)) { 1009 *sde_ier = intel_de_read_fw(display, SDEIER); 1010 intel_de_write_fw(display, SDEIER, 0); 1011 } else { 1012 *sde_ier = 0; 1013 } 1014 } 1015 1016 void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier) 1017 { 1018 intel_de_write_fw(display, DEIER, de_ier); 1019 1020 if (sde_ier) 1021 intel_de_write_fw(display, SDEIER, sde_ier); 1022 } 1023 1024 static bool ilk_display_irq_handler(struct intel_display *display, 1025 const struct intel_display_irq_state *state) 1026 { 1027 u32 de_iir; 1028 bool handled = false; 1029 1030 de_iir = intel_de_read_fw(display, DEIIR); 1031 if (de_iir) { 1032 intel_de_write_fw(display, DEIIR, de_iir); 1033 if (DISPLAY_VER(display) >= 7) 1034 _ivb_display_irq_handler(display, de_iir); 1035 else 1036 _ilk_display_irq_handler(display, de_iir); 1037 handled = true; 1038 } 1039 1040 return handled; 1041 } 1042 1043 static u32 gen8_de_port_aux_mask(struct intel_display *display) 1044 { 1045 u32 mask; 1046 1047 if (DISPLAY_VER(display) >= 20) 1048 return 0; 1049 else if (DISPLAY_VER(display) >= 14) 1050 return TGL_DE_PORT_AUX_DDIA | 1051 TGL_DE_PORT_AUX_DDIB; 1052 else if (DISPLAY_VER(display) >= 13) 1053 return TGL_DE_PORT_AUX_DDIA | 1054 TGL_DE_PORT_AUX_DDIB | 1055 TGL_DE_PORT_AUX_DDIC | 1056 XELPD_DE_PORT_AUX_DDID | 1057 XELPD_DE_PORT_AUX_DDIE | 1058 TGL_DE_PORT_AUX_USBC1 | 1059 TGL_DE_PORT_AUX_USBC2 | 1060 TGL_DE_PORT_AUX_USBC3 | 1061 TGL_DE_PORT_AUX_USBC4; 1062 else if (DISPLAY_VER(display) >= 12) 1063 return TGL_DE_PORT_AUX_DDIA | 1064 TGL_DE_PORT_AUX_DDIB | 1065 TGL_DE_PORT_AUX_DDIC | 1066 TGL_DE_PORT_AUX_USBC1 | 1067 TGL_DE_PORT_AUX_USBC2 | 1068 TGL_DE_PORT_AUX_USBC3 | 1069 TGL_DE_PORT_AUX_USBC4 | 1070 TGL_DE_PORT_AUX_USBC5 | 1071 TGL_DE_PORT_AUX_USBC6; 1072 1073 mask = GEN8_AUX_CHANNEL_A; 1074 if (DISPLAY_VER(display) >= 9) 1075 mask |= GEN9_AUX_CHANNEL_B | 1076 GEN9_AUX_CHANNEL_C | 1077 GEN9_AUX_CHANNEL_D; 1078 1079 if (DISPLAY_VER(display) == 11) { 1080 mask |= ICL_AUX_CHANNEL_F; 1081 mask |= ICL_AUX_CHANNEL_E; 1082 } 1083 1084 return mask; 1085 } 1086 1087 static u32 gen8_de_pipe_fault_mask(struct intel_display *display) 1088 { 1089 if (DISPLAY_VER(display) >= 20) 1090 return MTL_PLANE_ATS_FAULT | 1091 GEN9_PIPE_CURSOR_FAULT | 1092 GEN11_PIPE_PLANE5_FAULT | 1093 GEN9_PIPE_PLANE4_FAULT | 1094 GEN9_PIPE_PLANE3_FAULT | 1095 GEN9_PIPE_PLANE2_FAULT | 1096 GEN9_PIPE_PLANE1_FAULT; 1097 else if (DISPLAY_VER(display) >= 14) 1098 return MTL_PIPEDMC_ATS_FAULT | 1099 MTL_PLANE_ATS_FAULT | 1100 GEN12_PIPEDMC_FAULT | 1101 GEN9_PIPE_CURSOR_FAULT | 1102 GEN11_PIPE_PLANE5_FAULT | 1103 GEN9_PIPE_PLANE4_FAULT | 1104 GEN9_PIPE_PLANE3_FAULT | 1105 GEN9_PIPE_PLANE2_FAULT | 1106 GEN9_PIPE_PLANE1_FAULT; 1107 else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 1108 return GEN12_PIPEDMC_FAULT | 1109 GEN9_PIPE_CURSOR_FAULT | 1110 GEN11_PIPE_PLANE5_FAULT | 1111 GEN9_PIPE_PLANE4_FAULT | 1112 GEN9_PIPE_PLANE3_FAULT | 1113 GEN9_PIPE_PLANE2_FAULT | 1114 GEN9_PIPE_PLANE1_FAULT; 1115 else if (DISPLAY_VER(display) == 12) 1116 return GEN12_PIPEDMC_FAULT | 1117 GEN9_PIPE_CURSOR_FAULT | 1118 GEN11_PIPE_PLANE7_FAULT | 1119 GEN11_PIPE_PLANE6_FAULT | 1120 GEN11_PIPE_PLANE5_FAULT | 1121 GEN9_PIPE_PLANE4_FAULT | 1122 GEN9_PIPE_PLANE3_FAULT | 1123 GEN9_PIPE_PLANE2_FAULT | 1124 GEN9_PIPE_PLANE1_FAULT; 1125 else if (DISPLAY_VER(display) == 11) 1126 return GEN9_PIPE_CURSOR_FAULT | 1127 GEN11_PIPE_PLANE7_FAULT | 1128 GEN11_PIPE_PLANE6_FAULT | 1129 GEN11_PIPE_PLANE5_FAULT | 1130 GEN9_PIPE_PLANE4_FAULT | 1131 GEN9_PIPE_PLANE3_FAULT | 1132 GEN9_PIPE_PLANE2_FAULT | 1133 GEN9_PIPE_PLANE1_FAULT; 1134 else if (DISPLAY_VER(display) >= 9) 1135 return GEN9_PIPE_CURSOR_FAULT | 1136 GEN9_PIPE_PLANE4_FAULT | 1137 GEN9_PIPE_PLANE3_FAULT | 1138 GEN9_PIPE_PLANE2_FAULT | 1139 GEN9_PIPE_PLANE1_FAULT; 1140 else 1141 return GEN8_PIPE_CURSOR_FAULT | 1142 GEN8_PIPE_SPRITE_FAULT | 1143 GEN8_PIPE_PRIMARY_FAULT; 1144 } 1145 1146 static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) 1147 { 1148 struct intel_display *display = to_intel_display(crtc); 1149 1150 drm_err_ratelimited(display->drm, 1151 "[CRTC:%d:%s] PLANE ATS fault\n", 1152 crtc->base.base.id, crtc->base.name); 1153 1154 return true; 1155 } 1156 1157 static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) 1158 { 1159 struct intel_display *display = to_intel_display(crtc); 1160 1161 drm_err_ratelimited(display->drm, 1162 "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1163 crtc->base.base.id, crtc->base.name); 1164 1165 return true; 1166 } 1167 1168 static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id) 1169 { 1170 struct intel_display *display = to_intel_display(crtc); 1171 1172 drm_err_ratelimited(display->drm, 1173 "[CRTC:%d:%s] PIPEDMC fault\n", 1174 crtc->base.base.id, crtc->base.name); 1175 1176 return true; 1177 } 1178 1179 static const struct pipe_fault_handler mtl_pipe_fault_handlers[] = { 1180 { .fault = MTL_PLANE_ATS_FAULT, .handle = handle_plane_ats_fault, }, 1181 { .fault = MTL_PIPEDMC_ATS_FAULT, .handle = handle_pipedmc_ats_fault, }, 1182 { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, 1183 { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, 1184 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1185 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1186 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1187 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1188 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1189 {} 1190 }; 1191 1192 static const struct pipe_fault_handler tgl_pipe_fault_handlers[] = { 1193 { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, 1194 { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, 1195 { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, 1196 { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, 1197 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1198 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1199 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1200 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1201 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1202 {} 1203 }; 1204 1205 static const struct pipe_fault_handler icl_pipe_fault_handlers[] = { 1206 { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, 1207 { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, 1208 { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, 1209 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1210 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1211 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1212 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1213 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1214 {} 1215 }; 1216 1217 static const struct pipe_fault_handler skl_pipe_fault_handlers[] = { 1218 { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, 1219 { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, 1220 { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, 1221 { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, 1222 { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1223 {} 1224 }; 1225 1226 static const struct pipe_fault_handler bdw_pipe_fault_handlers[] = { 1227 { .fault = GEN8_PIPE_SPRITE_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1228 { .fault = GEN8_PIPE_PRIMARY_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1229 { .fault = GEN8_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1230 {} 1231 }; 1232 1233 static const struct pipe_fault_handler * 1234 gen8_pipe_fault_handlers(struct intel_display *display) 1235 { 1236 if (DISPLAY_VER(display) >= 14) 1237 return mtl_pipe_fault_handlers; 1238 else if (DISPLAY_VER(display) >= 12) 1239 return tgl_pipe_fault_handlers; 1240 else if (DISPLAY_VER(display) >= 11) 1241 return icl_pipe_fault_handlers; 1242 else if (DISPLAY_VER(display) >= 9) 1243 return skl_pipe_fault_handlers; 1244 else 1245 return bdw_pipe_fault_handlers; 1246 } 1247 1248 static void intel_pmdemand_irq_handler(struct intel_display *display) 1249 { 1250 wake_up_all(&display->pmdemand.waitqueue); 1251 } 1252 1253 static void 1254 gen8_de_misc_irq_handler(struct intel_display *display, u32 iir) 1255 { 1256 bool found = false; 1257 1258 if (HAS_DBUF_OVERLAP_DETECTION(display)) { 1259 if (iir & XE2LPD_DBUF_OVERLAP_DETECTED) { 1260 drm_warn(display->drm, "DBuf overlap detected\n"); 1261 found = true; 1262 } 1263 } 1264 1265 if (DISPLAY_VER(display) >= 14) { 1266 if (iir & (XELPDP_PMDEMAND_RSP | 1267 XELPDP_PMDEMAND_RSPTOUT_ERR)) { 1268 if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) 1269 drm_dbg(display->drm, 1270 "Error waiting for Punit PM Demand Response\n"); 1271 1272 intel_pmdemand_irq_handler(display); 1273 found = true; 1274 } 1275 1276 if (iir & XELPDP_RM_TIMEOUT) { 1277 u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE); 1278 drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val); 1279 found = true; 1280 } 1281 } else if (iir & GEN8_DE_MISC_GSE) { 1282 intel_opregion_asle_intr(display); 1283 found = true; 1284 } 1285 1286 if (iir & GEN8_DE_EDP_PSR) { 1287 struct intel_encoder *encoder; 1288 u32 psr_iir; 1289 intel_reg_t iir_reg; 1290 1291 for_each_intel_encoder_with_psr(display->drm, encoder) { 1292 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1293 1294 if (DISPLAY_VER(display) >= 12) 1295 iir_reg = TRANS_PSR_IIR(display, 1296 intel_dp->psr.transcoder); 1297 else 1298 iir_reg = EDP_PSR_IIR; 1299 1300 psr_iir = intel_de_rmw(display, iir_reg, 0, 0); 1301 1302 if (psr_iir) 1303 found = true; 1304 1305 intel_psr_irq_handler(intel_dp, psr_iir); 1306 1307 /* prior GEN12 only have one EDP PSR */ 1308 if (DISPLAY_VER(display) < 12) 1309 break; 1310 } 1311 } 1312 1313 if (!found) 1314 drm_err(display->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir); 1315 } 1316 1317 static void gen11_dsi_te_interrupt_handler(struct intel_display *display, 1318 u32 te_trigger) 1319 { 1320 enum pipe pipe = INVALID_PIPE; 1321 enum transcoder dsi_trans; 1322 enum port port; 1323 u32 val; 1324 1325 /* 1326 * Incase of dual link, TE comes from DSI_1 1327 * this is to check if dual link is enabled 1328 */ 1329 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0)); 1330 val &= PORT_SYNC_MODE_ENABLE; 1331 1332 /* 1333 * if dual link is enabled, then read DSI_0 1334 * transcoder registers 1335 */ 1336 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 1337 PORT_A : PORT_B; 1338 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 1339 1340 /* Check if DSI configured in command mode */ 1341 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1342 val = val & OP_MODE_MASK; 1343 1344 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 1345 drm_err(display->drm, "DSI trancoder not configured in command mode\n"); 1346 return; 1347 } 1348 1349 /* Get PIPE for handling VBLANK event */ 1350 val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1351 switch (val & TRANS_DDI_EDP_INPUT_MASK) { 1352 case TRANS_DDI_EDP_INPUT_A_ON: 1353 pipe = PIPE_A; 1354 break; 1355 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1356 pipe = PIPE_B; 1357 break; 1358 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1359 pipe = PIPE_C; 1360 break; 1361 default: 1362 drm_err(display->drm, "Invalid PIPE\n"); 1363 return; 1364 } 1365 1366 intel_handle_vblank(display, pipe); 1367 1368 /* clear TE in dsi IIR */ 1369 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 1370 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); 1371 } 1372 1373 static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display) 1374 { 1375 if (DISPLAY_VER(display) >= 9) 1376 return GEN9_PIPE_PLANE1_FLIP_DONE; 1377 else 1378 return GEN8_PIPE_PRIMARY_FLIP_DONE; 1379 } 1380 1381 static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir) 1382 { 1383 u32 pica_ier = 0; 1384 1385 *pica_iir = 0; 1386 *pch_iir = intel_de_read(display, SDEIIR); 1387 if (!*pch_iir) 1388 return; 1389 1390 /** 1391 * PICA IER must be disabled/re-enabled around clearing PICA IIR and 1392 * SDEIIR, to avoid losing PICA IRQs and to ensure that such IRQs set 1393 * their flags both in the PICA and SDE IIR. 1394 */ 1395 if (*pch_iir & SDE_PICAINTERRUPT) { 1396 drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL); 1397 1398 pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0); 1399 *pica_iir = intel_de_read(display, PICAINTERRUPT_IIR); 1400 intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir); 1401 } 1402 1403 intel_de_write(display, SDEIIR, *pch_iir); 1404 1405 if (pica_ier) 1406 intel_de_write(display, PICAINTERRUPT_IER, pica_ier); 1407 } 1408 1409 static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) 1410 { 1411 u32 iir; 1412 enum pipe pipe; 1413 1414 drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display)); 1415 1416 if (master_ctl & GEN8_DE_MISC_IRQ) { 1417 iir = intel_de_read(display, GEN8_DE_MISC_IIR); 1418 if (iir) { 1419 intel_de_write(display, GEN8_DE_MISC_IIR, iir); 1420 gen8_de_misc_irq_handler(display, iir); 1421 } else { 1422 drm_err_ratelimited(display->drm, 1423 "The master control interrupt lied (DE MISC)!\n"); 1424 } 1425 } 1426 1427 if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 1428 iir = intel_de_read(display, GEN11_DE_HPD_IIR); 1429 if (iir) { 1430 intel_de_write(display, GEN11_DE_HPD_IIR, iir); 1431 gen11_hpd_irq_handler(display, iir); 1432 } else { 1433 drm_err_ratelimited(display->drm, 1434 "The master control interrupt lied, (DE HPD)!\n"); 1435 } 1436 } 1437 1438 if (master_ctl & GEN8_DE_PORT_IRQ) { 1439 iir = intel_de_read(display, GEN8_DE_PORT_IIR); 1440 if (iir) { 1441 bool found = false; 1442 1443 intel_de_write(display, GEN8_DE_PORT_IIR, iir); 1444 1445 if (iir & gen8_de_port_aux_mask(display)) { 1446 intel_dp_aux_irq_handler(display); 1447 found = true; 1448 } 1449 1450 if (display->platform.geminilake || display->platform.broxton) { 1451 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 1452 1453 if (hotplug_trigger) { 1454 bxt_hpd_irq_handler(display, hotplug_trigger); 1455 found = true; 1456 } 1457 } else if (display->platform.broadwell) { 1458 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 1459 1460 if (hotplug_trigger) { 1461 ilk_hpd_irq_handler(display, hotplug_trigger); 1462 found = true; 1463 } 1464 } 1465 1466 if ((display->platform.geminilake || display->platform.broxton) && 1467 (iir & BXT_DE_PORT_GMBUS)) { 1468 intel_gmbus_irq_handler(display); 1469 found = true; 1470 } 1471 1472 if (DISPLAY_VER(display) >= 11) { 1473 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 1474 1475 if (te_trigger) { 1476 gen11_dsi_te_interrupt_handler(display, te_trigger); 1477 found = true; 1478 } 1479 } 1480 1481 if (!found) 1482 drm_err_ratelimited(display->drm, 1483 "Unexpected DE Port interrupt\n"); 1484 } else { 1485 drm_err_ratelimited(display->drm, 1486 "The master control interrupt lied (DE PORT)!\n"); 1487 } 1488 } 1489 1490 for_each_pipe(display, pipe) { 1491 u32 fault_errors; 1492 1493 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1494 continue; 1495 1496 iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe)); 1497 if (!iir) { 1498 drm_err_ratelimited(display->drm, 1499 "The master control interrupt lied (DE PIPE %c)!\n", 1500 pipe_name(pipe)); 1501 continue; 1502 } 1503 1504 intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir); 1505 1506 if (iir & GEN8_PIPE_VBLANK) 1507 intel_handle_vblank(display, pipe); 1508 1509 if (iir & gen8_de_pipe_flip_done_mask(display)) 1510 flip_done_handler(display, pipe); 1511 1512 if (HAS_DSB(display)) { 1513 if (iir & GEN12_DSB_INT(INTEL_DSB_0)) 1514 intel_dsb_irq_handler(display, pipe, INTEL_DSB_0); 1515 1516 if (iir & GEN12_DSB_INT(INTEL_DSB_1)) 1517 intel_dsb_irq_handler(display, pipe, INTEL_DSB_1); 1518 1519 if (iir & GEN12_DSB_INT(INTEL_DSB_2)) 1520 intel_dsb_irq_handler(display, pipe, INTEL_DSB_2); 1521 } 1522 1523 if (HAS_PIPEDMC(display) && iir & GEN12_PIPEDMC_INTERRUPT) 1524 intel_pipedmc_irq_handler(display, pipe); 1525 1526 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 1527 hsw_pipe_crc_irq_handler(display, pipe); 1528 1529 if (iir & GEN8_PIPE_FIFO_UNDERRUN) 1530 intel_cpu_fifo_underrun_irq_handler(display, pipe); 1531 1532 fault_errors = iir & gen8_de_pipe_fault_mask(display); 1533 if (fault_errors) 1534 intel_pipe_fault_irq_handler(display, 1535 gen8_pipe_fault_handlers(display), 1536 pipe, fault_errors); 1537 } 1538 1539 if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) && 1540 master_ctl & GEN8_DE_PCH_IRQ) { 1541 u32 pica_iir; 1542 1543 /* 1544 * FIXME(BDW): Assume for now that the new interrupt handling 1545 * scheme also closed the SDE interrupt handling race we've seen 1546 * on older pch-split platforms. But this needs testing. 1547 */ 1548 gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir); 1549 if (iir) { 1550 if (pica_iir) 1551 xelpdp_pica_irq_handler(display, pica_iir); 1552 1553 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 1554 icp_irq_handler(display, iir); 1555 else if (INTEL_PCH_TYPE(display) >= PCH_SPT) 1556 spt_irq_handler(display, iir); 1557 else 1558 cpt_irq_handler(display, iir); 1559 } else { 1560 /* 1561 * Like on previous PCH there seems to be something 1562 * fishy going on with forwarding PCH interrupts. 1563 */ 1564 drm_dbg(display->drm, 1565 "The master control interrupt lied (SDE)!\n"); 1566 } 1567 } 1568 } 1569 1570 static bool gen8_display_irq_handler(struct intel_display *display, 1571 const struct intel_display_irq_state *state) 1572 { 1573 gen8_de_irq_handler(display, state->master_ctl); 1574 1575 return true; 1576 } 1577 1578 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl) 1579 { 1580 u32 iir; 1581 1582 if (!(master_ctl & GEN11_GU_MISC_IRQ)) 1583 return 0; 1584 1585 intel_display_rpm_assert_block(display); 1586 1587 iir = intel_de_read(display, GEN11_GU_MISC_IIR); 1588 if (likely(iir)) 1589 intel_de_write(display, GEN11_GU_MISC_IIR, iir); 1590 1591 intel_display_rpm_assert_unblock(display); 1592 1593 return iir; 1594 } 1595 1596 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir) 1597 { 1598 if (iir & GEN11_GU_MISC_GSE) 1599 intel_opregion_asle_intr(display); 1600 } 1601 1602 static bool gen11_display_irq_handler(struct intel_display *display, 1603 const struct intel_display_irq_state *state) 1604 { 1605 u32 disp_ctl; 1606 1607 intel_display_rpm_assert_block(display); 1608 /* 1609 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 1610 * for the display related bits. 1611 */ 1612 disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL); 1613 1614 intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); 1615 gen8_de_irq_handler(display, disp_ctl); 1616 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 1617 1618 intel_display_rpm_assert_unblock(display); 1619 1620 return true; 1621 } 1622 1623 static void i915gm_irq_cstate_wa_enable(struct intel_display *display) 1624 { 1625 lockdep_assert_held(&display->drm->vblank_time_lock); 1626 1627 /* 1628 * Vblank/CRC interrupts fail to wake the device up from C2+. 1629 * Disabling render clock gating during C-states avoids 1630 * the problem. There is a small power cost so we do this 1631 * only when vblank/CRC interrupts are actually enabled. 1632 */ 1633 if (display->irq.vblank_enabled++ == 0) 1634 intel_de_write(display, SCPD0, 1635 REG_MASKED_FIELD_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1636 } 1637 1638 static void i915gm_irq_cstate_wa_disable(struct intel_display *display) 1639 { 1640 lockdep_assert_held(&display->drm->vblank_time_lock); 1641 1642 if (--display->irq.vblank_enabled == 0) 1643 intel_de_write(display, SCPD0, 1644 REG_MASKED_FIELD_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1645 } 1646 1647 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable) 1648 { 1649 spin_lock_irq(&display->drm->vblank_time_lock); 1650 1651 if (enable) 1652 i915gm_irq_cstate_wa_enable(display); 1653 else 1654 i915gm_irq_cstate_wa_disable(display); 1655 1656 spin_unlock_irq(&display->drm->vblank_time_lock); 1657 } 1658 1659 int i8xx_enable_vblank(struct drm_crtc *crtc) 1660 { 1661 struct intel_display *display = to_intel_display(crtc->dev); 1662 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1663 unsigned long irqflags; 1664 1665 spin_lock_irqsave(&display->irq.lock, irqflags); 1666 i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1667 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1668 1669 return 0; 1670 } 1671 1672 void i8xx_disable_vblank(struct drm_crtc *crtc) 1673 { 1674 struct intel_display *display = to_intel_display(crtc->dev); 1675 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1676 unsigned long irqflags; 1677 1678 spin_lock_irqsave(&display->irq.lock, irqflags); 1679 i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1680 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1681 } 1682 1683 int i915gm_enable_vblank(struct drm_crtc *crtc) 1684 { 1685 struct intel_display *display = to_intel_display(crtc->dev); 1686 1687 i915gm_irq_cstate_wa_enable(display); 1688 1689 return i8xx_enable_vblank(crtc); 1690 } 1691 1692 void i915gm_disable_vblank(struct drm_crtc *crtc) 1693 { 1694 struct intel_display *display = to_intel_display(crtc->dev); 1695 1696 i8xx_disable_vblank(crtc); 1697 1698 i915gm_irq_cstate_wa_disable(display); 1699 } 1700 1701 int i965_enable_vblank(struct drm_crtc *crtc) 1702 { 1703 struct intel_display *display = to_intel_display(crtc->dev); 1704 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1705 unsigned long irqflags; 1706 1707 spin_lock_irqsave(&display->irq.lock, irqflags); 1708 i915_enable_pipestat(display, pipe, 1709 PIPE_START_VBLANK_INTERRUPT_STATUS); 1710 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1711 1712 return 0; 1713 } 1714 1715 void i965_disable_vblank(struct drm_crtc *crtc) 1716 { 1717 struct intel_display *display = to_intel_display(crtc->dev); 1718 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1719 unsigned long irqflags; 1720 1721 spin_lock_irqsave(&display->irq.lock, irqflags); 1722 i915_disable_pipestat(display, pipe, 1723 PIPE_START_VBLANK_INTERRUPT_STATUS); 1724 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1725 } 1726 1727 int ilk_enable_vblank(struct drm_crtc *crtc) 1728 { 1729 struct intel_display *display = to_intel_display(crtc->dev); 1730 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1731 unsigned long irqflags; 1732 u32 bit = DISPLAY_VER(display) >= 7 ? 1733 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1734 1735 spin_lock_irqsave(&display->irq.lock, irqflags); 1736 ilk_enable_display_irq(display, bit); 1737 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1738 1739 /* Even though there is no DMC, frame counter can get stuck when 1740 * PSR is active as no frames are generated. 1741 */ 1742 if (HAS_PSR(display)) 1743 drm_crtc_vblank_restore(crtc); 1744 1745 return 0; 1746 } 1747 1748 void ilk_disable_vblank(struct drm_crtc *crtc) 1749 { 1750 struct intel_display *display = to_intel_display(crtc->dev); 1751 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1752 unsigned long irqflags; 1753 u32 bit = DISPLAY_VER(display) >= 7 ? 1754 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1755 1756 spin_lock_irqsave(&display->irq.lock, irqflags); 1757 ilk_disable_display_irq(display, bit); 1758 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1759 } 1760 1761 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 1762 bool enable) 1763 { 1764 struct intel_display *display = to_intel_display(intel_crtc); 1765 enum port port; 1766 1767 if (!(intel_crtc->mode_flags & 1768 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 1769 return false; 1770 1771 /* for dual link cases we consider TE from slave */ 1772 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 1773 port = PORT_B; 1774 else 1775 port = PORT_A; 1776 1777 intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT); 1778 1779 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); 1780 1781 return true; 1782 } 1783 1784 static void intel_display_vblank_notify_work(struct work_struct *work) 1785 { 1786 struct intel_display *display = 1787 container_of(work, typeof(*display), irq.vblank_notify_work); 1788 int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count); 1789 bool vblank_status = !!vblank_enable_count; 1790 1791 if (display->irq.vblank_status_last_notified != vblank_status) { 1792 intel_psr_notify_vblank_enable_disable(display, vblank_status); 1793 display->irq.vblank_status_last_notified = vblank_status; 1794 } 1795 } 1796 1797 int bdw_enable_vblank(struct drm_crtc *_crtc) 1798 { 1799 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1800 struct intel_display *display = to_intel_display(crtc); 1801 enum pipe pipe = crtc->pipe; 1802 unsigned long irqflags; 1803 1804 if (gen11_dsi_configure_te(crtc, true)) 1805 return 0; 1806 1807 spin_lock_irqsave(&display->irq.lock, irqflags); 1808 if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0) 1809 schedule_work(&display->irq.vblank_notify_work); 1810 1811 bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK); 1812 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1813 1814 /* Even if there is no DMC, frame counter can get stuck when 1815 * PSR is active as no frames are generated, so check only for PSR. 1816 */ 1817 if (HAS_PSR(display)) 1818 drm_crtc_vblank_restore(&crtc->base); 1819 1820 return 0; 1821 } 1822 1823 void bdw_disable_vblank(struct drm_crtc *_crtc) 1824 { 1825 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1826 struct intel_display *display = to_intel_display(crtc); 1827 enum pipe pipe = crtc->pipe; 1828 unsigned long irqflags; 1829 1830 if (gen11_dsi_configure_te(crtc, false)) 1831 return; 1832 1833 spin_lock_irqsave(&display->irq.lock, irqflags); 1834 bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK); 1835 spin_unlock_irqrestore(&display->irq.lock, irqflags); 1836 1837 if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0) 1838 schedule_work(&display->irq.vblank_notify_work); 1839 } 1840 1841 static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) 1842 { 1843 switch (pipe) { 1844 case PIPE_A: 1845 return SPRITEB_INVALID_GTT_STATUS | 1846 SPRITEA_INVALID_GTT_STATUS | 1847 PLANEA_INVALID_GTT_STATUS | 1848 CURSORA_INVALID_GTT_STATUS; 1849 case PIPE_B: 1850 return SPRITED_INVALID_GTT_STATUS | 1851 SPRITEC_INVALID_GTT_STATUS | 1852 PLANEB_INVALID_GTT_STATUS | 1853 CURSORB_INVALID_GTT_STATUS; 1854 case PIPE_C: 1855 return SPRITEF_INVALID_GTT_STATUS | 1856 SPRITEE_INVALID_GTT_STATUS | 1857 PLANEC_INVALID_GTT_STATUS | 1858 CURSORC_INVALID_GTT_STATUS; 1859 default: 1860 return 0; 1861 } 1862 } 1863 1864 static const struct pipe_fault_handler vlv_pipe_fault_handlers[] = { 1865 { .fault = SPRITEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, 1866 { .fault = SPRITEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1867 { .fault = PLANEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1868 { .fault = CURSORA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1869 { .fault = SPRITED_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, 1870 { .fault = SPRITEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1871 { .fault = PLANEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1872 { .fault = CURSORB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1873 { .fault = SPRITEF_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, 1874 { .fault = SPRITEE_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, 1875 { .fault = PLANEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, 1876 { .fault = CURSORC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, 1877 {} 1878 }; 1879 1880 static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt) 1881 { 1882 u32 status, enable, tmp; 1883 1884 tmp = intel_de_read(display, DPINVGTT); 1885 1886 enable = tmp >> 16; 1887 status = tmp & 0xffff; 1888 1889 /* 1890 * Despite what the docs claim, the status bits seem to get 1891 * stuck permanently (similar the old PGTBL_ER register), so 1892 * we have to disable and ignore them once set. They do get 1893 * reset if the display power well goes down, so no need to 1894 * track the enable mask explicitly. 1895 */ 1896 *dpinvgtt = status & enable; 1897 enable &= ~status; 1898 1899 /* customary ack+disable then re-enable to guarantee an edge */ 1900 intel_de_write(display, DPINVGTT, status); 1901 intel_de_write(display, DPINVGTT, enable << 16); 1902 } 1903 1904 static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt) 1905 { 1906 enum pipe pipe; 1907 1908 for_each_pipe(display, pipe) { 1909 u32 fault_errors; 1910 1911 fault_errors = dpinvgtt & vlv_dpinvgtt_pipe_fault_mask(pipe); 1912 if (fault_errors) 1913 intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers, 1914 pipe, fault_errors); 1915 } 1916 } 1917 1918 static void vlv_display_error_irq_ack(struct intel_display *display, 1919 u32 *eir, u32 *dpinvgtt) 1920 { 1921 u32 emr; 1922 1923 *eir = intel_de_read(display, VLV_EIR); 1924 1925 if (*eir & VLV_ERROR_PAGE_TABLE) 1926 vlv_page_table_error_irq_ack(display, dpinvgtt); 1927 1928 intel_de_write(display, VLV_EIR, *eir); 1929 1930 /* 1931 * Toggle all EMR bits to make sure we get an edge 1932 * in the ISR master error bit if we don't clear 1933 * all the EIR bits. 1934 */ 1935 emr = intel_de_read(display, VLV_EMR); 1936 intel_de_write(display, VLV_EMR, 0xffffffff); 1937 intel_de_write(display, VLV_EMR, emr); 1938 } 1939 1940 static void vlv_display_error_irq_handler(struct intel_display *display, 1941 u32 eir, u32 dpinvgtt) 1942 { 1943 drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir); 1944 1945 if (eir & VLV_ERROR_PAGE_TABLE) 1946 vlv_page_table_error_irq_handler(display, dpinvgtt); 1947 } 1948 1949 static void _vlv_display_irq_reset(struct intel_display *display) 1950 { 1951 if (display->platform.cherryview) 1952 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 1953 else 1954 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1955 1956 error_reset(display, VLV_ERROR_REGS); 1957 1958 i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0); 1959 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); 1960 1961 i9xx_pipestat_irq_reset(display); 1962 1963 irq_reset(display, VLV_IRQ_REGS); 1964 display->irq.vlv_imr_mask = ~0u; 1965 } 1966 1967 static void vlv_display_irq_reset(struct intel_display *display) 1968 { 1969 spin_lock_irq(&display->irq.lock); 1970 if (display->irq.vlv_display_irqs_enabled) 1971 _vlv_display_irq_reset(display); 1972 spin_unlock_irq(&display->irq.lock); 1973 } 1974 1975 static void i9xx_display_irq_reset(struct intel_display *display) 1976 { 1977 if (HAS_HOTPLUG(display)) { 1978 i915_hotplug_interrupt_update(display, 0xffffffff, 0); 1979 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); 1980 } 1981 1982 i9xx_pipestat_irq_reset(display); 1983 } 1984 1985 u32 i9xx_display_irq_enable_mask(struct intel_display *display) 1986 { 1987 u32 enable_mask; 1988 1989 enable_mask = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1990 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 1991 1992 if (DISPLAY_VER(display) >= 3) 1993 enable_mask |= I915_ASLE_INTERRUPT; 1994 1995 if (HAS_HOTPLUG(display)) 1996 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1997 1998 return enable_mask; 1999 } 2000 2001 static void i915_display_irq_postinstall(struct intel_display *display) 2002 { 2003 /* 2004 * Interrupt setup is already guaranteed to be single-threaded, this is 2005 * just to make the assert_spin_locked check happy. 2006 */ 2007 spin_lock_irq(&display->irq.lock); 2008 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 2009 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 2010 spin_unlock_irq(&display->irq.lock); 2011 2012 i915_enable_asle_pipestat(display); 2013 } 2014 2015 static void i965_display_irq_postinstall(struct intel_display *display) 2016 { 2017 /* 2018 * Interrupt setup is already guaranteed to be single-threaded, this is 2019 * just to make the assert_spin_locked check happy. 2020 */ 2021 spin_lock_irq(&display->irq.lock); 2022 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 2023 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 2024 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 2025 spin_unlock_irq(&display->irq.lock); 2026 2027 i915_enable_asle_pipestat(display); 2028 } 2029 2030 static void i9xx_display_irq_ack(struct intel_display *display, 2031 struct intel_display_irq_state *state) 2032 { 2033 if (state->iir & I915_DISPLAY_PORT_INTERRUPT) 2034 state->hotplug_status = i9xx_hpd_irq_ack(display); 2035 2036 /* Call regardless, as some status bits might not be signalled in IIR */ 2037 i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats); 2038 } 2039 2040 static bool i965_display_irq_handler(struct intel_display *display, 2041 const struct intel_display_irq_state *state) 2042 { 2043 if (state->hotplug_status) 2044 i9xx_hpd_irq_handler(display, state->hotplug_status); 2045 2046 i965_pipestat_irq_handler(display, state->iir, state->pipe_stats); 2047 2048 return true; 2049 } 2050 2051 static bool i915_display_irq_handler(struct intel_display *display, 2052 const struct intel_display_irq_state *state) 2053 { 2054 if (state->hotplug_status) 2055 i9xx_hpd_irq_handler(display, state->hotplug_status); 2056 2057 i915_pipestat_irq_handler(display, state->iir, state->pipe_stats); 2058 2059 return true; 2060 } 2061 2062 static u32 vlv_error_mask(void) 2063 { 2064 /* TODO enable other errors too? */ 2065 return VLV_ERROR_PAGE_TABLE; 2066 } 2067 2068 static void _vlv_display_irq_postinstall(struct intel_display *display) 2069 { 2070 u32 pipestat_mask; 2071 u32 enable_mask; 2072 enum pipe pipe; 2073 2074 if (display->platform.cherryview) 2075 intel_de_write(display, DPINVGTT, 2076 DPINVGTT_STATUS_MASK_CHV | 2077 DPINVGTT_EN_MASK_CHV); 2078 else 2079 intel_de_write(display, DPINVGTT, 2080 DPINVGTT_STATUS_MASK_VLV | 2081 DPINVGTT_EN_MASK_VLV); 2082 2083 error_init(display, VLV_ERROR_REGS, ~vlv_error_mask()); 2084 2085 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 2086 2087 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 2088 for_each_pipe(display, pipe) 2089 i915_enable_pipestat(display, pipe, pipestat_mask); 2090 2091 enable_mask = I915_DISPLAY_PORT_INTERRUPT | 2092 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2093 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2094 I915_LPE_PIPE_A_INTERRUPT | 2095 I915_LPE_PIPE_B_INTERRUPT | 2096 I915_MASTER_ERROR_INTERRUPT; 2097 2098 if (display->platform.cherryview) 2099 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 2100 I915_LPE_PIPE_C_INTERRUPT; 2101 2102 drm_WARN_ON(display->drm, display->irq.vlv_imr_mask != ~0u); 2103 2104 display->irq.vlv_imr_mask = ~enable_mask; 2105 2106 irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); 2107 } 2108 2109 static void vlv_display_irq_postinstall(struct intel_display *display) 2110 { 2111 spin_lock_irq(&display->irq.lock); 2112 if (display->irq.vlv_display_irqs_enabled) 2113 _vlv_display_irq_postinstall(display); 2114 spin_unlock_irq(&display->irq.lock); 2115 } 2116 2117 static u32 vlv_lpe_irq_mask(struct intel_display *display) 2118 { 2119 if (display->platform.cherryview) 2120 return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT | 2121 I915_LPE_PIPE_C_INTERRUPT; 2122 else 2123 return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT; 2124 } 2125 2126 static void vlv_display_irq_ack(struct intel_display *display, 2127 struct intel_display_irq_state *state) 2128 { 2129 if (state->iir & I915_DISPLAY_PORT_INTERRUPT) 2130 state->hotplug_status = i9xx_hpd_irq_ack(display); 2131 2132 if (state->iir & I915_MASTER_ERROR_INTERRUPT) 2133 vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt); 2134 2135 /* Call regardless, as some status bits might not be signalled in IIR */ 2136 i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats); 2137 2138 /* The handler acks the irq, so need to call the handler here */ 2139 if (state->iir & vlv_lpe_irq_mask(display)) 2140 intel_lpe_audio_irq_handler(display); 2141 } 2142 2143 static bool vlv_display_irq_handler(struct intel_display *display, 2144 const struct intel_display_irq_state *state) 2145 { 2146 if (state->hotplug_status) 2147 i9xx_hpd_irq_handler(display, state->hotplug_status); 2148 2149 if (state->iir & I915_MASTER_ERROR_INTERRUPT) 2150 vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt); 2151 2152 valleyview_pipestat_irq_handler(display, state->pipe_stats); 2153 2154 return true; 2155 } 2156 2157 static void ibx_display_irq_reset(struct intel_display *display) 2158 { 2159 if (HAS_PCH_NOP(display)) 2160 return; 2161 2162 irq_reset(display, SDE_IRQ_REGS); 2163 2164 if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) 2165 intel_de_write(display, SERR_INT, 0xffffffff); 2166 } 2167 2168 static void ilk_display_irq_reset(struct intel_display *display) 2169 { 2170 irq_reset(display, DE_IRQ_REGS); 2171 display->irq.ilk_de_imr_mask = ~0u; 2172 2173 if (DISPLAY_VER(display) == 7) 2174 intel_de_write(display, GEN7_ERR_INT, 0xffffffff); 2175 2176 if (display->platform.haswell) { 2177 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); 2178 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); 2179 } 2180 2181 ibx_display_irq_reset(display); 2182 } 2183 2184 static void gen8_display_irq_reset(struct intel_display *display) 2185 { 2186 enum pipe pipe; 2187 2188 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); 2189 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); 2190 2191 for_each_pipe(display, pipe) 2192 if (intel_display_power_is_enabled(display, 2193 POWER_DOMAIN_PIPE(pipe))) 2194 irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2195 2196 irq_reset(display, GEN8_DE_PORT_IRQ_REGS); 2197 irq_reset(display, GEN8_DE_MISC_IRQ_REGS); 2198 2199 if (HAS_PCH_SPLIT(display)) 2200 ibx_display_irq_reset(display); 2201 } 2202 2203 static void gen11_display_irq_reset(struct intel_display *display) 2204 { 2205 enum pipe pipe; 2206 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 2207 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 2208 2209 intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); 2210 2211 if (DISPLAY_VER(display) >= 12) { 2212 enum transcoder trans; 2213 2214 for_each_cpu_transcoder_masked(display, trans, trans_mask) { 2215 enum intel_display_power_domain domain; 2216 2217 domain = POWER_DOMAIN_TRANSCODER(trans); 2218 if (!intel_display_power_is_enabled(display, domain)) 2219 continue; 2220 2221 intel_de_write(display, 2222 TRANS_PSR_IMR(display, trans), 2223 0xffffffff); 2224 intel_de_write(display, 2225 TRANS_PSR_IIR(display, trans), 2226 0xffffffff); 2227 } 2228 } else { 2229 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); 2230 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); 2231 } 2232 2233 for_each_pipe(display, pipe) 2234 if (intel_display_power_is_enabled(display, 2235 POWER_DOMAIN_PIPE(pipe))) 2236 irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2237 2238 irq_reset(display, GEN8_DE_PORT_IRQ_REGS); 2239 irq_reset(display, GEN8_DE_MISC_IRQ_REGS); 2240 2241 if (DISPLAY_VER(display) >= 14) 2242 irq_reset(display, PICAINTERRUPT_IRQ_REGS); 2243 else 2244 irq_reset(display, GEN11_DE_HPD_IRQ_REGS); 2245 2246 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2247 irq_reset(display, SDE_IRQ_REGS); 2248 } 2249 2250 void gen8_irq_power_well_post_enable(struct intel_display *display, 2251 u8 pipe_mask) 2252 { 2253 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 2254 gen8_de_pipe_flip_done_mask(display); 2255 enum pipe pipe; 2256 2257 spin_lock_irq(&display->irq.lock); 2258 2259 if (!intel_parent_irq_enabled(display)) { 2260 spin_unlock_irq(&display->irq.lock); 2261 return; 2262 } 2263 2264 for_each_pipe_masked(display, pipe, pipe_mask) 2265 irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2266 display->irq.de_pipe_imr_mask[pipe], 2267 ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); 2268 2269 spin_unlock_irq(&display->irq.lock); 2270 } 2271 2272 void gen8_irq_power_well_pre_disable(struct intel_display *display, 2273 u8 pipe_mask) 2274 { 2275 enum pipe pipe; 2276 2277 spin_lock_irq(&display->irq.lock); 2278 2279 if (!intel_parent_irq_enabled(display)) { 2280 spin_unlock_irq(&display->irq.lock); 2281 return; 2282 } 2283 2284 for_each_pipe_masked(display, pipe, pipe_mask) 2285 irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2286 2287 spin_unlock_irq(&display->irq.lock); 2288 2289 /* make sure we're done processing display irqs */ 2290 intel_parent_irq_synchronize(display); 2291 } 2292 2293 /* 2294 * SDEIER is also touched by the interrupt handler to work around missed PCH 2295 * interrupts. Hence we can't update it after the interrupt handler is enabled - 2296 * instead we unconditionally enable all PCH interrupt sources here, but then 2297 * only unmask them as needed with SDEIMR. 2298 * 2299 * Note that we currently do this after installing the interrupt handler, 2300 * but before we enable the master interrupt. That should be sufficient 2301 * to avoid races with the irq handler, assuming we have MSI. Shared legacy 2302 * interrupts could still race. 2303 */ 2304 static void ibx_irq_postinstall(struct intel_display *display) 2305 { 2306 u32 mask; 2307 2308 if (HAS_PCH_NOP(display)) 2309 return; 2310 2311 if (HAS_PCH_IBX(display)) 2312 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 2313 else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) 2314 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 2315 else 2316 mask = SDE_GMBUS_CPT; 2317 2318 irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2319 } 2320 2321 void valleyview_enable_display_irqs(struct intel_display *display) 2322 { 2323 spin_lock_irq(&display->irq.lock); 2324 2325 if (display->irq.vlv_display_irqs_enabled) 2326 goto out; 2327 2328 display->irq.vlv_display_irqs_enabled = true; 2329 2330 if (intel_parent_irq_enabled(display)) { 2331 _vlv_display_irq_reset(display); 2332 _vlv_display_irq_postinstall(display); 2333 } 2334 2335 out: 2336 spin_unlock_irq(&display->irq.lock); 2337 } 2338 2339 void valleyview_disable_display_irqs(struct intel_display *display) 2340 { 2341 spin_lock_irq(&display->irq.lock); 2342 2343 if (!display->irq.vlv_display_irqs_enabled) 2344 goto out; 2345 2346 display->irq.vlv_display_irqs_enabled = false; 2347 2348 if (intel_parent_irq_enabled(display)) 2349 _vlv_display_irq_reset(display); 2350 out: 2351 spin_unlock_irq(&display->irq.lock); 2352 } 2353 2354 static void ilk_de_irq_postinstall(struct intel_display *display) 2355 { 2356 u32 display_mask, extra_mask; 2357 2358 if (DISPLAY_VER(display) >= 7) { 2359 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 2360 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 2361 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 2362 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 2363 DE_PLANE_FLIP_DONE_IVB(PLANE_C) | 2364 DE_PLANE_FLIP_DONE_IVB(PLANE_B) | 2365 DE_PLANE_FLIP_DONE_IVB(PLANE_A) | 2366 DE_DP_A_HOTPLUG_IVB); 2367 } else { 2368 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | 2369 DE_PCH_EVENT | DE_GTT_FAULT | 2370 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 2371 DE_PIPEA_CRC_DONE | DE_POISON); 2372 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 2373 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 2374 DE_PLANE_FLIP_DONE(PLANE_A) | 2375 DE_PLANE_FLIP_DONE(PLANE_B) | 2376 DE_DP_A_HOTPLUG); 2377 } 2378 2379 if (display->platform.haswell) { 2380 assert_iir_is_zero(display, EDP_PSR_IIR); 2381 display_mask |= DE_EDP_PSR_INT_HSW; 2382 } 2383 2384 if (display->platform.ironlake && display->platform.mobile) 2385 extra_mask |= DE_PCU_EVENT; 2386 2387 display->irq.ilk_de_imr_mask = ~display_mask; 2388 2389 ibx_irq_postinstall(display); 2390 2391 irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, 2392 display_mask | extra_mask); 2393 } 2394 2395 static void mtp_irq_postinstall(struct intel_display *display); 2396 static void icp_irq_postinstall(struct intel_display *display); 2397 2398 static void gen8_de_irq_postinstall(struct intel_display *display) 2399 { 2400 u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) | 2401 GEN8_PIPE_CDCLK_CRC_DONE; 2402 u32 de_pipe_enables; 2403 u32 de_port_masked = gen8_de_port_aux_mask(display); 2404 u32 de_port_enables; 2405 u32 de_misc_masked = GEN8_DE_EDP_PSR; 2406 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 2407 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 2408 enum pipe pipe; 2409 2410 if (!HAS_DISPLAY(display)) 2411 return; 2412 2413 if (DISPLAY_VER(display) >= 14) 2414 mtp_irq_postinstall(display); 2415 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2416 icp_irq_postinstall(display); 2417 else if (HAS_PCH_SPLIT(display)) 2418 ibx_irq_postinstall(display); 2419 2420 if (DISPLAY_VER(display) < 11) 2421 de_misc_masked |= GEN8_DE_MISC_GSE; 2422 2423 if (display->platform.geminilake || display->platform.broxton) 2424 de_port_masked |= BXT_DE_PORT_GMBUS; 2425 2426 if (DISPLAY_VER(display) >= 14) { 2427 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR | 2428 XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT; 2429 } else if (DISPLAY_VER(display) >= 11) { 2430 enum port port; 2431 2432 if (intel_bios_is_dsi_present(display, &port)) 2433 de_port_masked |= DSI0_TE | DSI1_TE; 2434 } 2435 2436 if (HAS_DBUF_OVERLAP_DETECTION(display)) 2437 de_misc_masked |= XE2LPD_DBUF_OVERLAP_DETECTED; 2438 2439 if (HAS_DSB(display)) 2440 de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) | 2441 GEN12_DSB_INT(INTEL_DSB_1) | 2442 GEN12_DSB_INT(INTEL_DSB_2); 2443 2444 /* TODO figure PIPEDMC interrupts for pre-LNL */ 2445 if (DISPLAY_VER(display) >= 20) 2446 de_pipe_masked |= GEN12_PIPEDMC_INTERRUPT; 2447 2448 de_pipe_enables = de_pipe_masked | 2449 GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 2450 gen8_de_pipe_flip_done_mask(display); 2451 2452 de_port_enables = de_port_masked; 2453 if (display->platform.geminilake || display->platform.broxton) 2454 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 2455 else if (display->platform.broadwell) 2456 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 2457 2458 if (DISPLAY_VER(display) >= 12) { 2459 enum transcoder trans; 2460 2461 for_each_cpu_transcoder_masked(display, trans, trans_mask) { 2462 enum intel_display_power_domain domain; 2463 2464 domain = POWER_DOMAIN_TRANSCODER(trans); 2465 if (!intel_display_power_is_enabled(display, domain)) 2466 continue; 2467 2468 assert_iir_is_zero(display, TRANS_PSR_IIR(display, trans)); 2469 } 2470 } else { 2471 assert_iir_is_zero(display, EDP_PSR_IIR); 2472 } 2473 2474 for_each_pipe(display, pipe) { 2475 display->irq.de_pipe_imr_mask[pipe] = ~de_pipe_masked; 2476 2477 if (intel_display_power_is_enabled(display, 2478 POWER_DOMAIN_PIPE(pipe))) 2479 irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2480 display->irq.de_pipe_imr_mask[pipe], 2481 de_pipe_enables); 2482 } 2483 2484 irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables); 2485 irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked); 2486 2487 if (IS_DISPLAY_VER(display, 11, 13)) { 2488 u32 de_hpd_masked = 0; 2489 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 2490 GEN11_DE_TBT_HOTPLUG_MASK; 2491 2492 irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables); 2493 } 2494 } 2495 2496 u32 xelpdp_pica_aux_mask(struct intel_display *display) 2497 { 2498 u32 mask = XELPDP_AUX_TC_MASK; 2499 2500 if (DISPLAY_VER(display) >= 20) 2501 mask |= XE2LPD_AUX_DDI_MASK; 2502 2503 return mask; 2504 } 2505 2506 static void mtp_irq_postinstall(struct intel_display *display) 2507 { 2508 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; 2509 u32 de_hpd_mask = xelpdp_pica_aux_mask(display); 2510 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 2511 XELPDP_TBT_HOTPLUG_MASK; 2512 2513 irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables); 2514 2515 irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); 2516 } 2517 2518 static void icp_irq_postinstall(struct intel_display *display) 2519 { 2520 u32 mask = SDE_GMBUS_ICP; 2521 2522 irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2523 } 2524 2525 static void gen11_de_irq_postinstall(struct intel_display *display) 2526 { 2527 gen8_de_irq_postinstall(display); 2528 2529 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 2530 } 2531 2532 struct intel_display_irq_funcs { 2533 void (*reset)(struct intel_display *display); 2534 void (*postinstall)(struct intel_display *display); 2535 void (*ack)(struct intel_display *display, struct intel_display_irq_state *state); 2536 bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state); 2537 }; 2538 2539 static const struct intel_display_irq_funcs gen11_display_irq_funcs = { 2540 .reset = gen11_display_irq_reset, 2541 .postinstall = gen11_de_irq_postinstall, 2542 .handler = gen11_display_irq_handler, 2543 }; 2544 2545 static const struct intel_display_irq_funcs gen8_display_irq_funcs = { 2546 .reset = gen8_display_irq_reset, 2547 .postinstall = gen8_de_irq_postinstall, 2548 .handler = gen8_display_irq_handler, 2549 }; 2550 2551 static const struct intel_display_irq_funcs vlv_display_irq_funcs = { 2552 .reset = vlv_display_irq_reset, 2553 .postinstall = vlv_display_irq_postinstall, 2554 .ack = vlv_display_irq_ack, 2555 .handler = vlv_display_irq_handler, 2556 }; 2557 2558 static const struct intel_display_irq_funcs ilk_display_irq_funcs = { 2559 .reset = ilk_display_irq_reset, 2560 .postinstall = ilk_de_irq_postinstall, 2561 .handler = ilk_display_irq_handler, 2562 }; 2563 2564 static const struct intel_display_irq_funcs i965_display_irq_funcs = { 2565 .reset = i9xx_display_irq_reset, 2566 .postinstall = i965_display_irq_postinstall, 2567 .ack = i9xx_display_irq_ack, 2568 .handler = i965_display_irq_handler, 2569 }; 2570 2571 static const struct intel_display_irq_funcs i915_display_irq_funcs = { 2572 .reset = i9xx_display_irq_reset, 2573 .postinstall = i915_display_irq_postinstall, 2574 .ack = i9xx_display_irq_ack, 2575 .handler = i915_display_irq_handler, 2576 }; 2577 2578 void intel_display_irq_reset(struct intel_display *display) 2579 { 2580 if (!HAS_DISPLAY(display)) 2581 return; 2582 2583 display->irq.funcs->reset(display); 2584 } 2585 2586 void intel_display_irq_postinstall(struct intel_display *display) 2587 { 2588 if (!HAS_DISPLAY(display)) 2589 return; 2590 2591 display->irq.funcs->postinstall(display); 2592 } 2593 2594 void intel_display_irq_ack(struct intel_display *display, 2595 struct intel_display_irq_state *state) 2596 { 2597 if (!HAS_DISPLAY(display) || !display->irq.funcs->ack) 2598 return; 2599 2600 display->irq.funcs->ack(display, state); 2601 } 2602 2603 bool intel_display_irq_handler(struct intel_display *display, 2604 const struct intel_display_irq_state *state) 2605 { 2606 if (!HAS_DISPLAY(display) || !display->irq.funcs->handler) 2607 return true; 2608 2609 return display->irq.funcs->handler(display, state); 2610 } 2611 2612 void intel_display_irq_init(struct intel_display *display) 2613 { 2614 spin_lock_init(&display->irq.lock); 2615 2616 display->drm->vblank_disable_immediate = true; 2617 2618 intel_hotplug_irq_init(display); 2619 2620 INIT_WORK(&display->irq.vblank_notify_work, 2621 intel_display_vblank_notify_work); 2622 2623 if (DISPLAY_VER(display) >= 11) 2624 display->irq.funcs = &gen11_display_irq_funcs; 2625 else if (display->platform.cherryview || display->platform.valleyview) 2626 display->irq.funcs = &vlv_display_irq_funcs; 2627 else if (DISPLAY_VER(display) >= 8) 2628 display->irq.funcs = &gen8_display_irq_funcs; 2629 else if (DISPLAY_VER(display) >= 5) 2630 display->irq.funcs = &ilk_display_irq_funcs; 2631 else if (DISPLAY_VER(display) == 4) 2632 display->irq.funcs = &i965_display_irq_funcs; 2633 else 2634 display->irq.funcs = &i915_display_irq_funcs; 2635 } 2636 2637 struct intel_display_irq_snapshot { 2638 u32 derrmr; 2639 u32 err_int; 2640 }; 2641 2642 struct intel_display_irq_snapshot * 2643 intel_display_irq_snapshot_capture(struct intel_display *display) 2644 { 2645 struct intel_display_irq_snapshot *snapshot; 2646 2647 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 2648 if (!snapshot) 2649 return NULL; 2650 2651 if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display)) 2652 snapshot->derrmr = intel_de_read(display, DERRMR); 2653 2654 if (DISPLAY_VER(display) == 7) 2655 snapshot->err_int = intel_de_read(display, GEN7_ERR_INT); 2656 2657 return snapshot; 2658 } 2659 2660 void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, 2661 struct drm_printer *p) 2662 { 2663 if (!snapshot) 2664 return; 2665 2666 drm_printf(p, "DERRMR: 0x%08x\n", snapshot->derrmr); 2667 drm_printf(p, "ERR_INT: 0x%08x\n", snapshot->err_int); 2668 } 2669