1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "gt/intel_rps.h" 7 #include "i915_drv.h" 8 #include "i915_irq.h" 9 #include "i915_reg.h" 10 #include "icl_dsi_regs.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_irq.h" 14 #include "intel_display_trace.h" 15 #include "intel_display_types.h" 16 #include "intel_dp_aux.h" 17 #include "intel_fdi_regs.h" 18 #include "intel_fifo_underrun.h" 19 #include "intel_gmbus.h" 20 #include "intel_hotplug_irq.h" 21 #include "intel_pipe_crc_regs.h" 22 #include "intel_pmdemand.h" 23 #include "intel_psr.h" 24 #include "intel_psr_regs.h" 25 26 static void 27 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 28 { 29 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 30 31 drm_crtc_handle_vblank(&crtc->base); 32 } 33 34 /** 35 * ilk_update_display_irq - update DEIMR 36 * @dev_priv: driver private 37 * @interrupt_mask: mask of interrupt bits to update 38 * @enabled_irq_mask: mask of interrupt bits to enable 39 */ 40 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 41 u32 interrupt_mask, u32 enabled_irq_mask) 42 { 43 u32 new_val; 44 45 lockdep_assert_held(&dev_priv->irq_lock); 46 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 47 48 new_val = dev_priv->irq_mask; 49 new_val &= ~interrupt_mask; 50 new_val |= (~enabled_irq_mask & interrupt_mask); 51 52 if (new_val != dev_priv->irq_mask && 53 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { 54 dev_priv->irq_mask = new_val; 55 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); 56 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); 57 } 58 } 59 60 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits) 61 { 62 ilk_update_display_irq(i915, bits, bits); 63 } 64 65 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits) 66 { 67 ilk_update_display_irq(i915, bits, 0); 68 } 69 70 /** 71 * bdw_update_port_irq - update DE port interrupt 72 * @dev_priv: driver private 73 * @interrupt_mask: mask of interrupt bits to update 74 * @enabled_irq_mask: mask of interrupt bits to enable 75 */ 76 void bdw_update_port_irq(struct drm_i915_private *dev_priv, 77 u32 interrupt_mask, u32 enabled_irq_mask) 78 { 79 u32 new_val; 80 u32 old_val; 81 82 lockdep_assert_held(&dev_priv->irq_lock); 83 84 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 85 86 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 87 return; 88 89 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 90 91 new_val = old_val; 92 new_val &= ~interrupt_mask; 93 new_val |= (~enabled_irq_mask & interrupt_mask); 94 95 if (new_val != old_val) { 96 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); 97 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 98 } 99 } 100 101 /** 102 * bdw_update_pipe_irq - update DE pipe interrupt 103 * @dev_priv: driver private 104 * @pipe: pipe whose interrupt to update 105 * @interrupt_mask: mask of interrupt bits to update 106 * @enabled_irq_mask: mask of interrupt bits to enable 107 */ 108 static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 109 enum pipe pipe, u32 interrupt_mask, 110 u32 enabled_irq_mask) 111 { 112 u32 new_val; 113 114 lockdep_assert_held(&dev_priv->irq_lock); 115 116 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 117 118 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 119 return; 120 121 new_val = dev_priv->display.irq.de_irq_mask[pipe]; 122 new_val &= ~interrupt_mask; 123 new_val |= (~enabled_irq_mask & interrupt_mask); 124 125 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { 126 dev_priv->display.irq.de_irq_mask[pipe] = new_val; 127 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), 128 dev_priv->display.irq.de_irq_mask[pipe]); 129 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); 130 } 131 } 132 133 void bdw_enable_pipe_irq(struct drm_i915_private *i915, 134 enum pipe pipe, u32 bits) 135 { 136 bdw_update_pipe_irq(i915, pipe, bits, bits); 137 } 138 139 void bdw_disable_pipe_irq(struct drm_i915_private *i915, 140 enum pipe pipe, u32 bits) 141 { 142 bdw_update_pipe_irq(i915, pipe, bits, 0); 143 } 144 145 /** 146 * ibx_display_interrupt_update - update SDEIMR 147 * @dev_priv: driver private 148 * @interrupt_mask: mask of interrupt bits to update 149 * @enabled_irq_mask: mask of interrupt bits to enable 150 */ 151 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 152 u32 interrupt_mask, 153 u32 enabled_irq_mask) 154 { 155 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); 156 157 sdeimr &= ~interrupt_mask; 158 sdeimr |= (~enabled_irq_mask & interrupt_mask); 159 160 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 161 162 lockdep_assert_held(&dev_priv->irq_lock); 163 164 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 165 return; 166 167 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); 168 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); 169 } 170 171 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits) 172 { 173 ibx_display_interrupt_update(i915, bits, bits); 174 } 175 176 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits) 177 { 178 ibx_display_interrupt_update(i915, bits, 0); 179 } 180 181 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 182 enum pipe pipe) 183 { 184 u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe]; 185 u32 enable_mask = status_mask << 16; 186 187 lockdep_assert_held(&dev_priv->irq_lock); 188 189 if (DISPLAY_VER(dev_priv) < 5) 190 goto out; 191 192 /* 193 * On pipe A we don't support the PSR interrupt yet, 194 * on pipe B and C the same bit MBZ. 195 */ 196 if (drm_WARN_ON_ONCE(&dev_priv->drm, 197 status_mask & PIPE_A_PSR_STATUS_VLV)) 198 return 0; 199 /* 200 * On pipe B and C we don't support the PSR interrupt yet, on pipe 201 * A the same bit is for perf counters which we don't use either. 202 */ 203 if (drm_WARN_ON_ONCE(&dev_priv->drm, 204 status_mask & PIPE_B_PSR_STATUS_VLV)) 205 return 0; 206 207 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 208 SPRITE0_FLIP_DONE_INT_EN_VLV | 209 SPRITE1_FLIP_DONE_INT_EN_VLV); 210 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 211 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 212 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 213 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 214 215 out: 216 drm_WARN_ONCE(&dev_priv->drm, 217 enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 218 status_mask & ~PIPESTAT_INT_STATUS_MASK, 219 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 220 pipe_name(pipe), enable_mask, status_mask); 221 222 return enable_mask; 223 } 224 225 void i915_enable_pipestat(struct drm_i915_private *dev_priv, 226 enum pipe pipe, u32 status_mask) 227 { 228 i915_reg_t reg = PIPESTAT(dev_priv, pipe); 229 u32 enable_mask; 230 231 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 232 "pipe %c: status_mask=0x%x\n", 233 pipe_name(pipe), status_mask); 234 235 lockdep_assert_held(&dev_priv->irq_lock); 236 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 237 238 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) 239 return; 240 241 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; 242 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 243 244 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 245 intel_uncore_posting_read(&dev_priv->uncore, reg); 246 } 247 248 void i915_disable_pipestat(struct drm_i915_private *dev_priv, 249 enum pipe pipe, u32 status_mask) 250 { 251 i915_reg_t reg = PIPESTAT(dev_priv, pipe); 252 u32 enable_mask; 253 254 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 255 "pipe %c: status_mask=0x%x\n", 256 pipe_name(pipe), status_mask); 257 258 lockdep_assert_held(&dev_priv->irq_lock); 259 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 260 261 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0) 262 return; 263 264 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; 265 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 266 267 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 268 intel_uncore_posting_read(&dev_priv->uncore, reg); 269 } 270 271 static bool i915_has_asle(struct drm_i915_private *i915) 272 { 273 if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915)) 274 return false; 275 276 return intel_opregion_asle_present(i915); 277 } 278 279 /** 280 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 281 * @dev_priv: i915 device private 282 */ 283 void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) 284 { 285 if (!i915_has_asle(dev_priv)) 286 return; 287 288 spin_lock_irq(&dev_priv->irq_lock); 289 290 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 291 if (DISPLAY_VER(dev_priv) >= 4) 292 i915_enable_pipestat(dev_priv, PIPE_A, 293 PIPE_LEGACY_BLC_EVENT_STATUS); 294 295 spin_unlock_irq(&dev_priv->irq_lock); 296 } 297 298 #if defined(CONFIG_DEBUG_FS) 299 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 300 enum pipe pipe, 301 u32 crc0, u32 crc1, 302 u32 crc2, u32 crc3, 303 u32 crc4) 304 { 305 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 306 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 307 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 308 309 trace_intel_pipe_crc(crtc, crcs); 310 311 spin_lock(&pipe_crc->lock); 312 /* 313 * For some not yet identified reason, the first CRC is 314 * bonkers. So let's just wait for the next vblank and read 315 * out the buggy result. 316 * 317 * On GEN8+ sometimes the second CRC is bonkers as well, so 318 * don't trust that one either. 319 */ 320 if (pipe_crc->skipped <= 0 || 321 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { 322 pipe_crc->skipped++; 323 spin_unlock(&pipe_crc->lock); 324 return; 325 } 326 spin_unlock(&pipe_crc->lock); 327 328 drm_crtc_add_crc_entry(&crtc->base, true, 329 drm_crtc_accurate_vblank_count(&crtc->base), 330 crcs); 331 } 332 #else 333 static inline void 334 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 335 enum pipe pipe, 336 u32 crc0, u32 crc1, 337 u32 crc2, u32 crc3, 338 u32 crc4) {} 339 #endif 340 341 static void flip_done_handler(struct drm_i915_private *i915, 342 enum pipe pipe) 343 { 344 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe); 345 346 spin_lock(&i915->drm.event_lock); 347 348 if (crtc->flip_done_event) { 349 trace_intel_crtc_flip_done(crtc); 350 drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event); 351 crtc->flip_done_event = NULL; 352 } 353 354 spin_unlock(&i915->drm.event_lock); 355 } 356 357 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 358 enum pipe pipe) 359 { 360 display_pipe_crc_irq_handler(dev_priv, pipe, 361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), 362 0, 0, 0, 0); 363 } 364 365 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 366 enum pipe pipe) 367 { 368 display_pipe_crc_irq_handler(dev_priv, pipe, 369 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 370 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), 371 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), 372 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), 373 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); 374 } 375 376 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 377 enum pipe pipe) 378 { 379 u32 res1, res2; 380 381 if (DISPLAY_VER(dev_priv) >= 3) 382 res1 = intel_uncore_read(&dev_priv->uncore, 383 PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); 384 else 385 res1 = 0; 386 387 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 388 res2 = intel_uncore_read(&dev_priv->uncore, 389 PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); 390 else 391 res2 = 0; 392 393 display_pipe_crc_irq_handler(dev_priv, pipe, 394 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), 395 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), 396 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), 397 res1, res2); 398 } 399 400 void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) 401 { 402 enum pipe pipe; 403 404 for_each_pipe(dev_priv, pipe) { 405 intel_uncore_write(&dev_priv->uncore, 406 PIPESTAT(dev_priv, pipe), 407 PIPESTAT_INT_STATUS_MASK | 408 PIPE_FIFO_UNDERRUN_STATUS); 409 410 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; 411 } 412 } 413 414 void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, 415 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 416 { 417 enum pipe pipe; 418 419 spin_lock(&dev_priv->irq_lock); 420 421 if (!dev_priv->display.irq.display_irqs_enabled) { 422 spin_unlock(&dev_priv->irq_lock); 423 return; 424 } 425 426 for_each_pipe(dev_priv, pipe) { 427 i915_reg_t reg; 428 u32 status_mask, enable_mask, iir_bit = 0; 429 430 /* 431 * PIPESTAT bits get signalled even when the interrupt is 432 * disabled with the mask bits, and some of the status bits do 433 * not generate interrupts at all (like the underrun bit). Hence 434 * we need to be careful that we only handle what we want to 435 * handle. 436 */ 437 438 /* fifo underruns are filterered in the underrun handler. */ 439 status_mask = PIPE_FIFO_UNDERRUN_STATUS; 440 441 switch (pipe) { 442 default: 443 case PIPE_A: 444 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 445 break; 446 case PIPE_B: 447 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 448 break; 449 case PIPE_C: 450 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 451 break; 452 } 453 if (iir & iir_bit) 454 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe]; 455 456 if (!status_mask) 457 continue; 458 459 reg = PIPESTAT(dev_priv, pipe); 460 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; 461 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 462 463 /* 464 * Clear the PIPE*STAT regs before the IIR 465 * 466 * Toggle the enable bits to make sure we get an 467 * edge in the ISR pipe event bit if we don't clear 468 * all the enabled status bits. Otherwise the edge 469 * triggered IIR on i965/g4x wouldn't notice that 470 * an interrupt is still pending. 471 */ 472 if (pipe_stats[pipe]) { 473 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); 474 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); 475 } 476 } 477 spin_unlock(&dev_priv->irq_lock); 478 } 479 480 void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, 481 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) 482 { 483 enum pipe pipe; 484 485 for_each_pipe(dev_priv, pipe) { 486 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 487 intel_handle_vblank(dev_priv, pipe); 488 489 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 490 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 491 492 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 493 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 494 } 495 } 496 497 void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, 498 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 499 { 500 bool blc_event = false; 501 enum pipe pipe; 502 503 for_each_pipe(dev_priv, pipe) { 504 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 505 intel_handle_vblank(dev_priv, pipe); 506 507 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 508 blc_event = true; 509 510 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 511 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 512 513 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 514 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 515 } 516 517 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 518 intel_opregion_asle_intr(dev_priv); 519 } 520 521 void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, 522 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 523 { 524 bool blc_event = false; 525 enum pipe pipe; 526 527 for_each_pipe(dev_priv, pipe) { 528 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 529 intel_handle_vblank(dev_priv, pipe); 530 531 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 532 blc_event = true; 533 534 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 535 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 536 537 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 538 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 539 } 540 541 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 542 intel_opregion_asle_intr(dev_priv); 543 544 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 545 intel_gmbus_irq_handler(dev_priv); 546 } 547 548 void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, 549 u32 pipe_stats[I915_MAX_PIPES]) 550 { 551 enum pipe pipe; 552 553 for_each_pipe(dev_priv, pipe) { 554 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 555 intel_handle_vblank(dev_priv, pipe); 556 557 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) 558 flip_done_handler(dev_priv, pipe); 559 560 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 561 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 562 563 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 564 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 565 } 566 567 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 568 intel_gmbus_irq_handler(dev_priv); 569 } 570 571 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 572 { 573 enum pipe pipe; 574 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 575 576 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 577 578 if (pch_iir & SDE_AUDIO_POWER_MASK) { 579 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 580 SDE_AUDIO_POWER_SHIFT); 581 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", 582 port_name(port)); 583 } 584 585 if (pch_iir & SDE_AUX_MASK) 586 intel_dp_aux_irq_handler(dev_priv); 587 588 if (pch_iir & SDE_GMBUS) 589 intel_gmbus_irq_handler(dev_priv); 590 591 if (pch_iir & SDE_AUDIO_HDCP_MASK) 592 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); 593 594 if (pch_iir & SDE_AUDIO_TRANS_MASK) 595 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); 596 597 if (pch_iir & SDE_POISON) 598 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 599 600 if (pch_iir & SDE_FDI_MASK) { 601 for_each_pipe(dev_priv, pipe) 602 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 603 pipe_name(pipe), 604 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 605 } 606 607 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 608 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); 609 610 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 611 drm_dbg(&dev_priv->drm, 612 "PCH transcoder CRC error interrupt\n"); 613 614 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 615 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); 616 617 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 618 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); 619 } 620 621 static void ivb_err_int_handler(struct drm_i915_private *dev_priv) 622 { 623 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); 624 enum pipe pipe; 625 626 if (err_int & ERR_INT_POISON) 627 drm_err(&dev_priv->drm, "Poison interrupt\n"); 628 629 for_each_pipe(dev_priv, pipe) { 630 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 631 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 632 633 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 634 if (IS_IVYBRIDGE(dev_priv)) 635 ivb_pipe_crc_irq_handler(dev_priv, pipe); 636 else 637 hsw_pipe_crc_irq_handler(dev_priv, pipe); 638 } 639 } 640 641 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); 642 } 643 644 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) 645 { 646 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); 647 enum pipe pipe; 648 649 if (serr_int & SERR_INT_POISON) 650 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 651 652 for_each_pipe(dev_priv, pipe) 653 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 654 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); 655 656 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); 657 } 658 659 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 660 { 661 enum pipe pipe; 662 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 663 664 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 665 666 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 667 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 668 SDE_AUDIO_POWER_SHIFT_CPT); 669 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", 670 port_name(port)); 671 } 672 673 if (pch_iir & SDE_AUX_MASK_CPT) 674 intel_dp_aux_irq_handler(dev_priv); 675 676 if (pch_iir & SDE_GMBUS_CPT) 677 intel_gmbus_irq_handler(dev_priv); 678 679 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 680 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); 681 682 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 683 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); 684 685 if (pch_iir & SDE_FDI_MASK_CPT) { 686 for_each_pipe(dev_priv, pipe) 687 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 688 pipe_name(pipe), 689 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 690 } 691 692 if (pch_iir & SDE_ERROR_CPT) 693 cpt_serr_int_handler(dev_priv); 694 } 695 696 void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 697 { 698 enum pipe pipe; 699 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 700 701 if (hotplug_trigger) 702 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 703 704 if (de_iir & DE_AUX_CHANNEL_A) 705 intel_dp_aux_irq_handler(dev_priv); 706 707 if (de_iir & DE_GSE) 708 intel_opregion_asle_intr(dev_priv); 709 710 if (de_iir & DE_POISON) 711 drm_err(&dev_priv->drm, "Poison interrupt\n"); 712 713 for_each_pipe(dev_priv, pipe) { 714 if (de_iir & DE_PIPE_VBLANK(pipe)) 715 intel_handle_vblank(dev_priv, pipe); 716 717 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) 718 flip_done_handler(dev_priv, pipe); 719 720 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 721 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 722 723 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 724 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 725 } 726 727 /* check event from PCH */ 728 if (de_iir & DE_PCH_EVENT) { 729 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 730 731 if (HAS_PCH_CPT(dev_priv)) 732 cpt_irq_handler(dev_priv, pch_iir); 733 else 734 ibx_irq_handler(dev_priv, pch_iir); 735 736 /* should clear PCH hotplug event before clear CPU irq */ 737 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 738 } 739 740 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT) 741 gen5_rps_irq_handler(&to_gt(dev_priv)->rps); 742 } 743 744 void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 745 { 746 enum pipe pipe; 747 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 748 749 if (hotplug_trigger) 750 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 751 752 if (de_iir & DE_ERR_INT_IVB) 753 ivb_err_int_handler(dev_priv); 754 755 if (de_iir & DE_EDP_PSR_INT_HSW) { 756 struct intel_encoder *encoder; 757 758 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 760 u32 psr_iir; 761 762 psr_iir = intel_uncore_rmw(&dev_priv->uncore, 763 EDP_PSR_IIR, 0, 0); 764 intel_psr_irq_handler(intel_dp, psr_iir); 765 break; 766 } 767 } 768 769 if (de_iir & DE_AUX_CHANNEL_A_IVB) 770 intel_dp_aux_irq_handler(dev_priv); 771 772 if (de_iir & DE_GSE_IVB) 773 intel_opregion_asle_intr(dev_priv); 774 775 for_each_pipe(dev_priv, pipe) { 776 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 777 intel_handle_vblank(dev_priv, pipe); 778 779 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) 780 flip_done_handler(dev_priv, pipe); 781 } 782 783 /* check event from PCH */ 784 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { 785 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 786 787 cpt_irq_handler(dev_priv, pch_iir); 788 789 /* clear PCH hotplug event before clear CPU irq */ 790 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 791 } 792 } 793 794 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 795 { 796 u32 mask; 797 798 if (DISPLAY_VER(dev_priv) >= 20) 799 return 0; 800 else if (DISPLAY_VER(dev_priv) >= 14) 801 return TGL_DE_PORT_AUX_DDIA | 802 TGL_DE_PORT_AUX_DDIB; 803 else if (DISPLAY_VER(dev_priv) >= 13) 804 return TGL_DE_PORT_AUX_DDIA | 805 TGL_DE_PORT_AUX_DDIB | 806 TGL_DE_PORT_AUX_DDIC | 807 XELPD_DE_PORT_AUX_DDID | 808 XELPD_DE_PORT_AUX_DDIE | 809 TGL_DE_PORT_AUX_USBC1 | 810 TGL_DE_PORT_AUX_USBC2 | 811 TGL_DE_PORT_AUX_USBC3 | 812 TGL_DE_PORT_AUX_USBC4; 813 else if (DISPLAY_VER(dev_priv) >= 12) 814 return TGL_DE_PORT_AUX_DDIA | 815 TGL_DE_PORT_AUX_DDIB | 816 TGL_DE_PORT_AUX_DDIC | 817 TGL_DE_PORT_AUX_USBC1 | 818 TGL_DE_PORT_AUX_USBC2 | 819 TGL_DE_PORT_AUX_USBC3 | 820 TGL_DE_PORT_AUX_USBC4 | 821 TGL_DE_PORT_AUX_USBC5 | 822 TGL_DE_PORT_AUX_USBC6; 823 824 mask = GEN8_AUX_CHANNEL_A; 825 if (DISPLAY_VER(dev_priv) >= 9) 826 mask |= GEN9_AUX_CHANNEL_B | 827 GEN9_AUX_CHANNEL_C | 828 GEN9_AUX_CHANNEL_D; 829 830 if (DISPLAY_VER(dev_priv) == 11) { 831 mask |= ICL_AUX_CHANNEL_F; 832 mask |= ICL_AUX_CHANNEL_E; 833 } 834 835 return mask; 836 } 837 838 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) 839 { 840 if (DISPLAY_VER(dev_priv) >= 14) 841 return MTL_PIPEDMC_ATS_FAULT | 842 MTL_PLANE_ATS_FAULT | 843 GEN12_PIPEDMC_FAULT | 844 GEN9_PIPE_CURSOR_FAULT | 845 GEN11_PIPE_PLANE5_FAULT | 846 GEN9_PIPE_PLANE4_FAULT | 847 GEN9_PIPE_PLANE3_FAULT | 848 GEN9_PIPE_PLANE2_FAULT | 849 GEN9_PIPE_PLANE1_FAULT; 850 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 851 return GEN12_PIPEDMC_FAULT | 852 GEN9_PIPE_CURSOR_FAULT | 853 GEN11_PIPE_PLANE5_FAULT | 854 GEN9_PIPE_PLANE4_FAULT | 855 GEN9_PIPE_PLANE3_FAULT | 856 GEN9_PIPE_PLANE2_FAULT | 857 GEN9_PIPE_PLANE1_FAULT; 858 else if (DISPLAY_VER(dev_priv) == 12) 859 return GEN12_PIPEDMC_FAULT | 860 GEN9_PIPE_CURSOR_FAULT | 861 GEN11_PIPE_PLANE7_FAULT | 862 GEN11_PIPE_PLANE6_FAULT | 863 GEN11_PIPE_PLANE5_FAULT | 864 GEN9_PIPE_PLANE4_FAULT | 865 GEN9_PIPE_PLANE3_FAULT | 866 GEN9_PIPE_PLANE2_FAULT | 867 GEN9_PIPE_PLANE1_FAULT; 868 else if (DISPLAY_VER(dev_priv) == 11) 869 return GEN9_PIPE_CURSOR_FAULT | 870 GEN11_PIPE_PLANE7_FAULT | 871 GEN11_PIPE_PLANE6_FAULT | 872 GEN11_PIPE_PLANE5_FAULT | 873 GEN9_PIPE_PLANE4_FAULT | 874 GEN9_PIPE_PLANE3_FAULT | 875 GEN9_PIPE_PLANE2_FAULT | 876 GEN9_PIPE_PLANE1_FAULT; 877 else if (DISPLAY_VER(dev_priv) >= 9) 878 return GEN9_PIPE_CURSOR_FAULT | 879 GEN9_PIPE_PLANE4_FAULT | 880 GEN9_PIPE_PLANE3_FAULT | 881 GEN9_PIPE_PLANE2_FAULT | 882 GEN9_PIPE_PLANE1_FAULT; 883 else 884 return GEN8_PIPE_CURSOR_FAULT | 885 GEN8_PIPE_SPRITE_FAULT | 886 GEN8_PIPE_PRIMARY_FAULT; 887 } 888 889 static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv) 890 { 891 wake_up_all(&dev_priv->display.pmdemand.waitqueue); 892 } 893 894 static void 895 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 896 { 897 bool found = false; 898 899 if (DISPLAY_VER(dev_priv) >= 14) { 900 if (iir & (XELPDP_PMDEMAND_RSP | 901 XELPDP_PMDEMAND_RSPTOUT_ERR)) { 902 if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) 903 drm_dbg(&dev_priv->drm, 904 "Error waiting for Punit PM Demand Response\n"); 905 906 intel_pmdemand_irq_handler(dev_priv); 907 found = true; 908 } 909 } else if (iir & GEN8_DE_MISC_GSE) { 910 intel_opregion_asle_intr(dev_priv); 911 found = true; 912 } 913 914 if (iir & GEN8_DE_EDP_PSR) { 915 struct intel_encoder *encoder; 916 u32 psr_iir; 917 i915_reg_t iir_reg; 918 919 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 920 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 921 922 if (DISPLAY_VER(dev_priv) >= 12) 923 iir_reg = TRANS_PSR_IIR(dev_priv, 924 intel_dp->psr.transcoder); 925 else 926 iir_reg = EDP_PSR_IIR; 927 928 psr_iir = intel_uncore_rmw(&dev_priv->uncore, iir_reg, 0, 0); 929 930 if (psr_iir) 931 found = true; 932 933 intel_psr_irq_handler(intel_dp, psr_iir); 934 935 /* prior GEN12 only have one EDP PSR */ 936 if (DISPLAY_VER(dev_priv) < 12) 937 break; 938 } 939 } 940 941 if (!found) 942 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir); 943 } 944 945 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, 946 u32 te_trigger) 947 { 948 enum pipe pipe = INVALID_PIPE; 949 enum transcoder dsi_trans; 950 enum port port; 951 u32 val; 952 953 /* 954 * Incase of dual link, TE comes from DSI_1 955 * this is to check if dual link is enabled 956 */ 957 val = intel_uncore_read(&dev_priv->uncore, 958 TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0)); 959 val &= PORT_SYNC_MODE_ENABLE; 960 961 /* 962 * if dual link is enabled, then read DSI_0 963 * transcoder registers 964 */ 965 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 966 PORT_A : PORT_B; 967 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 968 969 /* Check if DSI configured in command mode */ 970 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); 971 val = val & OP_MODE_MASK; 972 973 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 974 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); 975 return; 976 } 977 978 /* Get PIPE for handling VBLANK event */ 979 val = intel_uncore_read(&dev_priv->uncore, 980 TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); 981 switch (val & TRANS_DDI_EDP_INPUT_MASK) { 982 case TRANS_DDI_EDP_INPUT_A_ON: 983 pipe = PIPE_A; 984 break; 985 case TRANS_DDI_EDP_INPUT_B_ONOFF: 986 pipe = PIPE_B; 987 break; 988 case TRANS_DDI_EDP_INPUT_C_ONOFF: 989 pipe = PIPE_C; 990 break; 991 default: 992 drm_err(&dev_priv->drm, "Invalid PIPE\n"); 993 return; 994 } 995 996 intel_handle_vblank(dev_priv, pipe); 997 998 /* clear TE in dsi IIR */ 999 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 1000 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); 1001 } 1002 1003 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) 1004 { 1005 if (DISPLAY_VER(i915) >= 9) 1006 return GEN9_PIPE_PLANE1_FLIP_DONE; 1007 else 1008 return GEN8_PIPE_PRIMARY_FLIP_DONE; 1009 } 1010 1011 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv) 1012 { 1013 u32 mask = GEN8_PIPE_FIFO_UNDERRUN; 1014 1015 if (DISPLAY_VER(dev_priv) >= 13) 1016 mask |= XELPD_PIPE_SOFT_UNDERRUN | 1017 XELPD_PIPE_HARD_UNDERRUN; 1018 1019 return mask; 1020 } 1021 1022 static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir) 1023 { 1024 u32 pica_ier = 0; 1025 1026 *pica_iir = 0; 1027 *pch_iir = intel_de_read(i915, SDEIIR); 1028 if (!*pch_iir) 1029 return; 1030 1031 /** 1032 * PICA IER must be disabled/re-enabled around clearing PICA IIR and 1033 * SDEIIR, to avoid losing PICA IRQs and to ensure that such IRQs set 1034 * their flags both in the PICA and SDE IIR. 1035 */ 1036 if (*pch_iir & SDE_PICAINTERRUPT) { 1037 drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL); 1038 1039 pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0); 1040 *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR); 1041 intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir); 1042 } 1043 1044 intel_de_write(i915, SDEIIR, *pch_iir); 1045 1046 if (pica_ier) 1047 intel_de_write(i915, PICAINTERRUPT_IER, pica_ier); 1048 } 1049 1050 void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 1051 { 1052 u32 iir; 1053 enum pipe pipe; 1054 1055 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); 1056 1057 if (master_ctl & GEN8_DE_MISC_IRQ) { 1058 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); 1059 if (iir) { 1060 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); 1061 gen8_de_misc_irq_handler(dev_priv, iir); 1062 } else { 1063 drm_err_ratelimited(&dev_priv->drm, 1064 "The master control interrupt lied (DE MISC)!\n"); 1065 } 1066 } 1067 1068 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 1069 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); 1070 if (iir) { 1071 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); 1072 gen11_hpd_irq_handler(dev_priv, iir); 1073 } else { 1074 drm_err_ratelimited(&dev_priv->drm, 1075 "The master control interrupt lied, (DE HPD)!\n"); 1076 } 1077 } 1078 1079 if (master_ctl & GEN8_DE_PORT_IRQ) { 1080 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); 1081 if (iir) { 1082 bool found = false; 1083 1084 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); 1085 1086 if (iir & gen8_de_port_aux_mask(dev_priv)) { 1087 intel_dp_aux_irq_handler(dev_priv); 1088 found = true; 1089 } 1090 1091 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1092 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 1093 1094 if (hotplug_trigger) { 1095 bxt_hpd_irq_handler(dev_priv, hotplug_trigger); 1096 found = true; 1097 } 1098 } else if (IS_BROADWELL(dev_priv)) { 1099 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 1100 1101 if (hotplug_trigger) { 1102 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 1103 found = true; 1104 } 1105 } 1106 1107 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1108 (iir & BXT_DE_PORT_GMBUS)) { 1109 intel_gmbus_irq_handler(dev_priv); 1110 found = true; 1111 } 1112 1113 if (DISPLAY_VER(dev_priv) >= 11) { 1114 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 1115 1116 if (te_trigger) { 1117 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger); 1118 found = true; 1119 } 1120 } 1121 1122 if (!found) 1123 drm_err_ratelimited(&dev_priv->drm, 1124 "Unexpected DE Port interrupt\n"); 1125 } else { 1126 drm_err_ratelimited(&dev_priv->drm, 1127 "The master control interrupt lied (DE PORT)!\n"); 1128 } 1129 } 1130 1131 for_each_pipe(dev_priv, pipe) { 1132 u32 fault_errors; 1133 1134 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1135 continue; 1136 1137 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); 1138 if (!iir) { 1139 drm_err_ratelimited(&dev_priv->drm, 1140 "The master control interrupt lied (DE PIPE)!\n"); 1141 continue; 1142 } 1143 1144 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); 1145 1146 if (iir & GEN8_PIPE_VBLANK) 1147 intel_handle_vblank(dev_priv, pipe); 1148 1149 if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) 1150 flip_done_handler(dev_priv, pipe); 1151 1152 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 1153 hsw_pipe_crc_irq_handler(dev_priv, pipe); 1154 1155 if (iir & gen8_de_pipe_underrun_mask(dev_priv)) 1156 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1157 1158 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); 1159 if (fault_errors) 1160 drm_err_ratelimited(&dev_priv->drm, 1161 "Fault errors on pipe %c: 0x%08x\n", 1162 pipe_name(pipe), 1163 fault_errors); 1164 } 1165 1166 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && 1167 master_ctl & GEN8_DE_PCH_IRQ) { 1168 u32 pica_iir; 1169 1170 /* 1171 * FIXME(BDW): Assume for now that the new interrupt handling 1172 * scheme also closed the SDE interrupt handling race we've seen 1173 * on older pch-split platforms. But this needs testing. 1174 */ 1175 gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir); 1176 if (iir) { 1177 if (pica_iir) 1178 xelpdp_pica_irq_handler(dev_priv, pica_iir); 1179 1180 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1181 icp_irq_handler(dev_priv, iir); 1182 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 1183 spt_irq_handler(dev_priv, iir); 1184 else 1185 cpt_irq_handler(dev_priv, iir); 1186 } else { 1187 /* 1188 * Like on previous PCH there seems to be something 1189 * fishy going on with forwarding PCH interrupts. 1190 */ 1191 drm_dbg(&dev_priv->drm, 1192 "The master control interrupt lied (SDE)!\n"); 1193 } 1194 } 1195 } 1196 1197 u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl) 1198 { 1199 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 1200 u32 iir; 1201 1202 if (!(master_ctl & GEN11_GU_MISC_IRQ)) 1203 return 0; 1204 1205 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); 1206 if (likely(iir)) 1207 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir); 1208 1209 return iir; 1210 } 1211 1212 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir) 1213 { 1214 if (iir & GEN11_GU_MISC_GSE) 1215 intel_opregion_asle_intr(i915); 1216 } 1217 1218 void gen11_display_irq_handler(struct drm_i915_private *i915) 1219 { 1220 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 1221 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); 1222 1223 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1224 /* 1225 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 1226 * for the display related bits. 1227 */ 1228 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0); 1229 gen8_de_irq_handler(i915, disp_ctl); 1230 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 1231 GEN11_DISPLAY_IRQ_ENABLE); 1232 1233 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1234 } 1235 1236 /* Called from drm generic code, passed 'crtc' which 1237 * we use as a pipe index 1238 */ 1239 int i8xx_enable_vblank(struct drm_crtc *crtc) 1240 { 1241 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1242 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1243 unsigned long irqflags; 1244 1245 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1246 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1247 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1248 1249 return 0; 1250 } 1251 1252 int i915gm_enable_vblank(struct drm_crtc *crtc) 1253 { 1254 struct drm_i915_private *i915 = to_i915(crtc->dev); 1255 1256 /* 1257 * Vblank interrupts fail to wake the device up from C2+. 1258 * Disabling render clock gating during C-states avoids 1259 * the problem. There is a small power cost so we do this 1260 * only when vblank interrupts are actually enabled. 1261 */ 1262 if (i915->display.irq.vblank_enabled++ == 0) 1263 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1264 1265 return i8xx_enable_vblank(crtc); 1266 } 1267 1268 int i965_enable_vblank(struct drm_crtc *crtc) 1269 { 1270 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1271 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1272 unsigned long irqflags; 1273 1274 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1275 i915_enable_pipestat(dev_priv, pipe, 1276 PIPE_START_VBLANK_INTERRUPT_STATUS); 1277 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1278 1279 return 0; 1280 } 1281 1282 int ilk_enable_vblank(struct drm_crtc *crtc) 1283 { 1284 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1285 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1286 unsigned long irqflags; 1287 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 1288 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1289 1290 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1291 ilk_enable_display_irq(dev_priv, bit); 1292 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1293 1294 /* Even though there is no DMC, frame counter can get stuck when 1295 * PSR is active as no frames are generated. 1296 */ 1297 if (HAS_PSR(dev_priv)) 1298 drm_crtc_vblank_restore(crtc); 1299 1300 return 0; 1301 } 1302 1303 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 1304 bool enable) 1305 { 1306 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 1307 enum port port; 1308 1309 if (!(intel_crtc->mode_flags & 1310 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 1311 return false; 1312 1313 /* for dual link cases we consider TE from slave */ 1314 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 1315 port = PORT_B; 1316 else 1317 port = PORT_A; 1318 1319 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, 1320 enable ? 0 : DSI_TE_EVENT); 1321 1322 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); 1323 1324 return true; 1325 } 1326 1327 int bdw_enable_vblank(struct drm_crtc *_crtc) 1328 { 1329 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1330 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1331 enum pipe pipe = crtc->pipe; 1332 unsigned long irqflags; 1333 1334 if (gen11_dsi_configure_te(crtc, true)) 1335 return 0; 1336 1337 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1338 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 1339 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1340 1341 /* Even if there is no DMC, frame counter can get stuck when 1342 * PSR is active as no frames are generated, so check only for PSR. 1343 */ 1344 if (HAS_PSR(dev_priv)) 1345 drm_crtc_vblank_restore(&crtc->base); 1346 1347 return 0; 1348 } 1349 1350 /* Called from drm generic code, passed 'crtc' which 1351 * we use as a pipe index 1352 */ 1353 void i8xx_disable_vblank(struct drm_crtc *crtc) 1354 { 1355 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1356 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1357 unsigned long irqflags; 1358 1359 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1360 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1361 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1362 } 1363 1364 void i915gm_disable_vblank(struct drm_crtc *crtc) 1365 { 1366 struct drm_i915_private *i915 = to_i915(crtc->dev); 1367 1368 i8xx_disable_vblank(crtc); 1369 1370 if (--i915->display.irq.vblank_enabled == 0) 1371 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1372 } 1373 1374 void i965_disable_vblank(struct drm_crtc *crtc) 1375 { 1376 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1377 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1378 unsigned long irqflags; 1379 1380 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1381 i915_disable_pipestat(dev_priv, pipe, 1382 PIPE_START_VBLANK_INTERRUPT_STATUS); 1383 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1384 } 1385 1386 void ilk_disable_vblank(struct drm_crtc *crtc) 1387 { 1388 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1389 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1390 unsigned long irqflags; 1391 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 1392 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1393 1394 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1395 ilk_disable_display_irq(dev_priv, bit); 1396 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1397 } 1398 1399 void bdw_disable_vblank(struct drm_crtc *_crtc) 1400 { 1401 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1403 enum pipe pipe = crtc->pipe; 1404 unsigned long irqflags; 1405 1406 if (gen11_dsi_configure_te(crtc, false)) 1407 return; 1408 1409 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1410 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 1411 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1412 } 1413 1414 void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 1415 { 1416 struct intel_uncore *uncore = &dev_priv->uncore; 1417 1418 if (IS_CHERRYVIEW(dev_priv)) 1419 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 1420 else 1421 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1422 1423 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); 1424 intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0); 1425 1426 i9xx_pipestat_irq_reset(dev_priv); 1427 1428 GEN3_IRQ_RESET(uncore, VLV_); 1429 dev_priv->irq_mask = ~0u; 1430 } 1431 1432 void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 1433 { 1434 struct intel_uncore *uncore = &dev_priv->uncore; 1435 1436 u32 pipestat_mask; 1437 u32 enable_mask; 1438 enum pipe pipe; 1439 1440 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 1441 1442 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1443 for_each_pipe(dev_priv, pipe) 1444 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); 1445 1446 enable_mask = I915_DISPLAY_PORT_INTERRUPT | 1447 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1448 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1449 I915_LPE_PIPE_A_INTERRUPT | 1450 I915_LPE_PIPE_B_INTERRUPT; 1451 1452 if (IS_CHERRYVIEW(dev_priv)) 1453 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 1454 I915_LPE_PIPE_C_INTERRUPT; 1455 1456 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); 1457 1458 dev_priv->irq_mask = ~enable_mask; 1459 1460 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); 1461 } 1462 1463 void gen8_display_irq_reset(struct drm_i915_private *dev_priv) 1464 { 1465 struct intel_uncore *uncore = &dev_priv->uncore; 1466 enum pipe pipe; 1467 1468 if (!HAS_DISPLAY(dev_priv)) 1469 return; 1470 1471 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 1472 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 1473 1474 for_each_pipe(dev_priv, pipe) 1475 if (intel_display_power_is_enabled(dev_priv, 1476 POWER_DOMAIN_PIPE(pipe))) 1477 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1478 1479 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 1480 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 1481 } 1482 1483 void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 1484 { 1485 struct intel_uncore *uncore = &dev_priv->uncore; 1486 enum pipe pipe; 1487 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1488 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 1489 1490 if (!HAS_DISPLAY(dev_priv)) 1491 return; 1492 1493 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); 1494 1495 if (DISPLAY_VER(dev_priv) >= 12) { 1496 enum transcoder trans; 1497 1498 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 1499 enum intel_display_power_domain domain; 1500 1501 domain = POWER_DOMAIN_TRANSCODER(trans); 1502 if (!intel_display_power_is_enabled(dev_priv, domain)) 1503 continue; 1504 1505 intel_uncore_write(uncore, 1506 TRANS_PSR_IMR(dev_priv, trans), 1507 0xffffffff); 1508 intel_uncore_write(uncore, 1509 TRANS_PSR_IIR(dev_priv, trans), 1510 0xffffffff); 1511 } 1512 } else { 1513 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 1514 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 1515 } 1516 1517 for_each_pipe(dev_priv, pipe) 1518 if (intel_display_power_is_enabled(dev_priv, 1519 POWER_DOMAIN_PIPE(pipe))) 1520 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1521 1522 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 1523 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 1524 1525 if (DISPLAY_VER(dev_priv) >= 14) 1526 GEN3_IRQ_RESET(uncore, PICAINTERRUPT_); 1527 else 1528 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); 1529 1530 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1531 GEN3_IRQ_RESET(uncore, SDE); 1532 } 1533 1534 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 1535 u8 pipe_mask) 1536 { 1537 struct intel_uncore *uncore = &dev_priv->uncore; 1538 u32 extra_ier = GEN8_PIPE_VBLANK | 1539 gen8_de_pipe_underrun_mask(dev_priv) | 1540 gen8_de_pipe_flip_done_mask(dev_priv); 1541 enum pipe pipe; 1542 1543 spin_lock_irq(&dev_priv->irq_lock); 1544 1545 if (!intel_irqs_enabled(dev_priv)) { 1546 spin_unlock_irq(&dev_priv->irq_lock); 1547 return; 1548 } 1549 1550 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 1551 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 1552 dev_priv->display.irq.de_irq_mask[pipe], 1553 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); 1554 1555 spin_unlock_irq(&dev_priv->irq_lock); 1556 } 1557 1558 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 1559 u8 pipe_mask) 1560 { 1561 struct intel_uncore *uncore = &dev_priv->uncore; 1562 enum pipe pipe; 1563 1564 spin_lock_irq(&dev_priv->irq_lock); 1565 1566 if (!intel_irqs_enabled(dev_priv)) { 1567 spin_unlock_irq(&dev_priv->irq_lock); 1568 return; 1569 } 1570 1571 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 1572 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1573 1574 spin_unlock_irq(&dev_priv->irq_lock); 1575 1576 /* make sure we're done processing display irqs */ 1577 intel_synchronize_irq(dev_priv); 1578 } 1579 1580 /* 1581 * SDEIER is also touched by the interrupt handler to work around missed PCH 1582 * interrupts. Hence we can't update it after the interrupt handler is enabled - 1583 * instead we unconditionally enable all PCH interrupt sources here, but then 1584 * only unmask them as needed with SDEIMR. 1585 * 1586 * Note that we currently do this after installing the interrupt handler, 1587 * but before we enable the master interrupt. That should be sufficient 1588 * to avoid races with the irq handler, assuming we have MSI. Shared legacy 1589 * interrupts could still race. 1590 */ 1591 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) 1592 { 1593 struct intel_uncore *uncore = &dev_priv->uncore; 1594 u32 mask; 1595 1596 if (HAS_PCH_NOP(dev_priv)) 1597 return; 1598 1599 if (HAS_PCH_IBX(dev_priv)) 1600 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 1601 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 1602 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 1603 else 1604 mask = SDE_GMBUS_CPT; 1605 1606 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 1607 } 1608 1609 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 1610 { 1611 lockdep_assert_held(&dev_priv->irq_lock); 1612 1613 if (dev_priv->display.irq.display_irqs_enabled) 1614 return; 1615 1616 dev_priv->display.irq.display_irqs_enabled = true; 1617 1618 if (intel_irqs_enabled(dev_priv)) { 1619 vlv_display_irq_reset(dev_priv); 1620 vlv_display_irq_postinstall(dev_priv); 1621 } 1622 } 1623 1624 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 1625 { 1626 lockdep_assert_held(&dev_priv->irq_lock); 1627 1628 if (!dev_priv->display.irq.display_irqs_enabled) 1629 return; 1630 1631 dev_priv->display.irq.display_irqs_enabled = false; 1632 1633 if (intel_irqs_enabled(dev_priv)) 1634 vlv_display_irq_reset(dev_priv); 1635 } 1636 1637 void ilk_de_irq_postinstall(struct drm_i915_private *i915) 1638 { 1639 struct intel_uncore *uncore = &i915->uncore; 1640 u32 display_mask, extra_mask; 1641 1642 if (DISPLAY_VER(i915) >= 7) { 1643 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 1644 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 1645 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 1646 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 1647 DE_PLANE_FLIP_DONE_IVB(PLANE_C) | 1648 DE_PLANE_FLIP_DONE_IVB(PLANE_B) | 1649 DE_PLANE_FLIP_DONE_IVB(PLANE_A) | 1650 DE_DP_A_HOTPLUG_IVB); 1651 } else { 1652 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1653 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 1654 DE_PIPEA_CRC_DONE | DE_POISON); 1655 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 1656 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 1657 DE_PLANE_FLIP_DONE(PLANE_A) | 1658 DE_PLANE_FLIP_DONE(PLANE_B) | 1659 DE_DP_A_HOTPLUG); 1660 } 1661 1662 if (IS_HASWELL(i915)) { 1663 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 1664 display_mask |= DE_EDP_PSR_INT_HSW; 1665 } 1666 1667 if (IS_IRONLAKE_M(i915)) 1668 extra_mask |= DE_PCU_EVENT; 1669 1670 i915->irq_mask = ~display_mask; 1671 1672 ibx_irq_postinstall(i915); 1673 1674 GEN3_IRQ_INIT(uncore, DE, i915->irq_mask, 1675 display_mask | extra_mask); 1676 } 1677 1678 static void mtp_irq_postinstall(struct drm_i915_private *i915); 1679 static void icp_irq_postinstall(struct drm_i915_private *i915); 1680 1681 void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 1682 { 1683 struct intel_uncore *uncore = &dev_priv->uncore; 1684 1685 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | 1686 GEN8_PIPE_CDCLK_CRC_DONE; 1687 u32 de_pipe_enables; 1688 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); 1689 u32 de_port_enables; 1690 u32 de_misc_masked = GEN8_DE_EDP_PSR; 1691 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1692 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 1693 enum pipe pipe; 1694 1695 if (!HAS_DISPLAY(dev_priv)) 1696 return; 1697 1698 if (DISPLAY_VER(dev_priv) >= 14) 1699 mtp_irq_postinstall(dev_priv); 1700 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1701 icp_irq_postinstall(dev_priv); 1702 else if (HAS_PCH_SPLIT(dev_priv)) 1703 ibx_irq_postinstall(dev_priv); 1704 1705 if (DISPLAY_VER(dev_priv) < 11) 1706 de_misc_masked |= GEN8_DE_MISC_GSE; 1707 1708 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1709 de_port_masked |= BXT_DE_PORT_GMBUS; 1710 1711 if (DISPLAY_VER(dev_priv) >= 14) { 1712 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR | 1713 XELPDP_PMDEMAND_RSP; 1714 } else if (DISPLAY_VER(dev_priv) >= 11) { 1715 enum port port; 1716 1717 if (intel_bios_is_dsi_present(dev_priv, &port)) 1718 de_port_masked |= DSI0_TE | DSI1_TE; 1719 } 1720 1721 de_pipe_enables = de_pipe_masked | 1722 GEN8_PIPE_VBLANK | 1723 gen8_de_pipe_underrun_mask(dev_priv) | 1724 gen8_de_pipe_flip_done_mask(dev_priv); 1725 1726 de_port_enables = de_port_masked; 1727 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1728 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 1729 else if (IS_BROADWELL(dev_priv)) 1730 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 1731 1732 if (DISPLAY_VER(dev_priv) >= 12) { 1733 enum transcoder trans; 1734 1735 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 1736 enum intel_display_power_domain domain; 1737 1738 domain = POWER_DOMAIN_TRANSCODER(trans); 1739 if (!intel_display_power_is_enabled(dev_priv, domain)) 1740 continue; 1741 1742 gen3_assert_iir_is_zero(uncore, 1743 TRANS_PSR_IIR(dev_priv, trans)); 1744 } 1745 } else { 1746 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 1747 } 1748 1749 for_each_pipe(dev_priv, pipe) { 1750 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; 1751 1752 if (intel_display_power_is_enabled(dev_priv, 1753 POWER_DOMAIN_PIPE(pipe))) 1754 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 1755 dev_priv->display.irq.de_irq_mask[pipe], 1756 de_pipe_enables); 1757 } 1758 1759 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); 1760 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); 1761 1762 if (IS_DISPLAY_VER(dev_priv, 11, 13)) { 1763 u32 de_hpd_masked = 0; 1764 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 1765 GEN11_DE_TBT_HOTPLUG_MASK; 1766 1767 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, 1768 de_hpd_enables); 1769 } 1770 } 1771 1772 static void mtp_irq_postinstall(struct drm_i915_private *i915) 1773 { 1774 struct intel_uncore *uncore = &i915->uncore; 1775 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; 1776 u32 de_hpd_mask = XELPDP_AUX_TC_MASK; 1777 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 1778 XELPDP_TBT_HOTPLUG_MASK; 1779 1780 GEN3_IRQ_INIT(uncore, PICAINTERRUPT_, ~de_hpd_mask, 1781 de_hpd_enables); 1782 1783 GEN3_IRQ_INIT(uncore, SDE, ~sde_mask, 0xffffffff); 1784 } 1785 1786 static void icp_irq_postinstall(struct drm_i915_private *dev_priv) 1787 { 1788 struct intel_uncore *uncore = &dev_priv->uncore; 1789 u32 mask = SDE_GMBUS_ICP; 1790 1791 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 1792 } 1793 1794 void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv) 1795 { 1796 if (!HAS_DISPLAY(dev_priv)) 1797 return; 1798 1799 gen8_de_irq_postinstall(dev_priv); 1800 1801 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, 1802 GEN11_DISPLAY_IRQ_ENABLE); 1803 } 1804 1805 void dg1_de_irq_postinstall(struct drm_i915_private *i915) 1806 { 1807 if (!HAS_DISPLAY(i915)) 1808 return; 1809 1810 gen8_de_irq_postinstall(i915); 1811 intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL, 1812 GEN11_DISPLAY_IRQ_ENABLE); 1813 } 1814 1815 void intel_display_irq_init(struct drm_i915_private *i915) 1816 { 1817 i915->drm.vblank_disable_immediate = true; 1818 1819 /* 1820 * Most platforms treat the display irq block as an always-on power 1821 * domain. vlv/chv can disable it at runtime and need special care to 1822 * avoid writing any of the display block registers outside of the power 1823 * domain. We defer setting up the display irqs in this case to the 1824 * runtime pm. 1825 */ 1826 i915->display.irq.display_irqs_enabled = true; 1827 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 1828 i915->display.irq.display_irqs_enabled = false; 1829 1830 intel_hotplug_irq_init(i915); 1831 } 1832