1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "gt/intel_rps.h" 7 #include "i915_drv.h" 8 #include "i915_irq.h" 9 #include "i915_reg.h" 10 #include "icl_dsi_regs.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_irq.h" 14 #include "intel_display_trace.h" 15 #include "intel_display_types.h" 16 #include "intel_dp_aux.h" 17 #include "intel_dsb.h" 18 #include "intel_fdi_regs.h" 19 #include "intel_fifo_underrun.h" 20 #include "intel_gmbus.h" 21 #include "intel_hotplug_irq.h" 22 #include "intel_pipe_crc_regs.h" 23 #include "intel_pmdemand.h" 24 #include "intel_psr.h" 25 #include "intel_psr_regs.h" 26 27 static void 28 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 29 { 30 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 31 32 drm_crtc_handle_vblank(&crtc->base); 33 } 34 35 /** 36 * ilk_update_display_irq - update DEIMR 37 * @dev_priv: driver private 38 * @interrupt_mask: mask of interrupt bits to update 39 * @enabled_irq_mask: mask of interrupt bits to enable 40 */ 41 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 42 u32 interrupt_mask, u32 enabled_irq_mask) 43 { 44 u32 new_val; 45 46 lockdep_assert_held(&dev_priv->irq_lock); 47 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 48 49 new_val = dev_priv->irq_mask; 50 new_val &= ~interrupt_mask; 51 new_val |= (~enabled_irq_mask & interrupt_mask); 52 53 if (new_val != dev_priv->irq_mask && 54 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { 55 dev_priv->irq_mask = new_val; 56 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); 57 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); 58 } 59 } 60 61 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits) 62 { 63 ilk_update_display_irq(i915, bits, bits); 64 } 65 66 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits) 67 { 68 ilk_update_display_irq(i915, bits, 0); 69 } 70 71 /** 72 * bdw_update_port_irq - update DE port interrupt 73 * @dev_priv: driver private 74 * @interrupt_mask: mask of interrupt bits to update 75 * @enabled_irq_mask: mask of interrupt bits to enable 76 */ 77 void bdw_update_port_irq(struct drm_i915_private *dev_priv, 78 u32 interrupt_mask, u32 enabled_irq_mask) 79 { 80 u32 new_val; 81 u32 old_val; 82 83 lockdep_assert_held(&dev_priv->irq_lock); 84 85 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 86 87 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 88 return; 89 90 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 91 92 new_val = old_val; 93 new_val &= ~interrupt_mask; 94 new_val |= (~enabled_irq_mask & interrupt_mask); 95 96 if (new_val != old_val) { 97 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); 98 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 99 } 100 } 101 102 /** 103 * bdw_update_pipe_irq - update DE pipe interrupt 104 * @dev_priv: driver private 105 * @pipe: pipe whose interrupt to update 106 * @interrupt_mask: mask of interrupt bits to update 107 * @enabled_irq_mask: mask of interrupt bits to enable 108 */ 109 static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 110 enum pipe pipe, u32 interrupt_mask, 111 u32 enabled_irq_mask) 112 { 113 u32 new_val; 114 115 lockdep_assert_held(&dev_priv->irq_lock); 116 117 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 118 119 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 120 return; 121 122 new_val = dev_priv->display.irq.de_irq_mask[pipe]; 123 new_val &= ~interrupt_mask; 124 new_val |= (~enabled_irq_mask & interrupt_mask); 125 126 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { 127 dev_priv->display.irq.de_irq_mask[pipe] = new_val; 128 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), 129 dev_priv->display.irq.de_irq_mask[pipe]); 130 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); 131 } 132 } 133 134 void bdw_enable_pipe_irq(struct drm_i915_private *i915, 135 enum pipe pipe, u32 bits) 136 { 137 bdw_update_pipe_irq(i915, pipe, bits, bits); 138 } 139 140 void bdw_disable_pipe_irq(struct drm_i915_private *i915, 141 enum pipe pipe, u32 bits) 142 { 143 bdw_update_pipe_irq(i915, pipe, bits, 0); 144 } 145 146 /** 147 * ibx_display_interrupt_update - update SDEIMR 148 * @dev_priv: driver private 149 * @interrupt_mask: mask of interrupt bits to update 150 * @enabled_irq_mask: mask of interrupt bits to enable 151 */ 152 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 153 u32 interrupt_mask, 154 u32 enabled_irq_mask) 155 { 156 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); 157 158 sdeimr &= ~interrupt_mask; 159 sdeimr |= (~enabled_irq_mask & interrupt_mask); 160 161 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 162 163 lockdep_assert_held(&dev_priv->irq_lock); 164 165 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 166 return; 167 168 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); 169 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); 170 } 171 172 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits) 173 { 174 ibx_display_interrupt_update(i915, bits, bits); 175 } 176 177 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits) 178 { 179 ibx_display_interrupt_update(i915, bits, 0); 180 } 181 182 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 183 enum pipe pipe) 184 { 185 u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe]; 186 u32 enable_mask = status_mask << 16; 187 188 lockdep_assert_held(&dev_priv->irq_lock); 189 190 if (DISPLAY_VER(dev_priv) < 5) 191 goto out; 192 193 /* 194 * On pipe A we don't support the PSR interrupt yet, 195 * on pipe B and C the same bit MBZ. 196 */ 197 if (drm_WARN_ON_ONCE(&dev_priv->drm, 198 status_mask & PIPE_A_PSR_STATUS_VLV)) 199 return 0; 200 /* 201 * On pipe B and C we don't support the PSR interrupt yet, on pipe 202 * A the same bit is for perf counters which we don't use either. 203 */ 204 if (drm_WARN_ON_ONCE(&dev_priv->drm, 205 status_mask & PIPE_B_PSR_STATUS_VLV)) 206 return 0; 207 208 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 209 SPRITE0_FLIP_DONE_INT_EN_VLV | 210 SPRITE1_FLIP_DONE_INT_EN_VLV); 211 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 212 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 213 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 214 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 215 216 out: 217 drm_WARN_ONCE(&dev_priv->drm, 218 enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 219 status_mask & ~PIPESTAT_INT_STATUS_MASK, 220 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 221 pipe_name(pipe), enable_mask, status_mask); 222 223 return enable_mask; 224 } 225 226 void i915_enable_pipestat(struct drm_i915_private *dev_priv, 227 enum pipe pipe, u32 status_mask) 228 { 229 i915_reg_t reg = PIPESTAT(dev_priv, pipe); 230 u32 enable_mask; 231 232 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 233 "pipe %c: status_mask=0x%x\n", 234 pipe_name(pipe), status_mask); 235 236 lockdep_assert_held(&dev_priv->irq_lock); 237 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 238 239 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) 240 return; 241 242 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; 243 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 244 245 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 246 intel_uncore_posting_read(&dev_priv->uncore, reg); 247 } 248 249 void i915_disable_pipestat(struct drm_i915_private *dev_priv, 250 enum pipe pipe, u32 status_mask) 251 { 252 i915_reg_t reg = PIPESTAT(dev_priv, pipe); 253 u32 enable_mask; 254 255 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 256 "pipe %c: status_mask=0x%x\n", 257 pipe_name(pipe), status_mask); 258 259 lockdep_assert_held(&dev_priv->irq_lock); 260 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 261 262 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0) 263 return; 264 265 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; 266 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 267 268 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 269 intel_uncore_posting_read(&dev_priv->uncore, reg); 270 } 271 272 static bool i915_has_asle(struct drm_i915_private *i915) 273 { 274 struct intel_display *display = &i915->display; 275 276 if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915)) 277 return false; 278 279 return intel_opregion_asle_present(display); 280 } 281 282 /** 283 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 284 * @dev_priv: i915 device private 285 */ 286 void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) 287 { 288 if (!i915_has_asle(dev_priv)) 289 return; 290 291 spin_lock_irq(&dev_priv->irq_lock); 292 293 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 294 if (DISPLAY_VER(dev_priv) >= 4) 295 i915_enable_pipestat(dev_priv, PIPE_A, 296 PIPE_LEGACY_BLC_EVENT_STATUS); 297 298 spin_unlock_irq(&dev_priv->irq_lock); 299 } 300 301 #if defined(CONFIG_DEBUG_FS) 302 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 303 enum pipe pipe, 304 u32 crc0, u32 crc1, 305 u32 crc2, u32 crc3, 306 u32 crc4) 307 { 308 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 309 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 310 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 311 312 trace_intel_pipe_crc(crtc, crcs); 313 314 spin_lock(&pipe_crc->lock); 315 /* 316 * For some not yet identified reason, the first CRC is 317 * bonkers. So let's just wait for the next vblank and read 318 * out the buggy result. 319 * 320 * On GEN8+ sometimes the second CRC is bonkers as well, so 321 * don't trust that one either. 322 */ 323 if (pipe_crc->skipped <= 0 || 324 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { 325 pipe_crc->skipped++; 326 spin_unlock(&pipe_crc->lock); 327 return; 328 } 329 spin_unlock(&pipe_crc->lock); 330 331 drm_crtc_add_crc_entry(&crtc->base, true, 332 drm_crtc_accurate_vblank_count(&crtc->base), 333 crcs); 334 } 335 #else 336 static inline void 337 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 338 enum pipe pipe, 339 u32 crc0, u32 crc1, 340 u32 crc2, u32 crc3, 341 u32 crc4) {} 342 #endif 343 344 static void flip_done_handler(struct drm_i915_private *i915, 345 enum pipe pipe) 346 { 347 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe); 348 349 spin_lock(&i915->drm.event_lock); 350 351 if (crtc->flip_done_event) { 352 trace_intel_crtc_flip_done(crtc); 353 drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event); 354 crtc->flip_done_event = NULL; 355 } 356 357 spin_unlock(&i915->drm.event_lock); 358 } 359 360 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 361 enum pipe pipe) 362 { 363 display_pipe_crc_irq_handler(dev_priv, pipe, 364 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), 365 0, 0, 0, 0); 366 } 367 368 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 369 enum pipe pipe) 370 { 371 display_pipe_crc_irq_handler(dev_priv, pipe, 372 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 373 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), 374 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), 375 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), 376 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); 377 } 378 379 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 380 enum pipe pipe) 381 { 382 u32 res1, res2; 383 384 if (DISPLAY_VER(dev_priv) >= 3) 385 res1 = intel_uncore_read(&dev_priv->uncore, 386 PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); 387 else 388 res1 = 0; 389 390 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 391 res2 = intel_uncore_read(&dev_priv->uncore, 392 PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); 393 else 394 res2 = 0; 395 396 display_pipe_crc_irq_handler(dev_priv, pipe, 397 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), 398 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), 399 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), 400 res1, res2); 401 } 402 403 void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) 404 { 405 enum pipe pipe; 406 407 for_each_pipe(dev_priv, pipe) { 408 intel_uncore_write(&dev_priv->uncore, 409 PIPESTAT(dev_priv, pipe), 410 PIPESTAT_INT_STATUS_MASK | 411 PIPE_FIFO_UNDERRUN_STATUS); 412 413 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; 414 } 415 } 416 417 void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, 418 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 419 { 420 enum pipe pipe; 421 422 spin_lock(&dev_priv->irq_lock); 423 424 if (!dev_priv->display.irq.display_irqs_enabled) { 425 spin_unlock(&dev_priv->irq_lock); 426 return; 427 } 428 429 for_each_pipe(dev_priv, pipe) { 430 i915_reg_t reg; 431 u32 status_mask, enable_mask, iir_bit = 0; 432 433 /* 434 * PIPESTAT bits get signalled even when the interrupt is 435 * disabled with the mask bits, and some of the status bits do 436 * not generate interrupts at all (like the underrun bit). Hence 437 * we need to be careful that we only handle what we want to 438 * handle. 439 */ 440 441 /* fifo underruns are filterered in the underrun handler. */ 442 status_mask = PIPE_FIFO_UNDERRUN_STATUS; 443 444 switch (pipe) { 445 default: 446 case PIPE_A: 447 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 448 break; 449 case PIPE_B: 450 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 451 break; 452 case PIPE_C: 453 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 454 break; 455 } 456 if (iir & iir_bit) 457 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe]; 458 459 if (!status_mask) 460 continue; 461 462 reg = PIPESTAT(dev_priv, pipe); 463 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; 464 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 465 466 /* 467 * Clear the PIPE*STAT regs before the IIR 468 * 469 * Toggle the enable bits to make sure we get an 470 * edge in the ISR pipe event bit if we don't clear 471 * all the enabled status bits. Otherwise the edge 472 * triggered IIR on i965/g4x wouldn't notice that 473 * an interrupt is still pending. 474 */ 475 if (pipe_stats[pipe]) { 476 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); 477 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); 478 } 479 } 480 spin_unlock(&dev_priv->irq_lock); 481 } 482 483 void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, 484 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) 485 { 486 enum pipe pipe; 487 488 for_each_pipe(dev_priv, pipe) { 489 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 490 intel_handle_vblank(dev_priv, pipe); 491 492 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 493 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 494 495 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 496 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 497 } 498 } 499 500 void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, 501 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 502 { 503 struct intel_display *display = &dev_priv->display; 504 505 bool blc_event = false; 506 enum pipe pipe; 507 508 for_each_pipe(dev_priv, pipe) { 509 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 510 intel_handle_vblank(dev_priv, pipe); 511 512 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 513 blc_event = true; 514 515 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 516 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 517 518 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 519 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 520 } 521 522 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 523 intel_opregion_asle_intr(display); 524 } 525 526 void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, 527 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 528 { 529 struct intel_display *display = &dev_priv->display; 530 bool blc_event = false; 531 enum pipe pipe; 532 533 for_each_pipe(dev_priv, pipe) { 534 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 535 intel_handle_vblank(dev_priv, pipe); 536 537 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 538 blc_event = true; 539 540 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 541 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 542 543 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 544 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 545 } 546 547 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 548 intel_opregion_asle_intr(display); 549 550 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 551 intel_gmbus_irq_handler(dev_priv); 552 } 553 554 void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, 555 u32 pipe_stats[I915_MAX_PIPES]) 556 { 557 enum pipe pipe; 558 559 for_each_pipe(dev_priv, pipe) { 560 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 561 intel_handle_vblank(dev_priv, pipe); 562 563 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) 564 flip_done_handler(dev_priv, pipe); 565 566 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 567 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 568 569 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 570 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 571 } 572 573 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 574 intel_gmbus_irq_handler(dev_priv); 575 } 576 577 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 578 { 579 enum pipe pipe; 580 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 581 582 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 583 584 if (pch_iir & SDE_AUDIO_POWER_MASK) { 585 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 586 SDE_AUDIO_POWER_SHIFT); 587 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", 588 port_name(port)); 589 } 590 591 if (pch_iir & SDE_AUX_MASK) 592 intel_dp_aux_irq_handler(dev_priv); 593 594 if (pch_iir & SDE_GMBUS) 595 intel_gmbus_irq_handler(dev_priv); 596 597 if (pch_iir & SDE_AUDIO_HDCP_MASK) 598 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); 599 600 if (pch_iir & SDE_AUDIO_TRANS_MASK) 601 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); 602 603 if (pch_iir & SDE_POISON) 604 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 605 606 if (pch_iir & SDE_FDI_MASK) { 607 for_each_pipe(dev_priv, pipe) 608 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 609 pipe_name(pipe), 610 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 611 } 612 613 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 614 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); 615 616 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 617 drm_dbg(&dev_priv->drm, 618 "PCH transcoder CRC error interrupt\n"); 619 620 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 621 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); 622 623 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 624 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); 625 } 626 627 static void ivb_err_int_handler(struct drm_i915_private *dev_priv) 628 { 629 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); 630 enum pipe pipe; 631 632 if (err_int & ERR_INT_POISON) 633 drm_err(&dev_priv->drm, "Poison interrupt\n"); 634 635 for_each_pipe(dev_priv, pipe) { 636 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 637 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 638 639 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 640 if (IS_IVYBRIDGE(dev_priv)) 641 ivb_pipe_crc_irq_handler(dev_priv, pipe); 642 else 643 hsw_pipe_crc_irq_handler(dev_priv, pipe); 644 } 645 } 646 647 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); 648 } 649 650 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) 651 { 652 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); 653 enum pipe pipe; 654 655 if (serr_int & SERR_INT_POISON) 656 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 657 658 for_each_pipe(dev_priv, pipe) 659 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 660 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); 661 662 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); 663 } 664 665 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 666 { 667 enum pipe pipe; 668 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 669 670 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 671 672 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 673 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 674 SDE_AUDIO_POWER_SHIFT_CPT); 675 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", 676 port_name(port)); 677 } 678 679 if (pch_iir & SDE_AUX_MASK_CPT) 680 intel_dp_aux_irq_handler(dev_priv); 681 682 if (pch_iir & SDE_GMBUS_CPT) 683 intel_gmbus_irq_handler(dev_priv); 684 685 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 686 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); 687 688 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 689 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); 690 691 if (pch_iir & SDE_FDI_MASK_CPT) { 692 for_each_pipe(dev_priv, pipe) 693 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 694 pipe_name(pipe), 695 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 696 } 697 698 if (pch_iir & SDE_ERROR_CPT) 699 cpt_serr_int_handler(dev_priv); 700 } 701 702 void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 703 { 704 struct intel_display *display = &dev_priv->display; 705 enum pipe pipe; 706 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 707 708 if (hotplug_trigger) 709 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 710 711 if (de_iir & DE_AUX_CHANNEL_A) 712 intel_dp_aux_irq_handler(dev_priv); 713 714 if (de_iir & DE_GSE) 715 intel_opregion_asle_intr(display); 716 717 if (de_iir & DE_POISON) 718 drm_err(&dev_priv->drm, "Poison interrupt\n"); 719 720 for_each_pipe(dev_priv, pipe) { 721 if (de_iir & DE_PIPE_VBLANK(pipe)) 722 intel_handle_vblank(dev_priv, pipe); 723 724 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) 725 flip_done_handler(dev_priv, pipe); 726 727 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 728 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 729 730 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 731 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 732 } 733 734 /* check event from PCH */ 735 if (de_iir & DE_PCH_EVENT) { 736 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 737 738 if (HAS_PCH_CPT(dev_priv)) 739 cpt_irq_handler(dev_priv, pch_iir); 740 else 741 ibx_irq_handler(dev_priv, pch_iir); 742 743 /* should clear PCH hotplug event before clear CPU irq */ 744 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 745 } 746 747 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT) 748 gen5_rps_irq_handler(&to_gt(dev_priv)->rps); 749 } 750 751 void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 752 { 753 struct intel_display *display = &dev_priv->display; 754 enum pipe pipe; 755 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 756 757 if (hotplug_trigger) 758 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 759 760 if (de_iir & DE_ERR_INT_IVB) 761 ivb_err_int_handler(dev_priv); 762 763 if (de_iir & DE_EDP_PSR_INT_HSW) { 764 struct intel_encoder *encoder; 765 766 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 767 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 768 u32 psr_iir; 769 770 psr_iir = intel_uncore_rmw(&dev_priv->uncore, 771 EDP_PSR_IIR, 0, 0); 772 intel_psr_irq_handler(intel_dp, psr_iir); 773 break; 774 } 775 } 776 777 if (de_iir & DE_AUX_CHANNEL_A_IVB) 778 intel_dp_aux_irq_handler(dev_priv); 779 780 if (de_iir & DE_GSE_IVB) 781 intel_opregion_asle_intr(display); 782 783 for_each_pipe(dev_priv, pipe) { 784 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 785 intel_handle_vblank(dev_priv, pipe); 786 787 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) 788 flip_done_handler(dev_priv, pipe); 789 } 790 791 /* check event from PCH */ 792 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { 793 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 794 795 cpt_irq_handler(dev_priv, pch_iir); 796 797 /* clear PCH hotplug event before clear CPU irq */ 798 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 799 } 800 } 801 802 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 803 { 804 u32 mask; 805 806 if (DISPLAY_VER(dev_priv) >= 20) 807 return 0; 808 else if (DISPLAY_VER(dev_priv) >= 14) 809 return TGL_DE_PORT_AUX_DDIA | 810 TGL_DE_PORT_AUX_DDIB; 811 else if (DISPLAY_VER(dev_priv) >= 13) 812 return TGL_DE_PORT_AUX_DDIA | 813 TGL_DE_PORT_AUX_DDIB | 814 TGL_DE_PORT_AUX_DDIC | 815 XELPD_DE_PORT_AUX_DDID | 816 XELPD_DE_PORT_AUX_DDIE | 817 TGL_DE_PORT_AUX_USBC1 | 818 TGL_DE_PORT_AUX_USBC2 | 819 TGL_DE_PORT_AUX_USBC3 | 820 TGL_DE_PORT_AUX_USBC4; 821 else if (DISPLAY_VER(dev_priv) >= 12) 822 return TGL_DE_PORT_AUX_DDIA | 823 TGL_DE_PORT_AUX_DDIB | 824 TGL_DE_PORT_AUX_DDIC | 825 TGL_DE_PORT_AUX_USBC1 | 826 TGL_DE_PORT_AUX_USBC2 | 827 TGL_DE_PORT_AUX_USBC3 | 828 TGL_DE_PORT_AUX_USBC4 | 829 TGL_DE_PORT_AUX_USBC5 | 830 TGL_DE_PORT_AUX_USBC6; 831 832 mask = GEN8_AUX_CHANNEL_A; 833 if (DISPLAY_VER(dev_priv) >= 9) 834 mask |= GEN9_AUX_CHANNEL_B | 835 GEN9_AUX_CHANNEL_C | 836 GEN9_AUX_CHANNEL_D; 837 838 if (DISPLAY_VER(dev_priv) == 11) { 839 mask |= ICL_AUX_CHANNEL_F; 840 mask |= ICL_AUX_CHANNEL_E; 841 } 842 843 return mask; 844 } 845 846 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) 847 { 848 if (DISPLAY_VER(dev_priv) >= 14) 849 return MTL_PIPEDMC_ATS_FAULT | 850 MTL_PLANE_ATS_FAULT | 851 GEN12_PIPEDMC_FAULT | 852 GEN9_PIPE_CURSOR_FAULT | 853 GEN11_PIPE_PLANE5_FAULT | 854 GEN9_PIPE_PLANE4_FAULT | 855 GEN9_PIPE_PLANE3_FAULT | 856 GEN9_PIPE_PLANE2_FAULT | 857 GEN9_PIPE_PLANE1_FAULT; 858 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 859 return GEN12_PIPEDMC_FAULT | 860 GEN9_PIPE_CURSOR_FAULT | 861 GEN11_PIPE_PLANE5_FAULT | 862 GEN9_PIPE_PLANE4_FAULT | 863 GEN9_PIPE_PLANE3_FAULT | 864 GEN9_PIPE_PLANE2_FAULT | 865 GEN9_PIPE_PLANE1_FAULT; 866 else if (DISPLAY_VER(dev_priv) == 12) 867 return GEN12_PIPEDMC_FAULT | 868 GEN9_PIPE_CURSOR_FAULT | 869 GEN11_PIPE_PLANE7_FAULT | 870 GEN11_PIPE_PLANE6_FAULT | 871 GEN11_PIPE_PLANE5_FAULT | 872 GEN9_PIPE_PLANE4_FAULT | 873 GEN9_PIPE_PLANE3_FAULT | 874 GEN9_PIPE_PLANE2_FAULT | 875 GEN9_PIPE_PLANE1_FAULT; 876 else if (DISPLAY_VER(dev_priv) == 11) 877 return GEN9_PIPE_CURSOR_FAULT | 878 GEN11_PIPE_PLANE7_FAULT | 879 GEN11_PIPE_PLANE6_FAULT | 880 GEN11_PIPE_PLANE5_FAULT | 881 GEN9_PIPE_PLANE4_FAULT | 882 GEN9_PIPE_PLANE3_FAULT | 883 GEN9_PIPE_PLANE2_FAULT | 884 GEN9_PIPE_PLANE1_FAULT; 885 else if (DISPLAY_VER(dev_priv) >= 9) 886 return GEN9_PIPE_CURSOR_FAULT | 887 GEN9_PIPE_PLANE4_FAULT | 888 GEN9_PIPE_PLANE3_FAULT | 889 GEN9_PIPE_PLANE2_FAULT | 890 GEN9_PIPE_PLANE1_FAULT; 891 else 892 return GEN8_PIPE_CURSOR_FAULT | 893 GEN8_PIPE_SPRITE_FAULT | 894 GEN8_PIPE_PRIMARY_FAULT; 895 } 896 897 static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv) 898 { 899 wake_up_all(&dev_priv->display.pmdemand.waitqueue); 900 } 901 902 static void 903 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 904 { 905 struct intel_display *display = &dev_priv->display; 906 bool found = false; 907 908 if (DISPLAY_VER(dev_priv) >= 14) { 909 if (iir & (XELPDP_PMDEMAND_RSP | 910 XELPDP_PMDEMAND_RSPTOUT_ERR)) { 911 if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) 912 drm_dbg(&dev_priv->drm, 913 "Error waiting for Punit PM Demand Response\n"); 914 915 intel_pmdemand_irq_handler(dev_priv); 916 found = true; 917 } 918 919 if (iir & XELPDP_RM_TIMEOUT) { 920 u32 val = intel_uncore_read(&dev_priv->uncore, 921 RM_TIMEOUT_REG_CAPTURE); 922 drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val); 923 found = true; 924 } 925 } else if (iir & GEN8_DE_MISC_GSE) { 926 intel_opregion_asle_intr(display); 927 found = true; 928 } 929 930 if (iir & GEN8_DE_EDP_PSR) { 931 struct intel_encoder *encoder; 932 u32 psr_iir; 933 i915_reg_t iir_reg; 934 935 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 936 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 937 938 if (DISPLAY_VER(dev_priv) >= 12) 939 iir_reg = TRANS_PSR_IIR(dev_priv, 940 intel_dp->psr.transcoder); 941 else 942 iir_reg = EDP_PSR_IIR; 943 944 psr_iir = intel_uncore_rmw(&dev_priv->uncore, iir_reg, 0, 0); 945 946 if (psr_iir) 947 found = true; 948 949 intel_psr_irq_handler(intel_dp, psr_iir); 950 951 /* prior GEN12 only have one EDP PSR */ 952 if (DISPLAY_VER(dev_priv) < 12) 953 break; 954 } 955 } 956 957 if (!found) 958 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir); 959 } 960 961 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, 962 u32 te_trigger) 963 { 964 enum pipe pipe = INVALID_PIPE; 965 enum transcoder dsi_trans; 966 enum port port; 967 u32 val; 968 969 /* 970 * Incase of dual link, TE comes from DSI_1 971 * this is to check if dual link is enabled 972 */ 973 val = intel_uncore_read(&dev_priv->uncore, 974 TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0)); 975 val &= PORT_SYNC_MODE_ENABLE; 976 977 /* 978 * if dual link is enabled, then read DSI_0 979 * transcoder registers 980 */ 981 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 982 PORT_A : PORT_B; 983 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 984 985 /* Check if DSI configured in command mode */ 986 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); 987 val = val & OP_MODE_MASK; 988 989 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 990 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); 991 return; 992 } 993 994 /* Get PIPE for handling VBLANK event */ 995 val = intel_uncore_read(&dev_priv->uncore, 996 TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); 997 switch (val & TRANS_DDI_EDP_INPUT_MASK) { 998 case TRANS_DDI_EDP_INPUT_A_ON: 999 pipe = PIPE_A; 1000 break; 1001 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1002 pipe = PIPE_B; 1003 break; 1004 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1005 pipe = PIPE_C; 1006 break; 1007 default: 1008 drm_err(&dev_priv->drm, "Invalid PIPE\n"); 1009 return; 1010 } 1011 1012 intel_handle_vblank(dev_priv, pipe); 1013 1014 /* clear TE in dsi IIR */ 1015 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 1016 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); 1017 } 1018 1019 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) 1020 { 1021 if (DISPLAY_VER(i915) >= 9) 1022 return GEN9_PIPE_PLANE1_FLIP_DONE; 1023 else 1024 return GEN8_PIPE_PRIMARY_FLIP_DONE; 1025 } 1026 1027 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv) 1028 { 1029 u32 mask = GEN8_PIPE_FIFO_UNDERRUN; 1030 1031 if (DISPLAY_VER(dev_priv) >= 13) 1032 mask |= XELPD_PIPE_SOFT_UNDERRUN | 1033 XELPD_PIPE_HARD_UNDERRUN; 1034 1035 return mask; 1036 } 1037 1038 static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir) 1039 { 1040 u32 pica_ier = 0; 1041 1042 *pica_iir = 0; 1043 *pch_iir = intel_de_read(i915, SDEIIR); 1044 if (!*pch_iir) 1045 return; 1046 1047 /** 1048 * PICA IER must be disabled/re-enabled around clearing PICA IIR and 1049 * SDEIIR, to avoid losing PICA IRQs and to ensure that such IRQs set 1050 * their flags both in the PICA and SDE IIR. 1051 */ 1052 if (*pch_iir & SDE_PICAINTERRUPT) { 1053 drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL); 1054 1055 pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0); 1056 *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR); 1057 intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir); 1058 } 1059 1060 intel_de_write(i915, SDEIIR, *pch_iir); 1061 1062 if (pica_ier) 1063 intel_de_write(i915, PICAINTERRUPT_IER, pica_ier); 1064 } 1065 1066 void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 1067 { 1068 u32 iir; 1069 enum pipe pipe; 1070 1071 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); 1072 1073 if (master_ctl & GEN8_DE_MISC_IRQ) { 1074 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); 1075 if (iir) { 1076 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); 1077 gen8_de_misc_irq_handler(dev_priv, iir); 1078 } else { 1079 drm_err_ratelimited(&dev_priv->drm, 1080 "The master control interrupt lied (DE MISC)!\n"); 1081 } 1082 } 1083 1084 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 1085 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); 1086 if (iir) { 1087 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); 1088 gen11_hpd_irq_handler(dev_priv, iir); 1089 } else { 1090 drm_err_ratelimited(&dev_priv->drm, 1091 "The master control interrupt lied, (DE HPD)!\n"); 1092 } 1093 } 1094 1095 if (master_ctl & GEN8_DE_PORT_IRQ) { 1096 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); 1097 if (iir) { 1098 bool found = false; 1099 1100 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); 1101 1102 if (iir & gen8_de_port_aux_mask(dev_priv)) { 1103 intel_dp_aux_irq_handler(dev_priv); 1104 found = true; 1105 } 1106 1107 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1108 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 1109 1110 if (hotplug_trigger) { 1111 bxt_hpd_irq_handler(dev_priv, hotplug_trigger); 1112 found = true; 1113 } 1114 } else if (IS_BROADWELL(dev_priv)) { 1115 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 1116 1117 if (hotplug_trigger) { 1118 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 1119 found = true; 1120 } 1121 } 1122 1123 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1124 (iir & BXT_DE_PORT_GMBUS)) { 1125 intel_gmbus_irq_handler(dev_priv); 1126 found = true; 1127 } 1128 1129 if (DISPLAY_VER(dev_priv) >= 11) { 1130 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 1131 1132 if (te_trigger) { 1133 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger); 1134 found = true; 1135 } 1136 } 1137 1138 if (!found) 1139 drm_err_ratelimited(&dev_priv->drm, 1140 "Unexpected DE Port interrupt\n"); 1141 } else { 1142 drm_err_ratelimited(&dev_priv->drm, 1143 "The master control interrupt lied (DE PORT)!\n"); 1144 } 1145 } 1146 1147 for_each_pipe(dev_priv, pipe) { 1148 u32 fault_errors; 1149 1150 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1151 continue; 1152 1153 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); 1154 if (!iir) { 1155 drm_err_ratelimited(&dev_priv->drm, 1156 "The master control interrupt lied (DE PIPE)!\n"); 1157 continue; 1158 } 1159 1160 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); 1161 1162 if (iir & GEN8_PIPE_VBLANK) 1163 intel_handle_vblank(dev_priv, pipe); 1164 1165 if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) 1166 flip_done_handler(dev_priv, pipe); 1167 1168 if (HAS_DSB(dev_priv)) { 1169 if (iir & GEN12_DSB_INT(INTEL_DSB_0)) 1170 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); 1171 1172 if (iir & GEN12_DSB_INT(INTEL_DSB_1)) 1173 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); 1174 1175 if (iir & GEN12_DSB_INT(INTEL_DSB_2)) 1176 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); 1177 } 1178 1179 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 1180 hsw_pipe_crc_irq_handler(dev_priv, pipe); 1181 1182 if (iir & gen8_de_pipe_underrun_mask(dev_priv)) 1183 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1184 1185 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); 1186 if (fault_errors) 1187 drm_err_ratelimited(&dev_priv->drm, 1188 "Fault errors on pipe %c: 0x%08x\n", 1189 pipe_name(pipe), 1190 fault_errors); 1191 } 1192 1193 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && 1194 master_ctl & GEN8_DE_PCH_IRQ) { 1195 u32 pica_iir; 1196 1197 /* 1198 * FIXME(BDW): Assume for now that the new interrupt handling 1199 * scheme also closed the SDE interrupt handling race we've seen 1200 * on older pch-split platforms. But this needs testing. 1201 */ 1202 gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir); 1203 if (iir) { 1204 if (pica_iir) 1205 xelpdp_pica_irq_handler(dev_priv, pica_iir); 1206 1207 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1208 icp_irq_handler(dev_priv, iir); 1209 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 1210 spt_irq_handler(dev_priv, iir); 1211 else 1212 cpt_irq_handler(dev_priv, iir); 1213 } else { 1214 /* 1215 * Like on previous PCH there seems to be something 1216 * fishy going on with forwarding PCH interrupts. 1217 */ 1218 drm_dbg(&dev_priv->drm, 1219 "The master control interrupt lied (SDE)!\n"); 1220 } 1221 } 1222 } 1223 1224 u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl) 1225 { 1226 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 1227 u32 iir; 1228 1229 if (!(master_ctl & GEN11_GU_MISC_IRQ)) 1230 return 0; 1231 1232 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); 1233 if (likely(iir)) 1234 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir); 1235 1236 return iir; 1237 } 1238 1239 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir) 1240 { 1241 struct intel_display *display = &i915->display; 1242 1243 if (iir & GEN11_GU_MISC_GSE) 1244 intel_opregion_asle_intr(display); 1245 } 1246 1247 void gen11_display_irq_handler(struct drm_i915_private *i915) 1248 { 1249 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 1250 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); 1251 1252 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1253 /* 1254 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 1255 * for the display related bits. 1256 */ 1257 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0); 1258 gen8_de_irq_handler(i915, disp_ctl); 1259 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 1260 GEN11_DISPLAY_IRQ_ENABLE); 1261 1262 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1263 } 1264 1265 /* Called from drm generic code, passed 'crtc' which 1266 * we use as a pipe index 1267 */ 1268 int i8xx_enable_vblank(struct drm_crtc *crtc) 1269 { 1270 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1271 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1272 unsigned long irqflags; 1273 1274 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1275 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1276 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1277 1278 return 0; 1279 } 1280 1281 int i915gm_enable_vblank(struct drm_crtc *crtc) 1282 { 1283 struct drm_i915_private *i915 = to_i915(crtc->dev); 1284 1285 /* 1286 * Vblank interrupts fail to wake the device up from C2+. 1287 * Disabling render clock gating during C-states avoids 1288 * the problem. There is a small power cost so we do this 1289 * only when vblank interrupts are actually enabled. 1290 */ 1291 if (i915->display.irq.vblank_enabled++ == 0) 1292 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1293 1294 return i8xx_enable_vblank(crtc); 1295 } 1296 1297 int i965_enable_vblank(struct drm_crtc *crtc) 1298 { 1299 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1300 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1301 unsigned long irqflags; 1302 1303 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1304 i915_enable_pipestat(dev_priv, pipe, 1305 PIPE_START_VBLANK_INTERRUPT_STATUS); 1306 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1307 1308 return 0; 1309 } 1310 1311 int ilk_enable_vblank(struct drm_crtc *crtc) 1312 { 1313 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1314 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1315 unsigned long irqflags; 1316 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 1317 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1318 1319 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1320 ilk_enable_display_irq(dev_priv, bit); 1321 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1322 1323 /* Even though there is no DMC, frame counter can get stuck when 1324 * PSR is active as no frames are generated. 1325 */ 1326 if (HAS_PSR(dev_priv)) 1327 drm_crtc_vblank_restore(crtc); 1328 1329 return 0; 1330 } 1331 1332 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 1333 bool enable) 1334 { 1335 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 1336 enum port port; 1337 1338 if (!(intel_crtc->mode_flags & 1339 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 1340 return false; 1341 1342 /* for dual link cases we consider TE from slave */ 1343 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 1344 port = PORT_B; 1345 else 1346 port = PORT_A; 1347 1348 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, 1349 enable ? 0 : DSI_TE_EVENT); 1350 1351 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); 1352 1353 return true; 1354 } 1355 1356 int bdw_enable_vblank(struct drm_crtc *_crtc) 1357 { 1358 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1360 enum pipe pipe = crtc->pipe; 1361 unsigned long irqflags; 1362 1363 if (gen11_dsi_configure_te(crtc, true)) 1364 return 0; 1365 1366 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1367 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 1368 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1369 1370 /* Even if there is no DMC, frame counter can get stuck when 1371 * PSR is active as no frames are generated, so check only for PSR. 1372 */ 1373 if (HAS_PSR(dev_priv)) 1374 drm_crtc_vblank_restore(&crtc->base); 1375 1376 return 0; 1377 } 1378 1379 /* Called from drm generic code, passed 'crtc' which 1380 * we use as a pipe index 1381 */ 1382 void i8xx_disable_vblank(struct drm_crtc *crtc) 1383 { 1384 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1385 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1386 unsigned long irqflags; 1387 1388 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1389 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1390 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1391 } 1392 1393 void i915gm_disable_vblank(struct drm_crtc *crtc) 1394 { 1395 struct drm_i915_private *i915 = to_i915(crtc->dev); 1396 1397 i8xx_disable_vblank(crtc); 1398 1399 if (--i915->display.irq.vblank_enabled == 0) 1400 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1401 } 1402 1403 void i965_disable_vblank(struct drm_crtc *crtc) 1404 { 1405 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1406 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1407 unsigned long irqflags; 1408 1409 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1410 i915_disable_pipestat(dev_priv, pipe, 1411 PIPE_START_VBLANK_INTERRUPT_STATUS); 1412 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1413 } 1414 1415 void ilk_disable_vblank(struct drm_crtc *crtc) 1416 { 1417 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1418 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1419 unsigned long irqflags; 1420 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 1421 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1422 1423 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1424 ilk_disable_display_irq(dev_priv, bit); 1425 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1426 } 1427 1428 void bdw_disable_vblank(struct drm_crtc *_crtc) 1429 { 1430 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1432 enum pipe pipe = crtc->pipe; 1433 unsigned long irqflags; 1434 1435 if (gen11_dsi_configure_te(crtc, false)) 1436 return; 1437 1438 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1439 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 1440 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1441 } 1442 1443 void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 1444 { 1445 struct intel_uncore *uncore = &dev_priv->uncore; 1446 1447 if (IS_CHERRYVIEW(dev_priv)) 1448 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 1449 else 1450 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1451 1452 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); 1453 intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0); 1454 1455 i9xx_pipestat_irq_reset(dev_priv); 1456 1457 GEN3_IRQ_RESET(uncore, VLV_); 1458 dev_priv->irq_mask = ~0u; 1459 } 1460 1461 void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 1462 { 1463 struct intel_uncore *uncore = &dev_priv->uncore; 1464 1465 u32 pipestat_mask; 1466 u32 enable_mask; 1467 enum pipe pipe; 1468 1469 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 1470 1471 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1472 for_each_pipe(dev_priv, pipe) 1473 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); 1474 1475 enable_mask = I915_DISPLAY_PORT_INTERRUPT | 1476 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1477 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1478 I915_LPE_PIPE_A_INTERRUPT | 1479 I915_LPE_PIPE_B_INTERRUPT; 1480 1481 if (IS_CHERRYVIEW(dev_priv)) 1482 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 1483 I915_LPE_PIPE_C_INTERRUPT; 1484 1485 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); 1486 1487 dev_priv->irq_mask = ~enable_mask; 1488 1489 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); 1490 } 1491 1492 void gen8_display_irq_reset(struct drm_i915_private *dev_priv) 1493 { 1494 struct intel_uncore *uncore = &dev_priv->uncore; 1495 enum pipe pipe; 1496 1497 if (!HAS_DISPLAY(dev_priv)) 1498 return; 1499 1500 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 1501 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 1502 1503 for_each_pipe(dev_priv, pipe) 1504 if (intel_display_power_is_enabled(dev_priv, 1505 POWER_DOMAIN_PIPE(pipe))) 1506 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1507 1508 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 1509 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 1510 } 1511 1512 void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 1513 { 1514 struct intel_uncore *uncore = &dev_priv->uncore; 1515 enum pipe pipe; 1516 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1517 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 1518 1519 if (!HAS_DISPLAY(dev_priv)) 1520 return; 1521 1522 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); 1523 1524 if (DISPLAY_VER(dev_priv) >= 12) { 1525 enum transcoder trans; 1526 1527 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 1528 enum intel_display_power_domain domain; 1529 1530 domain = POWER_DOMAIN_TRANSCODER(trans); 1531 if (!intel_display_power_is_enabled(dev_priv, domain)) 1532 continue; 1533 1534 intel_uncore_write(uncore, 1535 TRANS_PSR_IMR(dev_priv, trans), 1536 0xffffffff); 1537 intel_uncore_write(uncore, 1538 TRANS_PSR_IIR(dev_priv, trans), 1539 0xffffffff); 1540 } 1541 } else { 1542 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 1543 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 1544 } 1545 1546 for_each_pipe(dev_priv, pipe) 1547 if (intel_display_power_is_enabled(dev_priv, 1548 POWER_DOMAIN_PIPE(pipe))) 1549 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1550 1551 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 1552 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 1553 1554 if (DISPLAY_VER(dev_priv) >= 14) 1555 GEN3_IRQ_RESET(uncore, PICAINTERRUPT_); 1556 else 1557 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); 1558 1559 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1560 GEN3_IRQ_RESET(uncore, SDE); 1561 } 1562 1563 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 1564 u8 pipe_mask) 1565 { 1566 struct intel_uncore *uncore = &dev_priv->uncore; 1567 u32 extra_ier = GEN8_PIPE_VBLANK | 1568 gen8_de_pipe_underrun_mask(dev_priv) | 1569 gen8_de_pipe_flip_done_mask(dev_priv); 1570 enum pipe pipe; 1571 1572 spin_lock_irq(&dev_priv->irq_lock); 1573 1574 if (!intel_irqs_enabled(dev_priv)) { 1575 spin_unlock_irq(&dev_priv->irq_lock); 1576 return; 1577 } 1578 1579 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 1580 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 1581 dev_priv->display.irq.de_irq_mask[pipe], 1582 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); 1583 1584 spin_unlock_irq(&dev_priv->irq_lock); 1585 } 1586 1587 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 1588 u8 pipe_mask) 1589 { 1590 struct intel_uncore *uncore = &dev_priv->uncore; 1591 enum pipe pipe; 1592 1593 spin_lock_irq(&dev_priv->irq_lock); 1594 1595 if (!intel_irqs_enabled(dev_priv)) { 1596 spin_unlock_irq(&dev_priv->irq_lock); 1597 return; 1598 } 1599 1600 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 1601 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1602 1603 spin_unlock_irq(&dev_priv->irq_lock); 1604 1605 /* make sure we're done processing display irqs */ 1606 intel_synchronize_irq(dev_priv); 1607 } 1608 1609 /* 1610 * SDEIER is also touched by the interrupt handler to work around missed PCH 1611 * interrupts. Hence we can't update it after the interrupt handler is enabled - 1612 * instead we unconditionally enable all PCH interrupt sources here, but then 1613 * only unmask them as needed with SDEIMR. 1614 * 1615 * Note that we currently do this after installing the interrupt handler, 1616 * but before we enable the master interrupt. That should be sufficient 1617 * to avoid races with the irq handler, assuming we have MSI. Shared legacy 1618 * interrupts could still race. 1619 */ 1620 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) 1621 { 1622 struct intel_uncore *uncore = &dev_priv->uncore; 1623 u32 mask; 1624 1625 if (HAS_PCH_NOP(dev_priv)) 1626 return; 1627 1628 if (HAS_PCH_IBX(dev_priv)) 1629 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 1630 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 1631 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 1632 else 1633 mask = SDE_GMBUS_CPT; 1634 1635 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 1636 } 1637 1638 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 1639 { 1640 lockdep_assert_held(&dev_priv->irq_lock); 1641 1642 if (dev_priv->display.irq.display_irqs_enabled) 1643 return; 1644 1645 dev_priv->display.irq.display_irqs_enabled = true; 1646 1647 if (intel_irqs_enabled(dev_priv)) { 1648 vlv_display_irq_reset(dev_priv); 1649 vlv_display_irq_postinstall(dev_priv); 1650 } 1651 } 1652 1653 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 1654 { 1655 lockdep_assert_held(&dev_priv->irq_lock); 1656 1657 if (!dev_priv->display.irq.display_irqs_enabled) 1658 return; 1659 1660 dev_priv->display.irq.display_irqs_enabled = false; 1661 1662 if (intel_irqs_enabled(dev_priv)) 1663 vlv_display_irq_reset(dev_priv); 1664 } 1665 1666 void ilk_de_irq_postinstall(struct drm_i915_private *i915) 1667 { 1668 struct intel_uncore *uncore = &i915->uncore; 1669 u32 display_mask, extra_mask; 1670 1671 if (DISPLAY_VER(i915) >= 7) { 1672 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 1673 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 1674 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 1675 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 1676 DE_PLANE_FLIP_DONE_IVB(PLANE_C) | 1677 DE_PLANE_FLIP_DONE_IVB(PLANE_B) | 1678 DE_PLANE_FLIP_DONE_IVB(PLANE_A) | 1679 DE_DP_A_HOTPLUG_IVB); 1680 } else { 1681 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1682 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 1683 DE_PIPEA_CRC_DONE | DE_POISON); 1684 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 1685 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 1686 DE_PLANE_FLIP_DONE(PLANE_A) | 1687 DE_PLANE_FLIP_DONE(PLANE_B) | 1688 DE_DP_A_HOTPLUG); 1689 } 1690 1691 if (IS_HASWELL(i915)) { 1692 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 1693 display_mask |= DE_EDP_PSR_INT_HSW; 1694 } 1695 1696 if (IS_IRONLAKE_M(i915)) 1697 extra_mask |= DE_PCU_EVENT; 1698 1699 i915->irq_mask = ~display_mask; 1700 1701 ibx_irq_postinstall(i915); 1702 1703 GEN3_IRQ_INIT(uncore, DE, i915->irq_mask, 1704 display_mask | extra_mask); 1705 } 1706 1707 static void mtp_irq_postinstall(struct drm_i915_private *i915); 1708 static void icp_irq_postinstall(struct drm_i915_private *i915); 1709 1710 void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 1711 { 1712 struct intel_display *display = &dev_priv->display; 1713 struct intel_uncore *uncore = &dev_priv->uncore; 1714 1715 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | 1716 GEN8_PIPE_CDCLK_CRC_DONE; 1717 u32 de_pipe_enables; 1718 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); 1719 u32 de_port_enables; 1720 u32 de_misc_masked = GEN8_DE_EDP_PSR; 1721 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1722 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 1723 enum pipe pipe; 1724 1725 if (!HAS_DISPLAY(dev_priv)) 1726 return; 1727 1728 if (DISPLAY_VER(dev_priv) >= 14) 1729 mtp_irq_postinstall(dev_priv); 1730 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1731 icp_irq_postinstall(dev_priv); 1732 else if (HAS_PCH_SPLIT(dev_priv)) 1733 ibx_irq_postinstall(dev_priv); 1734 1735 if (DISPLAY_VER(dev_priv) < 11) 1736 de_misc_masked |= GEN8_DE_MISC_GSE; 1737 1738 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1739 de_port_masked |= BXT_DE_PORT_GMBUS; 1740 1741 if (DISPLAY_VER(dev_priv) >= 14) { 1742 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR | 1743 XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT; 1744 } else if (DISPLAY_VER(dev_priv) >= 11) { 1745 enum port port; 1746 1747 if (intel_bios_is_dsi_present(display, &port)) 1748 de_port_masked |= DSI0_TE | DSI1_TE; 1749 } 1750 1751 if (HAS_DSB(dev_priv)) 1752 de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) | 1753 GEN12_DSB_INT(INTEL_DSB_1) | 1754 GEN12_DSB_INT(INTEL_DSB_2); 1755 1756 de_pipe_enables = de_pipe_masked | 1757 GEN8_PIPE_VBLANK | 1758 gen8_de_pipe_underrun_mask(dev_priv) | 1759 gen8_de_pipe_flip_done_mask(dev_priv); 1760 1761 de_port_enables = de_port_masked; 1762 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1763 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 1764 else if (IS_BROADWELL(dev_priv)) 1765 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 1766 1767 if (DISPLAY_VER(dev_priv) >= 12) { 1768 enum transcoder trans; 1769 1770 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 1771 enum intel_display_power_domain domain; 1772 1773 domain = POWER_DOMAIN_TRANSCODER(trans); 1774 if (!intel_display_power_is_enabled(dev_priv, domain)) 1775 continue; 1776 1777 gen3_assert_iir_is_zero(uncore, 1778 TRANS_PSR_IIR(dev_priv, trans)); 1779 } 1780 } else { 1781 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 1782 } 1783 1784 for_each_pipe(dev_priv, pipe) { 1785 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; 1786 1787 if (intel_display_power_is_enabled(dev_priv, 1788 POWER_DOMAIN_PIPE(pipe))) 1789 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 1790 dev_priv->display.irq.de_irq_mask[pipe], 1791 de_pipe_enables); 1792 } 1793 1794 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); 1795 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); 1796 1797 if (IS_DISPLAY_VER(dev_priv, 11, 13)) { 1798 u32 de_hpd_masked = 0; 1799 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 1800 GEN11_DE_TBT_HOTPLUG_MASK; 1801 1802 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, 1803 de_hpd_enables); 1804 } 1805 } 1806 1807 static void mtp_irq_postinstall(struct drm_i915_private *i915) 1808 { 1809 struct intel_uncore *uncore = &i915->uncore; 1810 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; 1811 u32 de_hpd_mask = XELPDP_AUX_TC_MASK; 1812 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 1813 XELPDP_TBT_HOTPLUG_MASK; 1814 1815 GEN3_IRQ_INIT(uncore, PICAINTERRUPT_, ~de_hpd_mask, 1816 de_hpd_enables); 1817 1818 GEN3_IRQ_INIT(uncore, SDE, ~sde_mask, 0xffffffff); 1819 } 1820 1821 static void icp_irq_postinstall(struct drm_i915_private *dev_priv) 1822 { 1823 struct intel_uncore *uncore = &dev_priv->uncore; 1824 u32 mask = SDE_GMBUS_ICP; 1825 1826 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 1827 } 1828 1829 void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv) 1830 { 1831 if (!HAS_DISPLAY(dev_priv)) 1832 return; 1833 1834 gen8_de_irq_postinstall(dev_priv); 1835 1836 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, 1837 GEN11_DISPLAY_IRQ_ENABLE); 1838 } 1839 1840 void dg1_de_irq_postinstall(struct drm_i915_private *i915) 1841 { 1842 if (!HAS_DISPLAY(i915)) 1843 return; 1844 1845 gen8_de_irq_postinstall(i915); 1846 intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL, 1847 GEN11_DISPLAY_IRQ_ENABLE); 1848 } 1849 1850 void intel_display_irq_init(struct drm_i915_private *i915) 1851 { 1852 i915->drm.vblank_disable_immediate = true; 1853 1854 /* 1855 * Most platforms treat the display irq block as an always-on power 1856 * domain. vlv/chv can disable it at runtime and need special care to 1857 * avoid writing any of the display block registers outside of the power 1858 * domain. We defer setting up the display irqs in this case to the 1859 * runtime pm. 1860 */ 1861 i915->display.irq.display_irqs_enabled = true; 1862 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 1863 i915->display.irq.display_irqs_enabled = false; 1864 1865 intel_hotplug_irq_init(i915); 1866 } 1867