1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 13 struct drm_i915_private; 14 struct drm_printer; 15 16 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 17 /* Keep in alphabetical order */ \ 18 func(cursor_needs_physical); \ 19 func(has_cdclk_crawl); \ 20 func(has_cdclk_squash); \ 21 func(has_ddi); \ 22 func(has_dp_mst); \ 23 func(has_dsb); \ 24 func(has_fpga_dbg); \ 25 func(has_gmch); \ 26 func(has_hotplug); \ 27 func(has_hti); \ 28 func(has_ipc); \ 29 func(has_overlay); \ 30 func(has_psr); \ 31 func(has_psr_hw_tracking); \ 32 func(overlay_needs_physical); \ 33 func(supports_tv); 34 35 #define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 36 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 37 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 38 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 39 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) 40 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 41 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 42 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 43 #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 44 #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 45 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 46 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 47 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 48 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 49 #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 50 #define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) 51 #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 52 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 53 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3) 54 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 55 #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 56 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 57 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 58 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 59 #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 60 #define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12) 61 #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 62 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 63 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 64 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 65 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 66 #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 67 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 68 #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) 69 #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 70 BIT(trans)) != 0) 71 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 72 #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) 73 #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 74 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 75 #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 76 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 77 78 /* Check that device has a display IP version within the specific range. */ 79 #define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \ 80 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 81 (DISPLAY_VER_FULL(__i915) >= (from) && \ 82 DISPLAY_VER_FULL(__i915) <= (until))) 83 84 /* 85 * Check if a device has a specific IP version as well as a stepping within the 86 * specified range [from, until). The lower bound is inclusive, the upper 87 * bound is exclusive. The most common use-case of this macro is for checking 88 * bounds for workarounds, which usually have a stepping ("from") at which the 89 * hardware issue is first present and another stepping ("until") at which a 90 * hardware fix is present and the software workaround is no longer necessary. 91 * E.g., 92 * 93 * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2) 94 * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER) 95 * 96 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 97 * stepping bound for the specified IP version. 98 */ 99 #define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \ 100 (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \ 101 IS_DISPLAY_STEP((__i915), (from), (until))) 102 103 #define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) 104 #define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) 105 106 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 107 #define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ 108 DISPLAY_RUNTIME_INFO(i915)->ip.rel) 109 #define IS_DISPLAY_VER(i915, from, until) \ 110 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 111 112 struct intel_display_runtime_info { 113 struct { 114 u16 ver; 115 u16 rel; 116 u16 step; 117 } ip; 118 119 u8 pipe_mask; 120 u8 cpu_transcoder_mask; 121 u16 port_mask; 122 123 u8 num_sprites[I915_MAX_PIPES]; 124 u8 num_scalers[I915_MAX_PIPES]; 125 126 u8 fbc_mask; 127 128 bool has_hdcp; 129 bool has_dmc; 130 bool has_dsc; 131 }; 132 133 struct intel_display_device_info { 134 /* Initial runtime info. */ 135 const struct intel_display_runtime_info __runtime_defaults; 136 137 u8 abox_mask; 138 139 struct { 140 u16 size; /* in blocks */ 141 u8 slice_mask; 142 } dbuf; 143 144 #define DEFINE_FLAG(name) u8 name:1 145 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 146 #undef DEFINE_FLAG 147 148 /* Global register offset for the display engine */ 149 u32 mmio_offset; 150 151 /* Register offsets for the various display pipes and transcoders */ 152 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 153 u32 trans_offsets[I915_MAX_TRANSCODERS]; 154 u32 cursor_offsets[I915_MAX_PIPES]; 155 156 struct { 157 u32 degamma_lut_size; 158 u32 gamma_lut_size; 159 u32 degamma_lut_tests; 160 u32 gamma_lut_tests; 161 } color; 162 }; 163 164 bool intel_display_device_enabled(struct drm_i915_private *i915); 165 void intel_display_device_probe(struct drm_i915_private *i915); 166 void intel_display_device_remove(struct drm_i915_private *i915); 167 void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 168 169 void intel_display_device_info_print(const struct intel_display_device_info *info, 170 const struct intel_display_runtime_info *runtime, 171 struct drm_printer *p); 172 173 #endif 174