1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_conversion.h" 12 #include "intel_display_limits.h" 13 14 struct drm_i915_private; 15 struct drm_printer; 16 17 /* Keep in gen based order, and chronological order within a gen */ 18 enum intel_display_platform { 19 INTEL_DISPLAY_PLATFORM_UNINITIALIZED = 0, 20 /* Display ver 2 */ 21 INTEL_DISPLAY_I830, 22 INTEL_DISPLAY_I845G, 23 INTEL_DISPLAY_I85X, 24 INTEL_DISPLAY_I865G, 25 /* Display ver 3 */ 26 INTEL_DISPLAY_I915G, 27 INTEL_DISPLAY_I915GM, 28 INTEL_DISPLAY_I945G, 29 INTEL_DISPLAY_I945GM, 30 INTEL_DISPLAY_G33, 31 INTEL_DISPLAY_PINEVIEW, 32 /* Display ver 4 */ 33 INTEL_DISPLAY_I965G, 34 INTEL_DISPLAY_I965GM, 35 INTEL_DISPLAY_G45, 36 INTEL_DISPLAY_GM45, 37 /* Display ver 5 */ 38 INTEL_DISPLAY_IRONLAKE, 39 /* Display ver 6 */ 40 INTEL_DISPLAY_SANDYBRIDGE, 41 /* Display ver 7 */ 42 INTEL_DISPLAY_IVYBRIDGE, 43 INTEL_DISPLAY_VALLEYVIEW, 44 INTEL_DISPLAY_HASWELL, 45 /* Display ver 8 */ 46 INTEL_DISPLAY_BROADWELL, 47 INTEL_DISPLAY_CHERRYVIEW, 48 /* Display ver 9 */ 49 INTEL_DISPLAY_SKYLAKE, 50 INTEL_DISPLAY_BROXTON, 51 INTEL_DISPLAY_KABYLAKE, 52 INTEL_DISPLAY_GEMINILAKE, 53 INTEL_DISPLAY_COFFEELAKE, 54 INTEL_DISPLAY_COMETLAKE, 55 /* Display ver 11 */ 56 INTEL_DISPLAY_ICELAKE, 57 INTEL_DISPLAY_JASPERLAKE, 58 INTEL_DISPLAY_ELKHARTLAKE, 59 /* Display ver 12 */ 60 INTEL_DISPLAY_TIGERLAKE, 61 INTEL_DISPLAY_ROCKETLAKE, 62 INTEL_DISPLAY_DG1, 63 INTEL_DISPLAY_ALDERLAKE_S, 64 /* Display ver 13 */ 65 INTEL_DISPLAY_ALDERLAKE_P, 66 INTEL_DISPLAY_DG2, 67 /* Display ver 14 (based on GMD ID) */ 68 INTEL_DISPLAY_METEORLAKE, 69 /* Display ver 20 (based on GMD ID) */ 70 INTEL_DISPLAY_LUNARLAKE, 71 /* Display ver 14.1 (based on GMD ID) */ 72 INTEL_DISPLAY_BATTLEMAGE, 73 }; 74 75 enum intel_display_subplatform { 76 INTEL_DISPLAY_SUBPLATFORM_UNINITIALIZED = 0, 77 INTEL_DISPLAY_HASWELL_ULT, 78 INTEL_DISPLAY_HASWELL_ULX, 79 INTEL_DISPLAY_BROADWELL_ULT, 80 INTEL_DISPLAY_BROADWELL_ULX, 81 INTEL_DISPLAY_SKYLAKE_ULT, 82 INTEL_DISPLAY_SKYLAKE_ULX, 83 INTEL_DISPLAY_KABYLAKE_ULT, 84 INTEL_DISPLAY_KABYLAKE_ULX, 85 INTEL_DISPLAY_COFFEELAKE_ULT, 86 INTEL_DISPLAY_COFFEELAKE_ULX, 87 INTEL_DISPLAY_COMETLAKE_ULT, 88 INTEL_DISPLAY_COMETLAKE_ULX, 89 INTEL_DISPLAY_ICELAKE_PORT_F, 90 INTEL_DISPLAY_TIGERLAKE_UY, 91 INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, 92 INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, 93 INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, 94 INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, 95 INTEL_DISPLAY_DG2_G10, 96 INTEL_DISPLAY_DG2_G11, 97 INTEL_DISPLAY_DG2_G12, 98 }; 99 100 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 101 /* Keep in alphabetical order */ \ 102 func(cursor_needs_physical); \ 103 func(has_cdclk_crawl); \ 104 func(has_cdclk_squash); \ 105 func(has_ddi); \ 106 func(has_dp_mst); \ 107 func(has_dsb); \ 108 func(has_fpga_dbg); \ 109 func(has_gmch); \ 110 func(has_hotplug); \ 111 func(has_hti); \ 112 func(has_ipc); \ 113 func(has_overlay); \ 114 func(has_psr); \ 115 func(has_psr_hw_tracking); \ 116 func(overlay_needs_physical); \ 117 func(supports_tv); 118 119 #define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 120 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 121 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 122 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 123 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) 124 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 125 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 126 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 127 #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 128 #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 129 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 130 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 131 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 132 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 133 #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 134 #define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) 135 #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 136 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 137 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3) 138 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 139 #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 140 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 141 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 142 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 143 #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 144 #define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12) 145 #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 146 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 147 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 148 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 149 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 150 #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 151 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 152 #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) 153 #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 154 BIT(trans)) != 0) 155 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 156 #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) 157 #define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) 158 #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 159 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 160 #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 161 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 162 163 /* Check that device has a display IP version within the specific range. */ 164 #define IS_DISPLAY_VER_FULL(__i915, from, until) ( \ 165 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 166 (DISPLAY_VER_FULL(__i915) >= (from) && \ 167 DISPLAY_VER_FULL(__i915) <= (until))) 168 169 /* 170 * Check if a device has a specific IP version as well as a stepping within the 171 * specified range [from, until). The lower bound is inclusive, the upper 172 * bound is exclusive. The most common use-case of this macro is for checking 173 * bounds for workarounds, which usually have a stepping ("from") at which the 174 * hardware issue is first present and another stepping ("until") at which a 175 * hardware fix is present and the software workaround is no longer necessary. 176 * E.g., 177 * 178 * IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2) 179 * IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER) 180 * 181 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 182 * stepping bound for the specified IP version. 183 */ 184 #define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \ 185 (IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \ 186 IS_DISPLAY_STEP((__i915), (from), (until))) 187 188 #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) 189 #define DISPLAY_RUNTIME_INFO(i915) (&__to_intel_display(i915)->info.__runtime_info) 190 191 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 192 #define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ 193 DISPLAY_RUNTIME_INFO(i915)->ip.rel) 194 #define IS_DISPLAY_VER(i915, from, until) \ 195 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 196 197 struct intel_display_runtime_info { 198 enum intel_display_platform platform; 199 enum intel_display_subplatform subplatform; 200 201 struct intel_display_ip_ver { 202 u16 ver; 203 u16 rel; 204 u16 step; 205 } ip; 206 207 u32 rawclk_freq; 208 209 u8 pipe_mask; 210 u8 cpu_transcoder_mask; 211 u16 port_mask; 212 213 u8 num_sprites[I915_MAX_PIPES]; 214 u8 num_scalers[I915_MAX_PIPES]; 215 216 u8 fbc_mask; 217 218 bool has_hdcp; 219 bool has_dmc; 220 bool has_dsc; 221 }; 222 223 struct intel_display_device_info { 224 /* Initial runtime info. */ 225 const struct intel_display_runtime_info __runtime_defaults; 226 227 u8 abox_mask; 228 229 struct { 230 u16 size; /* in blocks */ 231 u8 slice_mask; 232 } dbuf; 233 234 #define DEFINE_FLAG(name) u8 name:1 235 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 236 #undef DEFINE_FLAG 237 238 /* Global register offset for the display engine */ 239 u32 mmio_offset; 240 241 /* Register offsets for the various display pipes and transcoders */ 242 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 243 u32 trans_offsets[I915_MAX_TRANSCODERS]; 244 u32 cursor_offsets[I915_MAX_PIPES]; 245 246 struct { 247 u32 degamma_lut_size; 248 u32 gamma_lut_size; 249 u32 degamma_lut_tests; 250 u32 gamma_lut_tests; 251 } color; 252 }; 253 254 bool intel_display_device_enabled(struct drm_i915_private *i915); 255 void intel_display_device_probe(struct drm_i915_private *i915); 256 void intel_display_device_remove(struct drm_i915_private *i915); 257 void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 258 259 void intel_display_device_info_print(const struct intel_display_device_info *info, 260 const struct intel_display_runtime_info *runtime, 261 struct drm_printer *p); 262 263 #endif 264