1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/bitops.h> 10 #include <linux/types.h> 11 12 #include "intel_display_limits.h" 13 14 struct drm_printer; 15 struct intel_display; 16 struct intel_display_parent_interface; 17 struct pci_dev; 18 19 /* 20 * Display platforms and subplatforms. Keep platforms in display version based 21 * order, chronological order within a version, and subplatforms next to the 22 * platform. 23 */ 24 #define INTEL_DISPLAY_PLATFORMS(func) \ 25 /* Platform group aliases */ \ 26 func(g4x) /* g45 and gm45 */ \ 27 func(mobile) /* mobile platforms */ \ 28 func(dgfx) /* discrete graphics */ \ 29 /* Display ver 2 */ \ 30 func(i830) \ 31 func(i845g) \ 32 func(i85x) \ 33 func(i865g) \ 34 /* Display ver 3 */ \ 35 func(i915g) \ 36 func(i915gm) \ 37 func(i945g) \ 38 func(i945gm) \ 39 func(g33) \ 40 func(pineview) \ 41 /* Display ver 4 */ \ 42 func(i965g) \ 43 func(i965gm) \ 44 func(g45) \ 45 func(gm45) \ 46 /* Display ver 5 */ \ 47 func(ironlake) \ 48 /* Display ver 6 */ \ 49 func(sandybridge) \ 50 /* Display ver 7 */ \ 51 func(ivybridge) \ 52 func(valleyview) \ 53 func(haswell) \ 54 func(haswell_ult) \ 55 func(haswell_ulx) \ 56 /* Display ver 8 */ \ 57 func(broadwell) \ 58 func(broadwell_ult) \ 59 func(broadwell_ulx) \ 60 func(cherryview) \ 61 /* Display ver 9 */ \ 62 func(skylake) \ 63 func(skylake_ult) \ 64 func(skylake_ulx) \ 65 func(broxton) \ 66 func(kabylake) \ 67 func(kabylake_ult) \ 68 func(kabylake_ulx) \ 69 func(geminilake) \ 70 func(coffeelake) \ 71 func(coffeelake_ult) \ 72 func(coffeelake_ulx) \ 73 func(cometlake) \ 74 func(cometlake_ult) \ 75 func(cometlake_ulx) \ 76 /* Display ver 11 */ \ 77 func(icelake) \ 78 func(icelake_port_f) \ 79 func(jasperlake) \ 80 func(elkhartlake) \ 81 /* Display ver 12 */ \ 82 func(tigerlake) \ 83 func(tigerlake_uy) \ 84 func(rocketlake) \ 85 func(dg1) \ 86 func(alderlake_s) \ 87 func(alderlake_s_raptorlake_s) \ 88 /* Display ver 13 */ \ 89 func(alderlake_p) \ 90 func(alderlake_p_alderlake_n) \ 91 func(alderlake_p_raptorlake_p) \ 92 func(alderlake_p_raptorlake_u) \ 93 func(dg2) \ 94 func(dg2_g10) \ 95 func(dg2_g11) \ 96 func(dg2_g12) \ 97 /* Display ver 14 (based on GMD ID) */ \ 98 func(meteorlake) \ 99 func(meteorlake_u) \ 100 /* Display ver 20 (based on GMD ID) */ \ 101 func(lunarlake) \ 102 /* Display ver 14.1 (based on GMD ID) */ \ 103 func(battlemage) \ 104 /* Display ver 30 (based on GMD ID) */ \ 105 func(pantherlake) \ 106 func(pantherlake_wildcatlake) \ 107 /* Display ver 35 (based on GMD ID) */ \ 108 func(novalake) 109 110 111 #define __MEMBER(name) unsigned long name:1; 112 #define __COUNT(x) 1 + 113 114 #define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0) 115 116 struct intel_display_platforms { 117 union { 118 struct { 119 INTEL_DISPLAY_PLATFORMS(__MEMBER); 120 }; 121 DECLARE_BITMAP(bitmap, __NUM_PLATFORMS); 122 }; 123 }; 124 125 #undef __MEMBER 126 #undef __COUNT 127 #undef __NUM_PLATFORMS 128 129 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 130 /* Keep in alphabetical order */ \ 131 func(cursor_needs_physical); \ 132 func(has_cdclk_crawl); \ 133 func(has_cdclk_squash); \ 134 func(has_ddi); \ 135 func(has_dp_mst); \ 136 func(has_dsb); \ 137 func(has_fpga_dbg); \ 138 func(has_gmch); \ 139 func(has_hotplug); \ 140 func(has_hti); \ 141 func(has_ipc); \ 142 func(has_overlay); \ 143 func(has_psr); \ 144 func(has_psr_hw_tracking); \ 145 func(overlay_needs_physical); \ 146 func(supports_tv); 147 148 #define HAS_128B_Y_TILING(__display) (!(__display)->platform.i915g && !(__display)->platform.i915gm) 149 #define HAS_2PPC(__display) (DISPLAY_VER(__display) >= 10) 150 #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 151 #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) 152 #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) 153 #define HAS_AUX_DIST(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) 154 #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) 155 #define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20) 156 #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) 157 #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash) 158 #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20) 159 #define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13) 160 #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13)) 161 #define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s) 162 #define HAS_DBUF_OVERLAP_DETECTION(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection) 163 #define HAS_DC3CO(__display) (DISPLAY_VER(__display) >= 35) 164 #define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi) 165 #define HAS_DISPLAY(__display) (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0) 166 #define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc) 167 #define HAS_DOUBLE_BUFFERED_M_N(__display) (IS_DISPLAY_VER((__display), 9, 14) || (__display)->platform.broadwell) 168 #define HAS_DOUBLE_BUFFERED_LUT(__display) (DISPLAY_VER(__display) >= 30) 169 #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4) 170 #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 171 #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13) 172 #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) 173 #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) 174 #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) 175 #define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) 176 #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) 177 #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) 178 #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) 179 #define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx) 180 #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) 181 #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) 182 #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) 183 #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4) 184 #define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch) 185 #define HAS_FDI(__display) (IS_DISPLAY_VER((__display), 5, 8) && !HAS_GMCH(__display)) 186 #define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug) 187 #define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx) 188 #define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc) 189 #define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell) 190 #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12) 191 #define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10)) 192 #define HAS_LT_PHY(__display) ((__display)->platform.novalake) 193 #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) 194 #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) 195 #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) 196 #define HAS_PEAK_BW_THRESHOLD(__display) (DISPLAY_VER(__display) >= 30) 197 #define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12) 198 #define HAS_PIXEL_NORMALIZER(__display) (DISPLAY_VER(__display) >= 35) 199 #define HAS_PMDEMAND(__display) (DISPLAY_VER(__display) >= 14) 200 #define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr) 201 #define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking) 202 #define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12) 203 #define HAS_PSR_TRANS_PUSH_FRAME_CHANGE(__display) (DISPLAY_VER(__display) >= 20) 204 #define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \ 205 !(__display)->platform.broxton && !(__display)->platform.geminilake) 206 #define HAS_SAGV_WM(__display) (DISPLAY_VER(__display) >= 12 && !(__display)->platform.rocketlake) 207 #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ 208 BIT(trans)) != 0) 209 #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) 210 #define HAS_UNDERRUN_DBG_INFO(__display) (DISPLAY_VER(__display) >= 35) 211 #define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \ 212 DISPLAY_VER(__display) == 14) && HAS_DSC(__display)) 213 #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11) 214 #define HAS_VRR_DC_BALANCE(__display) (DISPLAY_VER(__display) >= 30) 215 #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask)) 216 #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical) 217 #define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv) 218 219 /* Check that device has a display IP version within the specific range. */ 220 #define IS_DISPLAY_VERx100(__display, from, until) ( \ 221 BUILD_BUG_ON_ZERO((from) < 200) + \ 222 (DISPLAY_VERx100(__display) >= (from) && \ 223 DISPLAY_VERx100(__display) <= (until))) 224 225 /* 226 * Check if a device has a specific IP version as well as a stepping within the 227 * specified range [from, until). The lower bound is inclusive, the upper 228 * bound is exclusive. The most common use-case of this macro is for checking 229 * bounds for workarounds, which usually have a stepping ("from") at which the 230 * hardware issue is first present and another stepping ("until") at which a 231 * hardware fix is present and the software workaround is no longer necessary. 232 * E.g., 233 * 234 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B2) 235 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_C0, STEP_FOREVER) 236 * 237 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 238 * stepping bound for the specified IP version. 239 */ 240 #define IS_DISPLAY_VERx100_STEP(__display, ipver, from, until) \ 241 (IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \ 242 IS_DISPLAY_STEP((__display), (from), (until))) 243 244 #define DISPLAY_INFO(__display) ((__display)->info.__device_info) 245 #define DISPLAY_RUNTIME_INFO(__display) (&(__display)->info.__runtime_info) 246 247 #define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver) 248 #define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \ 249 DISPLAY_RUNTIME_INFO(__display)->ip.rel) 250 #define IS_DISPLAY_VER(__display, from, until) \ 251 (DISPLAY_VER(__display) >= (from) && DISPLAY_VER(__display) <= (until)) 252 253 #define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step) 254 255 #define IS_DISPLAY_STEP(__display, since, until) \ 256 (drm_WARN_ON((__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \ 257 INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until)) 258 259 #define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C 260 #define ARLS_HOST_BRIDGE_PCI_ID2 0x7D2D 261 #define ARLS_HOST_BRIDGE_PCI_ID3 0x7D2E 262 #define ARLS_HOST_BRIDGE_PCI_ID4 0x7D2F 263 264 #define IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(id) \ 265 (((id) == ARLS_HOST_BRIDGE_PCI_ID1) || \ 266 ((id) == ARLS_HOST_BRIDGE_PCI_ID2) || \ 267 ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \ 268 ((id) == ARLS_HOST_BRIDGE_PCI_ID4)) 269 270 #define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe) \ 271 (DISPLAY_INFO((display))->pipe_offsets[(pipe)] - \ 272 DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \ 273 DISPLAY_MMIO_BASE((display))) 274 275 #define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \ 276 (DISPLAY_INFO((display))->trans_offsets[(trans)] - \ 277 DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \ 278 DISPLAY_MMIO_BASE((display))) 279 280 #define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \ 281 (DISPLAY_INFO((display))->cursor_offsets[(pipe)] - \ 282 DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \ 283 DISPLAY_MMIO_BASE((display))) 284 285 #define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset) 286 287 struct intel_display_runtime_info { 288 struct intel_display_ip_ver { 289 u16 ver; 290 u16 rel; 291 u16 step; /* hardware */ 292 } ip; 293 int step; /* symbolic */ 294 char step_name[3]; /* empty string if not applicable */ 295 296 u32 rawclk_freq; 297 298 u8 pipe_mask; 299 u16 cpu_transcoder_mask; 300 u16 port_mask; 301 302 u8 num_sprites[I915_MAX_PIPES]; 303 u8 num_scalers[I915_MAX_PIPES]; 304 305 u8 fbc_mask; 306 307 bool has_hdcp; 308 bool has_dmc; 309 bool has_dsc; 310 bool edp_typec_support; 311 bool has_dbuf_overlap_detection; 312 }; 313 314 struct intel_display_device_info { 315 /* Initial runtime info. */ 316 const struct intel_display_runtime_info __runtime_defaults; 317 318 u8 abox_mask; 319 320 struct { 321 u16 size; /* in blocks */ 322 u8 slice_mask; 323 } dbuf; 324 325 #define DEFINE_FLAG(name) u8 name:1 326 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 327 #undef DEFINE_FLAG 328 329 /* Global register offset for the display engine */ 330 u32 mmio_offset; 331 332 /* Register offsets for the various display pipes and transcoders */ 333 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 334 u32 trans_offsets[I915_MAX_TRANSCODERS]; 335 u32 cursor_offsets[I915_MAX_PIPES]; 336 337 struct { 338 u32 degamma_lut_size; 339 u32 gamma_lut_size; 340 u32 degamma_lut_tests; 341 u32 gamma_lut_tests; 342 } color; 343 }; 344 345 bool intel_display_device_present(struct intel_display *display); 346 bool intel_display_device_enabled(struct intel_display *display); 347 struct intel_display *intel_display_device_probe(struct pci_dev *pdev, 348 const struct intel_display_parent_interface *parent); 349 void intel_display_device_remove(struct intel_display *display); 350 void intel_display_device_info_runtime_init(struct intel_display *display); 351 352 void intel_display_device_info_print(const struct intel_display_device_info *info, 353 const struct intel_display_runtime_info *runtime, 354 struct drm_printer *p); 355 356 #endif 357