1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/intel/i915_pciids.h> 7 #include <drm/drm_color_mgmt.h> 8 #include <linux/pci.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_de.h" 13 #include "intel_display.h" 14 #include "intel_display_device.h" 15 #include "intel_display_params.h" 16 #include "intel_display_power.h" 17 #include "intel_display_reg_defs.h" 18 #include "intel_fbc.h" 19 20 __diag_push(); 21 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); 22 23 struct subplatform_desc { 24 enum intel_display_subplatform subplatform; 25 const char *name; 26 const u16 *pciidlist; 27 }; 28 29 struct platform_desc { 30 enum intel_display_platform platform; 31 const char *name; 32 const struct subplatform_desc *subplatforms; 33 const struct intel_display_device_info *info; /* NULL for GMD ID */ 34 }; 35 36 #define PLATFORM(_platform) \ 37 .platform = (INTEL_DISPLAY_##_platform), \ 38 .name = #_platform 39 40 #define ID(id) (id) 41 42 static const struct intel_display_device_info no_display = {}; 43 44 #define PIPE_A_OFFSET 0x70000 45 #define PIPE_B_OFFSET 0x71000 46 #define PIPE_C_OFFSET 0x72000 47 #define PIPE_D_OFFSET 0x73000 48 #define CHV_PIPE_C_OFFSET 0x74000 49 /* 50 * There's actually no pipe EDP. Some pipe registers have 51 * simply shifted from the pipe to the transcoder, while 52 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 53 * to access such registers in transcoder EDP. 54 */ 55 #define PIPE_EDP_OFFSET 0x7f000 56 57 /* ICL DSI 0 and 1 */ 58 #define PIPE_DSI0_OFFSET 0x7b000 59 #define PIPE_DSI1_OFFSET 0x7b800 60 61 #define TRANSCODER_A_OFFSET 0x60000 62 #define TRANSCODER_B_OFFSET 0x61000 63 #define TRANSCODER_C_OFFSET 0x62000 64 #define CHV_TRANSCODER_C_OFFSET 0x63000 65 #define TRANSCODER_D_OFFSET 0x63000 66 #define TRANSCODER_EDP_OFFSET 0x6f000 67 #define TRANSCODER_DSI0_OFFSET 0x6b000 68 #define TRANSCODER_DSI1_OFFSET 0x6b800 69 70 #define CURSOR_A_OFFSET 0x70080 71 #define CURSOR_B_OFFSET 0x700c0 72 #define CHV_CURSOR_C_OFFSET 0x700e0 73 #define IVB_CURSOR_B_OFFSET 0x71080 74 #define IVB_CURSOR_C_OFFSET 0x72080 75 #define TGL_CURSOR_D_OFFSET 0x73080 76 77 #define I845_PIPE_OFFSETS \ 78 .pipe_offsets = { \ 79 [TRANSCODER_A] = PIPE_A_OFFSET, \ 80 }, \ 81 .trans_offsets = { \ 82 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 83 } 84 85 #define I9XX_PIPE_OFFSETS \ 86 .pipe_offsets = { \ 87 [TRANSCODER_A] = PIPE_A_OFFSET, \ 88 [TRANSCODER_B] = PIPE_B_OFFSET, \ 89 }, \ 90 .trans_offsets = { \ 91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 93 } 94 95 #define IVB_PIPE_OFFSETS \ 96 .pipe_offsets = { \ 97 [TRANSCODER_A] = PIPE_A_OFFSET, \ 98 [TRANSCODER_B] = PIPE_B_OFFSET, \ 99 [TRANSCODER_C] = PIPE_C_OFFSET, \ 100 }, \ 101 .trans_offsets = { \ 102 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 103 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 104 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 105 } 106 107 #define HSW_PIPE_OFFSETS \ 108 .pipe_offsets = { \ 109 [TRANSCODER_A] = PIPE_A_OFFSET, \ 110 [TRANSCODER_B] = PIPE_B_OFFSET, \ 111 [TRANSCODER_C] = PIPE_C_OFFSET, \ 112 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 113 }, \ 114 .trans_offsets = { \ 115 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 116 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 117 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 118 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 119 } 120 121 #define CHV_PIPE_OFFSETS \ 122 .pipe_offsets = { \ 123 [TRANSCODER_A] = PIPE_A_OFFSET, \ 124 [TRANSCODER_B] = PIPE_B_OFFSET, \ 125 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 126 }, \ 127 .trans_offsets = { \ 128 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 129 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 130 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 131 } 132 133 #define I845_CURSOR_OFFSETS \ 134 .cursor_offsets = { \ 135 [PIPE_A] = CURSOR_A_OFFSET, \ 136 } 137 138 #define I9XX_CURSOR_OFFSETS \ 139 .cursor_offsets = { \ 140 [PIPE_A] = CURSOR_A_OFFSET, \ 141 [PIPE_B] = CURSOR_B_OFFSET, \ 142 } 143 144 #define CHV_CURSOR_OFFSETS \ 145 .cursor_offsets = { \ 146 [PIPE_A] = CURSOR_A_OFFSET, \ 147 [PIPE_B] = CURSOR_B_OFFSET, \ 148 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 149 } 150 151 #define IVB_CURSOR_OFFSETS \ 152 .cursor_offsets = { \ 153 [PIPE_A] = CURSOR_A_OFFSET, \ 154 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 155 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 156 } 157 158 #define TGL_CURSOR_OFFSETS \ 159 .cursor_offsets = { \ 160 [PIPE_A] = CURSOR_A_OFFSET, \ 161 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 162 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 163 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 164 } 165 166 #define I845_COLORS \ 167 .color = { .gamma_lut_size = 256 } 168 #define I9XX_COLORS \ 169 .color = { .gamma_lut_size = 129, \ 170 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 171 } 172 #define ILK_COLORS \ 173 .color = { .gamma_lut_size = 1024 } 174 #define IVB_COLORS \ 175 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 176 #define CHV_COLORS \ 177 .color = { \ 178 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 179 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 180 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 181 } 182 #define GLK_COLORS \ 183 .color = { \ 184 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 185 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 186 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 187 } 188 #define ICL_COLORS \ 189 .color = { \ 190 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 191 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 192 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 193 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 194 } 195 196 #define I830_DISPLAY \ 197 .has_overlay = 1, \ 198 .cursor_needs_physical = 1, \ 199 .overlay_needs_physical = 1, \ 200 .has_gmch = 1, \ 201 I9XX_PIPE_OFFSETS, \ 202 I9XX_CURSOR_OFFSETS, \ 203 I9XX_COLORS, \ 204 \ 205 .__runtime_defaults.ip.ver = 2, \ 206 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 207 .__runtime_defaults.cpu_transcoder_mask = \ 208 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 209 210 #define I845_DISPLAY \ 211 .has_overlay = 1, \ 212 .overlay_needs_physical = 1, \ 213 .has_gmch = 1, \ 214 I845_PIPE_OFFSETS, \ 215 I845_CURSOR_OFFSETS, \ 216 I845_COLORS, \ 217 \ 218 .__runtime_defaults.ip.ver = 2, \ 219 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ 220 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) 221 222 static const struct platform_desc i830_desc = { 223 PLATFORM(I830), 224 .info = &(const struct intel_display_device_info) { 225 I830_DISPLAY, 226 227 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ 228 }, 229 }; 230 231 static const struct platform_desc i845_desc = { 232 PLATFORM(I845G), 233 .info = &(const struct intel_display_device_info) { 234 I845_DISPLAY, 235 236 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 237 }, 238 }; 239 240 static const struct platform_desc i85x_desc = { 241 PLATFORM(I85X), 242 .info = &(const struct intel_display_device_info) { 243 I830_DISPLAY, 244 245 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 246 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 247 }, 248 }; 249 250 static const struct platform_desc i865g_desc = { 251 PLATFORM(I865G), 252 .info = &(const struct intel_display_device_info) { 253 I845_DISPLAY, 254 255 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 256 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 257 }, 258 }; 259 260 #define GEN3_DISPLAY \ 261 .has_gmch = 1, \ 262 .has_overlay = 1, \ 263 I9XX_PIPE_OFFSETS, \ 264 I9XX_CURSOR_OFFSETS, \ 265 \ 266 .__runtime_defaults.ip.ver = 3, \ 267 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 268 .__runtime_defaults.cpu_transcoder_mask = \ 269 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 270 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ 271 272 static const struct platform_desc i915g_desc = { 273 PLATFORM(I915G), 274 .info = &(const struct intel_display_device_info) { 275 GEN3_DISPLAY, 276 I845_COLORS, 277 .cursor_needs_physical = 1, 278 .overlay_needs_physical = 1, 279 }, 280 }; 281 282 static const struct platform_desc i915gm_desc = { 283 PLATFORM(I915GM), 284 .info = &(const struct intel_display_device_info) { 285 GEN3_DISPLAY, 286 I9XX_COLORS, 287 .cursor_needs_physical = 1, 288 .overlay_needs_physical = 1, 289 .supports_tv = 1, 290 291 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 292 }, 293 }; 294 295 static const struct platform_desc i945g_desc = { 296 PLATFORM(I945G), 297 .info = &(const struct intel_display_device_info) { 298 GEN3_DISPLAY, 299 I845_COLORS, 300 .has_hotplug = 1, 301 .cursor_needs_physical = 1, 302 .overlay_needs_physical = 1, 303 }, 304 }; 305 306 static const struct platform_desc i945gm_desc = { 307 PLATFORM(I915GM), 308 .info = &(const struct intel_display_device_info) { 309 GEN3_DISPLAY, 310 I9XX_COLORS, 311 .has_hotplug = 1, 312 .cursor_needs_physical = 1, 313 .overlay_needs_physical = 1, 314 .supports_tv = 1, 315 316 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 317 }, 318 }; 319 320 static const struct platform_desc g33_desc = { 321 PLATFORM(G33), 322 .info = &(const struct intel_display_device_info) { 323 GEN3_DISPLAY, 324 I845_COLORS, 325 .has_hotplug = 1, 326 }, 327 }; 328 329 static const struct platform_desc pnv_desc = { 330 PLATFORM(PINEVIEW), 331 .info = &(const struct intel_display_device_info) { 332 GEN3_DISPLAY, 333 I9XX_COLORS, 334 .has_hotplug = 1, 335 }, 336 }; 337 338 #define GEN4_DISPLAY \ 339 .has_hotplug = 1, \ 340 .has_gmch = 1, \ 341 I9XX_PIPE_OFFSETS, \ 342 I9XX_CURSOR_OFFSETS, \ 343 I9XX_COLORS, \ 344 \ 345 .__runtime_defaults.ip.ver = 4, \ 346 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 347 .__runtime_defaults.cpu_transcoder_mask = \ 348 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 349 350 static const struct platform_desc i965g_desc = { 351 PLATFORM(I965G), 352 .info = &(const struct intel_display_device_info) { 353 GEN4_DISPLAY, 354 .has_overlay = 1, 355 356 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 357 }, 358 }; 359 360 static const struct platform_desc i965gm_desc = { 361 PLATFORM(I965GM), 362 .info = &(const struct intel_display_device_info) { 363 GEN4_DISPLAY, 364 .has_overlay = 1, 365 .supports_tv = 1, 366 367 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 368 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 369 }, 370 }; 371 372 static const struct platform_desc g45_desc = { 373 PLATFORM(G45), 374 .info = &(const struct intel_display_device_info) { 375 GEN4_DISPLAY, 376 377 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 378 }, 379 }; 380 381 static const struct platform_desc gm45_desc = { 382 PLATFORM(GM45), 383 .info = &(const struct intel_display_device_info) { 384 GEN4_DISPLAY, 385 .supports_tv = 1, 386 387 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 388 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 389 }, 390 }; 391 392 #define ILK_DISPLAY \ 393 .has_hotplug = 1, \ 394 I9XX_PIPE_OFFSETS, \ 395 I9XX_CURSOR_OFFSETS, \ 396 ILK_COLORS, \ 397 \ 398 .__runtime_defaults.ip.ver = 5, \ 399 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 400 .__runtime_defaults.cpu_transcoder_mask = \ 401 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 402 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 403 404 static const struct platform_desc ilk_d_desc = { 405 PLATFORM(IRONLAKE), 406 .info = &(const struct intel_display_device_info) { 407 ILK_DISPLAY, 408 }, 409 }; 410 411 static const struct platform_desc ilk_m_desc = { 412 PLATFORM(IRONLAKE), 413 .info = &(const struct intel_display_device_info) { 414 ILK_DISPLAY, 415 416 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 417 }, 418 }; 419 420 static const struct platform_desc snb_desc = { 421 PLATFORM(SANDYBRIDGE), 422 .info = &(const struct intel_display_device_info) { 423 .has_hotplug = 1, 424 I9XX_PIPE_OFFSETS, 425 I9XX_CURSOR_OFFSETS, 426 ILK_COLORS, 427 428 .__runtime_defaults.ip.ver = 6, 429 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 430 .__runtime_defaults.cpu_transcoder_mask = 431 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 432 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 433 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 434 }, 435 }; 436 437 static const struct platform_desc ivb_desc = { 438 PLATFORM(IVYBRIDGE), 439 .info = &(const struct intel_display_device_info) { 440 .has_hotplug = 1, 441 IVB_PIPE_OFFSETS, 442 IVB_CURSOR_OFFSETS, 443 IVB_COLORS, 444 445 .__runtime_defaults.ip.ver = 7, 446 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 447 .__runtime_defaults.cpu_transcoder_mask = 448 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 449 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 450 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 451 }, 452 }; 453 454 static const struct platform_desc vlv_desc = { 455 PLATFORM(VALLEYVIEW), 456 .info = &(const struct intel_display_device_info) { 457 .has_gmch = 1, 458 .has_hotplug = 1, 459 .mmio_offset = VLV_DISPLAY_BASE, 460 I9XX_PIPE_OFFSETS, 461 I9XX_CURSOR_OFFSETS, 462 I9XX_COLORS, 463 464 .__runtime_defaults.ip.ver = 7, 465 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 466 .__runtime_defaults.cpu_transcoder_mask = 467 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 468 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ 469 }, 470 }; 471 472 static const u16 hsw_ult_ids[] = { 473 INTEL_HSW_ULT_GT1_IDS(ID), 474 INTEL_HSW_ULT_GT2_IDS(ID), 475 INTEL_HSW_ULT_GT3_IDS(ID), 476 0 477 }; 478 479 static const u16 hsw_ulx_ids[] = { 480 INTEL_HSW_ULX_GT1_IDS(ID), 481 INTEL_HSW_ULX_GT2_IDS(ID), 482 0 483 }; 484 485 static const struct platform_desc hsw_desc = { 486 PLATFORM(HASWELL), 487 .subplatforms = (const struct subplatform_desc[]) { 488 { INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids }, 489 { INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids }, 490 {}, 491 }, 492 .info = &(const struct intel_display_device_info) { 493 .has_ddi = 1, 494 .has_dp_mst = 1, 495 .has_fpga_dbg = 1, 496 .has_hotplug = 1, 497 .has_psr = 1, 498 .has_psr_hw_tracking = 1, 499 HSW_PIPE_OFFSETS, 500 IVB_CURSOR_OFFSETS, 501 IVB_COLORS, 502 503 .__runtime_defaults.ip.ver = 7, 504 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 505 .__runtime_defaults.cpu_transcoder_mask = 506 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 507 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 508 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 509 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 510 }, 511 }; 512 513 static const u16 bdw_ult_ids[] = { 514 INTEL_BDW_ULT_GT1_IDS(ID), 515 INTEL_BDW_ULT_GT2_IDS(ID), 516 INTEL_BDW_ULT_GT3_IDS(ID), 517 INTEL_BDW_ULT_RSVD_IDS(ID), 518 0 519 }; 520 521 static const u16 bdw_ulx_ids[] = { 522 INTEL_BDW_ULX_GT1_IDS(ID), 523 INTEL_BDW_ULX_GT2_IDS(ID), 524 INTEL_BDW_ULX_GT3_IDS(ID), 525 INTEL_BDW_ULX_RSVD_IDS(ID), 526 0 527 }; 528 529 static const struct platform_desc bdw_desc = { 530 PLATFORM(BROADWELL), 531 .subplatforms = (const struct subplatform_desc[]) { 532 { INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids }, 533 { INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids }, 534 {}, 535 }, 536 .info = &(const struct intel_display_device_info) { 537 .has_ddi = 1, 538 .has_dp_mst = 1, 539 .has_fpga_dbg = 1, 540 .has_hotplug = 1, 541 .has_psr = 1, 542 .has_psr_hw_tracking = 1, 543 HSW_PIPE_OFFSETS, 544 IVB_CURSOR_OFFSETS, 545 IVB_COLORS, 546 547 .__runtime_defaults.ip.ver = 8, 548 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 549 .__runtime_defaults.cpu_transcoder_mask = 550 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 551 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 552 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 553 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 554 }, 555 }; 556 557 static const struct platform_desc chv_desc = { 558 PLATFORM(CHERRYVIEW), 559 .info = &(const struct intel_display_device_info) { 560 .has_hotplug = 1, 561 .has_gmch = 1, 562 .mmio_offset = VLV_DISPLAY_BASE, 563 CHV_PIPE_OFFSETS, 564 CHV_CURSOR_OFFSETS, 565 CHV_COLORS, 566 567 .__runtime_defaults.ip.ver = 8, 568 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 569 .__runtime_defaults.cpu_transcoder_mask = 570 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 571 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ 572 }, 573 }; 574 575 static const struct intel_display_device_info skl_display = { 576 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ 577 .dbuf.slice_mask = BIT(DBUF_S1), 578 .has_ddi = 1, 579 .has_dp_mst = 1, 580 .has_fpga_dbg = 1, 581 .has_hotplug = 1, 582 .has_ipc = 1, 583 .has_psr = 1, 584 .has_psr_hw_tracking = 1, 585 HSW_PIPE_OFFSETS, 586 IVB_CURSOR_OFFSETS, 587 IVB_COLORS, 588 589 .__runtime_defaults.ip.ver = 9, 590 .__runtime_defaults.has_dmc = 1, 591 .__runtime_defaults.has_hdcp = 1, 592 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 593 .__runtime_defaults.cpu_transcoder_mask = 594 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 595 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 596 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 597 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 598 }; 599 600 static const u16 skl_ult_ids[] = { 601 INTEL_SKL_ULT_GT1_IDS(ID), 602 INTEL_SKL_ULT_GT2_IDS(ID), 603 INTEL_SKL_ULT_GT3_IDS(ID), 604 0 605 }; 606 607 static const u16 skl_ulx_ids[] = { 608 INTEL_SKL_ULX_GT1_IDS(ID), 609 INTEL_SKL_ULX_GT2_IDS(ID), 610 0 611 }; 612 613 static const struct platform_desc skl_desc = { 614 PLATFORM(SKYLAKE), 615 .subplatforms = (const struct subplatform_desc[]) { 616 { INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids }, 617 { INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids }, 618 {}, 619 }, 620 .info = &skl_display, 621 }; 622 623 static const u16 kbl_ult_ids[] = { 624 INTEL_KBL_ULT_GT1_IDS(ID), 625 INTEL_KBL_ULT_GT2_IDS(ID), 626 INTEL_KBL_ULT_GT3_IDS(ID), 627 0 628 }; 629 630 static const u16 kbl_ulx_ids[] = { 631 INTEL_KBL_ULX_GT1_IDS(ID), 632 INTEL_KBL_ULX_GT2_IDS(ID), 633 INTEL_AML_KBL_GT2_IDS(ID), 634 0 635 }; 636 637 static const struct platform_desc kbl_desc = { 638 PLATFORM(KABYLAKE), 639 .subplatforms = (const struct subplatform_desc[]) { 640 { INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids }, 641 { INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids }, 642 {}, 643 }, 644 .info = &skl_display, 645 }; 646 647 static const u16 cfl_ult_ids[] = { 648 INTEL_CFL_U_GT2_IDS(ID), 649 INTEL_CFL_U_GT3_IDS(ID), 650 INTEL_WHL_U_GT1_IDS(ID), 651 INTEL_WHL_U_GT2_IDS(ID), 652 INTEL_WHL_U_GT3_IDS(ID), 653 0 654 }; 655 656 static const u16 cfl_ulx_ids[] = { 657 INTEL_AML_CFL_GT2_IDS(ID), 658 0 659 }; 660 661 static const struct platform_desc cfl_desc = { 662 PLATFORM(COFFEELAKE), 663 .subplatforms = (const struct subplatform_desc[]) { 664 { INTEL_DISPLAY_COFFEELAKE_ULT, "ULT", cfl_ult_ids }, 665 { INTEL_DISPLAY_COFFEELAKE_ULX, "ULX", cfl_ulx_ids }, 666 {}, 667 }, 668 .info = &skl_display, 669 }; 670 671 static const u16 cml_ult_ids[] = { 672 INTEL_CML_U_GT1_IDS(ID), 673 INTEL_CML_U_GT2_IDS(ID), 674 0 675 }; 676 677 static const struct platform_desc cml_desc = { 678 PLATFORM(COMETLAKE), 679 .subplatforms = (const struct subplatform_desc[]) { 680 { INTEL_DISPLAY_COMETLAKE_ULT, "ULT", cml_ult_ids }, 681 {}, 682 }, 683 .info = &skl_display, 684 }; 685 686 #define GEN9_LP_DISPLAY \ 687 .dbuf.slice_mask = BIT(DBUF_S1), \ 688 .has_dp_mst = 1, \ 689 .has_ddi = 1, \ 690 .has_fpga_dbg = 1, \ 691 .has_hotplug = 1, \ 692 .has_ipc = 1, \ 693 .has_psr = 1, \ 694 .has_psr_hw_tracking = 1, \ 695 HSW_PIPE_OFFSETS, \ 696 IVB_CURSOR_OFFSETS, \ 697 IVB_COLORS, \ 698 \ 699 .__runtime_defaults.has_dmc = 1, \ 700 .__runtime_defaults.has_hdcp = 1, \ 701 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 702 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 703 .__runtime_defaults.cpu_transcoder_mask = \ 704 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 705 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 706 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 707 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) 708 709 static const struct platform_desc bxt_desc = { 710 PLATFORM(BROXTON), 711 .info = &(const struct intel_display_device_info) { 712 GEN9_LP_DISPLAY, 713 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 714 715 .__runtime_defaults.ip.ver = 9, 716 }, 717 }; 718 719 static const struct platform_desc glk_desc = { 720 PLATFORM(GEMINILAKE), 721 .info = &(const struct intel_display_device_info) { 722 GEN9_LP_DISPLAY, 723 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 724 GLK_COLORS, 725 726 .__runtime_defaults.ip.ver = 10, 727 }, 728 }; 729 730 #define ICL_DISPLAY \ 731 .abox_mask = BIT(0), \ 732 .dbuf.size = 2048, \ 733 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 734 .has_ddi = 1, \ 735 .has_dp_mst = 1, \ 736 .has_fpga_dbg = 1, \ 737 .has_hotplug = 1, \ 738 .has_ipc = 1, \ 739 .has_psr = 1, \ 740 .has_psr_hw_tracking = 1, \ 741 .pipe_offsets = { \ 742 [TRANSCODER_A] = PIPE_A_OFFSET, \ 743 [TRANSCODER_B] = PIPE_B_OFFSET, \ 744 [TRANSCODER_C] = PIPE_C_OFFSET, \ 745 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 746 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 747 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 748 }, \ 749 .trans_offsets = { \ 750 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 751 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 752 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 753 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 754 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 755 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 756 }, \ 757 IVB_CURSOR_OFFSETS, \ 758 ICL_COLORS, \ 759 \ 760 .__runtime_defaults.ip.ver = 11, \ 761 .__runtime_defaults.has_dmc = 1, \ 762 .__runtime_defaults.has_dsc = 1, \ 763 .__runtime_defaults.has_hdcp = 1, \ 764 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 765 .__runtime_defaults.cpu_transcoder_mask = \ 766 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 767 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 768 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 769 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 770 771 static const u16 icl_port_f_ids[] = { 772 INTEL_ICL_PORT_F_IDS(ID), 773 0 774 }; 775 776 static const struct platform_desc icl_desc = { 777 PLATFORM(ICELAKE), 778 .subplatforms = (const struct subplatform_desc[]) { 779 { INTEL_DISPLAY_ICELAKE_PORT_F, "Port F", icl_port_f_ids }, 780 {}, 781 }, 782 .info = &(const struct intel_display_device_info) { 783 ICL_DISPLAY, 784 785 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 786 }, 787 }; 788 789 static const struct intel_display_device_info jsl_ehl_display = { 790 ICL_DISPLAY, 791 792 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), 793 }; 794 795 static const struct platform_desc jsl_desc = { 796 PLATFORM(JASPERLAKE), 797 .info = &jsl_ehl_display, 798 }; 799 800 static const struct platform_desc ehl_desc = { 801 PLATFORM(ELKHARTLAKE), 802 .info = &jsl_ehl_display, 803 }; 804 805 #define XE_D_DISPLAY \ 806 .abox_mask = GENMASK(2, 1), \ 807 .dbuf.size = 2048, \ 808 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 809 .has_ddi = 1, \ 810 .has_dp_mst = 1, \ 811 .has_dsb = 1, \ 812 .has_fpga_dbg = 1, \ 813 .has_hotplug = 1, \ 814 .has_ipc = 1, \ 815 .has_psr = 1, \ 816 .has_psr_hw_tracking = 1, \ 817 .pipe_offsets = { \ 818 [TRANSCODER_A] = PIPE_A_OFFSET, \ 819 [TRANSCODER_B] = PIPE_B_OFFSET, \ 820 [TRANSCODER_C] = PIPE_C_OFFSET, \ 821 [TRANSCODER_D] = PIPE_D_OFFSET, \ 822 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 823 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 824 }, \ 825 .trans_offsets = { \ 826 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 827 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 828 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 829 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 830 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 831 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 832 }, \ 833 TGL_CURSOR_OFFSETS, \ 834 ICL_COLORS, \ 835 \ 836 .__runtime_defaults.ip.ver = 12, \ 837 .__runtime_defaults.has_dmc = 1, \ 838 .__runtime_defaults.has_dsc = 1, \ 839 .__runtime_defaults.has_hdcp = 1, \ 840 .__runtime_defaults.pipe_mask = \ 841 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 842 .__runtime_defaults.cpu_transcoder_mask = \ 843 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 844 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 845 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 846 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 847 848 static const u16 tgl_uy_ids[] = { 849 INTEL_TGL_GT2_IDS(ID), 850 0 851 }; 852 853 static const struct platform_desc tgl_desc = { 854 PLATFORM(TIGERLAKE), 855 .subplatforms = (const struct subplatform_desc[]) { 856 { INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids }, 857 {}, 858 }, 859 .info = &(const struct intel_display_device_info) { 860 XE_D_DISPLAY, 861 862 /* 863 * FIXME DDI C/combo PHY C missing due to combo PHY 864 * code making a mess on SKUs where the PHY is missing. 865 */ 866 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 867 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), 868 }, 869 }; 870 871 static const struct platform_desc dg1_desc = { 872 PLATFORM(DG1), 873 .info = &(const struct intel_display_device_info) { 874 XE_D_DISPLAY, 875 876 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 877 BIT(PORT_TC1) | BIT(PORT_TC2), 878 }, 879 }; 880 881 static const struct platform_desc rkl_desc = { 882 PLATFORM(ROCKETLAKE), 883 .info = &(const struct intel_display_device_info) { 884 XE_D_DISPLAY, 885 .abox_mask = BIT(0), 886 .has_hti = 1, 887 .has_psr_hw_tracking = 0, 888 889 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 890 .__runtime_defaults.cpu_transcoder_mask = 891 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 892 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 893 BIT(PORT_TC1) | BIT(PORT_TC2), 894 }, 895 }; 896 897 static const u16 adls_rpls_ids[] = { 898 INTEL_RPLS_IDS(ID), 899 0 900 }; 901 902 static const struct platform_desc adl_s_desc = { 903 PLATFORM(ALDERLAKE_S), 904 .subplatforms = (const struct subplatform_desc[]) { 905 { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids }, 906 {}, 907 }, 908 .info = &(const struct intel_display_device_info) { 909 XE_D_DISPLAY, 910 .has_hti = 1, 911 .has_psr_hw_tracking = 0, 912 913 .__runtime_defaults.port_mask = BIT(PORT_A) | 914 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 915 }, 916 }; 917 918 #define XE_LPD_FEATURES \ 919 .abox_mask = GENMASK(1, 0), \ 920 .color = { \ 921 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 922 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 923 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 924 }, \ 925 .dbuf.size = 4096, \ 926 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 927 BIT(DBUF_S4), \ 928 .has_ddi = 1, \ 929 .has_dp_mst = 1, \ 930 .has_dsb = 1, \ 931 .has_fpga_dbg = 1, \ 932 .has_hotplug = 1, \ 933 .has_ipc = 1, \ 934 .has_psr = 1, \ 935 .pipe_offsets = { \ 936 [TRANSCODER_A] = PIPE_A_OFFSET, \ 937 [TRANSCODER_B] = PIPE_B_OFFSET, \ 938 [TRANSCODER_C] = PIPE_C_OFFSET, \ 939 [TRANSCODER_D] = PIPE_D_OFFSET, \ 940 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 941 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 942 }, \ 943 .trans_offsets = { \ 944 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 945 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 946 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 947 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 948 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 949 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 950 }, \ 951 TGL_CURSOR_OFFSETS, \ 952 \ 953 .__runtime_defaults.ip.ver = 13, \ 954 .__runtime_defaults.has_dmc = 1, \ 955 .__runtime_defaults.has_dsc = 1, \ 956 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 957 .__runtime_defaults.has_hdcp = 1, \ 958 .__runtime_defaults.pipe_mask = \ 959 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D) 960 961 static const struct intel_display_device_info xe_lpd_display = { 962 XE_LPD_FEATURES, 963 .has_cdclk_crawl = 1, 964 .has_psr_hw_tracking = 0, 965 966 .__runtime_defaults.cpu_transcoder_mask = 967 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 968 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 969 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 970 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 971 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 972 }; 973 974 static const u16 adlp_adln_ids[] = { 975 INTEL_ADLN_IDS(ID), 976 0 977 }; 978 979 static const u16 adlp_rplu_ids[] = { 980 INTEL_RPLU_IDS(ID), 981 0 982 }; 983 984 static const u16 adlp_rplp_ids[] = { 985 INTEL_RPLP_IDS(ID), 986 0 987 }; 988 989 static const struct platform_desc adl_p_desc = { 990 PLATFORM(ALDERLAKE_P), 991 .subplatforms = (const struct subplatform_desc[]) { 992 { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids }, 993 { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids }, 994 { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids }, 995 {}, 996 }, 997 .info = &xe_lpd_display, 998 }; 999 1000 static const struct intel_display_device_info xe_hpd_display = { 1001 XE_LPD_FEATURES, 1002 .has_cdclk_squash = 1, 1003 1004 .__runtime_defaults.cpu_transcoder_mask = 1005 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1006 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1007 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) | 1008 BIT(PORT_TC1), 1009 }; 1010 1011 static const u16 dg2_g10_ids[] = { 1012 INTEL_DG2_G10_IDS(ID), 1013 0 1014 }; 1015 1016 static const u16 dg2_g11_ids[] = { 1017 INTEL_DG2_G11_IDS(ID), 1018 0 1019 }; 1020 1021 static const u16 dg2_g12_ids[] = { 1022 INTEL_DG2_G12_IDS(ID), 1023 0 1024 }; 1025 1026 static const struct platform_desc dg2_desc = { 1027 PLATFORM(DG2), 1028 .subplatforms = (const struct subplatform_desc[]) { 1029 { INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids }, 1030 { INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids }, 1031 { INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids }, 1032 {}, 1033 }, 1034 .info = &xe_hpd_display, 1035 }; 1036 1037 #define XE_LPDP_FEATURES \ 1038 .abox_mask = GENMASK(1, 0), \ 1039 .color = { \ 1040 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 1041 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 1042 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 1043 }, \ 1044 .dbuf.size = 4096, \ 1045 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 1046 BIT(DBUF_S4), \ 1047 .has_cdclk_crawl = 1, \ 1048 .has_cdclk_squash = 1, \ 1049 .has_ddi = 1, \ 1050 .has_dp_mst = 1, \ 1051 .has_dsb = 1, \ 1052 .has_fpga_dbg = 1, \ 1053 .has_hotplug = 1, \ 1054 .has_ipc = 1, \ 1055 .has_psr = 1, \ 1056 .pipe_offsets = { \ 1057 [TRANSCODER_A] = PIPE_A_OFFSET, \ 1058 [TRANSCODER_B] = PIPE_B_OFFSET, \ 1059 [TRANSCODER_C] = PIPE_C_OFFSET, \ 1060 [TRANSCODER_D] = PIPE_D_OFFSET, \ 1061 }, \ 1062 .trans_offsets = { \ 1063 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 1064 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 1065 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 1066 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 1067 }, \ 1068 TGL_CURSOR_OFFSETS, \ 1069 \ 1070 .__runtime_defaults.cpu_transcoder_mask = \ 1071 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 1072 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ 1073 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \ 1074 .__runtime_defaults.has_dmc = 1, \ 1075 .__runtime_defaults.has_dsc = 1, \ 1076 .__runtime_defaults.has_hdcp = 1, \ 1077 .__runtime_defaults.pipe_mask = \ 1078 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 1079 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \ 1080 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) 1081 1082 static const struct intel_display_device_info xe_lpdp_display = { 1083 XE_LPDP_FEATURES, 1084 }; 1085 1086 static const struct intel_display_device_info xe2_lpd_display = { 1087 XE_LPDP_FEATURES, 1088 1089 .__runtime_defaults.fbc_mask = 1090 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | 1091 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), 1092 }; 1093 1094 static const struct intel_display_device_info xe2_hpd_display = { 1095 XE_LPDP_FEATURES, 1096 .__runtime_defaults.port_mask = BIT(PORT_A) | 1097 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1098 }; 1099 1100 /* 1101 * Do not initialize the .info member of the platform desc for GMD ID based 1102 * platforms. Their display will be probed automatically based on the IP version 1103 * reported by the hardware. 1104 */ 1105 static const struct platform_desc mtl_desc = { 1106 PLATFORM(METEORLAKE), 1107 }; 1108 1109 static const struct platform_desc lnl_desc = { 1110 PLATFORM(LUNARLAKE), 1111 }; 1112 1113 static const struct platform_desc bmg_desc = { 1114 PLATFORM(BATTLEMAGE), 1115 }; 1116 1117 __diag_pop(); 1118 1119 /* 1120 * Separate detection for no display cases to keep the display id array simple. 1121 * 1122 * IVB Q requires subvendor and subdevice matching to differentiate from IVB D 1123 * GT2 server. 1124 */ 1125 static bool has_no_display(struct pci_dev *pdev) 1126 { 1127 static const struct pci_device_id ids[] = { 1128 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0), 1129 {} 1130 }; 1131 1132 return pci_match_id(ids, pdev); 1133 } 1134 1135 #define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) } 1136 1137 static const struct { 1138 u32 devid; 1139 const struct platform_desc *desc; 1140 } intel_display_ids[] = { 1141 INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_desc), 1142 INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_desc), 1143 INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_desc), 1144 INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_desc), 1145 INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_desc), 1146 INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_desc), 1147 INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_desc), 1148 INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_desc), 1149 INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_desc), 1150 INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_desc), 1151 INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc), 1152 INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc), 1153 INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc), 1154 INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_desc), 1155 INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc), 1156 INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc), 1157 INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_desc), 1158 INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_desc), 1159 INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc), 1160 INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc), 1161 INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc), 1162 INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_desc), 1163 INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_desc), 1164 INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_desc), 1165 INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_desc), 1166 INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &kbl_desc), 1167 INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), 1168 INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), 1169 INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &cml_desc), 1170 INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_desc), 1171 INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &ehl_desc), 1172 INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_desc), 1173 INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_desc), 1174 INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_desc), 1175 INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_desc), 1176 INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), 1177 INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), 1178 INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1179 INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1180 INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1181 INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1182 INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), 1183 INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), 1184 INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), 1185 INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), 1186 }; 1187 1188 static const struct { 1189 u16 ver; 1190 u16 rel; 1191 const struct intel_display_device_info *display; 1192 } gmdid_display_map[] = { 1193 { 14, 0, &xe_lpdp_display }, 1194 { 14, 1, &xe2_hpd_display }, 1195 { 20, 0, &xe2_lpd_display }, 1196 }; 1197 1198 static const struct intel_display_device_info * 1199 probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver *ip_ver) 1200 { 1201 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1202 struct intel_display_ip_ver gmd_id; 1203 void __iomem *addr; 1204 u32 val; 1205 int i; 1206 1207 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 1208 if (!addr) { 1209 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); 1210 return NULL; 1211 } 1212 1213 val = ioread32(addr); 1214 pci_iounmap(pdev, addr); 1215 1216 if (val == 0) { 1217 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 1218 return NULL; 1219 } 1220 1221 gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 1222 gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 1223 gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val); 1224 1225 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { 1226 if (gmd_id.ver == gmdid_display_map[i].ver && 1227 gmd_id.rel == gmdid_display_map[i].rel) { 1228 *ip_ver = gmd_id; 1229 return gmdid_display_map[i].display; 1230 } 1231 } 1232 1233 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", 1234 gmd_id.ver, gmd_id.rel); 1235 return NULL; 1236 } 1237 1238 static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) 1239 { 1240 int i; 1241 1242 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { 1243 if (intel_display_ids[i].devid == pdev->device) 1244 return intel_display_ids[i].desc; 1245 } 1246 1247 return NULL; 1248 } 1249 1250 static const struct subplatform_desc * 1251 find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc) 1252 { 1253 const struct subplatform_desc *sp; 1254 const u16 *id; 1255 1256 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 1257 for (id = sp->pciidlist; *id; id++) 1258 if (*id == pdev->device) 1259 return sp; 1260 1261 return NULL; 1262 } 1263 1264 void intel_display_device_probe(struct drm_i915_private *i915) 1265 { 1266 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1267 const struct intel_display_device_info *info; 1268 struct intel_display_ip_ver ip_ver = {}; 1269 const struct platform_desc *desc; 1270 const struct subplatform_desc *subdesc; 1271 1272 /* Add drm device backpointer as early as possible. */ 1273 i915->display.drm = &i915->drm; 1274 1275 intel_display_params_copy(&i915->display.params); 1276 1277 if (has_no_display(pdev)) { 1278 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 1279 goto no_display; 1280 } 1281 1282 desc = find_platform_desc(pdev); 1283 if (!desc) { 1284 drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n", 1285 pdev->device); 1286 goto no_display; 1287 } 1288 1289 info = desc->info; 1290 if (!info) 1291 info = probe_gmdid_display(i915, &ip_ver); 1292 if (!info) 1293 goto no_display; 1294 1295 DISPLAY_INFO(i915) = info; 1296 1297 memcpy(DISPLAY_RUNTIME_INFO(i915), 1298 &DISPLAY_INFO(i915)->__runtime_defaults, 1299 sizeof(*DISPLAY_RUNTIME_INFO(i915))); 1300 1301 drm_WARN_ON(&i915->drm, !desc->platform || !desc->name); 1302 DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform; 1303 1304 subdesc = find_subplatform_desc(pdev, desc); 1305 if (subdesc) { 1306 drm_WARN_ON(&i915->drm, !subdesc->subplatform || !subdesc->name); 1307 DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform; 1308 } 1309 1310 if (ip_ver.ver || ip_ver.rel || ip_ver.step) 1311 DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; 1312 1313 drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u\n", 1314 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", 1315 pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, 1316 DISPLAY_RUNTIME_INFO(i915)->ip.rel); 1317 1318 return; 1319 1320 no_display: 1321 DISPLAY_INFO(i915) = &no_display; 1322 } 1323 1324 void intel_display_device_remove(struct drm_i915_private *i915) 1325 { 1326 intel_display_params_free(&i915->display.params); 1327 } 1328 1329 static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1330 { 1331 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); 1332 enum pipe pipe; 1333 1334 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); 1335 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); 1336 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); 1337 1338 /* This covers both ULT and ULX */ 1339 if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915)) 1340 display_runtime->port_mask &= ~BIT(PORT_D); 1341 1342 if (IS_ICL_WITH_PORT_F(i915)) 1343 display_runtime->port_mask |= BIT(PORT_F); 1344 1345 /* Wa_14011765242: adl-s A0,A1 */ 1346 if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) 1347 for_each_pipe(i915, pipe) 1348 display_runtime->num_scalers[pipe] = 0; 1349 else if (DISPLAY_VER(i915) >= 11) { 1350 for_each_pipe(i915, pipe) 1351 display_runtime->num_scalers[pipe] = 2; 1352 } else if (DISPLAY_VER(i915) >= 9) { 1353 display_runtime->num_scalers[PIPE_A] = 2; 1354 display_runtime->num_scalers[PIPE_B] = 2; 1355 display_runtime->num_scalers[PIPE_C] = 1; 1356 } 1357 1358 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 1359 for_each_pipe(i915, pipe) 1360 display_runtime->num_sprites[pipe] = 4; 1361 else if (DISPLAY_VER(i915) >= 11) 1362 for_each_pipe(i915, pipe) 1363 display_runtime->num_sprites[pipe] = 6; 1364 else if (DISPLAY_VER(i915) == 10) 1365 for_each_pipe(i915, pipe) 1366 display_runtime->num_sprites[pipe] = 3; 1367 else if (IS_BROXTON(i915)) { 1368 /* 1369 * Skylake and Broxton currently don't expose the topmost plane as its 1370 * use is exclusive with the legacy cursor and we only want to expose 1371 * one of those, not both. Until we can safely expose the topmost plane 1372 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 1373 * we don't expose the topmost plane at all to prevent ABI breakage 1374 * down the line. 1375 */ 1376 1377 display_runtime->num_sprites[PIPE_A] = 2; 1378 display_runtime->num_sprites[PIPE_B] = 2; 1379 display_runtime->num_sprites[PIPE_C] = 1; 1380 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1381 for_each_pipe(i915, pipe) 1382 display_runtime->num_sprites[pipe] = 2; 1383 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { 1384 for_each_pipe(i915, pipe) 1385 display_runtime->num_sprites[pipe] = 1; 1386 } 1387 1388 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && 1389 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { 1390 drm_info(&i915->drm, "Display not present, disabling\n"); 1391 goto display_fused_off; 1392 } 1393 1394 if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { 1395 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); 1396 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); 1397 1398 /* 1399 * SFUSE_STRAP is supposed to have a bit signalling the display 1400 * is fused off. Unfortunately it seems that, at least in 1401 * certain cases, fused off display means that PCH display 1402 * reads don't land anywhere. In that case, we read 0s. 1403 * 1404 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 1405 * should be set when taking over after the firmware. 1406 */ 1407 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 1408 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 1409 (HAS_PCH_CPT(i915) && 1410 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 1411 drm_info(&i915->drm, 1412 "Display fused off, disabling\n"); 1413 goto display_fused_off; 1414 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 1415 drm_info(&i915->drm, "PipeC fused off\n"); 1416 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1417 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1418 } 1419 } else if (DISPLAY_VER(i915) >= 9) { 1420 u32 dfsm = intel_de_read(i915, SKL_DFSM); 1421 1422 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 1423 display_runtime->pipe_mask &= ~BIT(PIPE_A); 1424 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 1425 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 1426 } 1427 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 1428 display_runtime->pipe_mask &= ~BIT(PIPE_B); 1429 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 1430 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); 1431 } 1432 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 1433 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1434 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1435 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); 1436 } 1437 1438 if (DISPLAY_VER(i915) >= 12 && 1439 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1440 display_runtime->pipe_mask &= ~BIT(PIPE_D); 1441 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 1442 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); 1443 } 1444 1445 if (!display_runtime->pipe_mask) 1446 goto display_fused_off; 1447 1448 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1449 display_runtime->has_hdcp = 0; 1450 1451 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1452 display_runtime->fbc_mask = 0; 1453 1454 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1455 display_runtime->has_dmc = 0; 1456 1457 if (IS_DISPLAY_VER(i915, 10, 12) && 1458 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 1459 display_runtime->has_dsc = 0; 1460 } 1461 1462 if (DISPLAY_VER(i915) >= 20) { 1463 u32 cap = intel_de_read(i915, XE2LPD_DE_CAP); 1464 1465 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == 1466 XE2LPD_DE_CAP_DSC_REMOVED) 1467 display_runtime->has_dsc = 0; 1468 1469 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) == 1470 XE2LPD_DE_CAP_SCALER_SINGLE) { 1471 for_each_pipe(i915, pipe) 1472 if (display_runtime->num_scalers[pipe]) 1473 display_runtime->num_scalers[pipe] = 1; 1474 } 1475 } 1476 1477 return; 1478 1479 display_fused_off: 1480 memset(display_runtime, 0, sizeof(*display_runtime)); 1481 } 1482 1483 void intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1484 { 1485 if (HAS_DISPLAY(i915)) 1486 __intel_display_device_info_runtime_init(i915); 1487 1488 /* Display may have been disabled by runtime init */ 1489 if (!HAS_DISPLAY(i915)) { 1490 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 1491 i915->display.info.__device_info = &no_display; 1492 } 1493 1494 /* Disable nuclear pageflip by default on pre-g4x */ 1495 if (!i915->display.params.nuclear_pageflip && 1496 DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) 1497 i915->drm.driver_features &= ~DRIVER_ATOMIC; 1498 } 1499 1500 void intel_display_device_info_print(const struct intel_display_device_info *info, 1501 const struct intel_display_runtime_info *runtime, 1502 struct drm_printer *p) 1503 { 1504 if (runtime->ip.rel) 1505 drm_printf(p, "display version: %u.%02u\n", 1506 runtime->ip.ver, 1507 runtime->ip.rel); 1508 else 1509 drm_printf(p, "display version: %u\n", 1510 runtime->ip.ver); 1511 1512 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 1513 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 1514 #undef PRINT_FLAG 1515 1516 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); 1517 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); 1518 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); 1519 } 1520 1521 /* 1522 * Assuming the device has display hardware, should it be enabled? 1523 * 1524 * It's an error to call this function if the device does not have display 1525 * hardware. 1526 * 1527 * Disabling display means taking over the display hardware, putting it to 1528 * sleep, and preventing connectors from being connected via any means. 1529 */ 1530 bool intel_display_device_enabled(struct drm_i915_private *i915) 1531 { 1532 /* Only valid when HAS_DISPLAY() is true */ 1533 drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915)); 1534 1535 return !i915->display.params.disable_display && 1536 !intel_opregion_headless_sku(i915); 1537 } 1538