1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/i915_pciids.h> 7 #include <drm/drm_color_mgmt.h> 8 #include <linux/pci.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_de.h" 13 #include "intel_display.h" 14 #include "intel_display_device.h" 15 #include "intel_display_params.h" 16 #include "intel_display_power.h" 17 #include "intel_display_reg_defs.h" 18 #include "intel_fbc.h" 19 20 __diag_push(); 21 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); 22 23 static const struct intel_display_device_info no_display = {}; 24 25 #define PIPE_A_OFFSET 0x70000 26 #define PIPE_B_OFFSET 0x71000 27 #define PIPE_C_OFFSET 0x72000 28 #define PIPE_D_OFFSET 0x73000 29 #define CHV_PIPE_C_OFFSET 0x74000 30 /* 31 * There's actually no pipe EDP. Some pipe registers have 32 * simply shifted from the pipe to the transcoder, while 33 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 34 * to access such registers in transcoder EDP. 35 */ 36 #define PIPE_EDP_OFFSET 0x7f000 37 38 /* ICL DSI 0 and 1 */ 39 #define PIPE_DSI0_OFFSET 0x7b000 40 #define PIPE_DSI1_OFFSET 0x7b800 41 42 #define TRANSCODER_A_OFFSET 0x60000 43 #define TRANSCODER_B_OFFSET 0x61000 44 #define TRANSCODER_C_OFFSET 0x62000 45 #define CHV_TRANSCODER_C_OFFSET 0x63000 46 #define TRANSCODER_D_OFFSET 0x63000 47 #define TRANSCODER_EDP_OFFSET 0x6f000 48 #define TRANSCODER_DSI0_OFFSET 0x6b000 49 #define TRANSCODER_DSI1_OFFSET 0x6b800 50 51 #define CURSOR_A_OFFSET 0x70080 52 #define CURSOR_B_OFFSET 0x700c0 53 #define CHV_CURSOR_C_OFFSET 0x700e0 54 #define IVB_CURSOR_B_OFFSET 0x71080 55 #define IVB_CURSOR_C_OFFSET 0x72080 56 #define TGL_CURSOR_D_OFFSET 0x73080 57 58 #define I845_PIPE_OFFSETS \ 59 .pipe_offsets = { \ 60 [TRANSCODER_A] = PIPE_A_OFFSET, \ 61 }, \ 62 .trans_offsets = { \ 63 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 64 } 65 66 #define I9XX_PIPE_OFFSETS \ 67 .pipe_offsets = { \ 68 [TRANSCODER_A] = PIPE_A_OFFSET, \ 69 [TRANSCODER_B] = PIPE_B_OFFSET, \ 70 }, \ 71 .trans_offsets = { \ 72 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 73 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 74 } 75 76 #define IVB_PIPE_OFFSETS \ 77 .pipe_offsets = { \ 78 [TRANSCODER_A] = PIPE_A_OFFSET, \ 79 [TRANSCODER_B] = PIPE_B_OFFSET, \ 80 [TRANSCODER_C] = PIPE_C_OFFSET, \ 81 }, \ 82 .trans_offsets = { \ 83 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 84 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 85 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 86 } 87 88 #define HSW_PIPE_OFFSETS \ 89 .pipe_offsets = { \ 90 [TRANSCODER_A] = PIPE_A_OFFSET, \ 91 [TRANSCODER_B] = PIPE_B_OFFSET, \ 92 [TRANSCODER_C] = PIPE_C_OFFSET, \ 93 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 94 }, \ 95 .trans_offsets = { \ 96 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 97 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 98 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 99 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 100 } 101 102 #define CHV_PIPE_OFFSETS \ 103 .pipe_offsets = { \ 104 [TRANSCODER_A] = PIPE_A_OFFSET, \ 105 [TRANSCODER_B] = PIPE_B_OFFSET, \ 106 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 107 }, \ 108 .trans_offsets = { \ 109 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 110 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 111 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 112 } 113 114 #define I845_CURSOR_OFFSETS \ 115 .cursor_offsets = { \ 116 [PIPE_A] = CURSOR_A_OFFSET, \ 117 } 118 119 #define I9XX_CURSOR_OFFSETS \ 120 .cursor_offsets = { \ 121 [PIPE_A] = CURSOR_A_OFFSET, \ 122 [PIPE_B] = CURSOR_B_OFFSET, \ 123 } 124 125 #define CHV_CURSOR_OFFSETS \ 126 .cursor_offsets = { \ 127 [PIPE_A] = CURSOR_A_OFFSET, \ 128 [PIPE_B] = CURSOR_B_OFFSET, \ 129 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 130 } 131 132 #define IVB_CURSOR_OFFSETS \ 133 .cursor_offsets = { \ 134 [PIPE_A] = CURSOR_A_OFFSET, \ 135 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 136 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 137 } 138 139 #define TGL_CURSOR_OFFSETS \ 140 .cursor_offsets = { \ 141 [PIPE_A] = CURSOR_A_OFFSET, \ 142 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 143 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 144 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 145 } 146 147 #define I845_COLORS \ 148 .color = { .gamma_lut_size = 256 } 149 #define I9XX_COLORS \ 150 .color = { .gamma_lut_size = 129, \ 151 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 152 } 153 #define ILK_COLORS \ 154 .color = { .gamma_lut_size = 1024 } 155 #define IVB_COLORS \ 156 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 157 #define CHV_COLORS \ 158 .color = { \ 159 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 160 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 161 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 162 } 163 #define GLK_COLORS \ 164 .color = { \ 165 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 166 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 167 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 168 } 169 #define ICL_COLORS \ 170 .color = { \ 171 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 172 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 173 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 174 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 175 } 176 177 #define I830_DISPLAY \ 178 .has_overlay = 1, \ 179 .cursor_needs_physical = 1, \ 180 .overlay_needs_physical = 1, \ 181 .has_gmch = 1, \ 182 I9XX_PIPE_OFFSETS, \ 183 I9XX_CURSOR_OFFSETS, \ 184 I9XX_COLORS, \ 185 \ 186 .__runtime_defaults.ip.ver = 2, \ 187 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 188 .__runtime_defaults.cpu_transcoder_mask = \ 189 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 190 191 #define I845_DISPLAY \ 192 .has_overlay = 1, \ 193 .overlay_needs_physical = 1, \ 194 .has_gmch = 1, \ 195 I845_PIPE_OFFSETS, \ 196 I845_CURSOR_OFFSETS, \ 197 I845_COLORS, \ 198 \ 199 .__runtime_defaults.ip.ver = 2, \ 200 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ 201 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) 202 203 static const struct intel_display_device_info i830_display = { 204 I830_DISPLAY, 205 206 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ 207 }; 208 209 static const struct intel_display_device_info i845_display = { 210 I845_DISPLAY, 211 212 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 213 }; 214 215 static const struct intel_display_device_info i85x_display = { 216 I830_DISPLAY, 217 218 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 219 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 220 }; 221 222 static const struct intel_display_device_info i865g_display = { 223 I845_DISPLAY, 224 225 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 226 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 227 }; 228 229 #define GEN3_DISPLAY \ 230 .has_gmch = 1, \ 231 .has_overlay = 1, \ 232 I9XX_PIPE_OFFSETS, \ 233 I9XX_CURSOR_OFFSETS, \ 234 \ 235 .__runtime_defaults.ip.ver = 3, \ 236 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 237 .__runtime_defaults.cpu_transcoder_mask = \ 238 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 239 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ 240 241 static const struct intel_display_device_info i915g_display = { 242 GEN3_DISPLAY, 243 I845_COLORS, 244 .cursor_needs_physical = 1, 245 .overlay_needs_physical = 1, 246 }; 247 248 static const struct intel_display_device_info i915gm_display = { 249 GEN3_DISPLAY, 250 I9XX_COLORS, 251 .cursor_needs_physical = 1, 252 .overlay_needs_physical = 1, 253 .supports_tv = 1, 254 255 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 256 }; 257 258 static const struct intel_display_device_info i945g_display = { 259 GEN3_DISPLAY, 260 I845_COLORS, 261 .has_hotplug = 1, 262 .cursor_needs_physical = 1, 263 .overlay_needs_physical = 1, 264 }; 265 266 static const struct intel_display_device_info i945gm_display = { 267 GEN3_DISPLAY, 268 I9XX_COLORS, 269 .has_hotplug = 1, 270 .cursor_needs_physical = 1, 271 .overlay_needs_physical = 1, 272 .supports_tv = 1, 273 274 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 275 }; 276 277 static const struct intel_display_device_info g33_display = { 278 GEN3_DISPLAY, 279 I845_COLORS, 280 .has_hotplug = 1, 281 }; 282 283 static const struct intel_display_device_info pnv_display = { 284 GEN3_DISPLAY, 285 I9XX_COLORS, 286 .has_hotplug = 1, 287 }; 288 289 #define GEN4_DISPLAY \ 290 .has_hotplug = 1, \ 291 .has_gmch = 1, \ 292 I9XX_PIPE_OFFSETS, \ 293 I9XX_CURSOR_OFFSETS, \ 294 I9XX_COLORS, \ 295 \ 296 .__runtime_defaults.ip.ver = 4, \ 297 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 298 .__runtime_defaults.cpu_transcoder_mask = \ 299 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 300 301 static const struct intel_display_device_info i965g_display = { 302 GEN4_DISPLAY, 303 .has_overlay = 1, 304 305 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 306 }; 307 308 static const struct intel_display_device_info i965gm_display = { 309 GEN4_DISPLAY, 310 .has_overlay = 1, 311 .supports_tv = 1, 312 313 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 314 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 315 }; 316 317 static const struct intel_display_device_info g45_display = { 318 GEN4_DISPLAY, 319 320 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 321 }; 322 323 static const struct intel_display_device_info gm45_display = { 324 GEN4_DISPLAY, 325 .supports_tv = 1, 326 327 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 328 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 329 }; 330 331 #define ILK_DISPLAY \ 332 .has_hotplug = 1, \ 333 I9XX_PIPE_OFFSETS, \ 334 I9XX_CURSOR_OFFSETS, \ 335 ILK_COLORS, \ 336 \ 337 .__runtime_defaults.ip.ver = 5, \ 338 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 339 .__runtime_defaults.cpu_transcoder_mask = \ 340 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 341 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 342 343 static const struct intel_display_device_info ilk_d_display = { 344 ILK_DISPLAY, 345 }; 346 347 static const struct intel_display_device_info ilk_m_display = { 348 ILK_DISPLAY, 349 350 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 351 }; 352 353 static const struct intel_display_device_info snb_display = { 354 .has_hotplug = 1, 355 I9XX_PIPE_OFFSETS, 356 I9XX_CURSOR_OFFSETS, 357 ILK_COLORS, 358 359 .__runtime_defaults.ip.ver = 6, 360 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 361 .__runtime_defaults.cpu_transcoder_mask = 362 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 363 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 364 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 365 }; 366 367 static const struct intel_display_device_info ivb_display = { 368 .has_hotplug = 1, 369 IVB_PIPE_OFFSETS, 370 IVB_CURSOR_OFFSETS, 371 IVB_COLORS, 372 373 .__runtime_defaults.ip.ver = 7, 374 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 375 .__runtime_defaults.cpu_transcoder_mask = 376 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 377 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 378 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 379 }; 380 381 static const struct intel_display_device_info vlv_display = { 382 .has_gmch = 1, 383 .has_hotplug = 1, 384 .mmio_offset = VLV_DISPLAY_BASE, 385 I9XX_PIPE_OFFSETS, 386 I9XX_CURSOR_OFFSETS, 387 I9XX_COLORS, 388 389 .__runtime_defaults.ip.ver = 7, 390 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 391 .__runtime_defaults.cpu_transcoder_mask = 392 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 393 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ 394 }; 395 396 static const struct intel_display_device_info hsw_display = { 397 .has_ddi = 1, 398 .has_dp_mst = 1, 399 .has_fpga_dbg = 1, 400 .has_hotplug = 1, 401 .has_psr = 1, 402 .has_psr_hw_tracking = 1, 403 HSW_PIPE_OFFSETS, 404 IVB_CURSOR_OFFSETS, 405 IVB_COLORS, 406 407 .__runtime_defaults.ip.ver = 7, 408 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 409 .__runtime_defaults.cpu_transcoder_mask = 410 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 411 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 412 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 413 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 414 }; 415 416 static const struct intel_display_device_info bdw_display = { 417 .has_ddi = 1, 418 .has_dp_mst = 1, 419 .has_fpga_dbg = 1, 420 .has_hotplug = 1, 421 .has_psr = 1, 422 .has_psr_hw_tracking = 1, 423 HSW_PIPE_OFFSETS, 424 IVB_CURSOR_OFFSETS, 425 IVB_COLORS, 426 427 .__runtime_defaults.ip.ver = 8, 428 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 429 .__runtime_defaults.cpu_transcoder_mask = 430 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 431 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 432 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 433 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 434 }; 435 436 static const struct intel_display_device_info chv_display = { 437 .has_hotplug = 1, 438 .has_gmch = 1, 439 .mmio_offset = VLV_DISPLAY_BASE, 440 CHV_PIPE_OFFSETS, 441 CHV_CURSOR_OFFSETS, 442 CHV_COLORS, 443 444 .__runtime_defaults.ip.ver = 8, 445 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 446 .__runtime_defaults.cpu_transcoder_mask = 447 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 448 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ 449 }; 450 451 static const struct intel_display_device_info skl_display = { 452 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ 453 .dbuf.slice_mask = BIT(DBUF_S1), 454 .has_ddi = 1, 455 .has_dp_mst = 1, 456 .has_fpga_dbg = 1, 457 .has_hotplug = 1, 458 .has_ipc = 1, 459 .has_psr = 1, 460 .has_psr_hw_tracking = 1, 461 HSW_PIPE_OFFSETS, 462 IVB_CURSOR_OFFSETS, 463 IVB_COLORS, 464 465 .__runtime_defaults.ip.ver = 9, 466 .__runtime_defaults.has_dmc = 1, 467 .__runtime_defaults.has_hdcp = 1, 468 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 469 .__runtime_defaults.cpu_transcoder_mask = 470 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 471 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 472 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 473 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 474 }; 475 476 #define GEN9_LP_DISPLAY \ 477 .dbuf.slice_mask = BIT(DBUF_S1), \ 478 .has_dp_mst = 1, \ 479 .has_ddi = 1, \ 480 .has_fpga_dbg = 1, \ 481 .has_hotplug = 1, \ 482 .has_ipc = 1, \ 483 .has_psr = 1, \ 484 .has_psr_hw_tracking = 1, \ 485 HSW_PIPE_OFFSETS, \ 486 IVB_CURSOR_OFFSETS, \ 487 IVB_COLORS, \ 488 \ 489 .__runtime_defaults.has_dmc = 1, \ 490 .__runtime_defaults.has_hdcp = 1, \ 491 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 492 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 493 .__runtime_defaults.cpu_transcoder_mask = \ 494 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 495 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 496 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 497 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) 498 499 static const struct intel_display_device_info bxt_display = { 500 GEN9_LP_DISPLAY, 501 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 502 503 .__runtime_defaults.ip.ver = 9, 504 }; 505 506 static const struct intel_display_device_info glk_display = { 507 GEN9_LP_DISPLAY, 508 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 509 GLK_COLORS, 510 511 .__runtime_defaults.ip.ver = 10, 512 }; 513 514 #define ICL_DISPLAY \ 515 .abox_mask = BIT(0), \ 516 .dbuf.size = 2048, \ 517 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 518 .has_ddi = 1, \ 519 .has_dp_mst = 1, \ 520 .has_fpga_dbg = 1, \ 521 .has_hotplug = 1, \ 522 .has_ipc = 1, \ 523 .has_psr = 1, \ 524 .has_psr_hw_tracking = 1, \ 525 .pipe_offsets = { \ 526 [TRANSCODER_A] = PIPE_A_OFFSET, \ 527 [TRANSCODER_B] = PIPE_B_OFFSET, \ 528 [TRANSCODER_C] = PIPE_C_OFFSET, \ 529 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 530 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 531 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 532 }, \ 533 .trans_offsets = { \ 534 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 535 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 536 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 537 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 538 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 539 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 540 }, \ 541 IVB_CURSOR_OFFSETS, \ 542 ICL_COLORS, \ 543 \ 544 .__runtime_defaults.ip.ver = 11, \ 545 .__runtime_defaults.has_dmc = 1, \ 546 .__runtime_defaults.has_dsc = 1, \ 547 .__runtime_defaults.has_hdcp = 1, \ 548 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 549 .__runtime_defaults.cpu_transcoder_mask = \ 550 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 551 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 552 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 553 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 554 555 static const struct intel_display_device_info icl_display = { 556 ICL_DISPLAY, 557 558 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 559 }; 560 561 static const struct intel_display_device_info jsl_ehl_display = { 562 ICL_DISPLAY, 563 564 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), 565 }; 566 567 #define XE_D_DISPLAY \ 568 .abox_mask = GENMASK(2, 1), \ 569 .dbuf.size = 2048, \ 570 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 571 .has_ddi = 1, \ 572 .has_dp_mst = 1, \ 573 .has_dsb = 1, \ 574 .has_fpga_dbg = 1, \ 575 .has_hotplug = 1, \ 576 .has_ipc = 1, \ 577 .has_psr = 1, \ 578 .has_psr_hw_tracking = 1, \ 579 .pipe_offsets = { \ 580 [TRANSCODER_A] = PIPE_A_OFFSET, \ 581 [TRANSCODER_B] = PIPE_B_OFFSET, \ 582 [TRANSCODER_C] = PIPE_C_OFFSET, \ 583 [TRANSCODER_D] = PIPE_D_OFFSET, \ 584 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 585 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 586 }, \ 587 .trans_offsets = { \ 588 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 589 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 590 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 591 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 592 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 593 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 594 }, \ 595 TGL_CURSOR_OFFSETS, \ 596 ICL_COLORS, \ 597 \ 598 .__runtime_defaults.ip.ver = 12, \ 599 .__runtime_defaults.has_dmc = 1, \ 600 .__runtime_defaults.has_dsc = 1, \ 601 .__runtime_defaults.has_hdcp = 1, \ 602 .__runtime_defaults.pipe_mask = \ 603 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 604 .__runtime_defaults.cpu_transcoder_mask = \ 605 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 606 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 607 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 608 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 609 610 static const struct intel_display_device_info tgl_display = { 611 XE_D_DISPLAY, 612 613 /* 614 * FIXME DDI C/combo PHY C missing due to combo PHY 615 * code making a mess on SKUs where the PHY is missing. 616 */ 617 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 618 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), 619 }; 620 621 static const struct intel_display_device_info dg1_display = { 622 XE_D_DISPLAY, 623 624 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 625 BIT(PORT_TC1) | BIT(PORT_TC2), 626 }; 627 628 static const struct intel_display_device_info rkl_display = { 629 XE_D_DISPLAY, 630 .abox_mask = BIT(0), 631 .has_hti = 1, 632 .has_psr_hw_tracking = 0, 633 634 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 635 .__runtime_defaults.cpu_transcoder_mask = 636 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 637 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 638 BIT(PORT_TC1) | BIT(PORT_TC2), 639 }; 640 641 static const struct intel_display_device_info adl_s_display = { 642 XE_D_DISPLAY, 643 .has_hti = 1, 644 .has_psr_hw_tracking = 0, 645 646 .__runtime_defaults.port_mask = BIT(PORT_A) | 647 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 648 }; 649 650 #define XE_LPD_FEATURES \ 651 .abox_mask = GENMASK(1, 0), \ 652 .color = { \ 653 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 654 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 655 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 656 }, \ 657 .dbuf.size = 4096, \ 658 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 659 BIT(DBUF_S4), \ 660 .has_ddi = 1, \ 661 .has_dp_mst = 1, \ 662 .has_dsb = 1, \ 663 .has_fpga_dbg = 1, \ 664 .has_hotplug = 1, \ 665 .has_ipc = 1, \ 666 .has_psr = 1, \ 667 .pipe_offsets = { \ 668 [TRANSCODER_A] = PIPE_A_OFFSET, \ 669 [TRANSCODER_B] = PIPE_B_OFFSET, \ 670 [TRANSCODER_C] = PIPE_C_OFFSET, \ 671 [TRANSCODER_D] = PIPE_D_OFFSET, \ 672 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 673 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 674 }, \ 675 .trans_offsets = { \ 676 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 677 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 678 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 679 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 680 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 681 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 682 }, \ 683 TGL_CURSOR_OFFSETS, \ 684 \ 685 .__runtime_defaults.ip.ver = 13, \ 686 .__runtime_defaults.has_dmc = 1, \ 687 .__runtime_defaults.has_dsc = 1, \ 688 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 689 .__runtime_defaults.has_hdcp = 1, \ 690 .__runtime_defaults.pipe_mask = \ 691 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D) 692 693 static const struct intel_display_device_info xe_lpd_display = { 694 XE_LPD_FEATURES, 695 .has_cdclk_crawl = 1, 696 .has_psr_hw_tracking = 0, 697 698 .__runtime_defaults.cpu_transcoder_mask = 699 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 700 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 701 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 702 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 703 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 704 }; 705 706 static const struct intel_display_device_info xe_hpd_display = { 707 XE_LPD_FEATURES, 708 .has_cdclk_squash = 1, 709 710 .__runtime_defaults.cpu_transcoder_mask = 711 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 712 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 713 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) | 714 BIT(PORT_TC1), 715 }; 716 717 #define XE_LPDP_FEATURES \ 718 .abox_mask = GENMASK(1, 0), \ 719 .color = { \ 720 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 721 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 722 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 723 }, \ 724 .dbuf.size = 4096, \ 725 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 726 BIT(DBUF_S4), \ 727 .has_cdclk_crawl = 1, \ 728 .has_cdclk_squash = 1, \ 729 .has_ddi = 1, \ 730 .has_dp_mst = 1, \ 731 .has_dsb = 1, \ 732 .has_fpga_dbg = 1, \ 733 .has_hotplug = 1, \ 734 .has_ipc = 1, \ 735 .has_psr = 1, \ 736 .pipe_offsets = { \ 737 [TRANSCODER_A] = PIPE_A_OFFSET, \ 738 [TRANSCODER_B] = PIPE_B_OFFSET, \ 739 [TRANSCODER_C] = PIPE_C_OFFSET, \ 740 [TRANSCODER_D] = PIPE_D_OFFSET, \ 741 }, \ 742 .trans_offsets = { \ 743 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 744 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 745 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 746 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 747 }, \ 748 TGL_CURSOR_OFFSETS, \ 749 \ 750 .__runtime_defaults.cpu_transcoder_mask = \ 751 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 752 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ 753 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \ 754 .__runtime_defaults.has_dmc = 1, \ 755 .__runtime_defaults.has_dsc = 1, \ 756 .__runtime_defaults.has_hdcp = 1, \ 757 .__runtime_defaults.pipe_mask = \ 758 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 759 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \ 760 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) 761 762 static const struct intel_display_device_info xe_lpdp_display = { 763 XE_LPDP_FEATURES, 764 }; 765 766 static const struct intel_display_device_info xe2_lpd_display = { 767 XE_LPDP_FEATURES, 768 769 .__runtime_defaults.fbc_mask = 770 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | 771 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), 772 }; 773 774 __diag_pop(); 775 776 /* 777 * Separate detection for no display cases to keep the display id array simple. 778 * 779 * IVB Q requires subvendor and subdevice matching to differentiate from IVB D 780 * GT2 server. 781 */ 782 static bool has_no_display(struct pci_dev *pdev) 783 { 784 static const struct pci_device_id ids[] = { 785 INTEL_IVB_Q_IDS(0), 786 {} 787 }; 788 789 return pci_match_id(ids, pdev); 790 } 791 792 #undef INTEL_VGA_DEVICE 793 #define INTEL_VGA_DEVICE(id, info) { id, info } 794 795 static const struct { 796 u32 devid; 797 const struct intel_display_device_info *info; 798 } intel_display_ids[] = { 799 INTEL_I830_IDS(&i830_display), 800 INTEL_I845G_IDS(&i845_display), 801 INTEL_I85X_IDS(&i85x_display), 802 INTEL_I865G_IDS(&i865g_display), 803 INTEL_I915G_IDS(&i915g_display), 804 INTEL_I915GM_IDS(&i915gm_display), 805 INTEL_I945G_IDS(&i945g_display), 806 INTEL_I945GM_IDS(&i945gm_display), 807 INTEL_I965G_IDS(&i965g_display), 808 INTEL_G33_IDS(&g33_display), 809 INTEL_I965GM_IDS(&i965gm_display), 810 INTEL_GM45_IDS(&gm45_display), 811 INTEL_G45_IDS(&g45_display), 812 INTEL_PINEVIEW_G_IDS(&pnv_display), 813 INTEL_PINEVIEW_M_IDS(&pnv_display), 814 INTEL_IRONLAKE_D_IDS(&ilk_d_display), 815 INTEL_IRONLAKE_M_IDS(&ilk_m_display), 816 INTEL_SNB_D_IDS(&snb_display), 817 INTEL_SNB_M_IDS(&snb_display), 818 INTEL_IVB_M_IDS(&ivb_display), 819 INTEL_IVB_D_IDS(&ivb_display), 820 INTEL_HSW_IDS(&hsw_display), 821 INTEL_VLV_IDS(&vlv_display), 822 INTEL_BDW_IDS(&bdw_display), 823 INTEL_CHV_IDS(&chv_display), 824 INTEL_SKL_IDS(&skl_display), 825 INTEL_BXT_IDS(&bxt_display), 826 INTEL_GLK_IDS(&glk_display), 827 INTEL_KBL_IDS(&skl_display), 828 INTEL_CFL_IDS(&skl_display), 829 INTEL_ICL_11_IDS(&icl_display), 830 INTEL_EHL_IDS(&jsl_ehl_display), 831 INTEL_JSL_IDS(&jsl_ehl_display), 832 INTEL_TGL_12_IDS(&tgl_display), 833 INTEL_DG1_IDS(&dg1_display), 834 INTEL_RKL_IDS(&rkl_display), 835 INTEL_ADLS_IDS(&adl_s_display), 836 INTEL_RPLS_IDS(&adl_s_display), 837 INTEL_ADLP_IDS(&xe_lpd_display), 838 INTEL_ADLN_IDS(&xe_lpd_display), 839 INTEL_RPLP_IDS(&xe_lpd_display), 840 INTEL_DG2_IDS(&xe_hpd_display), 841 842 /* 843 * Do not add any GMD_ID-based platforms to this list. They will 844 * be probed automatically based on the IP version reported by 845 * the hardware. 846 */ 847 }; 848 849 static const struct { 850 u16 ver; 851 u16 rel; 852 const struct intel_display_device_info *display; 853 } gmdid_display_map[] = { 854 { 14, 0, &xe_lpdp_display }, 855 { 20, 0, &xe2_lpd_display }, 856 }; 857 858 static const struct intel_display_device_info * 859 probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step) 860 { 861 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 862 void __iomem *addr; 863 u32 val; 864 int i; 865 866 /* The caller expects to ver, rel and step to be initialized 867 * here, and there's no good way to check when there was a 868 * failure and no_display was returned. So initialize all these 869 * values here zero, to be sure. 870 */ 871 *ver = 0; 872 *rel = 0; 873 *step = 0; 874 875 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 876 if (!addr) { 877 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); 878 return &no_display; 879 } 880 881 val = ioread32(addr); 882 pci_iounmap(pdev, addr); 883 884 if (val == 0) { 885 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 886 return &no_display; 887 } 888 889 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 890 *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 891 *step = REG_FIELD_GET(GMD_ID_STEP, val); 892 893 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) 894 if (*ver == gmdid_display_map[i].ver && 895 *rel == gmdid_display_map[i].rel) 896 return gmdid_display_map[i].display; 897 898 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", 899 *ver, *rel); 900 return &no_display; 901 } 902 903 static const struct intel_display_device_info * 904 probe_display(struct drm_i915_private *i915) 905 { 906 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 907 int i; 908 909 if (has_no_display(pdev)) { 910 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 911 return &no_display; 912 } 913 914 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { 915 if (intel_display_ids[i].devid == pdev->device) 916 return intel_display_ids[i].info; 917 } 918 919 drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", 920 pdev->device); 921 922 return &no_display; 923 } 924 925 void intel_display_device_probe(struct drm_i915_private *i915) 926 { 927 const struct intel_display_device_info *info; 928 u16 ver, rel, step; 929 930 /* Add drm device backpointer as early as possible. */ 931 i915->display.drm = &i915->drm; 932 933 if (HAS_GMD_ID(i915)) 934 info = probe_gmdid_display(i915, &ver, &rel, &step); 935 else 936 info = probe_display(i915); 937 938 DISPLAY_INFO(i915) = info; 939 940 memcpy(DISPLAY_RUNTIME_INFO(i915), 941 &DISPLAY_INFO(i915)->__runtime_defaults, 942 sizeof(*DISPLAY_RUNTIME_INFO(i915))); 943 944 if (HAS_GMD_ID(i915)) { 945 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver; 946 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; 947 DISPLAY_RUNTIME_INFO(i915)->ip.step = step; 948 } 949 950 intel_display_params_copy(&i915->display.params); 951 } 952 953 void intel_display_device_remove(struct drm_i915_private *i915) 954 { 955 intel_display_params_free(&i915->display.params); 956 } 957 958 static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915) 959 { 960 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); 961 enum pipe pipe; 962 963 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); 964 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); 965 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); 966 967 /* This covers both ULT and ULX */ 968 if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915)) 969 display_runtime->port_mask &= ~BIT(PORT_D); 970 971 if (IS_ICL_WITH_PORT_F(i915)) 972 display_runtime->port_mask |= BIT(PORT_F); 973 974 /* Wa_14011765242: adl-s A0,A1 */ 975 if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) 976 for_each_pipe(i915, pipe) 977 display_runtime->num_scalers[pipe] = 0; 978 else if (DISPLAY_VER(i915) >= 11) { 979 for_each_pipe(i915, pipe) 980 display_runtime->num_scalers[pipe] = 2; 981 } else if (DISPLAY_VER(i915) >= 9) { 982 display_runtime->num_scalers[PIPE_A] = 2; 983 display_runtime->num_scalers[PIPE_B] = 2; 984 display_runtime->num_scalers[PIPE_C] = 1; 985 } 986 987 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 988 for_each_pipe(i915, pipe) 989 display_runtime->num_sprites[pipe] = 4; 990 else if (DISPLAY_VER(i915) >= 11) 991 for_each_pipe(i915, pipe) 992 display_runtime->num_sprites[pipe] = 6; 993 else if (DISPLAY_VER(i915) == 10) 994 for_each_pipe(i915, pipe) 995 display_runtime->num_sprites[pipe] = 3; 996 else if (IS_BROXTON(i915)) { 997 /* 998 * Skylake and Broxton currently don't expose the topmost plane as its 999 * use is exclusive with the legacy cursor and we only want to expose 1000 * one of those, not both. Until we can safely expose the topmost plane 1001 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 1002 * we don't expose the topmost plane at all to prevent ABI breakage 1003 * down the line. 1004 */ 1005 1006 display_runtime->num_sprites[PIPE_A] = 2; 1007 display_runtime->num_sprites[PIPE_B] = 2; 1008 display_runtime->num_sprites[PIPE_C] = 1; 1009 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1010 for_each_pipe(i915, pipe) 1011 display_runtime->num_sprites[pipe] = 2; 1012 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { 1013 for_each_pipe(i915, pipe) 1014 display_runtime->num_sprites[pipe] = 1; 1015 } 1016 1017 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && 1018 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { 1019 drm_info(&i915->drm, "Display not present, disabling\n"); 1020 goto display_fused_off; 1021 } 1022 1023 if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { 1024 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); 1025 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); 1026 1027 /* 1028 * SFUSE_STRAP is supposed to have a bit signalling the display 1029 * is fused off. Unfortunately it seems that, at least in 1030 * certain cases, fused off display means that PCH display 1031 * reads don't land anywhere. In that case, we read 0s. 1032 * 1033 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 1034 * should be set when taking over after the firmware. 1035 */ 1036 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 1037 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 1038 (HAS_PCH_CPT(i915) && 1039 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 1040 drm_info(&i915->drm, 1041 "Display fused off, disabling\n"); 1042 goto display_fused_off; 1043 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 1044 drm_info(&i915->drm, "PipeC fused off\n"); 1045 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1046 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1047 } 1048 } else if (DISPLAY_VER(i915) >= 9) { 1049 u32 dfsm = intel_de_read(i915, SKL_DFSM); 1050 1051 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 1052 display_runtime->pipe_mask &= ~BIT(PIPE_A); 1053 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 1054 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 1055 } 1056 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 1057 display_runtime->pipe_mask &= ~BIT(PIPE_B); 1058 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 1059 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); 1060 } 1061 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 1062 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1063 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1064 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); 1065 } 1066 1067 if (DISPLAY_VER(i915) >= 12 && 1068 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1069 display_runtime->pipe_mask &= ~BIT(PIPE_D); 1070 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 1071 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); 1072 } 1073 1074 if (!display_runtime->pipe_mask) 1075 goto display_fused_off; 1076 1077 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1078 display_runtime->has_hdcp = 0; 1079 1080 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1081 display_runtime->fbc_mask = 0; 1082 1083 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1084 display_runtime->has_dmc = 0; 1085 1086 if (IS_DISPLAY_VER(i915, 10, 12) && 1087 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 1088 display_runtime->has_dsc = 0; 1089 } 1090 1091 if (DISPLAY_VER(i915) >= 20) { 1092 u32 cap = intel_de_read(i915, XE2LPD_DE_CAP); 1093 1094 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == 1095 XE2LPD_DE_CAP_DSC_REMOVED) 1096 display_runtime->has_dsc = 0; 1097 1098 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) == 1099 XE2LPD_DE_CAP_SCALER_SINGLE) { 1100 for_each_pipe(i915, pipe) 1101 if (display_runtime->num_scalers[pipe]) 1102 display_runtime->num_scalers[pipe] = 1; 1103 } 1104 } 1105 1106 return; 1107 1108 display_fused_off: 1109 memset(display_runtime, 0, sizeof(*display_runtime)); 1110 } 1111 1112 void intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1113 { 1114 if (HAS_DISPLAY(i915)) 1115 __intel_display_device_info_runtime_init(i915); 1116 1117 /* Display may have been disabled by runtime init */ 1118 if (!HAS_DISPLAY(i915)) { 1119 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 1120 i915->display.info.__device_info = &no_display; 1121 } 1122 1123 /* Disable nuclear pageflip by default on pre-g4x */ 1124 if (!i915->display.params.nuclear_pageflip && 1125 DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) 1126 i915->drm.driver_features &= ~DRIVER_ATOMIC; 1127 } 1128 1129 void intel_display_device_info_print(const struct intel_display_device_info *info, 1130 const struct intel_display_runtime_info *runtime, 1131 struct drm_printer *p) 1132 { 1133 if (runtime->ip.rel) 1134 drm_printf(p, "display version: %u.%02u\n", 1135 runtime->ip.ver, 1136 runtime->ip.rel); 1137 else 1138 drm_printf(p, "display version: %u\n", 1139 runtime->ip.ver); 1140 1141 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 1142 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 1143 #undef PRINT_FLAG 1144 1145 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); 1146 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); 1147 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); 1148 } 1149 1150 /* 1151 * Assuming the device has display hardware, should it be enabled? 1152 * 1153 * It's an error to call this function if the device does not have display 1154 * hardware. 1155 * 1156 * Disabling display means taking over the display hardware, putting it to 1157 * sleep, and preventing connectors from being connected via any means. 1158 */ 1159 bool intel_display_device_enabled(struct drm_i915_private *i915) 1160 { 1161 /* Only valid when HAS_DISPLAY() is true */ 1162 drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915)); 1163 1164 return !i915->display.params.disable_display && 1165 !intel_opregion_headless_sku(i915); 1166 } 1167