1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/intel/pciids.h> 7 #include <drm/drm_color_mgmt.h> 8 #include <linux/pci.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_cx0_phy_regs.h" 13 #include "intel_de.h" 14 #include "intel_display.h" 15 #include "intel_display_device.h" 16 #include "intel_display_params.h" 17 #include "intel_display_power.h" 18 #include "intel_display_reg_defs.h" 19 #include "intel_fbc.h" 20 #include "intel_step.h" 21 22 __diag_push(); 23 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); 24 25 struct stepping_desc { 26 const enum intel_step *map; /* revid to step map */ 27 size_t size; /* map size */ 28 }; 29 30 #define STEP_INFO(_map) \ 31 .step_info.map = _map, \ 32 .step_info.size = ARRAY_SIZE(_map) 33 34 struct subplatform_desc { 35 struct intel_display_platforms platforms; 36 const char *name; 37 const u16 *pciidlist; 38 struct stepping_desc step_info; 39 }; 40 41 #define SUBPLATFORM(_platform, _subplatform) \ 42 .platforms._platform##_##_subplatform = 1, \ 43 .name = #_subplatform 44 45 /* 46 * Group subplatform alias that matches multiple subplatforms. For making ult 47 * cover both ult and ulx on HSW/BDW. 48 */ 49 #define SUBPLATFORM_GROUP(_platform, _subplatform) \ 50 .platforms._platform##_##_subplatform = 1 51 52 struct platform_desc { 53 struct intel_display_platforms platforms; 54 const char *name; 55 const struct subplatform_desc *subplatforms; 56 const struct intel_display_device_info *info; /* NULL for GMD ID */ 57 struct stepping_desc step_info; 58 }; 59 60 #define PLATFORM(_platform) \ 61 .platforms._platform = 1, \ 62 .name = #_platform 63 64 /* 65 * Group platform alias that matches multiple platforms. For aliases such as g4x 66 * that covers both g45 and gm45. 67 */ 68 #define PLATFORM_GROUP(_platform) \ 69 .platforms._platform = 1 70 71 #define ID(id) (id) 72 73 static const struct intel_display_device_info no_display = {}; 74 75 #define PIPE_A_OFFSET 0x70000 76 #define PIPE_B_OFFSET 0x71000 77 #define PIPE_C_OFFSET 0x72000 78 #define PIPE_D_OFFSET 0x73000 79 #define CHV_PIPE_C_OFFSET 0x74000 80 /* 81 * There's actually no pipe EDP. Some pipe registers have 82 * simply shifted from the pipe to the transcoder, while 83 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 84 * to access such registers in transcoder EDP. 85 */ 86 #define PIPE_EDP_OFFSET 0x7f000 87 88 /* ICL DSI 0 and 1 */ 89 #define PIPE_DSI0_OFFSET 0x7b000 90 #define PIPE_DSI1_OFFSET 0x7b800 91 92 #define TRANSCODER_A_OFFSET 0x60000 93 #define TRANSCODER_B_OFFSET 0x61000 94 #define TRANSCODER_C_OFFSET 0x62000 95 #define CHV_TRANSCODER_C_OFFSET 0x63000 96 #define TRANSCODER_D_OFFSET 0x63000 97 #define TRANSCODER_EDP_OFFSET 0x6f000 98 #define TRANSCODER_DSI0_OFFSET 0x6b000 99 #define TRANSCODER_DSI1_OFFSET 0x6b800 100 101 #define CURSOR_A_OFFSET 0x70080 102 #define CURSOR_B_OFFSET 0x700c0 103 #define CHV_CURSOR_C_OFFSET 0x700e0 104 #define IVB_CURSOR_B_OFFSET 0x71080 105 #define IVB_CURSOR_C_OFFSET 0x72080 106 #define TGL_CURSOR_D_OFFSET 0x73080 107 108 #define I845_PIPE_OFFSETS \ 109 .pipe_offsets = { \ 110 [TRANSCODER_A] = PIPE_A_OFFSET, \ 111 }, \ 112 .trans_offsets = { \ 113 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 114 } 115 116 #define I9XX_PIPE_OFFSETS \ 117 .pipe_offsets = { \ 118 [TRANSCODER_A] = PIPE_A_OFFSET, \ 119 [TRANSCODER_B] = PIPE_B_OFFSET, \ 120 }, \ 121 .trans_offsets = { \ 122 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 123 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 124 } 125 126 #define IVB_PIPE_OFFSETS \ 127 .pipe_offsets = { \ 128 [TRANSCODER_A] = PIPE_A_OFFSET, \ 129 [TRANSCODER_B] = PIPE_B_OFFSET, \ 130 [TRANSCODER_C] = PIPE_C_OFFSET, \ 131 }, \ 132 .trans_offsets = { \ 133 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 134 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 135 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 136 } 137 138 #define HSW_PIPE_OFFSETS \ 139 .pipe_offsets = { \ 140 [TRANSCODER_A] = PIPE_A_OFFSET, \ 141 [TRANSCODER_B] = PIPE_B_OFFSET, \ 142 [TRANSCODER_C] = PIPE_C_OFFSET, \ 143 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 144 }, \ 145 .trans_offsets = { \ 146 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 147 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 148 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 149 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 150 } 151 152 #define CHV_PIPE_OFFSETS \ 153 .pipe_offsets = { \ 154 [TRANSCODER_A] = PIPE_A_OFFSET, \ 155 [TRANSCODER_B] = PIPE_B_OFFSET, \ 156 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 157 }, \ 158 .trans_offsets = { \ 159 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 160 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 161 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 162 } 163 164 #define I845_CURSOR_OFFSETS \ 165 .cursor_offsets = { \ 166 [PIPE_A] = CURSOR_A_OFFSET, \ 167 } 168 169 #define I9XX_CURSOR_OFFSETS \ 170 .cursor_offsets = { \ 171 [PIPE_A] = CURSOR_A_OFFSET, \ 172 [PIPE_B] = CURSOR_B_OFFSET, \ 173 } 174 175 #define CHV_CURSOR_OFFSETS \ 176 .cursor_offsets = { \ 177 [PIPE_A] = CURSOR_A_OFFSET, \ 178 [PIPE_B] = CURSOR_B_OFFSET, \ 179 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 180 } 181 182 #define IVB_CURSOR_OFFSETS \ 183 .cursor_offsets = { \ 184 [PIPE_A] = CURSOR_A_OFFSET, \ 185 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 186 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 187 } 188 189 #define TGL_CURSOR_OFFSETS \ 190 .cursor_offsets = { \ 191 [PIPE_A] = CURSOR_A_OFFSET, \ 192 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 193 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 194 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 195 } 196 197 #define I845_COLORS \ 198 .color = { .gamma_lut_size = 256 } 199 #define I9XX_COLORS \ 200 .color = { .gamma_lut_size = 129, \ 201 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 202 } 203 #define ILK_COLORS \ 204 .color = { .gamma_lut_size = 1024 } 205 #define IVB_COLORS \ 206 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 207 #define CHV_COLORS \ 208 .color = { \ 209 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 210 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 211 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 212 } 213 #define GLK_COLORS \ 214 .color = { \ 215 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 216 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 217 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 218 } 219 #define ICL_COLORS \ 220 .color = { \ 221 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 222 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 223 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 224 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 225 } 226 227 #define I830_DISPLAY \ 228 .has_overlay = 1, \ 229 .cursor_needs_physical = 1, \ 230 .overlay_needs_physical = 1, \ 231 .has_gmch = 1, \ 232 I9XX_PIPE_OFFSETS, \ 233 I9XX_CURSOR_OFFSETS, \ 234 I9XX_COLORS, \ 235 \ 236 .__runtime_defaults.ip.ver = 2, \ 237 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 238 .__runtime_defaults.cpu_transcoder_mask = \ 239 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 240 241 #define I845_DISPLAY \ 242 .has_overlay = 1, \ 243 .overlay_needs_physical = 1, \ 244 .has_gmch = 1, \ 245 I845_PIPE_OFFSETS, \ 246 I845_CURSOR_OFFSETS, \ 247 I845_COLORS, \ 248 \ 249 .__runtime_defaults.ip.ver = 2, \ 250 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ 251 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) 252 253 static const struct platform_desc i830_desc = { 254 PLATFORM(i830), 255 .info = &(const struct intel_display_device_info) { 256 I830_DISPLAY, 257 258 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ 259 }, 260 }; 261 262 static const struct platform_desc i845_desc = { 263 PLATFORM(i845g), 264 .info = &(const struct intel_display_device_info) { 265 I845_DISPLAY, 266 267 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 268 }, 269 }; 270 271 static const struct platform_desc i85x_desc = { 272 PLATFORM(i85x), 273 .info = &(const struct intel_display_device_info) { 274 I830_DISPLAY, 275 276 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 277 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 278 }, 279 }; 280 281 static const struct platform_desc i865g_desc = { 282 PLATFORM(i865g), 283 .info = &(const struct intel_display_device_info) { 284 I845_DISPLAY, 285 286 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 287 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 288 }, 289 }; 290 291 #define GEN3_DISPLAY \ 292 .has_gmch = 1, \ 293 .has_overlay = 1, \ 294 I9XX_PIPE_OFFSETS, \ 295 I9XX_CURSOR_OFFSETS, \ 296 \ 297 .__runtime_defaults.ip.ver = 3, \ 298 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 299 .__runtime_defaults.cpu_transcoder_mask = \ 300 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 301 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ 302 303 static const struct platform_desc i915g_desc = { 304 PLATFORM(i915g), 305 .info = &(const struct intel_display_device_info) { 306 GEN3_DISPLAY, 307 I845_COLORS, 308 .cursor_needs_physical = 1, 309 .overlay_needs_physical = 1, 310 }, 311 }; 312 313 static const struct platform_desc i915gm_desc = { 314 PLATFORM(i915gm), 315 .info = &(const struct intel_display_device_info) { 316 GEN3_DISPLAY, 317 I9XX_COLORS, 318 .cursor_needs_physical = 1, 319 .overlay_needs_physical = 1, 320 .supports_tv = 1, 321 322 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 323 }, 324 }; 325 326 static const struct platform_desc i945g_desc = { 327 PLATFORM(i945g), 328 .info = &(const struct intel_display_device_info) { 329 GEN3_DISPLAY, 330 I845_COLORS, 331 .has_hotplug = 1, 332 .cursor_needs_physical = 1, 333 .overlay_needs_physical = 1, 334 }, 335 }; 336 337 static const struct platform_desc i945gm_desc = { 338 PLATFORM(i915gm), 339 .info = &(const struct intel_display_device_info) { 340 GEN3_DISPLAY, 341 I9XX_COLORS, 342 .has_hotplug = 1, 343 .cursor_needs_physical = 1, 344 .overlay_needs_physical = 1, 345 .supports_tv = 1, 346 347 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 348 }, 349 }; 350 351 static const struct platform_desc g33_desc = { 352 PLATFORM(g33), 353 .info = &(const struct intel_display_device_info) { 354 GEN3_DISPLAY, 355 I845_COLORS, 356 .has_hotplug = 1, 357 }, 358 }; 359 360 static const struct platform_desc pnv_desc = { 361 PLATFORM(pineview), 362 .info = &(const struct intel_display_device_info) { 363 GEN3_DISPLAY, 364 I9XX_COLORS, 365 .has_hotplug = 1, 366 }, 367 }; 368 369 #define GEN4_DISPLAY \ 370 .has_hotplug = 1, \ 371 .has_gmch = 1, \ 372 I9XX_PIPE_OFFSETS, \ 373 I9XX_CURSOR_OFFSETS, \ 374 I9XX_COLORS, \ 375 \ 376 .__runtime_defaults.ip.ver = 4, \ 377 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 378 .__runtime_defaults.cpu_transcoder_mask = \ 379 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 380 381 static const struct platform_desc i965g_desc = { 382 PLATFORM(i965g), 383 .info = &(const struct intel_display_device_info) { 384 GEN4_DISPLAY, 385 .has_overlay = 1, 386 387 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 388 }, 389 }; 390 391 static const struct platform_desc i965gm_desc = { 392 PLATFORM(i965gm), 393 .info = &(const struct intel_display_device_info) { 394 GEN4_DISPLAY, 395 .has_overlay = 1, 396 .supports_tv = 1, 397 398 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 399 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 400 }, 401 }; 402 403 static const struct platform_desc g45_desc = { 404 PLATFORM(g45), 405 PLATFORM_GROUP(g4x), 406 .info = &(const struct intel_display_device_info) { 407 GEN4_DISPLAY, 408 409 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 410 }, 411 }; 412 413 static const struct platform_desc gm45_desc = { 414 PLATFORM(gm45), 415 PLATFORM_GROUP(g4x), 416 .info = &(const struct intel_display_device_info) { 417 GEN4_DISPLAY, 418 .supports_tv = 1, 419 420 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 421 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 422 }, 423 }; 424 425 #define ILK_DISPLAY \ 426 .has_hotplug = 1, \ 427 I9XX_PIPE_OFFSETS, \ 428 I9XX_CURSOR_OFFSETS, \ 429 ILK_COLORS, \ 430 \ 431 .__runtime_defaults.ip.ver = 5, \ 432 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 433 .__runtime_defaults.cpu_transcoder_mask = \ 434 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 435 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 436 437 static const struct platform_desc ilk_d_desc = { 438 PLATFORM(ironlake), 439 .info = &(const struct intel_display_device_info) { 440 ILK_DISPLAY, 441 }, 442 }; 443 444 static const struct platform_desc ilk_m_desc = { 445 PLATFORM(ironlake), 446 .info = &(const struct intel_display_device_info) { 447 ILK_DISPLAY, 448 449 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 450 }, 451 }; 452 453 static const struct platform_desc snb_desc = { 454 PLATFORM(sandybridge), 455 .info = &(const struct intel_display_device_info) { 456 .has_hotplug = 1, 457 I9XX_PIPE_OFFSETS, 458 I9XX_CURSOR_OFFSETS, 459 ILK_COLORS, 460 461 .__runtime_defaults.ip.ver = 6, 462 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 463 .__runtime_defaults.cpu_transcoder_mask = 464 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 465 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 466 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 467 }, 468 }; 469 470 static const struct platform_desc ivb_desc = { 471 PLATFORM(ivybridge), 472 .info = &(const struct intel_display_device_info) { 473 .has_hotplug = 1, 474 IVB_PIPE_OFFSETS, 475 IVB_CURSOR_OFFSETS, 476 IVB_COLORS, 477 478 .__runtime_defaults.ip.ver = 7, 479 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 480 .__runtime_defaults.cpu_transcoder_mask = 481 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 482 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 483 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 484 }, 485 }; 486 487 static const struct platform_desc vlv_desc = { 488 PLATFORM(valleyview), 489 .info = &(const struct intel_display_device_info) { 490 .has_gmch = 1, 491 .has_hotplug = 1, 492 .mmio_offset = VLV_DISPLAY_BASE, 493 I9XX_PIPE_OFFSETS, 494 I9XX_CURSOR_OFFSETS, 495 I9XX_COLORS, 496 497 .__runtime_defaults.ip.ver = 7, 498 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 499 .__runtime_defaults.cpu_transcoder_mask = 500 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 501 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ 502 }, 503 }; 504 505 static const u16 hsw_ult_ids[] = { 506 INTEL_HSW_ULT_GT1_IDS(ID), 507 INTEL_HSW_ULT_GT2_IDS(ID), 508 INTEL_HSW_ULT_GT3_IDS(ID), 509 0 510 }; 511 512 static const u16 hsw_ulx_ids[] = { 513 INTEL_HSW_ULX_GT1_IDS(ID), 514 INTEL_HSW_ULX_GT2_IDS(ID), 515 0 516 }; 517 518 static const struct platform_desc hsw_desc = { 519 PLATFORM(haswell), 520 .subplatforms = (const struct subplatform_desc[]) { 521 /* Special case: Use ult both as group and subplatform. */ 522 { 523 SUBPLATFORM(haswell, ult), 524 SUBPLATFORM_GROUP(haswell, ult), 525 .pciidlist = hsw_ult_ids, 526 }, 527 { 528 SUBPLATFORM(haswell, ulx), 529 SUBPLATFORM_GROUP(haswell, ult), 530 .pciidlist = hsw_ulx_ids, 531 }, 532 {}, 533 }, 534 .info = &(const struct intel_display_device_info) { 535 .has_ddi = 1, 536 .has_dp_mst = 1, 537 .has_fpga_dbg = 1, 538 .has_hotplug = 1, 539 .has_psr = 1, 540 .has_psr_hw_tracking = 1, 541 HSW_PIPE_OFFSETS, 542 IVB_CURSOR_OFFSETS, 543 IVB_COLORS, 544 545 .__runtime_defaults.ip.ver = 7, 546 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 547 .__runtime_defaults.cpu_transcoder_mask = 548 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 549 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 550 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 551 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 552 }, 553 }; 554 555 static const u16 bdw_ult_ids[] = { 556 INTEL_BDW_ULT_GT1_IDS(ID), 557 INTEL_BDW_ULT_GT2_IDS(ID), 558 INTEL_BDW_ULT_GT3_IDS(ID), 559 INTEL_BDW_ULT_RSVD_IDS(ID), 560 0 561 }; 562 563 static const u16 bdw_ulx_ids[] = { 564 INTEL_BDW_ULX_GT1_IDS(ID), 565 INTEL_BDW_ULX_GT2_IDS(ID), 566 INTEL_BDW_ULX_GT3_IDS(ID), 567 INTEL_BDW_ULX_RSVD_IDS(ID), 568 0 569 }; 570 571 static const struct platform_desc bdw_desc = { 572 PLATFORM(broadwell), 573 .subplatforms = (const struct subplatform_desc[]) { 574 /* Special case: Use ult both as group and subplatform. */ 575 { 576 SUBPLATFORM(broadwell, ult), 577 SUBPLATFORM_GROUP(broadwell, ult), 578 .pciidlist = bdw_ult_ids, 579 }, 580 { 581 SUBPLATFORM(broadwell, ulx), 582 SUBPLATFORM_GROUP(broadwell, ult), 583 .pciidlist = bdw_ulx_ids, 584 }, 585 {}, 586 }, 587 .info = &(const struct intel_display_device_info) { 588 .has_ddi = 1, 589 .has_dp_mst = 1, 590 .has_fpga_dbg = 1, 591 .has_hotplug = 1, 592 .has_psr = 1, 593 .has_psr_hw_tracking = 1, 594 HSW_PIPE_OFFSETS, 595 IVB_CURSOR_OFFSETS, 596 IVB_COLORS, 597 598 .__runtime_defaults.ip.ver = 8, 599 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 600 .__runtime_defaults.cpu_transcoder_mask = 601 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 602 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 603 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 604 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 605 }, 606 }; 607 608 static const struct platform_desc chv_desc = { 609 PLATFORM(cherryview), 610 .info = &(const struct intel_display_device_info) { 611 .has_hotplug = 1, 612 .has_gmch = 1, 613 .mmio_offset = VLV_DISPLAY_BASE, 614 CHV_PIPE_OFFSETS, 615 CHV_CURSOR_OFFSETS, 616 CHV_COLORS, 617 618 .__runtime_defaults.ip.ver = 8, 619 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 620 .__runtime_defaults.cpu_transcoder_mask = 621 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 622 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ 623 }, 624 }; 625 626 static const struct intel_display_device_info skl_display = { 627 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ 628 .dbuf.slice_mask = BIT(DBUF_S1), 629 .has_ddi = 1, 630 .has_dp_mst = 1, 631 .has_fpga_dbg = 1, 632 .has_hotplug = 1, 633 .has_ipc = 1, 634 .has_psr = 1, 635 .has_psr_hw_tracking = 1, 636 HSW_PIPE_OFFSETS, 637 IVB_CURSOR_OFFSETS, 638 IVB_COLORS, 639 640 .__runtime_defaults.ip.ver = 9, 641 .__runtime_defaults.has_dmc = 1, 642 .__runtime_defaults.has_hdcp = 1, 643 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 644 .__runtime_defaults.cpu_transcoder_mask = 645 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 646 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 647 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 648 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 649 }; 650 651 static const u16 skl_ult_ids[] = { 652 INTEL_SKL_ULT_GT1_IDS(ID), 653 INTEL_SKL_ULT_GT2_IDS(ID), 654 INTEL_SKL_ULT_GT3_IDS(ID), 655 0 656 }; 657 658 static const u16 skl_ulx_ids[] = { 659 INTEL_SKL_ULX_GT1_IDS(ID), 660 INTEL_SKL_ULX_GT2_IDS(ID), 661 0 662 }; 663 664 static const enum intel_step skl_steppings[] = { 665 [0x6] = STEP_G0, 666 [0x7] = STEP_H0, 667 [0x9] = STEP_J0, 668 [0xA] = STEP_I1, 669 }; 670 671 static const struct platform_desc skl_desc = { 672 PLATFORM(skylake), 673 .subplatforms = (const struct subplatform_desc[]) { 674 { 675 SUBPLATFORM(skylake, ult), 676 .pciidlist = skl_ult_ids, 677 }, 678 { 679 SUBPLATFORM(skylake, ulx), 680 .pciidlist = skl_ulx_ids, 681 }, 682 {}, 683 }, 684 .info = &skl_display, 685 STEP_INFO(skl_steppings), 686 }; 687 688 static const u16 kbl_ult_ids[] = { 689 INTEL_KBL_ULT_GT1_IDS(ID), 690 INTEL_KBL_ULT_GT2_IDS(ID), 691 INTEL_KBL_ULT_GT3_IDS(ID), 692 0 693 }; 694 695 static const u16 kbl_ulx_ids[] = { 696 INTEL_KBL_ULX_GT1_IDS(ID), 697 INTEL_KBL_ULX_GT2_IDS(ID), 698 INTEL_AML_KBL_GT2_IDS(ID), 699 0 700 }; 701 702 static const enum intel_step kbl_steppings[] = { 703 [1] = STEP_B0, 704 [2] = STEP_B0, 705 [3] = STEP_B0, 706 [4] = STEP_C0, 707 [5] = STEP_B1, 708 [6] = STEP_B1, 709 [7] = STEP_C0, 710 }; 711 712 static const struct platform_desc kbl_desc = { 713 PLATFORM(kabylake), 714 .subplatforms = (const struct subplatform_desc[]) { 715 { 716 SUBPLATFORM(kabylake, ult), 717 .pciidlist = kbl_ult_ids, 718 }, 719 { 720 SUBPLATFORM(kabylake, ulx), 721 .pciidlist = kbl_ulx_ids, 722 }, 723 {}, 724 }, 725 .info = &skl_display, 726 STEP_INFO(kbl_steppings), 727 }; 728 729 static const u16 cfl_ult_ids[] = { 730 INTEL_CFL_U_GT2_IDS(ID), 731 INTEL_CFL_U_GT3_IDS(ID), 732 INTEL_WHL_U_GT1_IDS(ID), 733 INTEL_WHL_U_GT2_IDS(ID), 734 INTEL_WHL_U_GT3_IDS(ID), 735 0 736 }; 737 738 static const u16 cfl_ulx_ids[] = { 739 INTEL_AML_CFL_GT2_IDS(ID), 740 0 741 }; 742 743 static const struct platform_desc cfl_desc = { 744 PLATFORM(coffeelake), 745 .subplatforms = (const struct subplatform_desc[]) { 746 { 747 SUBPLATFORM(coffeelake, ult), 748 .pciidlist = cfl_ult_ids, 749 }, 750 { 751 SUBPLATFORM(coffeelake, ulx), 752 .pciidlist = cfl_ulx_ids, 753 }, 754 {}, 755 }, 756 .info = &skl_display, 757 }; 758 759 static const u16 cml_ult_ids[] = { 760 INTEL_CML_U_GT1_IDS(ID), 761 INTEL_CML_U_GT2_IDS(ID), 762 0 763 }; 764 765 static const struct platform_desc cml_desc = { 766 PLATFORM(cometlake), 767 .subplatforms = (const struct subplatform_desc[]) { 768 { 769 SUBPLATFORM(cometlake, ult), 770 .pciidlist = cml_ult_ids, 771 }, 772 {}, 773 }, 774 .info = &skl_display, 775 }; 776 777 #define GEN9_LP_DISPLAY \ 778 .dbuf.slice_mask = BIT(DBUF_S1), \ 779 .has_dp_mst = 1, \ 780 .has_ddi = 1, \ 781 .has_fpga_dbg = 1, \ 782 .has_hotplug = 1, \ 783 .has_ipc = 1, \ 784 .has_psr = 1, \ 785 .has_psr_hw_tracking = 1, \ 786 HSW_PIPE_OFFSETS, \ 787 IVB_CURSOR_OFFSETS, \ 788 IVB_COLORS, \ 789 \ 790 .__runtime_defaults.has_dmc = 1, \ 791 .__runtime_defaults.has_hdcp = 1, \ 792 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 793 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 794 .__runtime_defaults.cpu_transcoder_mask = \ 795 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 796 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 797 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 798 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) 799 800 static const enum intel_step bxt_steppings[] = { 801 [0xA] = STEP_C0, 802 [0xB] = STEP_C0, 803 [0xC] = STEP_D0, 804 [0xD] = STEP_E0, 805 }; 806 807 static const struct platform_desc bxt_desc = { 808 PLATFORM(broxton), 809 .info = &(const struct intel_display_device_info) { 810 GEN9_LP_DISPLAY, 811 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 812 813 .__runtime_defaults.ip.ver = 9, 814 }, 815 STEP_INFO(bxt_steppings), 816 }; 817 818 static const enum intel_step glk_steppings[] = { 819 [3] = STEP_B0, 820 }; 821 822 static const struct platform_desc glk_desc = { 823 PLATFORM(geminilake), 824 .info = &(const struct intel_display_device_info) { 825 GEN9_LP_DISPLAY, 826 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 827 GLK_COLORS, 828 829 .__runtime_defaults.ip.ver = 10, 830 }, 831 STEP_INFO(glk_steppings), 832 }; 833 834 #define ICL_DISPLAY \ 835 .abox_mask = BIT(0), \ 836 .dbuf.size = 2048, \ 837 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 838 .has_ddi = 1, \ 839 .has_dp_mst = 1, \ 840 .has_fpga_dbg = 1, \ 841 .has_hotplug = 1, \ 842 .has_ipc = 1, \ 843 .has_psr = 1, \ 844 .has_psr_hw_tracking = 1, \ 845 .pipe_offsets = { \ 846 [TRANSCODER_A] = PIPE_A_OFFSET, \ 847 [TRANSCODER_B] = PIPE_B_OFFSET, \ 848 [TRANSCODER_C] = PIPE_C_OFFSET, \ 849 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 850 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 851 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 852 }, \ 853 .trans_offsets = { \ 854 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 855 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 856 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 857 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 858 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 859 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 860 }, \ 861 IVB_CURSOR_OFFSETS, \ 862 ICL_COLORS, \ 863 \ 864 .__runtime_defaults.ip.ver = 11, \ 865 .__runtime_defaults.has_dmc = 1, \ 866 .__runtime_defaults.has_dsc = 1, \ 867 .__runtime_defaults.has_hdcp = 1, \ 868 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 869 .__runtime_defaults.cpu_transcoder_mask = \ 870 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 871 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 872 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 873 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 874 875 static const u16 icl_port_f_ids[] = { 876 INTEL_ICL_PORT_F_IDS(ID), 877 0 878 }; 879 880 static const enum intel_step icl_steppings[] = { 881 [7] = STEP_D0, 882 }; 883 884 static const struct platform_desc icl_desc = { 885 PLATFORM(icelake), 886 .subplatforms = (const struct subplatform_desc[]) { 887 { 888 SUBPLATFORM(icelake, port_f), 889 .pciidlist = icl_port_f_ids, 890 }, 891 {}, 892 }, 893 .info = &(const struct intel_display_device_info) { 894 ICL_DISPLAY, 895 896 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 897 }, 898 STEP_INFO(icl_steppings), 899 }; 900 901 static const struct intel_display_device_info jsl_ehl_display = { 902 ICL_DISPLAY, 903 904 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), 905 }; 906 907 static const enum intel_step jsl_ehl_steppings[] = { 908 [0] = STEP_A0, 909 [1] = STEP_B0, 910 }; 911 912 static const struct platform_desc jsl_desc = { 913 PLATFORM(jasperlake), 914 .info = &jsl_ehl_display, 915 STEP_INFO(jsl_ehl_steppings), 916 }; 917 918 static const struct platform_desc ehl_desc = { 919 PLATFORM(elkhartlake), 920 .info = &jsl_ehl_display, 921 STEP_INFO(jsl_ehl_steppings), 922 }; 923 924 #define XE_D_DISPLAY \ 925 .abox_mask = GENMASK(2, 1), \ 926 .dbuf.size = 2048, \ 927 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 928 .has_ddi = 1, \ 929 .has_dp_mst = 1, \ 930 .has_dsb = 1, \ 931 .has_fpga_dbg = 1, \ 932 .has_hotplug = 1, \ 933 .has_ipc = 1, \ 934 .has_psr = 1, \ 935 .has_psr_hw_tracking = 1, \ 936 .pipe_offsets = { \ 937 [TRANSCODER_A] = PIPE_A_OFFSET, \ 938 [TRANSCODER_B] = PIPE_B_OFFSET, \ 939 [TRANSCODER_C] = PIPE_C_OFFSET, \ 940 [TRANSCODER_D] = PIPE_D_OFFSET, \ 941 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 942 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 943 }, \ 944 .trans_offsets = { \ 945 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 946 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 947 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 948 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 949 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 950 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 951 }, \ 952 TGL_CURSOR_OFFSETS, \ 953 ICL_COLORS, \ 954 \ 955 .__runtime_defaults.ip.ver = 12, \ 956 .__runtime_defaults.has_dmc = 1, \ 957 .__runtime_defaults.has_dsc = 1, \ 958 .__runtime_defaults.has_hdcp = 1, \ 959 .__runtime_defaults.pipe_mask = \ 960 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 961 .__runtime_defaults.cpu_transcoder_mask = \ 962 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 963 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 964 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 965 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 966 967 static const u16 tgl_uy_ids[] = { 968 INTEL_TGL_GT2_IDS(ID), 969 0 970 }; 971 972 static const enum intel_step tgl_steppings[] = { 973 [0] = STEP_B0, 974 [1] = STEP_D0, 975 }; 976 977 static const enum intel_step tgl_uy_steppings[] = { 978 [0] = STEP_A0, 979 [1] = STEP_C0, 980 [2] = STEP_C0, 981 [3] = STEP_D0, 982 }; 983 984 static const struct platform_desc tgl_desc = { 985 PLATFORM(tigerlake), 986 .subplatforms = (const struct subplatform_desc[]) { 987 { 988 SUBPLATFORM(tigerlake, uy), 989 .pciidlist = tgl_uy_ids, 990 STEP_INFO(tgl_uy_steppings), 991 }, 992 {}, 993 }, 994 .info = &(const struct intel_display_device_info) { 995 XE_D_DISPLAY, 996 997 /* 998 * FIXME DDI C/combo PHY C missing due to combo PHY 999 * code making a mess on SKUs where the PHY is missing. 1000 */ 1001 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1002 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), 1003 }, 1004 STEP_INFO(tgl_steppings), 1005 }; 1006 1007 static const enum intel_step dg1_steppings[] = { 1008 [0] = STEP_A0, 1009 [1] = STEP_B0, 1010 }; 1011 1012 static const struct platform_desc dg1_desc = { 1013 PLATFORM(dg1), 1014 .info = &(const struct intel_display_device_info) { 1015 XE_D_DISPLAY, 1016 1017 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1018 BIT(PORT_TC1) | BIT(PORT_TC2), 1019 }, 1020 STEP_INFO(dg1_steppings), 1021 }; 1022 1023 static const enum intel_step rkl_steppings[] = { 1024 [0] = STEP_A0, 1025 [1] = STEP_B0, 1026 [4] = STEP_C0, 1027 }; 1028 1029 static const struct platform_desc rkl_desc = { 1030 PLATFORM(rocketlake), 1031 .info = &(const struct intel_display_device_info) { 1032 XE_D_DISPLAY, 1033 .abox_mask = BIT(0), 1034 .has_hti = 1, 1035 .has_psr_hw_tracking = 0, 1036 1037 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1038 .__runtime_defaults.cpu_transcoder_mask = 1039 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 1040 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1041 BIT(PORT_TC1) | BIT(PORT_TC2), 1042 }, 1043 STEP_INFO(rkl_steppings), 1044 }; 1045 1046 static const u16 adls_rpls_ids[] = { 1047 INTEL_RPLS_IDS(ID), 1048 0 1049 }; 1050 1051 static const enum intel_step adl_s_steppings[] = { 1052 [0x0] = STEP_A0, 1053 [0x1] = STEP_A2, 1054 [0x4] = STEP_B0, 1055 [0x8] = STEP_B0, 1056 [0xC] = STEP_C0, 1057 }; 1058 1059 static const enum intel_step adl_s_rpl_s_steppings[] = { 1060 [0x4] = STEP_D0, 1061 [0xC] = STEP_C0, 1062 }; 1063 1064 static const struct platform_desc adl_s_desc = { 1065 PLATFORM(alderlake_s), 1066 .subplatforms = (const struct subplatform_desc[]) { 1067 { 1068 SUBPLATFORM(alderlake_s, raptorlake_s), 1069 .pciidlist = adls_rpls_ids, 1070 STEP_INFO(adl_s_rpl_s_steppings), 1071 }, 1072 {}, 1073 }, 1074 .info = &(const struct intel_display_device_info) { 1075 XE_D_DISPLAY, 1076 .has_hti = 1, 1077 .has_psr_hw_tracking = 0, 1078 1079 .__runtime_defaults.port_mask = BIT(PORT_A) | 1080 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1081 }, 1082 STEP_INFO(adl_s_steppings), 1083 }; 1084 1085 #define XE_LPD_FEATURES \ 1086 .abox_mask = GENMASK(1, 0), \ 1087 .color = { \ 1088 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 1089 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 1090 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 1091 }, \ 1092 .dbuf.size = 4096, \ 1093 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 1094 BIT(DBUF_S4), \ 1095 .has_ddi = 1, \ 1096 .has_dp_mst = 1, \ 1097 .has_dsb = 1, \ 1098 .has_fpga_dbg = 1, \ 1099 .has_hotplug = 1, \ 1100 .has_ipc = 1, \ 1101 .has_psr = 1, \ 1102 .pipe_offsets = { \ 1103 [TRANSCODER_A] = PIPE_A_OFFSET, \ 1104 [TRANSCODER_B] = PIPE_B_OFFSET, \ 1105 [TRANSCODER_C] = PIPE_C_OFFSET, \ 1106 [TRANSCODER_D] = PIPE_D_OFFSET, \ 1107 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 1108 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 1109 }, \ 1110 .trans_offsets = { \ 1111 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 1112 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 1113 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 1114 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 1115 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 1116 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 1117 }, \ 1118 TGL_CURSOR_OFFSETS, \ 1119 \ 1120 .__runtime_defaults.ip.ver = 13, \ 1121 .__runtime_defaults.has_dmc = 1, \ 1122 .__runtime_defaults.has_dsc = 1, \ 1123 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 1124 .__runtime_defaults.has_hdcp = 1, \ 1125 .__runtime_defaults.pipe_mask = \ 1126 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D) 1127 1128 static const struct intel_display_device_info xe_lpd_display = { 1129 XE_LPD_FEATURES, 1130 .has_cdclk_crawl = 1, 1131 .has_psr_hw_tracking = 0, 1132 1133 .__runtime_defaults.cpu_transcoder_mask = 1134 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1135 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 1136 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 1137 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1138 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1139 }; 1140 1141 static const u16 adlp_adln_ids[] = { 1142 INTEL_ADLN_IDS(ID), 1143 0 1144 }; 1145 1146 static const u16 adlp_rplu_ids[] = { 1147 INTEL_RPLU_IDS(ID), 1148 0 1149 }; 1150 1151 static const u16 adlp_rplp_ids[] = { 1152 INTEL_RPLP_IDS(ID), 1153 0 1154 }; 1155 1156 static const enum intel_step adl_p_steppings[] = { 1157 [0x0] = STEP_A0, 1158 [0x4] = STEP_B0, 1159 [0x8] = STEP_C0, 1160 [0xC] = STEP_D0, 1161 }; 1162 1163 static const enum intel_step adl_p_adl_n_steppings[] = { 1164 [0x0] = STEP_D0, 1165 }; 1166 1167 static const enum intel_step adl_p_rpl_pu_steppings[] = { 1168 [0x4] = STEP_E0, 1169 }; 1170 1171 static const struct platform_desc adl_p_desc = { 1172 PLATFORM(alderlake_p), 1173 .subplatforms = (const struct subplatform_desc[]) { 1174 { 1175 SUBPLATFORM(alderlake_p, alderlake_n), 1176 .pciidlist = adlp_adln_ids, 1177 STEP_INFO(adl_p_adl_n_steppings), 1178 }, 1179 { 1180 SUBPLATFORM(alderlake_p, raptorlake_p), 1181 .pciidlist = adlp_rplp_ids, 1182 STEP_INFO(adl_p_rpl_pu_steppings), 1183 }, 1184 { 1185 SUBPLATFORM(alderlake_p, raptorlake_u), 1186 .pciidlist = adlp_rplu_ids, 1187 STEP_INFO(adl_p_rpl_pu_steppings), 1188 }, 1189 {}, 1190 }, 1191 .info = &xe_lpd_display, 1192 STEP_INFO(adl_p_steppings), 1193 }; 1194 1195 static const struct intel_display_device_info xe_hpd_display = { 1196 XE_LPD_FEATURES, 1197 .has_cdclk_squash = 1, 1198 1199 .__runtime_defaults.cpu_transcoder_mask = 1200 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1201 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1202 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) | 1203 BIT(PORT_TC1), 1204 }; 1205 1206 static const u16 dg2_g10_ids[] = { 1207 INTEL_DG2_G10_IDS(ID), 1208 0 1209 }; 1210 1211 static const u16 dg2_g11_ids[] = { 1212 INTEL_DG2_G11_IDS(ID), 1213 0 1214 }; 1215 1216 static const u16 dg2_g12_ids[] = { 1217 INTEL_DG2_G12_IDS(ID), 1218 0 1219 }; 1220 1221 static const enum intel_step dg2_g10_steppings[] = { 1222 [0x0] = STEP_A0, 1223 [0x1] = STEP_A0, 1224 [0x4] = STEP_B0, 1225 [0x8] = STEP_C0, 1226 }; 1227 1228 static const enum intel_step dg2_g11_steppings[] = { 1229 [0x0] = STEP_B0, 1230 [0x4] = STEP_C0, 1231 [0x5] = STEP_C0, 1232 }; 1233 1234 static const enum intel_step dg2_g12_steppings[] = { 1235 [0x0] = STEP_C0, 1236 [0x1] = STEP_C0, 1237 }; 1238 1239 static const struct platform_desc dg2_desc = { 1240 PLATFORM(dg2), 1241 .subplatforms = (const struct subplatform_desc[]) { 1242 { 1243 SUBPLATFORM(dg2, g10), 1244 .pciidlist = dg2_g10_ids, 1245 STEP_INFO(dg2_g10_steppings), 1246 }, 1247 { 1248 SUBPLATFORM(dg2, g11), 1249 .pciidlist = dg2_g11_ids, 1250 STEP_INFO(dg2_g11_steppings), 1251 }, 1252 { 1253 SUBPLATFORM(dg2, g12), 1254 .pciidlist = dg2_g12_ids, 1255 STEP_INFO(dg2_g12_steppings), 1256 }, 1257 {}, 1258 }, 1259 .info = &xe_hpd_display, 1260 }; 1261 1262 #define XE_LPDP_FEATURES \ 1263 .abox_mask = GENMASK(1, 0), \ 1264 .color = { \ 1265 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 1266 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 1267 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 1268 }, \ 1269 .dbuf.size = 4096, \ 1270 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 1271 BIT(DBUF_S4), \ 1272 .has_cdclk_crawl = 1, \ 1273 .has_cdclk_squash = 1, \ 1274 .has_ddi = 1, \ 1275 .has_dp_mst = 1, \ 1276 .has_dsb = 1, \ 1277 .has_fpga_dbg = 1, \ 1278 .has_hotplug = 1, \ 1279 .has_ipc = 1, \ 1280 .has_psr = 1, \ 1281 .pipe_offsets = { \ 1282 [TRANSCODER_A] = PIPE_A_OFFSET, \ 1283 [TRANSCODER_B] = PIPE_B_OFFSET, \ 1284 [TRANSCODER_C] = PIPE_C_OFFSET, \ 1285 [TRANSCODER_D] = PIPE_D_OFFSET, \ 1286 }, \ 1287 .trans_offsets = { \ 1288 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 1289 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 1290 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 1291 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 1292 }, \ 1293 TGL_CURSOR_OFFSETS, \ 1294 \ 1295 .__runtime_defaults.cpu_transcoder_mask = \ 1296 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 1297 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ 1298 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \ 1299 .__runtime_defaults.has_dmc = 1, \ 1300 .__runtime_defaults.has_dsc = 1, \ 1301 .__runtime_defaults.has_hdcp = 1, \ 1302 .__runtime_defaults.pipe_mask = \ 1303 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 1304 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \ 1305 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) 1306 1307 static const struct intel_display_device_info xe_lpdp_display = { 1308 XE_LPDP_FEATURES, 1309 }; 1310 1311 static const struct intel_display_device_info xe2_lpd_display = { 1312 XE_LPDP_FEATURES, 1313 1314 .__runtime_defaults.fbc_mask = 1315 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | 1316 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), 1317 .__runtime_defaults.has_dbuf_overlap_detection = true, 1318 }; 1319 1320 static const struct intel_display_device_info xe2_hpd_display = { 1321 XE_LPDP_FEATURES, 1322 .__runtime_defaults.port_mask = BIT(PORT_A) | 1323 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1324 }; 1325 1326 /* 1327 * Do not initialize the .info member of the platform desc for GMD ID based 1328 * platforms. Their display will be probed automatically based on the IP version 1329 * reported by the hardware. 1330 */ 1331 static const struct platform_desc mtl_desc = { 1332 PLATFORM(meteorlake), 1333 }; 1334 1335 static const struct platform_desc lnl_desc = { 1336 PLATFORM(lunarlake), 1337 }; 1338 1339 static const struct platform_desc bmg_desc = { 1340 PLATFORM(battlemage), 1341 }; 1342 1343 static const struct platform_desc ptl_desc = { 1344 PLATFORM(pantherlake), 1345 }; 1346 1347 __diag_pop(); 1348 1349 /* 1350 * Separate detection for no display cases to keep the display id array simple. 1351 * 1352 * IVB Q requires subvendor and subdevice matching to differentiate from IVB D 1353 * GT2 server. 1354 */ 1355 static bool has_no_display(struct pci_dev *pdev) 1356 { 1357 static const struct pci_device_id ids[] = { 1358 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0), 1359 {} 1360 }; 1361 1362 return pci_match_id(ids, pdev); 1363 } 1364 1365 #define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) } 1366 1367 static const struct { 1368 u32 devid; 1369 const struct platform_desc *desc; 1370 } intel_display_ids[] = { 1371 INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_desc), 1372 INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_desc), 1373 INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_desc), 1374 INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_desc), 1375 INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_desc), 1376 INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_desc), 1377 INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_desc), 1378 INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_desc), 1379 INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_desc), 1380 INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_desc), 1381 INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc), 1382 INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc), 1383 INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc), 1384 INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_desc), 1385 INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc), 1386 INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc), 1387 INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_desc), 1388 INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_desc), 1389 INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc), 1390 INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc), 1391 INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc), 1392 INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_desc), 1393 INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_desc), 1394 INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_desc), 1395 INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_desc), 1396 INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &kbl_desc), 1397 INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), 1398 INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), 1399 INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &cml_desc), 1400 INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_desc), 1401 INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &ehl_desc), 1402 INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_desc), 1403 INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_desc), 1404 INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_desc), 1405 INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_desc), 1406 INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), 1407 INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), 1408 INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1409 INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1410 INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1411 INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1412 INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), 1413 INTEL_ARL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), 1414 INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), 1415 INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), 1416 INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), 1417 INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1418 }; 1419 1420 static const struct { 1421 u16 ver; 1422 u16 rel; 1423 const struct intel_display_device_info *display; 1424 } gmdid_display_map[] = { 1425 { 14, 0, &xe_lpdp_display }, 1426 { 14, 1, &xe2_hpd_display }, 1427 { 20, 0, &xe2_lpd_display }, 1428 { 30, 0, &xe2_lpd_display }, 1429 }; 1430 1431 static const struct intel_display_device_info * 1432 probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver *ip_ver) 1433 { 1434 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1435 struct intel_display_ip_ver gmd_id; 1436 void __iomem *addr; 1437 u32 val; 1438 int i; 1439 1440 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 1441 if (!addr) { 1442 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); 1443 return NULL; 1444 } 1445 1446 val = ioread32(addr); 1447 pci_iounmap(pdev, addr); 1448 1449 if (val == 0) { 1450 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 1451 return NULL; 1452 } 1453 1454 gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 1455 gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 1456 gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val); 1457 1458 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { 1459 if (gmd_id.ver == gmdid_display_map[i].ver && 1460 gmd_id.rel == gmdid_display_map[i].rel) { 1461 *ip_ver = gmd_id; 1462 return gmdid_display_map[i].display; 1463 } 1464 } 1465 1466 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", 1467 gmd_id.ver, gmd_id.rel); 1468 return NULL; 1469 } 1470 1471 static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) 1472 { 1473 int i; 1474 1475 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { 1476 if (intel_display_ids[i].devid == pdev->device) 1477 return intel_display_ids[i].desc; 1478 } 1479 1480 return NULL; 1481 } 1482 1483 static const struct subplatform_desc * 1484 find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc) 1485 { 1486 const struct subplatform_desc *sp; 1487 const u16 *id; 1488 1489 for (sp = desc->subplatforms; sp && sp->pciidlist; sp++) 1490 for (id = sp->pciidlist; *id; id++) 1491 if (*id == pdev->device) 1492 return sp; 1493 1494 return NULL; 1495 } 1496 1497 static enum intel_step get_pre_gmdid_step(struct intel_display *display, 1498 const struct stepping_desc *main, 1499 const struct stepping_desc *sub) 1500 { 1501 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 1502 const enum intel_step *map = main->map; 1503 int size = main->size; 1504 int revision = pdev->revision; 1505 enum intel_step step; 1506 1507 /* subplatform stepping info trumps main platform info */ 1508 if (sub && sub->map && sub->size) { 1509 map = sub->map; 1510 size = sub->size; 1511 } 1512 1513 /* not all platforms define steppings, and it's fine */ 1514 if (!map || !size) 1515 return STEP_NONE; 1516 1517 if (revision < size && map[revision] != STEP_NONE) { 1518 step = map[revision]; 1519 } else { 1520 drm_warn(display->drm, "Unknown revision 0x%02x\n", revision); 1521 1522 /* 1523 * If we hit a gap in the revision to step map, use the information 1524 * for the next revision. 1525 * 1526 * This may be wrong in all sorts of ways, especially if the 1527 * steppings in the array are not monotonically increasing, but 1528 * it's better than defaulting to 0. 1529 */ 1530 while (revision < size && map[revision] == STEP_NONE) 1531 revision++; 1532 1533 if (revision < size) { 1534 drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n", 1535 revision); 1536 step = map[revision]; 1537 } else { 1538 drm_dbg_kms(display->drm, "Using future display stepping\n"); 1539 step = STEP_FUTURE; 1540 } 1541 } 1542 1543 drm_WARN_ON(display->drm, step == STEP_NONE); 1544 1545 return step; 1546 } 1547 1548 /* Size of the entire bitmap, not the number of platforms */ 1549 static unsigned int display_platforms_num_bits(void) 1550 { 1551 return sizeof(((struct intel_display_platforms *)0)->bitmap) * BITS_PER_BYTE; 1552 } 1553 1554 /* Number of platform bits set */ 1555 static unsigned int display_platforms_weight(const struct intel_display_platforms *p) 1556 { 1557 return bitmap_weight(p->bitmap, display_platforms_num_bits()); 1558 } 1559 1560 /* Merge the subplatform information from src to dst */ 1561 static void display_platforms_or(struct intel_display_platforms *dst, 1562 const struct intel_display_platforms *src) 1563 { 1564 bitmap_or(dst->bitmap, dst->bitmap, src->bitmap, display_platforms_num_bits()); 1565 } 1566 1567 void intel_display_device_probe(struct drm_i915_private *i915) 1568 { 1569 struct intel_display *display = &i915->display; 1570 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1571 const struct intel_display_device_info *info; 1572 struct intel_display_ip_ver ip_ver = {}; 1573 const struct platform_desc *desc; 1574 const struct subplatform_desc *subdesc; 1575 enum intel_step step; 1576 1577 /* Add drm device backpointer as early as possible. */ 1578 i915->display.drm = &i915->drm; 1579 1580 intel_display_params_copy(&i915->display.params); 1581 1582 if (has_no_display(pdev)) { 1583 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 1584 goto no_display; 1585 } 1586 1587 desc = find_platform_desc(pdev); 1588 if (!desc) { 1589 drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n", 1590 pdev->device); 1591 goto no_display; 1592 } 1593 1594 info = desc->info; 1595 if (!info) 1596 info = probe_gmdid_display(i915, &ip_ver); 1597 if (!info) 1598 goto no_display; 1599 1600 DISPLAY_INFO(i915) = info; 1601 1602 memcpy(DISPLAY_RUNTIME_INFO(i915), 1603 &DISPLAY_INFO(i915)->__runtime_defaults, 1604 sizeof(*DISPLAY_RUNTIME_INFO(i915))); 1605 1606 drm_WARN_ON(&i915->drm, !desc->name || 1607 !display_platforms_weight(&desc->platforms)); 1608 1609 display->platform = desc->platforms; 1610 1611 subdesc = find_subplatform_desc(pdev, desc); 1612 if (subdesc) { 1613 drm_WARN_ON(&i915->drm, !subdesc->name || 1614 !display_platforms_weight(&subdesc->platforms)); 1615 1616 display_platforms_or(&display->platform, &subdesc->platforms); 1617 1618 /* Ensure platform and subplatform are distinct */ 1619 drm_WARN_ON(&i915->drm, 1620 display_platforms_weight(&display->platform) != 1621 display_platforms_weight(&desc->platforms) + 1622 display_platforms_weight(&subdesc->platforms)); 1623 } 1624 1625 if (ip_ver.ver || ip_ver.rel || ip_ver.step) { 1626 DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; 1627 step = STEP_A0 + ip_ver.step; 1628 if (step > STEP_FUTURE) { 1629 drm_dbg_kms(display->drm, "Using future display stepping\n"); 1630 step = STEP_FUTURE; 1631 } 1632 } else { 1633 step = get_pre_gmdid_step(display, &desc->step_info, 1634 subdesc ? &subdesc->step_info : NULL); 1635 } 1636 1637 DISPLAY_RUNTIME_INFO(i915)->step = step; 1638 1639 drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u stepping %s\n", 1640 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", 1641 pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, 1642 DISPLAY_RUNTIME_INFO(i915)->ip.rel, 1643 step != STEP_NONE ? intel_step_name(step) : "N/A"); 1644 1645 return; 1646 1647 no_display: 1648 DISPLAY_INFO(i915) = &no_display; 1649 } 1650 1651 void intel_display_device_remove(struct drm_i915_private *i915) 1652 { 1653 intel_display_params_free(&i915->display.params); 1654 } 1655 1656 static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1657 { 1658 struct intel_display *display = &i915->display; 1659 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); 1660 enum pipe pipe; 1661 1662 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); 1663 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); 1664 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); 1665 1666 /* This covers both ULT and ULX */ 1667 if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915)) 1668 display_runtime->port_mask &= ~BIT(PORT_D); 1669 1670 if (IS_ICL_WITH_PORT_F(i915)) 1671 display_runtime->port_mask |= BIT(PORT_F); 1672 1673 /* Wa_14011765242: adl-s A0,A1 */ 1674 if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) 1675 for_each_pipe(i915, pipe) 1676 display_runtime->num_scalers[pipe] = 0; 1677 else if (DISPLAY_VER(i915) >= 11) { 1678 for_each_pipe(i915, pipe) 1679 display_runtime->num_scalers[pipe] = 2; 1680 } else if (DISPLAY_VER(i915) >= 9) { 1681 display_runtime->num_scalers[PIPE_A] = 2; 1682 display_runtime->num_scalers[PIPE_B] = 2; 1683 display_runtime->num_scalers[PIPE_C] = 1; 1684 } 1685 1686 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 1687 for_each_pipe(i915, pipe) 1688 display_runtime->num_sprites[pipe] = 4; 1689 else if (DISPLAY_VER(i915) >= 11) 1690 for_each_pipe(i915, pipe) 1691 display_runtime->num_sprites[pipe] = 6; 1692 else if (DISPLAY_VER(i915) == 10) 1693 for_each_pipe(i915, pipe) 1694 display_runtime->num_sprites[pipe] = 3; 1695 else if (IS_BROXTON(i915)) { 1696 /* 1697 * Skylake and Broxton currently don't expose the topmost plane as its 1698 * use is exclusive with the legacy cursor and we only want to expose 1699 * one of those, not both. Until we can safely expose the topmost plane 1700 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 1701 * we don't expose the topmost plane at all to prevent ABI breakage 1702 * down the line. 1703 */ 1704 1705 display_runtime->num_sprites[PIPE_A] = 2; 1706 display_runtime->num_sprites[PIPE_B] = 2; 1707 display_runtime->num_sprites[PIPE_C] = 1; 1708 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1709 for_each_pipe(i915, pipe) 1710 display_runtime->num_sprites[pipe] = 2; 1711 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { 1712 for_each_pipe(i915, pipe) 1713 display_runtime->num_sprites[pipe] = 1; 1714 } 1715 1716 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && 1717 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { 1718 drm_info(&i915->drm, "Display not present, disabling\n"); 1719 goto display_fused_off; 1720 } 1721 1722 if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { 1723 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); 1724 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); 1725 1726 /* 1727 * SFUSE_STRAP is supposed to have a bit signalling the display 1728 * is fused off. Unfortunately it seems that, at least in 1729 * certain cases, fused off display means that PCH display 1730 * reads don't land anywhere. In that case, we read 0s. 1731 * 1732 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 1733 * should be set when taking over after the firmware. 1734 */ 1735 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 1736 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 1737 (HAS_PCH_CPT(i915) && 1738 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 1739 drm_info(&i915->drm, 1740 "Display fused off, disabling\n"); 1741 goto display_fused_off; 1742 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 1743 drm_info(&i915->drm, "PipeC fused off\n"); 1744 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1745 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1746 } 1747 } else if (DISPLAY_VER(i915) >= 9) { 1748 u32 dfsm = intel_de_read(i915, SKL_DFSM); 1749 1750 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 1751 display_runtime->pipe_mask &= ~BIT(PIPE_A); 1752 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 1753 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 1754 } 1755 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 1756 display_runtime->pipe_mask &= ~BIT(PIPE_B); 1757 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 1758 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); 1759 } 1760 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 1761 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1762 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1763 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); 1764 } 1765 1766 if (DISPLAY_VER(i915) >= 12 && 1767 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1768 display_runtime->pipe_mask &= ~BIT(PIPE_D); 1769 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 1770 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); 1771 } 1772 1773 if (!display_runtime->pipe_mask) 1774 goto display_fused_off; 1775 1776 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1777 display_runtime->has_hdcp = 0; 1778 1779 if (IS_DG2(i915) || DISPLAY_VER(i915) < 13) { 1780 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1781 display_runtime->fbc_mask = 0; 1782 } 1783 1784 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1785 display_runtime->has_dmc = 0; 1786 1787 if (IS_DISPLAY_VER(i915, 10, 12) && 1788 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 1789 display_runtime->has_dsc = 0; 1790 1791 if (DISPLAY_VER(display) >= 20 && 1792 (dfsm & XE2LPD_DFSM_DBUF_OVERLAP_DISABLE)) 1793 display_runtime->has_dbuf_overlap_detection = false; 1794 } 1795 1796 if (DISPLAY_VER(i915) >= 20) { 1797 u32 cap = intel_de_read(i915, XE2LPD_DE_CAP); 1798 1799 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == 1800 XE2LPD_DE_CAP_DSC_REMOVED) 1801 display_runtime->has_dsc = 0; 1802 1803 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) == 1804 XE2LPD_DE_CAP_SCALER_SINGLE) { 1805 for_each_pipe(i915, pipe) 1806 if (display_runtime->num_scalers[pipe]) 1807 display_runtime->num_scalers[pipe] = 1; 1808 } 1809 } 1810 1811 if (DISPLAY_VER(i915) >= 30) 1812 display_runtime->edp_typec_support = 1813 intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC; 1814 1815 display_runtime->rawclk_freq = intel_read_rawclk(display); 1816 drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); 1817 1818 return; 1819 1820 display_fused_off: 1821 memset(display_runtime, 0, sizeof(*display_runtime)); 1822 } 1823 1824 void intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1825 { 1826 if (HAS_DISPLAY(i915)) 1827 __intel_display_device_info_runtime_init(i915); 1828 1829 /* Display may have been disabled by runtime init */ 1830 if (!HAS_DISPLAY(i915)) { 1831 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 1832 i915->display.info.__device_info = &no_display; 1833 } 1834 1835 /* Disable nuclear pageflip by default on pre-g4x */ 1836 if (!i915->display.params.nuclear_pageflip && 1837 DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) 1838 i915->drm.driver_features &= ~DRIVER_ATOMIC; 1839 } 1840 1841 void intel_display_device_info_print(const struct intel_display_device_info *info, 1842 const struct intel_display_runtime_info *runtime, 1843 struct drm_printer *p) 1844 { 1845 if (runtime->ip.rel) 1846 drm_printf(p, "display version: %u.%02u\n", 1847 runtime->ip.ver, 1848 runtime->ip.rel); 1849 else 1850 drm_printf(p, "display version: %u\n", 1851 runtime->ip.ver); 1852 1853 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step)); 1854 1855 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 1856 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 1857 #undef PRINT_FLAG 1858 1859 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); 1860 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); 1861 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); 1862 1863 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 1864 } 1865 1866 /* 1867 * Assuming the device has display hardware, should it be enabled? 1868 * 1869 * It's an error to call this function if the device does not have display 1870 * hardware. 1871 * 1872 * Disabling display means taking over the display hardware, putting it to 1873 * sleep, and preventing connectors from being connected via any means. 1874 */ 1875 bool intel_display_device_enabled(struct drm_i915_private *i915) 1876 { 1877 struct intel_display *display = &i915->display; 1878 1879 /* Only valid when HAS_DISPLAY() is true */ 1880 drm_WARN_ON(display->drm, !HAS_DISPLAY(display)); 1881 1882 return !display->params.disable_display && 1883 !intel_opregion_headless_sku(display); 1884 } 1885