1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/pci.h> 7 8 #include <drm/drm_color_mgmt.h> 9 #include <drm/drm_drv.h> 10 #include <drm/drm_print.h> 11 #include <drm/intel/pciids.h> 12 #include <drm/intel/step.h> 13 14 #include "intel_cx0_phy_regs.h" 15 #include "intel_de.h" 16 #include "intel_display.h" 17 #include "intel_display_device.h" 18 #include "intel_display_params.h" 19 #include "intel_display_power.h" 20 #include "intel_display_reg_defs.h" 21 #include "intel_display_regs.h" 22 #include "intel_display_types.h" 23 #include "intel_display_wa.h" 24 #include "intel_fbc.h" 25 26 __diag_push(); 27 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); 28 29 struct stepping_desc { 30 const enum intel_step *map; /* revid to step map */ 31 size_t size; /* map size */ 32 }; 33 34 #define STEP_INFO(_map) \ 35 .step_info.map = _map, \ 36 .step_info.size = ARRAY_SIZE(_map) 37 38 struct subplatform_desc { 39 struct intel_display_platforms platforms; 40 const char *name; 41 const u16 *pciidlist; 42 struct stepping_desc step_info; 43 }; 44 45 #define SUBPLATFORM(_platform, _subplatform) \ 46 .platforms._platform##_##_subplatform = 1, \ 47 .name = #_subplatform 48 49 /* 50 * Group subplatform alias that matches multiple subplatforms. For making ult 51 * cover both ult and ulx on HSW/BDW. 52 */ 53 #define SUBPLATFORM_GROUP(_platform, _subplatform) \ 54 .platforms._platform##_##_subplatform = 1 55 56 struct platform_desc { 57 struct intel_display_platforms platforms; 58 const char *name; 59 const struct subplatform_desc *subplatforms; 60 const struct intel_display_device_info *info; /* NULL for GMD ID */ 61 struct stepping_desc step_info; 62 }; 63 64 #define PLATFORM(_platform) \ 65 .platforms._platform = 1, \ 66 .name = #_platform 67 68 /* 69 * Group platform alias that matches multiple platforms. For aliases such as g4x 70 * that covers both g45 and gm45. 71 */ 72 #define PLATFORM_GROUP(_platform) \ 73 .platforms._platform = 1 74 75 #define ID(id) (id) 76 77 static const struct intel_display_device_info no_display = {}; 78 79 #define PIPE_A_OFFSET 0x70000 80 #define PIPE_B_OFFSET 0x71000 81 #define PIPE_C_OFFSET 0x72000 82 #define PIPE_D_OFFSET 0x73000 83 #define CHV_PIPE_C_OFFSET 0x74000 84 /* 85 * There's actually no pipe EDP. Some pipe registers have 86 * simply shifted from the pipe to the transcoder, while 87 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 88 * to access such registers in transcoder EDP. 89 */ 90 #define PIPE_EDP_OFFSET 0x7f000 91 92 /* ICL DSI 0 and 1 */ 93 #define PIPE_DSI0_OFFSET 0x7b000 94 #define PIPE_DSI1_OFFSET 0x7b800 95 96 #define TRANSCODER_A_OFFSET 0x60000 97 #define TRANSCODER_B_OFFSET 0x61000 98 #define TRANSCODER_C_OFFSET 0x62000 99 #define CHV_TRANSCODER_C_OFFSET 0x63000 100 #define TRANSCODER_D_OFFSET 0x63000 101 #define TRANSCODER_EDP_OFFSET 0x6f000 102 #define TRANSCODER_DSI0_OFFSET 0x6b000 103 #define TRANSCODER_DSI1_OFFSET 0x6b800 104 #define TRANSCODER_CMTG0_OFFSET 0x6F000 105 #define TRANSCODER_CMTG1_OFFSET 0x6F100 106 107 #define CURSOR_A_OFFSET 0x70080 108 #define CURSOR_B_OFFSET 0x700c0 109 #define CHV_CURSOR_C_OFFSET 0x700e0 110 #define IVB_CURSOR_B_OFFSET 0x71080 111 #define IVB_CURSOR_C_OFFSET 0x72080 112 #define TGL_CURSOR_D_OFFSET 0x73080 113 114 #define I845_PIPE_OFFSETS \ 115 .pipe_offsets = { \ 116 [TRANSCODER_A] = PIPE_A_OFFSET, \ 117 }, \ 118 .trans_offsets = { \ 119 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 120 } 121 122 #define I9XX_PIPE_OFFSETS \ 123 .pipe_offsets = { \ 124 [TRANSCODER_A] = PIPE_A_OFFSET, \ 125 [TRANSCODER_B] = PIPE_B_OFFSET, \ 126 }, \ 127 .trans_offsets = { \ 128 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 129 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 130 } 131 132 #define IVB_PIPE_OFFSETS \ 133 .pipe_offsets = { \ 134 [TRANSCODER_A] = PIPE_A_OFFSET, \ 135 [TRANSCODER_B] = PIPE_B_OFFSET, \ 136 [TRANSCODER_C] = PIPE_C_OFFSET, \ 137 }, \ 138 .trans_offsets = { \ 139 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 140 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 141 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 142 } 143 144 #define HSW_PIPE_OFFSETS \ 145 .pipe_offsets = { \ 146 [TRANSCODER_A] = PIPE_A_OFFSET, \ 147 [TRANSCODER_B] = PIPE_B_OFFSET, \ 148 [TRANSCODER_C] = PIPE_C_OFFSET, \ 149 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 150 }, \ 151 .trans_offsets = { \ 152 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 153 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 154 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 155 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 156 } 157 158 #define CHV_PIPE_OFFSETS \ 159 .pipe_offsets = { \ 160 [TRANSCODER_A] = PIPE_A_OFFSET, \ 161 [TRANSCODER_B] = PIPE_B_OFFSET, \ 162 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 163 }, \ 164 .trans_offsets = { \ 165 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 166 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 167 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 168 } 169 170 #define I845_CURSOR_OFFSETS \ 171 .cursor_offsets = { \ 172 [PIPE_A] = CURSOR_A_OFFSET, \ 173 } 174 175 #define I9XX_CURSOR_OFFSETS \ 176 .cursor_offsets = { \ 177 [PIPE_A] = CURSOR_A_OFFSET, \ 178 [PIPE_B] = CURSOR_B_OFFSET, \ 179 } 180 181 #define CHV_CURSOR_OFFSETS \ 182 .cursor_offsets = { \ 183 [PIPE_A] = CURSOR_A_OFFSET, \ 184 [PIPE_B] = CURSOR_B_OFFSET, \ 185 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 186 } 187 188 #define IVB_CURSOR_OFFSETS \ 189 .cursor_offsets = { \ 190 [PIPE_A] = CURSOR_A_OFFSET, \ 191 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 192 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 193 } 194 195 #define TGL_CURSOR_OFFSETS \ 196 .cursor_offsets = { \ 197 [PIPE_A] = CURSOR_A_OFFSET, \ 198 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 199 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 200 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 201 } 202 203 #define I845_COLORS \ 204 .color = { .gamma_lut_size = 256 } 205 #define I9XX_COLORS \ 206 .color = { .gamma_lut_size = 129, \ 207 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 208 } 209 #define ILK_COLORS \ 210 .color = { .gamma_lut_size = 1024 } 211 #define IVB_COLORS \ 212 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 213 #define CHV_COLORS \ 214 .color = { \ 215 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 216 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 217 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 218 } 219 #define GLK_COLORS \ 220 .color = { \ 221 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 222 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 223 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 224 } 225 #define ICL_COLORS \ 226 .color = { \ 227 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 228 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 229 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 230 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 231 } 232 233 #define I830_DISPLAY \ 234 .has_overlay = 1, \ 235 .cursor_needs_physical = 1, \ 236 .overlay_needs_physical = 1, \ 237 .has_gmch = 1, \ 238 I9XX_PIPE_OFFSETS, \ 239 I9XX_CURSOR_OFFSETS, \ 240 I9XX_COLORS, \ 241 \ 242 .__runtime_defaults.ip.ver = 2, \ 243 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 244 .__runtime_defaults.cpu_transcoder_mask = \ 245 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 246 247 #define I845_DISPLAY \ 248 .has_overlay = 1, \ 249 .overlay_needs_physical = 1, \ 250 .has_gmch = 1, \ 251 I845_PIPE_OFFSETS, \ 252 I845_CURSOR_OFFSETS, \ 253 I845_COLORS, \ 254 \ 255 .__runtime_defaults.ip.ver = 2, \ 256 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ 257 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) 258 259 static const struct platform_desc i830_desc = { 260 PLATFORM(i830), 261 PLATFORM_GROUP(mobile), 262 .info = &(const struct intel_display_device_info) { 263 I830_DISPLAY, 264 265 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ 266 }, 267 }; 268 269 static const struct platform_desc i845_desc = { 270 PLATFORM(i845g), 271 .info = &(const struct intel_display_device_info) { 272 I845_DISPLAY, 273 274 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 275 }, 276 }; 277 278 static const struct platform_desc i85x_desc = { 279 PLATFORM(i85x), 280 PLATFORM_GROUP(mobile), 281 .info = &(const struct intel_display_device_info) { 282 I830_DISPLAY, 283 284 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 285 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 286 }, 287 }; 288 289 static const struct platform_desc i865g_desc = { 290 PLATFORM(i865g), 291 .info = &(const struct intel_display_device_info) { 292 I845_DISPLAY, 293 294 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ 295 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 296 }, 297 }; 298 299 #define GEN3_DISPLAY \ 300 .has_gmch = 1, \ 301 .has_overlay = 1, \ 302 I9XX_PIPE_OFFSETS, \ 303 I9XX_CURSOR_OFFSETS, \ 304 \ 305 .__runtime_defaults.ip.ver = 3, \ 306 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 307 .__runtime_defaults.cpu_transcoder_mask = \ 308 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 309 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ 310 311 static const struct platform_desc i915g_desc = { 312 PLATFORM(i915g), 313 .info = &(const struct intel_display_device_info) { 314 GEN3_DISPLAY, 315 I845_COLORS, 316 .cursor_needs_physical = 1, 317 .overlay_needs_physical = 1, 318 }, 319 }; 320 321 static const struct platform_desc i915gm_desc = { 322 PLATFORM(i915gm), 323 PLATFORM_GROUP(mobile), 324 .info = &(const struct intel_display_device_info) { 325 GEN3_DISPLAY, 326 I9XX_COLORS, 327 .cursor_needs_physical = 1, 328 .overlay_needs_physical = 1, 329 .supports_tv = 1, 330 331 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 332 }, 333 }; 334 335 static const struct platform_desc i945g_desc = { 336 PLATFORM(i945g), 337 .info = &(const struct intel_display_device_info) { 338 GEN3_DISPLAY, 339 I845_COLORS, 340 .has_hotplug = 1, 341 .cursor_needs_physical = 1, 342 .overlay_needs_physical = 1, 343 }, 344 }; 345 346 static const struct platform_desc i945gm_desc = { 347 PLATFORM(i915gm), 348 PLATFORM_GROUP(mobile), 349 .info = &(const struct intel_display_device_info) { 350 GEN3_DISPLAY, 351 I9XX_COLORS, 352 .has_hotplug = 1, 353 .cursor_needs_physical = 1, 354 .overlay_needs_physical = 1, 355 .supports_tv = 1, 356 357 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 358 }, 359 }; 360 361 static const struct platform_desc g33_desc = { 362 PLATFORM(g33), 363 .info = &(const struct intel_display_device_info) { 364 GEN3_DISPLAY, 365 I845_COLORS, 366 .has_hotplug = 1, 367 }, 368 }; 369 370 static const struct intel_display_device_info pnv_display = { 371 GEN3_DISPLAY, 372 I9XX_COLORS, 373 .has_hotplug = 1, 374 }; 375 376 static const struct platform_desc pnv_g_desc = { 377 PLATFORM(pineview), 378 .info = &pnv_display, 379 }; 380 381 static const struct platform_desc pnv_m_desc = { 382 PLATFORM(pineview), 383 PLATFORM_GROUP(mobile), 384 .info = &pnv_display, 385 }; 386 387 #define GEN4_DISPLAY \ 388 .has_hotplug = 1, \ 389 .has_gmch = 1, \ 390 I9XX_PIPE_OFFSETS, \ 391 I9XX_CURSOR_OFFSETS, \ 392 I9XX_COLORS, \ 393 \ 394 .__runtime_defaults.ip.ver = 4, \ 395 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 396 .__runtime_defaults.cpu_transcoder_mask = \ 397 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 398 399 static const struct platform_desc i965g_desc = { 400 PLATFORM(i965g), 401 .info = &(const struct intel_display_device_info) { 402 GEN4_DISPLAY, 403 .has_overlay = 1, 404 405 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 406 }, 407 }; 408 409 static const struct platform_desc i965gm_desc = { 410 PLATFORM(i965gm), 411 PLATFORM_GROUP(mobile), 412 .info = &(const struct intel_display_device_info) { 413 GEN4_DISPLAY, 414 .has_overlay = 1, 415 .supports_tv = 1, 416 417 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ 418 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 419 }, 420 }; 421 422 static const struct platform_desc g45_desc = { 423 PLATFORM(g45), 424 PLATFORM_GROUP(g4x), 425 .info = &(const struct intel_display_device_info) { 426 GEN4_DISPLAY, 427 428 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 429 }, 430 }; 431 432 static const struct platform_desc gm45_desc = { 433 PLATFORM(gm45), 434 PLATFORM_GROUP(g4x), 435 PLATFORM_GROUP(mobile), 436 .info = &(const struct intel_display_device_info) { 437 GEN4_DISPLAY, 438 .supports_tv = 1, 439 440 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ 441 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 442 }, 443 }; 444 445 #define ILK_DISPLAY \ 446 .has_hotplug = 1, \ 447 I9XX_PIPE_OFFSETS, \ 448 I9XX_CURSOR_OFFSETS, \ 449 ILK_COLORS, \ 450 \ 451 .__runtime_defaults.ip.ver = 5, \ 452 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 453 .__runtime_defaults.cpu_transcoder_mask = \ 454 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 455 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 456 457 static const struct platform_desc ilk_d_desc = { 458 PLATFORM(ironlake), 459 .info = &(const struct intel_display_device_info) { 460 ILK_DISPLAY, 461 }, 462 }; 463 464 static const struct platform_desc ilk_m_desc = { 465 PLATFORM(ironlake), 466 PLATFORM_GROUP(mobile), 467 .info = &(const struct intel_display_device_info) { 468 ILK_DISPLAY, 469 470 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 471 }, 472 }; 473 474 static const struct intel_display_device_info snb_display = { 475 .has_hotplug = 1, 476 I9XX_PIPE_OFFSETS, 477 I9XX_CURSOR_OFFSETS, 478 ILK_COLORS, 479 480 .__runtime_defaults.ip.ver = 6, 481 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 482 .__runtime_defaults.cpu_transcoder_mask = 483 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 484 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 485 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 486 }; 487 488 static const struct platform_desc snb_d_desc = { 489 PLATFORM(sandybridge), 490 .info = &snb_display, 491 }; 492 493 static const struct platform_desc snb_m_desc = { 494 PLATFORM(sandybridge), 495 PLATFORM_GROUP(mobile), 496 .info = &snb_display, 497 }; 498 499 static const struct intel_display_device_info ivb_display = { 500 .has_hotplug = 1, 501 IVB_PIPE_OFFSETS, 502 IVB_CURSOR_OFFSETS, 503 IVB_COLORS, 504 505 .__runtime_defaults.ip.ver = 7, 506 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 507 .__runtime_defaults.cpu_transcoder_mask = 508 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 509 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 510 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 511 }; 512 513 static const struct platform_desc ivb_d_desc = { 514 PLATFORM(ivybridge), 515 .info = &ivb_display, 516 }; 517 518 static const struct platform_desc ivb_m_desc = { 519 PLATFORM(ivybridge), 520 PLATFORM_GROUP(mobile), 521 .info = &ivb_display, 522 }; 523 524 static const struct platform_desc vlv_desc = { 525 PLATFORM(valleyview), 526 .info = &(const struct intel_display_device_info) { 527 .has_gmch = 1, 528 .has_hotplug = 1, 529 .mmio_offset = VLV_DISPLAY_BASE, 530 I9XX_PIPE_OFFSETS, 531 I9XX_CURSOR_OFFSETS, 532 I9XX_COLORS, 533 534 .__runtime_defaults.ip.ver = 7, 535 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 536 .__runtime_defaults.cpu_transcoder_mask = 537 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 538 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ 539 }, 540 }; 541 542 static const u16 hsw_ult_ids[] = { 543 INTEL_HSW_ULT_GT1_IDS(ID), 544 INTEL_HSW_ULT_GT2_IDS(ID), 545 INTEL_HSW_ULT_GT3_IDS(ID), 546 0 547 }; 548 549 static const u16 hsw_ulx_ids[] = { 550 INTEL_HSW_ULX_GT1_IDS(ID), 551 INTEL_HSW_ULX_GT2_IDS(ID), 552 0 553 }; 554 555 static const struct platform_desc hsw_desc = { 556 PLATFORM(haswell), 557 .subplatforms = (const struct subplatform_desc[]) { 558 /* Special case: Use ult both as group and subplatform. */ 559 { 560 SUBPLATFORM(haswell, ult), 561 SUBPLATFORM_GROUP(haswell, ult), 562 .pciidlist = hsw_ult_ids, 563 }, 564 { 565 SUBPLATFORM(haswell, ulx), 566 SUBPLATFORM_GROUP(haswell, ult), 567 .pciidlist = hsw_ulx_ids, 568 }, 569 {}, 570 }, 571 .info = &(const struct intel_display_device_info) { 572 .has_ddi = 1, 573 .has_dp_mst = 1, 574 .has_fpga_dbg = 1, 575 .has_hotplug = 1, 576 .has_psr = 1, 577 .has_psr_hw_tracking = 1, 578 HSW_PIPE_OFFSETS, 579 IVB_CURSOR_OFFSETS, 580 IVB_COLORS, 581 582 .__runtime_defaults.ip.ver = 7, 583 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 584 .__runtime_defaults.cpu_transcoder_mask = 585 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 586 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 587 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 588 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 589 }, 590 }; 591 592 static const u16 bdw_ult_ids[] = { 593 INTEL_BDW_ULT_GT1_IDS(ID), 594 INTEL_BDW_ULT_GT2_IDS(ID), 595 INTEL_BDW_ULT_GT3_IDS(ID), 596 INTEL_BDW_ULT_RSVD_IDS(ID), 597 0 598 }; 599 600 static const u16 bdw_ulx_ids[] = { 601 INTEL_BDW_ULX_GT1_IDS(ID), 602 INTEL_BDW_ULX_GT2_IDS(ID), 603 INTEL_BDW_ULX_GT3_IDS(ID), 604 INTEL_BDW_ULX_RSVD_IDS(ID), 605 0 606 }; 607 608 static const struct platform_desc bdw_desc = { 609 PLATFORM(broadwell), 610 .subplatforms = (const struct subplatform_desc[]) { 611 /* Special case: Use ult both as group and subplatform. */ 612 { 613 SUBPLATFORM(broadwell, ult), 614 SUBPLATFORM_GROUP(broadwell, ult), 615 .pciidlist = bdw_ult_ids, 616 }, 617 { 618 SUBPLATFORM(broadwell, ulx), 619 SUBPLATFORM_GROUP(broadwell, ult), 620 .pciidlist = bdw_ulx_ids, 621 }, 622 {}, 623 }, 624 .info = &(const struct intel_display_device_info) { 625 .has_ddi = 1, 626 .has_dp_mst = 1, 627 .has_fpga_dbg = 1, 628 .has_hotplug = 1, 629 .has_psr = 1, 630 .has_psr_hw_tracking = 1, 631 HSW_PIPE_OFFSETS, 632 IVB_CURSOR_OFFSETS, 633 IVB_COLORS, 634 635 .__runtime_defaults.ip.ver = 8, 636 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 637 .__runtime_defaults.cpu_transcoder_mask = 638 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 639 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 640 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 641 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 642 }, 643 }; 644 645 static const struct platform_desc chv_desc = { 646 PLATFORM(cherryview), 647 .info = &(const struct intel_display_device_info) { 648 .has_hotplug = 1, 649 .has_gmch = 1, 650 .mmio_offset = VLV_DISPLAY_BASE, 651 CHV_PIPE_OFFSETS, 652 CHV_CURSOR_OFFSETS, 653 CHV_COLORS, 654 655 .__runtime_defaults.ip.ver = 8, 656 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 657 .__runtime_defaults.cpu_transcoder_mask = 658 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 659 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ 660 }, 661 }; 662 663 static const struct intel_display_device_info skl_display = { 664 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ 665 .dbuf.slice_mask = BIT(DBUF_S1), 666 .has_ddi = 1, 667 .has_dp_mst = 1, 668 .has_fpga_dbg = 1, 669 .has_hotplug = 1, 670 .has_ipc = 1, 671 .has_psr = 1, 672 .has_psr_hw_tracking = 1, 673 HSW_PIPE_OFFSETS, 674 IVB_CURSOR_OFFSETS, 675 IVB_COLORS, 676 677 .__runtime_defaults.ip.ver = 9, 678 .__runtime_defaults.has_dmc = 1, 679 .__runtime_defaults.has_hdcp = 1, 680 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 681 .__runtime_defaults.cpu_transcoder_mask = 682 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 683 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 684 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 685 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 686 }; 687 688 static const u16 skl_ult_ids[] = { 689 INTEL_SKL_ULT_GT1_IDS(ID), 690 INTEL_SKL_ULT_GT2_IDS(ID), 691 INTEL_SKL_ULT_GT3_IDS(ID), 692 0 693 }; 694 695 static const u16 skl_ulx_ids[] = { 696 INTEL_SKL_ULX_GT1_IDS(ID), 697 INTEL_SKL_ULX_GT2_IDS(ID), 698 0 699 }; 700 701 static const enum intel_step skl_steppings[] = { 702 [0x6] = STEP_G0, 703 [0x7] = STEP_H0, 704 [0x9] = STEP_J0, 705 [0xA] = STEP_I1, 706 }; 707 708 static const struct platform_desc skl_desc = { 709 PLATFORM(skylake), 710 .subplatforms = (const struct subplatform_desc[]) { 711 { 712 SUBPLATFORM(skylake, ult), 713 .pciidlist = skl_ult_ids, 714 }, 715 { 716 SUBPLATFORM(skylake, ulx), 717 .pciidlist = skl_ulx_ids, 718 }, 719 {}, 720 }, 721 .info = &skl_display, 722 STEP_INFO(skl_steppings), 723 }; 724 725 static const u16 kbl_ult_ids[] = { 726 INTEL_KBL_ULT_GT1_IDS(ID), 727 INTEL_KBL_ULT_GT2_IDS(ID), 728 INTEL_KBL_ULT_GT3_IDS(ID), 729 0 730 }; 731 732 static const u16 kbl_ulx_ids[] = { 733 INTEL_KBL_ULX_GT1_IDS(ID), 734 INTEL_KBL_ULX_GT2_IDS(ID), 735 INTEL_AML_KBL_GT2_IDS(ID), 736 0 737 }; 738 739 static const enum intel_step kbl_steppings[] = { 740 [1] = STEP_B0, 741 [2] = STEP_B0, 742 [3] = STEP_B0, 743 [4] = STEP_C0, 744 [5] = STEP_B1, 745 [6] = STEP_B1, 746 [7] = STEP_C0, 747 }; 748 749 static const struct platform_desc kbl_desc = { 750 PLATFORM(kabylake), 751 .subplatforms = (const struct subplatform_desc[]) { 752 { 753 SUBPLATFORM(kabylake, ult), 754 .pciidlist = kbl_ult_ids, 755 }, 756 { 757 SUBPLATFORM(kabylake, ulx), 758 .pciidlist = kbl_ulx_ids, 759 }, 760 {}, 761 }, 762 .info = &skl_display, 763 STEP_INFO(kbl_steppings), 764 }; 765 766 static const u16 cfl_ult_ids[] = { 767 INTEL_CFL_U_GT2_IDS(ID), 768 INTEL_CFL_U_GT3_IDS(ID), 769 INTEL_WHL_U_GT1_IDS(ID), 770 INTEL_WHL_U_GT2_IDS(ID), 771 INTEL_WHL_U_GT3_IDS(ID), 772 0 773 }; 774 775 static const u16 cfl_ulx_ids[] = { 776 INTEL_AML_CFL_GT2_IDS(ID), 777 0 778 }; 779 780 static const struct platform_desc cfl_desc = { 781 PLATFORM(coffeelake), 782 .subplatforms = (const struct subplatform_desc[]) { 783 { 784 SUBPLATFORM(coffeelake, ult), 785 .pciidlist = cfl_ult_ids, 786 }, 787 { 788 SUBPLATFORM(coffeelake, ulx), 789 .pciidlist = cfl_ulx_ids, 790 }, 791 {}, 792 }, 793 .info = &skl_display, 794 }; 795 796 static const u16 cml_ult_ids[] = { 797 INTEL_CML_U_GT1_IDS(ID), 798 INTEL_CML_U_GT2_IDS(ID), 799 0 800 }; 801 802 static const struct platform_desc cml_desc = { 803 PLATFORM(cometlake), 804 .subplatforms = (const struct subplatform_desc[]) { 805 { 806 SUBPLATFORM(cometlake, ult), 807 .pciidlist = cml_ult_ids, 808 }, 809 {}, 810 }, 811 .info = &skl_display, 812 }; 813 814 #define GEN9_LP_DISPLAY \ 815 .dbuf.slice_mask = BIT(DBUF_S1), \ 816 .has_dp_mst = 1, \ 817 .has_ddi = 1, \ 818 .has_fpga_dbg = 1, \ 819 .has_hotplug = 1, \ 820 .has_ipc = 1, \ 821 .has_psr = 1, \ 822 .has_psr_hw_tracking = 1, \ 823 HSW_PIPE_OFFSETS, \ 824 IVB_CURSOR_OFFSETS, \ 825 IVB_COLORS, \ 826 \ 827 .__runtime_defaults.has_dmc = 1, \ 828 .__runtime_defaults.has_hdcp = 1, \ 829 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 830 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 831 .__runtime_defaults.cpu_transcoder_mask = \ 832 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 833 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 834 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 835 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) 836 837 static const enum intel_step bxt_steppings[] = { 838 [0xA] = STEP_C0, 839 [0xB] = STEP_C0, 840 [0xC] = STEP_D0, 841 [0xD] = STEP_E0, 842 }; 843 844 static const struct platform_desc bxt_desc = { 845 PLATFORM(broxton), 846 .info = &(const struct intel_display_device_info) { 847 GEN9_LP_DISPLAY, 848 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 849 850 .__runtime_defaults.ip.ver = 9, 851 }, 852 STEP_INFO(bxt_steppings), 853 }; 854 855 static const enum intel_step glk_steppings[] = { 856 [3] = STEP_B0, 857 }; 858 859 static const struct platform_desc glk_desc = { 860 PLATFORM(geminilake), 861 .info = &(const struct intel_display_device_info) { 862 GEN9_LP_DISPLAY, 863 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 864 GLK_COLORS, 865 866 .__runtime_defaults.ip.ver = 10, 867 }, 868 STEP_INFO(glk_steppings), 869 }; 870 871 #define ICL_DISPLAY \ 872 .abox_mask = BIT(0), \ 873 .dbuf.size = 2048, \ 874 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 875 .has_ddi = 1, \ 876 .has_dp_mst = 1, \ 877 .has_fpga_dbg = 1, \ 878 .has_hotplug = 1, \ 879 .has_ipc = 1, \ 880 .has_psr = 1, \ 881 .has_psr_hw_tracking = 1, \ 882 .pipe_offsets = { \ 883 [TRANSCODER_A] = PIPE_A_OFFSET, \ 884 [TRANSCODER_B] = PIPE_B_OFFSET, \ 885 [TRANSCODER_C] = PIPE_C_OFFSET, \ 886 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 887 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 888 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 889 }, \ 890 .trans_offsets = { \ 891 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 892 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 893 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 894 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 895 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 896 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 897 }, \ 898 IVB_CURSOR_OFFSETS, \ 899 ICL_COLORS, \ 900 \ 901 .__runtime_defaults.ip.ver = 11, \ 902 .__runtime_defaults.has_dmc = 1, \ 903 .__runtime_defaults.has_dsc = 1, \ 904 .__runtime_defaults.has_hdcp = 1, \ 905 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 906 .__runtime_defaults.cpu_transcoder_mask = \ 907 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 908 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 909 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 910 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 911 912 static const u16 icl_port_f_ids[] = { 913 INTEL_ICL_PORT_F_IDS(ID), 914 0 915 }; 916 917 static const enum intel_step icl_steppings[] = { 918 [7] = STEP_D0, 919 }; 920 921 static const struct platform_desc icl_desc = { 922 PLATFORM(icelake), 923 .subplatforms = (const struct subplatform_desc[]) { 924 { 925 SUBPLATFORM(icelake, port_f), 926 .pciidlist = icl_port_f_ids, 927 }, 928 {}, 929 }, 930 .info = &(const struct intel_display_device_info) { 931 ICL_DISPLAY, 932 933 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 934 }, 935 STEP_INFO(icl_steppings), 936 }; 937 938 static const struct intel_display_device_info jsl_ehl_display = { 939 ICL_DISPLAY, 940 941 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), 942 }; 943 944 static const enum intel_step jsl_ehl_steppings[] = { 945 [0] = STEP_A0, 946 [1] = STEP_B0, 947 }; 948 949 static const struct platform_desc jsl_desc = { 950 PLATFORM(jasperlake), 951 .info = &jsl_ehl_display, 952 STEP_INFO(jsl_ehl_steppings), 953 }; 954 955 static const struct platform_desc ehl_desc = { 956 PLATFORM(elkhartlake), 957 .info = &jsl_ehl_display, 958 STEP_INFO(jsl_ehl_steppings), 959 }; 960 961 #define XE_D_DISPLAY \ 962 .abox_mask = GENMASK(2, 1), \ 963 .dbuf.size = 2048, \ 964 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 965 .has_ddi = 1, \ 966 .has_dp_mst = 1, \ 967 .has_dsb = 1, \ 968 .has_fpga_dbg = 1, \ 969 .has_hotplug = 1, \ 970 .has_ipc = 1, \ 971 .has_psr = 1, \ 972 .has_psr_hw_tracking = 1, \ 973 .pipe_offsets = { \ 974 [TRANSCODER_A] = PIPE_A_OFFSET, \ 975 [TRANSCODER_B] = PIPE_B_OFFSET, \ 976 [TRANSCODER_C] = PIPE_C_OFFSET, \ 977 [TRANSCODER_D] = PIPE_D_OFFSET, \ 978 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 979 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 980 }, \ 981 .trans_offsets = { \ 982 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 983 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 984 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 985 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 986 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 987 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 988 }, \ 989 TGL_CURSOR_OFFSETS, \ 990 ICL_COLORS, \ 991 \ 992 .__runtime_defaults.ip.ver = 12, \ 993 .__runtime_defaults.has_dmc = 1, \ 994 .__runtime_defaults.has_dsc = 1, \ 995 .__runtime_defaults.has_hdcp = 1, \ 996 .__runtime_defaults.pipe_mask = \ 997 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 998 .__runtime_defaults.cpu_transcoder_mask = \ 999 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 1000 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 1001 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 1002 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 1003 1004 static const u16 tgl_uy_ids[] = { 1005 INTEL_TGL_GT2_IDS(ID), 1006 0 1007 }; 1008 1009 static const enum intel_step tgl_steppings[] = { 1010 [0] = STEP_B0, 1011 [1] = STEP_D0, 1012 }; 1013 1014 static const enum intel_step tgl_uy_steppings[] = { 1015 [0] = STEP_A0, 1016 [1] = STEP_C0, 1017 [2] = STEP_C0, 1018 [3] = STEP_D0, 1019 }; 1020 1021 static const struct platform_desc tgl_desc = { 1022 PLATFORM(tigerlake), 1023 .subplatforms = (const struct subplatform_desc[]) { 1024 { 1025 SUBPLATFORM(tigerlake, uy), 1026 .pciidlist = tgl_uy_ids, 1027 STEP_INFO(tgl_uy_steppings), 1028 }, 1029 {}, 1030 }, 1031 .info = &(const struct intel_display_device_info) { 1032 XE_D_DISPLAY, 1033 1034 /* 1035 * FIXME DDI C/combo PHY C missing due to combo PHY 1036 * code making a mess on SKUs where the PHY is missing. 1037 */ 1038 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1039 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), 1040 }, 1041 STEP_INFO(tgl_steppings), 1042 }; 1043 1044 static const enum intel_step dg1_steppings[] = { 1045 [0] = STEP_A0, 1046 [1] = STEP_B0, 1047 }; 1048 1049 static const struct platform_desc dg1_desc = { 1050 PLATFORM(dg1), 1051 PLATFORM_GROUP(dgfx), 1052 .info = &(const struct intel_display_device_info) { 1053 XE_D_DISPLAY, 1054 1055 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1056 BIT(PORT_TC1) | BIT(PORT_TC2), 1057 }, 1058 STEP_INFO(dg1_steppings), 1059 }; 1060 1061 static const enum intel_step rkl_steppings[] = { 1062 [0] = STEP_A0, 1063 [1] = STEP_B0, 1064 [4] = STEP_C0, 1065 }; 1066 1067 static const struct platform_desc rkl_desc = { 1068 PLATFORM(rocketlake), 1069 .info = &(const struct intel_display_device_info) { 1070 XE_D_DISPLAY, 1071 .abox_mask = BIT(0), 1072 .has_hti = 1, 1073 .has_psr_hw_tracking = 0, 1074 1075 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1076 .__runtime_defaults.cpu_transcoder_mask = 1077 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 1078 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1079 BIT(PORT_TC1) | BIT(PORT_TC2), 1080 }, 1081 STEP_INFO(rkl_steppings), 1082 }; 1083 1084 static const u16 adls_rpls_ids[] = { 1085 INTEL_RPLS_IDS(ID), 1086 0 1087 }; 1088 1089 static const enum intel_step adl_s_steppings[] = { 1090 [0x0] = STEP_A0, 1091 [0x1] = STEP_A2, 1092 [0x4] = STEP_B0, 1093 [0x8] = STEP_B0, 1094 [0xC] = STEP_C0, 1095 }; 1096 1097 static const enum intel_step adl_s_rpl_s_steppings[] = { 1098 [0x4] = STEP_D0, 1099 [0xC] = STEP_C0, 1100 }; 1101 1102 static const struct platform_desc adl_s_desc = { 1103 PLATFORM(alderlake_s), 1104 .subplatforms = (const struct subplatform_desc[]) { 1105 { 1106 SUBPLATFORM(alderlake_s, raptorlake_s), 1107 .pciidlist = adls_rpls_ids, 1108 STEP_INFO(adl_s_rpl_s_steppings), 1109 }, 1110 {}, 1111 }, 1112 .info = &(const struct intel_display_device_info) { 1113 XE_D_DISPLAY, 1114 .has_hti = 1, 1115 .has_psr_hw_tracking = 0, 1116 1117 .__runtime_defaults.port_mask = BIT(PORT_A) | 1118 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1119 }, 1120 STEP_INFO(adl_s_steppings), 1121 }; 1122 1123 #define XE_LPD_FEATURES \ 1124 .abox_mask = GENMASK(1, 0), \ 1125 .color = { \ 1126 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 1127 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 1128 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 1129 }, \ 1130 .dbuf.size = 4096, \ 1131 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 1132 BIT(DBUF_S4), \ 1133 .has_ddi = 1, \ 1134 .has_dp_mst = 1, \ 1135 .has_dsb = 1, \ 1136 .has_fpga_dbg = 1, \ 1137 .has_hotplug = 1, \ 1138 .has_ipc = 1, \ 1139 .has_psr = 1, \ 1140 .pipe_offsets = { \ 1141 [TRANSCODER_A] = PIPE_A_OFFSET, \ 1142 [TRANSCODER_B] = PIPE_B_OFFSET, \ 1143 [TRANSCODER_C] = PIPE_C_OFFSET, \ 1144 [TRANSCODER_D] = PIPE_D_OFFSET, \ 1145 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 1146 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 1147 }, \ 1148 .trans_offsets = { \ 1149 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 1150 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 1151 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 1152 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 1153 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 1154 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 1155 }, \ 1156 TGL_CURSOR_OFFSETS, \ 1157 \ 1158 .__runtime_defaults.ip.ver = 13, \ 1159 .__runtime_defaults.has_dmc = 1, \ 1160 .__runtime_defaults.has_dsc = 1, \ 1161 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 1162 .__runtime_defaults.has_hdcp = 1, \ 1163 .__runtime_defaults.pipe_mask = \ 1164 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D) 1165 1166 static const struct intel_display_device_info xe_lpd_display = { 1167 XE_LPD_FEATURES, 1168 .has_cdclk_crawl = 1, 1169 .has_psr_hw_tracking = 0, 1170 1171 .__runtime_defaults.cpu_transcoder_mask = 1172 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1173 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 1174 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 1175 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 1176 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1177 }; 1178 1179 static const u16 adlp_adln_ids[] = { 1180 INTEL_ADLN_IDS(ID), 1181 0 1182 }; 1183 1184 static const u16 adlp_rplu_ids[] = { 1185 INTEL_RPLU_IDS(ID), 1186 0 1187 }; 1188 1189 static const u16 adlp_rplp_ids[] = { 1190 INTEL_RPLP_IDS(ID), 1191 0 1192 }; 1193 1194 static const enum intel_step adl_p_steppings[] = { 1195 [0x0] = STEP_A0, 1196 [0x4] = STEP_B0, 1197 [0x8] = STEP_C0, 1198 [0xC] = STEP_D0, 1199 }; 1200 1201 static const enum intel_step adl_p_adl_n_steppings[] = { 1202 [0x0] = STEP_D0, 1203 }; 1204 1205 static const enum intel_step adl_p_rpl_pu_steppings[] = { 1206 [0x4] = STEP_E0, 1207 }; 1208 1209 static const struct platform_desc adl_p_desc = { 1210 PLATFORM(alderlake_p), 1211 .subplatforms = (const struct subplatform_desc[]) { 1212 { 1213 SUBPLATFORM(alderlake_p, alderlake_n), 1214 .pciidlist = adlp_adln_ids, 1215 STEP_INFO(adl_p_adl_n_steppings), 1216 }, 1217 { 1218 SUBPLATFORM(alderlake_p, raptorlake_p), 1219 .pciidlist = adlp_rplp_ids, 1220 STEP_INFO(adl_p_rpl_pu_steppings), 1221 }, 1222 { 1223 SUBPLATFORM(alderlake_p, raptorlake_u), 1224 .pciidlist = adlp_rplu_ids, 1225 STEP_INFO(adl_p_rpl_pu_steppings), 1226 }, 1227 {}, 1228 }, 1229 .info = &xe_lpd_display, 1230 STEP_INFO(adl_p_steppings), 1231 }; 1232 1233 static const struct intel_display_device_info xe_hpd_display = { 1234 XE_LPD_FEATURES, 1235 .has_cdclk_squash = 1, 1236 1237 .__runtime_defaults.cpu_transcoder_mask = 1238 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1239 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1240 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) | 1241 BIT(PORT_TC1), 1242 }; 1243 1244 static const u16 dg2_g10_ids[] = { 1245 INTEL_DG2_G10_IDS(ID), 1246 0 1247 }; 1248 1249 static const u16 dg2_g11_ids[] = { 1250 INTEL_DG2_G11_IDS(ID), 1251 0 1252 }; 1253 1254 static const u16 dg2_g12_ids[] = { 1255 INTEL_DG2_G12_IDS(ID), 1256 0 1257 }; 1258 1259 static const enum intel_step dg2_g10_steppings[] = { 1260 [0x0] = STEP_A0, 1261 [0x1] = STEP_A0, 1262 [0x4] = STEP_B0, 1263 [0x8] = STEP_C0, 1264 }; 1265 1266 static const enum intel_step dg2_g11_steppings[] = { 1267 [0x0] = STEP_B0, 1268 [0x4] = STEP_C0, 1269 [0x5] = STEP_C0, 1270 }; 1271 1272 static const enum intel_step dg2_g12_steppings[] = { 1273 [0x0] = STEP_C0, 1274 [0x1] = STEP_C0, 1275 }; 1276 1277 static const struct platform_desc dg2_desc = { 1278 PLATFORM(dg2), 1279 PLATFORM_GROUP(dgfx), 1280 .subplatforms = (const struct subplatform_desc[]) { 1281 { 1282 SUBPLATFORM(dg2, g10), 1283 .pciidlist = dg2_g10_ids, 1284 STEP_INFO(dg2_g10_steppings), 1285 }, 1286 { 1287 SUBPLATFORM(dg2, g11), 1288 .pciidlist = dg2_g11_ids, 1289 STEP_INFO(dg2_g11_steppings), 1290 }, 1291 { 1292 SUBPLATFORM(dg2, g12), 1293 .pciidlist = dg2_g12_ids, 1294 STEP_INFO(dg2_g12_steppings), 1295 }, 1296 {}, 1297 }, 1298 .info = &xe_hpd_display, 1299 }; 1300 1301 #define XE_LPDP_FEATURES \ 1302 .abox_mask = GENMASK(1, 0), \ 1303 .color = { \ 1304 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 1305 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 1306 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 1307 }, \ 1308 .dbuf.size = 4096, \ 1309 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 1310 BIT(DBUF_S4), \ 1311 .has_cdclk_crawl = 1, \ 1312 .has_cdclk_squash = 1, \ 1313 .has_ddi = 1, \ 1314 .has_dp_mst = 1, \ 1315 .has_dsb = 1, \ 1316 .has_fpga_dbg = 1, \ 1317 .has_hotplug = 1, \ 1318 .has_ipc = 1, \ 1319 .has_psr = 1, \ 1320 .pipe_offsets = { \ 1321 [TRANSCODER_A] = PIPE_A_OFFSET, \ 1322 [TRANSCODER_B] = PIPE_B_OFFSET, \ 1323 [TRANSCODER_C] = PIPE_C_OFFSET, \ 1324 [TRANSCODER_D] = PIPE_D_OFFSET, \ 1325 }, \ 1326 .trans_offsets = { \ 1327 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 1328 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 1329 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 1330 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 1331 }, \ 1332 TGL_CURSOR_OFFSETS, \ 1333 \ 1334 .__runtime_defaults.cpu_transcoder_mask = \ 1335 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 1336 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ 1337 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \ 1338 .__runtime_defaults.has_dmc = 1, \ 1339 .__runtime_defaults.has_dsc = 1, \ 1340 .__runtime_defaults.has_hdcp = 1, \ 1341 .__runtime_defaults.pipe_mask = \ 1342 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 1343 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \ 1344 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) 1345 1346 static const struct intel_display_device_info xe_lpdp_display = { 1347 XE_LPDP_FEATURES, 1348 }; 1349 1350 static const struct intel_display_device_info xe2_lpd_display = { 1351 XE_LPDP_FEATURES, 1352 1353 .__runtime_defaults.fbc_mask = 1354 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | 1355 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), 1356 .__runtime_defaults.has_dbuf_overlap_detection = true, 1357 .trans_offsets = { 1358 [TRANSCODER_A] = TRANSCODER_A_OFFSET, 1359 [TRANSCODER_B] = TRANSCODER_B_OFFSET, 1360 [TRANSCODER_C] = TRANSCODER_C_OFFSET, 1361 [TRANSCODER_D] = TRANSCODER_D_OFFSET, 1362 [TRANSCODER_CMTG0] = TRANSCODER_CMTG0_OFFSET, 1363 [TRANSCODER_CMTG1] = TRANSCODER_CMTG1_OFFSET, 1364 }, 1365 .__runtime_defaults.cpu_transcoder_mask = 1366 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1367 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 1368 BIT(TRANSCODER_CMTG0) | BIT(TRANSCODER_CMTG1), 1369 }; 1370 1371 static const struct intel_display_device_info wcl_display = { 1372 XE_LPDP_FEATURES, 1373 1374 .__runtime_defaults.cpu_transcoder_mask = 1375 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 1376 .__runtime_defaults.pipe_mask = 1377 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1378 .__runtime_defaults.fbc_mask = 1379 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | BIT(INTEL_FBC_C), 1380 .__runtime_defaults.port_mask = 1381 BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2), 1382 }; 1383 1384 static const struct intel_display_device_info xe2_hpd_display = { 1385 XE_LPDP_FEATURES, 1386 .__runtime_defaults.port_mask = BIT(PORT_A) | 1387 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1388 }; 1389 1390 static const u16 mtl_u_ids[] = { 1391 INTEL_MTL_U_IDS(ID), 1392 INTEL_ARL_U_IDS(ID), 1393 0 1394 }; 1395 1396 /* 1397 * Do not initialize the .info member of the platform desc for GMD ID based 1398 * platforms. Their display will be probed automatically based on the IP version 1399 * reported by the hardware. 1400 */ 1401 static const struct platform_desc mtl_desc = { 1402 PLATFORM(meteorlake), 1403 .subplatforms = (const struct subplatform_desc[]) { 1404 { 1405 SUBPLATFORM(meteorlake, u), 1406 .pciidlist = mtl_u_ids, 1407 }, 1408 {}, 1409 } 1410 }; 1411 1412 static const struct platform_desc lnl_desc = { 1413 PLATFORM(lunarlake), 1414 }; 1415 1416 static const struct platform_desc bmg_desc = { 1417 PLATFORM(battlemage), 1418 PLATFORM_GROUP(dgfx), 1419 }; 1420 1421 static const u16 wcl_ids[] = { 1422 INTEL_WCL_IDS(ID), 1423 0 1424 }; 1425 1426 static const struct platform_desc ptl_desc = { 1427 PLATFORM(pantherlake), 1428 .subplatforms = (const struct subplatform_desc[]) { 1429 { 1430 SUBPLATFORM(pantherlake, wildcatlake), 1431 .pciidlist = wcl_ids, 1432 }, 1433 {}, 1434 } 1435 }; 1436 1437 static const struct platform_desc nvl_desc = { 1438 PLATFORM(novalake), 1439 }; 1440 1441 __diag_pop(); 1442 1443 /* 1444 * Separate detection for no display cases to keep the display id array simple. 1445 * 1446 * IVB Q requires subvendor and subdevice matching to differentiate from IVB D 1447 * GT2 server. 1448 */ 1449 static bool has_no_display(struct pci_dev *pdev) 1450 { 1451 static const struct pci_device_id ids[] = { 1452 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0), 1453 {} 1454 }; 1455 1456 return pci_match_id(ids, pdev); 1457 } 1458 1459 #define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) } 1460 1461 static const struct { 1462 u32 devid; 1463 const struct platform_desc *desc; 1464 } intel_display_ids[] = { 1465 INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_desc), 1466 INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_desc), 1467 INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_desc), 1468 INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_desc), 1469 INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_desc), 1470 INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_desc), 1471 INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_desc), 1472 INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_desc), 1473 INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_desc), 1474 INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_desc), 1475 INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc), 1476 INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc), 1477 INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc), 1478 INTEL_PNV_G_IDS(INTEL_DISPLAY_DEVICE, &pnv_g_desc), 1479 INTEL_PNV_M_IDS(INTEL_DISPLAY_DEVICE, &pnv_m_desc), 1480 INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc), 1481 INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc), 1482 INTEL_SNB_D_IDS(INTEL_DISPLAY_DEVICE, &snb_d_desc), 1483 INTEL_SNB_M_IDS(INTEL_DISPLAY_DEVICE, &snb_m_desc), 1484 INTEL_IVB_D_IDS(INTEL_DISPLAY_DEVICE, &ivb_d_desc), 1485 INTEL_IVB_M_IDS(INTEL_DISPLAY_DEVICE, &ivb_m_desc), 1486 INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc), 1487 INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc), 1488 INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc), 1489 INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_desc), 1490 INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_desc), 1491 INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_desc), 1492 INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_desc), 1493 INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &kbl_desc), 1494 INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), 1495 INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), 1496 INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &cml_desc), 1497 INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_desc), 1498 INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &ehl_desc), 1499 INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_desc), 1500 INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_desc), 1501 INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_desc), 1502 INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_desc), 1503 INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), 1504 INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), 1505 INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1506 INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1507 INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1508 INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), 1509 INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), 1510 INTEL_ARL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), 1511 INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), 1512 INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), 1513 INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), 1514 INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1515 INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1516 INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc), 1517 INTEL_NVLP_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc), 1518 }; 1519 1520 static const struct { 1521 u16 ver; 1522 u16 rel; 1523 const struct intel_display_device_info *display; 1524 } gmdid_display_map[] = { 1525 { 14, 0, &xe_lpdp_display }, 1526 { 14, 1, &xe2_hpd_display }, 1527 { 20, 0, &xe2_lpd_display }, 1528 { 30, 0, &xe2_lpd_display }, 1529 { 30, 2, &wcl_display }, 1530 { 35, 0, &xe2_lpd_display }, 1531 }; 1532 1533 static const struct intel_display_device_info * 1534 probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *ip_ver) 1535 { 1536 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 1537 struct intel_display_ip_ver gmd_id; 1538 void __iomem *addr; 1539 u32 val; 1540 int i; 1541 1542 addr = pci_iomap_range(pdev, 0, intel_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 1543 if (!addr) { 1544 drm_err(display->drm, 1545 "Cannot map MMIO BAR to read display GMD_ID\n"); 1546 return NULL; 1547 } 1548 1549 val = ioread32(addr); 1550 pci_iounmap(pdev, addr); 1551 1552 if (val == 0) { 1553 drm_dbg_kms(display->drm, "Device doesn't have display\n"); 1554 return NULL; 1555 } 1556 1557 gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val); 1558 gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val); 1559 gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val); 1560 1561 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { 1562 if (gmd_id.ver == gmdid_display_map[i].ver && 1563 gmd_id.rel == gmdid_display_map[i].rel) { 1564 *ip_ver = gmd_id; 1565 return gmdid_display_map[i].display; 1566 } 1567 } 1568 1569 drm_err(display->drm, 1570 "Unrecognized display IP version %d.%02d; disabling display.\n", 1571 gmd_id.ver, gmd_id.rel); 1572 return NULL; 1573 } 1574 1575 static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) 1576 { 1577 int i; 1578 1579 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { 1580 if (intel_display_ids[i].devid == pdev->device) 1581 return intel_display_ids[i].desc; 1582 } 1583 1584 return NULL; 1585 } 1586 1587 static const struct subplatform_desc * 1588 find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc) 1589 { 1590 const struct subplatform_desc *sp; 1591 const u16 *id; 1592 1593 for (sp = desc->subplatforms; sp && sp->pciidlist; sp++) 1594 for (id = sp->pciidlist; *id; id++) 1595 if (*id == pdev->device) 1596 return sp; 1597 1598 return NULL; 1599 } 1600 1601 static enum intel_step get_pre_gmdid_step(struct intel_display *display, 1602 const struct stepping_desc *main, 1603 const struct stepping_desc *sub) 1604 { 1605 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 1606 const enum intel_step *map = main->map; 1607 int size = main->size; 1608 int revision = pdev->revision; 1609 enum intel_step step; 1610 1611 /* subplatform stepping info trumps main platform info */ 1612 if (sub && sub->map && sub->size) { 1613 map = sub->map; 1614 size = sub->size; 1615 } 1616 1617 /* not all platforms define steppings, and it's fine */ 1618 if (!map || !size) 1619 return STEP_NONE; 1620 1621 if (revision < size && map[revision] != STEP_NONE) { 1622 step = map[revision]; 1623 } else { 1624 drm_warn(display->drm, "Unknown revision 0x%02x\n", revision); 1625 1626 /* 1627 * If we hit a gap in the revision to step map, use the information 1628 * for the next revision. 1629 * 1630 * This may be wrong in all sorts of ways, especially if the 1631 * steppings in the array are not monotonically increasing, but 1632 * it's better than defaulting to 0. 1633 */ 1634 while (revision < size && map[revision] == STEP_NONE) 1635 revision++; 1636 1637 if (revision < size) { 1638 drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n", 1639 revision); 1640 step = map[revision]; 1641 } else { 1642 drm_dbg_kms(display->drm, "Using future display stepping\n"); 1643 step = STEP_FUTURE; 1644 } 1645 } 1646 1647 drm_WARN_ON(display->drm, step == STEP_NONE); 1648 1649 return step; 1650 } 1651 1652 /* Size of the entire bitmap, not the number of platforms */ 1653 static unsigned int display_platforms_num_bits(void) 1654 { 1655 return sizeof(((struct intel_display_platforms *)0)->bitmap) * BITS_PER_BYTE; 1656 } 1657 1658 /* Number of platform bits set */ 1659 static unsigned int display_platforms_weight(const struct intel_display_platforms *p) 1660 { 1661 return bitmap_weight(p->bitmap, display_platforms_num_bits()); 1662 } 1663 1664 /* Merge the subplatform information from src to dst */ 1665 static void display_platforms_or(struct intel_display_platforms *dst, 1666 const struct intel_display_platforms *src) 1667 { 1668 bitmap_or(dst->bitmap, dst->bitmap, src->bitmap, display_platforms_num_bits()); 1669 } 1670 1671 #define __STEP_NAME(name) [STEP_##name] = #name, 1672 1673 static void initialize_step(struct intel_display *display, enum intel_step step) 1674 { 1675 static const char step_names[][3] = { 1676 STEP_NAME_LIST(__STEP_NAME) 1677 }; 1678 1679 DISPLAY_RUNTIME_INFO(display)->step = step; 1680 1681 /* Step name will remain an empty string if not applicable */ 1682 if (step >= 0 && step < ARRAY_SIZE(step_names)) 1683 strscpy(DISPLAY_RUNTIME_INFO(display)->step_name, step_names[step]); 1684 } 1685 1686 #undef __STEP_NAME 1687 1688 static const char *step_name(const struct intel_display_runtime_info *runtime) 1689 { 1690 return strlen(runtime->step_name) ? runtime->step_name : "N/A"; 1691 } 1692 1693 struct intel_display *intel_display_device_probe(struct pci_dev *pdev, 1694 const struct intel_display_parent_interface *parent) 1695 { 1696 struct intel_display *display; 1697 const struct intel_display_device_info *info; 1698 struct intel_display_ip_ver ip_ver = {}; 1699 const struct platform_desc *desc; 1700 const struct subplatform_desc *subdesc; 1701 enum intel_step step; 1702 1703 display = kzalloc_obj(*display); 1704 if (!display) 1705 return ERR_PTR(-ENOMEM); 1706 1707 /* Add drm device backpointer as early as possible. */ 1708 display->drm = pci_get_drvdata(pdev); 1709 1710 display->parent = parent; 1711 1712 intel_display_params_copy(&display->params); 1713 1714 if (has_no_display(pdev)) { 1715 drm_dbg_kms(display->drm, "Device doesn't have display\n"); 1716 goto no_display; 1717 } 1718 1719 desc = find_platform_desc(pdev); 1720 if (!desc) { 1721 drm_dbg_kms(display->drm, 1722 "Unknown device ID %04x; disabling display.\n", 1723 pdev->device); 1724 goto no_display; 1725 } 1726 1727 info = desc->info; 1728 if (!info) 1729 info = probe_gmdid_display(display, &ip_ver); 1730 if (!info) 1731 goto no_display; 1732 1733 DISPLAY_INFO(display) = info; 1734 1735 memcpy(DISPLAY_RUNTIME_INFO(display), 1736 &DISPLAY_INFO(display)->__runtime_defaults, 1737 sizeof(*DISPLAY_RUNTIME_INFO(display))); 1738 1739 drm_WARN_ON(display->drm, !desc->name || 1740 !display_platforms_weight(&desc->platforms)); 1741 1742 display->platform = desc->platforms; 1743 1744 subdesc = find_subplatform_desc(pdev, desc); 1745 if (subdesc) { 1746 drm_WARN_ON(display->drm, !subdesc->name || 1747 !display_platforms_weight(&subdesc->platforms)); 1748 1749 display_platforms_or(&display->platform, &subdesc->platforms); 1750 1751 /* Ensure platform and subplatform are distinct */ 1752 drm_WARN_ON(display->drm, 1753 display_platforms_weight(&display->platform) != 1754 display_platforms_weight(&desc->platforms) + 1755 display_platforms_weight(&subdesc->platforms)); 1756 } 1757 1758 if (ip_ver.ver || ip_ver.rel || ip_ver.step) { 1759 DISPLAY_RUNTIME_INFO(display)->ip = ip_ver; 1760 step = STEP_A0 + ip_ver.step; 1761 if (step > STEP_FUTURE) { 1762 drm_dbg_kms(display->drm, "Using future display stepping\n"); 1763 step = STEP_FUTURE; 1764 } 1765 } else { 1766 step = get_pre_gmdid_step(display, &desc->step_info, 1767 subdesc ? &subdesc->step_info : NULL); 1768 } 1769 1770 initialize_step(display, step); 1771 1772 drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n", 1773 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", 1774 pdev->device, display->platform.dgfx ? "discrete" : "integrated", 1775 DISPLAY_RUNTIME_INFO(display)->ip.ver, 1776 DISPLAY_RUNTIME_INFO(display)->ip.rel, 1777 step_name(DISPLAY_RUNTIME_INFO(display))); 1778 1779 return display; 1780 1781 no_display: 1782 DISPLAY_INFO(display) = &no_display; 1783 1784 return display; 1785 } 1786 1787 void intel_display_device_remove(struct intel_display *display) 1788 { 1789 if (!display) 1790 return; 1791 1792 intel_display_params_free(&display->params); 1793 kfree(display); 1794 } 1795 1796 static void __intel_display_device_info_runtime_init(struct intel_display *display) 1797 { 1798 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display); 1799 enum pipe pipe; 1800 1801 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); 1802 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); 1803 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); 1804 1805 /* This covers both ULT and ULX */ 1806 if (display->platform.haswell_ult || display->platform.broadwell_ult) 1807 display_runtime->port_mask &= ~BIT(PORT_D); 1808 1809 if (display->platform.icelake_port_f) 1810 display_runtime->port_mask |= BIT(PORT_F); 1811 1812 /* Wa_14011765242: adl-s A0,A1 */ 1813 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011765242)) 1814 for_each_pipe(display, pipe) 1815 display_runtime->num_scalers[pipe] = 0; 1816 else if (DISPLAY_VER(display) >= 11) { 1817 for_each_pipe(display, pipe) 1818 display_runtime->num_scalers[pipe] = 2; 1819 } else if (DISPLAY_VER(display) >= 9) { 1820 display_runtime->num_scalers[PIPE_A] = 2; 1821 display_runtime->num_scalers[PIPE_B] = 2; 1822 display_runtime->num_scalers[PIPE_C] = 1; 1823 } 1824 1825 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 1826 for_each_pipe(display, pipe) 1827 display_runtime->num_sprites[pipe] = 4; 1828 else if (DISPLAY_VER(display) >= 11) 1829 for_each_pipe(display, pipe) 1830 display_runtime->num_sprites[pipe] = 6; 1831 else if (DISPLAY_VER(display) == 10) 1832 for_each_pipe(display, pipe) 1833 display_runtime->num_sprites[pipe] = 3; 1834 else if (display->platform.broxton) { 1835 /* 1836 * Skylake and Broxton currently don't expose the topmost plane as its 1837 * use is exclusive with the legacy cursor and we only want to expose 1838 * one of those, not both. Until we can safely expose the topmost plane 1839 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 1840 * we don't expose the topmost plane at all to prevent ABI breakage 1841 * down the line. 1842 */ 1843 1844 display_runtime->num_sprites[PIPE_A] = 2; 1845 display_runtime->num_sprites[PIPE_B] = 2; 1846 display_runtime->num_sprites[PIPE_C] = 1; 1847 } else if (display->platform.valleyview || display->platform.cherryview) { 1848 for_each_pipe(display, pipe) 1849 display_runtime->num_sprites[pipe] = 2; 1850 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { 1851 for_each_pipe(display, pipe) 1852 display_runtime->num_sprites[pipe] = 1; 1853 } 1854 1855 if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) && 1856 !(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) { 1857 drm_info(display->drm, "Display not present, disabling\n"); 1858 goto display_fused_off; 1859 } 1860 1861 if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(display)) { 1862 u32 fuse_strap = intel_de_read(display, FUSE_STRAP); 1863 u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP); 1864 1865 /* 1866 * SFUSE_STRAP is supposed to have a bit signalling the display 1867 * is fused off. Unfortunately it seems that, at least in 1868 * certain cases, fused off display means that PCH display 1869 * reads don't land anywhere. In that case, we read 0s. 1870 * 1871 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 1872 * should be set when taking over after the firmware. 1873 */ 1874 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 1875 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 1876 (HAS_PCH_CPT(display) && 1877 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 1878 drm_info(display->drm, 1879 "Display fused off, disabling\n"); 1880 goto display_fused_off; 1881 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 1882 drm_info(display->drm, "PipeC fused off\n"); 1883 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1884 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1885 } 1886 } else if (DISPLAY_VER(display) >= 9) { 1887 u32 dfsm = intel_de_read(display, SKL_DFSM); 1888 1889 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 1890 display_runtime->pipe_mask &= ~BIT(PIPE_A); 1891 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 1892 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 1893 } 1894 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 1895 display_runtime->pipe_mask &= ~BIT(PIPE_B); 1896 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 1897 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); 1898 } 1899 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 1900 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1901 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1902 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); 1903 } 1904 1905 if (DISPLAY_VER(display) >= 12 && 1906 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1907 display_runtime->pipe_mask &= ~BIT(PIPE_D); 1908 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 1909 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); 1910 } 1911 1912 if (!display_runtime->pipe_mask) 1913 goto display_fused_off; 1914 1915 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1916 display_runtime->has_hdcp = 0; 1917 1918 if (display->platform.dg2 || DISPLAY_VER(display) < 13) { 1919 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1920 display_runtime->fbc_mask = 0; 1921 } 1922 1923 if (DISPLAY_VER(display) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1924 display_runtime->has_dmc = 0; 1925 1926 if (IS_DISPLAY_VER(display, 10, 12) && 1927 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 1928 display_runtime->has_dsc = 0; 1929 1930 if (DISPLAY_VER(display) >= 20 && 1931 (dfsm & XE2LPD_DFSM_DBUF_OVERLAP_DISABLE)) 1932 display_runtime->has_dbuf_overlap_detection = false; 1933 } 1934 1935 if (DISPLAY_VER(display) >= 20) { 1936 u32 cap = intel_de_read(display, XE2LPD_DE_CAP); 1937 1938 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == 1939 XE2LPD_DE_CAP_DSC_REMOVED) 1940 display_runtime->has_dsc = 0; 1941 1942 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) == 1943 XE2LPD_DE_CAP_SCALER_SINGLE) { 1944 for_each_pipe(display, pipe) 1945 if (display_runtime->num_scalers[pipe]) 1946 display_runtime->num_scalers[pipe] = 1; 1947 } 1948 } 1949 1950 if (DISPLAY_VER(display) >= 30) 1951 display_runtime->edp_typec_support = 1952 intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC; 1953 1954 display_runtime->rawclk_freq = intel_read_rawclk(display); 1955 drm_dbg_kms(display->drm, "rawclk rate: %d kHz\n", 1956 display_runtime->rawclk_freq); 1957 1958 return; 1959 1960 display_fused_off: 1961 memset(display_runtime, 0, sizeof(*display_runtime)); 1962 } 1963 1964 void intel_display_device_info_runtime_init(struct intel_display *display) 1965 { 1966 if (HAS_DISPLAY(display)) 1967 __intel_display_device_info_runtime_init(display); 1968 1969 /* Display may have been disabled by runtime init */ 1970 if (!HAS_DISPLAY(display)) { 1971 display->drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 1972 display->info.__device_info = &no_display; 1973 } 1974 1975 /* Disable nuclear pageflip by default on pre-g4x */ 1976 if (!display->params.nuclear_pageflip && 1977 DISPLAY_VER(display) < 5 && !display->platform.g4x) 1978 display->drm->driver_features &= ~DRIVER_ATOMIC; 1979 } 1980 1981 void intel_display_device_info_print(const struct intel_display_device_info *info, 1982 const struct intel_display_runtime_info *runtime, 1983 struct drm_printer *p) 1984 { 1985 if (runtime->ip.rel) 1986 drm_printf(p, "display version: %u.%02u\n", 1987 runtime->ip.ver, 1988 runtime->ip.rel); 1989 else 1990 drm_printf(p, "display version: %u\n", 1991 runtime->ip.ver); 1992 1993 drm_printf(p, "display stepping: %s\n", step_name(runtime)); 1994 1995 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 1996 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 1997 #undef PRINT_FLAG 1998 1999 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); 2000 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); 2001 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); 2002 2003 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 2004 } 2005 2006 bool intel_display_device_present(struct intel_display *display) 2007 { 2008 return display && HAS_DISPLAY(display); 2009 } 2010 2011 /* 2012 * Assuming the device has display hardware, should it be enabled? 2013 * 2014 * It's an error to call this function if the device does not have display 2015 * hardware. 2016 * 2017 * Disabling display means taking over the display hardware, putting it to 2018 * sleep, and preventing connectors from being connected via any means. 2019 */ 2020 bool intel_display_device_enabled(struct intel_display *display) 2021 { 2022 /* Only valid when HAS_DISPLAY() is true */ 2023 drm_WARN_ON(display->drm, !HAS_DISPLAY(display)); 2024 2025 return !display->params.disable_display && 2026 !intel_opregion_headless_sku(display); 2027 } 2028