1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/debugfs.h> 7 #include <linux/string_helpers.h> 8 9 #include <drm/drm_debugfs.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_file.h> 13 #include <drm/drm_fourcc.h> 14 15 #include "hsw_ips.h" 16 #include "i915_irq.h" 17 #include "i915_reg.h" 18 #include "i9xx_wm_regs.h" 19 #include "intel_alpm.h" 20 #include "intel_bo.h" 21 #include "intel_crtc.h" 22 #include "intel_crtc_state_dump.h" 23 #include "intel_de.h" 24 #include "intel_display_debugfs.h" 25 #include "intel_display_debugfs_params.h" 26 #include "intel_display_power.h" 27 #include "intel_display_power_well.h" 28 #include "intel_display_rpm.h" 29 #include "intel_display_types.h" 30 #include "intel_dmc.h" 31 #include "intel_dp.h" 32 #include "intel_dp_link_training.h" 33 #include "intel_dp_mst.h" 34 #include "intel_dp_test.h" 35 #include "intel_drrs.h" 36 #include "intel_fb.h" 37 #include "intel_fbc.h" 38 #include "intel_fbdev.h" 39 #include "intel_hdcp.h" 40 #include "intel_hdmi.h" 41 #include "intel_hotplug.h" 42 #include "intel_panel.h" 43 #include "intel_pps.h" 44 #include "intel_psr.h" 45 #include "intel_psr_regs.h" 46 #include "intel_vdsc.h" 47 #include "intel_wm.h" 48 49 static struct intel_display *node_to_intel_display(struct drm_info_node *node) 50 { 51 return to_intel_display(node->minor->dev); 52 } 53 54 static int intel_display_caps(struct seq_file *m, void *data) 55 { 56 struct intel_display *display = node_to_intel_display(m->private); 57 struct drm_printer p = drm_seq_file_printer(m); 58 59 drm_printf(&p, "PCH type: %d\n", INTEL_PCH_TYPE(display)); 60 61 intel_display_device_info_print(DISPLAY_INFO(display), 62 DISPLAY_RUNTIME_INFO(display), &p); 63 intel_display_params_dump(&display->params, display->drm->driver->name, &p); 64 65 return 0; 66 } 67 68 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 69 { 70 struct intel_display *display = node_to_intel_display(m->private); 71 72 spin_lock(&display->fb_tracking.lock); 73 74 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 75 display->fb_tracking.busy_bits); 76 77 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 78 display->fb_tracking.flip_bits); 79 80 spin_unlock(&display->fb_tracking.lock); 81 82 return 0; 83 } 84 85 static int i915_sr_status(struct seq_file *m, void *unused) 86 { 87 struct intel_display *display = node_to_intel_display(m->private); 88 intel_wakeref_t wakeref; 89 bool sr_enabled = false; 90 91 wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 92 93 if (DISPLAY_VER(display) >= 9) 94 /* no global SR status; inspect per-plane WM */; 95 else if (HAS_PCH_SPLIT(display)) 96 sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE; 97 else if (display->platform.i965gm || display->platform.g4x || 98 display->platform.i945g || display->platform.i945gm) 99 sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; 100 else if (display->platform.i915gm) 101 sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN; 102 else if (display->platform.pineview) 103 sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN; 104 else if (display->platform.valleyview || display->platform.cherryview) 105 sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 106 107 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 108 109 seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); 110 111 return 0; 112 } 113 114 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 115 { 116 struct intel_display *display = node_to_intel_display(m->private); 117 struct intel_framebuffer *fbdev_fb = NULL; 118 struct drm_framebuffer *drm_fb; 119 120 fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev); 121 if (fbdev_fb) { 122 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 123 fbdev_fb->base.width, 124 fbdev_fb->base.height, 125 fbdev_fb->base.format->depth, 126 fbdev_fb->base.format->cpp[0] * 8, 127 fbdev_fb->base.modifier, 128 drm_framebuffer_read_refcount(&fbdev_fb->base)); 129 intel_bo_describe(m, intel_fb_bo(&fbdev_fb->base)); 130 seq_putc(m, '\n'); 131 } 132 133 mutex_lock(&display->drm->mode_config.fb_lock); 134 drm_for_each_fb(drm_fb, display->drm) { 135 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 136 if (fb == fbdev_fb) 137 continue; 138 139 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 140 fb->base.width, 141 fb->base.height, 142 fb->base.format->depth, 143 fb->base.format->cpp[0] * 8, 144 fb->base.modifier, 145 drm_framebuffer_read_refcount(&fb->base)); 146 intel_bo_describe(m, intel_fb_bo(&fb->base)); 147 seq_putc(m, '\n'); 148 } 149 mutex_unlock(&display->drm->mode_config.fb_lock); 150 151 return 0; 152 } 153 154 static int i915_power_domain_info(struct seq_file *m, void *unused) 155 { 156 struct intel_display *display = node_to_intel_display(m->private); 157 158 intel_display_power_debug(display, m); 159 160 return 0; 161 } 162 163 static void intel_seq_print_mode(struct seq_file *m, int tabs, 164 const struct drm_display_mode *mode) 165 { 166 int i; 167 168 for (i = 0; i < tabs; i++) 169 seq_putc(m, '\t'); 170 171 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 172 } 173 174 static void intel_encoder_info(struct seq_file *m, 175 struct intel_crtc *crtc, 176 struct intel_encoder *encoder) 177 { 178 struct intel_display *display = node_to_intel_display(m->private); 179 struct drm_connector_list_iter conn_iter; 180 struct drm_connector *connector; 181 182 seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", 183 encoder->base.base.id, encoder->base.name); 184 185 drm_connector_list_iter_begin(display->drm, &conn_iter); 186 drm_for_each_connector_iter(connector, &conn_iter) { 187 const struct drm_connector_state *conn_state = 188 connector->state; 189 190 if (conn_state->best_encoder != &encoder->base) 191 continue; 192 193 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n", 194 connector->base.id, connector->name); 195 } 196 drm_connector_list_iter_end(&conn_iter); 197 } 198 199 static void intel_panel_info(struct seq_file *m, 200 struct intel_connector *connector) 201 { 202 const struct drm_display_mode *fixed_mode; 203 204 if (list_empty(&connector->panel.fixed_modes)) 205 return; 206 207 seq_puts(m, "\tfixed modes:\n"); 208 209 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 210 intel_seq_print_mode(m, 2, fixed_mode); 211 } 212 213 static void intel_dp_info(struct seq_file *m, struct intel_connector *connector) 214 { 215 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 216 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 217 218 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 219 seq_printf(m, "\taudio support: %s\n", 220 str_yes_no(connector->base.display_info.has_audio)); 221 222 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 223 connector->detect_edid, &intel_dp->aux); 224 } 225 226 static void intel_dp_mst_info(struct seq_file *m, 227 struct intel_connector *connector) 228 { 229 bool has_audio = connector->base.display_info.has_audio; 230 231 seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); 232 } 233 234 static void intel_hdmi_info(struct seq_file *m, 235 struct intel_connector *connector) 236 { 237 bool has_audio = connector->base.display_info.has_audio; 238 239 seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); 240 } 241 242 static void intel_connector_info(struct seq_file *m, 243 struct drm_connector *connector) 244 { 245 struct intel_connector *intel_connector = to_intel_connector(connector); 246 const struct drm_display_mode *mode; 247 248 seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n", 249 connector->base.id, connector->name, 250 drm_get_connector_status_name(connector->status)); 251 252 if (connector->status == connector_status_disconnected) 253 return; 254 255 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 256 connector->display_info.width_mm, 257 connector->display_info.height_mm); 258 seq_printf(m, "\tsubpixel order: %s\n", 259 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 260 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); 261 262 switch (connector->connector_type) { 263 case DRM_MODE_CONNECTOR_DisplayPort: 264 case DRM_MODE_CONNECTOR_eDP: 265 if (intel_connector->mst.dp) 266 intel_dp_mst_info(m, intel_connector); 267 else 268 intel_dp_info(m, intel_connector); 269 break; 270 case DRM_MODE_CONNECTOR_HDMIA: 271 intel_hdmi_info(m, intel_connector); 272 break; 273 default: 274 break; 275 } 276 277 intel_hdcp_info(m, intel_connector); 278 279 seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); 280 281 intel_panel_info(m, intel_connector); 282 283 seq_printf(m, "\tmodes:\n"); 284 list_for_each_entry(mode, &connector->modes, head) 285 intel_seq_print_mode(m, 2, mode); 286 } 287 288 static const char *plane_type(enum drm_plane_type type) 289 { 290 switch (type) { 291 case DRM_PLANE_TYPE_OVERLAY: 292 return "OVL"; 293 case DRM_PLANE_TYPE_PRIMARY: 294 return "PRI"; 295 case DRM_PLANE_TYPE_CURSOR: 296 return "CUR"; 297 /* 298 * Deliberately omitting default: to generate compiler warnings 299 * when a new drm_plane_type gets added. 300 */ 301 } 302 303 return "unknown"; 304 } 305 306 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation) 307 { 308 /* 309 * According to doc only one DRM_MODE_ROTATE_ is allowed but this 310 * will print them all to visualize if the values are misused 311 */ 312 snprintf(buf, bufsize, 313 "%s%s%s%s%s%s(0x%08x)", 314 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", 315 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", 316 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", 317 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", 318 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", 319 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", 320 rotation); 321 } 322 323 static const char *plane_visibility(const struct intel_plane_state *plane_state) 324 { 325 if (plane_state->uapi.visible) 326 return "visible"; 327 328 if (plane_state->is_y_plane) 329 return "Y plane"; 330 331 return "hidden"; 332 } 333 334 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) 335 { 336 const struct intel_plane_state *plane_state = 337 to_intel_plane_state(plane->base.state); 338 const struct drm_framebuffer *fb = plane_state->uapi.fb; 339 struct drm_rect src, dst; 340 char rot_str[48]; 341 342 src = drm_plane_state_src(&plane_state->uapi); 343 dst = drm_plane_state_dest(&plane_state->uapi); 344 345 plane_rotation(rot_str, sizeof(rot_str), 346 plane_state->uapi.rotation); 347 348 seq_puts(m, "\t\tuapi: [FB:"); 349 if (fb) 350 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id, 351 &fb->format->format, fb->modifier, fb->width, 352 fb->height); 353 else 354 seq_puts(m, "0] n/a,0x0,0x0,"); 355 seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT 356 ", rotation=%s\n", plane_visibility(plane_state), 357 DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str); 358 359 if (plane_state->planar_linked_plane) 360 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n", 361 plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, 362 plane_state->is_y_plane ? "Y plane" : "UV plane"); 363 } 364 365 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) 366 { 367 const struct intel_plane_state *plane_state = 368 to_intel_plane_state(plane->base.state); 369 const struct drm_framebuffer *fb = plane_state->hw.fb; 370 char rot_str[48]; 371 372 if (!fb) 373 return; 374 375 plane_rotation(rot_str, sizeof(rot_str), 376 plane_state->hw.rotation); 377 378 seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src=" 379 DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", 380 fb->base.id, &fb->format->format, 381 fb->modifier, fb->width, fb->height, 382 str_yes_no(plane_state->uapi.visible), 383 DRM_RECT_FP_ARG(&plane_state->uapi.src), 384 DRM_RECT_ARG(&plane_state->uapi.dst), 385 rot_str); 386 } 387 388 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) 389 { 390 struct intel_display *display = node_to_intel_display(m->private); 391 struct intel_plane *plane; 392 393 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 394 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", 395 plane->base.base.id, plane->base.name, 396 plane_type(plane->base.type)); 397 intel_plane_uapi_info(m, plane); 398 intel_plane_hw_info(m, plane); 399 } 400 } 401 402 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) 403 { 404 const struct intel_crtc_state *crtc_state = 405 to_intel_crtc_state(crtc->base.state); 406 int num_scalers = crtc->num_scalers; 407 int i; 408 409 /* Not all platforms have a scaler */ 410 if (num_scalers) { 411 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d", 412 num_scalers, 413 crtc_state->scaler_state.scaler_users, 414 crtc_state->scaler_state.scaler_id, 415 crtc_state->hw.scaling_filter); 416 417 for (i = 0; i < num_scalers; i++) { 418 const struct intel_scaler *sc = 419 &crtc_state->scaler_state.scalers[i]; 420 421 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 422 i, str_yes_no(sc->in_use), sc->mode); 423 } 424 seq_puts(m, "\n"); 425 } else { 426 seq_puts(m, "\tNo scalers available on this platform\n"); 427 } 428 } 429 430 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) 431 static void crtc_updates_info(struct seq_file *m, 432 struct intel_crtc *crtc, 433 const char *hdr) 434 { 435 u64 count; 436 int row; 437 438 count = 0; 439 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) 440 count += crtc->debug.vbl.times[row]; 441 seq_printf(m, "%sUpdates: %llu\n", hdr, count); 442 if (!count) 443 return; 444 445 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) { 446 char columns[80] = " |"; 447 unsigned int x; 448 449 if (row & 1) { 450 const char *units; 451 452 if (row > 10) { 453 x = 1000000; 454 units = "ms"; 455 } else { 456 x = 1000; 457 units = "us"; 458 } 459 460 snprintf(columns, sizeof(columns), "%4ld%s |", 461 DIV_ROUND_CLOSEST(BIT(row + 9), x), units); 462 } 463 464 if (crtc->debug.vbl.times[row]) { 465 x = ilog2(crtc->debug.vbl.times[row]); 466 memset(columns + 8, '*', x); 467 columns[8 + x] = '\0'; 468 } 469 470 seq_printf(m, "%s%s\n", hdr, columns); 471 } 472 473 seq_printf(m, "%sMin update: %lluns\n", 474 hdr, crtc->debug.vbl.min); 475 seq_printf(m, "%sMax update: %lluns\n", 476 hdr, crtc->debug.vbl.max); 477 seq_printf(m, "%sAverage update: %lluns\n", 478 hdr, div64_u64(crtc->debug.vbl.sum, count)); 479 seq_printf(m, "%sOverruns > %uus: %u\n", 480 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over); 481 } 482 483 static int crtc_updates_show(struct seq_file *m, void *data) 484 { 485 crtc_updates_info(m, m->private, ""); 486 return 0; 487 } 488 489 static int crtc_updates_open(struct inode *inode, struct file *file) 490 { 491 return single_open(file, crtc_updates_show, inode->i_private); 492 } 493 494 static ssize_t crtc_updates_write(struct file *file, 495 const char __user *ubuf, 496 size_t len, loff_t *offp) 497 { 498 struct seq_file *m = file->private_data; 499 struct intel_crtc *crtc = m->private; 500 501 /* May race with an update. Meh. */ 502 memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl)); 503 504 return len; 505 } 506 507 static const struct file_operations crtc_updates_fops = { 508 .owner = THIS_MODULE, 509 .open = crtc_updates_open, 510 .read = seq_read, 511 .llseek = seq_lseek, 512 .release = single_release, 513 .write = crtc_updates_write 514 }; 515 516 static void crtc_updates_add(struct intel_crtc *crtc) 517 { 518 debugfs_create_file("i915_update_info", 0644, crtc->base.debugfs_entry, 519 crtc, &crtc_updates_fops); 520 } 521 522 #else 523 static void crtc_updates_info(struct seq_file *m, 524 struct intel_crtc *crtc, 525 const char *hdr) 526 { 527 } 528 529 static void crtc_updates_add(struct intel_crtc *crtc) 530 { 531 } 532 #endif 533 534 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) 535 { 536 struct intel_display *display = node_to_intel_display(m->private); 537 struct drm_printer p = drm_seq_file_printer(m); 538 const struct intel_crtc_state *crtc_state = 539 to_intel_crtc_state(crtc->base.state); 540 struct intel_encoder *encoder; 541 542 seq_printf(m, "[CRTC:%d:%s]:\n", 543 crtc->base.base.id, crtc->base.name); 544 545 seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n", 546 str_yes_no(crtc_state->uapi.enable), 547 str_yes_no(crtc_state->uapi.active), 548 DRM_MODE_ARG(&crtc_state->uapi.mode)); 549 550 seq_printf(m, "\thw: enable=%s, active=%s\n", 551 str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active)); 552 seq_printf(m, "\tadjusted_mode=" DRM_MODE_FMT "\n", 553 DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); 554 seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", 555 DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); 556 557 seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", 558 DRM_RECT_ARG(&crtc_state->pipe_src), 559 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); 560 seq_printf(m, "\tport_clock=%d, lane_count=%d\n", 561 crtc_state->port_clock, crtc_state->lane_count); 562 563 intel_scaler_info(m, crtc); 564 565 if (crtc_state->joiner_pipes) 566 seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", 567 crtc_state->joiner_pipes, 568 intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master"); 569 570 intel_vdsc_state_dump(&p, 1, crtc_state); 571 572 for_each_intel_encoder_mask(display->drm, encoder, 573 crtc_state->uapi.encoder_mask) 574 intel_encoder_info(m, crtc, encoder); 575 576 intel_plane_info(m, crtc); 577 578 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n", 579 str_yes_no(!crtc->cpu_fifo_underrun_disabled), 580 str_yes_no(!crtc->pch_fifo_underrun_disabled)); 581 582 crtc_updates_info(m, crtc, "\t"); 583 } 584 585 static int i915_display_info(struct seq_file *m, void *unused) 586 { 587 struct intel_display *display = node_to_intel_display(m->private); 588 struct intel_crtc *crtc; 589 struct drm_connector *connector; 590 struct drm_connector_list_iter conn_iter; 591 struct ref_tracker *wakeref; 592 593 wakeref = intel_display_rpm_get(display); 594 595 drm_modeset_lock_all(display->drm); 596 597 seq_printf(m, "CRTC info\n"); 598 seq_printf(m, "---------\n"); 599 for_each_intel_crtc(display->drm, crtc) 600 intel_crtc_info(m, crtc); 601 602 seq_printf(m, "\n"); 603 seq_printf(m, "Connector info\n"); 604 seq_printf(m, "--------------\n"); 605 drm_connector_list_iter_begin(display->drm, &conn_iter); 606 drm_for_each_connector_iter(connector, &conn_iter) 607 intel_connector_info(m, connector); 608 drm_connector_list_iter_end(&conn_iter); 609 610 drm_modeset_unlock_all(display->drm); 611 612 intel_display_rpm_put(display, wakeref); 613 614 return 0; 615 } 616 617 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 618 { 619 struct intel_display *display = node_to_intel_display(m->private); 620 struct drm_printer p = drm_seq_file_printer(m); 621 struct intel_shared_dpll *pll; 622 int i; 623 624 drm_modeset_lock_all(display->drm); 625 626 drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", 627 display->dpll.ref_clks.nssc, 628 display->dpll.ref_clks.ssc); 629 630 for_each_shared_dpll(display, pll, i) { 631 drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index, 632 pll->info->name, pll->info->id); 633 drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", 634 pll->state.pipe_mask, pll->active_mask, 635 str_yes_no(pll->on)); 636 drm_printf(&p, " tracked hardware state:\n"); 637 intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state); 638 } 639 drm_modeset_unlock_all(display->drm); 640 641 return 0; 642 } 643 644 static int i915_ddb_info(struct seq_file *m, void *unused) 645 { 646 struct intel_display *display = node_to_intel_display(m->private); 647 struct skl_ddb_entry *entry; 648 struct intel_crtc *crtc; 649 650 if (DISPLAY_VER(display) < 9) 651 return -ENODEV; 652 653 drm_modeset_lock_all(display->drm); 654 655 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 656 657 for_each_intel_crtc(display->drm, crtc) { 658 struct intel_crtc_state *crtc_state = 659 to_intel_crtc_state(crtc->base.state); 660 enum pipe pipe = crtc->pipe; 661 enum plane_id plane_id; 662 663 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 664 665 for_each_plane_id_on_crtc(crtc, plane_id) { 666 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; 667 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, 668 entry->start, entry->end, 669 skl_ddb_entry_size(entry)); 670 } 671 672 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 673 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 674 entry->end, skl_ddb_entry_size(entry)); 675 } 676 677 drm_modeset_unlock_all(display->drm); 678 679 return 0; 680 } 681 682 static bool 683 intel_lpsp_power_well_enabled(struct intel_display *display, 684 enum i915_power_well_id power_well_id) 685 { 686 bool is_enabled; 687 688 with_intel_display_rpm(display) 689 is_enabled = intel_display_power_well_is_enabled(display, 690 power_well_id); 691 692 return is_enabled; 693 } 694 695 static int i915_lpsp_status(struct seq_file *m, void *unused) 696 { 697 struct intel_display *display = node_to_intel_display(m->private); 698 bool lpsp_enabled = false; 699 700 if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) { 701 lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2); 702 } else if (IS_DISPLAY_VER(display, 11, 12)) { 703 lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3); 704 } else if (display->platform.haswell || display->platform.broadwell) { 705 lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL); 706 } else { 707 seq_puts(m, "LPSP: not supported\n"); 708 return 0; 709 } 710 711 seq_printf(m, "LPSP: %s\n", str_enabled_disabled(lpsp_enabled)); 712 713 return 0; 714 } 715 716 static int i915_dp_mst_info(struct seq_file *m, void *unused) 717 { 718 struct intel_display *display = node_to_intel_display(m->private); 719 struct intel_encoder *intel_encoder; 720 struct intel_digital_port *dig_port; 721 struct drm_connector *connector; 722 struct drm_connector_list_iter conn_iter; 723 724 drm_connector_list_iter_begin(display->drm, &conn_iter); 725 drm_for_each_connector_iter(connector, &conn_iter) { 726 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 727 continue; 728 729 intel_encoder = intel_attached_encoder(to_intel_connector(connector)); 730 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 731 continue; 732 733 dig_port = enc_to_dig_port(intel_encoder); 734 if (!intel_dp_mst_source_support(&dig_port->dp)) 735 continue; 736 737 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", 738 dig_port->base.base.base.id, 739 dig_port->base.base.name); 740 drm_dp_mst_dump_topology(m, &dig_port->dp.mst.mgr); 741 } 742 drm_connector_list_iter_end(&conn_iter); 743 744 return 0; 745 } 746 747 static ssize_t 748 i915_fifo_underrun_reset_write(struct file *filp, 749 const char __user *ubuf, 750 size_t cnt, loff_t *ppos) 751 { 752 struct intel_display *display = filp->private_data; 753 struct intel_crtc *crtc; 754 int ret; 755 bool reset; 756 757 ret = kstrtobool_from_user(ubuf, cnt, &reset); 758 if (ret) 759 return ret; 760 761 if (!reset) 762 return cnt; 763 764 for_each_intel_crtc(display->drm, crtc) { 765 struct drm_crtc_commit *commit; 766 struct intel_crtc_state *crtc_state; 767 768 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 769 if (ret) 770 return ret; 771 772 crtc_state = to_intel_crtc_state(crtc->base.state); 773 commit = crtc_state->uapi.commit; 774 if (commit) { 775 ret = wait_for_completion_interruptible(&commit->hw_done); 776 if (!ret) 777 ret = wait_for_completion_interruptible(&commit->flip_done); 778 } 779 780 if (!ret && crtc_state->hw.active) { 781 drm_dbg_kms(display->drm, 782 "Re-arming FIFO underruns on pipe %c\n", 783 pipe_name(crtc->pipe)); 784 785 intel_crtc_arm_fifo_underrun(crtc, crtc_state); 786 } 787 788 drm_modeset_unlock(&crtc->base.mutex); 789 790 if (ret) 791 return ret; 792 } 793 794 intel_fbc_reset_underrun(display); 795 796 return cnt; 797 } 798 799 static const struct file_operations i915_fifo_underrun_reset_ops = { 800 .owner = THIS_MODULE, 801 .open = simple_open, 802 .write = i915_fifo_underrun_reset_write, 803 .llseek = default_llseek, 804 }; 805 806 static const struct drm_info_list intel_display_debugfs_list[] = { 807 {"intel_display_caps", intel_display_caps, 0}, 808 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 809 {"i915_sr_status", i915_sr_status, 0}, 810 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 811 {"i915_power_domain_info", i915_power_domain_info, 0}, 812 {"i915_display_info", i915_display_info, 0}, 813 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 814 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 815 {"i915_ddb_info", i915_ddb_info, 0}, 816 {"i915_lpsp_status", i915_lpsp_status, 0}, 817 }; 818 819 void intel_display_debugfs_register(struct intel_display *display) 820 { 821 struct drm_minor *minor = display->drm->primary; 822 823 debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root, 824 display, &i915_fifo_underrun_reset_ops); 825 826 drm_debugfs_create_files(intel_display_debugfs_list, 827 ARRAY_SIZE(intel_display_debugfs_list), 828 minor->debugfs_root, minor); 829 830 intel_bios_debugfs_register(display); 831 intel_cdclk_debugfs_register(display); 832 intel_dmc_debugfs_register(display); 833 intel_dp_test_debugfs_register(display); 834 intel_fbc_debugfs_register(display); 835 intel_hpd_debugfs_register(display); 836 intel_opregion_debugfs_register(display); 837 intel_psr_debugfs_register(display); 838 intel_wm_debugfs_register(display); 839 intel_display_debugfs_params(display); 840 } 841 842 static int i915_lpsp_capability_show(struct seq_file *m, void *data) 843 { 844 struct intel_connector *connector = m->private; 845 struct intel_display *display = to_intel_display(connector); 846 struct intel_encoder *encoder = intel_attached_encoder(connector); 847 int connector_type = connector->base.connector_type; 848 bool lpsp_capable = false; 849 850 if (!encoder) 851 return -ENODEV; 852 853 if (connector->base.status != connector_status_connected) 854 return -ENODEV; 855 856 if (DISPLAY_VER(display) >= 13) 857 lpsp_capable = encoder->port <= PORT_B; 858 else if (DISPLAY_VER(display) >= 12) 859 /* 860 * Actually TGL can drive LPSP on port till DDI_C 861 * but there is no physical connected DDI_C on TGL sku's, 862 * even driver is not initializing DDI_C port for gen12. 863 */ 864 lpsp_capable = encoder->port <= PORT_B; 865 else if (DISPLAY_VER(display) == 11) 866 lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI || 867 connector_type == DRM_MODE_CONNECTOR_eDP); 868 else if (IS_DISPLAY_VER(display, 9, 10)) 869 lpsp_capable = (encoder->port == PORT_A && 870 (connector_type == DRM_MODE_CONNECTOR_DSI || 871 connector_type == DRM_MODE_CONNECTOR_eDP || 872 connector_type == DRM_MODE_CONNECTOR_DisplayPort)); 873 else if (display->platform.haswell || display->platform.broadwell) 874 lpsp_capable = connector_type == DRM_MODE_CONNECTOR_eDP; 875 876 seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable"); 877 878 return 0; 879 } 880 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); 881 882 static int i915_dsc_fec_support_show(struct seq_file *m, void *data) 883 { 884 struct intel_connector *connector = m->private; 885 struct intel_display *display = to_intel_display(connector); 886 struct drm_crtc *crtc; 887 struct intel_dp *intel_dp; 888 struct drm_modeset_acquire_ctx ctx; 889 struct intel_crtc_state *crtc_state = NULL; 890 int ret = 0; 891 bool try_again = false; 892 893 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 894 895 do { 896 try_again = false; 897 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 898 &ctx); 899 if (ret) { 900 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { 901 try_again = true; 902 continue; 903 } 904 break; 905 } 906 crtc = connector->base.state->crtc; 907 if (connector->base.status != connector_status_connected || !crtc) { 908 ret = -ENODEV; 909 break; 910 } 911 ret = drm_modeset_lock(&crtc->mutex, &ctx); 912 if (ret == -EDEADLK) { 913 ret = drm_modeset_backoff(&ctx); 914 if (!ret) { 915 try_again = true; 916 continue; 917 } 918 break; 919 } else if (ret) { 920 break; 921 } 922 intel_dp = intel_attached_dp(connector); 923 crtc_state = to_intel_crtc_state(crtc->state); 924 seq_printf(m, "DSC_Enabled: %s\n", 925 str_yes_no(crtc_state->dsc.compression_enable)); 926 seq_printf(m, "DSC_Sink_Support: %s\n", 927 str_yes_no(drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))); 928 seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n", 929 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, 930 DP_DSC_RGB)), 931 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, 932 DP_DSC_YCbCr420_Native)), 933 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, 934 DP_DSC_YCbCr444))); 935 seq_printf(m, "DSC_Sink_BPP_Precision: %d\n", 936 drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd)); 937 seq_printf(m, "DSC_Sink_Max_Slice_Count: %d\n", 938 drm_dp_dsc_sink_max_slice_count((connector->dp.dsc_dpcd), intel_dp_is_edp(intel_dp))); 939 seq_printf(m, "Force_DSC_Enable: %s\n", 940 str_yes_no(intel_dp->force_dsc_en)); 941 if (!intel_dp_is_edp(intel_dp)) 942 seq_printf(m, "FEC_Sink_Support: %s\n", 943 str_yes_no(drm_dp_sink_supports_fec(connector->dp.fec_capability))); 944 } while (try_again); 945 946 drm_modeset_drop_locks(&ctx); 947 drm_modeset_acquire_fini(&ctx); 948 949 return ret; 950 } 951 952 static ssize_t i915_dsc_fec_support_write(struct file *file, 953 const char __user *ubuf, 954 size_t len, loff_t *offp) 955 { 956 struct seq_file *m = file->private_data; 957 struct intel_connector *connector = m->private; 958 struct intel_display *display = to_intel_display(connector); 959 struct intel_encoder *encoder = intel_attached_encoder(connector); 960 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 961 bool dsc_enable = false; 962 int ret; 963 964 if (len == 0) 965 return 0; 966 967 drm_dbg(display->drm, 968 "Copied %zu bytes from user to force DSC\n", len); 969 970 ret = kstrtobool_from_user(ubuf, len, &dsc_enable); 971 if (ret < 0) 972 return ret; 973 974 drm_dbg(display->drm, "Got %s for DSC Enable\n", 975 (dsc_enable) ? "true" : "false"); 976 intel_dp->force_dsc_en = dsc_enable; 977 978 *offp += len; 979 return len; 980 } 981 982 static int i915_dsc_fec_support_open(struct inode *inode, 983 struct file *file) 984 { 985 return single_open(file, i915_dsc_fec_support_show, 986 inode->i_private); 987 } 988 989 static const struct file_operations i915_dsc_fec_support_fops = { 990 .owner = THIS_MODULE, 991 .open = i915_dsc_fec_support_open, 992 .read = seq_read, 993 .llseek = seq_lseek, 994 .release = single_release, 995 .write = i915_dsc_fec_support_write 996 }; 997 998 static int i915_dsc_bpc_show(struct seq_file *m, void *data) 999 { 1000 struct intel_connector *connector = m->private; 1001 struct intel_display *display = to_intel_display(connector); 1002 struct intel_encoder *encoder = intel_attached_encoder(connector); 1003 struct drm_crtc *crtc; 1004 struct intel_crtc_state *crtc_state; 1005 int ret; 1006 1007 if (!encoder) 1008 return -ENODEV; 1009 1010 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1011 if (ret) 1012 return ret; 1013 1014 crtc = connector->base.state->crtc; 1015 if (connector->base.status != connector_status_connected || !crtc) { 1016 ret = -ENODEV; 1017 goto out; 1018 } 1019 1020 crtc_state = to_intel_crtc_state(crtc->state); 1021 seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component); 1022 1023 out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1024 1025 return ret; 1026 } 1027 1028 static ssize_t i915_dsc_bpc_write(struct file *file, 1029 const char __user *ubuf, 1030 size_t len, loff_t *offp) 1031 { 1032 struct seq_file *m = file->private_data; 1033 struct intel_connector *connector = m->private; 1034 struct intel_encoder *encoder = intel_attached_encoder(connector); 1035 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1036 int dsc_bpc = 0; 1037 int ret; 1038 1039 ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpc); 1040 if (ret < 0) 1041 return ret; 1042 1043 intel_dp->force_dsc_bpc = dsc_bpc; 1044 *offp += len; 1045 1046 return len; 1047 } 1048 1049 static int i915_dsc_bpc_open(struct inode *inode, 1050 struct file *file) 1051 { 1052 return single_open(file, i915_dsc_bpc_show, inode->i_private); 1053 } 1054 1055 static const struct file_operations i915_dsc_bpc_fops = { 1056 .owner = THIS_MODULE, 1057 .open = i915_dsc_bpc_open, 1058 .read = seq_read, 1059 .llseek = seq_lseek, 1060 .release = single_release, 1061 .write = i915_dsc_bpc_write 1062 }; 1063 1064 static int i915_dsc_output_format_show(struct seq_file *m, void *data) 1065 { 1066 struct intel_connector *connector = m->private; 1067 struct intel_display *display = to_intel_display(connector); 1068 struct intel_encoder *encoder = intel_attached_encoder(connector); 1069 struct drm_crtc *crtc; 1070 struct intel_crtc_state *crtc_state; 1071 int ret; 1072 1073 if (!encoder) 1074 return -ENODEV; 1075 1076 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1077 if (ret) 1078 return ret; 1079 1080 crtc = connector->base.state->crtc; 1081 if (connector->base.status != connector_status_connected || !crtc) { 1082 ret = -ENODEV; 1083 goto out; 1084 } 1085 1086 crtc_state = to_intel_crtc_state(crtc->state); 1087 seq_printf(m, "DSC_Output_Format: %s\n", 1088 intel_output_format_name(crtc_state->output_format)); 1089 1090 out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1091 1092 return ret; 1093 } 1094 1095 static ssize_t i915_dsc_output_format_write(struct file *file, 1096 const char __user *ubuf, 1097 size_t len, loff_t *offp) 1098 { 1099 struct seq_file *m = file->private_data; 1100 struct intel_connector *connector = m->private; 1101 struct intel_encoder *encoder = intel_attached_encoder(connector); 1102 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1103 int dsc_output_format = 0; 1104 int ret; 1105 1106 ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format); 1107 if (ret < 0) 1108 return ret; 1109 1110 intel_dp->force_dsc_output_format = dsc_output_format; 1111 *offp += len; 1112 1113 return len; 1114 } 1115 1116 static int i915_dsc_output_format_open(struct inode *inode, 1117 struct file *file) 1118 { 1119 return single_open(file, i915_dsc_output_format_show, inode->i_private); 1120 } 1121 1122 static const struct file_operations i915_dsc_output_format_fops = { 1123 .owner = THIS_MODULE, 1124 .open = i915_dsc_output_format_open, 1125 .read = seq_read, 1126 .llseek = seq_lseek, 1127 .release = single_release, 1128 .write = i915_dsc_output_format_write 1129 }; 1130 1131 static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data) 1132 { 1133 struct intel_connector *connector = m->private; 1134 struct intel_display *display = to_intel_display(connector); 1135 struct intel_encoder *encoder = intel_attached_encoder(connector); 1136 struct drm_crtc *crtc; 1137 struct intel_dp *intel_dp; 1138 int ret; 1139 1140 if (!encoder) 1141 return -ENODEV; 1142 1143 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1144 if (ret) 1145 return ret; 1146 1147 crtc = connector->base.state->crtc; 1148 if (connector->base.status != connector_status_connected || !crtc) { 1149 ret = -ENODEV; 1150 goto out; 1151 } 1152 1153 intel_dp = intel_attached_dp(connector); 1154 seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n", 1155 str_yes_no(intel_dp->force_dsc_fractional_bpp_en)); 1156 1157 out: 1158 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1159 1160 return ret; 1161 } 1162 1163 static ssize_t i915_dsc_fractional_bpp_write(struct file *file, 1164 const char __user *ubuf, 1165 size_t len, loff_t *offp) 1166 { 1167 struct seq_file *m = file->private_data; 1168 struct intel_connector *connector = m->private; 1169 struct intel_display *display = to_intel_display(connector); 1170 struct intel_encoder *encoder = intel_attached_encoder(connector); 1171 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1172 bool dsc_fractional_bpp_enable = false; 1173 int ret; 1174 1175 if (len == 0) 1176 return 0; 1177 1178 drm_dbg(display->drm, 1179 "Copied %zu bytes from user to force fractional bpp for DSC\n", len); 1180 1181 ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable); 1182 if (ret < 0) 1183 return ret; 1184 1185 drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n", 1186 (dsc_fractional_bpp_enable) ? "true" : "false"); 1187 intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable; 1188 1189 *offp += len; 1190 1191 return len; 1192 } 1193 1194 static int i915_dsc_fractional_bpp_open(struct inode *inode, 1195 struct file *file) 1196 { 1197 return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private); 1198 } 1199 1200 static const struct file_operations i915_dsc_fractional_bpp_fops = { 1201 .owner = THIS_MODULE, 1202 .open = i915_dsc_fractional_bpp_open, 1203 .read = seq_read, 1204 .llseek = seq_lseek, 1205 .release = single_release, 1206 .write = i915_dsc_fractional_bpp_write 1207 }; 1208 1209 /* 1210 * Returns the Current CRTC's bpc. 1211 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc 1212 */ 1213 static int i915_current_bpc_show(struct seq_file *m, void *data) 1214 { 1215 struct intel_crtc *crtc = m->private; 1216 struct intel_crtc_state *crtc_state; 1217 int ret; 1218 1219 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1220 if (ret) 1221 return ret; 1222 1223 crtc_state = to_intel_crtc_state(crtc->base.state); 1224 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); 1225 1226 drm_modeset_unlock(&crtc->base.mutex); 1227 1228 return ret; 1229 } 1230 DEFINE_SHOW_ATTRIBUTE(i915_current_bpc); 1231 1232 /* Pipe may differ from crtc index if pipes are fused off */ 1233 static int intel_crtc_pipe_show(struct seq_file *m, void *unused) 1234 { 1235 struct intel_crtc *crtc = m->private; 1236 1237 seq_printf(m, "%c\n", pipe_name(crtc->pipe)); 1238 1239 return 0; 1240 } 1241 DEFINE_SHOW_ATTRIBUTE(intel_crtc_pipe); 1242 1243 static int i915_joiner_show(struct seq_file *m, void *data) 1244 { 1245 struct intel_connector *connector = m->private; 1246 1247 seq_printf(m, "%d\n", connector->force_joined_pipes); 1248 1249 return 0; 1250 } 1251 1252 static ssize_t i915_joiner_write(struct file *file, 1253 const char __user *ubuf, 1254 size_t len, loff_t *offp) 1255 { 1256 struct seq_file *m = file->private_data; 1257 struct intel_connector *connector = m->private; 1258 struct intel_display *display = to_intel_display(connector); 1259 int force_joined_pipes = 0; 1260 int ret; 1261 1262 if (len == 0) 1263 return 0; 1264 1265 ret = kstrtoint_from_user(ubuf, len, 0, &force_joined_pipes); 1266 if (ret < 0) 1267 return ret; 1268 1269 switch (force_joined_pipes) { 1270 case 0: 1271 case 1: 1272 case 2: 1273 connector->force_joined_pipes = force_joined_pipes; 1274 break; 1275 case 4: 1276 if (HAS_ULTRAJOINER(display)) { 1277 connector->force_joined_pipes = force_joined_pipes; 1278 break; 1279 } 1280 1281 fallthrough; 1282 default: 1283 return -EINVAL; 1284 } 1285 1286 *offp += len; 1287 1288 return len; 1289 } 1290 1291 static int i915_joiner_open(struct inode *inode, struct file *file) 1292 { 1293 return single_open(file, i915_joiner_show, inode->i_private); 1294 } 1295 1296 static const struct file_operations i915_joiner_fops = { 1297 .owner = THIS_MODULE, 1298 .open = i915_joiner_open, 1299 .read = seq_read, 1300 .llseek = seq_lseek, 1301 .release = single_release, 1302 .write = i915_joiner_write 1303 }; 1304 1305 /** 1306 * intel_connector_debugfs_add - add i915 specific connector debugfs files 1307 * @connector: pointer to a registered intel_connector 1308 * 1309 * Cleanup will be done by drm_connector_unregister() through a call to 1310 * drm_debugfs_connector_remove(). 1311 */ 1312 void intel_connector_debugfs_add(struct intel_connector *connector) 1313 { 1314 struct intel_display *display = to_intel_display(connector); 1315 struct dentry *root = connector->base.debugfs_entry; 1316 int connector_type = connector->base.connector_type; 1317 1318 /* The connector must have been registered beforehands. */ 1319 if (!root) 1320 return; 1321 1322 intel_drrs_connector_debugfs_add(connector); 1323 intel_hdcp_connector_debugfs_add(connector); 1324 intel_pps_connector_debugfs_add(connector); 1325 intel_psr_connector_debugfs_add(connector); 1326 intel_alpm_lobf_debugfs_add(connector); 1327 intel_dp_link_training_debugfs_add(connector); 1328 1329 if (DISPLAY_VER(display) >= 11 && 1330 ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst.dp) || 1331 connector_type == DRM_MODE_CONNECTOR_eDP)) { 1332 debugfs_create_file("i915_dsc_fec_support", 0644, root, 1333 connector, &i915_dsc_fec_support_fops); 1334 1335 debugfs_create_file("i915_dsc_bpc", 0644, root, 1336 connector, &i915_dsc_bpc_fops); 1337 1338 debugfs_create_file("i915_dsc_output_format", 0644, root, 1339 connector, &i915_dsc_output_format_fops); 1340 1341 debugfs_create_file("i915_dsc_fractional_bpp", 0644, root, 1342 connector, &i915_dsc_fractional_bpp_fops); 1343 } 1344 1345 if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1346 connector_type == DRM_MODE_CONNECTOR_eDP) && 1347 intel_dp_has_joiner(intel_attached_dp(connector))) { 1348 debugfs_create_file("i915_joiner_force_enable", 0644, root, 1349 connector, &i915_joiner_fops); 1350 } 1351 1352 if (connector_type == DRM_MODE_CONNECTOR_DSI || 1353 connector_type == DRM_MODE_CONNECTOR_eDP || 1354 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1355 connector_type == DRM_MODE_CONNECTOR_HDMIA || 1356 connector_type == DRM_MODE_CONNECTOR_HDMIB) 1357 debugfs_create_file("i915_lpsp_capability", 0444, root, 1358 connector, &i915_lpsp_capability_fops); 1359 } 1360 1361 /** 1362 * intel_crtc_debugfs_add - add i915 specific crtc debugfs files 1363 * @crtc: pointer to a drm_crtc 1364 * 1365 * Failure to add debugfs entries should generally be ignored. 1366 */ 1367 void intel_crtc_debugfs_add(struct intel_crtc *crtc) 1368 { 1369 struct dentry *root = crtc->base.debugfs_entry; 1370 1371 if (!root) 1372 return; 1373 1374 crtc_updates_add(crtc); 1375 intel_drrs_crtc_debugfs_add(crtc); 1376 intel_fbc_crtc_debugfs_add(crtc); 1377 hsw_ips_crtc_debugfs_add(crtc); 1378 1379 debugfs_create_file("i915_current_bpc", 0444, root, crtc, 1380 &i915_current_bpc_fops); 1381 debugfs_create_file("i915_pipe", 0444, root, crtc, 1382 &intel_crtc_pipe_fops); 1383 } 1384