1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/drm_debugfs.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_debugfs.h" 12 #include "i915_irq.h" 13 #include "i915_reg.h" 14 #include "intel_de.h" 15 #include "intel_display_debugfs.h" 16 #include "intel_display_power.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_types.h" 19 #include "intel_dmc.h" 20 #include "intel_dp.h" 21 #include "intel_dp_mst.h" 22 #include "intel_drrs.h" 23 #include "intel_fbc.h" 24 #include "intel_fbdev.h" 25 #include "intel_hdcp.h" 26 #include "intel_hdmi.h" 27 #include "intel_hotplug.h" 28 #include "intel_panel.h" 29 #include "intel_pm.h" 30 #include "intel_psr.h" 31 #include "intel_sprite.h" 32 #include "skl_watermark.h" 33 34 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 35 { 36 return to_i915(node->minor->dev); 37 } 38 39 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 40 { 41 struct drm_i915_private *dev_priv = node_to_i915(m->private); 42 43 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 44 dev_priv->display.fb_tracking.busy_bits); 45 46 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 47 dev_priv->display.fb_tracking.flip_bits); 48 49 return 0; 50 } 51 52 static int i915_ips_status(struct seq_file *m, void *unused) 53 { 54 struct drm_i915_private *dev_priv = node_to_i915(m->private); 55 intel_wakeref_t wakeref; 56 57 if (!HAS_IPS(dev_priv)) 58 return -ENODEV; 59 60 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 61 62 seq_printf(m, "Enabled by kernel parameter: %s\n", 63 str_yes_no(dev_priv->params.enable_ips)); 64 65 if (DISPLAY_VER(dev_priv) >= 8) { 66 seq_puts(m, "Currently: unknown\n"); 67 } else { 68 if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE) 69 seq_puts(m, "Currently: enabled\n"); 70 else 71 seq_puts(m, "Currently: disabled\n"); 72 } 73 74 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 75 76 return 0; 77 } 78 79 static int i915_sr_status(struct seq_file *m, void *unused) 80 { 81 struct drm_i915_private *dev_priv = node_to_i915(m->private); 82 intel_wakeref_t wakeref; 83 bool sr_enabled = false; 84 85 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 86 87 if (DISPLAY_VER(dev_priv) >= 9) 88 /* no global SR status; inspect per-plane WM */; 89 else if (HAS_PCH_SPLIT(dev_priv)) 90 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE; 91 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || 92 IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 93 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; 94 else if (IS_I915GM(dev_priv)) 95 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; 96 else if (IS_PINEVIEW(dev_priv)) 97 sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 98 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 99 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 100 101 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 102 103 seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); 104 105 return 0; 106 } 107 108 static int i915_opregion(struct seq_file *m, void *unused) 109 { 110 struct drm_i915_private *i915 = node_to_i915(m->private); 111 struct intel_opregion *opregion = &i915->display.opregion; 112 113 if (opregion->header) 114 seq_write(m, opregion->header, OPREGION_SIZE); 115 116 return 0; 117 } 118 119 static int i915_vbt(struct seq_file *m, void *unused) 120 { 121 struct drm_i915_private *i915 = node_to_i915(m->private); 122 struct intel_opregion *opregion = &i915->display.opregion; 123 124 if (opregion->vbt) 125 seq_write(m, opregion->vbt, opregion->vbt_size); 126 127 return 0; 128 } 129 130 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 131 { 132 struct drm_i915_private *dev_priv = node_to_i915(m->private); 133 struct intel_framebuffer *fbdev_fb = NULL; 134 struct drm_framebuffer *drm_fb; 135 136 #ifdef CONFIG_DRM_FBDEV_EMULATION 137 fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev); 138 if (fbdev_fb) { 139 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 140 fbdev_fb->base.width, 141 fbdev_fb->base.height, 142 fbdev_fb->base.format->depth, 143 fbdev_fb->base.format->cpp[0] * 8, 144 fbdev_fb->base.modifier, 145 drm_framebuffer_read_refcount(&fbdev_fb->base)); 146 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base)); 147 seq_putc(m, '\n'); 148 } 149 #endif 150 151 mutex_lock(&dev_priv->drm.mode_config.fb_lock); 152 drm_for_each_fb(drm_fb, &dev_priv->drm) { 153 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 154 if (fb == fbdev_fb) 155 continue; 156 157 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 158 fb->base.width, 159 fb->base.height, 160 fb->base.format->depth, 161 fb->base.format->cpp[0] * 8, 162 fb->base.modifier, 163 drm_framebuffer_read_refcount(&fb->base)); 164 i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base)); 165 seq_putc(m, '\n'); 166 } 167 mutex_unlock(&dev_priv->drm.mode_config.fb_lock); 168 169 return 0; 170 } 171 172 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 173 { 174 u8 val; 175 static const char * const sink_status[] = { 176 "inactive", 177 "transition to active, capture and display", 178 "active, display from RFB", 179 "active, capture and display on sink device timings", 180 "transition to inactive, capture and display, timing re-sync", 181 "reserved", 182 "reserved", 183 "sink internal error", 184 }; 185 struct drm_connector *connector = m->private; 186 struct intel_dp *intel_dp = 187 intel_attached_dp(to_intel_connector(connector)); 188 int ret; 189 190 if (!CAN_PSR(intel_dp)) { 191 seq_puts(m, "PSR Unsupported\n"); 192 return -ENODEV; 193 } 194 195 if (connector->status != connector_status_connected) 196 return -ENODEV; 197 198 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val); 199 200 if (ret == 1) { 201 const char *str = "unknown"; 202 203 val &= DP_PSR_SINK_STATE_MASK; 204 if (val < ARRAY_SIZE(sink_status)) 205 str = sink_status[val]; 206 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); 207 } else { 208 return ret; 209 } 210 211 return 0; 212 } 213 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 214 215 static void 216 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 217 { 218 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 219 const char *status = "unknown"; 220 u32 val, status_val; 221 222 if (intel_dp->psr.psr2_enabled) { 223 static const char * const live_status[] = { 224 "IDLE", 225 "CAPTURE", 226 "CAPTURE_FS", 227 "SLEEP", 228 "BUFON_FW", 229 "ML_UP", 230 "SU_STANDBY", 231 "FAST_SLEEP", 232 "DEEP_SLEEP", 233 "BUF_ON", 234 "TG_ON" 235 }; 236 val = intel_de_read(dev_priv, 237 EDP_PSR2_STATUS(intel_dp->psr.transcoder)); 238 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 239 if (status_val < ARRAY_SIZE(live_status)) 240 status = live_status[status_val]; 241 } else { 242 static const char * const live_status[] = { 243 "IDLE", 244 "SRDONACK", 245 "SRDENT", 246 "BUFOFF", 247 "BUFON", 248 "AUXACK", 249 "SRDOFFACK", 250 "SRDENT_ON", 251 }; 252 val = intel_de_read(dev_priv, 253 EDP_PSR_STATUS(intel_dp->psr.transcoder)); 254 status_val = (val & EDP_PSR_STATUS_STATE_MASK) >> 255 EDP_PSR_STATUS_STATE_SHIFT; 256 if (status_val < ARRAY_SIZE(live_status)) 257 status = live_status[status_val]; 258 } 259 260 seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val); 261 } 262 263 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) 264 { 265 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 266 struct intel_psr *psr = &intel_dp->psr; 267 intel_wakeref_t wakeref; 268 const char *status; 269 bool enabled; 270 u32 val; 271 272 seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support)); 273 if (psr->sink_support) 274 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); 275 seq_puts(m, "\n"); 276 277 if (!psr->sink_support) 278 return 0; 279 280 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 281 mutex_lock(&psr->lock); 282 283 if (psr->enabled) 284 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; 285 else 286 status = "disabled"; 287 seq_printf(m, "PSR mode: %s\n", status); 288 289 if (!psr->enabled) { 290 seq_printf(m, "PSR sink not reliable: %s\n", 291 str_yes_no(psr->sink_not_reliable)); 292 293 goto unlock; 294 } 295 296 if (psr->psr2_enabled) { 297 val = intel_de_read(dev_priv, 298 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 299 enabled = val & EDP_PSR2_ENABLE; 300 } else { 301 val = intel_de_read(dev_priv, 302 EDP_PSR_CTL(intel_dp->psr.transcoder)); 303 enabled = val & EDP_PSR_ENABLE; 304 } 305 seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", 306 str_enabled_disabled(enabled), val); 307 psr_source_status(intel_dp, m); 308 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 309 psr->busy_frontbuffer_bits); 310 311 /* 312 * SKL+ Perf counter is reset to 0 everytime DC state is entered 313 */ 314 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 315 val = intel_de_read(dev_priv, 316 EDP_PSR_PERF_CNT(intel_dp->psr.transcoder)); 317 val &= EDP_PSR_PERF_CNT_MASK; 318 seq_printf(m, "Performance counter: %u\n", val); 319 } 320 321 if (psr->debug & I915_PSR_DEBUG_IRQ) { 322 seq_printf(m, "Last attempted entry at: %lld\n", 323 psr->last_entry_attempt); 324 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 325 } 326 327 if (psr->psr2_enabled) { 328 u32 su_frames_val[3]; 329 int frame; 330 331 /* 332 * Reading all 3 registers before hand to minimize crossing a 333 * frame boundary between register reads 334 */ 335 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 336 val = intel_de_read(dev_priv, 337 PSR2_SU_STATUS(intel_dp->psr.transcoder, frame)); 338 su_frames_val[frame / 3] = val; 339 } 340 341 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 342 343 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 344 u32 su_blocks; 345 346 su_blocks = su_frames_val[frame / 3] & 347 PSR2_SU_STATUS_MASK(frame); 348 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 349 seq_printf(m, "%d\t%d\n", frame, su_blocks); 350 } 351 352 seq_printf(m, "PSR2 selective fetch: %s\n", 353 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 354 } 355 356 unlock: 357 mutex_unlock(&psr->lock); 358 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 359 360 return 0; 361 } 362 363 static int i915_edp_psr_status(struct seq_file *m, void *data) 364 { 365 struct drm_i915_private *dev_priv = node_to_i915(m->private); 366 struct intel_dp *intel_dp = NULL; 367 struct intel_encoder *encoder; 368 369 if (!HAS_PSR(dev_priv)) 370 return -ENODEV; 371 372 /* Find the first EDP which supports PSR */ 373 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 374 intel_dp = enc_to_intel_dp(encoder); 375 break; 376 } 377 378 if (!intel_dp) 379 return -ENODEV; 380 381 return intel_psr_status(m, intel_dp); 382 } 383 384 static int 385 i915_edp_psr_debug_set(void *data, u64 val) 386 { 387 struct drm_i915_private *dev_priv = data; 388 struct intel_encoder *encoder; 389 intel_wakeref_t wakeref; 390 int ret = -ENODEV; 391 392 if (!HAS_PSR(dev_priv)) 393 return ret; 394 395 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 396 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 397 398 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); 399 400 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 401 402 // TODO: split to each transcoder's PSR debug state 403 ret = intel_psr_debug_set(intel_dp, val); 404 405 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 406 } 407 408 return ret; 409 } 410 411 static int 412 i915_edp_psr_debug_get(void *data, u64 *val) 413 { 414 struct drm_i915_private *dev_priv = data; 415 struct intel_encoder *encoder; 416 417 if (!HAS_PSR(dev_priv)) 418 return -ENODEV; 419 420 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 421 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 422 423 // TODO: split to each transcoder's PSR debug state 424 *val = READ_ONCE(intel_dp->psr.debug); 425 return 0; 426 } 427 428 return -ENODEV; 429 } 430 431 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 432 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 433 "%llu\n"); 434 435 static int i915_power_domain_info(struct seq_file *m, void *unused) 436 { 437 struct drm_i915_private *i915 = node_to_i915(m->private); 438 439 intel_display_power_debug(i915, m); 440 441 return 0; 442 } 443 444 static void intel_seq_print_mode(struct seq_file *m, int tabs, 445 const struct drm_display_mode *mode) 446 { 447 int i; 448 449 for (i = 0; i < tabs; i++) 450 seq_putc(m, '\t'); 451 452 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 453 } 454 455 static void intel_encoder_info(struct seq_file *m, 456 struct intel_crtc *crtc, 457 struct intel_encoder *encoder) 458 { 459 struct drm_i915_private *dev_priv = node_to_i915(m->private); 460 struct drm_connector_list_iter conn_iter; 461 struct drm_connector *connector; 462 463 seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", 464 encoder->base.base.id, encoder->base.name); 465 466 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 467 drm_for_each_connector_iter(connector, &conn_iter) { 468 const struct drm_connector_state *conn_state = 469 connector->state; 470 471 if (conn_state->best_encoder != &encoder->base) 472 continue; 473 474 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n", 475 connector->base.id, connector->name); 476 } 477 drm_connector_list_iter_end(&conn_iter); 478 } 479 480 static void intel_panel_info(struct seq_file *m, 481 struct intel_connector *connector) 482 { 483 const struct drm_display_mode *fixed_mode; 484 485 if (list_empty(&connector->panel.fixed_modes)) 486 return; 487 488 seq_puts(m, "\tfixed modes:\n"); 489 490 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 491 intel_seq_print_mode(m, 2, fixed_mode); 492 } 493 494 static void intel_hdcp_info(struct seq_file *m, 495 struct intel_connector *intel_connector) 496 { 497 bool hdcp_cap, hdcp2_cap; 498 499 if (!intel_connector->hdcp.shim) { 500 seq_puts(m, "No Connector Support"); 501 goto out; 502 } 503 504 hdcp_cap = intel_hdcp_capable(intel_connector); 505 hdcp2_cap = intel_hdcp2_capable(intel_connector); 506 507 if (hdcp_cap) 508 seq_puts(m, "HDCP1.4 "); 509 if (hdcp2_cap) 510 seq_puts(m, "HDCP2.2 "); 511 512 if (!hdcp_cap && !hdcp2_cap) 513 seq_puts(m, "None"); 514 515 out: 516 seq_puts(m, "\n"); 517 } 518 519 static void intel_dp_info(struct seq_file *m, 520 struct intel_connector *intel_connector) 521 { 522 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 523 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 524 const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr; 525 526 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 527 seq_printf(m, "\taudio support: %s\n", 528 str_yes_no(intel_dp->has_audio)); 529 530 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 531 edid ? edid->data : NULL, &intel_dp->aux); 532 } 533 534 static void intel_dp_mst_info(struct seq_file *m, 535 struct intel_connector *intel_connector) 536 { 537 bool has_audio = intel_connector->port->has_audio; 538 539 seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); 540 } 541 542 static void intel_hdmi_info(struct seq_file *m, 543 struct intel_connector *intel_connector) 544 { 545 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 546 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder); 547 548 seq_printf(m, "\taudio support: %s\n", 549 str_yes_no(intel_hdmi->has_audio)); 550 } 551 552 static void intel_connector_info(struct seq_file *m, 553 struct drm_connector *connector) 554 { 555 struct intel_connector *intel_connector = to_intel_connector(connector); 556 const struct drm_connector_state *conn_state = connector->state; 557 struct intel_encoder *encoder = 558 to_intel_encoder(conn_state->best_encoder); 559 const struct drm_display_mode *mode; 560 561 seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n", 562 connector->base.id, connector->name, 563 drm_get_connector_status_name(connector->status)); 564 565 if (connector->status == connector_status_disconnected) 566 return; 567 568 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 569 connector->display_info.width_mm, 570 connector->display_info.height_mm); 571 seq_printf(m, "\tsubpixel order: %s\n", 572 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 573 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); 574 575 if (!encoder) 576 return; 577 578 switch (connector->connector_type) { 579 case DRM_MODE_CONNECTOR_DisplayPort: 580 case DRM_MODE_CONNECTOR_eDP: 581 if (encoder->type == INTEL_OUTPUT_DP_MST) 582 intel_dp_mst_info(m, intel_connector); 583 else 584 intel_dp_info(m, intel_connector); 585 break; 586 case DRM_MODE_CONNECTOR_HDMIA: 587 if (encoder->type == INTEL_OUTPUT_HDMI || 588 encoder->type == INTEL_OUTPUT_DDI) 589 intel_hdmi_info(m, intel_connector); 590 break; 591 default: 592 break; 593 } 594 595 seq_puts(m, "\tHDCP version: "); 596 intel_hdcp_info(m, intel_connector); 597 598 seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); 599 600 intel_panel_info(m, intel_connector); 601 602 seq_printf(m, "\tmodes:\n"); 603 list_for_each_entry(mode, &connector->modes, head) 604 intel_seq_print_mode(m, 2, mode); 605 } 606 607 static const char *plane_type(enum drm_plane_type type) 608 { 609 switch (type) { 610 case DRM_PLANE_TYPE_OVERLAY: 611 return "OVL"; 612 case DRM_PLANE_TYPE_PRIMARY: 613 return "PRI"; 614 case DRM_PLANE_TYPE_CURSOR: 615 return "CUR"; 616 /* 617 * Deliberately omitting default: to generate compiler warnings 618 * when a new drm_plane_type gets added. 619 */ 620 } 621 622 return "unknown"; 623 } 624 625 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation) 626 { 627 /* 628 * According to doc only one DRM_MODE_ROTATE_ is allowed but this 629 * will print them all to visualize if the values are misused 630 */ 631 snprintf(buf, bufsize, 632 "%s%s%s%s%s%s(0x%08x)", 633 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", 634 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", 635 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", 636 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", 637 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", 638 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", 639 rotation); 640 } 641 642 static const char *plane_visibility(const struct intel_plane_state *plane_state) 643 { 644 if (plane_state->uapi.visible) 645 return "visible"; 646 647 if (plane_state->planar_slave) 648 return "planar-slave"; 649 650 return "hidden"; 651 } 652 653 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) 654 { 655 const struct intel_plane_state *plane_state = 656 to_intel_plane_state(plane->base.state); 657 const struct drm_framebuffer *fb = plane_state->uapi.fb; 658 struct drm_rect src, dst; 659 char rot_str[48]; 660 661 src = drm_plane_state_src(&plane_state->uapi); 662 dst = drm_plane_state_dest(&plane_state->uapi); 663 664 plane_rotation(rot_str, sizeof(rot_str), 665 plane_state->uapi.rotation); 666 667 seq_puts(m, "\t\tuapi: [FB:"); 668 if (fb) 669 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id, 670 &fb->format->format, fb->modifier, fb->width, 671 fb->height); 672 else 673 seq_puts(m, "0] n/a,0x0,0x0,"); 674 seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT 675 ", rotation=%s\n", plane_visibility(plane_state), 676 DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str); 677 678 if (plane_state->planar_linked_plane) 679 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n", 680 plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, 681 plane_state->planar_slave ? "slave" : "master"); 682 } 683 684 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) 685 { 686 const struct intel_plane_state *plane_state = 687 to_intel_plane_state(plane->base.state); 688 const struct drm_framebuffer *fb = plane_state->hw.fb; 689 char rot_str[48]; 690 691 if (!fb) 692 return; 693 694 plane_rotation(rot_str, sizeof(rot_str), 695 plane_state->hw.rotation); 696 697 seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src=" 698 DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", 699 fb->base.id, &fb->format->format, 700 fb->modifier, fb->width, fb->height, 701 str_yes_no(plane_state->uapi.visible), 702 DRM_RECT_FP_ARG(&plane_state->uapi.src), 703 DRM_RECT_ARG(&plane_state->uapi.dst), 704 rot_str); 705 } 706 707 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) 708 { 709 struct drm_i915_private *dev_priv = node_to_i915(m->private); 710 struct intel_plane *plane; 711 712 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 713 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", 714 plane->base.base.id, plane->base.name, 715 plane_type(plane->base.type)); 716 intel_plane_uapi_info(m, plane); 717 intel_plane_hw_info(m, plane); 718 } 719 } 720 721 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) 722 { 723 const struct intel_crtc_state *crtc_state = 724 to_intel_crtc_state(crtc->base.state); 725 int num_scalers = crtc->num_scalers; 726 int i; 727 728 /* Not all platformas have a scaler */ 729 if (num_scalers) { 730 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d", 731 num_scalers, 732 crtc_state->scaler_state.scaler_users, 733 crtc_state->scaler_state.scaler_id, 734 crtc_state->hw.scaling_filter); 735 736 for (i = 0; i < num_scalers; i++) { 737 const struct intel_scaler *sc = 738 &crtc_state->scaler_state.scalers[i]; 739 740 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 741 i, str_yes_no(sc->in_use), sc->mode); 742 } 743 seq_puts(m, "\n"); 744 } else { 745 seq_puts(m, "\tNo scalers available on this platform\n"); 746 } 747 } 748 749 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) 750 static void crtc_updates_info(struct seq_file *m, 751 struct intel_crtc *crtc, 752 const char *hdr) 753 { 754 u64 count; 755 int row; 756 757 count = 0; 758 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) 759 count += crtc->debug.vbl.times[row]; 760 seq_printf(m, "%sUpdates: %llu\n", hdr, count); 761 if (!count) 762 return; 763 764 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) { 765 char columns[80] = " |"; 766 unsigned int x; 767 768 if (row & 1) { 769 const char *units; 770 771 if (row > 10) { 772 x = 1000000; 773 units = "ms"; 774 } else { 775 x = 1000; 776 units = "us"; 777 } 778 779 snprintf(columns, sizeof(columns), "%4ld%s |", 780 DIV_ROUND_CLOSEST(BIT(row + 9), x), units); 781 } 782 783 if (crtc->debug.vbl.times[row]) { 784 x = ilog2(crtc->debug.vbl.times[row]); 785 memset(columns + 8, '*', x); 786 columns[8 + x] = '\0'; 787 } 788 789 seq_printf(m, "%s%s\n", hdr, columns); 790 } 791 792 seq_printf(m, "%sMin update: %lluns\n", 793 hdr, crtc->debug.vbl.min); 794 seq_printf(m, "%sMax update: %lluns\n", 795 hdr, crtc->debug.vbl.max); 796 seq_printf(m, "%sAverage update: %lluns\n", 797 hdr, div64_u64(crtc->debug.vbl.sum, count)); 798 seq_printf(m, "%sOverruns > %uus: %u\n", 799 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over); 800 } 801 802 static int crtc_updates_show(struct seq_file *m, void *data) 803 { 804 crtc_updates_info(m, m->private, ""); 805 return 0; 806 } 807 808 static int crtc_updates_open(struct inode *inode, struct file *file) 809 { 810 return single_open(file, crtc_updates_show, inode->i_private); 811 } 812 813 static ssize_t crtc_updates_write(struct file *file, 814 const char __user *ubuf, 815 size_t len, loff_t *offp) 816 { 817 struct seq_file *m = file->private_data; 818 struct intel_crtc *crtc = m->private; 819 820 /* May race with an update. Meh. */ 821 memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl)); 822 823 return len; 824 } 825 826 static const struct file_operations crtc_updates_fops = { 827 .owner = THIS_MODULE, 828 .open = crtc_updates_open, 829 .read = seq_read, 830 .llseek = seq_lseek, 831 .release = single_release, 832 .write = crtc_updates_write 833 }; 834 835 static void crtc_updates_add(struct drm_crtc *crtc) 836 { 837 debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry, 838 to_intel_crtc(crtc), &crtc_updates_fops); 839 } 840 841 #else 842 static void crtc_updates_info(struct seq_file *m, 843 struct intel_crtc *crtc, 844 const char *hdr) 845 { 846 } 847 848 static void crtc_updates_add(struct drm_crtc *crtc) 849 { 850 } 851 #endif 852 853 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) 854 { 855 struct drm_i915_private *dev_priv = node_to_i915(m->private); 856 const struct intel_crtc_state *crtc_state = 857 to_intel_crtc_state(crtc->base.state); 858 struct intel_encoder *encoder; 859 860 seq_printf(m, "[CRTC:%d:%s]:\n", 861 crtc->base.base.id, crtc->base.name); 862 863 seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n", 864 str_yes_no(crtc_state->uapi.enable), 865 str_yes_no(crtc_state->uapi.active), 866 DRM_MODE_ARG(&crtc_state->uapi.mode)); 867 868 seq_printf(m, "\thw: enable=%s, active=%s\n", 869 str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active)); 870 seq_printf(m, "\tadjusted_mode=" DRM_MODE_FMT "\n", 871 DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); 872 seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", 873 DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); 874 875 seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", 876 DRM_RECT_ARG(&crtc_state->pipe_src), 877 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); 878 879 intel_scaler_info(m, crtc); 880 881 if (crtc_state->bigjoiner_pipes) 882 seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", 883 crtc_state->bigjoiner_pipes, 884 intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave" : "master"); 885 886 for_each_intel_encoder_mask(&dev_priv->drm, encoder, 887 crtc_state->uapi.encoder_mask) 888 intel_encoder_info(m, crtc, encoder); 889 890 intel_plane_info(m, crtc); 891 892 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n", 893 str_yes_no(!crtc->cpu_fifo_underrun_disabled), 894 str_yes_no(!crtc->pch_fifo_underrun_disabled)); 895 896 crtc_updates_info(m, crtc, "\t"); 897 } 898 899 static int i915_display_info(struct seq_file *m, void *unused) 900 { 901 struct drm_i915_private *dev_priv = node_to_i915(m->private); 902 struct intel_crtc *crtc; 903 struct drm_connector *connector; 904 struct drm_connector_list_iter conn_iter; 905 intel_wakeref_t wakeref; 906 907 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 908 909 drm_modeset_lock_all(&dev_priv->drm); 910 911 seq_printf(m, "CRTC info\n"); 912 seq_printf(m, "---------\n"); 913 for_each_intel_crtc(&dev_priv->drm, crtc) 914 intel_crtc_info(m, crtc); 915 916 seq_printf(m, "\n"); 917 seq_printf(m, "Connector info\n"); 918 seq_printf(m, "--------------\n"); 919 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 920 drm_for_each_connector_iter(connector, &conn_iter) 921 intel_connector_info(m, connector); 922 drm_connector_list_iter_end(&conn_iter); 923 924 drm_modeset_unlock_all(&dev_priv->drm); 925 926 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 927 928 return 0; 929 } 930 931 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 932 { 933 struct drm_i915_private *dev_priv = node_to_i915(m->private); 934 int i; 935 936 drm_modeset_lock_all(&dev_priv->drm); 937 938 seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", 939 dev_priv->display.dpll.ref_clks.nssc, 940 dev_priv->display.dpll.ref_clks.ssc); 941 942 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { 943 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; 944 945 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, 946 pll->info->id); 947 seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", 948 pll->state.pipe_mask, pll->active_mask, 949 str_yes_no(pll->on)); 950 seq_printf(m, " tracked hardware state:\n"); 951 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); 952 seq_printf(m, " dpll_md: 0x%08x\n", 953 pll->state.hw_state.dpll_md); 954 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); 955 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); 956 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); 957 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); 958 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); 959 seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.div0); 960 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", 961 pll->state.hw_state.mg_refclkin_ctl); 962 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", 963 pll->state.hw_state.mg_clktop2_coreclkctl1); 964 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", 965 pll->state.hw_state.mg_clktop2_hsclkctl); 966 seq_printf(m, " mg_pll_div0: 0x%08x\n", 967 pll->state.hw_state.mg_pll_div0); 968 seq_printf(m, " mg_pll_div1: 0x%08x\n", 969 pll->state.hw_state.mg_pll_div1); 970 seq_printf(m, " mg_pll_lf: 0x%08x\n", 971 pll->state.hw_state.mg_pll_lf); 972 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", 973 pll->state.hw_state.mg_pll_frac_lock); 974 seq_printf(m, " mg_pll_ssc: 0x%08x\n", 975 pll->state.hw_state.mg_pll_ssc); 976 seq_printf(m, " mg_pll_bias: 0x%08x\n", 977 pll->state.hw_state.mg_pll_bias); 978 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", 979 pll->state.hw_state.mg_pll_tdc_coldst_bias); 980 } 981 drm_modeset_unlock_all(&dev_priv->drm); 982 983 return 0; 984 } 985 986 static int i915_ddb_info(struct seq_file *m, void *unused) 987 { 988 struct drm_i915_private *dev_priv = node_to_i915(m->private); 989 struct skl_ddb_entry *entry; 990 struct intel_crtc *crtc; 991 992 if (DISPLAY_VER(dev_priv) < 9) 993 return -ENODEV; 994 995 drm_modeset_lock_all(&dev_priv->drm); 996 997 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 998 999 for_each_intel_crtc(&dev_priv->drm, crtc) { 1000 struct intel_crtc_state *crtc_state = 1001 to_intel_crtc_state(crtc->base.state); 1002 enum pipe pipe = crtc->pipe; 1003 enum plane_id plane_id; 1004 1005 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 1006 1007 for_each_plane_id_on_crtc(crtc, plane_id) { 1008 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; 1009 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, 1010 entry->start, entry->end, 1011 skl_ddb_entry_size(entry)); 1012 } 1013 1014 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 1015 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 1016 entry->end, skl_ddb_entry_size(entry)); 1017 } 1018 1019 drm_modeset_unlock_all(&dev_priv->drm); 1020 1021 return 0; 1022 } 1023 1024 static bool 1025 intel_lpsp_power_well_enabled(struct drm_i915_private *i915, 1026 enum i915_power_well_id power_well_id) 1027 { 1028 intel_wakeref_t wakeref; 1029 bool is_enabled; 1030 1031 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1032 is_enabled = intel_display_power_well_is_enabled(i915, 1033 power_well_id); 1034 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1035 1036 return is_enabled; 1037 } 1038 1039 static int i915_lpsp_status(struct seq_file *m, void *unused) 1040 { 1041 struct drm_i915_private *i915 = node_to_i915(m->private); 1042 bool lpsp_enabled = false; 1043 1044 if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) { 1045 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2); 1046 } else if (IS_DISPLAY_VER(i915, 11, 12)) { 1047 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3); 1048 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1049 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL); 1050 } else { 1051 seq_puts(m, "LPSP: not supported\n"); 1052 return 0; 1053 } 1054 1055 seq_printf(m, "LPSP: %s\n", str_enabled_disabled(lpsp_enabled)); 1056 1057 return 0; 1058 } 1059 1060 static int i915_dp_mst_info(struct seq_file *m, void *unused) 1061 { 1062 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1063 struct intel_encoder *intel_encoder; 1064 struct intel_digital_port *dig_port; 1065 struct drm_connector *connector; 1066 struct drm_connector_list_iter conn_iter; 1067 1068 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 1069 drm_for_each_connector_iter(connector, &conn_iter) { 1070 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 1071 continue; 1072 1073 intel_encoder = intel_attached_encoder(to_intel_connector(connector)); 1074 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 1075 continue; 1076 1077 dig_port = enc_to_dig_port(intel_encoder); 1078 if (!intel_dp_mst_source_support(&dig_port->dp)) 1079 continue; 1080 1081 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", 1082 dig_port->base.base.base.id, 1083 dig_port->base.base.name); 1084 drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); 1085 } 1086 drm_connector_list_iter_end(&conn_iter); 1087 1088 return 0; 1089 } 1090 1091 static ssize_t i915_displayport_test_active_write(struct file *file, 1092 const char __user *ubuf, 1093 size_t len, loff_t *offp) 1094 { 1095 char *input_buffer; 1096 int status = 0; 1097 struct drm_device *dev; 1098 struct drm_connector *connector; 1099 struct drm_connector_list_iter conn_iter; 1100 struct intel_dp *intel_dp; 1101 int val = 0; 1102 1103 dev = ((struct seq_file *)file->private_data)->private; 1104 1105 if (len == 0) 1106 return 0; 1107 1108 input_buffer = memdup_user_nul(ubuf, len); 1109 if (IS_ERR(input_buffer)) 1110 return PTR_ERR(input_buffer); 1111 1112 drm_dbg(&to_i915(dev)->drm, 1113 "Copied %d bytes from user\n", (unsigned int)len); 1114 1115 drm_connector_list_iter_begin(dev, &conn_iter); 1116 drm_for_each_connector_iter(connector, &conn_iter) { 1117 struct intel_encoder *encoder; 1118 1119 if (connector->connector_type != 1120 DRM_MODE_CONNECTOR_DisplayPort) 1121 continue; 1122 1123 encoder = to_intel_encoder(connector->encoder); 1124 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1125 continue; 1126 1127 if (encoder && connector->status == connector_status_connected) { 1128 intel_dp = enc_to_intel_dp(encoder); 1129 status = kstrtoint(input_buffer, 10, &val); 1130 if (status < 0) 1131 break; 1132 drm_dbg(&to_i915(dev)->drm, 1133 "Got %d for test active\n", val); 1134 /* To prevent erroneous activation of the compliance 1135 * testing code, only accept an actual value of 1 here 1136 */ 1137 if (val == 1) 1138 intel_dp->compliance.test_active = true; 1139 else 1140 intel_dp->compliance.test_active = false; 1141 } 1142 } 1143 drm_connector_list_iter_end(&conn_iter); 1144 kfree(input_buffer); 1145 if (status < 0) 1146 return status; 1147 1148 *offp += len; 1149 return len; 1150 } 1151 1152 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 1153 { 1154 struct drm_i915_private *dev_priv = m->private; 1155 struct drm_connector *connector; 1156 struct drm_connector_list_iter conn_iter; 1157 struct intel_dp *intel_dp; 1158 1159 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 1160 drm_for_each_connector_iter(connector, &conn_iter) { 1161 struct intel_encoder *encoder; 1162 1163 if (connector->connector_type != 1164 DRM_MODE_CONNECTOR_DisplayPort) 1165 continue; 1166 1167 encoder = to_intel_encoder(connector->encoder); 1168 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1169 continue; 1170 1171 if (encoder && connector->status == connector_status_connected) { 1172 intel_dp = enc_to_intel_dp(encoder); 1173 if (intel_dp->compliance.test_active) 1174 seq_puts(m, "1"); 1175 else 1176 seq_puts(m, "0"); 1177 } else 1178 seq_puts(m, "0"); 1179 } 1180 drm_connector_list_iter_end(&conn_iter); 1181 1182 return 0; 1183 } 1184 1185 static int i915_displayport_test_active_open(struct inode *inode, 1186 struct file *file) 1187 { 1188 return single_open(file, i915_displayport_test_active_show, 1189 inode->i_private); 1190 } 1191 1192 static const struct file_operations i915_displayport_test_active_fops = { 1193 .owner = THIS_MODULE, 1194 .open = i915_displayport_test_active_open, 1195 .read = seq_read, 1196 .llseek = seq_lseek, 1197 .release = single_release, 1198 .write = i915_displayport_test_active_write 1199 }; 1200 1201 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 1202 { 1203 struct drm_i915_private *dev_priv = m->private; 1204 struct drm_connector *connector; 1205 struct drm_connector_list_iter conn_iter; 1206 struct intel_dp *intel_dp; 1207 1208 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 1209 drm_for_each_connector_iter(connector, &conn_iter) { 1210 struct intel_encoder *encoder; 1211 1212 if (connector->connector_type != 1213 DRM_MODE_CONNECTOR_DisplayPort) 1214 continue; 1215 1216 encoder = to_intel_encoder(connector->encoder); 1217 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1218 continue; 1219 1220 if (encoder && connector->status == connector_status_connected) { 1221 intel_dp = enc_to_intel_dp(encoder); 1222 if (intel_dp->compliance.test_type == 1223 DP_TEST_LINK_EDID_READ) 1224 seq_printf(m, "%lx", 1225 intel_dp->compliance.test_data.edid); 1226 else if (intel_dp->compliance.test_type == 1227 DP_TEST_LINK_VIDEO_PATTERN) { 1228 seq_printf(m, "hdisplay: %d\n", 1229 intel_dp->compliance.test_data.hdisplay); 1230 seq_printf(m, "vdisplay: %d\n", 1231 intel_dp->compliance.test_data.vdisplay); 1232 seq_printf(m, "bpc: %u\n", 1233 intel_dp->compliance.test_data.bpc); 1234 } else if (intel_dp->compliance.test_type == 1235 DP_TEST_LINK_PHY_TEST_PATTERN) { 1236 seq_printf(m, "pattern: %d\n", 1237 intel_dp->compliance.test_data.phytest.phy_pattern); 1238 seq_printf(m, "Number of lanes: %d\n", 1239 intel_dp->compliance.test_data.phytest.num_lanes); 1240 seq_printf(m, "Link Rate: %d\n", 1241 intel_dp->compliance.test_data.phytest.link_rate); 1242 seq_printf(m, "level: %02x\n", 1243 intel_dp->train_set[0]); 1244 } 1245 } else 1246 seq_puts(m, "0"); 1247 } 1248 drm_connector_list_iter_end(&conn_iter); 1249 1250 return 0; 1251 } 1252 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data); 1253 1254 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 1255 { 1256 struct drm_i915_private *dev_priv = m->private; 1257 struct drm_connector *connector; 1258 struct drm_connector_list_iter conn_iter; 1259 struct intel_dp *intel_dp; 1260 1261 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 1262 drm_for_each_connector_iter(connector, &conn_iter) { 1263 struct intel_encoder *encoder; 1264 1265 if (connector->connector_type != 1266 DRM_MODE_CONNECTOR_DisplayPort) 1267 continue; 1268 1269 encoder = to_intel_encoder(connector->encoder); 1270 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1271 continue; 1272 1273 if (encoder && connector->status == connector_status_connected) { 1274 intel_dp = enc_to_intel_dp(encoder); 1275 seq_printf(m, "%02lx\n", intel_dp->compliance.test_type); 1276 } else 1277 seq_puts(m, "0"); 1278 } 1279 drm_connector_list_iter_end(&conn_iter); 1280 1281 return 0; 1282 } 1283 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type); 1284 1285 static void wm_latency_show(struct seq_file *m, const u16 wm[8]) 1286 { 1287 struct drm_i915_private *dev_priv = m->private; 1288 int level; 1289 int num_levels; 1290 1291 if (IS_CHERRYVIEW(dev_priv)) 1292 num_levels = 3; 1293 else if (IS_VALLEYVIEW(dev_priv)) 1294 num_levels = 1; 1295 else if (IS_G4X(dev_priv)) 1296 num_levels = 3; 1297 else 1298 num_levels = ilk_wm_max_level(dev_priv) + 1; 1299 1300 drm_modeset_lock_all(&dev_priv->drm); 1301 1302 for (level = 0; level < num_levels; level++) { 1303 unsigned int latency = wm[level]; 1304 1305 /* 1306 * - WM1+ latency values in 0.5us units 1307 * - latencies are in us on gen9/vlv/chv 1308 */ 1309 if (DISPLAY_VER(dev_priv) >= 9 || 1310 IS_VALLEYVIEW(dev_priv) || 1311 IS_CHERRYVIEW(dev_priv) || 1312 IS_G4X(dev_priv)) 1313 latency *= 10; 1314 else if (level > 0) 1315 latency *= 5; 1316 1317 seq_printf(m, "WM%d %u (%u.%u usec)\n", 1318 level, wm[level], latency / 10, latency % 10); 1319 } 1320 1321 drm_modeset_unlock_all(&dev_priv->drm); 1322 } 1323 1324 static int pri_wm_latency_show(struct seq_file *m, void *data) 1325 { 1326 struct drm_i915_private *dev_priv = m->private; 1327 const u16 *latencies; 1328 1329 if (DISPLAY_VER(dev_priv) >= 9) 1330 latencies = dev_priv->display.wm.skl_latency; 1331 else 1332 latencies = dev_priv->display.wm.pri_latency; 1333 1334 wm_latency_show(m, latencies); 1335 1336 return 0; 1337 } 1338 1339 static int spr_wm_latency_show(struct seq_file *m, void *data) 1340 { 1341 struct drm_i915_private *dev_priv = m->private; 1342 const u16 *latencies; 1343 1344 if (DISPLAY_VER(dev_priv) >= 9) 1345 latencies = dev_priv->display.wm.skl_latency; 1346 else 1347 latencies = dev_priv->display.wm.spr_latency; 1348 1349 wm_latency_show(m, latencies); 1350 1351 return 0; 1352 } 1353 1354 static int cur_wm_latency_show(struct seq_file *m, void *data) 1355 { 1356 struct drm_i915_private *dev_priv = m->private; 1357 const u16 *latencies; 1358 1359 if (DISPLAY_VER(dev_priv) >= 9) 1360 latencies = dev_priv->display.wm.skl_latency; 1361 else 1362 latencies = dev_priv->display.wm.cur_latency; 1363 1364 wm_latency_show(m, latencies); 1365 1366 return 0; 1367 } 1368 1369 static int pri_wm_latency_open(struct inode *inode, struct file *file) 1370 { 1371 struct drm_i915_private *dev_priv = inode->i_private; 1372 1373 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 1374 return -ENODEV; 1375 1376 return single_open(file, pri_wm_latency_show, dev_priv); 1377 } 1378 1379 static int spr_wm_latency_open(struct inode *inode, struct file *file) 1380 { 1381 struct drm_i915_private *dev_priv = inode->i_private; 1382 1383 if (HAS_GMCH(dev_priv)) 1384 return -ENODEV; 1385 1386 return single_open(file, spr_wm_latency_show, dev_priv); 1387 } 1388 1389 static int cur_wm_latency_open(struct inode *inode, struct file *file) 1390 { 1391 struct drm_i915_private *dev_priv = inode->i_private; 1392 1393 if (HAS_GMCH(dev_priv)) 1394 return -ENODEV; 1395 1396 return single_open(file, cur_wm_latency_show, dev_priv); 1397 } 1398 1399 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 1400 size_t len, loff_t *offp, u16 wm[8]) 1401 { 1402 struct seq_file *m = file->private_data; 1403 struct drm_i915_private *dev_priv = m->private; 1404 u16 new[8] = { 0 }; 1405 int num_levels; 1406 int level; 1407 int ret; 1408 char tmp[32]; 1409 1410 if (IS_CHERRYVIEW(dev_priv)) 1411 num_levels = 3; 1412 else if (IS_VALLEYVIEW(dev_priv)) 1413 num_levels = 1; 1414 else if (IS_G4X(dev_priv)) 1415 num_levels = 3; 1416 else 1417 num_levels = ilk_wm_max_level(dev_priv) + 1; 1418 1419 if (len >= sizeof(tmp)) 1420 return -EINVAL; 1421 1422 if (copy_from_user(tmp, ubuf, len)) 1423 return -EFAULT; 1424 1425 tmp[len] = '\0'; 1426 1427 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 1428 &new[0], &new[1], &new[2], &new[3], 1429 &new[4], &new[5], &new[6], &new[7]); 1430 if (ret != num_levels) 1431 return -EINVAL; 1432 1433 drm_modeset_lock_all(&dev_priv->drm); 1434 1435 for (level = 0; level < num_levels; level++) 1436 wm[level] = new[level]; 1437 1438 drm_modeset_unlock_all(&dev_priv->drm); 1439 1440 return len; 1441 } 1442 1443 1444 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 1445 size_t len, loff_t *offp) 1446 { 1447 struct seq_file *m = file->private_data; 1448 struct drm_i915_private *dev_priv = m->private; 1449 u16 *latencies; 1450 1451 if (DISPLAY_VER(dev_priv) >= 9) 1452 latencies = dev_priv->display.wm.skl_latency; 1453 else 1454 latencies = dev_priv->display.wm.pri_latency; 1455 1456 return wm_latency_write(file, ubuf, len, offp, latencies); 1457 } 1458 1459 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 1460 size_t len, loff_t *offp) 1461 { 1462 struct seq_file *m = file->private_data; 1463 struct drm_i915_private *dev_priv = m->private; 1464 u16 *latencies; 1465 1466 if (DISPLAY_VER(dev_priv) >= 9) 1467 latencies = dev_priv->display.wm.skl_latency; 1468 else 1469 latencies = dev_priv->display.wm.spr_latency; 1470 1471 return wm_latency_write(file, ubuf, len, offp, latencies); 1472 } 1473 1474 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 1475 size_t len, loff_t *offp) 1476 { 1477 struct seq_file *m = file->private_data; 1478 struct drm_i915_private *dev_priv = m->private; 1479 u16 *latencies; 1480 1481 if (DISPLAY_VER(dev_priv) >= 9) 1482 latencies = dev_priv->display.wm.skl_latency; 1483 else 1484 latencies = dev_priv->display.wm.cur_latency; 1485 1486 return wm_latency_write(file, ubuf, len, offp, latencies); 1487 } 1488 1489 static const struct file_operations i915_pri_wm_latency_fops = { 1490 .owner = THIS_MODULE, 1491 .open = pri_wm_latency_open, 1492 .read = seq_read, 1493 .llseek = seq_lseek, 1494 .release = single_release, 1495 .write = pri_wm_latency_write 1496 }; 1497 1498 static const struct file_operations i915_spr_wm_latency_fops = { 1499 .owner = THIS_MODULE, 1500 .open = spr_wm_latency_open, 1501 .read = seq_read, 1502 .llseek = seq_lseek, 1503 .release = single_release, 1504 .write = spr_wm_latency_write 1505 }; 1506 1507 static const struct file_operations i915_cur_wm_latency_fops = { 1508 .owner = THIS_MODULE, 1509 .open = cur_wm_latency_open, 1510 .read = seq_read, 1511 .llseek = seq_lseek, 1512 .release = single_release, 1513 .write = cur_wm_latency_write 1514 }; 1515 1516 static ssize_t 1517 i915_fifo_underrun_reset_write(struct file *filp, 1518 const char __user *ubuf, 1519 size_t cnt, loff_t *ppos) 1520 { 1521 struct drm_i915_private *dev_priv = filp->private_data; 1522 struct intel_crtc *crtc; 1523 int ret; 1524 bool reset; 1525 1526 ret = kstrtobool_from_user(ubuf, cnt, &reset); 1527 if (ret) 1528 return ret; 1529 1530 if (!reset) 1531 return cnt; 1532 1533 for_each_intel_crtc(&dev_priv->drm, crtc) { 1534 struct drm_crtc_commit *commit; 1535 struct intel_crtc_state *crtc_state; 1536 1537 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1538 if (ret) 1539 return ret; 1540 1541 crtc_state = to_intel_crtc_state(crtc->base.state); 1542 commit = crtc_state->uapi.commit; 1543 if (commit) { 1544 ret = wait_for_completion_interruptible(&commit->hw_done); 1545 if (!ret) 1546 ret = wait_for_completion_interruptible(&commit->flip_done); 1547 } 1548 1549 if (!ret && crtc_state->hw.active) { 1550 drm_dbg_kms(&dev_priv->drm, 1551 "Re-arming FIFO underruns on pipe %c\n", 1552 pipe_name(crtc->pipe)); 1553 1554 intel_crtc_arm_fifo_underrun(crtc, crtc_state); 1555 } 1556 1557 drm_modeset_unlock(&crtc->base.mutex); 1558 1559 if (ret) 1560 return ret; 1561 } 1562 1563 intel_fbc_reset_underrun(dev_priv); 1564 1565 return cnt; 1566 } 1567 1568 static const struct file_operations i915_fifo_underrun_reset_ops = { 1569 .owner = THIS_MODULE, 1570 .open = simple_open, 1571 .write = i915_fifo_underrun_reset_write, 1572 .llseek = default_llseek, 1573 }; 1574 1575 static const struct drm_info_list intel_display_debugfs_list[] = { 1576 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 1577 {"i915_ips_status", i915_ips_status, 0}, 1578 {"i915_sr_status", i915_sr_status, 0}, 1579 {"i915_opregion", i915_opregion, 0}, 1580 {"i915_vbt", i915_vbt, 0}, 1581 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 1582 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 1583 {"i915_power_domain_info", i915_power_domain_info, 0}, 1584 {"i915_display_info", i915_display_info, 0}, 1585 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 1586 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 1587 {"i915_ddb_info", i915_ddb_info, 0}, 1588 {"i915_lpsp_status", i915_lpsp_status, 0}, 1589 }; 1590 1591 static const struct { 1592 const char *name; 1593 const struct file_operations *fops; 1594 } intel_display_debugfs_files[] = { 1595 {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops}, 1596 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 1597 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 1598 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 1599 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 1600 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 1601 {"i915_dp_test_active", &i915_displayport_test_active_fops}, 1602 {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, 1603 }; 1604 1605 void intel_display_debugfs_register(struct drm_i915_private *i915) 1606 { 1607 struct drm_minor *minor = i915->drm.primary; 1608 int i; 1609 1610 for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) { 1611 debugfs_create_file(intel_display_debugfs_files[i].name, 1612 S_IRUGO | S_IWUSR, 1613 minor->debugfs_root, 1614 to_i915(minor->dev), 1615 intel_display_debugfs_files[i].fops); 1616 } 1617 1618 drm_debugfs_create_files(intel_display_debugfs_list, 1619 ARRAY_SIZE(intel_display_debugfs_list), 1620 minor->debugfs_root, minor); 1621 1622 intel_dmc_debugfs_register(i915); 1623 intel_fbc_debugfs_register(i915); 1624 intel_hpd_debugfs_register(i915); 1625 skl_watermark_ipc_debugfs_register(i915); 1626 } 1627 1628 static int i915_panel_show(struct seq_file *m, void *data) 1629 { 1630 struct drm_connector *connector = m->private; 1631 struct intel_dp *intel_dp = 1632 intel_attached_dp(to_intel_connector(connector)); 1633 1634 if (connector->status != connector_status_connected) 1635 return -ENODEV; 1636 1637 seq_printf(m, "Panel power up delay: %d\n", 1638 intel_dp->pps.panel_power_up_delay); 1639 seq_printf(m, "Panel power down delay: %d\n", 1640 intel_dp->pps.panel_power_down_delay); 1641 seq_printf(m, "Backlight on delay: %d\n", 1642 intel_dp->pps.backlight_on_delay); 1643 seq_printf(m, "Backlight off delay: %d\n", 1644 intel_dp->pps.backlight_off_delay); 1645 1646 return 0; 1647 } 1648 DEFINE_SHOW_ATTRIBUTE(i915_panel); 1649 1650 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) 1651 { 1652 struct drm_connector *connector = m->private; 1653 struct drm_i915_private *i915 = to_i915(connector->dev); 1654 struct intel_connector *intel_connector = to_intel_connector(connector); 1655 int ret; 1656 1657 ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1658 if (ret) 1659 return ret; 1660 1661 if (!connector->encoder || connector->status != connector_status_connected) { 1662 ret = -ENODEV; 1663 goto out; 1664 } 1665 1666 seq_printf(m, "%s:%d HDCP version: ", connector->name, 1667 connector->base.id); 1668 intel_hdcp_info(m, intel_connector); 1669 1670 out: 1671 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1672 1673 return ret; 1674 } 1675 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); 1676 1677 static int i915_psr_status_show(struct seq_file *m, void *data) 1678 { 1679 struct drm_connector *connector = m->private; 1680 struct intel_dp *intel_dp = 1681 intel_attached_dp(to_intel_connector(connector)); 1682 1683 return intel_psr_status(m, intel_dp); 1684 } 1685 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 1686 1687 static int i915_lpsp_capability_show(struct seq_file *m, void *data) 1688 { 1689 struct drm_connector *connector = m->private; 1690 struct drm_i915_private *i915 = to_i915(connector->dev); 1691 struct intel_encoder *encoder; 1692 bool lpsp_capable = false; 1693 1694 encoder = intel_attached_encoder(to_intel_connector(connector)); 1695 if (!encoder) 1696 return -ENODEV; 1697 1698 if (connector->status != connector_status_connected) 1699 return -ENODEV; 1700 1701 if (DISPLAY_VER(i915) >= 13) 1702 lpsp_capable = encoder->port <= PORT_B; 1703 else if (DISPLAY_VER(i915) >= 12) 1704 /* 1705 * Actually TGL can drive LPSP on port till DDI_C 1706 * but there is no physical connected DDI_C on TGL sku's, 1707 * even driver is not initilizing DDI_C port for gen12. 1708 */ 1709 lpsp_capable = encoder->port <= PORT_B; 1710 else if (DISPLAY_VER(i915) == 11) 1711 lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1712 connector->connector_type == DRM_MODE_CONNECTOR_eDP); 1713 else if (IS_DISPLAY_VER(i915, 9, 10)) 1714 lpsp_capable = (encoder->port == PORT_A && 1715 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1716 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 1717 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)); 1718 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 1719 lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP; 1720 1721 seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable"); 1722 1723 return 0; 1724 } 1725 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); 1726 1727 static int i915_dsc_fec_support_show(struct seq_file *m, void *data) 1728 { 1729 struct drm_connector *connector = m->private; 1730 struct drm_device *dev = connector->dev; 1731 struct drm_crtc *crtc; 1732 struct intel_dp *intel_dp; 1733 struct drm_modeset_acquire_ctx ctx; 1734 struct intel_crtc_state *crtc_state = NULL; 1735 int ret = 0; 1736 bool try_again = false; 1737 1738 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1739 1740 do { 1741 try_again = false; 1742 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, 1743 &ctx); 1744 if (ret) { 1745 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { 1746 try_again = true; 1747 continue; 1748 } 1749 break; 1750 } 1751 crtc = connector->state->crtc; 1752 if (connector->status != connector_status_connected || !crtc) { 1753 ret = -ENODEV; 1754 break; 1755 } 1756 ret = drm_modeset_lock(&crtc->mutex, &ctx); 1757 if (ret == -EDEADLK) { 1758 ret = drm_modeset_backoff(&ctx); 1759 if (!ret) { 1760 try_again = true; 1761 continue; 1762 } 1763 break; 1764 } else if (ret) { 1765 break; 1766 } 1767 intel_dp = intel_attached_dp(to_intel_connector(connector)); 1768 crtc_state = to_intel_crtc_state(crtc->state); 1769 seq_printf(m, "DSC_Enabled: %s\n", 1770 str_yes_no(crtc_state->dsc.compression_enable)); 1771 seq_printf(m, "DSC_Sink_Support: %s\n", 1772 str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); 1773 seq_printf(m, "Force_DSC_Enable: %s\n", 1774 str_yes_no(intel_dp->force_dsc_en)); 1775 if (!intel_dp_is_edp(intel_dp)) 1776 seq_printf(m, "FEC_Sink_Support: %s\n", 1777 str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable))); 1778 } while (try_again); 1779 1780 drm_modeset_drop_locks(&ctx); 1781 drm_modeset_acquire_fini(&ctx); 1782 1783 return ret; 1784 } 1785 1786 static ssize_t i915_dsc_fec_support_write(struct file *file, 1787 const char __user *ubuf, 1788 size_t len, loff_t *offp) 1789 { 1790 bool dsc_enable = false; 1791 int ret; 1792 struct drm_connector *connector = 1793 ((struct seq_file *)file->private_data)->private; 1794 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 1795 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1796 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1797 1798 if (len == 0) 1799 return 0; 1800 1801 drm_dbg(&i915->drm, 1802 "Copied %zu bytes from user to force DSC\n", len); 1803 1804 ret = kstrtobool_from_user(ubuf, len, &dsc_enable); 1805 if (ret < 0) 1806 return ret; 1807 1808 drm_dbg(&i915->drm, "Got %s for DSC Enable\n", 1809 (dsc_enable) ? "true" : "false"); 1810 intel_dp->force_dsc_en = dsc_enable; 1811 1812 *offp += len; 1813 return len; 1814 } 1815 1816 static int i915_dsc_fec_support_open(struct inode *inode, 1817 struct file *file) 1818 { 1819 return single_open(file, i915_dsc_fec_support_show, 1820 inode->i_private); 1821 } 1822 1823 static const struct file_operations i915_dsc_fec_support_fops = { 1824 .owner = THIS_MODULE, 1825 .open = i915_dsc_fec_support_open, 1826 .read = seq_read, 1827 .llseek = seq_lseek, 1828 .release = single_release, 1829 .write = i915_dsc_fec_support_write 1830 }; 1831 1832 static int i915_dsc_bpc_show(struct seq_file *m, void *data) 1833 { 1834 struct drm_connector *connector = m->private; 1835 struct drm_device *dev = connector->dev; 1836 struct drm_crtc *crtc; 1837 struct intel_crtc_state *crtc_state; 1838 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 1839 int ret; 1840 1841 if (!encoder) 1842 return -ENODEV; 1843 1844 ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex); 1845 if (ret) 1846 return ret; 1847 1848 crtc = connector->state->crtc; 1849 if (connector->status != connector_status_connected || !crtc) { 1850 ret = -ENODEV; 1851 goto out; 1852 } 1853 1854 crtc_state = to_intel_crtc_state(crtc->state); 1855 seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component); 1856 1857 out: drm_modeset_unlock(&dev->mode_config.connection_mutex); 1858 1859 return ret; 1860 } 1861 1862 static ssize_t i915_dsc_bpc_write(struct file *file, 1863 const char __user *ubuf, 1864 size_t len, loff_t *offp) 1865 { 1866 struct drm_connector *connector = 1867 ((struct seq_file *)file->private_data)->private; 1868 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 1869 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1870 int dsc_bpc = 0; 1871 int ret; 1872 1873 ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpc); 1874 if (ret < 0) 1875 return ret; 1876 1877 intel_dp->force_dsc_bpc = dsc_bpc; 1878 *offp += len; 1879 1880 return len; 1881 } 1882 1883 static int i915_dsc_bpc_open(struct inode *inode, 1884 struct file *file) 1885 { 1886 return single_open(file, i915_dsc_bpc_show, inode->i_private); 1887 } 1888 1889 static const struct file_operations i915_dsc_bpc_fops = { 1890 .owner = THIS_MODULE, 1891 .open = i915_dsc_bpc_open, 1892 .read = seq_read, 1893 .llseek = seq_lseek, 1894 .release = single_release, 1895 .write = i915_dsc_bpc_write 1896 }; 1897 1898 /* 1899 * Returns the Current CRTC's bpc. 1900 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc 1901 */ 1902 static int i915_current_bpc_show(struct seq_file *m, void *data) 1903 { 1904 struct intel_crtc *crtc = to_intel_crtc(m->private); 1905 struct intel_crtc_state *crtc_state; 1906 int ret; 1907 1908 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1909 if (ret) 1910 return ret; 1911 1912 crtc_state = to_intel_crtc_state(crtc->base.state); 1913 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); 1914 1915 drm_modeset_unlock(&crtc->base.mutex); 1916 1917 return ret; 1918 } 1919 DEFINE_SHOW_ATTRIBUTE(i915_current_bpc); 1920 1921 /** 1922 * intel_connector_debugfs_add - add i915 specific connector debugfs files 1923 * @connector: pointer to a registered drm_connector 1924 * 1925 * Cleanup will be done by drm_connector_unregister() through a call to 1926 * drm_debugfs_connector_remove(). 1927 */ 1928 void intel_connector_debugfs_add(struct intel_connector *intel_connector) 1929 { 1930 struct drm_connector *connector = &intel_connector->base; 1931 struct dentry *root = connector->debugfs_entry; 1932 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1933 1934 /* The connector must have been registered beforehands. */ 1935 if (!root) 1936 return; 1937 1938 intel_drrs_connector_debugfs_add(intel_connector); 1939 1940 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1941 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 1942 connector, &i915_panel_fops); 1943 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, 1944 connector, &i915_psr_sink_status_fops); 1945 } 1946 1947 if (HAS_PSR(dev_priv) && 1948 connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1949 debugfs_create_file("i915_psr_status", 0444, root, 1950 connector, &i915_psr_status_fops); 1951 } 1952 1953 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1954 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 1955 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 1956 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 1957 connector, &i915_hdcp_sink_capability_fops); 1958 } 1959 1960 if (DISPLAY_VER(dev_priv) >= 11 && 1961 ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && 1962 !to_intel_connector(connector)->mst_port) || 1963 connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1964 debugfs_create_file("i915_dsc_fec_support", 0644, root, 1965 connector, &i915_dsc_fec_support_fops); 1966 1967 debugfs_create_file("i915_dsc_bpc", 0644, root, 1968 connector, &i915_dsc_bpc_fops); 1969 } 1970 1971 if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1972 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 1973 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1974 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 1975 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 1976 debugfs_create_file("i915_lpsp_capability", 0444, root, 1977 connector, &i915_lpsp_capability_fops); 1978 } 1979 1980 /** 1981 * intel_crtc_debugfs_add - add i915 specific crtc debugfs files 1982 * @crtc: pointer to a drm_crtc 1983 * 1984 * Failure to add debugfs entries should generally be ignored. 1985 */ 1986 void intel_crtc_debugfs_add(struct drm_crtc *crtc) 1987 { 1988 if (!crtc->debugfs_entry) 1989 return; 1990 1991 crtc_updates_add(crtc); 1992 intel_drrs_crtc_debugfs_add(to_intel_crtc(crtc)); 1993 intel_fbc_crtc_debugfs_add(to_intel_crtc(crtc)); 1994 1995 debugfs_create_file("i915_current_bpc", 0444, crtc->debugfs_entry, crtc, 1996 &i915_current_bpc_fops); 1997 } 1998