1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #include "i915_reg_defs.h" 31 #include "intel_display_limits.h" 32 33 struct drm_atomic_state; 34 struct drm_device; 35 struct drm_display_mode; 36 struct drm_encoder; 37 struct drm_format_info; 38 struct drm_modeset_acquire_ctx; 39 struct intel_atomic_state; 40 struct intel_crtc; 41 struct intel_crtc_state; 42 struct intel_digital_port; 43 struct intel_display; 44 struct intel_encoder; 45 struct intel_link_m_n; 46 struct intel_plane; 47 struct intel_plane_state; 48 struct intel_power_domain_mask; 49 50 #define pipe_name(p) ((p) + 'A') 51 52 static inline const char *transcoder_name(enum transcoder transcoder) 53 { 54 switch (transcoder) { 55 case TRANSCODER_A: 56 return "A"; 57 case TRANSCODER_B: 58 return "B"; 59 case TRANSCODER_C: 60 return "C"; 61 case TRANSCODER_D: 62 return "D"; 63 case TRANSCODER_EDP: 64 return "EDP"; 65 case TRANSCODER_DSI_A: 66 return "DSI A"; 67 case TRANSCODER_DSI_C: 68 return "DSI C"; 69 default: 70 return "<invalid>"; 71 } 72 } 73 74 static inline bool transcoder_is_dsi(enum transcoder transcoder) 75 { 76 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 77 } 78 79 #define plane_name(p) ((p) + 'A') 80 81 #define for_each_plane_id_on_crtc(__crtc, __p) \ 82 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 83 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 84 85 #define for_each_dbuf_slice(__dev_priv, __slice) \ 86 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 87 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice)) 88 89 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 90 for_each_dbuf_slice((__dev_priv), (__slice)) \ 91 for_each_if((__mask) & BIT(__slice)) 92 93 #define port_name(p) ((p) + 'A') 94 95 /* 96 * Ports identifier referenced from other drivers. 97 * Expected to remain stable over time 98 */ 99 static inline const char *port_identifier(enum port port) 100 { 101 switch (port) { 102 case PORT_A: 103 return "Port A"; 104 case PORT_B: 105 return "Port B"; 106 case PORT_C: 107 return "Port C"; 108 case PORT_D: 109 return "Port D"; 110 case PORT_E: 111 return "Port E"; 112 case PORT_F: 113 return "Port F"; 114 case PORT_G: 115 return "Port G"; 116 case PORT_H: 117 return "Port H"; 118 case PORT_I: 119 return "Port I"; 120 default: 121 return "<invalid>"; 122 } 123 } 124 125 enum tc_port { 126 TC_PORT_NONE = -1, 127 128 TC_PORT_1 = 0, 129 TC_PORT_2, 130 TC_PORT_3, 131 TC_PORT_4, 132 TC_PORT_5, 133 TC_PORT_6, 134 135 I915_MAX_TC_PORTS 136 }; 137 138 enum aux_ch { 139 AUX_CH_NONE = -1, 140 141 AUX_CH_A, 142 AUX_CH_B, 143 AUX_CH_C, 144 AUX_CH_D, 145 AUX_CH_E, /* ICL+ */ 146 AUX_CH_F, 147 AUX_CH_G, 148 AUX_CH_H, 149 AUX_CH_I, 150 151 /* tgl+ */ 152 AUX_CH_USBC1 = AUX_CH_D, 153 AUX_CH_USBC2, 154 AUX_CH_USBC3, 155 AUX_CH_USBC4, 156 AUX_CH_USBC5, 157 AUX_CH_USBC6, 158 159 /* XE_LPD repositions D/E offsets and bitfields */ 160 AUX_CH_D_XELPD = AUX_CH_USBC5, 161 AUX_CH_E_XELPD, 162 }; 163 164 enum phy { 165 PHY_NONE = -1, 166 167 PHY_A = 0, 168 PHY_B, 169 PHY_C, 170 PHY_D, 171 PHY_E, 172 PHY_F, 173 PHY_G, 174 PHY_H, 175 PHY_I, 176 177 I915_MAX_PHYS 178 }; 179 180 #define phy_name(a) ((a) + 'A') 181 182 enum phy_fia { 183 FIA1, 184 FIA2, 185 FIA3, 186 }; 187 188 #define for_each_hpd_pin(__pin) \ 189 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 190 191 #define for_each_pipe(__dev_priv, __p) \ 192 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 193 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 194 195 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 196 for_each_pipe(__dev_priv, __p) \ 197 for_each_if((__mask) & BIT(__p)) 198 199 #define for_each_cpu_transcoder(__dev_priv, __t) \ 200 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 201 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 202 203 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 204 for_each_cpu_transcoder(__dev_priv, __t) \ 205 for_each_if ((__mask) & BIT(__t)) 206 207 #define for_each_sprite(__dev_priv, __p, __s) \ 208 for ((__s) = 0; \ 209 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 210 (__s)++) 211 212 #define for_each_port(__port) \ 213 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 214 215 #define for_each_port_masked(__port, __ports_mask) \ 216 for_each_port(__port) \ 217 for_each_if((__ports_mask) & BIT(__port)) 218 219 #define for_each_phy_masked(__phy, __phys_mask) \ 220 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 221 for_each_if((__phys_mask) & BIT(__phy)) 222 223 #define for_each_intel_plane(dev, intel_plane) \ 224 list_for_each_entry(intel_plane, \ 225 &(dev)->mode_config.plane_list, \ 226 base.head) 227 228 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 229 list_for_each_entry(intel_plane, \ 230 &(dev)->mode_config.plane_list, \ 231 base.head) \ 232 for_each_if((plane_mask) & \ 233 drm_plane_mask(&intel_plane->base)) 234 235 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 236 list_for_each_entry(intel_plane, \ 237 &(dev)->mode_config.plane_list, \ 238 base.head) \ 239 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 240 241 #define for_each_intel_crtc(dev, intel_crtc) \ 242 list_for_each_entry(intel_crtc, \ 243 &(dev)->mode_config.crtc_list, \ 244 base.head) 245 246 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 247 list_for_each_entry(intel_crtc, \ 248 &(dev)->mode_config.crtc_list, \ 249 base.head) \ 250 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 251 252 #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ 253 list_for_each_entry_reverse((intel_crtc), \ 254 &(dev)->mode_config.crtc_list, \ 255 base.head) \ 256 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe)) 257 258 #define for_each_intel_encoder(dev, intel_encoder) \ 259 list_for_each_entry(intel_encoder, \ 260 &(dev)->mode_config.encoder_list, \ 261 base.head) 262 263 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 264 list_for_each_entry(intel_encoder, \ 265 &(dev)->mode_config.encoder_list, \ 266 base.head) \ 267 for_each_if((encoder_mask) & \ 268 drm_encoder_mask(&intel_encoder->base)) 269 270 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 271 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 272 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 273 intel_encoder_can_psr(intel_encoder)) 274 275 #define for_each_intel_dp(dev, intel_encoder) \ 276 for_each_intel_encoder(dev, intel_encoder) \ 277 for_each_if(intel_encoder_is_dp(intel_encoder)) 278 279 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 280 for_each_intel_encoder((dev), (intel_encoder)) \ 281 for_each_if(intel_encoder_can_psr(intel_encoder)) 282 283 #define for_each_intel_connector_iter(intel_connector, iter) \ 284 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 285 286 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 287 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 288 for_each_if((intel_encoder)->base.crtc == (__crtc)) 289 290 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 291 for ((__i) = 0; \ 292 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 293 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 294 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 295 (__i)++) \ 296 for_each_if(plane) 297 298 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 299 for ((__i) = 0; \ 300 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 301 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 302 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ 303 (__i)++) \ 304 for_each_if(crtc) 305 306 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 307 for ((__i) = 0; \ 308 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 309 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 310 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 311 (__i)++) \ 312 for_each_if(plane) 313 314 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 315 for ((__i) = 0; \ 316 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 317 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 318 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 319 (__i)++) \ 320 for_each_if(crtc) 321 322 #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \ 323 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 324 (__i) >= 0 && \ 325 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 326 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 327 (__i)--) \ 328 for_each_if(crtc) 329 330 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 331 for ((__i) = 0; \ 332 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 333 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 334 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 335 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 336 (__i)++) \ 337 for_each_if(plane) 338 339 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 340 for ((__i) = 0; \ 341 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 342 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 343 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 344 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 345 (__i)++) \ 346 for_each_if(crtc) 347 348 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 349 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 350 (__i) >= 0 && \ 351 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 352 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 353 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 354 (__i)--) \ 355 for_each_if(crtc) 356 357 #define intel_atomic_crtc_state_for_each_plane_state( \ 358 plane, plane_state, \ 359 crtc_state) \ 360 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 361 ((crtc_state)->uapi.plane_mask)) \ 362 for_each_if ((plane_state = \ 363 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 364 365 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 366 for ((__i) = 0; \ 367 (__i) < (__state)->base.num_connector; \ 368 (__i)++) \ 369 for_each_if ((__state)->base.connectors[__i].ptr && \ 370 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 371 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 372 373 #define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \ 374 for ((i) = 0; \ 375 (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \ 376 (i)++) \ 377 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i)) 378 379 #define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \ 380 for ((i) = (I915_MAX_PIPES * 2 - 1); \ 381 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \ 382 (i)--) \ 383 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i)) 384 385 #define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \ 386 for_each_crtc_in_masks(display, crtc, \ 387 _intel_modeset_primary_pipes(crtc_state), \ 388 _intel_modeset_secondary_pipes(crtc_state), \ 389 i) 390 391 #define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \ 392 for_each_crtc_in_masks_reverse(display, crtc, \ 393 _intel_modeset_primary_pipes(crtc_state), \ 394 _intel_modeset_secondary_pipes(crtc_state), \ 395 i) 396 397 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 398 u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, 399 u8 enabled_pipes); 400 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 401 u8 active_pipes); 402 void intel_link_compute_m_n(u16 bpp, int nlanes, 403 int pixel_clock, int link_clock, 404 int bw_overhead, 405 struct intel_link_m_n *m_n); 406 u32 intel_plane_fb_max_stride(struct intel_display *display, 407 const struct drm_format_info *info, 408 u64 modifier); 409 u32 intel_dumb_fb_max_stride(struct drm_device *drm, 410 u32 pixel_format, u64 modifier); 411 enum drm_mode_status 412 intel_mode_valid_max_plane_size(struct intel_display *display, 413 const struct drm_display_mode *mode, 414 int num_joined_pipes); 415 enum drm_mode_status 416 intel_cpu_transcoder_mode_valid(struct intel_display *display, 417 const struct drm_display_mode *mode); 418 enum phy intel_port_to_phy(struct intel_display *display, enum port port); 419 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 420 bool is_trans_port_sync_master(const struct intel_crtc_state *state); 421 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); 422 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); 423 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state); 424 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state); 425 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state); 426 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state); 427 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state); 428 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state); 429 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); 430 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state); 431 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state); 432 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); 433 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 434 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 435 const struct intel_crtc_state *pipe_config, 436 bool fastset); 437 438 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 439 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 440 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 441 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 442 void i830_enable_pipe(struct intel_display *display, enum pipe pipe); 443 void i830_disable_pipe(struct intel_display *display, enum pipe pipe); 444 bool intel_has_pending_fb_unpin(struct intel_display *display); 445 void intel_encoder_destroy(struct drm_encoder *encoder); 446 struct drm_display_mode * 447 intel_encoder_current_mode(struct intel_encoder *encoder); 448 void intel_encoder_get_config(struct intel_encoder *encoder, 449 struct intel_crtc_state *crtc_state); 450 bool intel_phy_is_combo(struct intel_display *display, enum phy phy); 451 bool intel_phy_is_tc(struct intel_display *display, enum phy phy); 452 bool intel_phy_is_snps(struct intel_display *display, enum phy phy); 453 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port); 454 455 enum phy intel_encoder_to_phy(struct intel_encoder *encoder); 456 bool intel_encoder_is_combo(struct intel_encoder *encoder); 457 bool intel_encoder_is_snps(struct intel_encoder *encoder); 458 bool intel_encoder_is_tc(struct intel_encoder *encoder); 459 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder); 460 461 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 462 463 bool intel_fuzzy_clock_check(int clock1, int clock2); 464 465 void intel_zero_m_n(struct intel_link_m_n *m_n); 466 void intel_set_m_n(struct intel_display *display, 467 const struct intel_link_m_n *m_n, 468 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 469 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 470 void intel_get_m_n(struct intel_display *display, 471 struct intel_link_m_n *m_n, 472 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 473 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 474 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 475 enum transcoder transcoder); 476 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 477 enum transcoder cpu_transcoder, 478 const struct intel_link_m_n *m_n); 479 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 480 enum transcoder cpu_transcoder, 481 const struct intel_link_m_n *m_n); 482 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 483 enum transcoder cpu_transcoder, 484 struct intel_link_m_n *m_n); 485 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 486 enum transcoder cpu_transcoder, 487 struct intel_link_m_n *m_n); 488 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 489 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 490 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 491 enum intel_display_power_domain 492 intel_aux_power_domain(struct intel_digital_port *dig_port); 493 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 494 struct intel_crtc_state *crtc_state); 495 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc); 496 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 497 498 struct intel_encoder * 499 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 500 const struct intel_crtc_state *crtc_state); 501 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 502 struct intel_plane *plane); 503 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 504 struct intel_plane_state *plane_state, 505 bool visible); 506 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 507 508 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 509 struct intel_crtc *crtc); 510 511 int intel_display_min_pipe_bpp(void); 512 int intel_display_max_pipe_bpp(struct intel_display *display); 513 514 /* modesetting */ 515 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 516 const char *reason, u8 pipe_mask); 517 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 518 const char *reason); 519 int intel_modeset_commit_pipes(struct intel_display *display, 520 u8 pipe_mask, 521 struct drm_modeset_acquire_ctx *ctx); 522 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 523 struct intel_power_domain_mask *old_domains); 524 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 525 struct intel_power_domain_mask *domains); 526 527 /* interface for intel_display_driver.c */ 528 void intel_init_display_hooks(struct intel_display *display); 529 void intel_setup_outputs(struct intel_display *display); 530 int intel_initial_commit(struct intel_display *display); 531 void intel_panel_sanitize_ssc(struct intel_display *display); 532 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 533 const struct drm_display_mode *mode); 534 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 535 bool nonblock); 536 537 /* modesetting asserts */ 538 void assert_transcoder(struct intel_display *display, 539 enum transcoder cpu_transcoder, bool state); 540 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 541 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 542 543 bool assert_port_valid(struct intel_display *display, enum port port); 544 545 /* 546 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw 547 * state sanity checks to check for unexpected conditions which may not 548 * necessarily be a user visible problem. This will either drm_WARN() or 549 * drm_err() depending on the verbose_state_checks module param, to enable 550 * distros and users to tailor their preferred amount of i915 abrt spam. 551 */ 552 #define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \ 553 int __ret_warn_on = !!(condition); \ 554 if (unlikely(__ret_warn_on)) \ 555 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \ 556 drm_err((__display)->drm, format); \ 557 unlikely(__ret_warn_on); \ 558 }) 559 560 bool intel_scanout_needs_vtd_wa(struct intel_display *display); 561 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state); 562 563 #endif 564