1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 enum link_m_n_set; 31 struct dpll; 32 struct drm_connector; 33 struct drm_device; 34 struct drm_display_mode; 35 struct drm_encoder; 36 struct drm_file; 37 struct drm_format_info; 38 struct drm_framebuffer; 39 struct drm_i915_error_state_buf; 40 struct drm_i915_gem_object; 41 struct drm_i915_private; 42 struct drm_mode_fb_cmd2; 43 struct drm_modeset_acquire_ctx; 44 struct drm_plane; 45 struct drm_plane_state; 46 struct i915_ggtt_view; 47 struct intel_atomic_state; 48 struct intel_crtc; 49 struct intel_crtc_state; 50 struct intel_crtc_state; 51 struct intel_digital_port; 52 struct intel_dp; 53 struct intel_encoder; 54 struct intel_load_detect_pipe; 55 struct intel_plane; 56 struct intel_plane_state; 57 struct intel_remapped_info; 58 struct intel_rotation_info; 59 60 enum i915_gpio { 61 GPIOA, 62 GPIOB, 63 GPIOC, 64 GPIOD, 65 GPIOE, 66 GPIOF, 67 GPIOG, 68 GPIOH, 69 __GPIOI_UNUSED, 70 GPIOJ, 71 GPIOK, 72 GPIOL, 73 GPIOM, 74 GPION, 75 GPIOO, 76 }; 77 78 /* 79 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 80 * rest have consecutive values and match the enum values of transcoders 81 * with a 1:1 transcoder -> pipe mapping. 82 */ 83 enum pipe { 84 INVALID_PIPE = -1, 85 86 PIPE_A = 0, 87 PIPE_B, 88 PIPE_C, 89 PIPE_D, 90 _PIPE_EDP, 91 92 I915_MAX_PIPES = _PIPE_EDP 93 }; 94 95 #define pipe_name(p) ((p) + 'A') 96 97 enum transcoder { 98 INVALID_TRANSCODER = -1, 99 /* 100 * The following transcoders have a 1:1 transcoder -> pipe mapping, 101 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 102 * rest have consecutive values and match the enum values of the pipes 103 * they map to. 104 */ 105 TRANSCODER_A = PIPE_A, 106 TRANSCODER_B = PIPE_B, 107 TRANSCODER_C = PIPE_C, 108 TRANSCODER_D = PIPE_D, 109 110 /* 111 * The following transcoders can map to any pipe, their enum value 112 * doesn't need to stay fixed. 113 */ 114 TRANSCODER_EDP, 115 TRANSCODER_DSI_0, 116 TRANSCODER_DSI_1, 117 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 118 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 119 120 I915_MAX_TRANSCODERS 121 }; 122 123 static inline const char *transcoder_name(enum transcoder transcoder) 124 { 125 switch (transcoder) { 126 case TRANSCODER_A: 127 return "A"; 128 case TRANSCODER_B: 129 return "B"; 130 case TRANSCODER_C: 131 return "C"; 132 case TRANSCODER_D: 133 return "D"; 134 case TRANSCODER_EDP: 135 return "EDP"; 136 case TRANSCODER_DSI_A: 137 return "DSI A"; 138 case TRANSCODER_DSI_C: 139 return "DSI C"; 140 default: 141 return "<invalid>"; 142 } 143 } 144 145 static inline bool transcoder_is_dsi(enum transcoder transcoder) 146 { 147 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 148 } 149 150 /* 151 * Global legacy plane identifier. Valid only for primary/sprite 152 * planes on pre-g4x, and only for primary planes on g4x-bdw. 153 */ 154 enum i9xx_plane_id { 155 PLANE_A, 156 PLANE_B, 157 PLANE_C, 158 }; 159 160 #define plane_name(p) ((p) + 'A') 161 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 162 163 /* 164 * Per-pipe plane identifier. 165 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 166 * number of planes per CRTC. Not all platforms really have this many planes, 167 * which means some arrays of size I915_MAX_PLANES may have unused entries 168 * between the topmost sprite plane and the cursor plane. 169 * 170 * This is expected to be passed to various register macros 171 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 172 */ 173 enum plane_id { 174 PLANE_PRIMARY, 175 PLANE_SPRITE0, 176 PLANE_SPRITE1, 177 PLANE_SPRITE2, 178 PLANE_SPRITE3, 179 PLANE_SPRITE4, 180 PLANE_SPRITE5, 181 PLANE_CURSOR, 182 183 I915_MAX_PLANES, 184 }; 185 186 #define for_each_plane_id_on_crtc(__crtc, __p) \ 187 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 188 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 189 190 enum port { 191 PORT_NONE = -1, 192 193 PORT_A = 0, 194 PORT_B, 195 PORT_C, 196 PORT_D, 197 PORT_E, 198 PORT_F, 199 PORT_G, 200 PORT_H, 201 PORT_I, 202 203 I915_MAX_PORTS 204 }; 205 206 #define port_name(p) ((p) + 'A') 207 208 /* 209 * Ports identifier referenced from other drivers. 210 * Expected to remain stable over time 211 */ 212 static inline const char *port_identifier(enum port port) 213 { 214 switch (port) { 215 case PORT_A: 216 return "Port A"; 217 case PORT_B: 218 return "Port B"; 219 case PORT_C: 220 return "Port C"; 221 case PORT_D: 222 return "Port D"; 223 case PORT_E: 224 return "Port E"; 225 case PORT_F: 226 return "Port F"; 227 case PORT_G: 228 return "Port G"; 229 case PORT_H: 230 return "Port H"; 231 case PORT_I: 232 return "Port I"; 233 default: 234 return "<invalid>"; 235 } 236 } 237 238 enum tc_port { 239 PORT_TC_NONE = -1, 240 241 PORT_TC1 = 0, 242 PORT_TC2, 243 PORT_TC3, 244 PORT_TC4, 245 PORT_TC5, 246 PORT_TC6, 247 248 I915_MAX_TC_PORTS 249 }; 250 251 enum tc_port_mode { 252 TC_PORT_TBT_ALT, 253 TC_PORT_DP_ALT, 254 TC_PORT_LEGACY, 255 }; 256 257 enum dpio_channel { 258 DPIO_CH0, 259 DPIO_CH1 260 }; 261 262 enum dpio_phy { 263 DPIO_PHY0, 264 DPIO_PHY1, 265 DPIO_PHY2, 266 }; 267 268 #define I915_NUM_PHYS_VLV 2 269 270 enum aux_ch { 271 AUX_CH_A, 272 AUX_CH_B, 273 AUX_CH_C, 274 AUX_CH_D, 275 AUX_CH_E, /* ICL+ */ 276 AUX_CH_F, 277 AUX_CH_G, 278 }; 279 280 #define aux_ch_name(a) ((a) + 'A') 281 282 /* Used by dp and fdi links */ 283 struct intel_link_m_n { 284 u32 tu; 285 u32 gmch_m; 286 u32 gmch_n; 287 u32 link_m; 288 u32 link_n; 289 }; 290 291 enum phy { 292 PHY_NONE = -1, 293 294 PHY_A = 0, 295 PHY_B, 296 PHY_C, 297 PHY_D, 298 PHY_E, 299 PHY_F, 300 PHY_G, 301 PHY_H, 302 PHY_I, 303 304 I915_MAX_PHYS 305 }; 306 307 #define phy_name(a) ((a) + 'A') 308 309 enum phy_fia { 310 FIA1, 311 FIA2, 312 FIA3, 313 }; 314 315 #define for_each_pipe(__dev_priv, __p) \ 316 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 317 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) 318 319 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 320 for_each_pipe(__dev_priv, __p) \ 321 for_each_if((__mask) & BIT(__p)) 322 323 #define for_each_cpu_transcoder(__dev_priv, __t) \ 324 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 325 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 326 327 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 328 for_each_cpu_transcoder(__dev_priv, __t) \ 329 for_each_if ((__mask) & BIT(__t)) 330 331 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 332 for ((__p) = 0; \ 333 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 334 (__p)++) 335 336 #define for_each_sprite(__dev_priv, __p, __s) \ 337 for ((__s) = 0; \ 338 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 339 (__s)++) 340 341 #define for_each_port(__port) \ 342 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 343 344 #define for_each_port_masked(__port, __ports_mask) \ 345 for_each_port(__port) \ 346 for_each_if((__ports_mask) & BIT(__port)) 347 348 #define for_each_phy_masked(__phy, __phys_mask) \ 349 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 350 for_each_if((__phys_mask) & BIT(__phy)) 351 352 #define for_each_crtc(dev, crtc) \ 353 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 354 355 #define for_each_intel_plane(dev, intel_plane) \ 356 list_for_each_entry(intel_plane, \ 357 &(dev)->mode_config.plane_list, \ 358 base.head) 359 360 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 361 list_for_each_entry(intel_plane, \ 362 &(dev)->mode_config.plane_list, \ 363 base.head) \ 364 for_each_if((plane_mask) & \ 365 drm_plane_mask(&intel_plane->base)) 366 367 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 368 list_for_each_entry(intel_plane, \ 369 &(dev)->mode_config.plane_list, \ 370 base.head) \ 371 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 372 373 #define for_each_intel_crtc(dev, intel_crtc) \ 374 list_for_each_entry(intel_crtc, \ 375 &(dev)->mode_config.crtc_list, \ 376 base.head) 377 378 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 379 list_for_each_entry(intel_crtc, \ 380 &(dev)->mode_config.crtc_list, \ 381 base.head) \ 382 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 383 384 #define for_each_intel_encoder(dev, intel_encoder) \ 385 list_for_each_entry(intel_encoder, \ 386 &(dev)->mode_config.encoder_list, \ 387 base.head) 388 389 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 390 list_for_each_entry(intel_encoder, \ 391 &(dev)->mode_config.encoder_list, \ 392 base.head) \ 393 for_each_if((encoder_mask) & \ 394 drm_encoder_mask(&intel_encoder->base)) 395 396 #define for_each_intel_dp(dev, intel_encoder) \ 397 for_each_intel_encoder(dev, intel_encoder) \ 398 for_each_if(intel_encoder_is_dp(intel_encoder)) 399 400 #define for_each_intel_connector_iter(intel_connector, iter) \ 401 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 402 403 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 404 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 405 for_each_if((intel_encoder)->base.crtc == (__crtc)) 406 407 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 408 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 409 for_each_if((intel_connector)->base.encoder == (__encoder)) 410 411 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 412 for ((__i) = 0; \ 413 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 414 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 415 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 416 (__i)++) \ 417 for_each_if(plane) 418 419 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 420 for ((__i) = 0; \ 421 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 422 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 423 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 424 (__i)++) \ 425 for_each_if(plane) 426 427 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 428 for ((__i) = 0; \ 429 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 430 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 431 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 432 (__i)++) \ 433 for_each_if(crtc) 434 435 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 436 for ((__i) = 0; \ 437 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 438 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 439 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 440 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 441 (__i)++) \ 442 for_each_if(plane) 443 444 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 445 for ((__i) = 0; \ 446 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 447 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 448 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 449 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 450 (__i)++) \ 451 for_each_if(crtc) 452 453 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 454 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 455 (__i) >= 0 && \ 456 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 457 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 458 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 459 (__i)--) \ 460 for_each_if(crtc) 461 462 #define intel_atomic_crtc_state_for_each_plane_state( \ 463 plane, plane_state, \ 464 crtc_state) \ 465 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 466 ((crtc_state)->uapi.plane_mask)) \ 467 for_each_if ((plane_state = \ 468 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 469 470 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 471 for ((__i) = 0; \ 472 (__i) < (__state)->base.num_connector; \ 473 (__i)++) \ 474 for_each_if ((__state)->base.connectors[__i].ptr && \ 475 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 476 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 477 478 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 479 u8 active_pipes); 480 void intel_link_compute_m_n(u16 bpp, int nlanes, 481 int pixel_clock, int link_clock, 482 struct intel_link_m_n *m_n, 483 bool constant_n, bool fec_enable); 484 bool is_ccs_modifier(u64 modifier); 485 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); 486 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 487 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 488 u32 pixel_format, u64 modifier); 489 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 490 enum drm_mode_status 491 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 492 const struct drm_display_mode *mode); 493 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 494 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 495 496 void intel_plane_destroy(struct drm_plane *plane); 497 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state); 498 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); 499 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 500 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 501 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 502 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 503 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 504 const char *name, u32 reg, int ref_freq); 505 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 506 const char *name, u32 reg); 507 void lpt_pch_enable(const struct intel_crtc_state *crtc_state); 508 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 509 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 510 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 511 unsigned int intel_fb_xy_to_linear(int x, int y, 512 const struct intel_plane_state *state, 513 int plane); 514 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 515 int color_plane, unsigned int height); 516 void intel_add_fb_offsets(int *x, int *y, 517 const struct intel_plane_state *state, int plane); 518 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 519 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 520 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 521 int intel_display_suspend(struct drm_device *dev); 522 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 523 void intel_encoder_destroy(struct drm_encoder *encoder); 524 struct drm_display_mode * 525 intel_encoder_current_mode(struct intel_encoder *encoder); 526 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 527 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 528 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 529 enum port port); 530 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 531 struct drm_file *file_priv); 532 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 533 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); 534 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); 535 536 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 537 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 538 struct intel_digital_port *dport, 539 unsigned int expected_mask); 540 int intel_get_load_detect_pipe(struct drm_connector *connector, 541 struct intel_load_detect_pipe *old, 542 struct drm_modeset_acquire_ctx *ctx); 543 void intel_release_load_detect_pipe(struct drm_connector *connector, 544 struct intel_load_detect_pipe *old, 545 struct drm_modeset_acquire_ctx *ctx); 546 struct i915_vma * 547 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 548 const struct i915_ggtt_view *view, 549 bool uses_fence, 550 unsigned long *out_flags); 551 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 552 struct drm_framebuffer * 553 intel_framebuffer_create(struct drm_i915_gem_object *obj, 554 struct drm_mode_fb_cmd2 *mode_cmd); 555 int intel_prepare_plane_fb(struct drm_plane *plane, 556 struct drm_plane_state *new_state); 557 void intel_cleanup_plane_fb(struct drm_plane *plane, 558 struct drm_plane_state *old_state); 559 560 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 561 enum pipe pipe); 562 563 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 564 const struct dpll *dpll); 565 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 566 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 567 bool intel_fuzzy_clock_check(int clock1, int clock2); 568 569 void intel_prepare_reset(struct drm_i915_private *dev_priv); 570 void intel_finish_reset(struct drm_i915_private *dev_priv); 571 void intel_dp_get_m_n(struct intel_crtc *crtc, 572 struct intel_crtc_state *pipe_config); 573 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 574 enum link_m_n_set m_n); 575 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 576 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 577 struct dpll *best_clock); 578 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 579 580 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 581 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 582 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 583 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 584 enum intel_display_power_domain 585 intel_aux_power_domain(struct intel_digital_port *dig_port); 586 enum intel_display_power_domain 587 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch); 588 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 589 struct intel_crtc_state *pipe_config); 590 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 591 struct intel_crtc_state *crtc_state); 592 593 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 594 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); 595 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 596 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 597 const struct intel_plane_state *plane_state); 598 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 599 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 600 const struct intel_plane_state *plane_state); 601 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 602 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 603 int plane); 604 int skl_check_plane_surface(struct intel_plane_state *plane_state); 605 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 606 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 607 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 608 u32 pixel_format, u64 modifier, 609 unsigned int rotation); 610 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 611 612 struct intel_display_error_state * 613 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 614 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 615 struct intel_display_error_state *error); 616 617 bool 618 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 619 uint64_t modifier); 620 621 /* modesetting */ 622 void intel_modeset_init_hw(struct drm_i915_private *i915); 623 int intel_modeset_init_noirq(struct drm_i915_private *i915); 624 int intel_modeset_init(struct drm_i915_private *i915); 625 void intel_modeset_driver_remove(struct drm_i915_private *i915); 626 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 627 void intel_display_resume(struct drm_device *dev); 628 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 629 630 /* modesetting asserts */ 631 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 632 enum pipe pipe); 633 void assert_pll(struct drm_i915_private *dev_priv, 634 enum pipe pipe, bool state); 635 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 636 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 637 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 638 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 639 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 640 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 641 enum pipe pipe, bool state); 642 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 643 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 644 void assert_pipe(struct drm_i915_private *dev_priv, 645 enum transcoder cpu_transcoder, bool state); 646 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true) 647 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false) 648 649 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 650 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 651 * which may not necessarily be a user visible problem. This will either 652 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 653 * enable distros and users to tailor their preferred amount of i915 abrt 654 * spam. 655 */ 656 #define I915_STATE_WARN(condition, format...) ({ \ 657 int __ret_warn_on = !!(condition); \ 658 if (unlikely(__ret_warn_on)) \ 659 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 660 DRM_ERROR(format); \ 661 unlikely(__ret_warn_on); \ 662 }) 663 664 #define I915_STATE_WARN_ON(x) \ 665 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 666 667 #endif 668