1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #include "i915_reg_defs.h" 31 #include "intel_display_limits.h" 32 33 enum drm_scaling_filter; 34 struct dpll; 35 struct drm_atomic_state; 36 struct drm_connector; 37 struct drm_device; 38 struct drm_display_mode; 39 struct drm_encoder; 40 struct drm_file; 41 struct drm_format_info; 42 struct drm_framebuffer; 43 struct drm_i915_private; 44 struct drm_mode_fb_cmd2; 45 struct drm_modeset_acquire_ctx; 46 struct drm_plane; 47 struct drm_plane_state; 48 struct i915_address_space; 49 struct i915_gtt_view; 50 struct intel_atomic_state; 51 struct intel_crtc; 52 struct intel_crtc_state; 53 struct intel_digital_port; 54 struct intel_display; 55 struct intel_dp; 56 struct intel_encoder; 57 struct intel_initial_plane_config; 58 struct intel_link_m_n; 59 struct intel_plane; 60 struct intel_plane_state; 61 struct intel_power_domain_mask; 62 struct pci_dev; 63 struct work_struct; 64 65 66 #define pipe_name(p) ((p) + 'A') 67 68 static inline const char *transcoder_name(enum transcoder transcoder) 69 { 70 switch (transcoder) { 71 case TRANSCODER_A: 72 return "A"; 73 case TRANSCODER_B: 74 return "B"; 75 case TRANSCODER_C: 76 return "C"; 77 case TRANSCODER_D: 78 return "D"; 79 case TRANSCODER_EDP: 80 return "EDP"; 81 case TRANSCODER_DSI_A: 82 return "DSI A"; 83 case TRANSCODER_DSI_C: 84 return "DSI C"; 85 default: 86 return "<invalid>"; 87 } 88 } 89 90 static inline bool transcoder_is_dsi(enum transcoder transcoder) 91 { 92 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 93 } 94 95 #define plane_name(p) ((p) + 'A') 96 97 #define for_each_plane_id_on_crtc(__crtc, __p) \ 98 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 99 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 100 101 #define for_each_dbuf_slice(__dev_priv, __slice) \ 102 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 103 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice)) 104 105 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 106 for_each_dbuf_slice((__dev_priv), (__slice)) \ 107 for_each_if((__mask) & BIT(__slice)) 108 109 #define port_name(p) ((p) + 'A') 110 111 /* 112 * Ports identifier referenced from other drivers. 113 * Expected to remain stable over time 114 */ 115 static inline const char *port_identifier(enum port port) 116 { 117 switch (port) { 118 case PORT_A: 119 return "Port A"; 120 case PORT_B: 121 return "Port B"; 122 case PORT_C: 123 return "Port C"; 124 case PORT_D: 125 return "Port D"; 126 case PORT_E: 127 return "Port E"; 128 case PORT_F: 129 return "Port F"; 130 case PORT_G: 131 return "Port G"; 132 case PORT_H: 133 return "Port H"; 134 case PORT_I: 135 return "Port I"; 136 default: 137 return "<invalid>"; 138 } 139 } 140 141 enum tc_port { 142 TC_PORT_NONE = -1, 143 144 TC_PORT_1 = 0, 145 TC_PORT_2, 146 TC_PORT_3, 147 TC_PORT_4, 148 TC_PORT_5, 149 TC_PORT_6, 150 151 I915_MAX_TC_PORTS 152 }; 153 154 enum aux_ch { 155 AUX_CH_NONE = -1, 156 157 AUX_CH_A, 158 AUX_CH_B, 159 AUX_CH_C, 160 AUX_CH_D, 161 AUX_CH_E, /* ICL+ */ 162 AUX_CH_F, 163 AUX_CH_G, 164 AUX_CH_H, 165 AUX_CH_I, 166 167 /* tgl+ */ 168 AUX_CH_USBC1 = AUX_CH_D, 169 AUX_CH_USBC2, 170 AUX_CH_USBC3, 171 AUX_CH_USBC4, 172 AUX_CH_USBC5, 173 AUX_CH_USBC6, 174 175 /* XE_LPD repositions D/E offsets and bitfields */ 176 AUX_CH_D_XELPD = AUX_CH_USBC5, 177 AUX_CH_E_XELPD, 178 }; 179 180 enum phy { 181 PHY_NONE = -1, 182 183 PHY_A = 0, 184 PHY_B, 185 PHY_C, 186 PHY_D, 187 PHY_E, 188 PHY_F, 189 PHY_G, 190 PHY_H, 191 PHY_I, 192 193 I915_MAX_PHYS 194 }; 195 196 #define phy_name(a) ((a) + 'A') 197 198 enum phy_fia { 199 FIA1, 200 FIA2, 201 FIA3, 202 }; 203 204 #define for_each_hpd_pin(__pin) \ 205 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 206 207 #define for_each_pipe(__dev_priv, __p) \ 208 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 209 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 210 211 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 212 for_each_pipe(__dev_priv, __p) \ 213 for_each_if((__mask) & BIT(__p)) 214 215 #define for_each_cpu_transcoder(__dev_priv, __t) \ 216 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 217 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 218 219 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 220 for_each_cpu_transcoder(__dev_priv, __t) \ 221 for_each_if ((__mask) & BIT(__t)) 222 223 #define for_each_sprite(__dev_priv, __p, __s) \ 224 for ((__s) = 0; \ 225 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 226 (__s)++) 227 228 #define for_each_port(__port) \ 229 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 230 231 #define for_each_port_masked(__port, __ports_mask) \ 232 for_each_port(__port) \ 233 for_each_if((__ports_mask) & BIT(__port)) 234 235 #define for_each_phy_masked(__phy, __phys_mask) \ 236 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 237 for_each_if((__phys_mask) & BIT(__phy)) 238 239 #define for_each_intel_plane(dev, intel_plane) \ 240 list_for_each_entry(intel_plane, \ 241 &(dev)->mode_config.plane_list, \ 242 base.head) 243 244 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 245 list_for_each_entry(intel_plane, \ 246 &(dev)->mode_config.plane_list, \ 247 base.head) \ 248 for_each_if((plane_mask) & \ 249 drm_plane_mask(&intel_plane->base)) 250 251 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 252 list_for_each_entry(intel_plane, \ 253 &(dev)->mode_config.plane_list, \ 254 base.head) \ 255 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 256 257 #define for_each_intel_crtc(dev, intel_crtc) \ 258 list_for_each_entry(intel_crtc, \ 259 &(dev)->mode_config.crtc_list, \ 260 base.head) 261 262 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 263 list_for_each_entry(intel_crtc, \ 264 &(dev)->mode_config.crtc_list, \ 265 base.head) \ 266 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 267 268 #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ 269 list_for_each_entry_reverse((intel_crtc), \ 270 &(dev)->mode_config.crtc_list, \ 271 base.head) \ 272 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe)) 273 274 #define for_each_intel_encoder(dev, intel_encoder) \ 275 list_for_each_entry(intel_encoder, \ 276 &(dev)->mode_config.encoder_list, \ 277 base.head) 278 279 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 280 list_for_each_entry(intel_encoder, \ 281 &(dev)->mode_config.encoder_list, \ 282 base.head) \ 283 for_each_if((encoder_mask) & \ 284 drm_encoder_mask(&intel_encoder->base)) 285 286 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 287 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 288 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 289 intel_encoder_can_psr(intel_encoder)) 290 291 #define for_each_intel_dp(dev, intel_encoder) \ 292 for_each_intel_encoder(dev, intel_encoder) \ 293 for_each_if(intel_encoder_is_dp(intel_encoder)) 294 295 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 296 for_each_intel_encoder((dev), (intel_encoder)) \ 297 for_each_if(intel_encoder_can_psr(intel_encoder)) 298 299 #define for_each_intel_connector_iter(intel_connector, iter) \ 300 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 301 302 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 303 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 304 for_each_if((intel_encoder)->base.crtc == (__crtc)) 305 306 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 307 for ((__i) = 0; \ 308 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 309 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 310 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 311 (__i)++) \ 312 for_each_if(plane) 313 314 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 315 for ((__i) = 0; \ 316 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 317 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 318 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ 319 (__i)++) \ 320 for_each_if(crtc) 321 322 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 323 for ((__i) = 0; \ 324 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 325 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 326 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 327 (__i)++) \ 328 for_each_if(plane) 329 330 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 331 for ((__i) = 0; \ 332 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 333 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 334 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 335 (__i)++) \ 336 for_each_if(crtc) 337 338 #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \ 339 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 340 (__i) >= 0 && \ 341 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 342 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 343 (__i)--) \ 344 for_each_if(crtc) 345 346 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 347 for ((__i) = 0; \ 348 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 349 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 350 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 351 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 352 (__i)++) \ 353 for_each_if(plane) 354 355 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 356 for ((__i) = 0; \ 357 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 358 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 359 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 360 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 361 (__i)++) \ 362 for_each_if(crtc) 363 364 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 365 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 366 (__i) >= 0 && \ 367 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 368 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 369 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 370 (__i)--) \ 371 for_each_if(crtc) 372 373 #define intel_atomic_crtc_state_for_each_plane_state( \ 374 plane, plane_state, \ 375 crtc_state) \ 376 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 377 ((crtc_state)->uapi.plane_mask)) \ 378 for_each_if ((plane_state = \ 379 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 380 381 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 382 for ((__i) = 0; \ 383 (__i) < (__state)->base.num_connector; \ 384 (__i)++) \ 385 for_each_if ((__state)->base.connectors[__i].ptr && \ 386 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 387 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 388 389 #define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \ 390 for ((i) = 0; \ 391 (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \ 392 (i)++) \ 393 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i)) 394 395 #define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \ 396 for ((i) = (I915_MAX_PIPES * 2 - 1); \ 397 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \ 398 (i)--) \ 399 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i)) 400 401 #define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \ 402 for_each_crtc_in_masks(display, crtc, \ 403 _intel_modeset_primary_pipes(crtc_state), \ 404 _intel_modeset_secondary_pipes(crtc_state), \ 405 i) 406 407 #define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \ 408 for_each_crtc_in_masks_reverse(display, crtc, \ 409 _intel_modeset_primary_pipes(crtc_state), \ 410 _intel_modeset_secondary_pipes(crtc_state), \ 411 i) 412 413 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 414 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 415 u8 active_pipes); 416 void intel_link_compute_m_n(u16 bpp, int nlanes, 417 int pixel_clock, int link_clock, 418 int bw_overhead, 419 struct intel_link_m_n *m_n); 420 u32 intel_plane_fb_max_stride(struct drm_device *drm, 421 u32 pixel_format, u64 modifier); 422 enum drm_mode_status 423 intel_mode_valid_max_plane_size(struct intel_display *display, 424 const struct drm_display_mode *mode, 425 int num_joined_pipes); 426 enum drm_mode_status 427 intel_cpu_transcoder_mode_valid(struct intel_display *display, 428 const struct drm_display_mode *mode); 429 enum phy intel_port_to_phy(struct intel_display *display, enum port port); 430 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 431 bool is_trans_port_sync_master(const struct intel_crtc_state *state); 432 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); 433 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); 434 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state); 435 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state); 436 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state); 437 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state); 438 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state); 439 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state); 440 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); 441 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state); 442 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state); 443 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); 444 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 445 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 446 const struct intel_crtc_state *pipe_config, 447 bool fastset); 448 449 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 450 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 451 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 452 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 453 void i830_enable_pipe(struct intel_display *display, enum pipe pipe); 454 void i830_disable_pipe(struct intel_display *display, enum pipe pipe); 455 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 456 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 457 const char *name, u32 reg, int ref_freq); 458 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 459 const char *name, u32 reg); 460 bool intel_has_pending_fb_unpin(struct intel_display *display); 461 void intel_encoder_destroy(struct drm_encoder *encoder); 462 struct drm_display_mode * 463 intel_encoder_current_mode(struct intel_encoder *encoder); 464 void intel_encoder_get_config(struct intel_encoder *encoder, 465 struct intel_crtc_state *crtc_state); 466 bool intel_phy_is_combo(struct intel_display *display, enum phy phy); 467 bool intel_phy_is_tc(struct intel_display *display, enum phy phy); 468 bool intel_phy_is_snps(struct intel_display *display, enum phy phy); 469 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port); 470 471 enum phy intel_encoder_to_phy(struct intel_encoder *encoder); 472 bool intel_encoder_is_combo(struct intel_encoder *encoder); 473 bool intel_encoder_is_snps(struct intel_encoder *encoder); 474 bool intel_encoder_is_tc(struct intel_encoder *encoder); 475 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder); 476 477 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 478 479 bool intel_fuzzy_clock_check(int clock1, int clock2); 480 481 void intel_zero_m_n(struct intel_link_m_n *m_n); 482 void intel_set_m_n(struct intel_display *display, 483 const struct intel_link_m_n *m_n, 484 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 485 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 486 void intel_get_m_n(struct intel_display *display, 487 struct intel_link_m_n *m_n, 488 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 489 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 490 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 491 enum transcoder transcoder); 492 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 493 enum transcoder cpu_transcoder, 494 const struct intel_link_m_n *m_n); 495 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 496 enum transcoder cpu_transcoder, 497 const struct intel_link_m_n *m_n); 498 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 499 enum transcoder cpu_transcoder, 500 struct intel_link_m_n *m_n); 501 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 502 enum transcoder cpu_transcoder, 503 struct intel_link_m_n *m_n); 504 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 505 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 506 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 507 enum intel_display_power_domain 508 intel_aux_power_domain(struct intel_digital_port *dig_port); 509 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 510 struct intel_crtc_state *crtc_state); 511 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc); 512 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 513 514 struct intel_encoder * 515 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 516 const struct intel_crtc_state *crtc_state); 517 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 518 struct intel_plane *plane); 519 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 520 struct intel_plane_state *plane_state, 521 bool visible); 522 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 523 524 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 525 struct intel_crtc *crtc); 526 527 /* modesetting */ 528 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 529 const char *reason, u8 pipe_mask); 530 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 531 const char *reason); 532 int intel_modeset_commit_pipes(struct intel_display *display, 533 u8 pipe_mask, 534 struct drm_modeset_acquire_ctx *ctx); 535 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 536 struct intel_power_domain_mask *old_domains); 537 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 538 struct intel_power_domain_mask *domains); 539 540 /* interface for intel_display_driver.c */ 541 void intel_init_display_hooks(struct intel_display *display); 542 void intel_setup_outputs(struct intel_display *display); 543 int intel_initial_commit(struct intel_display *display); 544 void intel_panel_sanitize_ssc(struct intel_display *display); 545 void intel_update_czclk(struct intel_display *display); 546 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 547 const struct drm_display_mode *mode); 548 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 549 bool nonblock); 550 551 /* modesetting asserts */ 552 void assert_transcoder(struct intel_display *display, 553 enum transcoder cpu_transcoder, bool state); 554 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 555 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 556 557 bool assert_port_valid(struct intel_display *display, enum port port); 558 559 /* 560 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw 561 * state sanity checks to check for unexpected conditions which may not 562 * necessarily be a user visible problem. This will either drm_WARN() or 563 * drm_err() depending on the verbose_state_checks module param, to enable 564 * distros and users to tailor their preferred amount of i915 abrt spam. 565 */ 566 #define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \ 567 int __ret_warn_on = !!(condition); \ 568 if (unlikely(__ret_warn_on)) \ 569 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \ 570 drm_err((__display)->drm, format); \ 571 unlikely(__ret_warn_on); \ 572 }) 573 574 bool intel_scanout_needs_vtd_wa(struct intel_display *display); 575 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state); 576 577 #endif 578