1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #include "i915_reg_defs.h" 31 32 enum drm_scaling_filter; 33 struct dpll; 34 struct drm_connector; 35 struct drm_device; 36 struct drm_display_mode; 37 struct drm_encoder; 38 struct drm_file; 39 struct drm_format_info; 40 struct drm_framebuffer; 41 struct drm_i915_gem_object; 42 struct drm_i915_private; 43 struct drm_mode_fb_cmd2; 44 struct drm_modeset_acquire_ctx; 45 struct drm_plane; 46 struct drm_plane_state; 47 struct i915_address_space; 48 struct i915_gtt_view; 49 struct intel_atomic_state; 50 struct intel_crtc; 51 struct intel_crtc_state; 52 struct intel_digital_port; 53 struct intel_dp; 54 struct intel_encoder; 55 struct intel_initial_plane_config; 56 struct intel_link_m_n; 57 struct intel_load_detect_pipe; 58 struct intel_plane; 59 struct intel_plane_state; 60 struct intel_power_domain_mask; 61 struct intel_remapped_info; 62 struct intel_rotation_info; 63 struct pci_dev; 64 65 /* 66 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 67 * rest have consecutive values and match the enum values of transcoders 68 * with a 1:1 transcoder -> pipe mapping. 69 */ 70 enum pipe { 71 INVALID_PIPE = -1, 72 73 PIPE_A = 0, 74 PIPE_B, 75 PIPE_C, 76 PIPE_D, 77 _PIPE_EDP, 78 79 I915_MAX_PIPES = _PIPE_EDP 80 }; 81 82 #define pipe_name(p) ((p) + 'A') 83 84 enum transcoder { 85 INVALID_TRANSCODER = -1, 86 /* 87 * The following transcoders have a 1:1 transcoder -> pipe mapping, 88 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 89 * rest have consecutive values and match the enum values of the pipes 90 * they map to. 91 */ 92 TRANSCODER_A = PIPE_A, 93 TRANSCODER_B = PIPE_B, 94 TRANSCODER_C = PIPE_C, 95 TRANSCODER_D = PIPE_D, 96 97 /* 98 * The following transcoders can map to any pipe, their enum value 99 * doesn't need to stay fixed. 100 */ 101 TRANSCODER_EDP, 102 TRANSCODER_DSI_0, 103 TRANSCODER_DSI_1, 104 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 105 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 106 107 I915_MAX_TRANSCODERS 108 }; 109 110 static inline const char *transcoder_name(enum transcoder transcoder) 111 { 112 switch (transcoder) { 113 case TRANSCODER_A: 114 return "A"; 115 case TRANSCODER_B: 116 return "B"; 117 case TRANSCODER_C: 118 return "C"; 119 case TRANSCODER_D: 120 return "D"; 121 case TRANSCODER_EDP: 122 return "EDP"; 123 case TRANSCODER_DSI_A: 124 return "DSI A"; 125 case TRANSCODER_DSI_C: 126 return "DSI C"; 127 default: 128 return "<invalid>"; 129 } 130 } 131 132 static inline bool transcoder_is_dsi(enum transcoder transcoder) 133 { 134 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 135 } 136 137 /* 138 * Global legacy plane identifier. Valid only for primary/sprite 139 * planes on pre-g4x, and only for primary planes on g4x-bdw. 140 */ 141 enum i9xx_plane_id { 142 PLANE_A, 143 PLANE_B, 144 PLANE_C, 145 }; 146 147 #define plane_name(p) ((p) + 'A') 148 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 149 150 /* 151 * Per-pipe plane identifier. 152 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 153 * number of planes per CRTC. Not all platforms really have this many planes, 154 * which means some arrays of size I915_MAX_PLANES may have unused entries 155 * between the topmost sprite plane and the cursor plane. 156 * 157 * This is expected to be passed to various register macros 158 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 159 */ 160 enum plane_id { 161 PLANE_PRIMARY, 162 PLANE_SPRITE0, 163 PLANE_SPRITE1, 164 PLANE_SPRITE2, 165 PLANE_SPRITE3, 166 PLANE_SPRITE4, 167 PLANE_SPRITE5, 168 PLANE_CURSOR, 169 170 I915_MAX_PLANES, 171 }; 172 173 #define for_each_plane_id_on_crtc(__crtc, __p) \ 174 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 175 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 176 177 #define for_each_dbuf_slice(__dev_priv, __slice) \ 178 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 179 for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice)) 180 181 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 182 for_each_dbuf_slice((__dev_priv), (__slice)) \ 183 for_each_if((__mask) & BIT(__slice)) 184 185 enum port { 186 PORT_NONE = -1, 187 188 PORT_A = 0, 189 PORT_B, 190 PORT_C, 191 PORT_D, 192 PORT_E, 193 PORT_F, 194 PORT_G, 195 PORT_H, 196 PORT_I, 197 198 /* tgl+ */ 199 PORT_TC1 = PORT_D, 200 PORT_TC2, 201 PORT_TC3, 202 PORT_TC4, 203 PORT_TC5, 204 PORT_TC6, 205 206 /* XE_LPD repositions D/E offsets and bitfields */ 207 PORT_D_XELPD = PORT_TC5, 208 PORT_E_XELPD, 209 210 I915_MAX_PORTS 211 }; 212 213 #define port_name(p) ((p) + 'A') 214 215 /* 216 * Ports identifier referenced from other drivers. 217 * Expected to remain stable over time 218 */ 219 static inline const char *port_identifier(enum port port) 220 { 221 switch (port) { 222 case PORT_A: 223 return "Port A"; 224 case PORT_B: 225 return "Port B"; 226 case PORT_C: 227 return "Port C"; 228 case PORT_D: 229 return "Port D"; 230 case PORT_E: 231 return "Port E"; 232 case PORT_F: 233 return "Port F"; 234 case PORT_G: 235 return "Port G"; 236 case PORT_H: 237 return "Port H"; 238 case PORT_I: 239 return "Port I"; 240 default: 241 return "<invalid>"; 242 } 243 } 244 245 enum tc_port { 246 TC_PORT_NONE = -1, 247 248 TC_PORT_1 = 0, 249 TC_PORT_2, 250 TC_PORT_3, 251 TC_PORT_4, 252 TC_PORT_5, 253 TC_PORT_6, 254 255 I915_MAX_TC_PORTS 256 }; 257 258 enum tc_port_mode { 259 TC_PORT_DISCONNECTED, 260 TC_PORT_TBT_ALT, 261 TC_PORT_DP_ALT, 262 TC_PORT_LEGACY, 263 }; 264 265 enum aux_ch { 266 AUX_CH_A, 267 AUX_CH_B, 268 AUX_CH_C, 269 AUX_CH_D, 270 AUX_CH_E, /* ICL+ */ 271 AUX_CH_F, 272 AUX_CH_G, 273 AUX_CH_H, 274 AUX_CH_I, 275 276 /* tgl+ */ 277 AUX_CH_USBC1 = AUX_CH_D, 278 AUX_CH_USBC2, 279 AUX_CH_USBC3, 280 AUX_CH_USBC4, 281 AUX_CH_USBC5, 282 AUX_CH_USBC6, 283 284 /* XE_LPD repositions D/E offsets and bitfields */ 285 AUX_CH_D_XELPD = AUX_CH_USBC5, 286 AUX_CH_E_XELPD, 287 }; 288 289 #define aux_ch_name(a) ((a) + 'A') 290 291 enum phy { 292 PHY_NONE = -1, 293 294 PHY_A = 0, 295 PHY_B, 296 PHY_C, 297 PHY_D, 298 PHY_E, 299 PHY_F, 300 PHY_G, 301 PHY_H, 302 PHY_I, 303 304 I915_MAX_PHYS 305 }; 306 307 #define phy_name(a) ((a) + 'A') 308 309 enum phy_fia { 310 FIA1, 311 FIA2, 312 FIA3, 313 }; 314 315 enum hpd_pin { 316 HPD_NONE = 0, 317 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 318 HPD_CRT, 319 HPD_SDVO_B, 320 HPD_SDVO_C, 321 HPD_PORT_A, 322 HPD_PORT_B, 323 HPD_PORT_C, 324 HPD_PORT_D, 325 HPD_PORT_E, 326 HPD_PORT_TC1, 327 HPD_PORT_TC2, 328 HPD_PORT_TC3, 329 HPD_PORT_TC4, 330 HPD_PORT_TC5, 331 HPD_PORT_TC6, 332 333 HPD_NUM_PINS 334 }; 335 336 #define for_each_hpd_pin(__pin) \ 337 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 338 339 #define for_each_pipe(__dev_priv, __p) \ 340 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 341 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 342 343 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 344 for_each_pipe(__dev_priv, __p) \ 345 for_each_if((__mask) & BIT(__p)) 346 347 #define for_each_cpu_transcoder(__dev_priv, __t) \ 348 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 349 for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 350 351 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 352 for_each_cpu_transcoder(__dev_priv, __t) \ 353 for_each_if ((__mask) & BIT(__t)) 354 355 #define for_each_sprite(__dev_priv, __p, __s) \ 356 for ((__s) = 0; \ 357 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 358 (__s)++) 359 360 #define for_each_port(__port) \ 361 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 362 363 #define for_each_port_masked(__port, __ports_mask) \ 364 for_each_port(__port) \ 365 for_each_if((__ports_mask) & BIT(__port)) 366 367 #define for_each_phy_masked(__phy, __phys_mask) \ 368 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 369 for_each_if((__phys_mask) & BIT(__phy)) 370 371 #define for_each_crtc(dev, crtc) \ 372 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 373 374 #define for_each_intel_plane(dev, intel_plane) \ 375 list_for_each_entry(intel_plane, \ 376 &(dev)->mode_config.plane_list, \ 377 base.head) 378 379 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 380 list_for_each_entry(intel_plane, \ 381 &(dev)->mode_config.plane_list, \ 382 base.head) \ 383 for_each_if((plane_mask) & \ 384 drm_plane_mask(&intel_plane->base)) 385 386 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 387 list_for_each_entry(intel_plane, \ 388 &(dev)->mode_config.plane_list, \ 389 base.head) \ 390 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 391 392 #define for_each_intel_crtc(dev, intel_crtc) \ 393 list_for_each_entry(intel_crtc, \ 394 &(dev)->mode_config.crtc_list, \ 395 base.head) 396 397 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 398 list_for_each_entry(intel_crtc, \ 399 &(dev)->mode_config.crtc_list, \ 400 base.head) \ 401 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 402 403 #define for_each_intel_encoder(dev, intel_encoder) \ 404 list_for_each_entry(intel_encoder, \ 405 &(dev)->mode_config.encoder_list, \ 406 base.head) 407 408 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 409 list_for_each_entry(intel_encoder, \ 410 &(dev)->mode_config.encoder_list, \ 411 base.head) \ 412 for_each_if((encoder_mask) & \ 413 drm_encoder_mask(&intel_encoder->base)) 414 415 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 416 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 417 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 418 intel_encoder_can_psr(intel_encoder)) 419 420 #define for_each_intel_dp(dev, intel_encoder) \ 421 for_each_intel_encoder(dev, intel_encoder) \ 422 for_each_if(intel_encoder_is_dp(intel_encoder)) 423 424 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 425 for_each_intel_encoder((dev), (intel_encoder)) \ 426 for_each_if(intel_encoder_can_psr(intel_encoder)) 427 428 #define for_each_intel_connector_iter(intel_connector, iter) \ 429 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 430 431 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 432 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 433 for_each_if((intel_encoder)->base.crtc == (__crtc)) 434 435 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 436 for ((__i) = 0; \ 437 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 438 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 439 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 440 (__i)++) \ 441 for_each_if(plane) 442 443 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 444 for ((__i) = 0; \ 445 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 446 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 447 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 448 (__i)++) \ 449 for_each_if(plane) 450 451 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 452 for ((__i) = 0; \ 453 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 454 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 455 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 456 (__i)++) \ 457 for_each_if(crtc) 458 459 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 460 for ((__i) = 0; \ 461 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 462 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 463 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 464 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 465 (__i)++) \ 466 for_each_if(plane) 467 468 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 469 for ((__i) = 0; \ 470 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 471 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 472 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 473 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 474 (__i)++) \ 475 for_each_if(crtc) 476 477 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 478 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 479 (__i) >= 0 && \ 480 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 481 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 482 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 483 (__i)--) \ 484 for_each_if(crtc) 485 486 #define intel_atomic_crtc_state_for_each_plane_state( \ 487 plane, plane_state, \ 488 crtc_state) \ 489 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 490 ((crtc_state)->uapi.plane_mask)) \ 491 for_each_if ((plane_state = \ 492 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 493 494 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 495 for ((__i) = 0; \ 496 (__i) < (__state)->base.num_connector; \ 497 (__i)++) \ 498 for_each_if ((__state)->base.connectors[__i].ptr && \ 499 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 500 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 501 502 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 503 struct intel_crtc *crtc); 504 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 505 u8 active_pipes); 506 void intel_link_compute_m_n(u16 bpp, int nlanes, 507 int pixel_clock, int link_clock, 508 struct intel_link_m_n *m_n, 509 bool fec_enable); 510 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 511 u32 pixel_format, u64 modifier); 512 enum drm_mode_status 513 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 514 const struct drm_display_mode *mode, 515 bool bigjoiner); 516 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 517 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 518 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); 519 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); 520 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); 521 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); 522 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 523 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 524 const struct intel_crtc_state *pipe_config, 525 bool fastset); 526 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state); 527 528 void intel_plane_destroy(struct drm_plane *plane); 529 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 530 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 531 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 532 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 533 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 534 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 535 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 536 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 537 const char *name, u32 reg, int ref_freq); 538 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 539 const char *name, u32 reg); 540 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 541 unsigned int intel_fb_xy_to_linear(int x, int y, 542 const struct intel_plane_state *state, 543 int plane); 544 void intel_add_fb_offsets(int *x, int *y, 545 const struct intel_plane_state *state, int plane); 546 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 547 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 548 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 549 int intel_display_suspend(struct drm_device *dev); 550 void intel_encoder_destroy(struct drm_encoder *encoder); 551 struct drm_display_mode * 552 intel_encoder_current_mode(struct intel_encoder *encoder); 553 void intel_encoder_get_config(struct intel_encoder *encoder, 554 struct intel_crtc_state *crtc_state); 555 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 556 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 557 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); 558 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 559 enum port port); 560 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 561 struct drm_file *file_priv); 562 563 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 564 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 565 struct intel_digital_port *dig_port, 566 unsigned int expected_mask); 567 int intel_get_load_detect_pipe(struct drm_connector *connector, 568 struct intel_load_detect_pipe *old, 569 struct drm_modeset_acquire_ctx *ctx); 570 void intel_release_load_detect_pipe(struct drm_connector *connector, 571 struct intel_load_detect_pipe *old, 572 struct drm_modeset_acquire_ctx *ctx); 573 struct drm_framebuffer * 574 intel_framebuffer_create(struct drm_i915_gem_object *obj, 575 struct drm_mode_fb_cmd2 *mode_cmd); 576 577 bool intel_fuzzy_clock_check(int clock1, int clock2); 578 579 void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 580 void intel_display_finish_reset(struct drm_i915_private *dev_priv); 581 void intel_zero_m_n(struct intel_link_m_n *m_n); 582 void intel_set_m_n(struct drm_i915_private *i915, 583 const struct intel_link_m_n *m_n, 584 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 585 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 586 void intel_get_m_n(struct drm_i915_private *i915, 587 struct intel_link_m_n *m_n, 588 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 589 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 590 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 591 enum transcoder transcoder); 592 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 593 enum transcoder cpu_transcoder, 594 const struct intel_link_m_n *m_n); 595 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 596 enum transcoder cpu_transcoder, 597 const struct intel_link_m_n *m_n); 598 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 599 enum transcoder cpu_transcoder, 600 struct intel_link_m_n *m_n); 601 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 602 enum transcoder cpu_transcoder, 603 struct intel_link_m_n *m_n); 604 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 605 struct intel_crtc_state *pipe_config); 606 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 607 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 608 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 609 enum intel_display_power_domain 610 intel_aux_power_domain(struct intel_digital_port *dig_port); 611 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 612 struct intel_crtc_state *crtc_state); 613 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 614 615 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 616 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 617 618 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); 619 620 struct intel_encoder * 621 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 622 const struct intel_crtc_state *crtc_state); 623 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 624 struct intel_plane *plane); 625 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 626 struct intel_plane_state *plane_state, 627 bool visible); 628 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 629 630 void intel_display_driver_register(struct drm_i915_private *i915); 631 void intel_display_driver_unregister(struct drm_i915_private *i915); 632 633 void intel_update_watermarks(struct drm_i915_private *i915); 634 635 /* modesetting */ 636 bool intel_modeset_probe_defer(struct pci_dev *pdev); 637 void intel_modeset_init_hw(struct drm_i915_private *i915); 638 int intel_modeset_init_noirq(struct drm_i915_private *i915); 639 int intel_modeset_init_nogem(struct drm_i915_private *i915); 640 int intel_modeset_init(struct drm_i915_private *i915); 641 void intel_modeset_driver_remove(struct drm_i915_private *i915); 642 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 643 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 644 void intel_display_resume(struct drm_device *dev); 645 int intel_modeset_all_pipes(struct intel_atomic_state *state, 646 const char *reason); 647 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 648 struct intel_power_domain_mask *old_domains); 649 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 650 struct intel_power_domain_mask *domains); 651 652 /* modesetting asserts */ 653 void assert_transcoder(struct drm_i915_private *dev_priv, 654 enum transcoder cpu_transcoder, bool state); 655 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 656 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 657 658 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 659 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 660 * which may not necessarily be a user visible problem. This will either 661 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 662 * enable distros and users to tailor their preferred amount of i915 abrt 663 * spam. 664 */ 665 #define I915_STATE_WARN(condition, format...) ({ \ 666 int __ret_warn_on = !!(condition); \ 667 if (unlikely(__ret_warn_on)) \ 668 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 669 DRM_ERROR(format); \ 670 unlikely(__ret_warn_on); \ 671 }) 672 673 #define I915_STATE_WARN_ON(x) \ 674 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 675 676 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); 677 678 #endif 679