1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #include "i915_reg_defs.h" 31 #include "intel_display_limits.h" 32 33 struct drm_atomic_state; 34 struct drm_device; 35 struct drm_display_mode; 36 struct drm_encoder; 37 struct drm_format_info; 38 struct drm_modeset_acquire_ctx; 39 struct intel_atomic_state; 40 struct intel_crtc; 41 struct intel_crtc_state; 42 struct intel_digital_port; 43 struct intel_display; 44 struct intel_encoder; 45 struct intel_link_m_n; 46 struct intel_plane; 47 struct intel_plane_state; 48 struct intel_power_domain_mask; 49 50 #define pipe_name(p) ((p) + 'A') 51 52 static inline const char *transcoder_name(enum transcoder transcoder) 53 { 54 switch (transcoder) { 55 case TRANSCODER_A: 56 return "A"; 57 case TRANSCODER_B: 58 return "B"; 59 case TRANSCODER_C: 60 return "C"; 61 case TRANSCODER_D: 62 return "D"; 63 case TRANSCODER_EDP: 64 return "EDP"; 65 case TRANSCODER_DSI_A: 66 return "DSI A"; 67 case TRANSCODER_DSI_C: 68 return "DSI C"; 69 default: 70 return "<invalid>"; 71 } 72 } 73 74 static inline bool transcoder_is_dsi(enum transcoder transcoder) 75 { 76 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 77 } 78 79 #define plane_name(p) ((p) + 'A') 80 81 #define for_each_plane_id_on_crtc(__crtc, __p) \ 82 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 83 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 84 85 #define for_each_dbuf_slice(__dev_priv, __slice) \ 86 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 87 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice)) 88 89 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 90 for_each_dbuf_slice((__dev_priv), (__slice)) \ 91 for_each_if((__mask) & BIT(__slice)) 92 93 #define port_name(p) ((p) + 'A') 94 95 /* 96 * Ports identifier referenced from other drivers. 97 * Expected to remain stable over time 98 */ 99 static inline const char *port_identifier(enum port port) 100 { 101 switch (port) { 102 case PORT_A: 103 return "Port A"; 104 case PORT_B: 105 return "Port B"; 106 case PORT_C: 107 return "Port C"; 108 case PORT_D: 109 return "Port D"; 110 case PORT_E: 111 return "Port E"; 112 case PORT_F: 113 return "Port F"; 114 case PORT_G: 115 return "Port G"; 116 case PORT_H: 117 return "Port H"; 118 case PORT_I: 119 return "Port I"; 120 default: 121 return "<invalid>"; 122 } 123 } 124 125 enum tc_port { 126 TC_PORT_NONE = -1, 127 128 TC_PORT_1 = 0, 129 TC_PORT_2, 130 TC_PORT_3, 131 TC_PORT_4, 132 TC_PORT_5, 133 TC_PORT_6, 134 135 I915_MAX_TC_PORTS 136 }; 137 138 enum phy { 139 PHY_NONE = -1, 140 141 PHY_A = 0, 142 PHY_B, 143 PHY_C, 144 PHY_D, 145 PHY_E, 146 PHY_F, 147 PHY_G, 148 PHY_H, 149 PHY_I, 150 151 I915_MAX_PHYS 152 }; 153 154 #define phy_name(a) ((a) + 'A') 155 156 enum phy_fia { 157 FIA1, 158 FIA2, 159 FIA3, 160 }; 161 162 #define for_each_hpd_pin(__pin) \ 163 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 164 165 #define for_each_pipe(__dev_priv, __p) \ 166 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 167 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 168 169 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 170 for_each_pipe(__dev_priv, __p) \ 171 for_each_if((__mask) & BIT(__p)) 172 173 #define for_each_cpu_transcoder(__dev_priv, __t) \ 174 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 175 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 176 177 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 178 for_each_cpu_transcoder(__dev_priv, __t) \ 179 for_each_if ((__mask) & BIT(__t)) 180 181 #define for_each_sprite(__dev_priv, __p, __s) \ 182 for ((__s) = 0; \ 183 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 184 (__s)++) 185 186 #define for_each_port(__port) \ 187 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 188 189 #define for_each_port_masked(__port, __ports_mask) \ 190 for_each_port(__port) \ 191 for_each_if((__ports_mask) & BIT(__port)) 192 193 #define for_each_phy_masked(__phy, __phys_mask) \ 194 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 195 for_each_if((__phys_mask) & BIT(__phy)) 196 197 #define for_each_intel_plane(dev, intel_plane) \ 198 list_for_each_entry(intel_plane, \ 199 &(dev)->mode_config.plane_list, \ 200 base.head) 201 202 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 203 list_for_each_entry(intel_plane, \ 204 &(dev)->mode_config.plane_list, \ 205 base.head) \ 206 for_each_if((plane_mask) & \ 207 drm_plane_mask(&intel_plane->base)) 208 209 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 210 list_for_each_entry(intel_plane, \ 211 &(dev)->mode_config.plane_list, \ 212 base.head) \ 213 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 214 215 #define for_each_intel_crtc(dev, intel_crtc) \ 216 list_for_each_entry(intel_crtc, \ 217 &(dev)->mode_config.crtc_list, \ 218 base.head) 219 220 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 221 list_for_each_entry(intel_crtc, \ 222 &(dev)->mode_config.crtc_list, \ 223 base.head) \ 224 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 225 226 #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ 227 list_for_each_entry_reverse((intel_crtc), \ 228 &(dev)->mode_config.crtc_list, \ 229 base.head) \ 230 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe)) 231 232 #define for_each_intel_encoder(dev, intel_encoder) \ 233 list_for_each_entry(intel_encoder, \ 234 &(dev)->mode_config.encoder_list, \ 235 base.head) 236 237 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 238 list_for_each_entry(intel_encoder, \ 239 &(dev)->mode_config.encoder_list, \ 240 base.head) \ 241 for_each_if((encoder_mask) & \ 242 drm_encoder_mask(&intel_encoder->base)) 243 244 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 245 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 246 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 247 intel_encoder_can_psr(intel_encoder)) 248 249 #define for_each_intel_dp(dev, intel_encoder) \ 250 for_each_intel_encoder(dev, intel_encoder) \ 251 for_each_if(intel_encoder_is_dp(intel_encoder)) 252 253 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 254 for_each_intel_encoder((dev), (intel_encoder)) \ 255 for_each_if(intel_encoder_can_psr(intel_encoder)) 256 257 #define for_each_intel_connector_iter(intel_connector, iter) \ 258 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 259 260 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 261 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 262 for_each_if((intel_encoder)->base.crtc == (__crtc)) 263 264 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 265 for ((__i) = 0; \ 266 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 267 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 268 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 269 (__i)++) \ 270 for_each_if(plane) 271 272 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 273 for ((__i) = 0; \ 274 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 275 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 276 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ 277 (__i)++) \ 278 for_each_if(crtc) 279 280 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 281 for ((__i) = 0; \ 282 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 283 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 284 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 285 (__i)++) \ 286 for_each_if(plane) 287 288 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 289 for ((__i) = 0; \ 290 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 291 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 292 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 293 (__i)++) \ 294 for_each_if(crtc) 295 296 #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \ 297 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 298 (__i) >= 0 && \ 299 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 300 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 301 (__i)--) \ 302 for_each_if(crtc) 303 304 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 305 for ((__i) = 0; \ 306 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 307 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 308 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 309 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 310 (__i)++) \ 311 for_each_if(plane) 312 313 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 314 for ((__i) = 0; \ 315 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 316 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 317 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 318 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 319 (__i)++) \ 320 for_each_if(crtc) 321 322 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 323 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 324 (__i) >= 0 && \ 325 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 326 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 327 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 328 (__i)--) \ 329 for_each_if(crtc) 330 331 #define intel_atomic_crtc_state_for_each_plane_state( \ 332 plane, plane_state, \ 333 crtc_state) \ 334 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 335 ((crtc_state)->uapi.plane_mask)) \ 336 for_each_if ((plane_state = \ 337 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 338 339 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 340 for ((__i) = 0; \ 341 (__i) < (__state)->base.num_connector; \ 342 (__i)++) \ 343 for_each_if ((__state)->base.connectors[__i].ptr && \ 344 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 345 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 346 347 #define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \ 348 for ((i) = 0; \ 349 (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \ 350 (i)++) \ 351 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i)) 352 353 #define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \ 354 for ((i) = (I915_MAX_PIPES * 2 - 1); \ 355 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \ 356 (i)--) \ 357 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i)) 358 359 #define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \ 360 for_each_crtc_in_masks(display, crtc, \ 361 _intel_modeset_primary_pipes(crtc_state), \ 362 _intel_modeset_secondary_pipes(crtc_state), \ 363 i) 364 365 #define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \ 366 for_each_crtc_in_masks_reverse(display, crtc, \ 367 _intel_modeset_primary_pipes(crtc_state), \ 368 _intel_modeset_secondary_pipes(crtc_state), \ 369 i) 370 371 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 372 u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, 373 u8 enabled_pipes); 374 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 375 u8 active_pipes); 376 void intel_link_compute_m_n(u16 bpp, int nlanes, 377 int pixel_clock, int link_clock, 378 int bw_overhead, 379 struct intel_link_m_n *m_n); 380 u32 intel_plane_fb_max_stride(struct intel_display *display, 381 const struct drm_format_info *info, 382 u64 modifier); 383 u32 intel_dumb_fb_max_stride(struct drm_device *drm, 384 u32 pixel_format, u64 modifier); 385 enum drm_mode_status 386 intel_mode_valid_max_plane_size(struct intel_display *display, 387 const struct drm_display_mode *mode, 388 int num_joined_pipes); 389 enum drm_mode_status 390 intel_cpu_transcoder_mode_valid(struct intel_display *display, 391 const struct drm_display_mode *mode); 392 enum phy intel_port_to_phy(struct intel_display *display, enum port port); 393 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 394 bool is_trans_port_sync_master(const struct intel_crtc_state *state); 395 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); 396 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); 397 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state); 398 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state); 399 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state); 400 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state); 401 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state); 402 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state); 403 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); 404 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state); 405 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state); 406 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); 407 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 408 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 409 const struct intel_crtc_state *pipe_config, 410 bool fastset); 411 412 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 413 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 414 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 415 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 416 void i830_enable_pipe(struct intel_display *display, enum pipe pipe); 417 void i830_disable_pipe(struct intel_display *display, enum pipe pipe); 418 bool intel_has_pending_fb_unpin(struct intel_display *display); 419 void intel_encoder_destroy(struct drm_encoder *encoder); 420 struct drm_display_mode * 421 intel_encoder_current_mode(struct intel_encoder *encoder); 422 void intel_encoder_get_config(struct intel_encoder *encoder, 423 struct intel_crtc_state *crtc_state); 424 bool intel_phy_is_combo(struct intel_display *display, enum phy phy); 425 bool intel_phy_is_tc(struct intel_display *display, enum phy phy); 426 bool intel_phy_is_snps(struct intel_display *display, enum phy phy); 427 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port); 428 enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port); 429 430 enum phy intel_encoder_to_phy(struct intel_encoder *encoder); 431 bool intel_encoder_is_combo(struct intel_encoder *encoder); 432 bool intel_encoder_is_snps(struct intel_encoder *encoder); 433 bool intel_encoder_is_tc(struct intel_encoder *encoder); 434 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder); 435 436 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 437 438 bool intel_fuzzy_clock_check(int clock1, int clock2); 439 440 void intel_zero_m_n(struct intel_link_m_n *m_n); 441 void intel_set_m_n(struct intel_display *display, 442 const struct intel_link_m_n *m_n, 443 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 444 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 445 void intel_get_m_n(struct intel_display *display, 446 struct intel_link_m_n *m_n, 447 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 448 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 449 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 450 enum transcoder transcoder); 451 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 452 enum transcoder cpu_transcoder, 453 const struct intel_link_m_n *m_n); 454 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 455 enum transcoder cpu_transcoder, 456 const struct intel_link_m_n *m_n); 457 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 458 enum transcoder cpu_transcoder, 459 struct intel_link_m_n *m_n); 460 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 461 enum transcoder cpu_transcoder, 462 struct intel_link_m_n *m_n); 463 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 464 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 465 int intel_max_uncompressed_dotclock(struct intel_display *display); 466 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 467 enum intel_display_power_domain 468 intel_aux_power_domain(struct intel_digital_port *dig_port); 469 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 470 struct intel_crtc_state *crtc_state); 471 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc); 472 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 473 474 struct intel_encoder * 475 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 476 const struct intel_crtc_state *crtc_state); 477 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 478 struct intel_plane *plane); 479 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 480 struct intel_plane_state *plane_state, 481 bool visible); 482 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 483 484 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 485 struct intel_crtc *crtc); 486 487 int intel_display_min_pipe_bpp(void); 488 int intel_display_max_pipe_bpp(struct intel_display *display); 489 490 /* modesetting */ 491 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 492 const char *reason, u8 pipe_mask); 493 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 494 const char *reason); 495 int intel_modeset_commit_pipes(struct intel_display *display, 496 u8 pipe_mask, 497 struct drm_modeset_acquire_ctx *ctx); 498 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 499 struct intel_power_domain_mask *old_domains); 500 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 501 struct intel_power_domain_mask *domains); 502 503 /* interface for intel_display_driver.c */ 504 void intel_init_display_hooks(struct intel_display *display); 505 void intel_setup_outputs(struct intel_display *display); 506 int intel_initial_commit(struct intel_display *display); 507 void intel_panel_sanitize_ssc(struct intel_display *display); 508 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 509 const struct drm_display_mode *mode); 510 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 511 bool nonblock); 512 513 /* modesetting asserts */ 514 void assert_transcoder(struct intel_display *display, 515 enum transcoder cpu_transcoder, bool state); 516 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 517 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 518 519 bool assert_port_valid(struct intel_display *display, enum port port); 520 521 /* 522 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw 523 * state sanity checks to check for unexpected conditions which may not 524 * necessarily be a user visible problem. This will either drm_WARN() or 525 * drm_err() depending on the verbose_state_checks module param, to enable 526 * distros and users to tailor their preferred amount of i915 abrt spam. 527 */ 528 #define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \ 529 int __ret_warn_on = !!(condition); \ 530 if (unlikely(__ret_warn_on)) \ 531 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \ 532 drm_err((__display)->drm, format); \ 533 unlikely(__ret_warn_on); \ 534 }) 535 536 bool intel_scanout_needs_vtd_wa(struct intel_display *display); 537 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state); 538 539 #endif 540