1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_tunnel.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_damage_helper.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_fixed.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_print.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 #include <drm/drm_vblank.h> 48 #include <drm/intel/step.h> 49 50 #include "g4x_dp.h" 51 #include "g4x_hdmi.h" 52 #include "hsw_ips.h" 53 #include "i915_config.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_plane_regs.h" 56 #include "i9xx_wm.h" 57 #include "intel_alpm.h" 58 #include "intel_atomic.h" 59 #include "intel_audio.h" 60 #include "intel_bo.h" 61 #include "intel_bw.h" 62 #include "intel_cdclk.h" 63 #include "intel_clock_gating.h" 64 #include "intel_cmtg.h" 65 #include "intel_color.h" 66 #include "intel_crt.h" 67 #include "intel_crtc.h" 68 #include "intel_crtc_state_dump.h" 69 #include "intel_cursor.h" 70 #include "intel_cursor_regs.h" 71 #include "intel_cx0_phy.h" 72 #include "intel_ddi.h" 73 #include "intel_de.h" 74 #include "intel_display_driver.h" 75 #include "intel_display_power.h" 76 #include "intel_display_regs.h" 77 #include "intel_display_rpm.h" 78 #include "intel_display_types.h" 79 #include "intel_display_utils.h" 80 #include "intel_display_wa.h" 81 #include "intel_dmc.h" 82 #include "intel_dp.h" 83 #include "intel_dp_link_training.h" 84 #include "intel_dp_mst.h" 85 #include "intel_dp_tunnel.h" 86 #include "intel_dpll.h" 87 #include "intel_dpll_mgr.h" 88 #include "intel_dpt.h" 89 #include "intel_drrs.h" 90 #include "intel_dsb.h" 91 #include "intel_dsi.h" 92 #include "intel_dvo.h" 93 #include "intel_fb.h" 94 #include "intel_fbc.h" 95 #include "intel_fdi.h" 96 #include "intel_fifo_underrun.h" 97 #include "intel_flipq.h" 98 #include "intel_frontbuffer.h" 99 #include "intel_hdmi.h" 100 #include "intel_hotplug.h" 101 #include "intel_initial_plane.h" 102 #include "intel_link_bw.h" 103 #include "intel_lt_phy.h" 104 #include "intel_lvds.h" 105 #include "intel_lvds_regs.h" 106 #include "intel_modeset_setup.h" 107 #include "intel_modeset_verify.h" 108 #include "intel_overlay.h" 109 #include "intel_panel.h" 110 #include "intel_pch_display.h" 111 #include "intel_pch_refclk.h" 112 #include "intel_pfit.h" 113 #include "intel_pipe_crc.h" 114 #include "intel_plane.h" 115 #include "intel_pmdemand.h" 116 #include "intel_pps.h" 117 #include "intel_psr.h" 118 #include "intel_psr_regs.h" 119 #include "intel_sdvo.h" 120 #include "intel_snps_phy.h" 121 #include "intel_tc.h" 122 #include "intel_tdf.h" 123 #include "intel_tv.h" 124 #include "intel_vblank.h" 125 #include "intel_vdsc.h" 126 #include "intel_vdsc_regs.h" 127 #include "intel_vga.h" 128 #include "intel_vrr.h" 129 #include "intel_wm.h" 130 #include "skl_scaler.h" 131 #include "skl_universal_plane.h" 132 #include "skl_watermark.h" 133 #include "vlv_dsi.h" 134 #include "vlv_dsi_pll.h" 135 #include "vlv_dsi_regs.h" 136 137 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 138 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 139 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 140 const struct intel_crtc_state *crtc_state); 141 142 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 143 { 144 return (crtc_state->active_planes & 145 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 146 } 147 148 /* WA Display #0827: Gen9:all */ 149 static void 150 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) 151 { 152 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 153 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 154 enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0); 155 } 156 157 /* Wa_2006604312:icl,ehl */ 158 static void 159 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, 160 bool enable) 161 { 162 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 163 DPFR_GATING_DIS, 164 enable ? DPFR_GATING_DIS : 0); 165 } 166 167 /* Wa_1604331009:icl,jsl,ehl */ 168 static void 169 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, 170 bool enable) 171 { 172 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 173 CURSOR_GATING_DIS, 174 enable ? CURSOR_GATING_DIS : 0); 175 } 176 177 static bool 178 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 179 { 180 return crtc_state->master_transcoder != INVALID_TRANSCODER; 181 } 182 183 bool 184 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 185 { 186 return crtc_state->sync_mode_slaves_mask != 0; 187 } 188 189 bool 190 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 191 { 192 return is_trans_port_sync_master(crtc_state) || 193 is_trans_port_sync_slave(crtc_state); 194 } 195 196 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) 197 { 198 return ffs(crtc_state->joiner_pipes) - 1; 199 } 200 201 /* 202 * The following helper functions, despite being named for bigjoiner, 203 * are applicable to both bigjoiner and uncompressed joiner configurations. 204 */ 205 static bool is_bigjoiner(const struct intel_crtc_state *crtc_state) 206 { 207 return hweight8(crtc_state->joiner_pipes) >= 2; 208 } 209 210 static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 211 { 212 if (!is_bigjoiner(crtc_state)) 213 return 0; 214 215 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state)); 216 } 217 218 static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 219 { 220 if (!is_bigjoiner(crtc_state)) 221 return 0; 222 223 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state)); 224 } 225 226 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state) 227 { 228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 229 230 if (!is_bigjoiner(crtc_state)) 231 return false; 232 233 return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state); 234 } 235 236 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state) 237 { 238 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 239 240 if (!is_bigjoiner(crtc_state)) 241 return false; 242 243 return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state); 244 } 245 246 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state) 247 { 248 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 249 250 if (!is_bigjoiner(crtc_state)) 251 return BIT(crtc->pipe); 252 253 return bigjoiner_primary_pipes(crtc_state); 254 } 255 256 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state) 257 { 258 return bigjoiner_secondary_pipes(crtc_state); 259 } 260 261 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state) 262 { 263 return intel_crtc_num_joined_pipes(crtc_state) >= 4; 264 } 265 266 static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 267 { 268 if (!intel_crtc_is_ultrajoiner(crtc_state)) 269 return 0; 270 271 return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state)); 272 } 273 274 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state) 275 { 276 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 277 278 return intel_crtc_is_ultrajoiner(crtc_state) && 279 BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state); 280 } 281 282 /* 283 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or 284 * any other logic, so lets just add helper function to 285 * at least hide this hassle.. 286 */ 287 static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state) 288 { 289 if (!intel_crtc_is_ultrajoiner(crtc_state)) 290 return 0; 291 292 return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state)); 293 } 294 295 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state) 296 { 297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 298 299 return intel_crtc_is_ultrajoiner(crtc_state) && 300 BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state); 301 } 302 303 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 304 { 305 if (crtc_state->joiner_pipes) 306 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); 307 else 308 return 0; 309 } 310 311 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) 312 { 313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 314 315 return crtc_state->joiner_pipes && 316 crtc->pipe != joiner_primary_pipe(crtc_state); 317 } 318 319 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) 320 { 321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 322 323 return crtc_state->joiner_pipes && 324 crtc->pipe == joiner_primary_pipe(crtc_state); 325 } 326 327 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state) 328 { 329 return hweight8(intel_crtc_joined_pipe_mask(crtc_state)); 330 } 331 332 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) 333 { 334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 335 336 return BIT(crtc->pipe) | crtc_state->joiner_pipes; 337 } 338 339 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) 340 { 341 struct intel_display *display = to_intel_display(crtc_state); 342 343 if (intel_crtc_is_joiner_secondary(crtc_state)) 344 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); 345 else 346 return to_intel_crtc(crtc_state->uapi.crtc); 347 } 348 349 static void 350 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 351 { 352 struct intel_display *display = to_intel_display(old_crtc_state); 353 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 354 355 if (DISPLAY_VER(display) >= 4) { 356 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 357 358 /* Wait for the Pipe State to go off */ 359 if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder), 360 TRANSCONF_STATE_ENABLE, 100)) 361 drm_WARN(display->drm, 1, "pipe_off wait timed out\n"); 362 } else { 363 intel_wait_for_pipe_scanline_stopped(crtc); 364 } 365 } 366 367 void assert_transcoder(struct intel_display *display, 368 enum transcoder cpu_transcoder, bool state) 369 { 370 bool cur_state; 371 enum intel_display_power_domain power_domain; 372 struct ref_tracker *wakeref; 373 374 /* we keep both pipes enabled on 830 */ 375 if (display->platform.i830) 376 state = true; 377 378 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 379 wakeref = intel_display_power_get_if_enabled(display, power_domain); 380 if (wakeref) { 381 u32 val = intel_de_read(display, 382 TRANSCONF(display, cpu_transcoder)); 383 cur_state = !!(val & TRANSCONF_ENABLE); 384 385 intel_display_power_put(display, power_domain, wakeref); 386 } else { 387 cur_state = false; 388 } 389 390 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 391 "transcoder %s assertion failure (expected %s, current %s)\n", 392 transcoder_name(cpu_transcoder), str_on_off(state), 393 str_on_off(cur_state)); 394 } 395 396 static void assert_plane(struct intel_plane *plane, bool state) 397 { 398 struct intel_display *display = to_intel_display(plane->base.dev); 399 enum pipe pipe; 400 bool cur_state; 401 402 cur_state = plane->get_hw_state(plane, &pipe); 403 404 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 405 "%s assertion failure (expected %s, current %s)\n", 406 plane->base.name, str_on_off(state), 407 str_on_off(cur_state)); 408 } 409 410 #define assert_plane_enabled(p) assert_plane(p, true) 411 #define assert_plane_disabled(p) assert_plane(p, false) 412 413 static void assert_planes_disabled(struct intel_crtc *crtc) 414 { 415 struct intel_display *display = to_intel_display(crtc); 416 struct intel_plane *plane; 417 418 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 419 assert_plane_disabled(plane); 420 } 421 422 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 423 { 424 struct intel_display *display = to_intel_display(new_crtc_state); 425 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 426 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 427 enum pipe pipe = crtc->pipe; 428 u32 val; 429 430 drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe)); 431 432 assert_planes_disabled(crtc); 433 434 /* 435 * A pipe without a PLL won't actually be able to drive bits from 436 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 437 * need the check. 438 */ 439 if (HAS_GMCH(display)) { 440 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 441 assert_dsi_pll_enabled(display); 442 else 443 assert_pll_enabled(display, pipe); 444 } else { 445 if (new_crtc_state->has_pch_encoder) { 446 /* if driving the PCH, we need FDI enabled */ 447 assert_fdi_rx_pll_enabled(display, 448 intel_crtc_pch_transcoder(crtc)); 449 assert_fdi_tx_pll_enabled(display, 450 (enum pipe) cpu_transcoder); 451 } 452 /* FIXME: assert CPU port conditions for SNB+ */ 453 } 454 455 /* Wa_22012358565:adl-p */ 456 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012358565)) 457 intel_de_rmw(display, PIPE_ARB_CTL(display, pipe), 458 0, PIPE_ARB_USE_PROG_SLOTS); 459 460 if (DISPLAY_VER(display) >= 14) { 461 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; 462 u32 set = 0; 463 464 if (DISPLAY_VER(display) == 14) 465 set |= DP_FEC_BS_JITTER_WA; 466 467 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 468 clear, set); 469 } 470 471 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 472 if (val & TRANSCONF_ENABLE) { 473 /* we keep both pipes enabled on 830 */ 474 drm_WARN_ON(display->drm, !display->platform.i830); 475 return; 476 } 477 478 /* Wa_1409098942:adlp+ */ 479 if (DISPLAY_VER(display) >= 13 && 480 new_crtc_state->dsc.compression_enable) { 481 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 482 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, 483 TRANSCONF_PIXEL_COUNT_SCALING_X4); 484 } 485 486 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 487 val | TRANSCONF_ENABLE); 488 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 489 490 /* 491 * Until the pipe starts PIPEDSL reads will return a stale value, 492 * which causes an apparent vblank timestamp jump when PIPEDSL 493 * resets to its proper value. That also messes up the frame count 494 * when it's derived from the timestamps. So let's wait for the 495 * pipe to start properly before we call drm_crtc_vblank_on() 496 */ 497 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 498 intel_wait_for_pipe_scanline_moving(crtc); 499 } 500 501 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 502 { 503 struct intel_display *display = to_intel_display(old_crtc_state); 504 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 505 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 506 enum pipe pipe = crtc->pipe; 507 u32 val; 508 509 drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe)); 510 511 /* 512 * Make sure planes won't keep trying to pump pixels to us, 513 * or we might hang the display. 514 */ 515 assert_planes_disabled(crtc); 516 517 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 518 if ((val & TRANSCONF_ENABLE) == 0) 519 return; 520 521 /* 522 * Double wide has implications for planes 523 * so best keep it disabled when not needed. 524 */ 525 if (old_crtc_state->double_wide) 526 val &= ~TRANSCONF_DOUBLE_WIDE; 527 528 /* Don't disable pipe or pipe PLLs if needed */ 529 if (!display->platform.i830) 530 val &= ~TRANSCONF_ENABLE; 531 532 /* Wa_1409098942:adlp+ */ 533 if (DISPLAY_VER(display) >= 13 && 534 old_crtc_state->dsc.compression_enable) 535 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 536 537 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 538 539 if (DISPLAY_VER(display) >= 12) 540 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 541 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 542 543 if ((val & TRANSCONF_ENABLE) == 0) 544 intel_wait_for_pipe_off(old_crtc_state); 545 } 546 547 u32 intel_plane_fb_max_stride(struct intel_display *display, 548 const struct drm_format_info *info, 549 u64 modifier) 550 { 551 struct intel_crtc *crtc; 552 struct intel_plane *plane; 553 554 /* 555 * We assume the primary plane for pipe A has 556 * the highest stride limits of them all, 557 * if in case pipe A is disabled, use the first pipe from pipe_mask. 558 */ 559 crtc = intel_first_crtc(display); 560 if (!crtc) 561 return 0; 562 563 plane = to_intel_plane(crtc->base.primary); 564 565 return plane->max_stride(plane, info, modifier, 566 DRM_MODE_ROTATE_0); 567 } 568 569 u32 intel_dumb_fb_max_stride(struct drm_device *drm, 570 u32 pixel_format, u64 modifier) 571 { 572 struct intel_display *display = to_intel_display(drm); 573 574 if (!HAS_DISPLAY(display)) 575 return 0; 576 577 return intel_plane_fb_max_stride(display, 578 drm_get_format_info(drm, pixel_format, modifier), 579 modifier); 580 } 581 582 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 583 struct intel_plane_state *plane_state, 584 bool visible) 585 { 586 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 587 588 plane_state->uapi.visible = visible; 589 590 if (visible) 591 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 592 else 593 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 594 } 595 596 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 597 { 598 struct intel_display *display = to_intel_display(crtc_state); 599 struct drm_plane *plane; 600 601 /* 602 * Active_planes aliases if multiple "primary" or cursor planes 603 * have been used on the same (or wrong) pipe. plane_mask uses 604 * unique ids, hence we can use that to reconstruct active_planes. 605 */ 606 crtc_state->enabled_planes = 0; 607 crtc_state->active_planes = 0; 608 609 drm_for_each_plane_mask(plane, display->drm, 610 crtc_state->uapi.plane_mask) { 611 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 612 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 613 } 614 } 615 616 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 617 struct intel_plane *plane) 618 { 619 struct intel_display *display = to_intel_display(crtc); 620 struct intel_crtc_state *crtc_state = 621 to_intel_crtc_state(crtc->base.state); 622 struct intel_plane_state *plane_state = 623 to_intel_plane_state(plane->base.state); 624 625 drm_dbg_kms(display->drm, 626 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 627 plane->base.base.id, plane->base.name, 628 crtc->base.base.id, crtc->base.name); 629 630 intel_plane_set_invisible(crtc_state, plane_state); 631 intel_set_plane_visible(crtc_state, plane_state, false); 632 intel_plane_fixup_bitmasks(crtc_state); 633 634 skl_wm_plane_disable_noatomic(crtc, plane); 635 636 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 637 hsw_ips_disable(crtc_state)) { 638 crtc_state->ips_enabled = false; 639 intel_initial_plane_vblank_wait(crtc); 640 } 641 642 /* 643 * Vblank time updates from the shadow to live plane control register 644 * are blocked if the memory self-refresh mode is active at that 645 * moment. So to make sure the plane gets truly disabled, disable 646 * first the self-refresh mode. The self-refresh enable bit in turn 647 * will be checked/applied by the HW only at the next frame start 648 * event which is after the vblank start event, so we need to have a 649 * wait-for-vblank between disabling the plane and the pipe. 650 */ 651 if (HAS_GMCH(display) && 652 intel_set_memory_cxsr(display, false)) 653 intel_initial_plane_vblank_wait(crtc); 654 655 /* 656 * Gen2 reports pipe underruns whenever all planes are disabled. 657 * So disable underrun reporting before all the planes get disabled. 658 */ 659 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) 660 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); 661 662 intel_plane_disable_arm(NULL, plane, crtc_state); 663 intel_initial_plane_vblank_wait(crtc); 664 } 665 666 unsigned int 667 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 668 { 669 int x = 0, y = 0; 670 671 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 672 plane_state->view.color_plane[0].offset, 0); 673 674 return y; 675 } 676 677 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 678 { 679 struct intel_display *display = to_intel_display(crtc_state); 680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 681 enum pipe pipe = crtc->pipe; 682 u32 tmp; 683 684 tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); 685 686 /* 687 * Display WA #1153: icl 688 * enable hardware to bypass the alpha math 689 * and rounding for per-pixel values 00 and 0xff 690 */ 691 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 692 /* 693 * Display WA # 1605353570: icl 694 * Set the pixel rounding bit to 1 for allowing 695 * passthrough of Frame buffer pixels unmodified 696 * across pipe 697 */ 698 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 699 700 /* 701 * Underrun recovery must always be disabled on display 13+. 702 * DG2 chicken bit meaning is inverted compared to other platforms. 703 */ 704 if (display->platform.dg2) 705 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 706 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) 707 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 708 709 /* Wa_14010547955:dg2 */ 710 if (intel_display_wa(display, INTEL_DISPLAY_WA_14010547955)) 711 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 712 713 intel_de_write(display, PIPE_CHICKEN(pipe), tmp); 714 } 715 716 bool intel_has_pending_fb_unpin(struct intel_display *display) 717 { 718 struct intel_crtc *crtc; 719 bool cleanup_done; 720 721 for_each_intel_crtc(display, crtc) { 722 struct drm_crtc_commit *commit; 723 spin_lock(&crtc->base.commit_lock); 724 commit = list_first_entry_or_null(&crtc->base.commit_list, 725 struct drm_crtc_commit, commit_entry); 726 cleanup_done = commit ? 727 try_wait_for_completion(&commit->cleanup_done) : true; 728 spin_unlock(&crtc->base.commit_lock); 729 730 if (cleanup_done) 731 continue; 732 733 intel_crtc_wait_for_next_vblank(crtc); 734 735 return true; 736 } 737 738 return false; 739 } 740 741 /* FIXME: remove this and just flush the cleanup wq where appropriate */ 742 void intel_display_flush_cleanup_work(struct intel_display *display) 743 { 744 struct intel_crtc *crtc; 745 746 for_each_intel_crtc(display, crtc) { 747 struct drm_crtc_commit *commit; 748 749 spin_lock(&crtc->base.commit_lock); 750 commit = list_first_entry_or_null(&crtc->base.commit_list, 751 struct drm_crtc_commit, commit_entry); 752 if (commit) 753 drm_crtc_commit_get(commit); 754 spin_unlock(&crtc->base.commit_lock); 755 756 if (commit) { 757 wait_for_completion(&commit->cleanup_done); 758 drm_crtc_commit_put(commit); 759 } 760 } 761 } 762 763 /* 764 * Finds the encoder associated with the given CRTC. This can only be 765 * used when we know that the CRTC isn't feeding multiple encoders! 766 */ 767 struct intel_encoder * 768 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 769 const struct intel_crtc_state *crtc_state) 770 { 771 const struct drm_connector_state *connector_state; 772 const struct drm_connector *connector; 773 struct intel_encoder *encoder = NULL; 774 struct intel_crtc *primary_crtc; 775 int num_encoders = 0; 776 int i; 777 778 primary_crtc = intel_primary_crtc(crtc_state); 779 780 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 781 if (connector_state->crtc != &primary_crtc->base) 782 continue; 783 784 encoder = to_intel_encoder(connector_state->best_encoder); 785 num_encoders++; 786 } 787 788 drm_WARN(state->base.dev, num_encoders != 1, 789 "%d encoders for pipe %c\n", 790 num_encoders, pipe_name(primary_crtc->pipe)); 791 792 return encoder; 793 } 794 795 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 796 { 797 if (crtc->overlay) 798 (void) intel_overlay_switch_off(crtc->overlay); 799 800 /* Let userspace switch the overlay on again. In most cases userspace 801 * has to recompute where to put it anyway. 802 */ 803 } 804 805 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 806 { 807 struct intel_display *display = to_intel_display(crtc_state); 808 809 if (!crtc_state->nv12_planes) 810 return false; 811 812 /* WA Display #0827: Gen9:all */ 813 if (DISPLAY_VER(display) == 9) 814 return true; 815 816 return false; 817 } 818 819 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 820 { 821 struct intel_display *display = to_intel_display(crtc_state); 822 823 /* Wa_2006604312:icl,ehl */ 824 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) 825 return true; 826 827 return false; 828 } 829 830 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 831 { 832 struct intel_display *display = to_intel_display(crtc_state); 833 834 /* Wa_1604331009:icl,jsl,ehl */ 835 if (is_hdr_mode(crtc_state) && 836 crtc_state->active_planes & BIT(PLANE_CURSOR) && 837 DISPLAY_VER(display) == 11) 838 return true; 839 840 return false; 841 } 842 843 static void intel_async_flip_vtd_wa(struct intel_display *display, 844 enum pipe pipe, bool enable) 845 { 846 if (DISPLAY_VER(display) == 9) { 847 /* 848 * "Plane N stretch max must be programmed to 11b (x1) 849 * when Async flips are enabled on that plane." 850 */ 851 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 852 SKL_PLANE1_STRETCH_MAX_MASK, 853 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 854 } else { 855 /* Also needed on HSW/BDW albeit undocumented */ 856 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 857 HSW_PRI_STRETCH_MAX_MASK, 858 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 859 } 860 } 861 862 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 863 { 864 struct intel_display *display = to_intel_display(crtc_state); 865 866 return crtc_state->uapi.async_flip && intel_display_vtd_active(display) && 867 (DISPLAY_VER(display) == 9 || display->platform.broadwell || 868 display->platform.haswell); 869 } 870 871 static void intel_encoders_audio_enable(struct intel_atomic_state *state, 872 struct intel_crtc *crtc) 873 { 874 const struct intel_crtc_state *crtc_state = 875 intel_atomic_get_new_crtc_state(state, crtc); 876 const struct drm_connector_state *conn_state; 877 struct drm_connector *conn; 878 int i; 879 880 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 881 struct intel_encoder *encoder = 882 to_intel_encoder(conn_state->best_encoder); 883 884 if (conn_state->crtc != &crtc->base) 885 continue; 886 887 if (encoder->audio_enable) 888 encoder->audio_enable(encoder, crtc_state, conn_state); 889 } 890 } 891 892 static void intel_encoders_audio_disable(struct intel_atomic_state *state, 893 struct intel_crtc *crtc) 894 { 895 const struct intel_crtc_state *old_crtc_state = 896 intel_atomic_get_old_crtc_state(state, crtc); 897 const struct drm_connector_state *old_conn_state; 898 struct drm_connector *conn; 899 int i; 900 901 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 902 struct intel_encoder *encoder = 903 to_intel_encoder(old_conn_state->best_encoder); 904 905 if (old_conn_state->crtc != &crtc->base) 906 continue; 907 908 if (encoder->audio_disable) 909 encoder->audio_disable(encoder, old_crtc_state, old_conn_state); 910 } 911 } 912 913 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 914 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 915 (new_crtc_state)->feature) 916 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 917 ((old_crtc_state)->feature && \ 918 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 919 920 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 921 const struct intel_crtc_state *new_crtc_state) 922 { 923 if (!new_crtc_state->hw.active) 924 return false; 925 926 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 927 } 928 929 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 930 const struct intel_crtc_state *new_crtc_state) 931 { 932 if (!old_crtc_state->hw.active) 933 return false; 934 935 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 936 } 937 938 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, 939 const struct intel_crtc_state *new_crtc_state) 940 { 941 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline || 942 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || 943 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || 944 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || 945 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full || 946 old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start || 947 old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end; 948 } 949 950 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, 951 const struct intel_crtc_state *new_crtc_state) 952 { 953 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || 954 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; 955 } 956 957 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, 958 struct intel_crtc *crtc) 959 { 960 const struct intel_crtc_state *old_crtc_state = 961 intel_atomic_get_old_crtc_state(state, crtc); 962 const struct intel_crtc_state *new_crtc_state = 963 intel_atomic_get_new_crtc_state(state, crtc); 964 965 if (!new_crtc_state->hw.active) 966 return false; 967 968 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) || 969 (new_crtc_state->vrr.enable && 970 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 971 vrr_params_changed(old_crtc_state, new_crtc_state))); 972 } 973 974 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 975 struct intel_crtc *crtc) 976 { 977 const struct intel_crtc_state *old_crtc_state = 978 intel_atomic_get_old_crtc_state(state, crtc); 979 const struct intel_crtc_state *new_crtc_state = 980 intel_atomic_get_new_crtc_state(state, crtc); 981 982 if (!old_crtc_state->hw.active) 983 return false; 984 985 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) || 986 (old_crtc_state->vrr.enable && 987 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 988 vrr_params_changed(old_crtc_state, new_crtc_state))); 989 } 990 991 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, 992 const struct intel_crtc_state *new_crtc_state) 993 { 994 if (!new_crtc_state->hw.active) 995 return false; 996 997 return is_enabling(has_audio, old_crtc_state, new_crtc_state) || 998 (new_crtc_state->has_audio && 999 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 1000 } 1001 1002 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, 1003 const struct intel_crtc_state *new_crtc_state) 1004 { 1005 if (!old_crtc_state->hw.active) 1006 return false; 1007 1008 return is_disabling(has_audio, old_crtc_state, new_crtc_state) || 1009 (old_crtc_state->has_audio && 1010 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 1011 } 1012 1013 static bool intel_crtc_lobf_enabling(const struct intel_crtc_state *old_crtc_state, 1014 const struct intel_crtc_state *new_crtc_state) 1015 { 1016 if (!new_crtc_state->hw.active) 1017 return false; 1018 1019 return is_enabling(has_lobf, old_crtc_state, new_crtc_state) || 1020 (new_crtc_state->has_lobf && 1021 (new_crtc_state->update_lrr || new_crtc_state->update_m_n)); 1022 } 1023 1024 static bool intel_crtc_lobf_disabling(const struct intel_crtc_state *old_crtc_state, 1025 const struct intel_crtc_state *new_crtc_state) 1026 { 1027 if (!old_crtc_state->hw.active) 1028 return false; 1029 1030 return is_disabling(has_lobf, old_crtc_state, new_crtc_state) || 1031 (old_crtc_state->has_lobf && 1032 (new_crtc_state->update_lrr || new_crtc_state->update_m_n)); 1033 } 1034 1035 #undef is_disabling 1036 #undef is_enabling 1037 1038 static void intel_post_plane_update(struct intel_atomic_state *state, 1039 struct intel_crtc *crtc) 1040 { 1041 struct intel_display *display = to_intel_display(state); 1042 const struct intel_crtc_state *old_crtc_state = 1043 intel_atomic_get_old_crtc_state(state, crtc); 1044 const struct intel_crtc_state *new_crtc_state = 1045 intel_atomic_get_new_crtc_state(state, crtc); 1046 enum pipe pipe = crtc->pipe; 1047 1048 intel_frontbuffer_flip(display, new_crtc_state->fb_bits); 1049 1050 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1051 intel_update_watermarks(display); 1052 1053 intel_fbc_post_update(state, crtc); 1054 1055 if (needs_async_flip_vtd_wa(old_crtc_state) && 1056 !needs_async_flip_vtd_wa(new_crtc_state)) 1057 intel_async_flip_vtd_wa(display, pipe, false); 1058 1059 if (needs_nv12_wa(old_crtc_state) && 1060 !needs_nv12_wa(new_crtc_state)) 1061 skl_wa_827(display, pipe, false); 1062 1063 if (needs_scalerclk_wa(old_crtc_state) && 1064 !needs_scalerclk_wa(new_crtc_state)) 1065 icl_wa_scalerclkgating(display, pipe, false); 1066 1067 if (needs_cursorclk_wa(old_crtc_state) && 1068 !needs_cursorclk_wa(new_crtc_state)) 1069 icl_wa_cursorclkgating(display, pipe, false); 1070 1071 if (intel_crtc_needs_color_update(new_crtc_state)) 1072 intel_color_post_update(new_crtc_state); 1073 1074 if (audio_enabling(old_crtc_state, new_crtc_state)) 1075 intel_encoders_audio_enable(state, crtc); 1076 1077 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503117)) { 1078 if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled) 1079 adl_scaler_ecc_unmask(new_crtc_state); 1080 } 1081 1082 if (intel_crtc_lobf_enabling(old_crtc_state, new_crtc_state)) 1083 intel_alpm_lobf_enable(new_crtc_state); 1084 1085 intel_psr_post_plane_update(state, crtc); 1086 } 1087 1088 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, 1089 struct intel_crtc *crtc) 1090 { 1091 const struct intel_crtc_state *new_crtc_state = 1092 intel_atomic_get_new_crtc_state(state, crtc); 1093 1094 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 1095 hsw_ips_post_update(state, crtc); 1096 1097 /* 1098 * Activate DRRS after state readout to avoid 1099 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 1100 */ 1101 intel_drrs_activate(new_crtc_state); 1102 } 1103 1104 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1105 struct intel_crtc *crtc) 1106 { 1107 const struct intel_crtc_state *crtc_state = 1108 intel_atomic_get_new_crtc_state(state, crtc); 1109 u8 update_planes = crtc_state->update_planes; 1110 const struct intel_plane_state __maybe_unused *plane_state; 1111 struct intel_plane *plane; 1112 int i; 1113 1114 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1115 if (plane->pipe == crtc->pipe && 1116 update_planes & BIT(plane->id)) 1117 plane->enable_flip_done(plane); 1118 } 1119 } 1120 1121 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1122 struct intel_crtc *crtc) 1123 { 1124 const struct intel_crtc_state *crtc_state = 1125 intel_atomic_get_new_crtc_state(state, crtc); 1126 u8 update_planes = crtc_state->update_planes; 1127 const struct intel_plane_state __maybe_unused *plane_state; 1128 struct intel_plane *plane; 1129 int i; 1130 1131 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1132 if (plane->pipe == crtc->pipe && 1133 update_planes & BIT(plane->id)) 1134 plane->disable_flip_done(plane); 1135 } 1136 } 1137 1138 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1139 struct intel_crtc *crtc) 1140 { 1141 const struct intel_crtc_state *old_crtc_state = 1142 intel_atomic_get_old_crtc_state(state, crtc); 1143 const struct intel_crtc_state *new_crtc_state = 1144 intel_atomic_get_new_crtc_state(state, crtc); 1145 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1146 ~new_crtc_state->async_flip_planes; 1147 const struct intel_plane_state *old_plane_state; 1148 struct intel_plane *plane; 1149 bool need_vbl_wait = false; 1150 int i; 1151 1152 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1153 if (plane->need_async_flip_toggle_wa && 1154 plane->pipe == crtc->pipe && 1155 disable_async_flip_planes & BIT(plane->id)) { 1156 /* 1157 * Apart from the async flip bit we want to 1158 * preserve the old state for the plane. 1159 */ 1160 intel_plane_async_flip(NULL, plane, 1161 old_crtc_state, old_plane_state, false); 1162 need_vbl_wait = true; 1163 } 1164 } 1165 1166 if (need_vbl_wait) 1167 intel_crtc_wait_for_next_vblank(crtc); 1168 } 1169 1170 static void intel_pre_plane_update(struct intel_atomic_state *state, 1171 struct intel_crtc *crtc) 1172 { 1173 struct intel_display *display = to_intel_display(state); 1174 const struct intel_crtc_state *old_crtc_state = 1175 intel_atomic_get_old_crtc_state(state, crtc); 1176 const struct intel_crtc_state *new_crtc_state = 1177 intel_atomic_get_new_crtc_state(state, crtc); 1178 enum pipe pipe = crtc->pipe; 1179 1180 if (intel_crtc_lobf_disabling(old_crtc_state, new_crtc_state)) 1181 intel_alpm_lobf_disable(new_crtc_state); 1182 1183 intel_psr_pre_plane_update(state, crtc); 1184 1185 if (intel_crtc_vrr_disabling(state, crtc)) { 1186 intel_vrr_disable(old_crtc_state); 1187 intel_vrr_dcb_reset(old_crtc_state, crtc); 1188 intel_crtc_update_active_timings(old_crtc_state, false); 1189 } 1190 1191 if (audio_disabling(old_crtc_state, new_crtc_state)) 1192 intel_encoders_audio_disable(state, crtc); 1193 1194 intel_drrs_deactivate(old_crtc_state); 1195 1196 if (hsw_ips_pre_update(state, crtc)) 1197 intel_crtc_wait_for_next_vblank(crtc); 1198 1199 if (intel_fbc_pre_update(state, crtc)) 1200 intel_crtc_wait_for_next_vblank(crtc); 1201 1202 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1203 needs_async_flip_vtd_wa(new_crtc_state)) 1204 intel_async_flip_vtd_wa(display, pipe, true); 1205 1206 /* Display WA 827 */ 1207 if (!needs_nv12_wa(old_crtc_state) && 1208 needs_nv12_wa(new_crtc_state)) 1209 skl_wa_827(display, pipe, true); 1210 1211 /* Wa_2006604312:icl,ehl */ 1212 if (!needs_scalerclk_wa(old_crtc_state) && 1213 needs_scalerclk_wa(new_crtc_state)) 1214 icl_wa_scalerclkgating(display, pipe, true); 1215 1216 /* Wa_1604331009:icl,jsl,ehl */ 1217 if (!needs_cursorclk_wa(old_crtc_state) && 1218 needs_cursorclk_wa(new_crtc_state)) 1219 icl_wa_cursorclkgating(display, pipe, true); 1220 1221 /* 1222 * Vblank time updates from the shadow to live plane control register 1223 * are blocked if the memory self-refresh mode is active at that 1224 * moment. So to make sure the plane gets truly disabled, disable 1225 * first the self-refresh mode. The self-refresh enable bit in turn 1226 * will be checked/applied by the HW only at the next frame start 1227 * event which is after the vblank start event, so we need to have a 1228 * wait-for-vblank between disabling the plane and the pipe. 1229 */ 1230 if (HAS_GMCH(display) && old_crtc_state->hw.active && 1231 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false)) 1232 intel_crtc_wait_for_next_vblank(crtc); 1233 1234 /* 1235 * IVB workaround: must disable low power watermarks for at least 1236 * one frame before enabling scaling. LP watermarks can be re-enabled 1237 * when scaling is disabled. 1238 * 1239 * WaCxSRDisabledForSpriteScaling:ivb 1240 */ 1241 if (!HAS_GMCH(display) && old_crtc_state->hw.active && 1242 new_crtc_state->disable_cxsr && ilk_disable_cxsr(display)) 1243 intel_crtc_wait_for_next_vblank(crtc); 1244 1245 /* 1246 * If we're doing a modeset we don't need to do any 1247 * pre-vblank watermark programming here. 1248 */ 1249 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1250 /* 1251 * For platforms that support atomic watermarks, program the 1252 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1253 * will be the intermediate values that are safe for both pre- and 1254 * post- vblank; when vblank happens, the 'active' values will be set 1255 * to the final 'target' values and we'll do this again to get the 1256 * optimal watermarks. For gen9+ platforms, the values we program here 1257 * will be the final target values which will get automatically latched 1258 * at vblank time; no further programming will be necessary. 1259 * 1260 * If a platform hasn't been transitioned to atomic watermarks yet, 1261 * we'll continue to update watermarks the old way, if flags tell 1262 * us to. 1263 */ 1264 if (!intel_initial_watermarks(state, crtc)) 1265 if (new_crtc_state->update_wm_pre) 1266 intel_update_watermarks(display); 1267 } 1268 1269 /* 1270 * Gen2 reports pipe underruns whenever all planes are disabled. 1271 * So disable underrun reporting before all the planes get disabled. 1272 * 1273 * We do this after .initial_watermarks() so that we have a 1274 * chance of catching underruns with the intermediate watermarks 1275 * vs. the old plane configuration. 1276 */ 1277 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1278 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1279 1280 /* 1281 * WA for platforms where async address update enable bit 1282 * is double buffered and only latched at start of vblank. 1283 */ 1284 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1285 intel_crtc_async_flip_disable_wa(state, crtc); 1286 } 1287 1288 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1289 struct intel_crtc *crtc) 1290 { 1291 struct intel_display *display = to_intel_display(state); 1292 const struct intel_crtc_state *new_crtc_state = 1293 intel_atomic_get_new_crtc_state(state, crtc); 1294 unsigned int update_mask = new_crtc_state->update_planes; 1295 const struct intel_plane_state *old_plane_state; 1296 struct intel_plane *plane; 1297 unsigned fb_bits = 0; 1298 int i; 1299 1300 intel_crtc_dpms_overlay_disable(crtc); 1301 1302 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1303 if (crtc->pipe != plane->pipe || 1304 !(update_mask & BIT(plane->id))) 1305 continue; 1306 1307 intel_plane_disable_arm(NULL, plane, new_crtc_state); 1308 1309 if (old_plane_state->uapi.visible) 1310 fb_bits |= plane->frontbuffer_bit; 1311 } 1312 1313 intel_frontbuffer_flip(display, fb_bits); 1314 } 1315 1316 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1317 { 1318 struct intel_display *display = to_intel_display(state); 1319 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1320 struct intel_crtc *crtc; 1321 1322 /* 1323 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1324 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1325 */ 1326 if (display->dpll.mgr) { 1327 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 1328 if (intel_crtc_needs_modeset(new_crtc_state)) 1329 continue; 1330 1331 new_crtc_state->intel_dpll = old_crtc_state->intel_dpll; 1332 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1333 } 1334 } 1335 } 1336 1337 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1338 struct intel_crtc *crtc) 1339 { 1340 const struct intel_crtc_state *crtc_state = 1341 intel_atomic_get_new_crtc_state(state, crtc); 1342 const struct drm_connector_state *conn_state; 1343 struct drm_connector *conn; 1344 int i; 1345 1346 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1347 struct intel_encoder *encoder = 1348 to_intel_encoder(conn_state->best_encoder); 1349 1350 if (conn_state->crtc != &crtc->base) 1351 continue; 1352 1353 if (encoder->pre_pll_enable) 1354 encoder->pre_pll_enable(state, encoder, 1355 crtc_state, conn_state); 1356 } 1357 } 1358 1359 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1360 struct intel_crtc *crtc) 1361 { 1362 const struct intel_crtc_state *crtc_state = 1363 intel_atomic_get_new_crtc_state(state, crtc); 1364 const struct drm_connector_state *conn_state; 1365 struct drm_connector *conn; 1366 int i; 1367 1368 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1369 struct intel_encoder *encoder = 1370 to_intel_encoder(conn_state->best_encoder); 1371 1372 if (conn_state->crtc != &crtc->base) 1373 continue; 1374 1375 if (encoder->pre_enable) 1376 encoder->pre_enable(state, encoder, 1377 crtc_state, conn_state); 1378 } 1379 } 1380 1381 static void intel_encoders_enable(struct intel_atomic_state *state, 1382 struct intel_crtc *crtc) 1383 { 1384 const struct intel_crtc_state *crtc_state = 1385 intel_atomic_get_new_crtc_state(state, crtc); 1386 const struct drm_connector_state *conn_state; 1387 struct drm_connector *conn; 1388 int i; 1389 1390 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1391 struct intel_encoder *encoder = 1392 to_intel_encoder(conn_state->best_encoder); 1393 1394 if (conn_state->crtc != &crtc->base) 1395 continue; 1396 1397 if (encoder->enable) 1398 encoder->enable(state, encoder, 1399 crtc_state, conn_state); 1400 intel_opregion_notify_encoder(encoder, true); 1401 } 1402 } 1403 1404 static void intel_encoders_disable(struct intel_atomic_state *state, 1405 struct intel_crtc *crtc) 1406 { 1407 const struct intel_crtc_state *old_crtc_state = 1408 intel_atomic_get_old_crtc_state(state, crtc); 1409 const struct drm_connector_state *old_conn_state; 1410 struct drm_connector *conn; 1411 int i; 1412 1413 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1414 struct intel_encoder *encoder = 1415 to_intel_encoder(old_conn_state->best_encoder); 1416 1417 if (old_conn_state->crtc != &crtc->base) 1418 continue; 1419 1420 intel_opregion_notify_encoder(encoder, false); 1421 if (encoder->disable) 1422 encoder->disable(state, encoder, 1423 old_crtc_state, old_conn_state); 1424 } 1425 } 1426 1427 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1428 struct intel_crtc *crtc) 1429 { 1430 const struct intel_crtc_state *old_crtc_state = 1431 intel_atomic_get_old_crtc_state(state, crtc); 1432 const struct drm_connector_state *old_conn_state; 1433 struct drm_connector *conn; 1434 int i; 1435 1436 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1437 struct intel_encoder *encoder = 1438 to_intel_encoder(old_conn_state->best_encoder); 1439 1440 if (old_conn_state->crtc != &crtc->base) 1441 continue; 1442 1443 if (encoder->post_disable) 1444 encoder->post_disable(state, encoder, 1445 old_crtc_state, old_conn_state); 1446 } 1447 } 1448 1449 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1450 struct intel_crtc *crtc) 1451 { 1452 const struct intel_crtc_state *old_crtc_state = 1453 intel_atomic_get_old_crtc_state(state, crtc); 1454 const struct drm_connector_state *old_conn_state; 1455 struct drm_connector *conn; 1456 int i; 1457 1458 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1459 struct intel_encoder *encoder = 1460 to_intel_encoder(old_conn_state->best_encoder); 1461 1462 if (old_conn_state->crtc != &crtc->base) 1463 continue; 1464 1465 if (encoder->post_pll_disable) 1466 encoder->post_pll_disable(state, encoder, 1467 old_crtc_state, old_conn_state); 1468 } 1469 } 1470 1471 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1472 struct intel_crtc *crtc) 1473 { 1474 const struct intel_crtc_state *crtc_state = 1475 intel_atomic_get_new_crtc_state(state, crtc); 1476 const struct drm_connector_state *conn_state; 1477 struct drm_connector *conn; 1478 int i; 1479 1480 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1481 struct intel_encoder *encoder = 1482 to_intel_encoder(conn_state->best_encoder); 1483 1484 if (conn_state->crtc != &crtc->base) 1485 continue; 1486 1487 if (encoder->update_pipe) 1488 encoder->update_pipe(state, encoder, 1489 crtc_state, conn_state); 1490 } 1491 } 1492 1493 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1494 { 1495 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1496 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1497 1498 if (crtc_state->has_pch_encoder) { 1499 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1500 &crtc_state->fdi_m_n); 1501 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1502 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1503 &crtc_state->dp_m_n); 1504 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1505 &crtc_state->dp_m2_n2); 1506 } 1507 1508 intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder); 1509 1510 ilk_set_pipeconf(crtc_state); 1511 } 1512 1513 static void ilk_crtc_enable(struct intel_atomic_state *state, 1514 struct intel_crtc *crtc) 1515 { 1516 struct intel_display *display = to_intel_display(crtc); 1517 const struct intel_crtc_state *new_crtc_state = 1518 intel_atomic_get_new_crtc_state(state, crtc); 1519 enum pipe pipe = crtc->pipe; 1520 1521 if (drm_WARN_ON(display->drm, crtc->active)) 1522 return; 1523 1524 /* 1525 * Sometimes spurious CPU pipe underruns happen during FDI 1526 * training, at least with VGA+HDMI cloning. Suppress them. 1527 * 1528 * On ILK we get an occasional spurious CPU pipe underruns 1529 * between eDP port A enable and vdd enable. Also PCH port 1530 * enable seems to result in the occasional CPU pipe underrun. 1531 * 1532 * Spurious PCH underruns also occur during PCH enabling. 1533 */ 1534 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1535 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1536 1537 ilk_configure_cpu_transcoder(new_crtc_state); 1538 1539 intel_set_pipe_src_size(new_crtc_state); 1540 1541 crtc->active = true; 1542 1543 intel_encoders_pre_enable(state, crtc); 1544 1545 if (new_crtc_state->has_pch_encoder) { 1546 ilk_pch_pre_enable(state, crtc); 1547 } else { 1548 assert_fdi_tx_disabled(display, pipe); 1549 assert_fdi_rx_disabled(display, pipe); 1550 } 1551 1552 ilk_pfit_enable(new_crtc_state); 1553 1554 /* 1555 * On ILK+ LUT must be loaded before the pipe is running but with 1556 * clocks enabled 1557 */ 1558 intel_color_modeset(new_crtc_state); 1559 1560 intel_initial_watermarks(state, crtc); 1561 intel_enable_transcoder(new_crtc_state); 1562 1563 if (new_crtc_state->has_pch_encoder) 1564 ilk_pch_enable(state, crtc); 1565 1566 intel_crtc_vblank_on(new_crtc_state); 1567 1568 intel_encoders_enable(state, crtc); 1569 1570 if (HAS_PCH_CPT(display)) 1571 intel_wait_for_pipe_scanline_moving(crtc); 1572 1573 /* 1574 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1575 * And a second vblank wait is needed at least on ILK with 1576 * some interlaced HDMI modes. Let's do the double wait always 1577 * in case there are more corner cases we don't know about. 1578 */ 1579 if (new_crtc_state->has_pch_encoder) { 1580 intel_crtc_wait_for_next_vblank(crtc); 1581 intel_crtc_wait_for_next_vblank(crtc); 1582 } 1583 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1584 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1585 } 1586 1587 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1588 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) 1589 { 1590 struct intel_display *display = to_intel_display(crtc_state); 1591 1592 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; 1593 } 1594 1595 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) 1596 { 1597 struct intel_display *display = to_intel_display(crtc); 1598 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1599 1600 intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe), 1601 mask, enable ? mask : 0); 1602 } 1603 1604 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1605 { 1606 struct intel_display *display = to_intel_display(crtc_state); 1607 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1608 1609 intel_de_write(display, WM_LINETIME(crtc->pipe), 1610 HSW_LINETIME(crtc_state->linetime) | 1611 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1612 } 1613 1614 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1615 { 1616 struct intel_display *display = to_intel_display(crtc_state); 1617 1618 intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder), 1619 HSW_FRAME_START_DELAY_MASK, 1620 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1621 } 1622 1623 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1624 { 1625 struct intel_display *display = to_intel_display(crtc_state); 1626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1628 1629 if (crtc_state->has_pch_encoder) { 1630 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1631 &crtc_state->fdi_m_n); 1632 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1633 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1634 &crtc_state->dp_m_n); 1635 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1636 &crtc_state->dp_m2_n2); 1637 } 1638 1639 intel_cmtg_set_m_n(crtc_state); 1640 intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder); 1641 intel_cmtg_set_timings(crtc_state, MODESET); 1642 1643 if (cpu_transcoder != TRANSCODER_EDP) 1644 intel_de_write(display, TRANS_MULT(display, cpu_transcoder), 1645 crtc_state->pixel_multiplier - 1); 1646 1647 hsw_set_frame_start_delay(crtc_state); 1648 1649 hsw_set_transconf(crtc_state); 1650 } 1651 1652 static void hsw_crtc_enable(struct intel_atomic_state *state, 1653 struct intel_crtc *crtc) 1654 { 1655 struct intel_display *display = to_intel_display(state); 1656 const struct intel_crtc_state *new_crtc_state = 1657 intel_atomic_get_new_crtc_state(state, crtc); 1658 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1659 struct intel_crtc *pipe_crtc; 1660 1661 if (drm_WARN_ON(display->drm, crtc->active)) 1662 return; 1663 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1664 const struct intel_crtc_state *new_pipe_crtc_state = 1665 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1666 1667 intel_dmc_enable_pipe(new_pipe_crtc_state); 1668 } 1669 1670 intel_encoders_pre_pll_enable(state, crtc); 1671 1672 if (new_crtc_state->intel_dpll) 1673 intel_dpll_enable(new_crtc_state); 1674 1675 intel_encoders_pre_enable(state, crtc); 1676 1677 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1678 const struct intel_crtc_state *pipe_crtc_state = 1679 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1680 1681 intel_dsc_enable(pipe_crtc_state); 1682 1683 if (HAS_UNCOMPRESSED_JOINER(display)) 1684 intel_uncompressed_joiner_enable(pipe_crtc_state); 1685 1686 intel_set_pipe_src_size(pipe_crtc_state); 1687 1688 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 1689 bdw_set_pipe_misc(NULL, pipe_crtc_state); 1690 } 1691 1692 if (!transcoder_is_dsi(cpu_transcoder)) 1693 hsw_configure_cpu_transcoder(new_crtc_state); 1694 1695 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1696 const struct intel_crtc_state *pipe_crtc_state = 1697 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1698 1699 pipe_crtc->active = true; 1700 1701 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) 1702 glk_pipe_scaler_clock_gating_wa(pipe_crtc, true); 1703 1704 if (DISPLAY_VER(display) >= 9) 1705 skl_pfit_enable(pipe_crtc_state); 1706 else 1707 ilk_pfit_enable(pipe_crtc_state); 1708 1709 /* 1710 * On ILK+ LUT must be loaded before the pipe is running but with 1711 * clocks enabled 1712 */ 1713 intel_color_modeset(pipe_crtc_state); 1714 1715 hsw_set_linetime_wm(pipe_crtc_state); 1716 1717 if (DISPLAY_VER(display) >= 11) 1718 icl_set_pipe_chicken(pipe_crtc_state); 1719 1720 intel_initial_watermarks(state, pipe_crtc); 1721 } 1722 1723 intel_encoders_enable(state, crtc); 1724 1725 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1726 const struct intel_crtc_state *pipe_crtc_state = 1727 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1728 enum pipe hsw_workaround_pipe; 1729 1730 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) { 1731 intel_crtc_wait_for_next_vblank(pipe_crtc); 1732 glk_pipe_scaler_clock_gating_wa(pipe_crtc, false); 1733 } 1734 1735 /* 1736 * If we change the relative order between pipe/planes 1737 * enabling, we need to change the workaround. 1738 */ 1739 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe; 1740 if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) { 1741 struct intel_crtc *wa_crtc = 1742 intel_crtc_for_pipe(display, hsw_workaround_pipe); 1743 1744 intel_crtc_wait_for_next_vblank(wa_crtc); 1745 intel_crtc_wait_for_next_vblank(wa_crtc); 1746 } 1747 } 1748 } 1749 1750 static void ilk_crtc_disable(struct intel_atomic_state *state, 1751 struct intel_crtc *crtc) 1752 { 1753 struct intel_display *display = to_intel_display(crtc); 1754 const struct intel_crtc_state *old_crtc_state = 1755 intel_atomic_get_old_crtc_state(state, crtc); 1756 enum pipe pipe = crtc->pipe; 1757 1758 /* 1759 * Sometimes spurious CPU pipe underruns happen when the 1760 * pipe is already disabled, but FDI RX/TX is still enabled. 1761 * Happens at least with VGA+HDMI cloning. Suppress them. 1762 */ 1763 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1764 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1765 1766 intel_encoders_disable(state, crtc); 1767 1768 intel_crtc_vblank_off(old_crtc_state); 1769 1770 intel_disable_transcoder(old_crtc_state); 1771 1772 ilk_pfit_disable(old_crtc_state); 1773 1774 if (old_crtc_state->has_pch_encoder) 1775 ilk_pch_disable(state, crtc); 1776 1777 intel_encoders_post_disable(state, crtc); 1778 1779 if (old_crtc_state->has_pch_encoder) 1780 ilk_pch_post_disable(state, crtc); 1781 1782 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1783 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1784 } 1785 1786 static void hsw_crtc_disable(struct intel_atomic_state *state, 1787 struct intel_crtc *crtc) 1788 { 1789 struct intel_display *display = to_intel_display(state); 1790 const struct intel_crtc_state *old_crtc_state = 1791 intel_atomic_get_old_crtc_state(state, crtc); 1792 struct intel_crtc *pipe_crtc; 1793 1794 if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) { 1795 intel_cmtg_set_clk_select(old_crtc_state); 1796 intel_cmtg_disable(old_crtc_state); 1797 } 1798 /* 1799 * FIXME collapse everything to one hook. 1800 * Need care with mst->ddi interactions. 1801 */ 1802 intel_encoders_disable(state, crtc); 1803 intel_encoders_post_disable(state, crtc); 1804 1805 intel_dpll_disable(old_crtc_state); 1806 1807 intel_encoders_post_pll_disable(state, crtc); 1808 1809 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 1810 const struct intel_crtc_state *old_pipe_crtc_state = 1811 intel_atomic_get_old_crtc_state(state, pipe_crtc); 1812 1813 intel_dmc_disable_pipe(old_pipe_crtc_state); 1814 } 1815 } 1816 1817 /* Prefer intel_encoder_is_combo() */ 1818 bool intel_phy_is_combo(struct intel_display *display, enum phy phy) 1819 { 1820 if (phy == PHY_NONE) 1821 return false; 1822 else if (display->platform.alderlake_s) 1823 return phy <= PHY_E; 1824 else if (display->platform.dg1 || display->platform.rocketlake) 1825 return phy <= PHY_D; 1826 else if (display->platform.jasperlake || display->platform.elkhartlake) 1827 return phy <= PHY_C; 1828 else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12)) 1829 return phy <= PHY_B; 1830 else 1831 /* 1832 * DG2 outputs labelled as "combo PHY" in the bspec use 1833 * SNPS PHYs with completely different programming, 1834 * hence we always return false here. 1835 */ 1836 return false; 1837 } 1838 1839 /* 1840 * This function returns true if the DDI port respective to the PHY enumeration 1841 * is a Type-C capable port. 1842 * 1843 * Depending on the VBT, the port might be configured 1844 * as a "dedicated external" port, meaning that actual physical PHY is outside 1845 * of the Type-C subsystem and, as such, not really a "Type-C PHY". 1846 * 1847 * Prefer intel_encoder_is_tc(), especially if you really need to know if we 1848 * are dealing with Type-C connections. 1849 */ 1850 bool intel_phy_is_tc(struct intel_display *display, enum phy phy) 1851 { 1852 /* 1853 * Discrete GPU phy's are not attached to FIA's to support TC 1854 * subsystem Legacy or non-legacy, and only support native DP/HDMI 1855 */ 1856 if (display->platform.dgfx) 1857 return false; 1858 1859 if (DISPLAY_VER(display) >= 13) 1860 return phy >= PHY_F && phy <= PHY_I; 1861 else if (display->platform.tigerlake) 1862 return phy >= PHY_D && phy <= PHY_I; 1863 else if (display->platform.icelake) 1864 return phy >= PHY_C && phy <= PHY_F; 1865 1866 return false; 1867 } 1868 1869 /* Prefer intel_encoder_is_snps() */ 1870 bool intel_phy_is_snps(struct intel_display *display, enum phy phy) 1871 { 1872 /* 1873 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port 1874 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc(). 1875 */ 1876 return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E; 1877 } 1878 1879 /* Prefer intel_encoder_to_phy() */ 1880 enum phy intel_port_to_phy(struct intel_display *display, enum port port) 1881 { 1882 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) 1883 return PHY_D + port - PORT_D_XELPD; 1884 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) 1885 return PHY_F + port - PORT_TC1; 1886 else if (display->platform.alderlake_s && port >= PORT_TC1) 1887 return PHY_B + port - PORT_TC1; 1888 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) 1889 return PHY_C + port - PORT_TC1; 1890 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 1891 port == PORT_D) 1892 return PHY_A; 1893 1894 return PHY_A + port - PORT_A; 1895 } 1896 1897 /* Prefer intel_encoder_to_tc() */ 1898 /* 1899 * Return TC_PORT_1..I915_MAX_TC_PORTS for any TypeC DDI port. The function 1900 * can be also called for TypeC DDI ports not connected to a TypeC PHY such as 1901 * the PORT_TC1..4 ports on RKL/ADLS/BMG. 1902 */ 1903 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) 1904 { 1905 if (DISPLAY_VER(display) >= 12) 1906 return TC_PORT_1 + port - PORT_TC1; 1907 else 1908 return TC_PORT_1 + port - PORT_C; 1909 } 1910 1911 /* 1912 * Return TC_PORT_1..I915_MAX_TC_PORTS for TypeC DDI ports connected to a TypeC PHY. 1913 * Note that on RKL, ADLS, BMG the PORT_TC1..4 ports are connected to a non-TypeC 1914 * PHY, so on those platforms the function returns TC_PORT_NONE. 1915 */ 1916 enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) 1917 { 1918 if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) 1919 return TC_PORT_NONE; 1920 1921 return intel_port_to_tc(display, port); 1922 } 1923 1924 enum phy intel_encoder_to_phy(struct intel_encoder *encoder) 1925 { 1926 struct intel_display *display = to_intel_display(encoder); 1927 1928 return intel_port_to_phy(display, encoder->port); 1929 } 1930 1931 bool intel_encoder_is_combo(struct intel_encoder *encoder) 1932 { 1933 struct intel_display *display = to_intel_display(encoder); 1934 1935 return intel_phy_is_combo(display, intel_encoder_to_phy(encoder)); 1936 } 1937 1938 bool intel_encoder_is_snps(struct intel_encoder *encoder) 1939 { 1940 struct intel_display *display = to_intel_display(encoder); 1941 1942 return intel_phy_is_snps(display, intel_encoder_to_phy(encoder)); 1943 } 1944 1945 bool intel_encoder_is_tc(struct intel_encoder *encoder) 1946 { 1947 struct intel_display *display = to_intel_display(encoder); 1948 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1949 1950 if (dig_port && dig_port->dedicated_external) 1951 return false; 1952 1953 return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); 1954 } 1955 1956 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) 1957 { 1958 struct intel_display *display = to_intel_display(encoder); 1959 1960 return intel_tc_phy_port_to_tc(display, encoder->port); 1961 } 1962 1963 enum intel_display_power_domain 1964 intel_aux_power_domain(struct intel_digital_port *dig_port) 1965 { 1966 struct intel_display *display = to_intel_display(dig_port); 1967 1968 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1969 return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch); 1970 1971 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); 1972 } 1973 1974 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1975 struct intel_power_domain_mask *mask) 1976 { 1977 struct intel_display *display = to_intel_display(crtc_state); 1978 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1979 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1980 struct drm_encoder *encoder; 1981 enum pipe pipe = crtc->pipe; 1982 1983 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1984 1985 if (!crtc_state->hw.active) 1986 return; 1987 1988 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1989 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1990 if (crtc_state->pch_pfit.enabled || 1991 crtc_state->pch_pfit.force_thru) 1992 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1993 1994 drm_for_each_encoder_mask(encoder, display->drm, 1995 crtc_state->uapi.encoder_mask) { 1996 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1997 1998 set_bit(intel_encoder->power_domain, mask->bits); 1999 } 2000 2001 if (HAS_DDI(display) && crtc_state->has_audio) 2002 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2003 2004 if (crtc_state->intel_dpll) 2005 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2006 2007 if (crtc_state->dsc.compression_enable) 2008 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2009 } 2010 2011 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2012 struct intel_power_domain_mask *old_domains) 2013 { 2014 struct intel_display *display = to_intel_display(crtc_state); 2015 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2016 enum intel_display_power_domain domain; 2017 struct intel_power_domain_mask domains, new_domains; 2018 2019 get_crtc_power_domains(crtc_state, &domains); 2020 2021 bitmap_andnot(new_domains.bits, 2022 domains.bits, 2023 crtc->enabled_power_domains.mask.bits, 2024 POWER_DOMAIN_NUM); 2025 bitmap_andnot(old_domains->bits, 2026 crtc->enabled_power_domains.mask.bits, 2027 domains.bits, 2028 POWER_DOMAIN_NUM); 2029 2030 for_each_power_domain(domain, &new_domains) 2031 intel_display_power_get_in_set(display, 2032 &crtc->enabled_power_domains, 2033 domain); 2034 } 2035 2036 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2037 struct intel_power_domain_mask *domains) 2038 { 2039 struct intel_display *display = to_intel_display(crtc); 2040 2041 intel_display_power_put_mask_in_set(display, 2042 &crtc->enabled_power_domains, 2043 domains); 2044 } 2045 2046 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2047 { 2048 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2049 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2050 2051 if (intel_crtc_has_dp_encoder(crtc_state)) { 2052 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2053 &crtc_state->dp_m_n); 2054 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2055 &crtc_state->dp_m2_n2); 2056 } 2057 2058 intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder); 2059 2060 i9xx_set_pipeconf(crtc_state); 2061 } 2062 2063 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2064 struct intel_crtc *crtc) 2065 { 2066 struct intel_display *display = to_intel_display(crtc); 2067 const struct intel_crtc_state *new_crtc_state = 2068 intel_atomic_get_new_crtc_state(state, crtc); 2069 enum pipe pipe = crtc->pipe; 2070 2071 if (drm_WARN_ON(display->drm, crtc->active)) 2072 return; 2073 2074 i9xx_configure_cpu_transcoder(new_crtc_state); 2075 2076 intel_set_pipe_src_size(new_crtc_state); 2077 2078 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); 2079 2080 if (display->platform.cherryview && pipe == PIPE_B) { 2081 intel_de_write(display, CHV_BLEND(display, pipe), 2082 CHV_BLEND_LEGACY); 2083 intel_de_write(display, CHV_CANVAS(display, pipe), 0); 2084 } 2085 2086 crtc->active = true; 2087 2088 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2089 2090 intel_encoders_pre_pll_enable(state, crtc); 2091 2092 if (display->platform.cherryview) 2093 chv_enable_pll(new_crtc_state); 2094 else 2095 vlv_enable_pll(new_crtc_state); 2096 2097 intel_encoders_pre_enable(state, crtc); 2098 2099 i9xx_pfit_enable(new_crtc_state); 2100 2101 intel_color_modeset(new_crtc_state); 2102 2103 intel_initial_watermarks(state, crtc); 2104 intel_enable_transcoder(new_crtc_state); 2105 2106 intel_crtc_vblank_on(new_crtc_state); 2107 2108 intel_encoders_enable(state, crtc); 2109 } 2110 2111 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2112 struct intel_crtc *crtc) 2113 { 2114 struct intel_display *display = to_intel_display(crtc); 2115 const struct intel_crtc_state *new_crtc_state = 2116 intel_atomic_get_new_crtc_state(state, crtc); 2117 enum pipe pipe = crtc->pipe; 2118 2119 if (drm_WARN_ON(display->drm, crtc->active)) 2120 return; 2121 2122 i9xx_configure_cpu_transcoder(new_crtc_state); 2123 2124 intel_set_pipe_src_size(new_crtc_state); 2125 2126 crtc->active = true; 2127 2128 if (DISPLAY_VER(display) != 2) 2129 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2130 2131 intel_encoders_pre_enable(state, crtc); 2132 2133 i9xx_enable_pll(new_crtc_state); 2134 2135 i9xx_pfit_enable(new_crtc_state); 2136 2137 intel_color_modeset(new_crtc_state); 2138 2139 if (!intel_initial_watermarks(state, crtc)) 2140 intel_update_watermarks(display); 2141 intel_enable_transcoder(new_crtc_state); 2142 2143 intel_crtc_vblank_on(new_crtc_state); 2144 2145 intel_encoders_enable(state, crtc); 2146 2147 /* prevents spurious underruns */ 2148 if (DISPLAY_VER(display) == 2) 2149 intel_crtc_wait_for_next_vblank(crtc); 2150 } 2151 2152 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2153 struct intel_crtc *crtc) 2154 { 2155 struct intel_display *display = to_intel_display(state); 2156 struct intel_crtc_state *old_crtc_state = 2157 intel_atomic_get_old_crtc_state(state, crtc); 2158 enum pipe pipe = crtc->pipe; 2159 2160 /* 2161 * On gen2 planes are double buffered but the pipe isn't, so we must 2162 * wait for planes to fully turn off before disabling the pipe. 2163 */ 2164 if (DISPLAY_VER(display) == 2) 2165 intel_crtc_wait_for_next_vblank(crtc); 2166 2167 intel_encoders_disable(state, crtc); 2168 2169 intel_crtc_vblank_off(old_crtc_state); 2170 2171 intel_disable_transcoder(old_crtc_state); 2172 2173 i9xx_pfit_disable(old_crtc_state); 2174 2175 intel_encoders_post_disable(state, crtc); 2176 2177 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2178 if (display->platform.cherryview) 2179 chv_disable_pll(display, pipe); 2180 else if (display->platform.valleyview) 2181 vlv_disable_pll(display, pipe); 2182 else 2183 i9xx_disable_pll(old_crtc_state); 2184 } 2185 2186 intel_encoders_post_pll_disable(state, crtc); 2187 2188 if (DISPLAY_VER(display) != 2) 2189 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 2190 2191 if (!display->wm.funcs->initial_watermarks) 2192 intel_update_watermarks(display); 2193 2194 /* clock the pipe down to 640x480@60 to potentially save power */ 2195 if (display->platform.i830) 2196 i830_enable_pipe(display, pipe); 2197 } 2198 2199 void intel_encoder_destroy(struct drm_encoder *encoder) 2200 { 2201 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2202 2203 drm_encoder_cleanup(encoder); 2204 kfree(intel_encoder); 2205 } 2206 2207 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2208 { 2209 struct intel_display *display = to_intel_display(crtc); 2210 2211 /* GDG double wide on either pipe, otherwise pipe A only */ 2212 return HAS_DOUBLE_WIDE(display) && 2213 (crtc->pipe == PIPE_A || display->platform.i915g); 2214 } 2215 2216 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2217 { 2218 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2219 struct drm_rect src; 2220 2221 /* 2222 * We only use IF-ID interlacing. If we ever use 2223 * PF-ID we'll need to adjust the pixel_rate here. 2224 */ 2225 2226 if (!crtc_state->pch_pfit.enabled) 2227 return pixel_rate; 2228 2229 drm_rect_init(&src, 0, 0, 2230 drm_rect_width(&crtc_state->pipe_src) << 16, 2231 drm_rect_height(&crtc_state->pipe_src) << 16); 2232 2233 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2234 pixel_rate); 2235 } 2236 2237 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2238 const struct drm_display_mode *timings) 2239 { 2240 mode->hdisplay = timings->crtc_hdisplay; 2241 mode->htotal = timings->crtc_htotal; 2242 mode->hsync_start = timings->crtc_hsync_start; 2243 mode->hsync_end = timings->crtc_hsync_end; 2244 2245 mode->vdisplay = timings->crtc_vdisplay; 2246 mode->vtotal = timings->crtc_vtotal; 2247 mode->vsync_start = timings->crtc_vsync_start; 2248 mode->vsync_end = timings->crtc_vsync_end; 2249 2250 mode->flags = timings->flags; 2251 mode->type = DRM_MODE_TYPE_DRIVER; 2252 2253 mode->clock = timings->crtc_clock; 2254 2255 drm_mode_set_name(mode); 2256 } 2257 2258 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2259 { 2260 struct intel_display *display = to_intel_display(crtc_state); 2261 2262 if (HAS_GMCH(display)) 2263 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2264 crtc_state->pixel_rate = 2265 crtc_state->hw.pipe_mode.crtc_clock; 2266 else 2267 crtc_state->pixel_rate = 2268 ilk_pipe_pixel_rate(crtc_state); 2269 } 2270 2271 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2272 struct drm_display_mode *mode) 2273 { 2274 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2275 2276 if (num_pipes == 1) 2277 return; 2278 2279 mode->crtc_clock /= num_pipes; 2280 mode->crtc_hdisplay /= num_pipes; 2281 mode->crtc_hblank_start /= num_pipes; 2282 mode->crtc_hblank_end /= num_pipes; 2283 mode->crtc_hsync_start /= num_pipes; 2284 mode->crtc_hsync_end /= num_pipes; 2285 mode->crtc_htotal /= num_pipes; 2286 } 2287 2288 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2289 struct drm_display_mode *mode) 2290 { 2291 int overlap = crtc_state->splitter.pixel_overlap; 2292 int n = crtc_state->splitter.link_count; 2293 2294 if (!crtc_state->splitter.enable) 2295 return; 2296 2297 /* 2298 * eDP MSO uses segment timings from EDID for transcoder 2299 * timings, but full mode for everything else. 2300 * 2301 * h_full = (h_segment - pixel_overlap) * link_count 2302 */ 2303 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2304 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2305 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2306 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2307 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2308 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2309 mode->crtc_clock *= n; 2310 } 2311 2312 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2313 { 2314 struct drm_display_mode *mode = &crtc_state->hw.mode; 2315 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2316 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2317 2318 /* 2319 * Start with the adjusted_mode crtc timings, which 2320 * have been filled with the transcoder timings. 2321 */ 2322 drm_mode_copy(pipe_mode, adjusted_mode); 2323 2324 /* Expand MSO per-segment transcoder timings to full */ 2325 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2326 2327 /* 2328 * We want the full numbers in adjusted_mode normal timings, 2329 * adjusted_mode crtc timings are left with the raw transcoder 2330 * timings. 2331 */ 2332 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2333 2334 /* Populate the "user" mode with full numbers */ 2335 drm_mode_copy(mode, pipe_mode); 2336 intel_mode_from_crtc_timings(mode, mode); 2337 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2338 intel_crtc_num_joined_pipes(crtc_state); 2339 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2340 2341 /* Derive per-pipe timings in case joiner is used */ 2342 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2343 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2344 2345 intel_crtc_compute_pixel_rate(crtc_state); 2346 } 2347 2348 void intel_encoder_get_config(struct intel_encoder *encoder, 2349 struct intel_crtc_state *crtc_state) 2350 { 2351 encoder->get_config(encoder, crtc_state); 2352 2353 intel_crtc_readout_derived_state(crtc_state); 2354 } 2355 2356 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2357 { 2358 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2359 int width, height; 2360 2361 if (num_pipes == 1) 2362 return; 2363 2364 width = drm_rect_width(&crtc_state->pipe_src); 2365 height = drm_rect_height(&crtc_state->pipe_src); 2366 2367 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2368 width / num_pipes, height); 2369 } 2370 2371 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2372 { 2373 struct intel_display *display = to_intel_display(crtc_state); 2374 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2375 2376 intel_joiner_compute_pipe_src(crtc_state); 2377 2378 /* 2379 * Pipe horizontal size must be even in: 2380 * - DVO ganged mode 2381 * - LVDS dual channel mode 2382 * - Double wide pipe 2383 */ 2384 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2385 if (crtc_state->double_wide) { 2386 drm_dbg_kms(display->drm, 2387 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2388 crtc->base.base.id, crtc->base.name); 2389 return -EINVAL; 2390 } 2391 2392 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2393 intel_is_dual_link_lvds(display)) { 2394 drm_dbg_kms(display->drm, 2395 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2396 crtc->base.base.id, crtc->base.name); 2397 return -EINVAL; 2398 } 2399 } 2400 2401 return 0; 2402 } 2403 2404 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2405 { 2406 struct intel_display *display = to_intel_display(crtc_state); 2407 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2408 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2409 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2410 int clock_limit = display->cdclk.max_dotclk_freq; 2411 2412 /* 2413 * Start with the adjusted_mode crtc timings, which 2414 * have been filled with the transcoder timings. 2415 */ 2416 drm_mode_copy(pipe_mode, adjusted_mode); 2417 2418 /* Expand MSO per-segment transcoder timings to full */ 2419 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2420 2421 /* Derive per-pipe timings in case joiner is used */ 2422 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2423 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2424 2425 if (DISPLAY_VER(display) < 4) { 2426 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; 2427 2428 /* 2429 * Enable double wide mode when the dot clock 2430 * is > 90% of the (display) core speed. 2431 */ 2432 if (intel_crtc_supports_double_wide(crtc) && 2433 pipe_mode->crtc_clock > clock_limit) { 2434 clock_limit = display->cdclk.max_dotclk_freq; 2435 crtc_state->double_wide = true; 2436 } 2437 } 2438 2439 if (pipe_mode->crtc_clock > clock_limit) { 2440 drm_dbg_kms(display->drm, 2441 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2442 crtc->base.base.id, crtc->base.name, 2443 pipe_mode->crtc_clock, clock_limit, 2444 str_yes_no(crtc_state->double_wide)); 2445 return -EINVAL; 2446 } 2447 2448 return 0; 2449 } 2450 2451 static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state) 2452 { 2453 struct intel_display *display = to_intel_display(crtc_state); 2454 int set_context_latency = 0; 2455 2456 if (!HAS_DSB(display)) 2457 return 0; 2458 2459 set_context_latency = max(set_context_latency, 2460 intel_psr_min_set_context_latency(crtc_state)); 2461 2462 return set_context_latency; 2463 } 2464 2465 static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state, 2466 struct intel_crtc *crtc) 2467 { 2468 struct intel_display *display = to_intel_display(state); 2469 struct intel_crtc_state *crtc_state = 2470 intel_atomic_get_new_crtc_state(state, crtc); 2471 struct drm_display_mode *adjusted_mode = 2472 &crtc_state->hw.adjusted_mode; 2473 int set_context_latency, max_vblank_delay; 2474 2475 set_context_latency = intel_crtc_set_context_latency(crtc_state); 2476 2477 max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1; 2478 2479 if (set_context_latency > max_vblank_delay) { 2480 drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n", 2481 crtc->base.base.id, crtc->base.name, 2482 set_context_latency, 2483 max_vblank_delay); 2484 return -EINVAL; 2485 } 2486 2487 crtc_state->set_context_latency = set_context_latency; 2488 adjusted_mode->crtc_vblank_start += set_context_latency; 2489 2490 return 0; 2491 } 2492 2493 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2494 struct intel_crtc *crtc) 2495 { 2496 struct intel_crtc_state *crtc_state = 2497 intel_atomic_get_new_crtc_state(state, crtc); 2498 int ret; 2499 2500 ret = intel_dpll_crtc_compute_clock(state, crtc); 2501 if (ret) 2502 return ret; 2503 2504 ret = intel_crtc_compute_set_context_latency(state, crtc); 2505 if (ret) 2506 return ret; 2507 2508 ret = intel_crtc_compute_pipe_src(crtc_state); 2509 if (ret) 2510 return ret; 2511 2512 ret = intel_crtc_compute_pipe_mode(crtc_state); 2513 if (ret) 2514 return ret; 2515 2516 intel_crtc_compute_pixel_rate(crtc_state); 2517 2518 if (crtc_state->has_pch_encoder) 2519 return ilk_fdi_compute_config(crtc, crtc_state); 2520 2521 intel_vrr_compute_guardband(crtc_state); 2522 2523 return 0; 2524 } 2525 2526 static void 2527 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2528 { 2529 while (*num > DATA_LINK_M_N_MASK || 2530 *den > DATA_LINK_M_N_MASK) { 2531 *num >>= 1; 2532 *den >>= 1; 2533 } 2534 } 2535 2536 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2537 u32 m, u32 n, u32 constant_n) 2538 { 2539 if (constant_n) 2540 *ret_n = constant_n; 2541 else 2542 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2543 2544 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2545 intel_reduce_m_n_ratio(ret_m, ret_n); 2546 } 2547 2548 void 2549 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 2550 int pixel_clock, int link_clock, 2551 int bw_overhead, 2552 struct intel_link_m_n *m_n) 2553 { 2554 u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); 2555 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, 2556 bw_overhead); 2557 u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); 2558 2559 /* 2560 * Windows/BIOS uses fixed M/N values always. Follow suit. 2561 * 2562 * Also several DP dongles in particular seem to be fussy 2563 * about too large link M/N values. Presumably the 20bit 2564 * value used by Windows/BIOS is acceptable to everyone. 2565 */ 2566 m_n->tu = 64; 2567 compute_m_n(&m_n->data_m, &m_n->data_n, 2568 data_m, data_n, 2569 0x8000000); 2570 2571 compute_m_n(&m_n->link_m, &m_n->link_n, 2572 pixel_clock, link_symbol_clock, 2573 0x80000); 2574 } 2575 2576 void intel_panel_sanitize_ssc(struct intel_display *display) 2577 { 2578 /* 2579 * There may be no VBT; and if the BIOS enabled SSC we can 2580 * just keep using it to avoid unnecessary flicker. Whereas if the 2581 * BIOS isn't using it, don't assume it will work even if the VBT 2582 * indicates as much. 2583 */ 2584 if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { 2585 bool bios_lvds_use_ssc = intel_de_read(display, 2586 PCH_DREF_CONTROL) & 2587 DREF_SSC1_ENABLE; 2588 2589 if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2590 drm_dbg_kms(display->drm, 2591 "SSC %s by BIOS, overriding VBT which says %s\n", 2592 str_enabled_disabled(bios_lvds_use_ssc), 2593 str_enabled_disabled(display->vbt.lvds_use_ssc)); 2594 display->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2595 } 2596 } 2597 } 2598 2599 void intel_zero_m_n(struct intel_link_m_n *m_n) 2600 { 2601 /* corresponds to 0 register value */ 2602 memset(m_n, 0, sizeof(*m_n)); 2603 m_n->tu = 1; 2604 } 2605 2606 void intel_set_m_n(struct intel_display *display, 2607 const struct intel_link_m_n *m_n, 2608 intel_reg_t data_m_reg, intel_reg_t data_n_reg, 2609 intel_reg_t link_m_reg, intel_reg_t link_n_reg) 2610 { 2611 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2612 intel_de_write(display, data_n_reg, m_n->data_n); 2613 intel_de_write(display, link_m_reg, m_n->link_m); 2614 /* 2615 * On BDW+ writing LINK_N arms the double buffered update 2616 * of all the M/N registers, so it must be written last. 2617 */ 2618 intel_de_write(display, link_n_reg, m_n->link_n); 2619 } 2620 2621 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 2622 enum transcoder transcoder) 2623 { 2624 if (display->platform.haswell) 2625 return transcoder == TRANSCODER_EDP; 2626 2627 return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; 2628 } 2629 2630 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2631 enum transcoder transcoder, 2632 const struct intel_link_m_n *m_n) 2633 { 2634 struct intel_display *display = to_intel_display(crtc); 2635 enum pipe pipe = crtc->pipe; 2636 2637 if (DISPLAY_VER(display) >= 5) 2638 intel_set_m_n(display, m_n, 2639 PIPE_DATA_M1(display, transcoder), 2640 PIPE_DATA_N1(display, transcoder), 2641 PIPE_LINK_M1(display, transcoder), 2642 PIPE_LINK_N1(display, transcoder)); 2643 else 2644 intel_set_m_n(display, m_n, 2645 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2646 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2647 } 2648 2649 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2650 enum transcoder transcoder, 2651 const struct intel_link_m_n *m_n) 2652 { 2653 struct intel_display *display = to_intel_display(crtc); 2654 2655 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 2656 return; 2657 2658 intel_set_m_n(display, m_n, 2659 PIPE_DATA_M2(display, transcoder), 2660 PIPE_DATA_N2(display, transcoder), 2661 PIPE_LINK_M2(display, transcoder), 2662 PIPE_LINK_N2(display, transcoder)); 2663 } 2664 2665 static bool 2666 transcoder_has_vrr(const struct intel_crtc_state *crtc_state) 2667 { 2668 struct intel_display *display = to_intel_display(crtc_state); 2669 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2670 2671 return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder); 2672 } 2673 2674 void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state, 2675 enum transcoder transcoder) 2676 { 2677 struct intel_display *display = to_intel_display(crtc_state); 2678 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2679 enum pipe pipe = crtc->pipe; 2680 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2681 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2682 int vsyncshift = 0; 2683 2684 drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder)); 2685 2686 /* We need to be careful not to changed the adjusted mode, for otherwise 2687 * the hw state checker will get angry at the mismatch. */ 2688 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2689 crtc_vtotal = adjusted_mode->crtc_vtotal; 2690 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2691 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2692 2693 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2694 /* the chip adds 2 halflines automatically */ 2695 crtc_vtotal -= 1; 2696 crtc_vblank_end -= 1; 2697 2698 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2699 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2700 else 2701 vsyncshift = adjusted_mode->crtc_hsync_start - 2702 adjusted_mode->crtc_htotal / 2; 2703 if (vsyncshift < 0) 2704 vsyncshift += adjusted_mode->crtc_htotal; 2705 } 2706 2707 /* 2708 * VBLANK_START no longer works on ADL+, instead we must use 2709 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2710 */ 2711 if (DISPLAY_VER(display) >= 13) { 2712 intel_de_write(display, 2713 TRANS_SET_CONTEXT_LATENCY(display, transcoder), 2714 crtc_state->set_context_latency); 2715 2716 /* 2717 * VBLANK_START not used by hw, just clear it 2718 * to make it stand out in register dumps. 2719 */ 2720 crtc_vblank_start = 1; 2721 } else if (DISPLAY_VER(display) == 12) { 2722 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2723 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2724 } 2725 2726 if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35) 2727 intel_de_write(display, 2728 TRANS_VSYNCSHIFT(display, transcoder), 2729 vsyncshift); 2730 2731 intel_de_write(display, TRANS_HTOTAL(display, transcoder), 2732 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2733 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2734 intel_de_write(display, TRANS_HBLANK(display, transcoder), 2735 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2736 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2737 intel_de_write(display, TRANS_HSYNC(display, transcoder), 2738 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2739 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2740 2741 if (display->platform.novalake && 2742 IS_DISPLAY_STEP(display, STEP_A0, STEP_C0)) 2743 crtc_vtotal = 1; 2744 2745 intel_de_write(display, TRANS_VTOTAL(display, transcoder), 2746 VACTIVE(crtc_vdisplay - 1) | 2747 VTOTAL(crtc_vtotal - 1)); 2748 intel_de_write(display, TRANS_VBLANK(display, transcoder), 2749 VBLANK_START(crtc_vblank_start - 1) | 2750 VBLANK_END(crtc_vblank_end - 1)); 2751 intel_de_write(display, TRANS_VSYNC(display, transcoder), 2752 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2753 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2754 2755 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2756 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2757 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2758 * bits. */ 2759 if (display->platform.haswell && transcoder == TRANSCODER_EDP && 2760 (pipe == PIPE_B || pipe == PIPE_C)) 2761 intel_de_write(display, TRANS_VTOTAL(display, pipe), 2762 VACTIVE(crtc_vdisplay - 1) | 2763 VTOTAL(crtc_vtotal - 1)); 2764 2765 if (DISPLAY_VER(display) >= 30 && 2766 transcoder != TRANSCODER_CMTG0 && 2767 transcoder != TRANSCODER_CMTG1) { 2768 /* 2769 * Address issues for resolutions with high refresh rate that 2770 * have small Hblank, specifically where Hblank is smaller than 2771 * one MTP. Simulations indicate this will address the 2772 * jitter issues that currently causes BS to be immediately 2773 * followed by BE which DPRX devices are unable to handle. 2774 * https://groups.vesa.org/wg/DP/document/20494 2775 */ 2776 intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder), 2777 crtc_state->min_hblank); 2778 } 2779 } 2780 2781 void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state, 2782 enum transcoder transcoder) 2783 { 2784 struct intel_display *display = to_intel_display(crtc_state); 2785 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2786 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2787 2788 drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder)); 2789 2790 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2791 crtc_vtotal = adjusted_mode->crtc_vtotal; 2792 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2793 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2794 2795 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2796 /* the chip adds 2 halflines automatically */ 2797 crtc_vtotal -= 1; 2798 crtc_vblank_end -= 1; 2799 } 2800 2801 if (DISPLAY_VER(display) >= 13) { 2802 intel_de_write(display, 2803 TRANS_SET_CONTEXT_LATENCY(display, transcoder), 2804 crtc_state->set_context_latency); 2805 2806 /* 2807 * VBLANK_START not used by hw, just clear it 2808 * to make it stand out in register dumps. 2809 */ 2810 crtc_vblank_start = 1; 2811 } else if (DISPLAY_VER(display) == 12) { 2812 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2813 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2814 } 2815 2816 /* 2817 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. 2818 * But let's write it anyway to keep the state checker happy. 2819 */ 2820 intel_de_write(display, TRANS_VBLANK(display, transcoder), 2821 VBLANK_START(crtc_vblank_start - 1) | 2822 VBLANK_END(crtc_vblank_end - 1)); 2823 2824 /* 2825 * DP doesn't have vertical sync, so TRANS_VSYNC only affects 2826 * the position of the vsync interrupt (and does so even when 2827 * using the VRR timing generator!). Thus updating TRANS_VSYNC 2828 * here seems fine even if it isn't double buffered. 2829 */ 2830 intel_de_write(display, TRANS_VSYNC(display, transcoder), 2831 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2832 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2833 2834 /* 2835 * The double buffer latch point for TRANS_VTOTAL 2836 * is the transcoder's undelayed vblank. 2837 */ 2838 if (display->platform.novalake && 2839 IS_DISPLAY_STEP(display, STEP_A0, STEP_C0)) 2840 crtc_vtotal = 1; 2841 2842 intel_de_write(display, TRANS_VTOTAL(display, transcoder), 2843 VACTIVE(crtc_vdisplay - 1) | 2844 VTOTAL(crtc_vtotal - 1)); 2845 } 2846 2847 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2848 { 2849 struct intel_display *display = to_intel_display(crtc_state); 2850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2851 int width = drm_rect_width(&crtc_state->pipe_src); 2852 int height = drm_rect_height(&crtc_state->pipe_src); 2853 enum pipe pipe = crtc->pipe; 2854 2855 /* pipesrc controls the size that is scaled from, which should 2856 * always be the user's requested size. 2857 */ 2858 intel_de_write(display, PIPESRC(display, pipe), 2859 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2860 } 2861 2862 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2863 { 2864 struct intel_display *display = to_intel_display(crtc_state); 2865 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2866 2867 if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35) 2868 return false; 2869 2870 if (DISPLAY_VER(display) >= 9 || 2871 display->platform.broadwell || display->platform.haswell) 2872 return intel_de_read(display, 2873 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2874 else 2875 return intel_de_read(display, 2876 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2877 } 2878 2879 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2880 struct intel_crtc_state *pipe_config) 2881 { 2882 struct intel_display *display = to_intel_display(crtc); 2883 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2884 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2885 u32 tmp; 2886 2887 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); 2888 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2889 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2890 2891 if (!transcoder_is_dsi(cpu_transcoder)) { 2892 tmp = intel_de_read(display, 2893 TRANS_HBLANK(display, cpu_transcoder)); 2894 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2895 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2896 } 2897 2898 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); 2899 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2900 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2901 2902 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); 2903 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2904 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2905 2906 /* FIXME TGL+ DSI transcoders have this! */ 2907 if (!transcoder_is_dsi(cpu_transcoder)) { 2908 tmp = intel_de_read(display, 2909 TRANS_VBLANK(display, cpu_transcoder)); 2910 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2911 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2912 } 2913 tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)); 2914 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2915 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2916 2917 if (intel_pipe_is_interlaced(pipe_config)) { 2918 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2919 adjusted_mode->crtc_vtotal += 1; 2920 adjusted_mode->crtc_vblank_end += 1; 2921 } 2922 2923 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) { 2924 pipe_config->set_context_latency = 2925 intel_de_read(display, 2926 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); 2927 adjusted_mode->crtc_vblank_start = 2928 adjusted_mode->crtc_vdisplay + 2929 pipe_config->set_context_latency; 2930 } else if (DISPLAY_VER(display) == 12) { 2931 /* 2932 * TGL doesn't have a dedicated register for SCL. 2933 * Instead, the hardware derives SCL from the difference between 2934 * TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive. 2935 * To reflect the HW behaviour, readout the value for SCL as 2936 * Vblank start - Vactive. 2937 */ 2938 pipe_config->set_context_latency = 2939 adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 2940 } 2941 2942 if (DISPLAY_VER(display) >= 30) 2943 pipe_config->min_hblank = intel_de_read(display, 2944 DP_MIN_HBLANK_CTL(cpu_transcoder)); 2945 } 2946 2947 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2948 { 2949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2950 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2951 enum pipe primary_pipe, pipe = crtc->pipe; 2952 int width; 2953 2954 if (num_pipes == 1) 2955 return; 2956 2957 primary_pipe = joiner_primary_pipe(crtc_state); 2958 width = drm_rect_width(&crtc_state->pipe_src); 2959 2960 drm_rect_translate_to(&crtc_state->pipe_src, 2961 (pipe - primary_pipe) * width, 0); 2962 } 2963 2964 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2965 struct intel_crtc_state *pipe_config) 2966 { 2967 struct intel_display *display = to_intel_display(crtc); 2968 u32 tmp; 2969 2970 tmp = intel_de_read(display, PIPESRC(display, crtc->pipe)); 2971 2972 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2973 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2974 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2975 2976 intel_joiner_adjust_pipe_src(pipe_config); 2977 } 2978 2979 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2980 { 2981 struct intel_display *display = to_intel_display(crtc_state); 2982 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2983 u32 val = 0; 2984 2985 /* 2986 * - We keep both pipes enabled on 830 2987 * - During modeset the pipe is still disabled and must remain so 2988 * - During fastset the pipe is already enabled and must remain so 2989 */ 2990 if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state)) 2991 val |= TRANSCONF_ENABLE; 2992 2993 if (crtc_state->double_wide) 2994 val |= TRANSCONF_DOUBLE_WIDE; 2995 2996 /* only g4x and later have fancy bpc/dither controls */ 2997 if (display->platform.g4x || display->platform.valleyview || 2998 display->platform.cherryview) { 2999 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3000 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3001 val |= TRANSCONF_DITHER_EN | 3002 TRANSCONF_DITHER_TYPE_SP; 3003 3004 switch (crtc_state->pipe_bpp) { 3005 default: 3006 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3007 MISSING_CASE(crtc_state->pipe_bpp); 3008 fallthrough; 3009 case 18: 3010 val |= TRANSCONF_BPC_6; 3011 break; 3012 case 24: 3013 val |= TRANSCONF_BPC_8; 3014 break; 3015 case 30: 3016 val |= TRANSCONF_BPC_10; 3017 break; 3018 } 3019 } 3020 3021 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3022 if (DISPLAY_VER(display) < 4 || 3023 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3024 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 3025 else 3026 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 3027 } else { 3028 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 3029 } 3030 3031 if ((display->platform.valleyview || display->platform.cherryview) && 3032 crtc_state->limited_color_range) 3033 val |= TRANSCONF_COLOR_RANGE_SELECT; 3034 3035 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3036 3037 if (crtc_state->wgc_enable) 3038 val |= TRANSCONF_WGC_ENABLE; 3039 3040 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3041 3042 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3043 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3044 } 3045 3046 static enum intel_output_format 3047 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 3048 { 3049 struct intel_display *display = to_intel_display(crtc); 3050 u32 tmp; 3051 3052 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3053 3054 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3055 /* 3056 * We support 4:2:0 in full blend mode only. 3057 * For xe3_lpd+ this is implied in YUV420 Enable bit. 3058 * Ensure the same for prior platforms in YUV420 Mode bit. 3059 */ 3060 if (DISPLAY_VER(display) < 30) 3061 drm_WARN_ON(display->drm, 3062 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3063 3064 return INTEL_OUTPUT_FORMAT_YCBCR420; 3065 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 3066 return INTEL_OUTPUT_FORMAT_YCBCR444; 3067 } else { 3068 return INTEL_OUTPUT_FORMAT_RGB; 3069 } 3070 } 3071 3072 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3073 struct intel_crtc_state *pipe_config) 3074 { 3075 struct intel_display *display = to_intel_display(crtc); 3076 enum intel_display_power_domain power_domain; 3077 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3078 struct ref_tracker *wakeref; 3079 bool ret = false; 3080 u32 tmp; 3081 3082 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3083 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3084 if (!wakeref) 3085 return false; 3086 3087 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3088 if (!(tmp & TRANSCONF_ENABLE)) 3089 goto out; 3090 3091 pipe_config->cpu_transcoder = cpu_transcoder; 3092 3093 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3094 pipe_config->sink_format = pipe_config->output_format; 3095 3096 if (display->platform.g4x || display->platform.valleyview || 3097 display->platform.cherryview) { 3098 switch (tmp & TRANSCONF_BPC_MASK) { 3099 case TRANSCONF_BPC_6: 3100 pipe_config->pipe_bpp = 18; 3101 break; 3102 case TRANSCONF_BPC_8: 3103 pipe_config->pipe_bpp = 24; 3104 break; 3105 case TRANSCONF_BPC_10: 3106 pipe_config->pipe_bpp = 30; 3107 break; 3108 default: 3109 MISSING_CASE(tmp); 3110 break; 3111 } 3112 } 3113 3114 if ((display->platform.valleyview || display->platform.cherryview) && 3115 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3116 pipe_config->limited_color_range = true; 3117 3118 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3119 3120 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3121 3122 if ((display->platform.valleyview || display->platform.cherryview) && 3123 (tmp & TRANSCONF_WGC_ENABLE)) 3124 pipe_config->wgc_enable = true; 3125 3126 intel_color_get_config(pipe_config); 3127 3128 if (HAS_DOUBLE_WIDE(display)) 3129 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3130 3131 intel_get_transcoder_timings(crtc, pipe_config); 3132 intel_get_pipe_src_size(crtc, pipe_config); 3133 3134 i9xx_pfit_get_config(pipe_config); 3135 3136 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); 3137 3138 if (DISPLAY_VER(display) >= 4) { 3139 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; 3140 pipe_config->pixel_multiplier = 3141 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3142 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3143 } else if (display->platform.i945g || display->platform.i945gm || 3144 display->platform.g33 || display->platform.pineview) { 3145 tmp = pipe_config->dpll_hw_state.i9xx.dpll; 3146 pipe_config->pixel_multiplier = 3147 ((tmp & SDVO_MULTIPLIER_MASK) 3148 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3149 } else { 3150 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3151 * port and will be fixed up in the encoder->get_config 3152 * function. */ 3153 pipe_config->pixel_multiplier = 1; 3154 } 3155 3156 if (display->platform.cherryview) 3157 chv_crtc_clock_get(pipe_config); 3158 else if (display->platform.valleyview) 3159 vlv_crtc_clock_get(pipe_config); 3160 else 3161 i9xx_crtc_clock_get(pipe_config); 3162 3163 /* 3164 * Normally the dotclock is filled in by the encoder .get_config() 3165 * but in case the pipe is enabled w/o any ports we need a sane 3166 * default. 3167 */ 3168 pipe_config->hw.adjusted_mode.crtc_clock = 3169 pipe_config->port_clock / pipe_config->pixel_multiplier; 3170 3171 ret = true; 3172 3173 out: 3174 intel_display_power_put(display, power_domain, wakeref); 3175 3176 return ret; 3177 } 3178 3179 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3180 { 3181 struct intel_display *display = to_intel_display(crtc_state); 3182 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3183 u32 val = 0; 3184 3185 /* 3186 * - During modeset the pipe is still disabled and must remain so 3187 * - During fastset the pipe is already enabled and must remain so 3188 */ 3189 if (!intel_crtc_needs_modeset(crtc_state)) 3190 val |= TRANSCONF_ENABLE; 3191 3192 switch (crtc_state->pipe_bpp) { 3193 default: 3194 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3195 MISSING_CASE(crtc_state->pipe_bpp); 3196 fallthrough; 3197 case 18: 3198 val |= TRANSCONF_BPC_6; 3199 break; 3200 case 24: 3201 val |= TRANSCONF_BPC_8; 3202 break; 3203 case 30: 3204 val |= TRANSCONF_BPC_10; 3205 break; 3206 case 36: 3207 val |= TRANSCONF_BPC_12; 3208 break; 3209 } 3210 3211 if (crtc_state->dither) 3212 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3213 3214 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3215 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3216 else 3217 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3218 3219 /* 3220 * This would end up with an odd purple hue over 3221 * the entire display. Make sure we don't do it. 3222 */ 3223 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 3224 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3225 3226 if (crtc_state->limited_color_range && 3227 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3228 val |= TRANSCONF_COLOR_RANGE_SELECT; 3229 3230 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3231 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3232 3233 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3234 3235 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3236 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3237 3238 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3239 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3240 } 3241 3242 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3243 { 3244 struct intel_display *display = to_intel_display(crtc_state); 3245 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3246 u32 val = 0; 3247 3248 /* 3249 * - During modeset the pipe is still disabled and must remain so 3250 * - During fastset the pipe is already enabled and must remain so 3251 */ 3252 if (!intel_crtc_needs_modeset(crtc_state)) 3253 val |= TRANSCONF_ENABLE; 3254 3255 if (display->platform.haswell && crtc_state->dither) 3256 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3257 3258 if (DISPLAY_VER(display) < 35) { 3259 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3260 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3261 else 3262 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3263 } 3264 3265 if (display->platform.haswell && 3266 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3267 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3268 3269 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3270 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3271 } 3272 3273 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 3274 const struct intel_crtc_state *crtc_state) 3275 { 3276 struct intel_display *display = to_intel_display(crtc_state); 3277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3278 u32 val = 0; 3279 3280 switch (crtc_state->pipe_bpp) { 3281 case 18: 3282 val |= PIPE_MISC_BPC_6; 3283 break; 3284 case 24: 3285 val |= PIPE_MISC_BPC_8; 3286 break; 3287 case 30: 3288 val |= PIPE_MISC_BPC_10; 3289 break; 3290 case 36: 3291 /* Port output 12BPC defined for ADLP+ */ 3292 if (DISPLAY_VER(display) >= 13) 3293 val |= PIPE_MISC_BPC_12_ADLP; 3294 break; 3295 default: 3296 MISSING_CASE(crtc_state->pipe_bpp); 3297 break; 3298 } 3299 3300 if (crtc_state->dither) 3301 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3302 3303 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3304 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3305 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3306 3307 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3308 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : 3309 PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND; 3310 3311 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) 3312 val |= PIPE_MISC_HDR_MODE_PRECISION; 3313 3314 if (DISPLAY_VER(display) >= 12) 3315 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3316 3317 /* allow PSR with sprite enabled */ 3318 if (display->platform.broadwell) 3319 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3320 3321 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val); 3322 } 3323 3324 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3325 { 3326 struct intel_display *display = to_intel_display(crtc); 3327 u32 tmp; 3328 3329 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3330 3331 switch (tmp & PIPE_MISC_BPC_MASK) { 3332 case PIPE_MISC_BPC_6: 3333 return 18; 3334 case PIPE_MISC_BPC_8: 3335 return 24; 3336 case PIPE_MISC_BPC_10: 3337 return 30; 3338 /* 3339 * PORT OUTPUT 12 BPC defined for ADLP+. 3340 * 3341 * TODO: 3342 * For previous platforms with DSI interface, bits 5:7 3343 * are used for storing pipe_bpp irrespective of dithering. 3344 * Since the value of 12 BPC is not defined for these bits 3345 * on older platforms, need to find a workaround for 12 BPC 3346 * MIPI DSI HW readout. 3347 */ 3348 case PIPE_MISC_BPC_12_ADLP: 3349 if (DISPLAY_VER(display) >= 13) 3350 return 36; 3351 fallthrough; 3352 default: 3353 MISSING_CASE(tmp); 3354 return 0; 3355 } 3356 } 3357 3358 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3359 { 3360 /* 3361 * Account for spread spectrum to avoid 3362 * oversubscribing the link. Max center spread 3363 * is 2.5%; use 5% for safety's sake. 3364 */ 3365 u32 bps = target_clock * bpp * 21 / 20; 3366 return DIV_ROUND_UP(bps, link_bw * 8); 3367 } 3368 3369 void intel_get_m_n(struct intel_display *display, 3370 struct intel_link_m_n *m_n, 3371 intel_reg_t data_m_reg, intel_reg_t data_n_reg, 3372 intel_reg_t link_m_reg, intel_reg_t link_n_reg) 3373 { 3374 m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; 3375 m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; 3376 m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; 3377 m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; 3378 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; 3379 } 3380 3381 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3382 enum transcoder transcoder, 3383 struct intel_link_m_n *m_n) 3384 { 3385 struct intel_display *display = to_intel_display(crtc); 3386 enum pipe pipe = crtc->pipe; 3387 3388 if (DISPLAY_VER(display) >= 5) 3389 intel_get_m_n(display, m_n, 3390 PIPE_DATA_M1(display, transcoder), 3391 PIPE_DATA_N1(display, transcoder), 3392 PIPE_LINK_M1(display, transcoder), 3393 PIPE_LINK_N1(display, transcoder)); 3394 else 3395 intel_get_m_n(display, m_n, 3396 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3397 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3398 } 3399 3400 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3401 enum transcoder transcoder, 3402 struct intel_link_m_n *m_n) 3403 { 3404 struct intel_display *display = to_intel_display(crtc); 3405 3406 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 3407 return; 3408 3409 intel_get_m_n(display, m_n, 3410 PIPE_DATA_M2(display, transcoder), 3411 PIPE_DATA_N2(display, transcoder), 3412 PIPE_LINK_M2(display, transcoder), 3413 PIPE_LINK_N2(display, transcoder)); 3414 } 3415 3416 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3417 struct intel_crtc_state *pipe_config) 3418 { 3419 struct intel_display *display = to_intel_display(crtc); 3420 enum intel_display_power_domain power_domain; 3421 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3422 struct ref_tracker *wakeref; 3423 bool ret = false; 3424 u32 tmp; 3425 3426 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3427 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3428 if (!wakeref) 3429 return false; 3430 3431 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3432 if (!(tmp & TRANSCONF_ENABLE)) 3433 goto out; 3434 3435 pipe_config->cpu_transcoder = cpu_transcoder; 3436 3437 switch (tmp & TRANSCONF_BPC_MASK) { 3438 case TRANSCONF_BPC_6: 3439 pipe_config->pipe_bpp = 18; 3440 break; 3441 case TRANSCONF_BPC_8: 3442 pipe_config->pipe_bpp = 24; 3443 break; 3444 case TRANSCONF_BPC_10: 3445 pipe_config->pipe_bpp = 30; 3446 break; 3447 case TRANSCONF_BPC_12: 3448 pipe_config->pipe_bpp = 36; 3449 break; 3450 default: 3451 break; 3452 } 3453 3454 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3455 pipe_config->limited_color_range = true; 3456 3457 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3458 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3459 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3460 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3461 break; 3462 default: 3463 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3464 break; 3465 } 3466 3467 pipe_config->sink_format = pipe_config->output_format; 3468 3469 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3470 3471 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3472 3473 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3474 3475 intel_color_get_config(pipe_config); 3476 3477 pipe_config->pixel_multiplier = 1; 3478 3479 ilk_pch_get_config(pipe_config); 3480 3481 intel_get_transcoder_timings(crtc, pipe_config); 3482 intel_get_pipe_src_size(crtc, pipe_config); 3483 3484 ilk_pfit_get_config(pipe_config); 3485 3486 ret = true; 3487 3488 out: 3489 intel_display_power_put(display, power_domain, wakeref); 3490 3491 return ret; 3492 } 3493 3494 static u8 joiner_pipes(struct intel_display *display) 3495 { 3496 u8 pipes; 3497 3498 if (DISPLAY_VER(display) >= 12) 3499 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3500 else if (DISPLAY_VER(display) >= 11) 3501 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3502 else 3503 pipes = 0; 3504 3505 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; 3506 } 3507 3508 static bool transcoder_ddi_func_is_enabled(struct intel_display *display, 3509 enum transcoder cpu_transcoder) 3510 { 3511 enum intel_display_power_domain power_domain; 3512 u32 tmp = 0; 3513 3514 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3515 3516 with_intel_display_power_if_enabled(display, power_domain) 3517 tmp = intel_de_read(display, 3518 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3519 3520 return tmp & TRANS_DDI_FUNC_ENABLE; 3521 } 3522 3523 static void enabled_uncompressed_joiner_pipes(struct intel_display *display, 3524 u8 *primary_pipes, u8 *secondary_pipes) 3525 { 3526 struct intel_crtc *crtc; 3527 3528 *primary_pipes = 0; 3529 *secondary_pipes = 0; 3530 3531 if (!HAS_UNCOMPRESSED_JOINER(display)) 3532 return; 3533 3534 for_each_intel_crtc_in_pipe_mask(display, crtc, 3535 joiner_pipes(display)) { 3536 enum intel_display_power_domain power_domain; 3537 enum pipe pipe = crtc->pipe; 3538 3539 power_domain = POWER_DOMAIN_PIPE(pipe); 3540 with_intel_display_power_if_enabled(display, power_domain) { 3541 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3542 3543 if (tmp & UNCOMPRESSED_JOINER_PRIMARY) 3544 *primary_pipes |= BIT(pipe); 3545 if (tmp & UNCOMPRESSED_JOINER_SECONDARY) 3546 *secondary_pipes |= BIT(pipe); 3547 } 3548 } 3549 } 3550 3551 static void enabled_bigjoiner_pipes(struct intel_display *display, 3552 u8 *primary_pipes, u8 *secondary_pipes) 3553 { 3554 struct intel_crtc *crtc; 3555 3556 *primary_pipes = 0; 3557 *secondary_pipes = 0; 3558 3559 if (!HAS_BIGJOINER(display)) 3560 return; 3561 3562 for_each_intel_crtc_in_pipe_mask(display, crtc, 3563 joiner_pipes(display)) { 3564 enum intel_display_power_domain power_domain; 3565 enum pipe pipe = crtc->pipe; 3566 3567 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3568 with_intel_display_power_if_enabled(display, power_domain) { 3569 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3570 3571 if (!(tmp & BIG_JOINER_ENABLE)) 3572 continue; 3573 3574 if (tmp & PRIMARY_BIG_JOINER_ENABLE) 3575 *primary_pipes |= BIT(pipe); 3576 else 3577 *secondary_pipes |= BIT(pipe); 3578 } 3579 } 3580 } 3581 3582 static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes) 3583 { 3584 u8 secondary_pipes = 0; 3585 3586 for (int i = 1; i < num_pipes; i++) 3587 secondary_pipes |= primary_pipes << i; 3588 3589 return secondary_pipes; 3590 } 3591 3592 static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes) 3593 { 3594 return expected_secondary_pipes(uncompjoiner_primary_pipes, 2); 3595 } 3596 3597 static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes) 3598 { 3599 return expected_secondary_pipes(bigjoiner_primary_pipes, 2); 3600 } 3601 3602 static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes) 3603 { 3604 primary_pipes &= GENMASK(pipe, 0); 3605 3606 return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0; 3607 } 3608 3609 static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes) 3610 { 3611 return expected_secondary_pipes(ultrajoiner_primary_pipes, 4); 3612 } 3613 3614 static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes, 3615 u8 ultrajoiner_secondary_pipes) 3616 { 3617 return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3; 3618 } 3619 3620 static void enabled_ultrajoiner_pipes(struct intel_display *display, 3621 u8 *primary_pipes, u8 *secondary_pipes) 3622 { 3623 struct intel_crtc *crtc; 3624 3625 *primary_pipes = 0; 3626 *secondary_pipes = 0; 3627 3628 if (!HAS_ULTRAJOINER(display)) 3629 return; 3630 3631 for_each_intel_crtc_in_pipe_mask(display, crtc, 3632 joiner_pipes(display)) { 3633 enum intel_display_power_domain power_domain; 3634 enum pipe pipe = crtc->pipe; 3635 3636 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3637 with_intel_display_power_if_enabled(display, power_domain) { 3638 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3639 3640 if (!(tmp & ULTRA_JOINER_ENABLE)) 3641 continue; 3642 3643 if (tmp & PRIMARY_ULTRA_JOINER_ENABLE) 3644 *primary_pipes |= BIT(pipe); 3645 else 3646 *secondary_pipes |= BIT(pipe); 3647 } 3648 } 3649 } 3650 3651 static void enabled_joiner_pipes(struct intel_display *display, 3652 enum pipe pipe, 3653 u8 *primary_pipe, u8 *secondary_pipes) 3654 { 3655 u8 primary_ultrajoiner_pipes; 3656 u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes; 3657 u8 secondary_ultrajoiner_pipes; 3658 u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes; 3659 u8 ultrajoiner_pipes; 3660 u8 uncompressed_joiner_pipes, bigjoiner_pipes; 3661 3662 enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes, 3663 &secondary_ultrajoiner_pipes); 3664 /* 3665 * For some strange reason the last pipe in the set of four 3666 * shouldn't have ultrajoiner enable bit set in hardware. 3667 * Set the bit anyway to make life easier. 3668 */ 3669 drm_WARN_ON(display->drm, 3670 expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != 3671 secondary_ultrajoiner_pipes); 3672 secondary_ultrajoiner_pipes = 3673 fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes, 3674 secondary_ultrajoiner_pipes); 3675 3676 drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); 3677 3678 enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes, 3679 &secondary_uncompressed_joiner_pipes); 3680 3681 drm_WARN_ON(display->drm, 3682 (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0); 3683 3684 enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes, 3685 &secondary_bigjoiner_pipes); 3686 3687 drm_WARN_ON(display->drm, 3688 (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0); 3689 3690 ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes; 3691 uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes | 3692 secondary_uncompressed_joiner_pipes; 3693 bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes; 3694 3695 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes, 3696 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n", 3697 ultrajoiner_pipes, bigjoiner_pipes); 3698 3699 drm_WARN(display->drm, secondary_ultrajoiner_pipes != 3700 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3701 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n", 3702 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3703 secondary_ultrajoiner_pipes); 3704 3705 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0, 3706 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n", 3707 uncompressed_joiner_pipes, bigjoiner_pipes); 3708 3709 drm_WARN(display->drm, secondary_bigjoiner_pipes != 3710 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3711 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n", 3712 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3713 secondary_bigjoiner_pipes); 3714 3715 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes != 3716 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3717 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n", 3718 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3719 secondary_uncompressed_joiner_pipes); 3720 3721 *primary_pipe = 0; 3722 *secondary_pipes = 0; 3723 3724 if (ultrajoiner_pipes & BIT(pipe)) { 3725 *primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes); 3726 *secondary_pipes = secondary_ultrajoiner_pipes & 3727 expected_ultrajoiner_secondary_pipes(*primary_pipe); 3728 3729 drm_WARN(display->drm, 3730 expected_ultrajoiner_secondary_pipes(*primary_pipe) != 3731 *secondary_pipes, 3732 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3733 *primary_pipe, 3734 expected_ultrajoiner_secondary_pipes(*primary_pipe), 3735 *secondary_pipes); 3736 return; 3737 } 3738 3739 if (uncompressed_joiner_pipes & BIT(pipe)) { 3740 *primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes); 3741 *secondary_pipes = secondary_uncompressed_joiner_pipes & 3742 expected_uncompressed_joiner_secondary_pipes(*primary_pipe); 3743 3744 drm_WARN(display->drm, 3745 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) != 3746 *secondary_pipes, 3747 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3748 *primary_pipe, 3749 expected_uncompressed_joiner_secondary_pipes(*primary_pipe), 3750 *secondary_pipes); 3751 return; 3752 } 3753 3754 if (bigjoiner_pipes & BIT(pipe)) { 3755 *primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes); 3756 *secondary_pipes = secondary_bigjoiner_pipes & 3757 expected_bigjoiner_secondary_pipes(*primary_pipe); 3758 3759 drm_WARN(display->drm, 3760 expected_bigjoiner_secondary_pipes(*primary_pipe) != 3761 *secondary_pipes, 3762 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3763 *primary_pipe, 3764 expected_bigjoiner_secondary_pipes(*primary_pipe), 3765 *secondary_pipes); 3766 return; 3767 } 3768 } 3769 3770 static u8 hsw_panel_transcoders(struct intel_display *display) 3771 { 3772 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3773 3774 if (DISPLAY_VER(display) >= 11) 3775 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3776 3777 return panel_transcoder_mask; 3778 } 3779 3780 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3781 { 3782 struct intel_display *display = to_intel_display(crtc); 3783 u8 panel_transcoder_mask = hsw_panel_transcoders(display); 3784 enum transcoder cpu_transcoder; 3785 u8 primary_pipe, secondary_pipes; 3786 u8 enabled_transcoders = 0; 3787 3788 /* 3789 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3790 * consistency and less surprising code; it's in always on power). 3791 */ 3792 for_each_cpu_transcoder_masked(display, cpu_transcoder, 3793 panel_transcoder_mask) { 3794 enum intel_display_power_domain power_domain; 3795 enum pipe trans_pipe; 3796 u32 tmp = 0; 3797 3798 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3799 with_intel_display_power_if_enabled(display, power_domain) 3800 tmp = intel_de_read(display, 3801 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3802 3803 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3804 continue; 3805 3806 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3807 default: 3808 drm_WARN(display->drm, 1, 3809 "unknown pipe linked to transcoder %s\n", 3810 transcoder_name(cpu_transcoder)); 3811 fallthrough; 3812 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3813 case TRANS_DDI_EDP_INPUT_A_ON: 3814 trans_pipe = PIPE_A; 3815 break; 3816 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3817 trans_pipe = PIPE_B; 3818 break; 3819 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3820 trans_pipe = PIPE_C; 3821 break; 3822 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3823 trans_pipe = PIPE_D; 3824 break; 3825 } 3826 3827 if (trans_pipe == crtc->pipe) 3828 enabled_transcoders |= BIT(cpu_transcoder); 3829 } 3830 3831 /* single pipe or joiner primary */ 3832 cpu_transcoder = (enum transcoder) crtc->pipe; 3833 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3834 enabled_transcoders |= BIT(cpu_transcoder); 3835 3836 /* joiner secondary -> consider the primary pipe's transcoder as well */ 3837 enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes); 3838 if (secondary_pipes & BIT(crtc->pipe)) { 3839 cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1; 3840 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3841 enabled_transcoders |= BIT(cpu_transcoder); 3842 } 3843 3844 return enabled_transcoders; 3845 } 3846 3847 static bool has_edp_transcoders(u8 enabled_transcoders) 3848 { 3849 return enabled_transcoders & BIT(TRANSCODER_EDP); 3850 } 3851 3852 static bool has_dsi_transcoders(u8 enabled_transcoders) 3853 { 3854 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3855 BIT(TRANSCODER_DSI_1)); 3856 } 3857 3858 static bool has_pipe_transcoders(u8 enabled_transcoders) 3859 { 3860 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3861 BIT(TRANSCODER_DSI_0) | 3862 BIT(TRANSCODER_DSI_1)); 3863 } 3864 3865 static void assert_enabled_transcoders(struct intel_display *display, 3866 u8 enabled_transcoders) 3867 { 3868 /* Only one type of transcoder please */ 3869 drm_WARN_ON(display->drm, 3870 has_edp_transcoders(enabled_transcoders) + 3871 has_dsi_transcoders(enabled_transcoders) + 3872 has_pipe_transcoders(enabled_transcoders) > 1); 3873 3874 /* Only DSI transcoders can be ganged */ 3875 drm_WARN_ON(display->drm, 3876 !has_dsi_transcoders(enabled_transcoders) && 3877 !is_power_of_2(enabled_transcoders)); 3878 } 3879 3880 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3881 struct intel_crtc_state *pipe_config, 3882 struct intel_display_power_domain_set *power_domain_set) 3883 { 3884 struct intel_display *display = to_intel_display(crtc); 3885 unsigned long enabled_transcoders; 3886 u32 tmp; 3887 3888 enabled_transcoders = hsw_enabled_transcoders(crtc); 3889 if (!enabled_transcoders) 3890 return false; 3891 3892 assert_enabled_transcoders(display, enabled_transcoders); 3893 3894 /* 3895 * With the exception of DSI we should only ever have 3896 * a single enabled transcoder. With DSI let's just 3897 * pick the first one. 3898 */ 3899 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3900 3901 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3902 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3903 return false; 3904 3905 if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) { 3906 tmp = intel_de_read(display, 3907 TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder)); 3908 3909 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3910 pipe_config->pch_pfit.force_thru = true; 3911 } 3912 3913 tmp = intel_de_read(display, 3914 TRANSCONF(display, pipe_config->cpu_transcoder)); 3915 3916 return tmp & TRANSCONF_ENABLE; 3917 } 3918 3919 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3920 struct intel_crtc_state *pipe_config, 3921 struct intel_display_power_domain_set *power_domain_set) 3922 { 3923 struct intel_display *display = to_intel_display(crtc); 3924 enum transcoder cpu_transcoder; 3925 enum port port; 3926 u32 tmp; 3927 3928 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3929 if (port == PORT_A) 3930 cpu_transcoder = TRANSCODER_DSI_A; 3931 else 3932 cpu_transcoder = TRANSCODER_DSI_C; 3933 3934 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3935 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3936 continue; 3937 3938 /* 3939 * The PLL needs to be enabled with a valid divider 3940 * configuration, otherwise accessing DSI registers will hang 3941 * the machine. See BSpec North Display Engine 3942 * registers/MIPI[BXT]. We can break out here early, since we 3943 * need the same DSI PLL to be enabled for both DSI ports. 3944 */ 3945 if (!bxt_dsi_pll_is_enabled(display)) 3946 break; 3947 3948 /* XXX: this works for video mode only */ 3949 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); 3950 if (!(tmp & DPI_ENABLE)) 3951 continue; 3952 3953 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 3954 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3955 continue; 3956 3957 pipe_config->cpu_transcoder = cpu_transcoder; 3958 break; 3959 } 3960 3961 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3962 } 3963 3964 static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) 3965 { 3966 struct intel_display *display = to_intel_display(crtc_state); 3967 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3968 u8 primary_pipe, secondary_pipes; 3969 enum pipe pipe = crtc->pipe; 3970 3971 enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes); 3972 3973 if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0) 3974 return; 3975 3976 crtc_state->joiner_pipes = primary_pipe | secondary_pipes; 3977 } 3978 3979 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3980 struct intel_crtc_state *pipe_config) 3981 { 3982 struct intel_display *display = to_intel_display(crtc); 3983 bool active; 3984 u32 tmp; 3985 3986 if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 3987 POWER_DOMAIN_PIPE(crtc->pipe))) 3988 return false; 3989 3990 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3991 3992 if ((display->platform.geminilake || display->platform.broxton) && 3993 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3994 drm_WARN_ON(display->drm, active); 3995 active = true; 3996 } 3997 3998 if (!active) 3999 goto out; 4000 4001 intel_joiner_get_config(pipe_config); 4002 intel_dsc_get_config(pipe_config); 4003 4004 /* intel_vrr_get_config() depends on .framestart_delay */ 4005 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4006 tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); 4007 4008 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4009 } else { 4010 /* no idea if this is correct */ 4011 pipe_config->framestart_delay = 1; 4012 } 4013 4014 /* 4015 * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY 4016 * readout done by intel_get_transcoder_timings(). 4017 */ 4018 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4019 DISPLAY_VER(display) >= 11) 4020 intel_get_transcoder_timings(crtc, pipe_config); 4021 4022 if (transcoder_has_vrr(pipe_config)) 4023 intel_vrr_get_config(pipe_config); 4024 4025 intel_get_pipe_src_size(crtc, pipe_config); 4026 4027 if (display->platform.haswell) { 4028 u32 tmp = intel_de_read(display, 4029 TRANSCONF(display, pipe_config->cpu_transcoder)); 4030 4031 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 4032 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4033 else 4034 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4035 } else { 4036 pipe_config->output_format = 4037 bdw_get_pipe_misc_output_format(crtc); 4038 } 4039 4040 pipe_config->sink_format = pipe_config->output_format; 4041 4042 intel_color_get_config(pipe_config); 4043 4044 tmp = intel_de_read(display, WM_LINETIME(crtc->pipe)); 4045 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4046 if (display->platform.broadwell || display->platform.haswell) 4047 pipe_config->ips_linetime = 4048 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4049 4050 if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 4051 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4052 if (DISPLAY_VER(display) >= 9) 4053 skl_scaler_get_config(pipe_config); 4054 else 4055 ilk_pfit_get_config(pipe_config); 4056 } 4057 4058 hsw_ips_get_config(pipe_config); 4059 4060 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4061 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4062 pipe_config->pixel_multiplier = 4063 intel_de_read(display, 4064 TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1; 4065 } else { 4066 pipe_config->pixel_multiplier = 1; 4067 } 4068 4069 out: 4070 intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); 4071 4072 return active; 4073 } 4074 4075 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4076 { 4077 struct intel_display *display = to_intel_display(crtc_state); 4078 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4079 4080 if (!display->modeset.funcs->get_pipe_config(crtc, crtc_state)) 4081 return false; 4082 4083 crtc_state->hw.active = true; 4084 4085 intel_crtc_readout_derived_state(crtc_state); 4086 4087 return true; 4088 } 4089 4090 int intel_dotclock_calculate(int link_freq, 4091 const struct intel_link_m_n *m_n) 4092 { 4093 /* 4094 * The calculation for the data clock -> pixel clock is: 4095 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4096 * But we want to avoid losing precision if possible, so: 4097 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4098 * 4099 * and for link freq (10kbs units) -> pixel clock it is: 4100 * link_symbol_clock = link_freq * 10 / link_symbol_size 4101 * pixel_clock = (m * link_symbol_clock) / n 4102 * or for more precision: 4103 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) 4104 */ 4105 4106 if (!m_n->link_n) 4107 return 0; 4108 4109 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), 4110 m_n->link_n * intel_dp_link_symbol_size(link_freq)); 4111 } 4112 4113 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4114 { 4115 int dotclock; 4116 4117 if (intel_crtc_has_dp_encoder(pipe_config)) 4118 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4119 &pipe_config->dp_m_n); 4120 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4121 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4122 pipe_config->pipe_bpp); 4123 else 4124 dotclock = pipe_config->port_clock; 4125 4126 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4127 !intel_crtc_has_dp_encoder(pipe_config)) 4128 dotclock *= 2; 4129 4130 if (pipe_config->pixel_multiplier) 4131 dotclock /= pipe_config->pixel_multiplier; 4132 4133 return dotclock; 4134 } 4135 4136 /* Returns the currently programmed mode of the given encoder. */ 4137 struct drm_display_mode * 4138 intel_encoder_current_mode(struct intel_encoder *encoder) 4139 { 4140 struct intel_display *display = to_intel_display(encoder); 4141 struct intel_crtc_state *crtc_state; 4142 struct drm_display_mode *mode; 4143 struct intel_crtc *crtc; 4144 enum pipe pipe; 4145 4146 if (!encoder->get_hw_state(encoder, &pipe)) 4147 return NULL; 4148 4149 crtc = intel_crtc_for_pipe(display, pipe); 4150 4151 mode = kzalloc_obj(*mode); 4152 if (!mode) 4153 return NULL; 4154 4155 crtc_state = intel_crtc_state_alloc(crtc); 4156 if (!crtc_state) { 4157 kfree(mode); 4158 return NULL; 4159 } 4160 4161 if (!intel_crtc_get_pipe_config(crtc_state)) { 4162 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4163 kfree(mode); 4164 return NULL; 4165 } 4166 4167 intel_encoder_get_config(encoder, crtc_state); 4168 4169 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4170 4171 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4172 4173 return mode; 4174 } 4175 4176 static bool encoders_cloneable(const struct intel_encoder *a, 4177 const struct intel_encoder *b) 4178 { 4179 /* masks could be asymmetric, so check both ways */ 4180 return a == b || (a->cloneable & BIT(b->type) && 4181 b->cloneable & BIT(a->type)); 4182 } 4183 4184 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4185 struct intel_crtc *crtc, 4186 struct intel_encoder *encoder) 4187 { 4188 struct intel_encoder *source_encoder; 4189 struct drm_connector *connector; 4190 struct drm_connector_state *connector_state; 4191 int i; 4192 4193 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4194 if (connector_state->crtc != &crtc->base) 4195 continue; 4196 4197 source_encoder = 4198 to_intel_encoder(connector_state->best_encoder); 4199 if (!encoders_cloneable(encoder, source_encoder)) 4200 return false; 4201 } 4202 4203 return true; 4204 } 4205 4206 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4207 { 4208 const struct drm_display_mode *pipe_mode = 4209 &crtc_state->hw.pipe_mode; 4210 int linetime_wm; 4211 4212 if (!crtc_state->hw.enable) 4213 return 0; 4214 4215 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4216 pipe_mode->crtc_clock); 4217 4218 return min(linetime_wm, 0x1ff); 4219 } 4220 4221 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4222 const struct intel_cdclk_state *cdclk_state) 4223 { 4224 const struct drm_display_mode *pipe_mode = 4225 &crtc_state->hw.pipe_mode; 4226 int linetime_wm; 4227 4228 if (!crtc_state->hw.enable) 4229 return 0; 4230 4231 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4232 intel_cdclk_logical(cdclk_state)); 4233 4234 return min(linetime_wm, 0x1ff); 4235 } 4236 4237 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4238 { 4239 struct intel_display *display = to_intel_display(crtc_state); 4240 const struct drm_display_mode *pipe_mode = 4241 &crtc_state->hw.pipe_mode; 4242 int linetime_wm; 4243 4244 if (!crtc_state->hw.enable) 4245 return 0; 4246 4247 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4248 crtc_state->pixel_rate); 4249 4250 /* Display WA #1135: BXT:ALL GLK:ALL */ 4251 if ((display->platform.geminilake || display->platform.broxton) && 4252 skl_watermark_ipc_enabled(display)) 4253 linetime_wm /= 2; 4254 4255 return min(linetime_wm, 0x1ff); 4256 } 4257 4258 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4259 struct intel_crtc *crtc) 4260 { 4261 struct intel_display *display = to_intel_display(state); 4262 struct intel_crtc_state *crtc_state = 4263 intel_atomic_get_new_crtc_state(state, crtc); 4264 const struct intel_cdclk_state *cdclk_state; 4265 4266 if (DISPLAY_VER(display) >= 9) 4267 crtc_state->linetime = skl_linetime_wm(crtc_state); 4268 else 4269 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4270 4271 if (!hsw_crtc_supports_ips(crtc)) 4272 return 0; 4273 4274 cdclk_state = intel_atomic_get_cdclk_state(state); 4275 if (IS_ERR(cdclk_state)) 4276 return PTR_ERR(cdclk_state); 4277 4278 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4279 cdclk_state); 4280 4281 return 0; 4282 } 4283 4284 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4285 struct intel_crtc *crtc) 4286 { 4287 struct intel_display *display = to_intel_display(crtc); 4288 struct intel_crtc_state *crtc_state = 4289 intel_atomic_get_new_crtc_state(state, crtc); 4290 int ret; 4291 4292 if (DISPLAY_VER(display) < 5 && !display->platform.g4x && 4293 intel_crtc_needs_modeset(crtc_state) && 4294 !crtc_state->hw.active) 4295 crtc_state->update_wm_post = true; 4296 4297 if (intel_crtc_needs_modeset(crtc_state)) { 4298 ret = intel_dpll_crtc_get_dpll(state, crtc); 4299 if (ret) 4300 return ret; 4301 } 4302 4303 ret = intel_color_check(state, crtc); 4304 if (ret) 4305 return ret; 4306 4307 ret = intel_wm_compute(state, crtc); 4308 if (ret) { 4309 drm_dbg_kms(display->drm, 4310 "[CRTC:%d:%s] watermarks are invalid\n", 4311 crtc->base.base.id, crtc->base.name); 4312 return ret; 4313 } 4314 4315 if (DISPLAY_VER(display) >= 9) { 4316 if (intel_crtc_needs_modeset(crtc_state) || 4317 intel_crtc_needs_fastset(crtc_state)) { 4318 ret = skl_update_scaler_crtc(crtc_state); 4319 if (ret) 4320 return ret; 4321 } 4322 4323 ret = intel_atomic_setup_scalers(state, crtc); 4324 if (ret) 4325 return ret; 4326 } 4327 4328 if (HAS_IPS(display)) { 4329 ret = hsw_ips_compute_config(state, crtc); 4330 if (ret) 4331 return ret; 4332 } 4333 4334 if (DISPLAY_VER(display) >= 9 || 4335 display->platform.broadwell || display->platform.haswell) { 4336 ret = hsw_compute_linetime_wm(state, crtc); 4337 if (ret) 4338 return ret; 4339 4340 } 4341 4342 ret = intel_psr2_sel_fetch_update(state, crtc); 4343 if (ret) 4344 return ret; 4345 4346 return 0; 4347 } 4348 4349 static int bpc_to_bpp(int bpc) 4350 { 4351 switch (bpc) { 4352 case 6 ... 7: 4353 return 6 * 3; 4354 case 8 ... 9: 4355 return 8 * 3; 4356 case 10 ... 11: 4357 return 10 * 3; 4358 case 12 ... 16: 4359 return 12 * 3; 4360 default: 4361 MISSING_CASE(bpc); 4362 return -EINVAL; 4363 } 4364 } 4365 4366 static int 4367 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4368 struct intel_crtc_state *crtc_state) 4369 { 4370 struct intel_display *display = to_intel_display(crtc_state); 4371 struct drm_connector *connector = conn_state->connector; 4372 const struct drm_display_info *info = &connector->display_info; 4373 int edid_bpc = info->bpc ? : 8; 4374 int target_pipe_bpp; 4375 int max_edid_bpp; 4376 4377 max_edid_bpp = bpc_to_bpp(edid_bpc); 4378 if (max_edid_bpp < 0) 4379 return max_edid_bpp; 4380 4381 target_pipe_bpp = bpc_to_bpp(conn_state->max_bpc); 4382 if (target_pipe_bpp < 0) 4383 return target_pipe_bpp; 4384 4385 /* 4386 * The maximum pipe BPP is the minimum of the max platform BPP and 4387 * the max EDID BPP. 4388 */ 4389 crtc_state->max_pipe_bpp = min(crtc_state->pipe_bpp, max_edid_bpp); 4390 4391 if (target_pipe_bpp < crtc_state->pipe_bpp) { 4392 drm_dbg_kms(display->drm, 4393 "[CONNECTOR:%d:%s] Limiting target display pipe bpp to %d " 4394 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4395 connector->base.id, connector->name, 4396 target_pipe_bpp, 3 * info->bpc, 4397 3 * conn_state->max_requested_bpc, 4398 crtc_state->pipe_bpp); 4399 4400 crtc_state->pipe_bpp = target_pipe_bpp; 4401 } 4402 4403 return 0; 4404 } 4405 4406 int intel_display_min_pipe_bpp(void) 4407 { 4408 return 6 * 3; 4409 } 4410 4411 int intel_display_max_pipe_bpp(struct intel_display *display) 4412 { 4413 if (display->platform.g4x || display->platform.valleyview || 4414 display->platform.cherryview) 4415 return 10*3; 4416 else if (DISPLAY_VER(display) >= 5) 4417 return 12*3; 4418 else 4419 return 8*3; 4420 } 4421 4422 static int 4423 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4424 struct intel_crtc *crtc) 4425 { 4426 struct intel_display *display = to_intel_display(crtc); 4427 struct intel_crtc_state *crtc_state = 4428 intel_atomic_get_new_crtc_state(state, crtc); 4429 struct drm_connector *connector; 4430 struct drm_connector_state *connector_state; 4431 int i; 4432 4433 crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display); 4434 4435 /* Clamp display bpp to connector max bpp */ 4436 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4437 int ret; 4438 4439 if (connector_state->crtc != &crtc->base) 4440 continue; 4441 4442 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4443 if (ret) 4444 return ret; 4445 } 4446 4447 return 0; 4448 } 4449 4450 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4451 { 4452 struct intel_display *display = to_intel_display(state); 4453 struct drm_connector *connector; 4454 struct drm_connector_list_iter conn_iter; 4455 unsigned int used_ports = 0; 4456 unsigned int used_mst_ports = 0; 4457 bool ret = true; 4458 4459 /* 4460 * We're going to peek into connector->state, 4461 * hence connection_mutex must be held. 4462 */ 4463 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 4464 4465 /* 4466 * Walk the connector list instead of the encoder 4467 * list to detect the problem on ddi platforms 4468 * where there's just one encoder per digital port. 4469 */ 4470 drm_connector_list_iter_begin(display->drm, &conn_iter); 4471 drm_for_each_connector_iter(connector, &conn_iter) { 4472 struct drm_connector_state *connector_state; 4473 struct intel_encoder *encoder; 4474 4475 connector_state = 4476 drm_atomic_get_new_connector_state(&state->base, 4477 connector); 4478 if (!connector_state) 4479 connector_state = connector->state; 4480 4481 if (!connector_state->best_encoder) 4482 continue; 4483 4484 encoder = to_intel_encoder(connector_state->best_encoder); 4485 4486 drm_WARN_ON(display->drm, !connector_state->crtc); 4487 4488 switch (encoder->type) { 4489 case INTEL_OUTPUT_DDI: 4490 if (drm_WARN_ON(display->drm, !HAS_DDI(display))) 4491 break; 4492 fallthrough; 4493 case INTEL_OUTPUT_DP: 4494 case INTEL_OUTPUT_HDMI: 4495 case INTEL_OUTPUT_EDP: 4496 /* the same port mustn't appear more than once */ 4497 if (used_ports & BIT(encoder->port)) 4498 ret = false; 4499 4500 used_ports |= BIT(encoder->port); 4501 break; 4502 case INTEL_OUTPUT_DP_MST: 4503 used_mst_ports |= 4504 1 << encoder->port; 4505 break; 4506 default: 4507 break; 4508 } 4509 } 4510 drm_connector_list_iter_end(&conn_iter); 4511 4512 /* can't mix MST and SST/HDMI on the same port */ 4513 if (used_ports & used_mst_ports) 4514 return false; 4515 4516 return ret; 4517 } 4518 4519 static void 4520 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4521 struct intel_crtc *crtc) 4522 { 4523 struct intel_crtc_state *crtc_state = 4524 intel_atomic_get_new_crtc_state(state, crtc); 4525 4526 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4527 4528 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4529 crtc_state->uapi.degamma_lut); 4530 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4531 crtc_state->uapi.gamma_lut); 4532 drm_property_replace_blob(&crtc_state->hw.ctm, 4533 crtc_state->uapi.ctm); 4534 crtc_state->hw.background_color = 4535 intel_color_background_color_drm_to_hw(crtc_state->uapi.background_color); 4536 } 4537 4538 static void 4539 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4540 struct intel_crtc *crtc) 4541 { 4542 struct intel_crtc_state *crtc_state = 4543 intel_atomic_get_new_crtc_state(state, crtc); 4544 4545 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4546 4547 crtc_state->hw.enable = crtc_state->uapi.enable; 4548 crtc_state->hw.active = crtc_state->uapi.active; 4549 drm_mode_copy(&crtc_state->hw.mode, 4550 &crtc_state->uapi.mode); 4551 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4552 &crtc_state->uapi.adjusted_mode); 4553 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4554 crtc_state->hw.sharpness_strength = crtc_state->uapi.sharpness_strength; 4555 4556 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4557 } 4558 4559 static void 4560 copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4561 struct intel_crtc *secondary_crtc) 4562 { 4563 struct intel_crtc_state *secondary_crtc_state = 4564 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4565 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4566 const struct intel_crtc_state *primary_crtc_state = 4567 intel_atomic_get_new_crtc_state(state, primary_crtc); 4568 4569 drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut, 4570 primary_crtc_state->hw.degamma_lut); 4571 drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut, 4572 primary_crtc_state->hw.gamma_lut); 4573 drm_property_replace_blob(&secondary_crtc_state->hw.ctm, 4574 primary_crtc_state->hw.ctm); 4575 secondary_crtc_state->hw.background_color = primary_crtc_state->hw.background_color; 4576 4577 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed; 4578 } 4579 4580 static int 4581 copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, 4582 struct intel_crtc *secondary_crtc) 4583 { 4584 struct intel_crtc_state *secondary_crtc_state = 4585 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4586 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4587 const struct intel_crtc_state *primary_crtc_state = 4588 intel_atomic_get_new_crtc_state(state, primary_crtc); 4589 struct intel_crtc_state *saved_state; 4590 4591 WARN_ON(primary_crtc_state->joiner_pipes != 4592 secondary_crtc_state->joiner_pipes); 4593 4594 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4595 if (!saved_state) 4596 return -ENOMEM; 4597 4598 /* preserve some things from the slave's original crtc state */ 4599 saved_state->uapi = secondary_crtc_state->uapi; 4600 saved_state->scaler_state = secondary_crtc_state->scaler_state; 4601 saved_state->intel_dpll = secondary_crtc_state->intel_dpll; 4602 saved_state->crc_enabled = secondary_crtc_state->crc_enabled; 4603 4604 intel_crtc_free_hw_state(secondary_crtc_state); 4605 if (secondary_crtc_state->dp_tunnel_ref.tunnel) 4606 drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref); 4607 memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state)); 4608 kfree(saved_state); 4609 4610 /* Re-init hw state */ 4611 memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw)); 4612 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable; 4613 secondary_crtc_state->hw.active = primary_crtc_state->hw.active; 4614 drm_mode_copy(&secondary_crtc_state->hw.mode, 4615 &primary_crtc_state->hw.mode); 4616 drm_mode_copy(&secondary_crtc_state->hw.pipe_mode, 4617 &primary_crtc_state->hw.pipe_mode); 4618 drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, 4619 &primary_crtc_state->hw.adjusted_mode); 4620 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; 4621 secondary_crtc_state->hw.sharpness_strength = primary_crtc_state->hw.sharpness_strength; 4622 4623 if (primary_crtc_state->dp_tunnel_ref.tunnel) 4624 drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, 4625 &secondary_crtc_state->dp_tunnel_ref); 4626 4627 copy_joiner_crtc_state_nomodeset(state, secondary_crtc); 4628 4629 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed; 4630 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed; 4631 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed; 4632 4633 WARN_ON(primary_crtc_state->joiner_pipes != 4634 secondary_crtc_state->joiner_pipes); 4635 4636 return 0; 4637 } 4638 4639 static int 4640 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4641 struct intel_crtc *crtc) 4642 { 4643 struct intel_display *display = to_intel_display(state); 4644 struct intel_crtc_state *crtc_state = 4645 intel_atomic_get_new_crtc_state(state, crtc); 4646 struct intel_crtc_state *saved_state; 4647 int err; 4648 4649 saved_state = intel_crtc_state_alloc(crtc); 4650 if (!saved_state) 4651 return -ENOMEM; 4652 4653 /* free the old crtc_state->hw members */ 4654 intel_crtc_free_hw_state(crtc_state); 4655 4656 err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4657 if (err) { 4658 kfree(saved_state); 4659 4660 return err; 4661 } 4662 4663 /* FIXME: before the switch to atomic started, a new pipe_config was 4664 * kzalloc'd. Code that depends on any field being zero should be 4665 * fixed, so that the crtc_state can be safely duplicated. For now, 4666 * only fields that are know to not cause problems are preserved. */ 4667 4668 saved_state->uapi = crtc_state->uapi; 4669 saved_state->inherited = crtc_state->inherited; 4670 saved_state->scaler_state = crtc_state->scaler_state; 4671 saved_state->intel_dpll = crtc_state->intel_dpll; 4672 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4673 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4674 sizeof(saved_state->icl_port_dplls)); 4675 saved_state->crc_enabled = crtc_state->crc_enabled; 4676 if (display->platform.g4x || 4677 display->platform.valleyview || display->platform.cherryview) 4678 saved_state->wm = crtc_state->wm; 4679 4680 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4681 kfree(saved_state); 4682 4683 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4684 4685 return 0; 4686 } 4687 4688 static int 4689 intel_modeset_pipe_config(struct intel_atomic_state *state, 4690 struct intel_crtc *crtc, 4691 const struct intel_link_bw_limits *limits) 4692 { 4693 struct intel_display *display = to_intel_display(crtc); 4694 struct intel_crtc_state *crtc_state = 4695 intel_atomic_get_new_crtc_state(state, crtc); 4696 struct drm_connector *connector; 4697 struct drm_connector_state *connector_state; 4698 int pipe_src_w, pipe_src_h; 4699 int base_bpp, ret, i; 4700 4701 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4702 4703 crtc_state->framestart_delay = 1; 4704 4705 /* 4706 * Sanitize sync polarity flags based on requested ones. If neither 4707 * positive or negative polarity is requested, treat this as meaning 4708 * negative polarity. 4709 */ 4710 if (!(crtc_state->hw.adjusted_mode.flags & 4711 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4712 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4713 4714 if (!(crtc_state->hw.adjusted_mode.flags & 4715 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4716 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4717 4718 ret = compute_baseline_pipe_bpp(state, crtc); 4719 if (ret) 4720 return ret; 4721 4722 crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe); 4723 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; 4724 4725 if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) { 4726 drm_dbg_kms(display->drm, 4727 "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n", 4728 crtc->base.base.id, crtc->base.name, 4729 FXP_Q4_ARGS(crtc_state->max_link_bpp_x16)); 4730 crtc_state->bw_constrained = true; 4731 } 4732 4733 base_bpp = crtc_state->pipe_bpp; 4734 4735 /* 4736 * Determine the real pipe dimensions. Note that stereo modes can 4737 * increase the actual pipe size due to the frame doubling and 4738 * insertion of additional space for blanks between the frame. This 4739 * is stored in the crtc timings. We use the requested mode to do this 4740 * computation to clearly distinguish it from the adjusted mode, which 4741 * can be changed by the connectors in the below retry loop. 4742 */ 4743 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4744 &pipe_src_w, &pipe_src_h); 4745 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4746 pipe_src_w, pipe_src_h); 4747 4748 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4749 struct intel_encoder *encoder = 4750 to_intel_encoder(connector_state->best_encoder); 4751 4752 if (connector_state->crtc != &crtc->base) 4753 continue; 4754 4755 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4756 drm_dbg_kms(display->drm, 4757 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4758 encoder->base.base.id, encoder->base.name); 4759 return -EINVAL; 4760 } 4761 4762 /* 4763 * Determine output_types before calling the .compute_config() 4764 * hooks so that the hooks can use this information safely. 4765 */ 4766 if (encoder->compute_output_type) 4767 crtc_state->output_types |= 4768 BIT(encoder->compute_output_type(encoder, crtc_state, 4769 connector_state)); 4770 else 4771 crtc_state->output_types |= BIT(encoder->type); 4772 } 4773 4774 /* Ensure the port clock defaults are reset when retrying. */ 4775 crtc_state->port_clock = 0; 4776 crtc_state->pixel_multiplier = 1; 4777 4778 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4779 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4780 CRTC_STEREO_DOUBLE); 4781 4782 /* Pass our mode to the connectors and the CRTC to give them a chance to 4783 * adjust it according to limitations or connector properties, and also 4784 * a chance to reject the mode entirely. 4785 */ 4786 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4787 struct intel_encoder *encoder = 4788 to_intel_encoder(connector_state->best_encoder); 4789 4790 if (connector_state->crtc != &crtc->base) 4791 continue; 4792 4793 ret = encoder->compute_config(state, encoder, crtc_state, 4794 connector_state); 4795 if (ret == -EDEADLK) 4796 return ret; 4797 if (ret < 0) { 4798 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n", 4799 encoder->base.base.id, encoder->base.name, ret); 4800 return ret; 4801 } 4802 } 4803 4804 /* Set default port clock if not overwritten by the encoder. Needs to be 4805 * done afterwards in case the encoder adjusts the mode. */ 4806 if (!crtc_state->port_clock) 4807 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4808 * crtc_state->pixel_multiplier; 4809 4810 ret = intel_crtc_compute_config(state, crtc); 4811 if (ret == -EDEADLK) 4812 return ret; 4813 if (ret < 0) { 4814 drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n", 4815 crtc->base.base.id, crtc->base.name, ret); 4816 return ret; 4817 } 4818 4819 /* Dithering seems to not pass-through bits correctly when it should, so 4820 * only enable it on 6bpc panels and when its not a compliance 4821 * test requesting 6bpc video pattern. 4822 */ 4823 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4824 !crtc_state->dither_force_disable; 4825 drm_dbg_kms(display->drm, 4826 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4827 crtc->base.base.id, crtc->base.name, 4828 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4829 4830 return 0; 4831 } 4832 4833 static int 4834 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4835 struct intel_crtc *crtc) 4836 { 4837 struct intel_crtc_state *crtc_state = 4838 intel_atomic_get_new_crtc_state(state, crtc); 4839 struct drm_connector_state *conn_state; 4840 struct drm_connector *connector; 4841 int i; 4842 4843 for_each_new_connector_in_state(&state->base, connector, 4844 conn_state, i) { 4845 struct intel_encoder *encoder = 4846 to_intel_encoder(conn_state->best_encoder); 4847 int ret; 4848 4849 if (conn_state->crtc != &crtc->base || 4850 !encoder->compute_config_late) 4851 continue; 4852 4853 ret = encoder->compute_config_late(state, encoder, crtc_state, 4854 conn_state); 4855 if (ret) 4856 return ret; 4857 } 4858 4859 return 0; 4860 } 4861 4862 bool intel_fuzzy_clock_check(int clock1, int clock2) 4863 { 4864 int diff; 4865 4866 if (clock1 == clock2) 4867 return true; 4868 4869 if (!clock1 || !clock2) 4870 return false; 4871 4872 diff = abs(clock1 - clock2); 4873 4874 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4875 return true; 4876 4877 return false; 4878 } 4879 4880 static bool 4881 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4882 const struct intel_link_m_n *m2_n2) 4883 { 4884 return m_n->tu == m2_n2->tu && 4885 m_n->data_m == m2_n2->data_m && 4886 m_n->data_n == m2_n2->data_n && 4887 m_n->link_m == m2_n2->link_m && 4888 m_n->link_n == m2_n2->link_n; 4889 } 4890 4891 static bool 4892 intel_compare_infoframe(const union hdmi_infoframe *a, 4893 const union hdmi_infoframe *b) 4894 { 4895 return memcmp(a, b, sizeof(*a)) == 0; 4896 } 4897 4898 static bool 4899 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4900 const struct drm_dp_vsc_sdp *b) 4901 { 4902 return a->pixelformat == b->pixelformat && 4903 a->colorimetry == b->colorimetry && 4904 a->bpc == b->bpc && 4905 a->dynamic_range == b->dynamic_range && 4906 a->content_type == b->content_type; 4907 } 4908 4909 static bool 4910 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, 4911 const struct drm_dp_as_sdp *b) 4912 { 4913 return a->sdp_type == b->sdp_type && 4914 a->revision == b->revision && 4915 a->length == b->length && 4916 a->vtotal == b->vtotal && 4917 a->target_rr == b->target_rr && 4918 a->duration_incr_ms == b->duration_incr_ms && 4919 a->duration_decr_ms == b->duration_decr_ms && 4920 a->target_rr_divider == b->target_rr_divider && 4921 a->mode == b->mode && 4922 a->coasting_vtotal == b->coasting_vtotal; 4923 } 4924 4925 static bool 4926 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4927 { 4928 return memcmp(a, b, len) == 0; 4929 } 4930 4931 static void __printf(5, 6) 4932 pipe_config_mismatch(struct drm_printer *p, bool fastset, 4933 const struct intel_crtc *crtc, 4934 const char *name, const char *format, ...) 4935 { 4936 struct va_format vaf; 4937 va_list args; 4938 4939 va_start(args, format); 4940 vaf.fmt = format; 4941 vaf.va = &args; 4942 4943 if (fastset) 4944 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4945 crtc->base.base.id, crtc->base.name, name, &vaf); 4946 else 4947 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n", 4948 crtc->base.base.id, crtc->base.name, name, &vaf); 4949 4950 va_end(args); 4951 } 4952 4953 static void 4954 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, 4955 const struct intel_crtc *crtc, 4956 const char *name, 4957 const union hdmi_infoframe *a, 4958 const union hdmi_infoframe *b) 4959 { 4960 struct intel_display *display = to_intel_display(crtc); 4961 const char *loglevel; 4962 4963 if (fastset) { 4964 if (!drm_debug_enabled(DRM_UT_KMS)) 4965 return; 4966 4967 loglevel = KERN_DEBUG; 4968 } else { 4969 loglevel = KERN_ERR; 4970 } 4971 4972 pipe_config_mismatch(p, fastset, crtc, name, "infoframe"); 4973 4974 drm_printf(p, "expected:\n"); 4975 hdmi_infoframe_log(loglevel, display->drm->dev, a); 4976 drm_printf(p, "found:\n"); 4977 hdmi_infoframe_log(loglevel, display->drm->dev, b); 4978 } 4979 4980 static void 4981 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset, 4982 const struct intel_crtc *crtc, 4983 const char *name, 4984 const struct drm_dp_vsc_sdp *a, 4985 const struct drm_dp_vsc_sdp *b) 4986 { 4987 pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp"); 4988 4989 drm_printf(p, "expected:\n"); 4990 drm_dp_vsc_sdp_log(p, a); 4991 drm_printf(p, "found:\n"); 4992 drm_dp_vsc_sdp_log(p, b); 4993 } 4994 4995 static void 4996 pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset, 4997 const struct intel_crtc *crtc, 4998 const char *name, 4999 const struct drm_dp_as_sdp *a, 5000 const struct drm_dp_as_sdp *b) 5001 { 5002 pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp"); 5003 5004 drm_printf(p, "expected:\n"); 5005 drm_dp_as_sdp_log(p, a); 5006 drm_printf(p, "found:\n"); 5007 drm_dp_as_sdp_log(p, b); 5008 } 5009 5010 /* Returns the length up to and including the last differing byte */ 5011 static size_t 5012 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 5013 { 5014 int i; 5015 5016 for (i = len - 1; i >= 0; i--) { 5017 if (a[i] != b[i]) 5018 return i + 1; 5019 } 5020 5021 return 0; 5022 } 5023 5024 static void 5025 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset, 5026 const struct intel_crtc *crtc, 5027 const char *name, 5028 const u8 *a, const u8 *b, size_t len) 5029 { 5030 pipe_config_mismatch(p, fastset, crtc, name, "buffer"); 5031 5032 /* only dump up to the last difference */ 5033 len = memcmp_diff_len(a, b, len); 5034 5035 drm_print_hex_dump(p, "expected: ", a, len); 5036 drm_print_hex_dump(p, "found: ", b, len); 5037 } 5038 5039 static void 5040 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, 5041 const struct intel_crtc *crtc, 5042 const char *name, 5043 const struct intel_dpll_hw_state *a, 5044 const struct intel_dpll_hw_state *b) 5045 { 5046 struct intel_display *display = to_intel_display(crtc); 5047 5048 pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */ 5049 5050 drm_printf(p, "expected:\n"); 5051 intel_dpll_dump_hw_state(display, p, a); 5052 drm_printf(p, "found:\n"); 5053 intel_dpll_dump_hw_state(display, p, b); 5054 } 5055 5056 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) 5057 { 5058 struct intel_display *display = to_intel_display(old_crtc_state); 5059 5060 /* 5061 * Allow fastboot to fix up vblank delay (handled via LRR 5062 * codepaths), a bit dodgy as the registers aren't 5063 * double buffered but seems to be working more or less... 5064 * 5065 * Also allow this when the VRR timing generator is always on, 5066 * and optimized guardband is used. In such cases, 5067 * vblank delay may vary even without inherited state, but it's 5068 * still safe as VRR guardband is still same. 5069 */ 5070 return HAS_LRR(display) && 5071 (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) && 5072 !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI); 5073 } 5074 5075 bool 5076 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5077 const struct intel_crtc_state *pipe_config, 5078 bool fastset) 5079 { 5080 struct intel_display *display = to_intel_display(current_config); 5081 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5082 struct drm_printer p; 5083 u32 exclude_infoframes = 0; 5084 bool ret = true; 5085 5086 if (fastset) 5087 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 5088 else 5089 p = drm_err_printer(display->drm, NULL); 5090 5091 #define PIPE_CONF_CHECK_X(name) do { \ 5092 if (current_config->name != pipe_config->name) { \ 5093 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5094 __stringify(name) " is bool"); \ 5095 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5096 "(expected 0x%08x, found 0x%08x)", \ 5097 current_config->name, \ 5098 pipe_config->name); \ 5099 ret = false; \ 5100 } \ 5101 } while (0) 5102 5103 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5104 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5105 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5106 __stringify(name) " is bool"); \ 5107 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5108 "(expected 0x%08x, found 0x%08x)", \ 5109 current_config->name & (mask), \ 5110 pipe_config->name & (mask)); \ 5111 ret = false; \ 5112 } \ 5113 } while (0) 5114 5115 #define PIPE_CONF_CHECK_I(name) do { \ 5116 if (current_config->name != pipe_config->name) { \ 5117 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5118 __stringify(name) " is bool"); \ 5119 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5120 "(expected %i, found %i)", \ 5121 current_config->name, \ 5122 pipe_config->name); \ 5123 ret = false; \ 5124 } \ 5125 } while (0) 5126 5127 #define PIPE_CONF_CHECK_LLI(name) do { \ 5128 if (current_config->name != pipe_config->name) { \ 5129 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5130 "(expected %lli, found %lli)", \ 5131 current_config->name, \ 5132 pipe_config->name); \ 5133 ret = false; \ 5134 } \ 5135 } while (0) 5136 5137 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5138 if (current_config->name != pipe_config->name) { \ 5139 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ 5140 __stringify(name) " is not bool"); \ 5141 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5142 "(expected %s, found %s)", \ 5143 str_yes_no(current_config->name), \ 5144 str_yes_no(pipe_config->name)); \ 5145 ret = false; \ 5146 } \ 5147 } while (0) 5148 5149 #define PIPE_CONF_CHECK_P(name) do { \ 5150 if (current_config->name != pipe_config->name) { \ 5151 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5152 "(expected %p, found %p)", \ 5153 current_config->name, \ 5154 pipe_config->name); \ 5155 ret = false; \ 5156 } \ 5157 } while (0) 5158 5159 #define PIPE_CONF_CHECK_M_N(name) do { \ 5160 if (!intel_compare_link_m_n(¤t_config->name, \ 5161 &pipe_config->name)) { \ 5162 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5163 "(expected tu %i data %i/%i link %i/%i, " \ 5164 "found tu %i, data %i/%i link %i/%i)", \ 5165 current_config->name.tu, \ 5166 current_config->name.data_m, \ 5167 current_config->name.data_n, \ 5168 current_config->name.link_m, \ 5169 current_config->name.link_n, \ 5170 pipe_config->name.tu, \ 5171 pipe_config->name.data_m, \ 5172 pipe_config->name.data_n, \ 5173 pipe_config->name.link_m, \ 5174 pipe_config->name.link_n); \ 5175 ret = false; \ 5176 } \ 5177 } while (0) 5178 5179 #define PIPE_CONF_CHECK_PLL(name) do { \ 5180 if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \ 5181 &pipe_config->name)) { \ 5182 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5183 ¤t_config->name, \ 5184 &pipe_config->name); \ 5185 ret = false; \ 5186 } \ 5187 } while (0) 5188 5189 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5190 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5191 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5192 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5193 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5194 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5195 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5196 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5197 if (!fastset || !allow_vblank_delay_fastset(current_config)) \ 5198 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5199 if (!fastset || !pipe_config->update_lrr) { \ 5200 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5201 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5202 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5203 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5204 } \ 5205 } while (0) 5206 5207 #define PIPE_CONF_CHECK_RECT(name) do { \ 5208 PIPE_CONF_CHECK_I(name.x1); \ 5209 PIPE_CONF_CHECK_I(name.x2); \ 5210 PIPE_CONF_CHECK_I(name.y1); \ 5211 PIPE_CONF_CHECK_I(name.y2); \ 5212 } while (0) 5213 5214 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5215 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5216 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5217 "(%x) (expected %i, found %i)", \ 5218 (mask), \ 5219 current_config->name & (mask), \ 5220 pipe_config->name & (mask)); \ 5221 ret = false; \ 5222 } \ 5223 } while (0) 5224 5225 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5226 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5227 &pipe_config->infoframes.name)) { \ 5228 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \ 5229 ¤t_config->infoframes.name, \ 5230 &pipe_config->infoframes.name); \ 5231 ret = false; \ 5232 } \ 5233 } while (0) 5234 5235 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5236 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5237 &pipe_config->infoframes.name)) { \ 5238 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5239 ¤t_config->infoframes.name, \ 5240 &pipe_config->infoframes.name); \ 5241 ret = false; \ 5242 } \ 5243 } while (0) 5244 5245 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ 5246 if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \ 5247 &pipe_config->infoframes.name)) { \ 5248 pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5249 ¤t_config->infoframes.name, \ 5250 &pipe_config->infoframes.name); \ 5251 ret = false; \ 5252 } \ 5253 } while (0) 5254 5255 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5256 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5257 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5258 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5259 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \ 5260 current_config->name, \ 5261 pipe_config->name, \ 5262 (len)); \ 5263 ret = false; \ 5264 } \ 5265 } while (0) 5266 5267 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5268 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5269 !intel_color_lut_equal(current_config, \ 5270 current_config->lut, pipe_config->lut, \ 5271 is_pre_csc_lut)) { \ 5272 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \ 5273 "hw_state doesn't match sw_state"); \ 5274 ret = false; \ 5275 } \ 5276 } while (0) 5277 5278 #define PIPE_CONF_CHECK_CSC(name) do { \ 5279 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5280 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5281 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5282 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5283 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5284 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5285 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5286 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5287 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5288 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5289 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5290 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5291 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5292 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5293 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5294 } while (0) 5295 5296 #define PIPE_CONF_QUIRK(quirk) \ 5297 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5298 5299 PIPE_CONF_CHECK_BOOL(hw.enable); 5300 PIPE_CONF_CHECK_BOOL(hw.active); 5301 5302 PIPE_CONF_CHECK_I(cpu_transcoder); 5303 PIPE_CONF_CHECK_I(mst_master_transcoder); 5304 5305 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5306 PIPE_CONF_CHECK_I(fdi_lanes); 5307 PIPE_CONF_CHECK_M_N(fdi_m_n); 5308 5309 PIPE_CONF_CHECK_I(lane_count); 5310 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5311 5312 PIPE_CONF_CHECK_I(min_hblank); 5313 5314 if (HAS_DOUBLE_BUFFERED_M_N(display)) { 5315 if (!fastset || !pipe_config->update_m_n) 5316 PIPE_CONF_CHECK_M_N(dp_m_n); 5317 } else { 5318 PIPE_CONF_CHECK_M_N(dp_m_n); 5319 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5320 } 5321 5322 PIPE_CONF_CHECK_X(output_types); 5323 5324 PIPE_CONF_CHECK_I(framestart_delay); 5325 PIPE_CONF_CHECK_I(msa_timing_delay); 5326 5327 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5328 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5329 5330 PIPE_CONF_CHECK_I(pixel_multiplier); 5331 5332 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5333 DRM_MODE_FLAG_INTERLACE); 5334 5335 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5336 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5337 DRM_MODE_FLAG_PHSYNC); 5338 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5339 DRM_MODE_FLAG_NHSYNC); 5340 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5341 DRM_MODE_FLAG_PVSYNC); 5342 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5343 DRM_MODE_FLAG_NVSYNC); 5344 } 5345 5346 PIPE_CONF_CHECK_I(output_format); 5347 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5348 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || 5349 display->platform.valleyview || display->platform.cherryview) 5350 PIPE_CONF_CHECK_BOOL(limited_color_range); 5351 5352 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5353 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5354 PIPE_CONF_CHECK_BOOL(has_infoframe); 5355 PIPE_CONF_CHECK_BOOL(enhanced_framing); 5356 PIPE_CONF_CHECK_BOOL(fec_enable); 5357 5358 if (!fastset) { 5359 PIPE_CONF_CHECK_BOOL(has_audio); 5360 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5361 } 5362 5363 PIPE_CONF_CHECK_X(gmch_pfit.control); 5364 /* pfit ratios are autocomputed by the hw on gen4+ */ 5365 if (DISPLAY_VER(display) < 4) 5366 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5367 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5368 5369 /* 5370 * Changing the EDP transcoder input mux 5371 * (A_ONOFF vs. A_ON) requires a full modeset. 5372 */ 5373 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5374 5375 if (!fastset) { 5376 PIPE_CONF_CHECK_RECT(pipe_src); 5377 5378 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5379 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5380 PIPE_CONF_CHECK_BOOL(pch_pfit.casf.enable); 5381 PIPE_CONF_CHECK_I(pch_pfit.casf.win_size); 5382 PIPE_CONF_CHECK_I(pch_pfit.casf.strength); 5383 5384 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5385 PIPE_CONF_CHECK_I(pixel_rate); 5386 5387 PIPE_CONF_CHECK_X(gamma_mode); 5388 if (display->platform.cherryview) 5389 PIPE_CONF_CHECK_X(cgm_mode); 5390 else 5391 PIPE_CONF_CHECK_X(csc_mode); 5392 PIPE_CONF_CHECK_BOOL(gamma_enable); 5393 5394 PIPE_CONF_CHECK_X(hw.background_color); 5395 PIPE_CONF_CHECK_BOOL(csc_enable); 5396 PIPE_CONF_CHECK_BOOL(wgc_enable); 5397 5398 PIPE_CONF_CHECK_I(linetime); 5399 PIPE_CONF_CHECK_I(ips_linetime); 5400 5401 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5402 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5403 5404 PIPE_CONF_CHECK_CSC(csc); 5405 PIPE_CONF_CHECK_CSC(output_csc); 5406 } 5407 5408 PIPE_CONF_CHECK_BOOL(double_wide); 5409 5410 if (display->dpll.mgr) 5411 PIPE_CONF_CHECK_P(intel_dpll); 5412 5413 /* FIXME convert everything over the dpll_mgr */ 5414 if (display->dpll.mgr || HAS_GMCH(display)) 5415 PIPE_CONF_CHECK_PLL(dpll_hw_state); 5416 5417 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5418 PIPE_CONF_CHECK_X(dsi_pll.div); 5419 5420 if (display->platform.g4x || DISPLAY_VER(display) >= 5) 5421 PIPE_CONF_CHECK_I(pipe_bpp); 5422 5423 if (!fastset || !pipe_config->update_m_n) { 5424 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5425 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5426 } 5427 PIPE_CONF_CHECK_I(port_clock); 5428 5429 PIPE_CONF_CHECK_I(min_voltage_level); 5430 5431 if (current_config->has_psr || pipe_config->has_psr) 5432 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 5433 5434 if (current_config->vrr.enable || pipe_config->vrr.enable) 5435 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 5436 5437 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes); 5438 PIPE_CONF_CHECK_X(infoframes.gcp); 5439 PIPE_CONF_CHECK_INFOFRAME(avi); 5440 PIPE_CONF_CHECK_INFOFRAME(spd); 5441 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5442 if (!fastset) { 5443 PIPE_CONF_CHECK_INFOFRAME(drm); 5444 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); 5445 } 5446 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5447 5448 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5449 PIPE_CONF_CHECK_I(master_transcoder); 5450 PIPE_CONF_CHECK_X(joiner_pipes); 5451 5452 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); 5453 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); 5454 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422); 5455 PIPE_CONF_CHECK_BOOL(dsc.config.native_422); 5456 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); 5457 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable); 5458 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth); 5459 PIPE_CONF_CHECK_I(dsc.config.bits_per_component); 5460 PIPE_CONF_CHECK_I(dsc.config.pic_width); 5461 PIPE_CONF_CHECK_I(dsc.config.pic_height); 5462 PIPE_CONF_CHECK_I(dsc.config.slice_width); 5463 PIPE_CONF_CHECK_I(dsc.config.slice_height); 5464 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay); 5465 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay); 5466 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval); 5467 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval); 5468 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value); 5469 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset); 5470 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp); 5471 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp); 5472 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset); 5473 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset); 5474 PIPE_CONF_CHECK_I(dsc.config.initial_offset); 5475 PIPE_CONF_CHECK_I(dsc.config.final_offset); 5476 PIPE_CONF_CHECK_I(dsc.config.rc_model_size); 5477 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0); 5478 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1); 5479 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size); 5480 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset); 5481 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); 5482 5483 PIPE_CONF_CHECK_BOOL(dsc.compression_enable); 5484 PIPE_CONF_CHECK_I(dsc.slice_config.streams_per_pipe); 5485 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); 5486 5487 PIPE_CONF_CHECK_BOOL(splitter.enable); 5488 PIPE_CONF_CHECK_I(splitter.link_count); 5489 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5490 5491 if (!fastset) { 5492 PIPE_CONF_CHECK_BOOL(vrr.enable); 5493 PIPE_CONF_CHECK_I(vrr.vmin); 5494 PIPE_CONF_CHECK_I(vrr.vmax); 5495 PIPE_CONF_CHECK_I(vrr.flipline); 5496 PIPE_CONF_CHECK_I(vrr.vsync_start); 5497 PIPE_CONF_CHECK_I(vrr.vsync_end); 5498 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); 5499 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); 5500 PIPE_CONF_CHECK_BOOL(cmrr.enable); 5501 PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); 5502 PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); 5503 PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); 5504 PIPE_CONF_CHECK_I(vrr.dc_balance.slope); 5505 PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); 5506 PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); 5507 PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); 5508 } 5509 5510 if (!fastset || intel_vrr_always_use_vrr_tg(display)) { 5511 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5512 PIPE_CONF_CHECK_I(vrr.guardband); 5513 } 5514 5515 PIPE_CONF_CHECK_I(set_context_latency); 5516 5517 #undef PIPE_CONF_CHECK_X 5518 #undef PIPE_CONF_CHECK_I 5519 #undef PIPE_CONF_CHECK_LLI 5520 #undef PIPE_CONF_CHECK_BOOL 5521 #undef PIPE_CONF_CHECK_P 5522 #undef PIPE_CONF_CHECK_FLAGS 5523 #undef PIPE_CONF_CHECK_COLOR_LUT 5524 #undef PIPE_CONF_CHECK_TIMINGS 5525 #undef PIPE_CONF_CHECK_RECT 5526 #undef PIPE_CONF_QUIRK 5527 5528 return ret; 5529 } 5530 5531 static void 5532 intel_verify_planes(struct intel_atomic_state *state) 5533 { 5534 struct intel_plane *plane; 5535 const struct intel_plane_state *plane_state; 5536 int i; 5537 5538 for_each_new_intel_plane_in_state(state, plane, 5539 plane_state, i) 5540 assert_plane(plane, plane_state->is_y_plane || 5541 plane_state->uapi.visible); 5542 } 5543 5544 static int intel_modeset_pipe(struct intel_atomic_state *state, 5545 struct intel_crtc_state *crtc_state, 5546 const char *reason) 5547 { 5548 struct intel_display *display = to_intel_display(state); 5549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5550 int ret; 5551 5552 drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5553 crtc->base.base.id, crtc->base.name, reason); 5554 5555 ret = drm_atomic_add_affected_connectors(&state->base, 5556 &crtc->base); 5557 if (ret) 5558 return ret; 5559 5560 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc); 5561 if (ret) 5562 return ret; 5563 5564 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5565 if (ret) 5566 return ret; 5567 5568 ret = intel_plane_add_affected(state, crtc); 5569 if (ret) 5570 return ret; 5571 5572 crtc_state->uapi.mode_changed = true; 5573 5574 return 0; 5575 } 5576 5577 /** 5578 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes 5579 * @state: intel atomic state 5580 * @reason: the reason for the full modeset 5581 * @mask: mask of pipes to modeset 5582 * 5583 * Add pipes in @mask to @state and force a full modeset on the enabled ones 5584 * due to the description in @reason. 5585 * This function can be called only before new plane states are computed. 5586 * 5587 * Returns 0 in case of success, negative error code otherwise. 5588 */ 5589 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 5590 const char *reason, u8 mask) 5591 { 5592 struct intel_display *display = to_intel_display(state); 5593 struct intel_crtc *crtc; 5594 5595 for_each_intel_crtc_in_pipe_mask(display, crtc, mask) { 5596 struct intel_crtc_state *crtc_state; 5597 int ret; 5598 5599 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5600 if (IS_ERR(crtc_state)) 5601 return PTR_ERR(crtc_state); 5602 5603 if (!crtc_state->hw.enable || 5604 intel_crtc_needs_modeset(crtc_state)) 5605 continue; 5606 5607 ret = intel_modeset_pipe(state, crtc_state, reason); 5608 if (ret) 5609 return ret; 5610 } 5611 5612 return 0; 5613 } 5614 5615 static void 5616 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) 5617 { 5618 crtc_state->uapi.mode_changed = true; 5619 5620 crtc_state->update_pipe = false; 5621 crtc_state->update_m_n = false; 5622 crtc_state->update_lrr = false; 5623 } 5624 5625 /** 5626 * intel_modeset_all_pipes_late - force a full modeset on all pipes 5627 * @state: intel atomic state 5628 * @reason: the reason for the full modeset 5629 * 5630 * Add all pipes to @state and force a full modeset on the active ones due to 5631 * the description in @reason. 5632 * This function can be called only after new plane states are computed already. 5633 * 5634 * Returns 0 in case of success, negative error code otherwise. 5635 */ 5636 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 5637 const char *reason) 5638 { 5639 struct intel_display *display = to_intel_display(state); 5640 struct intel_crtc *crtc; 5641 5642 for_each_intel_crtc(display, crtc) { 5643 struct intel_crtc_state *crtc_state; 5644 int ret; 5645 5646 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5647 if (IS_ERR(crtc_state)) 5648 return PTR_ERR(crtc_state); 5649 5650 if (!crtc_state->hw.active || 5651 intel_crtc_needs_modeset(crtc_state)) 5652 continue; 5653 5654 ret = intel_modeset_pipe(state, crtc_state, reason); 5655 if (ret) 5656 return ret; 5657 5658 intel_crtc_flag_modeset(crtc_state); 5659 5660 crtc_state->update_planes |= crtc_state->active_planes; 5661 crtc_state->async_flip_planes = 0; 5662 crtc_state->do_async_flip = false; 5663 } 5664 5665 return 0; 5666 } 5667 5668 int intel_modeset_commit_pipes_for_atomic_state(struct intel_atomic_state *state, 5669 u8 pipe_mask, 5670 struct drm_modeset_acquire_ctx *ctx) 5671 { 5672 struct intel_display *display = to_intel_display(state); 5673 struct intel_crtc *crtc; 5674 5675 state->base.acquire_ctx = ctx; 5676 state->internal = true; 5677 5678 for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) { 5679 struct intel_crtc_state *crtc_state = 5680 intel_atomic_get_crtc_state(&state->base, crtc); 5681 5682 if (IS_ERR(crtc_state)) 5683 return PTR_ERR(crtc_state); 5684 5685 crtc_state->uapi.connectors_changed = true; 5686 } 5687 5688 return drm_atomic_commit(&state->base); 5689 } 5690 5691 int intel_modeset_commit_pipes(struct intel_display *display, 5692 u8 pipe_mask, 5693 struct drm_modeset_acquire_ctx *ctx) 5694 { 5695 struct drm_atomic_commit *state; 5696 int ret; 5697 5698 state = drm_atomic_commit_alloc(display->drm); 5699 if (!state) 5700 return -ENOMEM; 5701 5702 ret = intel_modeset_commit_pipes_for_atomic_state(to_intel_atomic_state(state), 5703 pipe_mask, ctx); 5704 5705 drm_atomic_commit_put(state); 5706 5707 return ret; 5708 } 5709 5710 /* 5711 * This implements the workaround described in the "notes" section of the mode 5712 * set sequence documentation. When going from no pipes or single pipe to 5713 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5714 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5715 */ 5716 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5717 { 5718 struct intel_display *display = to_intel_display(state); 5719 struct intel_crtc_state *crtc_state; 5720 struct intel_crtc *crtc; 5721 struct intel_crtc_state *first_crtc_state = NULL; 5722 struct intel_crtc_state *other_crtc_state = NULL; 5723 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5724 5725 /* look at all crtc's that are going to be enabled in during modeset */ 5726 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5727 if (!crtc_state->hw.active || 5728 !intel_crtc_needs_modeset(crtc_state)) 5729 continue; 5730 5731 if (first_crtc_state) { 5732 other_crtc_state = crtc_state; 5733 break; 5734 } else { 5735 first_crtc_state = crtc_state; 5736 first_pipe = crtc->pipe; 5737 } 5738 } 5739 5740 /* No workaround needed? */ 5741 if (!first_crtc_state) 5742 return 0; 5743 5744 /* w/a possibly needed, check how many crtc's are already enabled. */ 5745 for_each_intel_crtc(display, crtc) { 5746 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5747 if (IS_ERR(crtc_state)) 5748 return PTR_ERR(crtc_state); 5749 5750 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5751 5752 if (!crtc_state->hw.active || 5753 intel_crtc_needs_modeset(crtc_state)) 5754 continue; 5755 5756 /* 2 or more enabled crtcs means no need for w/a */ 5757 if (enabled_pipe != INVALID_PIPE) 5758 return 0; 5759 5760 enabled_pipe = crtc->pipe; 5761 } 5762 5763 if (enabled_pipe != INVALID_PIPE) 5764 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5765 else if (other_crtc_state) 5766 other_crtc_state->hsw_workaround_pipe = first_pipe; 5767 5768 return 0; 5769 } 5770 5771 u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, 5772 u8 enabled_pipes) 5773 { 5774 const struct intel_crtc_state *crtc_state; 5775 struct intel_crtc *crtc; 5776 5777 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5778 if (crtc_state->hw.enable) 5779 enabled_pipes |= BIT(crtc->pipe); 5780 else 5781 enabled_pipes &= ~BIT(crtc->pipe); 5782 } 5783 5784 return enabled_pipes; 5785 } 5786 5787 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5788 u8 active_pipes) 5789 { 5790 const struct intel_crtc_state *crtc_state; 5791 struct intel_crtc *crtc; 5792 5793 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5794 if (crtc_state->hw.active) 5795 active_pipes |= BIT(crtc->pipe); 5796 else 5797 active_pipes &= ~BIT(crtc->pipe); 5798 } 5799 5800 return active_pipes; 5801 } 5802 5803 static int intel_modeset_checks(struct intel_atomic_state *state) 5804 { 5805 struct intel_display *display = to_intel_display(state); 5806 5807 state->modeset = true; 5808 5809 if (display->platform.haswell) 5810 return hsw_mode_set_planes_workaround(state); 5811 5812 return 0; 5813 } 5814 5815 static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state, 5816 const struct intel_crtc_state *new_crtc_state) 5817 { 5818 const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode; 5819 const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode; 5820 5821 return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start || 5822 old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end || 5823 old_adjusted_mode->crtc_vsync_start != new_adjusted_mode->crtc_vsync_start || 5824 old_adjusted_mode->crtc_vsync_end != new_adjusted_mode->crtc_vsync_end || 5825 old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal || 5826 old_crtc_state->set_context_latency != new_crtc_state->set_context_latency; 5827 } 5828 5829 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5830 struct intel_crtc_state *new_crtc_state) 5831 { 5832 struct intel_display *display = to_intel_display(new_crtc_state); 5833 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 5834 5835 /* only allow LRR when the timings stay within the VRR range */ 5836 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range) 5837 new_crtc_state->update_lrr = false; 5838 5839 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5840 drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", 5841 crtc->base.base.id, crtc->base.name); 5842 } else { 5843 if (allow_vblank_delay_fastset(old_crtc_state)) 5844 new_crtc_state->update_lrr = true; 5845 new_crtc_state->uapi.mode_changed = false; 5846 } 5847 5848 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, 5849 &new_crtc_state->dp_m_n)) 5850 new_crtc_state->update_m_n = false; 5851 5852 if (!lrr_params_changed(old_crtc_state, new_crtc_state)) 5853 new_crtc_state->update_lrr = false; 5854 5855 if (intel_crtc_needs_modeset(new_crtc_state)) 5856 intel_crtc_flag_modeset(new_crtc_state); 5857 else 5858 new_crtc_state->update_pipe = true; 5859 } 5860 5861 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5862 { 5863 struct intel_display *display = to_intel_display(state); 5864 struct intel_crtc_state __maybe_unused *crtc_state; 5865 struct intel_crtc *crtc; 5866 5867 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5868 int ret; 5869 5870 ret = intel_crtc_atomic_check(state, crtc); 5871 if (ret) { 5872 drm_dbg_atomic(display->drm, 5873 "[CRTC:%d:%s] atomic driver check failed\n", 5874 crtc->base.base.id, crtc->base.name); 5875 return ret; 5876 } 5877 } 5878 5879 return 0; 5880 } 5881 5882 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5883 u8 transcoders) 5884 { 5885 const struct intel_crtc_state *new_crtc_state; 5886 struct intel_crtc *crtc; 5887 5888 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 5889 if (new_crtc_state->hw.enable && 5890 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5891 intel_crtc_needs_modeset(new_crtc_state)) 5892 return true; 5893 } 5894 5895 return false; 5896 } 5897 5898 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5899 u8 pipes) 5900 { 5901 const struct intel_crtc_state *new_crtc_state; 5902 struct intel_crtc *crtc; 5903 5904 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 5905 if (new_crtc_state->hw.enable && 5906 pipes & BIT(crtc->pipe) && 5907 intel_crtc_needs_modeset(new_crtc_state)) 5908 return true; 5909 } 5910 5911 return false; 5912 } 5913 5914 static int intel_atomic_check_joiner(struct intel_atomic_state *state, 5915 struct intel_crtc *primary_crtc) 5916 { 5917 struct intel_display *display = to_intel_display(state); 5918 struct intel_crtc_state *primary_crtc_state = 5919 intel_atomic_get_new_crtc_state(state, primary_crtc); 5920 struct intel_crtc *secondary_crtc; 5921 5922 if (!primary_crtc_state->joiner_pipes) 5923 return 0; 5924 5925 /* sanity check */ 5926 if (drm_WARN_ON(display->drm, 5927 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) 5928 return -EINVAL; 5929 5930 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) { 5931 drm_dbg_kms(display->drm, 5932 "[CRTC:%d:%s] Cannot act as joiner primary " 5933 "(need 0x%x as pipes, only 0x%x possible)\n", 5934 primary_crtc->base.base.id, primary_crtc->base.name, 5935 primary_crtc_state->joiner_pipes, joiner_pipes(display)); 5936 return -EINVAL; 5937 } 5938 5939 for_each_intel_crtc_in_pipe_mask(display, secondary_crtc, 5940 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5941 struct intel_crtc_state *secondary_crtc_state; 5942 int ret; 5943 5944 secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc); 5945 if (IS_ERR(secondary_crtc_state)) 5946 return PTR_ERR(secondary_crtc_state); 5947 5948 /* primary being enabled, secondary was already configured? */ 5949 if (secondary_crtc_state->uapi.enable) { 5950 drm_dbg_kms(display->drm, 5951 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " 5952 "[CRTC:%d:%s] claiming this CRTC for joiner.\n", 5953 secondary_crtc->base.base.id, secondary_crtc->base.name, 5954 primary_crtc->base.base.id, primary_crtc->base.name); 5955 return -EINVAL; 5956 } 5957 5958 drm_dbg_kms(display->drm, 5959 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", 5960 secondary_crtc->base.base.id, secondary_crtc->base.name, 5961 primary_crtc->base.base.id, primary_crtc->base.name); 5962 5963 secondary_crtc_state->joiner_pipes = 5964 primary_crtc_state->joiner_pipes; 5965 5966 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc); 5967 if (ret) 5968 return ret; 5969 } 5970 5971 return 0; 5972 } 5973 5974 static void kill_joiner_secondaries(struct intel_atomic_state *state, 5975 struct intel_crtc *primary_crtc) 5976 { 5977 struct intel_display *display = to_intel_display(state); 5978 struct intel_crtc_state *primary_crtc_state = 5979 intel_atomic_get_new_crtc_state(state, primary_crtc); 5980 struct intel_crtc *secondary_crtc; 5981 5982 for_each_intel_crtc_in_pipe_mask(display, secondary_crtc, 5983 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5984 struct intel_crtc_state *secondary_crtc_state = 5985 intel_atomic_get_new_crtc_state(state, secondary_crtc); 5986 5987 secondary_crtc_state->joiner_pipes = 0; 5988 5989 intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc); 5990 } 5991 5992 primary_crtc_state->joiner_pipes = 0; 5993 } 5994 5995 /** 5996 * DOC: asynchronous flip implementation 5997 * 5998 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5999 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6000 * Correspondingly, support is currently added for primary plane only. 6001 * 6002 * Async flip can only change the plane surface address, so anything else 6003 * changing is rejected from the intel_async_flip_check_hw() function. 6004 * Once this check is cleared, flip done interrupt is enabled using 6005 * the intel_crtc_enable_flip_done() function. 6006 * 6007 * As soon as the surface address register is written, flip done interrupt is 6008 * generated and the requested events are sent to the userspace in the interrupt 6009 * handler itself. The timestamp and sequence sent during the flip done event 6010 * correspond to the last vblank and have no relation to the actual time when 6011 * the flip done event was sent. 6012 */ 6013 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6014 struct intel_crtc *crtc) 6015 { 6016 struct intel_display *display = to_intel_display(state); 6017 const struct intel_crtc_state *new_crtc_state = 6018 intel_atomic_get_new_crtc_state(state, crtc); 6019 const struct intel_plane_state *old_plane_state; 6020 struct intel_plane_state *new_plane_state; 6021 struct intel_plane *plane; 6022 int i; 6023 6024 if (!new_crtc_state->uapi.async_flip) 6025 return 0; 6026 6027 if (!new_crtc_state->uapi.active) { 6028 drm_dbg_kms(display->drm, 6029 "[CRTC:%d:%s] not active\n", 6030 crtc->base.base.id, crtc->base.name); 6031 return -EINVAL; 6032 } 6033 6034 if (intel_crtc_needs_modeset(new_crtc_state)) { 6035 drm_dbg_kms(display->drm, 6036 "[CRTC:%d:%s] modeset required\n", 6037 crtc->base.base.id, crtc->base.name); 6038 return -EINVAL; 6039 } 6040 6041 /* 6042 * FIXME: joiner+async flip is busted currently. 6043 * Remove this check once the issues are fixed. 6044 */ 6045 if (new_crtc_state->joiner_pipes) { 6046 drm_dbg_kms(display->drm, 6047 "[CRTC:%d:%s] async flip disallowed with joiner\n", 6048 crtc->base.base.id, crtc->base.name); 6049 return -EINVAL; 6050 } 6051 6052 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6053 new_plane_state, i) { 6054 if (plane->pipe != crtc->pipe) 6055 continue; 6056 6057 /* 6058 * TODO: Async flip is only supported through the page flip IOCTL 6059 * as of now. So support currently added for primary plane only. 6060 * Support for other planes on platforms on which supports 6061 * this(vlv/chv and icl+) should be added when async flip is 6062 * enabled in the atomic IOCTL path. 6063 */ 6064 if (!plane->async_flip) { 6065 drm_dbg_kms(display->drm, 6066 "[PLANE:%d:%s] async flip not supported\n", 6067 plane->base.base.id, plane->base.name); 6068 return -EINVAL; 6069 } 6070 6071 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6072 drm_dbg_kms(display->drm, 6073 "[PLANE:%d:%s] no old or new framebuffer\n", 6074 plane->base.base.id, plane->base.name); 6075 return -EINVAL; 6076 } 6077 } 6078 6079 return 0; 6080 } 6081 6082 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6083 { 6084 struct intel_display *display = to_intel_display(state); 6085 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6086 const struct intel_plane_state *new_plane_state, *old_plane_state; 6087 struct intel_plane *plane; 6088 int i; 6089 6090 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6091 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6092 6093 if (!new_crtc_state->uapi.async_flip) 6094 return 0; 6095 6096 if (!new_crtc_state->hw.active) { 6097 drm_dbg_kms(display->drm, 6098 "[CRTC:%d:%s] not active\n", 6099 crtc->base.base.id, crtc->base.name); 6100 return -EINVAL; 6101 } 6102 6103 if (intel_crtc_needs_modeset(new_crtc_state)) { 6104 drm_dbg_kms(display->drm, 6105 "[CRTC:%d:%s] modeset required\n", 6106 crtc->base.base.id, crtc->base.name); 6107 return -EINVAL; 6108 } 6109 6110 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6111 drm_dbg_kms(display->drm, 6112 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6113 crtc->base.base.id, crtc->base.name); 6114 return -EINVAL; 6115 } 6116 6117 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6118 new_plane_state, i) { 6119 if (plane->pipe != crtc->pipe) 6120 continue; 6121 6122 /* 6123 * Only async flip capable planes should be in the state 6124 * if we're really about to ask the hardware to perform 6125 * an async flip. We should never get this far otherwise. 6126 */ 6127 if (drm_WARN_ON(display->drm, 6128 new_crtc_state->do_async_flip && !plane->async_flip)) 6129 return -EINVAL; 6130 6131 /* 6132 * Only check async flip capable planes other planes 6133 * may be involved in the initial commit due to 6134 * the wm0/ddb optimization. 6135 * 6136 * TODO maybe should track which planes actually 6137 * were requested to do the async flip... 6138 */ 6139 if (!plane->async_flip) 6140 continue; 6141 6142 if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format, 6143 new_plane_state->hw.fb->modifier)) { 6144 drm_dbg_kms(display->drm, 6145 "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", 6146 plane->base.base.id, plane->base.name, 6147 &new_plane_state->hw.fb->format->format, 6148 new_plane_state->hw.fb->modifier); 6149 return -EINVAL; 6150 } 6151 6152 /* 6153 * We turn the first async flip request into a sync flip 6154 * so that we can reconfigure the plane (eg. change modifier). 6155 */ 6156 if (!new_crtc_state->do_async_flip) 6157 continue; 6158 6159 if (old_plane_state->view.color_plane[0].mapping_stride != 6160 new_plane_state->view.color_plane[0].mapping_stride) { 6161 drm_dbg_kms(display->drm, 6162 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6163 plane->base.base.id, plane->base.name); 6164 return -EINVAL; 6165 } 6166 6167 if (old_plane_state->hw.fb->modifier != 6168 new_plane_state->hw.fb->modifier) { 6169 drm_dbg_kms(display->drm, 6170 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6171 plane->base.base.id, plane->base.name); 6172 return -EINVAL; 6173 } 6174 6175 if (old_plane_state->hw.fb->format != 6176 new_plane_state->hw.fb->format) { 6177 drm_dbg_kms(display->drm, 6178 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6179 plane->base.base.id, plane->base.name); 6180 return -EINVAL; 6181 } 6182 6183 if (old_plane_state->hw.rotation != 6184 new_plane_state->hw.rotation) { 6185 drm_dbg_kms(display->drm, 6186 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6187 plane->base.base.id, plane->base.name); 6188 return -EINVAL; 6189 } 6190 6191 if (skl_plane_aux_dist(old_plane_state, 0) != 6192 skl_plane_aux_dist(new_plane_state, 0)) { 6193 drm_dbg_kms(display->drm, 6194 "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n", 6195 plane->base.base.id, plane->base.name); 6196 return -EINVAL; 6197 } 6198 6199 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6200 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6201 drm_dbg_kms(display->drm, 6202 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6203 plane->base.base.id, plane->base.name); 6204 return -EINVAL; 6205 } 6206 6207 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6208 drm_dbg_kms(display->drm, 6209 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6210 plane->base.base.id, plane->base.name); 6211 return -EINVAL; 6212 } 6213 6214 if (old_plane_state->hw.pixel_blend_mode != 6215 new_plane_state->hw.pixel_blend_mode) { 6216 drm_dbg_kms(display->drm, 6217 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6218 plane->base.base.id, plane->base.name); 6219 return -EINVAL; 6220 } 6221 6222 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6223 drm_dbg_kms(display->drm, 6224 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6225 plane->base.base.id, plane->base.name); 6226 return -EINVAL; 6227 } 6228 6229 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6230 drm_dbg_kms(display->drm, 6231 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6232 plane->base.base.id, plane->base.name); 6233 return -EINVAL; 6234 } 6235 6236 /* plane decryption is allow to change only in synchronous flips */ 6237 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6238 drm_dbg_kms(display->drm, 6239 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6240 plane->base.base.id, plane->base.name); 6241 return -EINVAL; 6242 } 6243 } 6244 6245 return 0; 6246 } 6247 6248 static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) 6249 { 6250 struct intel_display *display = to_intel_display(state); 6251 const struct intel_plane_state *plane_state; 6252 struct intel_crtc_state *crtc_state; 6253 struct intel_plane *plane; 6254 struct intel_crtc *crtc; 6255 u8 affected_pipes = 0; 6256 u8 modeset_pipes = 0; 6257 int i; 6258 6259 /* 6260 * Any plane which is in use by the joiner needs its crtc. 6261 * Pull those in first as this will not have happened yet 6262 * if the plane remains disabled according to uapi. 6263 */ 6264 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6265 crtc = to_intel_crtc(plane_state->hw.crtc); 6266 if (!crtc) 6267 continue; 6268 6269 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6270 if (IS_ERR(crtc_state)) 6271 return PTR_ERR(crtc_state); 6272 } 6273 6274 /* Now pull in all joined crtcs */ 6275 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 6276 affected_pipes |= crtc_state->joiner_pipes; 6277 if (intel_crtc_needs_modeset(crtc_state)) 6278 modeset_pipes |= crtc_state->joiner_pipes; 6279 } 6280 6281 for_each_intel_crtc_in_pipe_mask(display, crtc, affected_pipes) { 6282 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6283 if (IS_ERR(crtc_state)) 6284 return PTR_ERR(crtc_state); 6285 } 6286 6287 for_each_intel_crtc_in_pipe_mask(display, crtc, modeset_pipes) { 6288 int ret; 6289 6290 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6291 6292 crtc_state->uapi.mode_changed = true; 6293 6294 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6295 if (ret) 6296 return ret; 6297 6298 ret = intel_plane_add_affected(state, crtc); 6299 if (ret) 6300 return ret; 6301 } 6302 6303 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 6304 /* Kill old joiner link, we may re-establish afterwards */ 6305 if (intel_crtc_needs_modeset(crtc_state) && 6306 intel_crtc_is_joiner_primary(crtc_state)) 6307 kill_joiner_secondaries(state, crtc); 6308 } 6309 6310 return 0; 6311 } 6312 6313 static int intel_atomic_check_config(struct intel_atomic_state *state, 6314 struct intel_link_bw_limits *limits, 6315 enum pipe *failed_pipe) 6316 { 6317 struct intel_display *display = to_intel_display(state); 6318 struct intel_crtc_state *new_crtc_state; 6319 struct intel_crtc *crtc; 6320 int ret; 6321 6322 *failed_pipe = INVALID_PIPE; 6323 6324 ret = intel_joiner_add_affected_crtcs(state); 6325 if (ret) 6326 return ret; 6327 6328 ret = intel_fdi_add_affected_crtcs(state); 6329 if (ret) 6330 return ret; 6331 6332 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6333 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6334 if (!intel_crtc_is_joiner_secondary(new_crtc_state)) 6335 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6336 continue; 6337 } 6338 6339 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6340 continue; 6341 6342 ret = intel_crtc_prepare_cleared_state(state, crtc); 6343 if (ret) 6344 goto fail; 6345 6346 if (!new_crtc_state->hw.enable) 6347 continue; 6348 6349 ret = intel_modeset_pipe_config(state, crtc, limits); 6350 if (ret) 6351 goto fail; 6352 } 6353 6354 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6355 if (!intel_crtc_needs_modeset(new_crtc_state)) 6356 continue; 6357 6358 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6359 continue; 6360 6361 if (!new_crtc_state->hw.enable) 6362 continue; 6363 6364 ret = intel_modeset_pipe_config_late(state, crtc); 6365 if (ret) 6366 goto fail; 6367 } 6368 6369 fail: 6370 if (ret) 6371 *failed_pipe = crtc->pipe; 6372 6373 return ret; 6374 } 6375 6376 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) 6377 { 6378 struct intel_link_bw_limits new_limits; 6379 struct intel_link_bw_limits old_limits; 6380 int ret; 6381 6382 intel_link_bw_init_limits(state, &new_limits); 6383 old_limits = new_limits; 6384 6385 while (true) { 6386 enum pipe failed_pipe; 6387 6388 ret = intel_atomic_check_config(state, &new_limits, 6389 &failed_pipe); 6390 if (ret) { 6391 /* 6392 * The bpp limit for a pipe is below the minimum it supports, set the 6393 * limit to the minimum and recalculate the config. 6394 */ 6395 if (ret == -EINVAL && 6396 intel_link_bw_set_bpp_limit_for_pipe(state, 6397 &old_limits, 6398 &new_limits, 6399 failed_pipe)) 6400 continue; 6401 6402 break; 6403 } 6404 6405 old_limits = new_limits; 6406 6407 ret = intel_link_bw_atomic_check(state, &new_limits); 6408 if (ret != -EAGAIN) 6409 break; 6410 } 6411 6412 return ret; 6413 } 6414 /** 6415 * intel_atomic_check - validate state object 6416 * @dev: drm device 6417 * @_state: state to validate 6418 */ 6419 int intel_atomic_check(struct drm_device *dev, 6420 struct drm_atomic_commit *_state) 6421 { 6422 struct intel_display *display = to_intel_display(dev); 6423 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6424 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6425 struct intel_crtc *crtc; 6426 int ret; 6427 6428 if (!intel_display_driver_check_access(display)) 6429 return -ENODEV; 6430 6431 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6432 /* 6433 * crtc's state no longer considered to be inherited 6434 * after the first userspace/client initiated commit. 6435 */ 6436 if (!state->internal) 6437 new_crtc_state->inherited = false; 6438 6439 if (new_crtc_state->inherited != old_crtc_state->inherited) 6440 new_crtc_state->uapi.mode_changed = true; 6441 6442 if (new_crtc_state->uapi.scaling_filter != 6443 old_crtc_state->uapi.scaling_filter) 6444 new_crtc_state->uapi.mode_changed = true; 6445 6446 if (new_crtc_state->uapi.sharpness_strength != 6447 old_crtc_state->uapi.sharpness_strength) 6448 new_crtc_state->uapi.mode_changed = true; 6449 } 6450 6451 intel_vrr_check_modeset(state); 6452 6453 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6454 if (ret) 6455 goto fail; 6456 6457 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6458 ret = intel_async_flip_check_uapi(state, crtc); 6459 if (ret) 6460 return ret; 6461 } 6462 6463 ret = intel_atomic_check_config_and_link(state); 6464 if (ret) 6465 goto fail; 6466 6467 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6468 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6469 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6470 copy_joiner_crtc_state_nomodeset(state, crtc); 6471 continue; 6472 } 6473 6474 if (intel_crtc_is_joiner_secondary(new_crtc_state)) { 6475 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable); 6476 continue; 6477 } 6478 6479 ret = intel_atomic_check_joiner(state, crtc); 6480 if (ret) 6481 goto fail; 6482 } 6483 6484 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6485 if (!intel_crtc_needs_modeset(new_crtc_state)) 6486 continue; 6487 6488 intel_joiner_adjust_pipe_src(new_crtc_state); 6489 6490 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6491 } 6492 6493 /** 6494 * Check if fastset is allowed by external dependencies like other 6495 * pipes and transcoders. 6496 * 6497 * Right now it only forces a fullmodeset when the MST master 6498 * transcoder did not changed but the pipe of the master transcoder 6499 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6500 * in case of port synced crtcs, if one of the synced crtcs 6501 * needs a full modeset, all other synced crtcs should be 6502 * forced a full modeset. 6503 */ 6504 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6505 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6506 continue; 6507 6508 if (intel_dp_mst_crtc_needs_modeset(state, crtc)) 6509 intel_crtc_flag_modeset(new_crtc_state); 6510 6511 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6512 enum transcoder master = new_crtc_state->mst_master_transcoder; 6513 6514 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) 6515 intel_crtc_flag_modeset(new_crtc_state); 6516 } 6517 6518 if (is_trans_port_sync_mode(new_crtc_state)) { 6519 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6520 6521 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6522 trans |= BIT(new_crtc_state->master_transcoder); 6523 6524 if (intel_cpu_transcoders_need_modeset(state, trans)) 6525 intel_crtc_flag_modeset(new_crtc_state); 6526 } 6527 6528 if (new_crtc_state->joiner_pipes) { 6529 if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes)) 6530 intel_crtc_flag_modeset(new_crtc_state); 6531 } 6532 } 6533 6534 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6535 if (!intel_crtc_needs_modeset(new_crtc_state)) 6536 continue; 6537 6538 intel_dpll_release(state, crtc); 6539 } 6540 6541 if (intel_any_crtc_needs_modeset(state) && !check_digital_port_conflicts(state)) { 6542 drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n"); 6543 ret = -EINVAL; 6544 goto fail; 6545 } 6546 6547 ret = intel_plane_atomic_check(state); 6548 if (ret) 6549 goto fail; 6550 6551 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 6552 new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state); 6553 6554 ret = intel_compute_global_watermarks(state); 6555 if (ret) 6556 goto fail; 6557 6558 ret = intel_bw_atomic_check(state); 6559 if (ret) 6560 goto fail; 6561 6562 ret = intel_cdclk_atomic_check(state); 6563 if (ret) 6564 goto fail; 6565 6566 if (intel_any_crtc_needs_modeset(state)) { 6567 ret = intel_modeset_checks(state); 6568 if (ret) 6569 goto fail; 6570 } 6571 6572 ret = intel_pmdemand_atomic_check(state); 6573 if (ret) 6574 goto fail; 6575 6576 ret = intel_atomic_check_crtcs(state); 6577 if (ret) 6578 goto fail; 6579 6580 ret = intel_fbc_atomic_check(state); 6581 if (ret) 6582 goto fail; 6583 6584 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6585 intel_color_assert_luts(new_crtc_state); 6586 6587 ret = intel_async_flip_check_hw(state, crtc); 6588 if (ret) 6589 goto fail; 6590 6591 /* Either full modeset or fastset (or neither), never both */ 6592 drm_WARN_ON(display->drm, 6593 intel_crtc_needs_modeset(new_crtc_state) && 6594 intel_crtc_needs_fastset(new_crtc_state)); 6595 6596 if (!intel_crtc_needs_modeset(new_crtc_state) && 6597 !intel_crtc_needs_fastset(new_crtc_state)) 6598 continue; 6599 6600 intel_crtc_state_dump(new_crtc_state, state, 6601 intel_crtc_needs_modeset(new_crtc_state) ? 6602 "modeset" : "fastset"); 6603 } 6604 6605 return 0; 6606 6607 fail: 6608 if (ret == -EDEADLK) 6609 return ret; 6610 6611 /* 6612 * FIXME would probably be nice to know which crtc specifically 6613 * caused the failure, in cases where we can pinpoint it. 6614 */ 6615 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) 6616 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6617 6618 return ret; 6619 } 6620 6621 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6622 { 6623 int ret; 6624 6625 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6626 if (ret < 0) 6627 return ret; 6628 6629 return 0; 6630 } 6631 6632 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6633 struct intel_crtc_state *crtc_state) 6634 { 6635 struct intel_display *display = to_intel_display(crtc); 6636 6637 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) 6638 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 6639 6640 if (crtc_state->has_pch_encoder) { 6641 enum pipe pch_transcoder = 6642 intel_crtc_pch_transcoder(crtc); 6643 6644 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true); 6645 } 6646 } 6647 6648 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6649 const struct intel_crtc_state *new_crtc_state) 6650 { 6651 struct intel_display *display = to_intel_display(new_crtc_state); 6652 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6653 6654 /* 6655 * Update pipe size and adjust fitter if needed: the reason for this is 6656 * that in compute_mode_changes we check the native mode (not the pfit 6657 * mode) to see if we can flip rather than do a full mode set. In the 6658 * fastboot case, we'll flip, but if we don't update the pipesrc and 6659 * pfit state, we'll end up with a big fb scanned out into the wrong 6660 * sized surface. 6661 */ 6662 intel_set_pipe_src_size(new_crtc_state); 6663 6664 /* on skylake this is done by detaching scalers */ 6665 if (DISPLAY_VER(display) >= 9) { 6666 if (new_crtc_state->pch_pfit.enabled) 6667 skl_pfit_enable(new_crtc_state); 6668 } else if (HAS_PCH_SPLIT(display)) { 6669 if (new_crtc_state->pch_pfit.enabled) 6670 ilk_pfit_enable(new_crtc_state); 6671 else if (old_crtc_state->pch_pfit.enabled) 6672 ilk_pfit_disable(old_crtc_state); 6673 } 6674 6675 /* 6676 * The register is supposedly single buffered so perhaps 6677 * not 100% correct to do this here. But SKL+ calculate 6678 * this based on the adjust pixel rate so pfit changes do 6679 * affect it and so it must be updated for fastsets. 6680 * HSW/BDW only really need this here for fastboot, after 6681 * that the value should not change without a full modeset. 6682 */ 6683 if (DISPLAY_VER(display) >= 9 || 6684 display->platform.broadwell || display->platform.haswell) 6685 hsw_set_linetime_wm(new_crtc_state); 6686 6687 if (new_crtc_state->update_m_n) { 6688 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6689 &new_crtc_state->dp_m_n); 6690 intel_cmtg_set_m_n(new_crtc_state); 6691 } 6692 6693 if (new_crtc_state->update_lrr) { 6694 intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder); 6695 intel_cmtg_set_timings(new_crtc_state, LRR); 6696 intel_vrr_set_fixed_rr_timings(new_crtc_state, new_crtc_state->cpu_transcoder); 6697 intel_cmtg_set_vrr_timings(new_crtc_state); 6698 intel_vrr_transcoder_enable(new_crtc_state); 6699 } 6700 } 6701 6702 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6703 struct intel_crtc *crtc) 6704 { 6705 struct intel_display *display = to_intel_display(state); 6706 const struct intel_crtc_state *old_crtc_state = 6707 intel_atomic_get_old_crtc_state(state, crtc); 6708 const struct intel_crtc_state *new_crtc_state = 6709 intel_atomic_get_new_crtc_state(state, crtc); 6710 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6711 6712 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6713 6714 /* 6715 * During modesets pipe configuration was programmed as the 6716 * CRTC was enabled. 6717 */ 6718 if (!modeset) { 6719 if (intel_crtc_needs_color_update(new_crtc_state)) 6720 intel_color_commit_arm(NULL, new_crtc_state); 6721 6722 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 6723 bdw_set_pipe_misc(NULL, new_crtc_state); 6724 6725 if (intel_crtc_needs_fastset(new_crtc_state)) 6726 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6727 } 6728 6729 intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); 6730 6731 intel_atomic_update_watermarks(state, crtc); 6732 } 6733 6734 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6735 struct intel_crtc *crtc) 6736 { 6737 struct intel_display *display = to_intel_display(state); 6738 const struct intel_crtc_state *new_crtc_state = 6739 intel_atomic_get_new_crtc_state(state, crtc); 6740 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6741 6742 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6743 6744 /* 6745 * Disable the scaler(s) after the plane(s) so that we don't 6746 * get a catastrophic underrun even if the two operations 6747 * end up happening in two different frames. 6748 */ 6749 if (DISPLAY_VER(display) >= 9 && !modeset) 6750 skl_detach_scalers(NULL, new_crtc_state); 6751 6752 if (!modeset && 6753 intel_crtc_needs_color_update(new_crtc_state) && 6754 !intel_color_uses_dsb(new_crtc_state) && 6755 HAS_DOUBLE_BUFFERED_LUT(display)) 6756 intel_color_load_luts(new_crtc_state); 6757 6758 if (intel_crtc_vrr_enabling(state, crtc)) 6759 intel_vrr_enable(new_crtc_state); 6760 } 6761 6762 static void intel_enable_crtc(struct intel_atomic_state *state, 6763 struct intel_crtc *crtc) 6764 { 6765 struct intel_display *display = to_intel_display(state); 6766 const struct intel_crtc_state *new_crtc_state = 6767 intel_atomic_get_new_crtc_state(state, crtc); 6768 struct intel_crtc *pipe_crtc; 6769 6770 if (!intel_crtc_needs_modeset(new_crtc_state)) 6771 return; 6772 6773 for_each_intel_crtc_in_pipe_mask_reverse(display, pipe_crtc, 6774 intel_crtc_joined_pipe_mask(new_crtc_state)) { 6775 const struct intel_crtc_state *pipe_crtc_state = 6776 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6777 6778 /* VRR will be enable later, if required */ 6779 intel_crtc_update_active_timings(pipe_crtc_state, false); 6780 } 6781 6782 intel_psr_notify_pipe_change(state, crtc, true); 6783 6784 display->modeset.funcs->crtc_enable(state, crtc); 6785 6786 intel_crtc_wait_for_next_vblank(crtc); 6787 6788 /* vblanks work again, re-enable pipe CRC. */ 6789 intel_crtc_enable_pipe_crc(crtc); 6790 } 6791 6792 static void intel_pre_update_crtc(struct intel_atomic_state *state, 6793 struct intel_crtc *crtc) 6794 { 6795 struct intel_display *display = to_intel_display(state); 6796 const struct intel_crtc_state *old_crtc_state = 6797 intel_atomic_get_old_crtc_state(state, crtc); 6798 struct intel_crtc_state *new_crtc_state = 6799 intel_atomic_get_new_crtc_state(state, crtc); 6800 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6801 6802 if (old_crtc_state->inherited || 6803 intel_crtc_needs_modeset(new_crtc_state)) { 6804 if (HAS_DPT(display)) 6805 intel_dpt_configure(crtc); 6806 } 6807 6808 if (!modeset) { 6809 if (new_crtc_state->preload_luts && 6810 intel_crtc_needs_color_update(new_crtc_state)) 6811 intel_color_load_luts(new_crtc_state); 6812 6813 intel_pre_plane_update(state, crtc); 6814 6815 if (intel_crtc_needs_fastset(new_crtc_state)) 6816 intel_encoders_update_pipe(state, crtc); 6817 6818 if (DISPLAY_VER(display) >= 11 && 6819 intel_crtc_needs_fastset(new_crtc_state)) 6820 icl_set_pipe_chicken(new_crtc_state); 6821 6822 if (vrr_params_changed(old_crtc_state, new_crtc_state) || 6823 cmrr_params_changed(old_crtc_state, new_crtc_state)) 6824 intel_vrr_set_transcoder_timings(new_crtc_state); 6825 } 6826 6827 intel_fbc_update(state, crtc); 6828 6829 drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); 6830 6831 if (!modeset && 6832 intel_crtc_needs_color_update(new_crtc_state) && 6833 !new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6834 intel_color_commit_noarm(NULL, new_crtc_state); 6835 6836 if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6837 intel_crtc_planes_update_noarm(NULL, state, crtc); 6838 } 6839 6840 static void intel_update_crtc(struct intel_atomic_state *state, 6841 struct intel_crtc *crtc) 6842 { 6843 const struct intel_crtc_state *old_crtc_state = 6844 intel_atomic_get_old_crtc_state(state, crtc); 6845 struct intel_crtc_state *new_crtc_state = 6846 intel_atomic_get_new_crtc_state(state, crtc); 6847 6848 if (new_crtc_state->use_flipq) { 6849 intel_flipq_enable(new_crtc_state); 6850 6851 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event); 6852 6853 intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0, 6854 new_crtc_state->dsb_commit); 6855 } else if (new_crtc_state->use_dsb) { 6856 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); 6857 6858 intel_dsb_commit(new_crtc_state->dsb_commit); 6859 } else { 6860 /* Perform vblank evasion around commit operation */ 6861 intel_pipe_update_start(state, crtc); 6862 6863 if (new_crtc_state->dsb_commit) 6864 intel_dsb_commit(new_crtc_state->dsb_commit); 6865 6866 commit_pipe_pre_planes(state, crtc); 6867 6868 intel_crtc_planes_update_arm(NULL, state, crtc); 6869 6870 commit_pipe_post_planes(state, crtc); 6871 6872 intel_pipe_update_end(state, crtc); 6873 } 6874 6875 /* 6876 * VRR/Seamless M/N update may need to update frame timings. 6877 * 6878 * FIXME Should be synchronized with the start of vblank somehow... 6879 */ 6880 if (intel_crtc_vrr_enabling(state, crtc) || 6881 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 6882 intel_crtc_update_active_timings(new_crtc_state, 6883 new_crtc_state->vrr.enable); 6884 6885 if (new_crtc_state->vrr.dc_balance.enable) 6886 intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); 6887 6888 /* 6889 * We usually enable FIFO underrun interrupts as part of the 6890 * CRTC enable sequence during modesets. But when we inherit a 6891 * valid pipe configuration from the BIOS we need to take care 6892 * of enabling them on the CRTC's first fastset. 6893 */ 6894 if (intel_crtc_needs_fastset(new_crtc_state) && 6895 old_crtc_state->inherited) 6896 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6897 6898 if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc) && 6899 intel_cmtg_is_allowed(new_crtc_state)) { 6900 intel_cmtg_set_clk_select(new_crtc_state); 6901 intel_cmtg_disable(new_crtc_state); 6902 } 6903 } 6904 6905 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6906 struct intel_crtc *crtc) 6907 { 6908 struct intel_display *display = to_intel_display(state); 6909 const struct intel_crtc_state *old_crtc_state = 6910 intel_atomic_get_old_crtc_state(state, crtc); 6911 struct intel_crtc *pipe_crtc; 6912 6913 /* 6914 * We need to disable pipe CRC before disabling the pipe, 6915 * or we race against vblank off. 6916 */ 6917 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 6918 intel_crtc_joined_pipe_mask(old_crtc_state)) 6919 intel_crtc_disable_pipe_crc(pipe_crtc); 6920 6921 intel_psr_notify_pipe_change(state, crtc, false); 6922 6923 display->modeset.funcs->crtc_disable(state, crtc); 6924 6925 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 6926 intel_crtc_joined_pipe_mask(old_crtc_state)) { 6927 const struct intel_crtc_state *new_pipe_crtc_state = 6928 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6929 6930 pipe_crtc->active = false; 6931 intel_fbc_disable(pipe_crtc); 6932 6933 if (!new_pipe_crtc_state->hw.active) 6934 intel_initial_watermarks(state, pipe_crtc); 6935 } 6936 } 6937 6938 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6939 { 6940 struct intel_display *display = to_intel_display(state); 6941 const struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6942 struct intel_crtc *crtc; 6943 u8 disable_pipes = 0; 6944 6945 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6946 if (!intel_crtc_needs_modeset(new_crtc_state)) 6947 continue; 6948 6949 /* 6950 * Needs to be done even for pipes 6951 * that weren't enabled previously. 6952 */ 6953 intel_pre_plane_update(state, crtc); 6954 6955 if (!old_crtc_state->hw.active) 6956 continue; 6957 6958 disable_pipes |= BIT(crtc->pipe); 6959 } 6960 6961 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) { 6962 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6963 continue; 6964 6965 intel_crtc_disable_planes(state, crtc); 6966 6967 drm_vblank_work_flush_all(&crtc->base); 6968 } 6969 6970 /* Only disable port sync and MST slaves */ 6971 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) { 6972 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6973 continue; 6974 6975 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 6976 continue; 6977 6978 /* In case of Transcoder port Sync master slave CRTCs can be 6979 * assigned in any order and we need to make sure that 6980 * slave CRTCs are disabled first and then master CRTC since 6981 * Slave vblanks are masked till Master Vblanks. 6982 */ 6983 if (!is_trans_port_sync_slave(old_crtc_state) && 6984 !intel_dp_mst_is_slave_trans(old_crtc_state)) 6985 continue; 6986 6987 intel_old_crtc_state_disables(state, crtc); 6988 6989 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 6990 } 6991 6992 /* Disable everything else left on */ 6993 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) { 6994 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6995 continue; 6996 6997 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 6998 continue; 6999 7000 intel_old_crtc_state_disables(state, crtc); 7001 7002 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 7003 } 7004 7005 drm_WARN_ON(display->drm, disable_pipes); 7006 } 7007 7008 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7009 { 7010 struct intel_crtc_state *new_crtc_state; 7011 struct intel_crtc *crtc; 7012 7013 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7014 if (!new_crtc_state->hw.active) 7015 continue; 7016 7017 intel_enable_crtc(state, crtc); 7018 intel_pre_update_crtc(state, crtc); 7019 } 7020 7021 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7022 if (!new_crtc_state->hw.active) 7023 continue; 7024 7025 intel_update_crtc(state, crtc); 7026 } 7027 } 7028 7029 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7030 { 7031 struct intel_display *display = to_intel_display(state); 7032 struct intel_crtc *crtc; 7033 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7034 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7035 u8 update_pipes = 0, modeset_pipes = 0; 7036 7037 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7038 enum pipe pipe = crtc->pipe; 7039 7040 if (!new_crtc_state->hw.active) 7041 continue; 7042 7043 /* ignore allocations for crtc's that have been turned off. */ 7044 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7045 entries[pipe] = old_crtc_state->wm.skl.ddb; 7046 update_pipes |= BIT(pipe); 7047 } else { 7048 modeset_pipes |= BIT(pipe); 7049 } 7050 } 7051 7052 /* 7053 * Whenever the number of active pipes changes, we need to make sure we 7054 * update the pipes in the right order so that their ddb allocations 7055 * never overlap with each other between CRTC updates. Otherwise we'll 7056 * cause pipe underruns and other bad stuff. 7057 * 7058 * So first lets enable all pipes that do not need a fullmodeset as 7059 * those don't have any external dependency. 7060 */ 7061 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7062 enum pipe pipe = crtc->pipe; 7063 7064 if ((update_pipes & BIT(pipe)) == 0) 7065 continue; 7066 7067 intel_pre_update_crtc(state, crtc); 7068 } 7069 7070 intel_dbuf_mbus_pre_ddb_update(state); 7071 7072 while (update_pipes) { 7073 /* 7074 * Commit in reverse order to make joiner primary 7075 * send the uapi events after secondaries are done. 7076 */ 7077 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, new_crtc_state) { 7078 enum pipe pipe = crtc->pipe; 7079 7080 if ((update_pipes & BIT(pipe)) == 0) 7081 continue; 7082 7083 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7084 entries, I915_MAX_PIPES, pipe)) 7085 continue; 7086 7087 entries[pipe] = new_crtc_state->wm.skl.ddb; 7088 update_pipes &= ~BIT(pipe); 7089 7090 intel_update_crtc(state, crtc); 7091 7092 /* 7093 * If this is an already active pipe, it's DDB changed, 7094 * and this isn't the last pipe that needs updating 7095 * then we need to wait for a vblank to pass for the 7096 * new ddb allocation to take effect. 7097 */ 7098 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7099 &old_crtc_state->wm.skl.ddb) && 7100 (update_pipes | modeset_pipes)) 7101 intel_crtc_wait_for_next_vblank(crtc); 7102 } 7103 } 7104 7105 intel_dbuf_mbus_post_ddb_update(state); 7106 7107 update_pipes = modeset_pipes; 7108 7109 /* 7110 * Enable all pipes that needs a modeset and do not depends on other 7111 * pipes 7112 */ 7113 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7114 enum pipe pipe = crtc->pipe; 7115 7116 if ((modeset_pipes & BIT(pipe)) == 0) 7117 continue; 7118 7119 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7120 continue; 7121 7122 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7123 is_trans_port_sync_master(new_crtc_state)) 7124 continue; 7125 7126 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7127 7128 intel_enable_crtc(state, crtc); 7129 } 7130 7131 /* 7132 * Then we enable all remaining pipes that depend on other 7133 * pipes: MST slaves and port sync masters 7134 */ 7135 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7136 enum pipe pipe = crtc->pipe; 7137 7138 if ((modeset_pipes & BIT(pipe)) == 0) 7139 continue; 7140 7141 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7142 continue; 7143 7144 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7145 7146 intel_enable_crtc(state, crtc); 7147 } 7148 7149 /* 7150 * Finally we do the plane updates/etc. for all pipes that got enabled. 7151 */ 7152 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7153 enum pipe pipe = crtc->pipe; 7154 7155 if ((update_pipes & BIT(pipe)) == 0) 7156 continue; 7157 7158 intel_pre_update_crtc(state, crtc); 7159 } 7160 7161 /* 7162 * Commit in reverse order to make joiner primary 7163 * send the uapi events after secondaries are done. 7164 */ 7165 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state) { 7166 enum pipe pipe = crtc->pipe; 7167 7168 if ((update_pipes & BIT(pipe)) == 0) 7169 continue; 7170 7171 drm_WARN_ON(display->drm, 7172 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7173 entries, I915_MAX_PIPES, pipe)); 7174 7175 entries[pipe] = new_crtc_state->wm.skl.ddb; 7176 update_pipes &= ~BIT(pipe); 7177 7178 intel_update_crtc(state, crtc); 7179 } 7180 7181 drm_WARN_ON(display->drm, modeset_pipes); 7182 drm_WARN_ON(display->drm, update_pipes); 7183 } 7184 7185 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7186 { 7187 struct drm_plane *plane; 7188 struct drm_plane_state *new_plane_state; 7189 long ret; 7190 int i; 7191 7192 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) { 7193 if (new_plane_state->fence) { 7194 ret = dma_fence_wait_timeout(new_plane_state->fence, false, 7195 i915_fence_timeout()); 7196 if (ret <= 0) 7197 break; 7198 7199 dma_fence_put(new_plane_state->fence); 7200 new_plane_state->fence = NULL; 7201 } 7202 } 7203 } 7204 7205 static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state) 7206 { 7207 if (crtc_state->dsb_commit) 7208 intel_dsb_wait(crtc_state->dsb_commit); 7209 7210 intel_color_wait_commit(crtc_state); 7211 } 7212 7213 static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state) 7214 { 7215 if (crtc_state->dsb_commit) { 7216 intel_dsb_cleanup(crtc_state->dsb_commit); 7217 crtc_state->dsb_commit = NULL; 7218 } 7219 7220 intel_color_cleanup_commit(crtc_state); 7221 } 7222 7223 static void intel_atomic_cleanup_work(struct work_struct *work) 7224 { 7225 struct intel_atomic_state *state = 7226 container_of(work, struct intel_atomic_state, cleanup_work); 7227 struct intel_display *display = to_intel_display(state); 7228 struct intel_crtc_state *old_crtc_state; 7229 struct intel_crtc *crtc; 7230 7231 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) 7232 intel_atomic_dsb_cleanup(old_crtc_state); 7233 7234 drm_atomic_helper_cleanup_planes(display->drm, &state->base); 7235 drm_atomic_helper_commit_cleanup_done(&state->base); 7236 drm_atomic_commit_put(&state->base); 7237 } 7238 7239 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7240 { 7241 struct intel_display *display = to_intel_display(state); 7242 struct intel_plane *plane; 7243 struct intel_plane_state *plane_state; 7244 int i; 7245 7246 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7247 struct drm_framebuffer *fb = plane_state->hw.fb; 7248 int cc_plane; 7249 int ret; 7250 7251 if (!fb) 7252 continue; 7253 7254 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7255 if (cc_plane < 0) 7256 continue; 7257 7258 /* 7259 * The layout of the fast clear color value expected by HW 7260 * (the DRM ABI requiring this value to be located in fb at 7261 * offset 0 of cc plane, plane #2 previous generations or 7262 * plane #1 for flat ccs): 7263 * - 4 x 4 bytes per-channel value 7264 * (in surface type specific float/int format provided by the fb user) 7265 * - 8 bytes native color value used by the display 7266 * (converted/written by GPU during a fast clear operation using the 7267 * above per-channel values) 7268 * 7269 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7270 * caller made sure that the object is synced wrt. the related color clear value 7271 * GPU write on it. 7272 */ 7273 ret = intel_bo_read_from_page(intel_fb_bo(fb), 7274 fb->offsets[cc_plane] + 16, 7275 &plane_state->ccval, 7276 sizeof(plane_state->ccval)); 7277 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7278 drm_WARN_ON(display->drm, ret); 7279 } 7280 } 7281 7282 static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, 7283 struct intel_crtc *crtc) 7284 { 7285 struct intel_display *display = to_intel_display(state); 7286 struct intel_crtc_state *new_crtc_state = 7287 intel_atomic_get_new_crtc_state(state, crtc); 7288 7289 if (!new_crtc_state->hw.active) 7290 return; 7291 7292 if (state->base.legacy_cursor_update) 7293 return; 7294 7295 /* FIXME deal with everything */ 7296 new_crtc_state->use_flipq = 7297 intel_flipq_supported(display) && 7298 !new_crtc_state->do_async_flip && 7299 !new_crtc_state->vrr.enable && 7300 !new_crtc_state->has_psr && 7301 !intel_crtc_needs_modeset(new_crtc_state) && 7302 !intel_crtc_needs_fastset(new_crtc_state) && 7303 !intel_crtc_needs_color_update(new_crtc_state); 7304 7305 new_crtc_state->use_dsb = 7306 !new_crtc_state->use_flipq && 7307 !new_crtc_state->do_async_flip && 7308 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && 7309 !intel_crtc_needs_modeset(new_crtc_state) && 7310 !intel_crtc_needs_fastset(new_crtc_state); 7311 7312 intel_color_prepare_commit(state, crtc); 7313 } 7314 7315 static void intel_atomic_dsb_finish(struct intel_atomic_state *state, 7316 struct intel_crtc *crtc) 7317 { 7318 struct intel_display *display = to_intel_display(state); 7319 struct intel_crtc_state *new_crtc_state = 7320 intel_atomic_get_new_crtc_state(state, crtc); 7321 unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024; 7322 7323 if (!new_crtc_state->use_flipq && 7324 !new_crtc_state->use_dsb && 7325 !new_crtc_state->dsb_color) 7326 return; 7327 7328 /* 7329 * Rough estimate: 7330 * ~64 registers per each plane * 8 planes = 512 7331 * Double that for pipe stuff and other overhead. 7332 * ~4913 registers for 3DLUT 7333 * ~200 color registers * 3 HDR planes 7334 */ 7335 new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 7336 new_crtc_state->use_dsb || 7337 new_crtc_state->use_flipq ? size : 16); 7338 if (!new_crtc_state->dsb_commit) { 7339 new_crtc_state->use_flipq = false; 7340 new_crtc_state->use_dsb = false; 7341 intel_color_cleanup_commit(new_crtc_state); 7342 return; 7343 } 7344 7345 if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) { 7346 /* Wa_18034343758 */ 7347 if (new_crtc_state->use_flipq) 7348 intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); 7349 7350 if (new_crtc_state->vrr.dc_balance.enable) { 7351 /* 7352 * Pause the DMC DC balancing for the remainder of 7353 * the commit so that vmin/vmax won't change after 7354 * we've baked them into the DSB vblank evasion 7355 * commands. 7356 * 7357 * FIXME maybe need a small delay here to make sure 7358 * DMC has finished updating the values? Or we need 7359 * a better DMC<->driver protocol that gives is real 7360 * guarantees about that... 7361 */ 7362 intel_pipedmc_dcb_disable(NULL, crtc); 7363 } 7364 7365 if (intel_crtc_needs_color_update(new_crtc_state)) 7366 intel_color_commit_noarm(new_crtc_state->dsb_commit, 7367 new_crtc_state); 7368 intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, 7369 state, crtc); 7370 7371 /* 7372 * Ensure we have "Frame Change" event when PSR state is 7373 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank 7374 * evasion hangs as PIPEDSL is reading as 0. 7375 */ 7376 intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, 7377 state, crtc); 7378 7379 if (new_crtc_state->use_dsb) 7380 intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); 7381 7382 if (intel_crtc_needs_color_update(new_crtc_state)) 7383 intel_color_commit_arm(new_crtc_state->dsb_commit, 7384 new_crtc_state); 7385 bdw_set_pipe_misc(new_crtc_state->dsb_commit, 7386 new_crtc_state); 7387 intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, 7388 new_crtc_state); 7389 intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, 7390 state, crtc); 7391 7392 if (DISPLAY_VER(display) >= 9) 7393 skl_detach_scalers(new_crtc_state->dsb_commit, 7394 new_crtc_state); 7395 7396 /* Wa_18034343758 */ 7397 if (new_crtc_state->use_flipq) 7398 intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc); 7399 } 7400 7401 if (intel_color_uses_chained_dsb(new_crtc_state)) 7402 intel_dsb_chain(state, new_crtc_state->dsb_commit, 7403 new_crtc_state->dsb_color, true); 7404 else if (intel_color_uses_gosub_dsb(new_crtc_state)) 7405 intel_dsb_gosub(new_crtc_state->dsb_commit, 7406 new_crtc_state->dsb_color); 7407 7408 if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { 7409 /* 7410 * Dsb wait vblank may or may not skip. Let's remove it for PSR 7411 * trans push case to ensure we are not waiting two vblanks 7412 */ 7413 if (!intel_psr_use_trans_push(new_crtc_state)) 7414 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); 7415 7416 intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); 7417 7418 /* 7419 * Wait for idle is needed for corner case where PSR HW 7420 * is transitioning into DEEP_SLEEP/SRDENT_OFF when 7421 * new Frame Change event comes in. It is ok to do it 7422 * here for both Frame Change mechanism (trans push 7423 * and register write). 7424 */ 7425 intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit, 7426 new_crtc_state); 7427 7428 /* 7429 * In case PSR uses trans push as a "frame change" event and 7430 * VRR is not in use we need to wait vblank. Otherwise we may 7431 * miss selective updates. DSB skips all waits while PSR is 7432 * active. Check push send is skipped as well because trans push 7433 * send bit is not reset by the HW if VRR is not 7434 * enabled -> we may start configuring new selective 7435 * update while previous is not complete. 7436 */ 7437 if (intel_psr_use_trans_push(new_crtc_state)) 7438 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); 7439 7440 intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); 7441 intel_vrr_check_push_sent(new_crtc_state->dsb_commit, 7442 new_crtc_state); 7443 7444 if (new_crtc_state->vrr.dc_balance.enable) 7445 intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); 7446 7447 intel_dsb_interrupt(new_crtc_state->dsb_commit); 7448 } 7449 7450 intel_dsb_finish(new_crtc_state->dsb_commit); 7451 } 7452 7453 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7454 { 7455 struct intel_display *display = to_intel_display(state); 7456 struct intel_uncore *uncore = to_intel_uncore(display->drm); 7457 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7458 struct intel_crtc *crtc; 7459 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7460 struct ref_tracker *wakeref = NULL; 7461 int power_async_delay; 7462 7463 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7464 intel_atomic_dsb_prepare(state, crtc); 7465 7466 intel_atomic_commit_fence_wait(state); 7467 7468 intel_td_flush(display); 7469 7470 intel_atomic_prepare_plane_clear_colors(state); 7471 7472 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7473 intel_fbc_prepare_dirty_rect(state, crtc); 7474 7475 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7476 intel_atomic_dsb_finish(state, crtc); 7477 7478 drm_atomic_helper_wait_for_dependencies(&state->base); 7479 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7480 intel_atomic_global_state_wait_for_dependencies(state); 7481 7482 /* 7483 * During full modesets we write a lot of registers, wait 7484 * for PLLs, etc. Doing that while DC states are enabled 7485 * is not a good idea. 7486 * 7487 * During fastsets and other updates we also need to 7488 * disable DC states due to the following scenario: 7489 * 1. DC5 exit and PSR exit happen 7490 * 2. Some or all _noarm() registers are written 7491 * 3. Due to some long delay PSR is re-entered 7492 * 4. DC5 entry -> DMC saves the already written new 7493 * _noarm() registers and the old not yet written 7494 * _arm() registers 7495 * 5. DC5 exit -> DMC restores a mixture of old and 7496 * new register values and arms the update 7497 * 6. PSR exit -> hardware latches a mixture of old and 7498 * new register values -> corrupted frame, or worse 7499 * 7. New _arm() registers are finally written 7500 * 8. Hardware finally latches a complete set of new 7501 * register values, and subsequent frames will be OK again 7502 * 7503 * Also note that due to the pipe CSC hardware issues on 7504 * SKL/GLK DC states must remain off until the pipe CSC 7505 * state readout has happened. Otherwise we risk corrupting 7506 * the CSC latched register values with the readout (see 7507 * skl_read_csc() and skl_color_commit_noarm()). 7508 */ 7509 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); 7510 7511 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7512 if (intel_crtc_needs_modeset(new_crtc_state) || 7513 intel_crtc_needs_fastset(new_crtc_state)) 7514 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7515 } 7516 7517 intel_commit_modeset_disables(state); 7518 7519 intel_dp_tunnel_atomic_alloc_bw(state); 7520 7521 /* FIXME: Eventually get rid of our crtc->config pointer */ 7522 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7523 crtc->config = new_crtc_state; 7524 7525 /* 7526 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7527 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7528 * index, cdclk/ddiclk frequencies are supposed to be configured before 7529 * the cdclk config is set. 7530 */ 7531 intel_pmdemand_pre_plane_update(state); 7532 7533 if (state->modeset) 7534 drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base); 7535 7536 intel_set_cdclk_pre_plane_update(state); 7537 7538 if (state->modeset) 7539 intel_modeset_verify_disabled(state); 7540 7541 intel_sagv_pre_plane_update(state); 7542 7543 /* Complete the events for pipes that have now been disabled */ 7544 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7545 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7546 7547 /* Complete events for now disable pipes here. */ 7548 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7549 spin_lock_irq(&display->drm->event_lock); 7550 drm_crtc_send_vblank_event(&crtc->base, 7551 new_crtc_state->uapi.event); 7552 spin_unlock_irq(&display->drm->event_lock); 7553 7554 new_crtc_state->uapi.event = NULL; 7555 } 7556 } 7557 7558 intel_encoders_update_prepare(state); 7559 7560 intel_dbuf_pre_plane_update(state); 7561 7562 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7563 if (new_crtc_state->do_async_flip) 7564 intel_crtc_enable_flip_done(state, crtc); 7565 } 7566 7567 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7568 display->modeset.funcs->commit_modeset_enables(state); 7569 7570 intel_display_power_dc3co_compute(state); 7571 7572 /* FIXME probably need to sequence this properly */ 7573 intel_program_dpkgc_latency(state); 7574 7575 if (intel_display_power_dc3co_allowed(display)) 7576 intel_cmtg_program(state); 7577 7578 intel_wait_for_vblank_workers(state); 7579 7580 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7581 * already, but still need the state for the delayed optimization. To 7582 * fix this: 7583 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7584 * - schedule that vblank worker _before_ calling hw_done 7585 * - at the start of commit_tail, cancel it _synchrously 7586 * - switch over to the vblank wait helper in the core after that since 7587 * we don't need out special handling any more. 7588 */ 7589 drm_atomic_helper_wait_for_flip_done(display->drm, &state->base); 7590 7591 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7592 if (new_crtc_state->do_async_flip) 7593 intel_crtc_disable_flip_done(state, crtc); 7594 7595 intel_atomic_dsb_wait_commit(new_crtc_state); 7596 7597 if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb) 7598 intel_vrr_check_push_sent(NULL, new_crtc_state); 7599 7600 if (new_crtc_state->use_flipq) 7601 intel_flipq_disable(new_crtc_state); 7602 } 7603 7604 /* 7605 * Now that the vblank has passed, we can go ahead and program the 7606 * optimal watermarks on platforms that need two-step watermark 7607 * programming. 7608 * 7609 * TODO: Move this (and other cleanup) to an async worker eventually. 7610 */ 7611 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7612 /* 7613 * Gen2 reports pipe underruns whenever all planes are disabled. 7614 * So re-enable underrun reporting after some planes get enabled. 7615 * 7616 * We do this before .optimize_watermarks() so that we have a 7617 * chance of catching underruns with the intermediate watermarks 7618 * vs. the new plane configuration. 7619 */ 7620 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7621 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 7622 7623 intel_optimize_watermarks(state, crtc); 7624 } 7625 7626 intel_dbuf_post_plane_update(state); 7627 7628 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7629 intel_post_plane_update(state, crtc); 7630 7631 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7632 7633 intel_modeset_verify_crtc(state, crtc); 7634 7635 intel_post_plane_update_after_readout(state, crtc); 7636 7637 /* 7638 * DSB cleanup is done in cleanup_work aligning with framebuffer 7639 * cleanup. So copy and reset the dsb structure to sync with 7640 * commit_done and later do dsb cleanup in cleanup_work. 7641 * 7642 * FIXME get rid of this funny new->old swapping 7643 */ 7644 old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color); 7645 old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); 7646 } 7647 7648 /* Underruns don't always raise interrupts, so check manually */ 7649 intel_check_cpu_fifo_underruns(display); 7650 intel_check_pch_fifo_underruns(display); 7651 7652 if (state->modeset) 7653 intel_verify_planes(state); 7654 7655 intel_sagv_post_plane_update(state); 7656 intel_set_cdclk_post_plane_update(state); 7657 intel_pmdemand_post_plane_update(state); 7658 7659 drm_atomic_helper_commit_hw_done(&state->base); 7660 intel_atomic_global_state_commit_done(state); 7661 7662 if (state->modeset) { 7663 /* As one of the primary mmio accessors, KMS has a high 7664 * likelihood of triggering bugs in unclaimed access. After we 7665 * finish modesetting, see if an error has been flagged, and if 7666 * so enable debugging for the next modeset - and hope we catch 7667 * the culprit. 7668 */ 7669 intel_uncore_arm_unclaimed_mmio_detection(uncore); 7670 } 7671 7672 power_async_delay = intel_display_power_select_target_dc_state(state); 7673 7674 intel_display_power_put_async_delay(display, 7675 POWER_DOMAIN_DC_OFF, wakeref, power_async_delay); 7676 7677 intel_display_rpm_put(display, state->wakeref); 7678 7679 /* 7680 * Defer the cleanup of the old state to a separate worker to not 7681 * impede the current task (userspace for blocking modesets) that 7682 * are executed inline. For out-of-line asynchronous modesets/flips, 7683 * deferring to a new worker seems overkill, but we would place a 7684 * schedule point (cond_resched()) here anyway to keep latencies 7685 * down. 7686 */ 7687 INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work); 7688 queue_work(display->wq.cleanup, &state->cleanup_work); 7689 } 7690 7691 static void intel_atomic_commit_work(struct work_struct *work) 7692 { 7693 struct intel_atomic_state *state = 7694 container_of(work, struct intel_atomic_state, base.commit_work); 7695 7696 intel_atomic_commit_tail(state); 7697 } 7698 7699 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7700 { 7701 struct intel_plane_state *old_plane_state, *new_plane_state; 7702 struct intel_plane *plane; 7703 int i; 7704 7705 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7706 new_plane_state, i) 7707 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7708 to_intel_frontbuffer(new_plane_state->hw.fb), 7709 plane->frontbuffer_bit); 7710 } 7711 7712 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock) 7713 { 7714 int ret; 7715 7716 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7717 if (ret) 7718 return ret; 7719 7720 ret = intel_atomic_global_state_setup_commit(state); 7721 if (ret) 7722 return ret; 7723 7724 return 0; 7725 } 7726 7727 static int intel_atomic_swap_state(struct intel_atomic_state *state) 7728 { 7729 int ret; 7730 7731 ret = drm_atomic_helper_swap_state(&state->base, true); 7732 if (ret) 7733 return ret; 7734 7735 intel_atomic_swap_global_state(state); 7736 7737 intel_dpll_swap_state(state); 7738 7739 intel_atomic_track_fbs(state); 7740 7741 return 0; 7742 } 7743 7744 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_commit *_state, 7745 bool nonblock) 7746 { 7747 struct intel_display *display = to_intel_display(dev); 7748 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7749 int ret = 0; 7750 7751 state->wakeref = intel_display_rpm_get(display); 7752 7753 /* 7754 * The intel_legacy_cursor_update() fast path takes care 7755 * of avoiding the vblank waits for simple cursor 7756 * movement and flips. For cursor on/off and size changes, 7757 * we want to perform the vblank waits so that watermark 7758 * updates happen during the correct frames. Gen9+ have 7759 * double buffered watermarks and so shouldn't need this. 7760 * 7761 * Unset state->legacy_cursor_update before the call to 7762 * drm_atomic_helper_setup_commit() because otherwise 7763 * drm_atomic_helper_wait_for_flip_done() is a noop and 7764 * we get FIFO underruns because we didn't wait 7765 * for vblank. 7766 * 7767 * FIXME doing watermarks and fb cleanup from a vblank worker 7768 * (assuming we had any) would solve these problems. 7769 */ 7770 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { 7771 struct intel_crtc_state *new_crtc_state; 7772 struct intel_crtc *crtc; 7773 7774 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7775 if (new_crtc_state->wm.need_postvbl_update || 7776 new_crtc_state->update_wm_post) 7777 state->base.legacy_cursor_update = false; 7778 } 7779 7780 ret = intel_atomic_prepare_commit(state); 7781 if (ret) { 7782 drm_dbg_atomic(display->drm, 7783 "Preparing state failed with %i\n", ret); 7784 intel_display_rpm_put(display, state->wakeref); 7785 return ret; 7786 } 7787 7788 ret = intel_atomic_setup_commit(state, nonblock); 7789 if (!ret) 7790 ret = intel_atomic_swap_state(state); 7791 7792 if (ret) { 7793 drm_atomic_helper_unprepare_planes(dev, &state->base); 7794 intel_display_rpm_put(display, state->wakeref); 7795 return ret; 7796 } 7797 7798 drm_atomic_commit_get(&state->base); 7799 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7800 7801 if (nonblock && state->modeset) { 7802 queue_work(display->wq.modeset, &state->base.commit_work); 7803 } else if (nonblock) { 7804 queue_work(display->wq.flip, &state->base.commit_work); 7805 } else { 7806 if (state->modeset) 7807 flush_workqueue(display->wq.modeset); 7808 intel_atomic_commit_tail(state); 7809 } 7810 7811 return 0; 7812 } 7813 7814 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7815 { 7816 struct intel_display *display = to_intel_display(encoder); 7817 struct intel_encoder *source_encoder; 7818 u32 possible_clones = 0; 7819 7820 for_each_intel_encoder(display->drm, source_encoder) { 7821 if (encoders_cloneable(encoder, source_encoder)) 7822 possible_clones |= drm_encoder_mask(&source_encoder->base); 7823 } 7824 7825 return possible_clones; 7826 } 7827 7828 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7829 { 7830 struct intel_display *display = to_intel_display(encoder); 7831 struct intel_crtc *crtc; 7832 u32 possible_crtcs = 0; 7833 7834 for_each_intel_crtc_in_pipe_mask(display, crtc, encoder->pipe_mask) 7835 possible_crtcs |= drm_crtc_mask(&crtc->base); 7836 7837 return possible_crtcs; 7838 } 7839 7840 static bool ilk_has_edp_a(struct intel_display *display) 7841 { 7842 if (!display->platform.mobile) 7843 return false; 7844 7845 if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0) 7846 return false; 7847 7848 if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7849 return false; 7850 7851 return true; 7852 } 7853 7854 static bool intel_ddi_crt_present(struct intel_display *display) 7855 { 7856 if (DISPLAY_VER(display) >= 9) 7857 return false; 7858 7859 if (display->platform.haswell_ult || display->platform.broadwell_ult) 7860 return false; 7861 7862 if (HAS_PCH_LPT_H(display) && 7863 intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7864 return false; 7865 7866 /* DDI E can't be used if DDI A requires 4 lanes */ 7867 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7868 return false; 7869 7870 if (!display->vbt.int_crt_support) 7871 return false; 7872 7873 return true; 7874 } 7875 7876 bool assert_port_valid(struct intel_display *display, enum port port) 7877 { 7878 return !drm_WARN(display->drm, 7879 !(port >= 0 && DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)), 7880 "Platform does not support port %c\n", port_name(port)); 7881 } 7882 7883 void intel_setup_outputs(struct intel_display *display) 7884 { 7885 struct intel_encoder *encoder; 7886 bool dpd_is_edp = false; 7887 7888 intel_pps_unlock_regs_wa(display); 7889 7890 if (!HAS_DISPLAY(display)) 7891 return; 7892 7893 if (HAS_DDI(display)) { 7894 if (intel_ddi_crt_present(display)) 7895 intel_crt_init(display); 7896 7897 intel_bios_for_each_encoder(display, intel_ddi_init); 7898 7899 if (display->platform.geminilake || display->platform.broxton) 7900 vlv_dsi_init(display); 7901 } else if (HAS_PCH_SPLIT(display)) { 7902 int found; 7903 7904 /* 7905 * intel_edp_init_connector() depends on this completing first, 7906 * to prevent the registration of both eDP and LVDS and the 7907 * incorrect sharing of the PPS. 7908 */ 7909 intel_lvds_init(display); 7910 intel_crt_init(display); 7911 7912 dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); 7913 7914 if (ilk_has_edp_a(display)) 7915 g4x_dp_init(display, DP_A, PORT_A); 7916 7917 if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) { 7918 /* PCH SDVOB multiplex with HDMIB */ 7919 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); 7920 if (!found) 7921 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); 7922 if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED)) 7923 g4x_dp_init(display, PCH_DP_B, PORT_B); 7924 } 7925 7926 if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED) 7927 g4x_hdmi_init(display, PCH_HDMIC, PORT_C); 7928 7929 if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED) 7930 g4x_hdmi_init(display, PCH_HDMID, PORT_D); 7931 7932 if (intel_de_read(display, PCH_DP_C) & DP_DETECTED) 7933 g4x_dp_init(display, PCH_DP_C, PORT_C); 7934 7935 if (intel_de_read(display, PCH_DP_D) & DP_DETECTED) 7936 g4x_dp_init(display, PCH_DP_D, PORT_D); 7937 } else if (display->platform.valleyview || display->platform.cherryview) { 7938 bool has_edp, has_port; 7939 7940 if (display->platform.valleyview && display->vbt.int_crt_support) 7941 intel_crt_init(display); 7942 7943 /* 7944 * The DP_DETECTED bit is the latched state of the DDC 7945 * SDA pin at boot. However since eDP doesn't require DDC 7946 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7947 * eDP ports may have been muxed to an alternate function. 7948 * Thus we can't rely on the DP_DETECTED bit alone to detect 7949 * eDP ports. Consult the VBT as well as DP_DETECTED to 7950 * detect eDP ports. 7951 * 7952 * Sadly the straps seem to be missing sometimes even for HDMI 7953 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7954 * and VBT for the presence of the port. Additionally we can't 7955 * trust the port type the VBT declares as we've seen at least 7956 * HDMI ports that the VBT claim are DP or eDP. 7957 */ 7958 has_edp = intel_dp_is_port_edp(display, PORT_B); 7959 has_port = intel_bios_is_port_present(display, PORT_B); 7960 if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port) 7961 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); 7962 if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7963 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); 7964 7965 has_edp = intel_dp_is_port_edp(display, PORT_C); 7966 has_port = intel_bios_is_port_present(display, PORT_C); 7967 if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port) 7968 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); 7969 if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7970 g4x_hdmi_init(display, VLV_HDMIC, PORT_C); 7971 7972 if (display->platform.cherryview) { 7973 /* 7974 * eDP not supported on port D, 7975 * so no need to worry about it 7976 */ 7977 has_port = intel_bios_is_port_present(display, PORT_D); 7978 if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port) 7979 g4x_dp_init(display, CHV_DP_D, PORT_D); 7980 if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port) 7981 g4x_hdmi_init(display, CHV_HDMID, PORT_D); 7982 } 7983 7984 vlv_dsi_init(display); 7985 } else if (display->platform.pineview) { 7986 intel_lvds_init(display); 7987 intel_crt_init(display); 7988 } else if (IS_DISPLAY_VER(display, 3, 4)) { 7989 bool found = false; 7990 7991 if (display->platform.mobile) 7992 intel_lvds_init(display); 7993 7994 intel_crt_init(display); 7995 7996 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 7997 drm_dbg_kms(display->drm, "probing SDVOB\n"); 7998 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); 7999 if (!found && display->platform.g4x) { 8000 drm_dbg_kms(display->drm, 8001 "probing HDMI on SDVOB\n"); 8002 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); 8003 } 8004 8005 if (!found && display->platform.g4x) 8006 g4x_dp_init(display, DP_B, PORT_B); 8007 } 8008 8009 /* Before G4X SDVOC doesn't have its own detect register */ 8010 8011 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 8012 drm_dbg_kms(display->drm, "probing SDVOC\n"); 8013 found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); 8014 } 8015 8016 if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) { 8017 8018 if (display->platform.g4x) { 8019 drm_dbg_kms(display->drm, 8020 "probing HDMI on SDVOC\n"); 8021 g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); 8022 } 8023 if (display->platform.g4x) 8024 g4x_dp_init(display, DP_C, PORT_C); 8025 } 8026 8027 if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED)) 8028 g4x_dp_init(display, DP_D, PORT_D); 8029 8030 if (SUPPORTS_TV(display)) 8031 intel_tv_init(display); 8032 } else if (DISPLAY_VER(display) == 2) { 8033 if (display->platform.i85x) 8034 intel_lvds_init(display); 8035 8036 intel_crt_init(display); 8037 intel_dvo_init(display); 8038 } 8039 8040 for_each_intel_encoder(display->drm, encoder) { 8041 encoder->base.possible_crtcs = 8042 intel_encoder_possible_crtcs(encoder); 8043 encoder->base.possible_clones = 8044 intel_encoder_possible_clones(encoder); 8045 } 8046 8047 intel_init_pch_refclk(display); 8048 8049 drm_helper_move_panel_connectors_to_head(display->drm); 8050 } 8051 8052 int intel_max_uncompressed_dotclock(struct intel_display *display) 8053 { 8054 int max_dotclock = display->cdclk.max_dotclk_freq; 8055 int limit = max_dotclock; 8056 8057 if (DISPLAY_VERx100(display) == 3002) 8058 limit = 937500; 8059 else if (DISPLAY_VER(display) >= 30) 8060 limit = 1350000; 8061 /* 8062 * Note: For other platforms though there are limits given 8063 * in the Bspec, however the limit is intentionally not 8064 * enforced to avoid regressions, unless real issues are 8065 * observed. 8066 */ 8067 8068 return min(max_dotclock, limit); 8069 } 8070 8071 static int max_dotclock(struct intel_display *display) 8072 { 8073 int max_dotclock = display->cdclk.max_dotclk_freq; 8074 8075 if (HAS_ULTRAJOINER(display)) 8076 max_dotclock *= 4; 8077 else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display)) 8078 max_dotclock *= 2; 8079 8080 return max_dotclock; 8081 } 8082 8083 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 8084 const struct drm_display_mode *mode) 8085 { 8086 struct intel_display *display = to_intel_display(dev); 8087 int hdisplay_max, htotal_max; 8088 int vdisplay_max, vtotal_max; 8089 8090 /* 8091 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8092 * of DBLSCAN modes to the output's mode list when they detect 8093 * the scaling mode property on the connector. And they don't 8094 * ask the kernel to validate those modes in any way until 8095 * modeset time at which point the client gets a protocol error. 8096 * So in order to not upset those clients we silently ignore the 8097 * DBLSCAN flag on such connectors. For other connectors we will 8098 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8099 * And we always reject DBLSCAN modes in connector->mode_valid() 8100 * as we never want such modes on the connector's mode list. 8101 */ 8102 8103 if (mode->vscan > 1) 8104 return MODE_NO_VSCAN; 8105 8106 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8107 return MODE_H_ILLEGAL; 8108 8109 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8110 DRM_MODE_FLAG_NCSYNC | 8111 DRM_MODE_FLAG_PCSYNC)) 8112 return MODE_HSYNC; 8113 8114 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8115 DRM_MODE_FLAG_PIXMUX | 8116 DRM_MODE_FLAG_CLKDIV2)) 8117 return MODE_BAD; 8118 8119 /* 8120 * Reject clearly excessive dotclocks early to 8121 * avoid having to worry about huge integers later. 8122 */ 8123 if (mode->clock > max_dotclock(display)) 8124 return MODE_CLOCK_HIGH; 8125 8126 /* Transcoder timing limits */ 8127 if (DISPLAY_VER(display) >= 11) { 8128 hdisplay_max = 16384; 8129 vdisplay_max = 8192; 8130 htotal_max = 16384; 8131 vtotal_max = 8192; 8132 } else if (DISPLAY_VER(display) >= 9 || 8133 display->platform.broadwell || display->platform.haswell) { 8134 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8135 vdisplay_max = 4096; 8136 htotal_max = 8192; 8137 vtotal_max = 8192; 8138 } else if (DISPLAY_VER(display) >= 3) { 8139 hdisplay_max = 4096; 8140 vdisplay_max = 4096; 8141 htotal_max = 8192; 8142 vtotal_max = 8192; 8143 } else { 8144 hdisplay_max = 2048; 8145 vdisplay_max = 2048; 8146 htotal_max = 4096; 8147 vtotal_max = 4096; 8148 } 8149 8150 if (mode->hdisplay > hdisplay_max || 8151 mode->hsync_start > htotal_max || 8152 mode->hsync_end > htotal_max || 8153 mode->htotal > htotal_max) 8154 return MODE_H_ILLEGAL; 8155 8156 if (mode->vdisplay > vdisplay_max || 8157 mode->vsync_start > vtotal_max || 8158 mode->vsync_end > vtotal_max || 8159 mode->vtotal > vtotal_max) 8160 return MODE_V_ILLEGAL; 8161 8162 /* 8163 * WM_LINETIME only goes up to (almost) 64 usec, and also 8164 * knowing that the linetime is always bounded will ease the 8165 * mind during various calculations. 8166 */ 8167 if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64) 8168 return MODE_H_ILLEGAL; 8169 8170 return MODE_OK; 8171 } 8172 8173 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display, 8174 const struct drm_display_mode *mode) 8175 { 8176 /* 8177 * Additional transcoder timing limits, 8178 * excluding BXT/GLK DSI transcoders. 8179 */ 8180 if (DISPLAY_VER(display) >= 5) { 8181 if (mode->hdisplay < 64 || 8182 mode->htotal - mode->hdisplay < 32) 8183 return MODE_H_ILLEGAL; 8184 8185 if (mode->vtotal - mode->vdisplay < 5) 8186 return MODE_V_ILLEGAL; 8187 } else { 8188 if (mode->htotal - mode->hdisplay < 32) 8189 return MODE_H_ILLEGAL; 8190 8191 if (mode->vtotal - mode->vdisplay < 3) 8192 return MODE_V_ILLEGAL; 8193 } 8194 8195 /* 8196 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8197 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8198 */ 8199 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && 8200 mode->hsync_start == mode->hdisplay) 8201 return MODE_H_ILLEGAL; 8202 8203 return MODE_OK; 8204 } 8205 8206 enum drm_mode_status 8207 intel_mode_valid_max_plane_size(struct intel_display *display, 8208 const struct drm_display_mode *mode, 8209 int num_joined_pipes) 8210 { 8211 int plane_width_max, plane_height_max; 8212 8213 /* 8214 * intel_mode_valid() should be 8215 * sufficient on older platforms. 8216 */ 8217 if (DISPLAY_VER(display) < 9) 8218 return MODE_OK; 8219 8220 /* 8221 * Most people will probably want a fullscreen 8222 * plane so let's not advertize modes that are 8223 * too big for that. 8224 */ 8225 if (DISPLAY_VER(display) >= 30) { 8226 plane_width_max = 6144 * num_joined_pipes; 8227 plane_height_max = 4800; 8228 } else if (DISPLAY_VER(display) >= 11) { 8229 plane_width_max = 5120 * num_joined_pipes; 8230 plane_height_max = 4320; 8231 } else { 8232 plane_width_max = 5120; 8233 plane_height_max = 4096; 8234 } 8235 8236 if (mode->hdisplay > plane_width_max) 8237 return MODE_H_ILLEGAL; 8238 8239 if (mode->vdisplay > plane_height_max) 8240 return MODE_V_ILLEGAL; 8241 8242 return MODE_OK; 8243 } 8244 8245 static const struct intel_modeset_funcs skl_display_funcs = { 8246 .get_pipe_config = hsw_get_pipe_config, 8247 .crtc_enable = hsw_crtc_enable, 8248 .crtc_disable = hsw_crtc_disable, 8249 .commit_modeset_enables = skl_commit_modeset_enables, 8250 .get_initial_plane_config = skl_get_initial_plane_config, 8251 .fixup_initial_plane_config = skl_fixup_initial_plane_config, 8252 }; 8253 8254 static const struct intel_modeset_funcs ddi_display_funcs = { 8255 .get_pipe_config = hsw_get_pipe_config, 8256 .crtc_enable = hsw_crtc_enable, 8257 .crtc_disable = hsw_crtc_disable, 8258 .commit_modeset_enables = intel_commit_modeset_enables, 8259 .get_initial_plane_config = i9xx_get_initial_plane_config, 8260 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8261 }; 8262 8263 static const struct intel_modeset_funcs pch_split_display_funcs = { 8264 .get_pipe_config = ilk_get_pipe_config, 8265 .crtc_enable = ilk_crtc_enable, 8266 .crtc_disable = ilk_crtc_disable, 8267 .commit_modeset_enables = intel_commit_modeset_enables, 8268 .get_initial_plane_config = i9xx_get_initial_plane_config, 8269 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8270 }; 8271 8272 static const struct intel_modeset_funcs vlv_display_funcs = { 8273 .get_pipe_config = i9xx_get_pipe_config, 8274 .crtc_enable = valleyview_crtc_enable, 8275 .crtc_disable = i9xx_crtc_disable, 8276 .commit_modeset_enables = intel_commit_modeset_enables, 8277 .get_initial_plane_config = i9xx_get_initial_plane_config, 8278 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8279 }; 8280 8281 static const struct intel_modeset_funcs i9xx_display_funcs = { 8282 .get_pipe_config = i9xx_get_pipe_config, 8283 .crtc_enable = i9xx_crtc_enable, 8284 .crtc_disable = i9xx_crtc_disable, 8285 .commit_modeset_enables = intel_commit_modeset_enables, 8286 .get_initial_plane_config = i9xx_get_initial_plane_config, 8287 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8288 }; 8289 8290 /** 8291 * intel_init_display_hooks - initialize the display modesetting hooks 8292 * @display: display device private 8293 */ 8294 void intel_init_display_hooks(struct intel_display *display) 8295 { 8296 if (DISPLAY_VER(display) >= 9) { 8297 display->modeset.funcs = &skl_display_funcs; 8298 } else if (HAS_DDI(display)) { 8299 display->modeset.funcs = &ddi_display_funcs; 8300 } else if (HAS_PCH_SPLIT(display)) { 8301 display->modeset.funcs = &pch_split_display_funcs; 8302 } else if (display->platform.cherryview || 8303 display->platform.valleyview) { 8304 display->modeset.funcs = &vlv_display_funcs; 8305 } else { 8306 display->modeset.funcs = &i9xx_display_funcs; 8307 } 8308 } 8309 8310 int intel_initial_commit(struct intel_display *display) 8311 { 8312 struct drm_atomic_commit *state = NULL; 8313 struct drm_modeset_acquire_ctx ctx; 8314 struct intel_crtc *crtc; 8315 int ret = 0; 8316 8317 state = drm_atomic_commit_alloc(display->drm); 8318 if (!state) 8319 return -ENOMEM; 8320 8321 drm_modeset_acquire_init(&ctx, 0); 8322 8323 state->acquire_ctx = &ctx; 8324 to_intel_atomic_state(state)->internal = true; 8325 8326 retry: 8327 for_each_intel_crtc(display, crtc) { 8328 struct intel_crtc_state *crtc_state = 8329 intel_atomic_get_crtc_state(state, crtc); 8330 8331 if (IS_ERR(crtc_state)) { 8332 ret = PTR_ERR(crtc_state); 8333 goto out; 8334 } 8335 8336 if (!crtc_state->hw.active) 8337 crtc_state->inherited = false; 8338 8339 if (crtc_state->hw.active) { 8340 struct intel_encoder *encoder; 8341 8342 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8343 if (ret) 8344 goto out; 8345 8346 /* 8347 * FIXME hack to force a LUT update to avoid the 8348 * plane update forcing the pipe gamma on without 8349 * having a proper LUT loaded. Remove once we 8350 * have readout for pipe gamma enable. 8351 */ 8352 crtc_state->uapi.color_mgmt_changed = true; 8353 8354 for_each_intel_encoder_mask(display->drm, encoder, 8355 crtc_state->uapi.encoder_mask) { 8356 if (encoder->initial_fastset_check && 8357 !encoder->initial_fastset_check(encoder, crtc_state)) { 8358 ret = drm_atomic_add_affected_connectors(state, 8359 &crtc->base); 8360 if (ret) 8361 goto out; 8362 } 8363 } 8364 } 8365 } 8366 8367 ret = drm_atomic_commit(state); 8368 8369 out: 8370 if (ret == -EDEADLK) { 8371 drm_atomic_commit_clear(state); 8372 drm_modeset_backoff(&ctx); 8373 goto retry; 8374 } 8375 8376 drm_atomic_commit_put(state); 8377 8378 drm_modeset_drop_locks(&ctx); 8379 drm_modeset_acquire_fini(&ctx); 8380 8381 return ret; 8382 } 8383 8384 void i830_enable_pipe(struct intel_display *display, enum pipe pipe) 8385 { 8386 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8387 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8388 /* 640x480@60Hz, ~25175 kHz */ 8389 struct dpll clock = { 8390 .m1 = 18, 8391 .m2 = 7, 8392 .p1 = 13, 8393 .p2 = 4, 8394 .n = 2, 8395 }; 8396 u32 dpll, fp; 8397 int i; 8398 8399 drm_WARN_ON(display->drm, 8400 i9xx_calc_dpll_params(48000, &clock) != 25154); 8401 8402 drm_dbg_kms(display->drm, 8403 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8404 pipe_name(pipe), clock.vco, clock.dot); 8405 8406 fp = i9xx_dpll_compute_fp(&clock); 8407 dpll = DPLL_DVO_2X_MODE | 8408 DPLL_VGA_MODE_DIS | 8409 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8410 PLL_P2_DIVIDE_BY_4 | 8411 PLL_REF_INPUT_DREFCLK | 8412 DPLL_VCO_ENABLE; 8413 8414 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), 8415 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8416 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), 8417 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8418 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), 8419 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8420 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 8421 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8422 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 8423 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8424 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), 8425 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8426 intel_de_write(display, PIPESRC(display, pipe), 8427 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8428 8429 intel_de_write(display, FP0(pipe), fp); 8430 intel_de_write(display, FP1(pipe), fp); 8431 8432 /* 8433 * Apparently we need to have VGA mode enabled prior to changing 8434 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8435 * dividers, even though the register value does change. 8436 */ 8437 intel_de_write(display, DPLL(display, pipe), 8438 dpll & ~DPLL_VGA_MODE_DIS); 8439 intel_de_write(display, DPLL(display, pipe), dpll); 8440 8441 /* Wait for the clocks to stabilize. */ 8442 intel_de_posting_read(display, DPLL(display, pipe)); 8443 udelay(150); 8444 8445 /* The pixel multiplier can only be updated once the 8446 * DPLL is enabled and the clocks are stable. 8447 * 8448 * So write it again. 8449 */ 8450 intel_de_write(display, DPLL(display, pipe), dpll); 8451 8452 /* We do this three times for luck */ 8453 for (i = 0; i < 3 ; i++) { 8454 intel_de_write(display, DPLL(display, pipe), dpll); 8455 intel_de_posting_read(display, DPLL(display, pipe)); 8456 udelay(150); /* wait for warmup */ 8457 } 8458 8459 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); 8460 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8461 8462 intel_wait_for_pipe_scanline_moving(crtc); 8463 } 8464 8465 void i830_disable_pipe(struct intel_display *display, enum pipe pipe) 8466 { 8467 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8468 8469 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", 8470 pipe_name(pipe)); 8471 8472 drm_WARN_ON(display->drm, 8473 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); 8474 drm_WARN_ON(display->drm, 8475 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); 8476 drm_WARN_ON(display->drm, 8477 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); 8478 drm_WARN_ON(display->drm, 8479 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); 8480 drm_WARN_ON(display->drm, 8481 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); 8482 8483 intel_de_write(display, TRANSCONF(display, pipe), 0); 8484 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8485 8486 intel_wait_for_pipe_scanline_stopped(crtc); 8487 8488 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); 8489 intel_de_posting_read(display, DPLL(display, pipe)); 8490 } 8491 8492 bool intel_scanout_needs_vtd_wa(struct intel_display *display) 8493 { 8494 return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display); 8495 } 8496