1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_tunnel.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_damage_helper.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_fixed.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_print.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 #include <drm/drm_vblank.h> 48 #include <drm/intel/step.h> 49 50 #include "g4x_dp.h" 51 #include "g4x_hdmi.h" 52 #include "hsw_ips.h" 53 #include "i915_config.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_plane_regs.h" 56 #include "i9xx_wm.h" 57 #include "intel_alpm.h" 58 #include "intel_atomic.h" 59 #include "intel_audio.h" 60 #include "intel_bo.h" 61 #include "intel_bw.h" 62 #include "intel_cdclk.h" 63 #include "intel_clock_gating.h" 64 #include "intel_cmtg.h" 65 #include "intel_color.h" 66 #include "intel_crt.h" 67 #include "intel_crtc.h" 68 #include "intel_crtc_state_dump.h" 69 #include "intel_cursor.h" 70 #include "intel_cursor_regs.h" 71 #include "intel_cx0_phy.h" 72 #include "intel_ddi.h" 73 #include "intel_de.h" 74 #include "intel_display_driver.h" 75 #include "intel_display_power.h" 76 #include "intel_display_regs.h" 77 #include "intel_display_rpm.h" 78 #include "intel_display_types.h" 79 #include "intel_display_utils.h" 80 #include "intel_display_wa.h" 81 #include "intel_dmc.h" 82 #include "intel_dp.h" 83 #include "intel_dp_link_training.h" 84 #include "intel_dp_mst.h" 85 #include "intel_dp_tunnel.h" 86 #include "intel_dpll.h" 87 #include "intel_dpll_mgr.h" 88 #include "intel_dpt.h" 89 #include "intel_drrs.h" 90 #include "intel_dsb.h" 91 #include "intel_dsi.h" 92 #include "intel_dvo.h" 93 #include "intel_fb.h" 94 #include "intel_fbc.h" 95 #include "intel_fdi.h" 96 #include "intel_fifo_underrun.h" 97 #include "intel_flipq.h" 98 #include "intel_frontbuffer.h" 99 #include "intel_hdmi.h" 100 #include "intel_hotplug.h" 101 #include "intel_initial_plane.h" 102 #include "intel_link_bw.h" 103 #include "intel_lt_phy.h" 104 #include "intel_lvds.h" 105 #include "intel_lvds_regs.h" 106 #include "intel_modeset_setup.h" 107 #include "intel_modeset_verify.h" 108 #include "intel_overlay.h" 109 #include "intel_panel.h" 110 #include "intel_pch_display.h" 111 #include "intel_pch_refclk.h" 112 #include "intel_pfit.h" 113 #include "intel_pipe_crc.h" 114 #include "intel_plane.h" 115 #include "intel_pmdemand.h" 116 #include "intel_pps.h" 117 #include "intel_psr.h" 118 #include "intel_psr_regs.h" 119 #include "intel_sdvo.h" 120 #include "intel_snps_phy.h" 121 #include "intel_tc.h" 122 #include "intel_tdf.h" 123 #include "intel_tv.h" 124 #include "intel_vblank.h" 125 #include "intel_vdsc.h" 126 #include "intel_vdsc_regs.h" 127 #include "intel_vga.h" 128 #include "intel_vrr.h" 129 #include "intel_wm.h" 130 #include "skl_scaler.h" 131 #include "skl_universal_plane.h" 132 #include "skl_watermark.h" 133 #include "vlv_dsi.h" 134 #include "vlv_dsi_pll.h" 135 #include "vlv_dsi_regs.h" 136 137 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 138 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 139 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 140 const struct intel_crtc_state *crtc_state); 141 142 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 143 { 144 return (crtc_state->active_planes & 145 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 146 } 147 148 /* WA Display #0827: Gen9:all */ 149 static void 150 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) 151 { 152 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 153 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 154 enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0); 155 } 156 157 /* Wa_2006604312:icl,ehl */ 158 static void 159 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, 160 bool enable) 161 { 162 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 163 DPFR_GATING_DIS, 164 enable ? DPFR_GATING_DIS : 0); 165 } 166 167 /* Wa_1604331009:icl,jsl,ehl */ 168 static void 169 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, 170 bool enable) 171 { 172 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 173 CURSOR_GATING_DIS, 174 enable ? CURSOR_GATING_DIS : 0); 175 } 176 177 static bool 178 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 179 { 180 return crtc_state->master_transcoder != INVALID_TRANSCODER; 181 } 182 183 bool 184 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 185 { 186 return crtc_state->sync_mode_slaves_mask != 0; 187 } 188 189 bool 190 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 191 { 192 return is_trans_port_sync_master(crtc_state) || 193 is_trans_port_sync_slave(crtc_state); 194 } 195 196 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) 197 { 198 return ffs(crtc_state->joiner_pipes) - 1; 199 } 200 201 /* 202 * The following helper functions, despite being named for bigjoiner, 203 * are applicable to both bigjoiner and uncompressed joiner configurations. 204 */ 205 static bool is_bigjoiner(const struct intel_crtc_state *crtc_state) 206 { 207 return hweight8(crtc_state->joiner_pipes) >= 2; 208 } 209 210 static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 211 { 212 if (!is_bigjoiner(crtc_state)) 213 return 0; 214 215 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state)); 216 } 217 218 static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 219 { 220 if (!is_bigjoiner(crtc_state)) 221 return 0; 222 223 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state)); 224 } 225 226 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state) 227 { 228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 229 230 if (!is_bigjoiner(crtc_state)) 231 return false; 232 233 return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state); 234 } 235 236 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state) 237 { 238 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 239 240 if (!is_bigjoiner(crtc_state)) 241 return false; 242 243 return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state); 244 } 245 246 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state) 247 { 248 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 249 250 if (!is_bigjoiner(crtc_state)) 251 return BIT(crtc->pipe); 252 253 return bigjoiner_primary_pipes(crtc_state); 254 } 255 256 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state) 257 { 258 return bigjoiner_secondary_pipes(crtc_state); 259 } 260 261 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state) 262 { 263 return intel_crtc_num_joined_pipes(crtc_state) >= 4; 264 } 265 266 static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 267 { 268 if (!intel_crtc_is_ultrajoiner(crtc_state)) 269 return 0; 270 271 return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state)); 272 } 273 274 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state) 275 { 276 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 277 278 return intel_crtc_is_ultrajoiner(crtc_state) && 279 BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state); 280 } 281 282 /* 283 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or 284 * any other logic, so lets just add helper function to 285 * at least hide this hassle.. 286 */ 287 static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state) 288 { 289 if (!intel_crtc_is_ultrajoiner(crtc_state)) 290 return 0; 291 292 return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state)); 293 } 294 295 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state) 296 { 297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 298 299 return intel_crtc_is_ultrajoiner(crtc_state) && 300 BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state); 301 } 302 303 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 304 { 305 if (crtc_state->joiner_pipes) 306 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); 307 else 308 return 0; 309 } 310 311 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) 312 { 313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 314 315 return crtc_state->joiner_pipes && 316 crtc->pipe != joiner_primary_pipe(crtc_state); 317 } 318 319 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) 320 { 321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 322 323 return crtc_state->joiner_pipes && 324 crtc->pipe == joiner_primary_pipe(crtc_state); 325 } 326 327 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state) 328 { 329 return hweight8(intel_crtc_joined_pipe_mask(crtc_state)); 330 } 331 332 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) 333 { 334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 335 336 return BIT(crtc->pipe) | crtc_state->joiner_pipes; 337 } 338 339 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) 340 { 341 struct intel_display *display = to_intel_display(crtc_state); 342 343 if (intel_crtc_is_joiner_secondary(crtc_state)) 344 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); 345 else 346 return to_intel_crtc(crtc_state->uapi.crtc); 347 } 348 349 static void 350 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 351 { 352 struct intel_display *display = to_intel_display(old_crtc_state); 353 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 354 355 if (DISPLAY_VER(display) >= 4) { 356 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 357 358 /* Wait for the Pipe State to go off */ 359 if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder), 360 TRANSCONF_STATE_ENABLE, 100)) 361 drm_WARN(display->drm, 1, "pipe_off wait timed out\n"); 362 } else { 363 intel_wait_for_pipe_scanline_stopped(crtc); 364 } 365 } 366 367 void assert_transcoder(struct intel_display *display, 368 enum transcoder cpu_transcoder, bool state) 369 { 370 bool cur_state; 371 enum intel_display_power_domain power_domain; 372 struct ref_tracker *wakeref; 373 374 /* we keep both pipes enabled on 830 */ 375 if (display->platform.i830) 376 state = true; 377 378 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 379 wakeref = intel_display_power_get_if_enabled(display, power_domain); 380 if (wakeref) { 381 u32 val = intel_de_read(display, 382 TRANSCONF(display, cpu_transcoder)); 383 cur_state = !!(val & TRANSCONF_ENABLE); 384 385 intel_display_power_put(display, power_domain, wakeref); 386 } else { 387 cur_state = false; 388 } 389 390 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 391 "transcoder %s assertion failure (expected %s, current %s)\n", 392 transcoder_name(cpu_transcoder), str_on_off(state), 393 str_on_off(cur_state)); 394 } 395 396 static void assert_plane(struct intel_plane *plane, bool state) 397 { 398 struct intel_display *display = to_intel_display(plane->base.dev); 399 enum pipe pipe; 400 bool cur_state; 401 402 cur_state = plane->get_hw_state(plane, &pipe); 403 404 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 405 "%s assertion failure (expected %s, current %s)\n", 406 plane->base.name, str_on_off(state), 407 str_on_off(cur_state)); 408 } 409 410 #define assert_plane_enabled(p) assert_plane(p, true) 411 #define assert_plane_disabled(p) assert_plane(p, false) 412 413 static void assert_planes_disabled(struct intel_crtc *crtc) 414 { 415 struct intel_display *display = to_intel_display(crtc); 416 struct intel_plane *plane; 417 418 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 419 assert_plane_disabled(plane); 420 } 421 422 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 423 { 424 struct intel_display *display = to_intel_display(new_crtc_state); 425 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 426 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 427 enum pipe pipe = crtc->pipe; 428 u32 val; 429 430 drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe)); 431 432 assert_planes_disabled(crtc); 433 434 /* 435 * A pipe without a PLL won't actually be able to drive bits from 436 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 437 * need the check. 438 */ 439 if (HAS_GMCH(display)) { 440 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 441 assert_dsi_pll_enabled(display); 442 else 443 assert_pll_enabled(display, pipe); 444 } else { 445 if (new_crtc_state->has_pch_encoder) { 446 /* if driving the PCH, we need FDI enabled */ 447 assert_fdi_rx_pll_enabled(display, 448 intel_crtc_pch_transcoder(crtc)); 449 assert_fdi_tx_pll_enabled(display, 450 (enum pipe) cpu_transcoder); 451 } 452 /* FIXME: assert CPU port conditions for SNB+ */ 453 } 454 455 /* Wa_22012358565:adl-p */ 456 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012358565)) 457 intel_de_rmw(display, PIPE_ARB_CTL(display, pipe), 458 0, PIPE_ARB_USE_PROG_SLOTS); 459 460 if (DISPLAY_VER(display) >= 14) { 461 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; 462 u32 set = 0; 463 464 if (DISPLAY_VER(display) == 14) 465 set |= DP_FEC_BS_JITTER_WA; 466 467 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 468 clear, set); 469 } 470 471 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 472 if (val & TRANSCONF_ENABLE) { 473 /* we keep both pipes enabled on 830 */ 474 drm_WARN_ON(display->drm, !display->platform.i830); 475 return; 476 } 477 478 /* Wa_1409098942:adlp+ */ 479 if (DISPLAY_VER(display) >= 13 && 480 new_crtc_state->dsc.compression_enable) { 481 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 482 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, 483 TRANSCONF_PIXEL_COUNT_SCALING_X4); 484 } 485 486 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 487 val | TRANSCONF_ENABLE); 488 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 489 490 /* 491 * Until the pipe starts PIPEDSL reads will return a stale value, 492 * which causes an apparent vblank timestamp jump when PIPEDSL 493 * resets to its proper value. That also messes up the frame count 494 * when it's derived from the timestamps. So let's wait for the 495 * pipe to start properly before we call drm_crtc_vblank_on() 496 */ 497 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 498 intel_wait_for_pipe_scanline_moving(crtc); 499 } 500 501 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 502 { 503 struct intel_display *display = to_intel_display(old_crtc_state); 504 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 505 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 506 enum pipe pipe = crtc->pipe; 507 u32 val; 508 509 drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe)); 510 511 /* 512 * Make sure planes won't keep trying to pump pixels to us, 513 * or we might hang the display. 514 */ 515 assert_planes_disabled(crtc); 516 517 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 518 if ((val & TRANSCONF_ENABLE) == 0) 519 return; 520 521 /* 522 * Double wide has implications for planes 523 * so best keep it disabled when not needed. 524 */ 525 if (old_crtc_state->double_wide) 526 val &= ~TRANSCONF_DOUBLE_WIDE; 527 528 /* Don't disable pipe or pipe PLLs if needed */ 529 if (!display->platform.i830) 530 val &= ~TRANSCONF_ENABLE; 531 532 /* Wa_1409098942:adlp+ */ 533 if (DISPLAY_VER(display) >= 13 && 534 old_crtc_state->dsc.compression_enable) 535 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 536 537 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 538 539 if (DISPLAY_VER(display) >= 12) 540 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 541 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 542 543 if ((val & TRANSCONF_ENABLE) == 0) 544 intel_wait_for_pipe_off(old_crtc_state); 545 } 546 547 u32 intel_plane_fb_max_stride(struct intel_display *display, 548 const struct drm_format_info *info, 549 u64 modifier) 550 { 551 struct intel_crtc *crtc; 552 struct intel_plane *plane; 553 554 /* 555 * We assume the primary plane for pipe A has 556 * the highest stride limits of them all, 557 * if in case pipe A is disabled, use the first pipe from pipe_mask. 558 */ 559 crtc = intel_first_crtc(display); 560 if (!crtc) 561 return 0; 562 563 plane = to_intel_plane(crtc->base.primary); 564 565 return plane->max_stride(plane, info, modifier, 566 DRM_MODE_ROTATE_0); 567 } 568 569 u32 intel_dumb_fb_max_stride(struct drm_device *drm, 570 u32 pixel_format, u64 modifier) 571 { 572 struct intel_display *display = to_intel_display(drm); 573 574 if (!HAS_DISPLAY(display)) 575 return 0; 576 577 return intel_plane_fb_max_stride(display, 578 drm_get_format_info(drm, pixel_format, modifier), 579 modifier); 580 } 581 582 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 583 struct intel_plane_state *plane_state, 584 bool visible) 585 { 586 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 587 588 plane_state->uapi.visible = visible; 589 590 if (visible) 591 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 592 else 593 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 594 } 595 596 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 597 { 598 struct intel_display *display = to_intel_display(crtc_state); 599 struct drm_plane *plane; 600 601 /* 602 * Active_planes aliases if multiple "primary" or cursor planes 603 * have been used on the same (or wrong) pipe. plane_mask uses 604 * unique ids, hence we can use that to reconstruct active_planes. 605 */ 606 crtc_state->enabled_planes = 0; 607 crtc_state->active_planes = 0; 608 609 drm_for_each_plane_mask(plane, display->drm, 610 crtc_state->uapi.plane_mask) { 611 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 612 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 613 } 614 } 615 616 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 617 struct intel_plane *plane) 618 { 619 struct intel_display *display = to_intel_display(crtc); 620 struct intel_crtc_state *crtc_state = 621 to_intel_crtc_state(crtc->base.state); 622 struct intel_plane_state *plane_state = 623 to_intel_plane_state(plane->base.state); 624 625 drm_dbg_kms(display->drm, 626 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 627 plane->base.base.id, plane->base.name, 628 crtc->base.base.id, crtc->base.name); 629 630 intel_plane_set_invisible(crtc_state, plane_state); 631 intel_set_plane_visible(crtc_state, plane_state, false); 632 intel_plane_fixup_bitmasks(crtc_state); 633 634 skl_wm_plane_disable_noatomic(crtc, plane); 635 636 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 637 hsw_ips_disable(crtc_state)) { 638 crtc_state->ips_enabled = false; 639 intel_initial_plane_vblank_wait(crtc); 640 } 641 642 /* 643 * Vblank time updates from the shadow to live plane control register 644 * are blocked if the memory self-refresh mode is active at that 645 * moment. So to make sure the plane gets truly disabled, disable 646 * first the self-refresh mode. The self-refresh enable bit in turn 647 * will be checked/applied by the HW only at the next frame start 648 * event which is after the vblank start event, so we need to have a 649 * wait-for-vblank between disabling the plane and the pipe. 650 */ 651 if (HAS_GMCH(display) && 652 intel_set_memory_cxsr(display, false)) 653 intel_initial_plane_vblank_wait(crtc); 654 655 /* 656 * Gen2 reports pipe underruns whenever all planes are disabled. 657 * So disable underrun reporting before all the planes get disabled. 658 */ 659 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) 660 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); 661 662 intel_plane_disable_arm(NULL, plane, crtc_state); 663 intel_initial_plane_vblank_wait(crtc); 664 } 665 666 unsigned int 667 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 668 { 669 int x = 0, y = 0; 670 671 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 672 plane_state->view.color_plane[0].offset, 0); 673 674 return y; 675 } 676 677 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 678 { 679 struct intel_display *display = to_intel_display(crtc_state); 680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 681 enum pipe pipe = crtc->pipe; 682 u32 tmp; 683 684 tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); 685 686 /* 687 * Display WA #1153: icl 688 * enable hardware to bypass the alpha math 689 * and rounding for per-pixel values 00 and 0xff 690 */ 691 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 692 /* 693 * Display WA # 1605353570: icl 694 * Set the pixel rounding bit to 1 for allowing 695 * passthrough of Frame buffer pixels unmodified 696 * across pipe 697 */ 698 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 699 700 /* 701 * Underrun recovery must always be disabled on display 13+. 702 * DG2 chicken bit meaning is inverted compared to other platforms. 703 */ 704 if (display->platform.dg2) 705 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 706 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) 707 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 708 709 /* Wa_14010547955:dg2 */ 710 if (intel_display_wa(display, INTEL_DISPLAY_WA_14010547955)) 711 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 712 713 intel_de_write(display, PIPE_CHICKEN(pipe), tmp); 714 } 715 716 bool intel_has_pending_fb_unpin(struct intel_display *display) 717 { 718 struct intel_crtc *crtc; 719 bool cleanup_done; 720 721 for_each_intel_crtc(display, crtc) { 722 struct drm_crtc_commit *commit; 723 spin_lock(&crtc->base.commit_lock); 724 commit = list_first_entry_or_null(&crtc->base.commit_list, 725 struct drm_crtc_commit, commit_entry); 726 cleanup_done = commit ? 727 try_wait_for_completion(&commit->cleanup_done) : true; 728 spin_unlock(&crtc->base.commit_lock); 729 730 if (cleanup_done) 731 continue; 732 733 intel_crtc_wait_for_next_vblank(crtc); 734 735 return true; 736 } 737 738 return false; 739 } 740 741 /* FIXME: remove this and just flush the cleanup wq where appropriate */ 742 void intel_display_flush_cleanup_work(struct intel_display *display) 743 { 744 struct intel_crtc *crtc; 745 746 for_each_intel_crtc(display, crtc) { 747 struct drm_crtc_commit *commit; 748 749 spin_lock(&crtc->base.commit_lock); 750 commit = list_first_entry_or_null(&crtc->base.commit_list, 751 struct drm_crtc_commit, commit_entry); 752 if (commit) 753 drm_crtc_commit_get(commit); 754 spin_unlock(&crtc->base.commit_lock); 755 756 if (commit) { 757 wait_for_completion(&commit->cleanup_done); 758 drm_crtc_commit_put(commit); 759 } 760 } 761 } 762 763 /* 764 * Finds the encoder associated with the given CRTC. This can only be 765 * used when we know that the CRTC isn't feeding multiple encoders! 766 */ 767 struct intel_encoder * 768 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 769 const struct intel_crtc_state *crtc_state) 770 { 771 const struct drm_connector_state *connector_state; 772 const struct drm_connector *connector; 773 struct intel_encoder *encoder = NULL; 774 struct intel_crtc *primary_crtc; 775 int num_encoders = 0; 776 int i; 777 778 primary_crtc = intel_primary_crtc(crtc_state); 779 780 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 781 if (connector_state->crtc != &primary_crtc->base) 782 continue; 783 784 encoder = to_intel_encoder(connector_state->best_encoder); 785 num_encoders++; 786 } 787 788 drm_WARN(state->base.dev, num_encoders != 1, 789 "%d encoders for pipe %c\n", 790 num_encoders, pipe_name(primary_crtc->pipe)); 791 792 return encoder; 793 } 794 795 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 796 { 797 if (crtc->overlay) 798 (void) intel_overlay_switch_off(crtc->overlay); 799 800 /* Let userspace switch the overlay on again. In most cases userspace 801 * has to recompute where to put it anyway. 802 */ 803 } 804 805 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 806 { 807 struct intel_display *display = to_intel_display(crtc_state); 808 809 if (!crtc_state->nv12_planes) 810 return false; 811 812 /* WA Display #0827: Gen9:all */ 813 if (DISPLAY_VER(display) == 9) 814 return true; 815 816 return false; 817 } 818 819 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 820 { 821 struct intel_display *display = to_intel_display(crtc_state); 822 823 /* Wa_2006604312:icl,ehl */ 824 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) 825 return true; 826 827 return false; 828 } 829 830 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 831 { 832 struct intel_display *display = to_intel_display(crtc_state); 833 834 /* Wa_1604331009:icl,jsl,ehl */ 835 if (is_hdr_mode(crtc_state) && 836 crtc_state->active_planes & BIT(PLANE_CURSOR) && 837 DISPLAY_VER(display) == 11) 838 return true; 839 840 return false; 841 } 842 843 static void intel_async_flip_vtd_wa(struct intel_display *display, 844 enum pipe pipe, bool enable) 845 { 846 if (DISPLAY_VER(display) == 9) { 847 /* 848 * "Plane N stretch max must be programmed to 11b (x1) 849 * when Async flips are enabled on that plane." 850 */ 851 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 852 SKL_PLANE1_STRETCH_MAX_MASK, 853 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 854 } else { 855 /* Also needed on HSW/BDW albeit undocumented */ 856 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 857 HSW_PRI_STRETCH_MAX_MASK, 858 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 859 } 860 } 861 862 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 863 { 864 struct intel_display *display = to_intel_display(crtc_state); 865 866 return crtc_state->uapi.async_flip && intel_display_vtd_active(display) && 867 (DISPLAY_VER(display) == 9 || display->platform.broadwell || 868 display->platform.haswell); 869 } 870 871 static void intel_encoders_audio_enable(struct intel_atomic_state *state, 872 struct intel_crtc *crtc) 873 { 874 const struct intel_crtc_state *crtc_state = 875 intel_atomic_get_new_crtc_state(state, crtc); 876 const struct drm_connector_state *conn_state; 877 struct drm_connector *conn; 878 int i; 879 880 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 881 struct intel_encoder *encoder = 882 to_intel_encoder(conn_state->best_encoder); 883 884 if (conn_state->crtc != &crtc->base) 885 continue; 886 887 if (encoder->audio_enable) 888 encoder->audio_enable(encoder, crtc_state, conn_state); 889 } 890 } 891 892 static void intel_encoders_audio_disable(struct intel_atomic_state *state, 893 struct intel_crtc *crtc) 894 { 895 const struct intel_crtc_state *old_crtc_state = 896 intel_atomic_get_old_crtc_state(state, crtc); 897 const struct drm_connector_state *old_conn_state; 898 struct drm_connector *conn; 899 int i; 900 901 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 902 struct intel_encoder *encoder = 903 to_intel_encoder(old_conn_state->best_encoder); 904 905 if (old_conn_state->crtc != &crtc->base) 906 continue; 907 908 if (encoder->audio_disable) 909 encoder->audio_disable(encoder, old_crtc_state, old_conn_state); 910 } 911 } 912 913 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 914 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 915 (new_crtc_state)->feature) 916 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 917 ((old_crtc_state)->feature && \ 918 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 919 920 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 921 const struct intel_crtc_state *new_crtc_state) 922 { 923 if (!new_crtc_state->hw.active) 924 return false; 925 926 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 927 } 928 929 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 930 const struct intel_crtc_state *new_crtc_state) 931 { 932 if (!old_crtc_state->hw.active) 933 return false; 934 935 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 936 } 937 938 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, 939 const struct intel_crtc_state *new_crtc_state) 940 { 941 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline || 942 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || 943 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || 944 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || 945 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full || 946 old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start || 947 old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end; 948 } 949 950 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, 951 const struct intel_crtc_state *new_crtc_state) 952 { 953 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || 954 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; 955 } 956 957 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, 958 struct intel_crtc *crtc) 959 { 960 const struct intel_crtc_state *old_crtc_state = 961 intel_atomic_get_old_crtc_state(state, crtc); 962 const struct intel_crtc_state *new_crtc_state = 963 intel_atomic_get_new_crtc_state(state, crtc); 964 965 if (!new_crtc_state->hw.active) 966 return false; 967 968 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) || 969 (new_crtc_state->vrr.enable && 970 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 971 vrr_params_changed(old_crtc_state, new_crtc_state))); 972 } 973 974 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 975 struct intel_crtc *crtc) 976 { 977 const struct intel_crtc_state *old_crtc_state = 978 intel_atomic_get_old_crtc_state(state, crtc); 979 const struct intel_crtc_state *new_crtc_state = 980 intel_atomic_get_new_crtc_state(state, crtc); 981 982 if (!old_crtc_state->hw.active) 983 return false; 984 985 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) || 986 (old_crtc_state->vrr.enable && 987 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 988 vrr_params_changed(old_crtc_state, new_crtc_state))); 989 } 990 991 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, 992 const struct intel_crtc_state *new_crtc_state) 993 { 994 if (!new_crtc_state->hw.active) 995 return false; 996 997 return is_enabling(has_audio, old_crtc_state, new_crtc_state) || 998 (new_crtc_state->has_audio && 999 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 1000 } 1001 1002 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, 1003 const struct intel_crtc_state *new_crtc_state) 1004 { 1005 if (!old_crtc_state->hw.active) 1006 return false; 1007 1008 return is_disabling(has_audio, old_crtc_state, new_crtc_state) || 1009 (old_crtc_state->has_audio && 1010 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 1011 } 1012 1013 static bool intel_crtc_lobf_enabling(const struct intel_crtc_state *old_crtc_state, 1014 const struct intel_crtc_state *new_crtc_state) 1015 { 1016 if (!new_crtc_state->hw.active) 1017 return false; 1018 1019 return is_enabling(has_lobf, old_crtc_state, new_crtc_state) || 1020 (new_crtc_state->has_lobf && 1021 (new_crtc_state->update_lrr || new_crtc_state->update_m_n)); 1022 } 1023 1024 static bool intel_crtc_lobf_disabling(const struct intel_crtc_state *old_crtc_state, 1025 const struct intel_crtc_state *new_crtc_state) 1026 { 1027 if (!old_crtc_state->hw.active) 1028 return false; 1029 1030 return is_disabling(has_lobf, old_crtc_state, new_crtc_state) || 1031 (old_crtc_state->has_lobf && 1032 (new_crtc_state->update_lrr || new_crtc_state->update_m_n)); 1033 } 1034 1035 #undef is_disabling 1036 #undef is_enabling 1037 1038 static void intel_post_plane_update(struct intel_atomic_state *state, 1039 struct intel_crtc *crtc) 1040 { 1041 struct intel_display *display = to_intel_display(state); 1042 const struct intel_crtc_state *old_crtc_state = 1043 intel_atomic_get_old_crtc_state(state, crtc); 1044 const struct intel_crtc_state *new_crtc_state = 1045 intel_atomic_get_new_crtc_state(state, crtc); 1046 enum pipe pipe = crtc->pipe; 1047 1048 intel_frontbuffer_flip(display, new_crtc_state->fb_bits); 1049 1050 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1051 intel_update_watermarks(display); 1052 1053 intel_fbc_post_update(state, crtc); 1054 1055 if (needs_async_flip_vtd_wa(old_crtc_state) && 1056 !needs_async_flip_vtd_wa(new_crtc_state)) 1057 intel_async_flip_vtd_wa(display, pipe, false); 1058 1059 if (needs_nv12_wa(old_crtc_state) && 1060 !needs_nv12_wa(new_crtc_state)) 1061 skl_wa_827(display, pipe, false); 1062 1063 if (needs_scalerclk_wa(old_crtc_state) && 1064 !needs_scalerclk_wa(new_crtc_state)) 1065 icl_wa_scalerclkgating(display, pipe, false); 1066 1067 if (needs_cursorclk_wa(old_crtc_state) && 1068 !needs_cursorclk_wa(new_crtc_state)) 1069 icl_wa_cursorclkgating(display, pipe, false); 1070 1071 if (intel_crtc_needs_color_update(new_crtc_state)) 1072 intel_color_post_update(new_crtc_state); 1073 1074 if (audio_enabling(old_crtc_state, new_crtc_state)) 1075 intel_encoders_audio_enable(state, crtc); 1076 1077 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503117)) { 1078 if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled) 1079 adl_scaler_ecc_unmask(new_crtc_state); 1080 } 1081 1082 if (intel_crtc_lobf_enabling(old_crtc_state, new_crtc_state)) 1083 intel_alpm_lobf_enable(new_crtc_state); 1084 1085 intel_psr_post_plane_update(state, crtc); 1086 } 1087 1088 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, 1089 struct intel_crtc *crtc) 1090 { 1091 const struct intel_crtc_state *new_crtc_state = 1092 intel_atomic_get_new_crtc_state(state, crtc); 1093 1094 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 1095 hsw_ips_post_update(state, crtc); 1096 1097 /* 1098 * Activate DRRS after state readout to avoid 1099 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 1100 */ 1101 intel_drrs_activate(new_crtc_state); 1102 } 1103 1104 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1105 struct intel_crtc *crtc) 1106 { 1107 const struct intel_crtc_state *crtc_state = 1108 intel_atomic_get_new_crtc_state(state, crtc); 1109 u8 update_planes = crtc_state->update_planes; 1110 const struct intel_plane_state __maybe_unused *plane_state; 1111 struct intel_plane *plane; 1112 int i; 1113 1114 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1115 if (plane->pipe == crtc->pipe && 1116 update_planes & BIT(plane->id)) 1117 plane->enable_flip_done(plane); 1118 } 1119 } 1120 1121 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1122 struct intel_crtc *crtc) 1123 { 1124 const struct intel_crtc_state *crtc_state = 1125 intel_atomic_get_new_crtc_state(state, crtc); 1126 u8 update_planes = crtc_state->update_planes; 1127 const struct intel_plane_state __maybe_unused *plane_state; 1128 struct intel_plane *plane; 1129 int i; 1130 1131 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1132 if (plane->pipe == crtc->pipe && 1133 update_planes & BIT(plane->id)) 1134 plane->disable_flip_done(plane); 1135 } 1136 } 1137 1138 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1139 struct intel_crtc *crtc) 1140 { 1141 const struct intel_crtc_state *old_crtc_state = 1142 intel_atomic_get_old_crtc_state(state, crtc); 1143 const struct intel_crtc_state *new_crtc_state = 1144 intel_atomic_get_new_crtc_state(state, crtc); 1145 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1146 ~new_crtc_state->async_flip_planes; 1147 const struct intel_plane_state *old_plane_state; 1148 struct intel_plane *plane; 1149 bool need_vbl_wait = false; 1150 int i; 1151 1152 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1153 if (plane->need_async_flip_toggle_wa && 1154 plane->pipe == crtc->pipe && 1155 disable_async_flip_planes & BIT(plane->id)) { 1156 /* 1157 * Apart from the async flip bit we want to 1158 * preserve the old state for the plane. 1159 */ 1160 intel_plane_async_flip(NULL, plane, 1161 old_crtc_state, old_plane_state, false); 1162 need_vbl_wait = true; 1163 } 1164 } 1165 1166 if (need_vbl_wait) 1167 intel_crtc_wait_for_next_vblank(crtc); 1168 } 1169 1170 static void intel_pre_plane_update(struct intel_atomic_state *state, 1171 struct intel_crtc *crtc) 1172 { 1173 struct intel_display *display = to_intel_display(state); 1174 const struct intel_crtc_state *old_crtc_state = 1175 intel_atomic_get_old_crtc_state(state, crtc); 1176 const struct intel_crtc_state *new_crtc_state = 1177 intel_atomic_get_new_crtc_state(state, crtc); 1178 enum pipe pipe = crtc->pipe; 1179 1180 if (intel_crtc_lobf_disabling(old_crtc_state, new_crtc_state)) 1181 intel_alpm_lobf_disable(new_crtc_state); 1182 1183 intel_psr_pre_plane_update(state, crtc); 1184 1185 if (intel_crtc_vrr_disabling(state, crtc)) { 1186 intel_vrr_disable(old_crtc_state); 1187 intel_vrr_dcb_reset(old_crtc_state, crtc); 1188 intel_crtc_update_active_timings(old_crtc_state, false); 1189 } 1190 1191 if (audio_disabling(old_crtc_state, new_crtc_state)) 1192 intel_encoders_audio_disable(state, crtc); 1193 1194 intel_drrs_deactivate(old_crtc_state); 1195 1196 if (hsw_ips_pre_update(state, crtc)) 1197 intel_crtc_wait_for_next_vblank(crtc); 1198 1199 if (intel_fbc_pre_update(state, crtc)) 1200 intel_crtc_wait_for_next_vblank(crtc); 1201 1202 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1203 needs_async_flip_vtd_wa(new_crtc_state)) 1204 intel_async_flip_vtd_wa(display, pipe, true); 1205 1206 /* Display WA 827 */ 1207 if (!needs_nv12_wa(old_crtc_state) && 1208 needs_nv12_wa(new_crtc_state)) 1209 skl_wa_827(display, pipe, true); 1210 1211 /* Wa_2006604312:icl,ehl */ 1212 if (!needs_scalerclk_wa(old_crtc_state) && 1213 needs_scalerclk_wa(new_crtc_state)) 1214 icl_wa_scalerclkgating(display, pipe, true); 1215 1216 /* Wa_1604331009:icl,jsl,ehl */ 1217 if (!needs_cursorclk_wa(old_crtc_state) && 1218 needs_cursorclk_wa(new_crtc_state)) 1219 icl_wa_cursorclkgating(display, pipe, true); 1220 1221 /* 1222 * Vblank time updates from the shadow to live plane control register 1223 * are blocked if the memory self-refresh mode is active at that 1224 * moment. So to make sure the plane gets truly disabled, disable 1225 * first the self-refresh mode. The self-refresh enable bit in turn 1226 * will be checked/applied by the HW only at the next frame start 1227 * event which is after the vblank start event, so we need to have a 1228 * wait-for-vblank between disabling the plane and the pipe. 1229 */ 1230 if (HAS_GMCH(display) && old_crtc_state->hw.active && 1231 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false)) 1232 intel_crtc_wait_for_next_vblank(crtc); 1233 1234 /* 1235 * IVB workaround: must disable low power watermarks for at least 1236 * one frame before enabling scaling. LP watermarks can be re-enabled 1237 * when scaling is disabled. 1238 * 1239 * WaCxSRDisabledForSpriteScaling:ivb 1240 */ 1241 if (!HAS_GMCH(display) && old_crtc_state->hw.active && 1242 new_crtc_state->disable_cxsr && ilk_disable_cxsr(display)) 1243 intel_crtc_wait_for_next_vblank(crtc); 1244 1245 /* 1246 * If we're doing a modeset we don't need to do any 1247 * pre-vblank watermark programming here. 1248 */ 1249 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1250 /* 1251 * For platforms that support atomic watermarks, program the 1252 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1253 * will be the intermediate values that are safe for both pre- and 1254 * post- vblank; when vblank happens, the 'active' values will be set 1255 * to the final 'target' values and we'll do this again to get the 1256 * optimal watermarks. For gen9+ platforms, the values we program here 1257 * will be the final target values which will get automatically latched 1258 * at vblank time; no further programming will be necessary. 1259 * 1260 * If a platform hasn't been transitioned to atomic watermarks yet, 1261 * we'll continue to update watermarks the old way, if flags tell 1262 * us to. 1263 */ 1264 if (!intel_initial_watermarks(state, crtc)) 1265 if (new_crtc_state->update_wm_pre) 1266 intel_update_watermarks(display); 1267 } 1268 1269 /* 1270 * Gen2 reports pipe underruns whenever all planes are disabled. 1271 * So disable underrun reporting before all the planes get disabled. 1272 * 1273 * We do this after .initial_watermarks() so that we have a 1274 * chance of catching underruns with the intermediate watermarks 1275 * vs. the old plane configuration. 1276 */ 1277 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1278 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1279 1280 /* 1281 * WA for platforms where async address update enable bit 1282 * is double buffered and only latched at start of vblank. 1283 */ 1284 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1285 intel_crtc_async_flip_disable_wa(state, crtc); 1286 } 1287 1288 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1289 struct intel_crtc *crtc) 1290 { 1291 struct intel_display *display = to_intel_display(state); 1292 const struct intel_crtc_state *new_crtc_state = 1293 intel_atomic_get_new_crtc_state(state, crtc); 1294 unsigned int update_mask = new_crtc_state->update_planes; 1295 const struct intel_plane_state *old_plane_state; 1296 struct intel_plane *plane; 1297 unsigned fb_bits = 0; 1298 int i; 1299 1300 intel_crtc_dpms_overlay_disable(crtc); 1301 1302 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1303 if (crtc->pipe != plane->pipe || 1304 !(update_mask & BIT(plane->id))) 1305 continue; 1306 1307 intel_plane_disable_arm(NULL, plane, new_crtc_state); 1308 1309 if (old_plane_state->uapi.visible) 1310 fb_bits |= plane->frontbuffer_bit; 1311 } 1312 1313 intel_frontbuffer_flip(display, fb_bits); 1314 } 1315 1316 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1317 { 1318 struct intel_display *display = to_intel_display(state); 1319 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1320 struct intel_crtc *crtc; 1321 1322 /* 1323 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1324 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1325 */ 1326 if (display->dpll.mgr) { 1327 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 1328 if (intel_crtc_needs_modeset(new_crtc_state)) 1329 continue; 1330 1331 new_crtc_state->intel_dpll = old_crtc_state->intel_dpll; 1332 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1333 } 1334 } 1335 } 1336 1337 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1338 struct intel_crtc *crtc) 1339 { 1340 const struct intel_crtc_state *crtc_state = 1341 intel_atomic_get_new_crtc_state(state, crtc); 1342 const struct drm_connector_state *conn_state; 1343 struct drm_connector *conn; 1344 int i; 1345 1346 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1347 struct intel_encoder *encoder = 1348 to_intel_encoder(conn_state->best_encoder); 1349 1350 if (conn_state->crtc != &crtc->base) 1351 continue; 1352 1353 if (encoder->pre_pll_enable) 1354 encoder->pre_pll_enable(state, encoder, 1355 crtc_state, conn_state); 1356 } 1357 } 1358 1359 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1360 struct intel_crtc *crtc) 1361 { 1362 const struct intel_crtc_state *crtc_state = 1363 intel_atomic_get_new_crtc_state(state, crtc); 1364 const struct drm_connector_state *conn_state; 1365 struct drm_connector *conn; 1366 int i; 1367 1368 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1369 struct intel_encoder *encoder = 1370 to_intel_encoder(conn_state->best_encoder); 1371 1372 if (conn_state->crtc != &crtc->base) 1373 continue; 1374 1375 if (encoder->pre_enable) 1376 encoder->pre_enable(state, encoder, 1377 crtc_state, conn_state); 1378 } 1379 } 1380 1381 static void intel_encoders_enable(struct intel_atomic_state *state, 1382 struct intel_crtc *crtc) 1383 { 1384 const struct intel_crtc_state *crtc_state = 1385 intel_atomic_get_new_crtc_state(state, crtc); 1386 const struct drm_connector_state *conn_state; 1387 struct drm_connector *conn; 1388 int i; 1389 1390 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1391 struct intel_encoder *encoder = 1392 to_intel_encoder(conn_state->best_encoder); 1393 1394 if (conn_state->crtc != &crtc->base) 1395 continue; 1396 1397 if (encoder->enable) 1398 encoder->enable(state, encoder, 1399 crtc_state, conn_state); 1400 intel_opregion_notify_encoder(encoder, true); 1401 } 1402 } 1403 1404 static void intel_encoders_disable(struct intel_atomic_state *state, 1405 struct intel_crtc *crtc) 1406 { 1407 const struct intel_crtc_state *old_crtc_state = 1408 intel_atomic_get_old_crtc_state(state, crtc); 1409 const struct drm_connector_state *old_conn_state; 1410 struct drm_connector *conn; 1411 int i; 1412 1413 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1414 struct intel_encoder *encoder = 1415 to_intel_encoder(old_conn_state->best_encoder); 1416 1417 if (old_conn_state->crtc != &crtc->base) 1418 continue; 1419 1420 intel_opregion_notify_encoder(encoder, false); 1421 if (encoder->disable) 1422 encoder->disable(state, encoder, 1423 old_crtc_state, old_conn_state); 1424 } 1425 } 1426 1427 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1428 struct intel_crtc *crtc) 1429 { 1430 const struct intel_crtc_state *old_crtc_state = 1431 intel_atomic_get_old_crtc_state(state, crtc); 1432 const struct drm_connector_state *old_conn_state; 1433 struct drm_connector *conn; 1434 int i; 1435 1436 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1437 struct intel_encoder *encoder = 1438 to_intel_encoder(old_conn_state->best_encoder); 1439 1440 if (old_conn_state->crtc != &crtc->base) 1441 continue; 1442 1443 if (encoder->post_disable) 1444 encoder->post_disable(state, encoder, 1445 old_crtc_state, old_conn_state); 1446 } 1447 } 1448 1449 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1450 struct intel_crtc *crtc) 1451 { 1452 const struct intel_crtc_state *old_crtc_state = 1453 intel_atomic_get_old_crtc_state(state, crtc); 1454 const struct drm_connector_state *old_conn_state; 1455 struct drm_connector *conn; 1456 int i; 1457 1458 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1459 struct intel_encoder *encoder = 1460 to_intel_encoder(old_conn_state->best_encoder); 1461 1462 if (old_conn_state->crtc != &crtc->base) 1463 continue; 1464 1465 if (encoder->post_pll_disable) 1466 encoder->post_pll_disable(state, encoder, 1467 old_crtc_state, old_conn_state); 1468 } 1469 } 1470 1471 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1472 struct intel_crtc *crtc) 1473 { 1474 const struct intel_crtc_state *crtc_state = 1475 intel_atomic_get_new_crtc_state(state, crtc); 1476 const struct drm_connector_state *conn_state; 1477 struct drm_connector *conn; 1478 int i; 1479 1480 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1481 struct intel_encoder *encoder = 1482 to_intel_encoder(conn_state->best_encoder); 1483 1484 if (conn_state->crtc != &crtc->base) 1485 continue; 1486 1487 if (encoder->update_pipe) 1488 encoder->update_pipe(state, encoder, 1489 crtc_state, conn_state); 1490 } 1491 } 1492 1493 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1494 { 1495 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1496 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1497 1498 if (crtc_state->has_pch_encoder) { 1499 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1500 &crtc_state->fdi_m_n); 1501 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1502 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1503 &crtc_state->dp_m_n); 1504 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1505 &crtc_state->dp_m2_n2); 1506 } 1507 1508 intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder); 1509 1510 ilk_set_pipeconf(crtc_state); 1511 } 1512 1513 static void ilk_crtc_enable(struct intel_atomic_state *state, 1514 struct intel_crtc *crtc) 1515 { 1516 struct intel_display *display = to_intel_display(crtc); 1517 const struct intel_crtc_state *new_crtc_state = 1518 intel_atomic_get_new_crtc_state(state, crtc); 1519 enum pipe pipe = crtc->pipe; 1520 1521 if (drm_WARN_ON(display->drm, crtc->active)) 1522 return; 1523 1524 /* 1525 * Sometimes spurious CPU pipe underruns happen during FDI 1526 * training, at least with VGA+HDMI cloning. Suppress them. 1527 * 1528 * On ILK we get an occasional spurious CPU pipe underruns 1529 * between eDP port A enable and vdd enable. Also PCH port 1530 * enable seems to result in the occasional CPU pipe underrun. 1531 * 1532 * Spurious PCH underruns also occur during PCH enabling. 1533 */ 1534 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1535 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1536 1537 ilk_configure_cpu_transcoder(new_crtc_state); 1538 1539 intel_set_pipe_src_size(new_crtc_state); 1540 1541 crtc->active = true; 1542 1543 intel_encoders_pre_enable(state, crtc); 1544 1545 if (new_crtc_state->has_pch_encoder) { 1546 ilk_pch_pre_enable(state, crtc); 1547 } else { 1548 assert_fdi_tx_disabled(display, pipe); 1549 assert_fdi_rx_disabled(display, pipe); 1550 } 1551 1552 ilk_pfit_enable(new_crtc_state); 1553 1554 /* 1555 * On ILK+ LUT must be loaded before the pipe is running but with 1556 * clocks enabled 1557 */ 1558 intel_color_modeset(new_crtc_state); 1559 1560 intel_initial_watermarks(state, crtc); 1561 intel_enable_transcoder(new_crtc_state); 1562 1563 if (new_crtc_state->has_pch_encoder) 1564 ilk_pch_enable(state, crtc); 1565 1566 intel_crtc_vblank_on(new_crtc_state); 1567 1568 intel_encoders_enable(state, crtc); 1569 1570 if (HAS_PCH_CPT(display)) 1571 intel_wait_for_pipe_scanline_moving(crtc); 1572 1573 /* 1574 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1575 * And a second vblank wait is needed at least on ILK with 1576 * some interlaced HDMI modes. Let's do the double wait always 1577 * in case there are more corner cases we don't know about. 1578 */ 1579 if (new_crtc_state->has_pch_encoder) { 1580 intel_crtc_wait_for_next_vblank(crtc); 1581 intel_crtc_wait_for_next_vblank(crtc); 1582 } 1583 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1584 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1585 } 1586 1587 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1588 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) 1589 { 1590 struct intel_display *display = to_intel_display(crtc_state); 1591 1592 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; 1593 } 1594 1595 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) 1596 { 1597 struct intel_display *display = to_intel_display(crtc); 1598 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1599 1600 intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe), 1601 mask, enable ? mask : 0); 1602 } 1603 1604 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1605 { 1606 struct intel_display *display = to_intel_display(crtc_state); 1607 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1608 1609 intel_de_write(display, WM_LINETIME(crtc->pipe), 1610 HSW_LINETIME(crtc_state->linetime) | 1611 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1612 } 1613 1614 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1615 { 1616 struct intel_display *display = to_intel_display(crtc_state); 1617 1618 intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder), 1619 HSW_FRAME_START_DELAY_MASK, 1620 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1621 } 1622 1623 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1624 { 1625 struct intel_display *display = to_intel_display(crtc_state); 1626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1628 1629 if (crtc_state->has_pch_encoder) { 1630 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1631 &crtc_state->fdi_m_n); 1632 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1633 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1634 &crtc_state->dp_m_n); 1635 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1636 &crtc_state->dp_m2_n2); 1637 } 1638 1639 intel_cmtg_set_m_n(crtc_state); 1640 intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder); 1641 intel_cmtg_set_timings(crtc_state, MODESET); 1642 1643 if (cpu_transcoder != TRANSCODER_EDP) 1644 intel_de_write(display, TRANS_MULT(display, cpu_transcoder), 1645 crtc_state->pixel_multiplier - 1); 1646 1647 hsw_set_frame_start_delay(crtc_state); 1648 1649 hsw_set_transconf(crtc_state); 1650 } 1651 1652 static void hsw_crtc_enable(struct intel_atomic_state *state, 1653 struct intel_crtc *crtc) 1654 { 1655 struct intel_display *display = to_intel_display(state); 1656 const struct intel_crtc_state *new_crtc_state = 1657 intel_atomic_get_new_crtc_state(state, crtc); 1658 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1659 struct intel_crtc *pipe_crtc; 1660 1661 if (drm_WARN_ON(display->drm, crtc->active)) 1662 return; 1663 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1664 const struct intel_crtc_state *new_pipe_crtc_state = 1665 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1666 1667 intel_dmc_enable_pipe(new_pipe_crtc_state); 1668 } 1669 1670 intel_encoders_pre_pll_enable(state, crtc); 1671 1672 if (new_crtc_state->intel_dpll) 1673 intel_dpll_enable(new_crtc_state); 1674 1675 intel_encoders_pre_enable(state, crtc); 1676 1677 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1678 const struct intel_crtc_state *pipe_crtc_state = 1679 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1680 1681 intel_dsc_enable(pipe_crtc_state); 1682 1683 if (HAS_UNCOMPRESSED_JOINER(display)) 1684 intel_uncompressed_joiner_enable(pipe_crtc_state); 1685 1686 intel_set_pipe_src_size(pipe_crtc_state); 1687 1688 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 1689 bdw_set_pipe_misc(NULL, pipe_crtc_state); 1690 } 1691 1692 if (!transcoder_is_dsi(cpu_transcoder)) 1693 hsw_configure_cpu_transcoder(new_crtc_state); 1694 1695 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1696 const struct intel_crtc_state *pipe_crtc_state = 1697 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1698 1699 pipe_crtc->active = true; 1700 1701 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) 1702 glk_pipe_scaler_clock_gating_wa(pipe_crtc, true); 1703 1704 if (DISPLAY_VER(display) >= 9) 1705 skl_pfit_enable(pipe_crtc_state); 1706 else 1707 ilk_pfit_enable(pipe_crtc_state); 1708 1709 /* 1710 * On ILK+ LUT must be loaded before the pipe is running but with 1711 * clocks enabled 1712 */ 1713 intel_color_modeset(pipe_crtc_state); 1714 1715 hsw_set_linetime_wm(pipe_crtc_state); 1716 1717 if (DISPLAY_VER(display) >= 11) 1718 icl_set_pipe_chicken(pipe_crtc_state); 1719 1720 intel_initial_watermarks(state, pipe_crtc); 1721 } 1722 1723 intel_encoders_enable(state, crtc); 1724 1725 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) { 1726 const struct intel_crtc_state *pipe_crtc_state = 1727 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1728 enum pipe hsw_workaround_pipe; 1729 1730 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) { 1731 intel_crtc_wait_for_next_vblank(pipe_crtc); 1732 glk_pipe_scaler_clock_gating_wa(pipe_crtc, false); 1733 } 1734 1735 /* 1736 * If we change the relative order between pipe/planes 1737 * enabling, we need to change the workaround. 1738 */ 1739 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe; 1740 if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) { 1741 struct intel_crtc *wa_crtc = 1742 intel_crtc_for_pipe(display, hsw_workaround_pipe); 1743 1744 intel_crtc_wait_for_next_vblank(wa_crtc); 1745 intel_crtc_wait_for_next_vblank(wa_crtc); 1746 } 1747 } 1748 } 1749 1750 static void ilk_crtc_disable(struct intel_atomic_state *state, 1751 struct intel_crtc *crtc) 1752 { 1753 struct intel_display *display = to_intel_display(crtc); 1754 const struct intel_crtc_state *old_crtc_state = 1755 intel_atomic_get_old_crtc_state(state, crtc); 1756 enum pipe pipe = crtc->pipe; 1757 1758 /* 1759 * Sometimes spurious CPU pipe underruns happen when the 1760 * pipe is already disabled, but FDI RX/TX is still enabled. 1761 * Happens at least with VGA+HDMI cloning. Suppress them. 1762 */ 1763 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1764 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1765 1766 intel_encoders_disable(state, crtc); 1767 1768 intel_crtc_vblank_off(old_crtc_state); 1769 1770 intel_disable_transcoder(old_crtc_state); 1771 1772 ilk_pfit_disable(old_crtc_state); 1773 1774 if (old_crtc_state->has_pch_encoder) 1775 ilk_pch_disable(state, crtc); 1776 1777 intel_encoders_post_disable(state, crtc); 1778 1779 if (old_crtc_state->has_pch_encoder) 1780 ilk_pch_post_disable(state, crtc); 1781 1782 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1783 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1784 } 1785 1786 static void hsw_crtc_disable(struct intel_atomic_state *state, 1787 struct intel_crtc *crtc) 1788 { 1789 struct intel_display *display = to_intel_display(state); 1790 const struct intel_crtc_state *old_crtc_state = 1791 intel_atomic_get_old_crtc_state(state, crtc); 1792 struct intel_crtc *pipe_crtc; 1793 1794 if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) { 1795 intel_cmtg_set_clk_select(old_crtc_state); 1796 intel_cmtg_disable(old_crtc_state); 1797 } 1798 /* 1799 * FIXME collapse everything to one hook. 1800 * Need care with mst->ddi interactions. 1801 */ 1802 intel_encoders_disable(state, crtc); 1803 intel_encoders_post_disable(state, crtc); 1804 1805 intel_dpll_disable(old_crtc_state); 1806 1807 intel_encoders_post_pll_disable(state, crtc); 1808 1809 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 1810 const struct intel_crtc_state *old_pipe_crtc_state = 1811 intel_atomic_get_old_crtc_state(state, pipe_crtc); 1812 1813 intel_dmc_disable_pipe(old_pipe_crtc_state); 1814 } 1815 } 1816 1817 /* Prefer intel_encoder_is_combo() */ 1818 bool intel_phy_is_combo(struct intel_display *display, enum phy phy) 1819 { 1820 if (phy == PHY_NONE) 1821 return false; 1822 else if (display->platform.alderlake_s) 1823 return phy <= PHY_E; 1824 else if (display->platform.dg1 || display->platform.rocketlake) 1825 return phy <= PHY_D; 1826 else if (display->platform.jasperlake || display->platform.elkhartlake) 1827 return phy <= PHY_C; 1828 else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12)) 1829 return phy <= PHY_B; 1830 else 1831 /* 1832 * DG2 outputs labelled as "combo PHY" in the bspec use 1833 * SNPS PHYs with completely different programming, 1834 * hence we always return false here. 1835 */ 1836 return false; 1837 } 1838 1839 /* 1840 * This function returns true if the DDI port respective to the PHY enumeration 1841 * is a Type-C capable port. 1842 * 1843 * Depending on the VBT, the port might be configured 1844 * as a "dedicated external" port, meaning that actual physical PHY is outside 1845 * of the Type-C subsystem and, as such, not really a "Type-C PHY". 1846 * 1847 * Prefer intel_encoder_is_tc(), especially if you really need to know if we 1848 * are dealing with Type-C connections. 1849 */ 1850 bool intel_phy_is_tc(struct intel_display *display, enum phy phy) 1851 { 1852 /* 1853 * Discrete GPU phy's are not attached to FIA's to support TC 1854 * subsystem Legacy or non-legacy, and only support native DP/HDMI 1855 */ 1856 if (display->platform.dgfx) 1857 return false; 1858 1859 if (DISPLAY_VER(display) >= 13) 1860 return phy >= PHY_F && phy <= PHY_I; 1861 else if (display->platform.tigerlake) 1862 return phy >= PHY_D && phy <= PHY_I; 1863 else if (display->platform.icelake) 1864 return phy >= PHY_C && phy <= PHY_F; 1865 1866 return false; 1867 } 1868 1869 /* Prefer intel_encoder_is_snps() */ 1870 bool intel_phy_is_snps(struct intel_display *display, enum phy phy) 1871 { 1872 /* 1873 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port 1874 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc(). 1875 */ 1876 return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E; 1877 } 1878 1879 /* Prefer intel_encoder_to_phy() */ 1880 enum phy intel_port_to_phy(struct intel_display *display, enum port port) 1881 { 1882 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) 1883 return PHY_D + port - PORT_D_XELPD; 1884 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) 1885 return PHY_F + port - PORT_TC1; 1886 else if (display->platform.alderlake_s && port >= PORT_TC1) 1887 return PHY_B + port - PORT_TC1; 1888 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) 1889 return PHY_C + port - PORT_TC1; 1890 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 1891 port == PORT_D) 1892 return PHY_A; 1893 1894 return PHY_A + port - PORT_A; 1895 } 1896 1897 /* Prefer intel_encoder_to_tc() */ 1898 /* 1899 * Return TC_PORT_1..I915_MAX_TC_PORTS for any TypeC DDI port. The function 1900 * can be also called for TypeC DDI ports not connected to a TypeC PHY such as 1901 * the PORT_TC1..4 ports on RKL/ADLS/BMG. 1902 */ 1903 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) 1904 { 1905 if (DISPLAY_VER(display) >= 12) 1906 return TC_PORT_1 + port - PORT_TC1; 1907 else 1908 return TC_PORT_1 + port - PORT_C; 1909 } 1910 1911 /* 1912 * Return TC_PORT_1..I915_MAX_TC_PORTS for TypeC DDI ports connected to a TypeC PHY. 1913 * Note that on RKL, ADLS, BMG the PORT_TC1..4 ports are connected to a non-TypeC 1914 * PHY, so on those platforms the function returns TC_PORT_NONE. 1915 */ 1916 enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) 1917 { 1918 if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) 1919 return TC_PORT_NONE; 1920 1921 return intel_port_to_tc(display, port); 1922 } 1923 1924 enum phy intel_encoder_to_phy(struct intel_encoder *encoder) 1925 { 1926 struct intel_display *display = to_intel_display(encoder); 1927 1928 return intel_port_to_phy(display, encoder->port); 1929 } 1930 1931 bool intel_encoder_is_combo(struct intel_encoder *encoder) 1932 { 1933 struct intel_display *display = to_intel_display(encoder); 1934 1935 return intel_phy_is_combo(display, intel_encoder_to_phy(encoder)); 1936 } 1937 1938 bool intel_encoder_is_snps(struct intel_encoder *encoder) 1939 { 1940 struct intel_display *display = to_intel_display(encoder); 1941 1942 return intel_phy_is_snps(display, intel_encoder_to_phy(encoder)); 1943 } 1944 1945 bool intel_encoder_is_tc(struct intel_encoder *encoder) 1946 { 1947 struct intel_display *display = to_intel_display(encoder); 1948 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1949 1950 if (dig_port && dig_port->dedicated_external) 1951 return false; 1952 1953 return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); 1954 } 1955 1956 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) 1957 { 1958 struct intel_display *display = to_intel_display(encoder); 1959 1960 return intel_tc_phy_port_to_tc(display, encoder->port); 1961 } 1962 1963 enum intel_display_power_domain 1964 intel_aux_power_domain(struct intel_digital_port *dig_port) 1965 { 1966 struct intel_display *display = to_intel_display(dig_port); 1967 1968 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1969 return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch); 1970 1971 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); 1972 } 1973 1974 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1975 struct intel_power_domain_mask *mask) 1976 { 1977 struct intel_display *display = to_intel_display(crtc_state); 1978 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1979 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1980 struct drm_encoder *encoder; 1981 enum pipe pipe = crtc->pipe; 1982 1983 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1984 1985 if (!crtc_state->hw.active) 1986 return; 1987 1988 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1989 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1990 if (crtc_state->pch_pfit.enabled || 1991 crtc_state->pch_pfit.force_thru) 1992 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1993 1994 drm_for_each_encoder_mask(encoder, display->drm, 1995 crtc_state->uapi.encoder_mask) { 1996 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1997 1998 set_bit(intel_encoder->power_domain, mask->bits); 1999 } 2000 2001 if (HAS_DDI(display) && crtc_state->has_audio) 2002 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2003 2004 if (crtc_state->intel_dpll) 2005 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2006 2007 if (crtc_state->dsc.compression_enable) 2008 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2009 } 2010 2011 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2012 struct intel_power_domain_mask *old_domains) 2013 { 2014 struct intel_display *display = to_intel_display(crtc_state); 2015 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2016 enum intel_display_power_domain domain; 2017 struct intel_power_domain_mask domains, new_domains; 2018 2019 get_crtc_power_domains(crtc_state, &domains); 2020 2021 bitmap_andnot(new_domains.bits, 2022 domains.bits, 2023 crtc->enabled_power_domains.mask.bits, 2024 POWER_DOMAIN_NUM); 2025 bitmap_andnot(old_domains->bits, 2026 crtc->enabled_power_domains.mask.bits, 2027 domains.bits, 2028 POWER_DOMAIN_NUM); 2029 2030 for_each_power_domain(domain, &new_domains) 2031 intel_display_power_get_in_set(display, 2032 &crtc->enabled_power_domains, 2033 domain); 2034 } 2035 2036 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2037 struct intel_power_domain_mask *domains) 2038 { 2039 struct intel_display *display = to_intel_display(crtc); 2040 2041 intel_display_power_put_mask_in_set(display, 2042 &crtc->enabled_power_domains, 2043 domains); 2044 } 2045 2046 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2047 { 2048 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2049 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2050 2051 if (intel_crtc_has_dp_encoder(crtc_state)) { 2052 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2053 &crtc_state->dp_m_n); 2054 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2055 &crtc_state->dp_m2_n2); 2056 } 2057 2058 intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder); 2059 2060 i9xx_set_pipeconf(crtc_state); 2061 } 2062 2063 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2064 struct intel_crtc *crtc) 2065 { 2066 struct intel_display *display = to_intel_display(crtc); 2067 const struct intel_crtc_state *new_crtc_state = 2068 intel_atomic_get_new_crtc_state(state, crtc); 2069 enum pipe pipe = crtc->pipe; 2070 2071 if (drm_WARN_ON(display->drm, crtc->active)) 2072 return; 2073 2074 i9xx_configure_cpu_transcoder(new_crtc_state); 2075 2076 intel_set_pipe_src_size(new_crtc_state); 2077 2078 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); 2079 2080 if (display->platform.cherryview && pipe == PIPE_B) { 2081 intel_de_write(display, CHV_BLEND(display, pipe), 2082 CHV_BLEND_LEGACY); 2083 intel_de_write(display, CHV_CANVAS(display, pipe), 0); 2084 } 2085 2086 crtc->active = true; 2087 2088 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2089 2090 intel_encoders_pre_pll_enable(state, crtc); 2091 2092 if (display->platform.cherryview) 2093 chv_enable_pll(new_crtc_state); 2094 else 2095 vlv_enable_pll(new_crtc_state); 2096 2097 intel_encoders_pre_enable(state, crtc); 2098 2099 i9xx_pfit_enable(new_crtc_state); 2100 2101 intel_color_modeset(new_crtc_state); 2102 2103 intel_initial_watermarks(state, crtc); 2104 intel_enable_transcoder(new_crtc_state); 2105 2106 intel_crtc_vblank_on(new_crtc_state); 2107 2108 intel_encoders_enable(state, crtc); 2109 } 2110 2111 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2112 struct intel_crtc *crtc) 2113 { 2114 struct intel_display *display = to_intel_display(crtc); 2115 const struct intel_crtc_state *new_crtc_state = 2116 intel_atomic_get_new_crtc_state(state, crtc); 2117 enum pipe pipe = crtc->pipe; 2118 2119 if (drm_WARN_ON(display->drm, crtc->active)) 2120 return; 2121 2122 i9xx_configure_cpu_transcoder(new_crtc_state); 2123 2124 intel_set_pipe_src_size(new_crtc_state); 2125 2126 crtc->active = true; 2127 2128 if (DISPLAY_VER(display) != 2) 2129 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2130 2131 intel_encoders_pre_enable(state, crtc); 2132 2133 i9xx_enable_pll(new_crtc_state); 2134 2135 i9xx_pfit_enable(new_crtc_state); 2136 2137 intel_color_modeset(new_crtc_state); 2138 2139 if (!intel_initial_watermarks(state, crtc)) 2140 intel_update_watermarks(display); 2141 intel_enable_transcoder(new_crtc_state); 2142 2143 intel_crtc_vblank_on(new_crtc_state); 2144 2145 intel_encoders_enable(state, crtc); 2146 2147 /* prevents spurious underruns */ 2148 if (DISPLAY_VER(display) == 2) 2149 intel_crtc_wait_for_next_vblank(crtc); 2150 } 2151 2152 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2153 struct intel_crtc *crtc) 2154 { 2155 struct intel_display *display = to_intel_display(state); 2156 struct intel_crtc_state *old_crtc_state = 2157 intel_atomic_get_old_crtc_state(state, crtc); 2158 enum pipe pipe = crtc->pipe; 2159 2160 /* 2161 * On gen2 planes are double buffered but the pipe isn't, so we must 2162 * wait for planes to fully turn off before disabling the pipe. 2163 */ 2164 if (DISPLAY_VER(display) == 2) 2165 intel_crtc_wait_for_next_vblank(crtc); 2166 2167 intel_encoders_disable(state, crtc); 2168 2169 intel_crtc_vblank_off(old_crtc_state); 2170 2171 intel_disable_transcoder(old_crtc_state); 2172 2173 i9xx_pfit_disable(old_crtc_state); 2174 2175 intel_encoders_post_disable(state, crtc); 2176 2177 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2178 if (display->platform.cherryview) 2179 chv_disable_pll(display, pipe); 2180 else if (display->platform.valleyview) 2181 vlv_disable_pll(display, pipe); 2182 else 2183 i9xx_disable_pll(old_crtc_state); 2184 } 2185 2186 intel_encoders_post_pll_disable(state, crtc); 2187 2188 if (DISPLAY_VER(display) != 2) 2189 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 2190 2191 if (!display->wm.funcs->initial_watermarks) 2192 intel_update_watermarks(display); 2193 2194 /* clock the pipe down to 640x480@60 to potentially save power */ 2195 if (display->platform.i830) 2196 i830_enable_pipe(display, pipe); 2197 } 2198 2199 void intel_encoder_destroy(struct drm_encoder *encoder) 2200 { 2201 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2202 2203 drm_encoder_cleanup(encoder); 2204 kfree(intel_encoder); 2205 } 2206 2207 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2208 { 2209 struct intel_display *display = to_intel_display(crtc); 2210 2211 /* GDG double wide on either pipe, otherwise pipe A only */ 2212 return HAS_DOUBLE_WIDE(display) && 2213 (crtc->pipe == PIPE_A || display->platform.i915g); 2214 } 2215 2216 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2217 { 2218 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2219 struct drm_rect src; 2220 2221 /* 2222 * We only use IF-ID interlacing. If we ever use 2223 * PF-ID we'll need to adjust the pixel_rate here. 2224 */ 2225 2226 if (!crtc_state->pch_pfit.enabled) 2227 return pixel_rate; 2228 2229 drm_rect_init(&src, 0, 0, 2230 drm_rect_width(&crtc_state->pipe_src) << 16, 2231 drm_rect_height(&crtc_state->pipe_src) << 16); 2232 2233 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2234 pixel_rate); 2235 } 2236 2237 static u32 ilk_pipe_pixel_rate_cdclk(const struct intel_crtc_state *crtc_state) 2238 { 2239 struct intel_display *display = to_intel_display(crtc_state); 2240 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2241 unsigned int ppc = HAS_2PPC(display) ? 2 : 1; 2242 struct drm_rect src; 2243 2244 /* 2245 * We only use IF-ID interlacing. If we ever use 2246 * PF-ID we'll need to adjust the pixel_rate here. 2247 */ 2248 2249 if (!crtc_state->pch_pfit.enabled) 2250 return pixel_rate; 2251 2252 drm_rect_init(&src, 0, 0, 2253 drm_rect_width(&crtc_state->pipe_src) << 16, 2254 drm_rect_height(&crtc_state->pipe_src) << 16); 2255 2256 return intel_adjusted_rate_cdclk(&src, &crtc_state->pch_pfit.dst, 2257 pixel_rate, ppc); 2258 } 2259 2260 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2261 const struct drm_display_mode *timings) 2262 { 2263 mode->hdisplay = timings->crtc_hdisplay; 2264 mode->htotal = timings->crtc_htotal; 2265 mode->hsync_start = timings->crtc_hsync_start; 2266 mode->hsync_end = timings->crtc_hsync_end; 2267 2268 mode->vdisplay = timings->crtc_vdisplay; 2269 mode->vtotal = timings->crtc_vtotal; 2270 mode->vsync_start = timings->crtc_vsync_start; 2271 mode->vsync_end = timings->crtc_vsync_end; 2272 2273 mode->flags = timings->flags; 2274 mode->type = DRM_MODE_TYPE_DRIVER; 2275 2276 mode->clock = timings->crtc_clock; 2277 2278 drm_mode_set_name(mode); 2279 } 2280 2281 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2282 { 2283 struct intel_display *display = to_intel_display(crtc_state); 2284 2285 if (HAS_GMCH(display)) { 2286 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2287 crtc_state->pixel_rate = 2288 crtc_state->hw.pipe_mode.crtc_clock; 2289 crtc_state->pixel_rate_cdclk = crtc_state->pixel_rate; 2290 } else { 2291 crtc_state->pixel_rate = 2292 ilk_pipe_pixel_rate(crtc_state); 2293 crtc_state->pixel_rate_cdclk = 2294 ilk_pipe_pixel_rate_cdclk(crtc_state); 2295 } 2296 } 2297 2298 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2299 struct drm_display_mode *mode) 2300 { 2301 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2302 2303 if (num_pipes == 1) 2304 return; 2305 2306 mode->crtc_clock /= num_pipes; 2307 mode->crtc_hdisplay /= num_pipes; 2308 mode->crtc_hblank_start /= num_pipes; 2309 mode->crtc_hblank_end /= num_pipes; 2310 mode->crtc_hsync_start /= num_pipes; 2311 mode->crtc_hsync_end /= num_pipes; 2312 mode->crtc_htotal /= num_pipes; 2313 } 2314 2315 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2316 struct drm_display_mode *mode) 2317 { 2318 int overlap = crtc_state->splitter.pixel_overlap; 2319 int n = crtc_state->splitter.link_count; 2320 2321 if (!crtc_state->splitter.enable) 2322 return; 2323 2324 /* 2325 * eDP MSO uses segment timings from EDID for transcoder 2326 * timings, but full mode for everything else. 2327 * 2328 * h_full = (h_segment - pixel_overlap) * link_count 2329 */ 2330 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2331 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2332 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2333 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2334 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2335 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2336 mode->crtc_clock *= n; 2337 } 2338 2339 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2340 { 2341 struct drm_display_mode *mode = &crtc_state->hw.mode; 2342 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2343 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2344 2345 /* 2346 * Start with the adjusted_mode crtc timings, which 2347 * have been filled with the transcoder timings. 2348 */ 2349 drm_mode_copy(pipe_mode, adjusted_mode); 2350 2351 /* Expand MSO per-segment transcoder timings to full */ 2352 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2353 2354 /* 2355 * We want the full numbers in adjusted_mode normal timings, 2356 * adjusted_mode crtc timings are left with the raw transcoder 2357 * timings. 2358 */ 2359 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2360 2361 /* Populate the "user" mode with full numbers */ 2362 drm_mode_copy(mode, pipe_mode); 2363 intel_mode_from_crtc_timings(mode, mode); 2364 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2365 intel_crtc_num_joined_pipes(crtc_state); 2366 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2367 2368 /* Derive per-pipe timings in case joiner is used */ 2369 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2370 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2371 2372 intel_crtc_compute_pixel_rate(crtc_state); 2373 } 2374 2375 void intel_encoder_get_config(struct intel_encoder *encoder, 2376 struct intel_crtc_state *crtc_state) 2377 { 2378 encoder->get_config(encoder, crtc_state); 2379 2380 intel_crtc_readout_derived_state(crtc_state); 2381 } 2382 2383 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2384 { 2385 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2386 int width, height; 2387 2388 if (num_pipes == 1) 2389 return; 2390 2391 width = drm_rect_width(&crtc_state->pipe_src); 2392 height = drm_rect_height(&crtc_state->pipe_src); 2393 2394 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2395 width / num_pipes, height); 2396 } 2397 2398 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2399 { 2400 struct intel_display *display = to_intel_display(crtc_state); 2401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2402 2403 intel_joiner_compute_pipe_src(crtc_state); 2404 2405 /* 2406 * Pipe horizontal size must be even in: 2407 * - DVO ganged mode 2408 * - LVDS dual channel mode 2409 * - Double wide pipe 2410 */ 2411 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2412 if (crtc_state->double_wide) { 2413 drm_dbg_kms(display->drm, 2414 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2415 crtc->base.base.id, crtc->base.name); 2416 return -EINVAL; 2417 } 2418 2419 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2420 intel_is_dual_link_lvds(display)) { 2421 drm_dbg_kms(display->drm, 2422 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2423 crtc->base.base.id, crtc->base.name); 2424 return -EINVAL; 2425 } 2426 } 2427 2428 return 0; 2429 } 2430 2431 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2432 { 2433 struct intel_display *display = to_intel_display(crtc_state); 2434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2435 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2436 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2437 int clock_limit = display->cdclk.max_dotclk_freq; 2438 2439 /* 2440 * Start with the adjusted_mode crtc timings, which 2441 * have been filled with the transcoder timings. 2442 */ 2443 drm_mode_copy(pipe_mode, adjusted_mode); 2444 2445 /* Expand MSO per-segment transcoder timings to full */ 2446 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2447 2448 /* Derive per-pipe timings in case joiner is used */ 2449 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2450 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2451 2452 if (DISPLAY_VER(display) < 4) { 2453 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; 2454 2455 /* 2456 * Enable double wide mode when the dot clock 2457 * is > 90% of the (display) core speed. 2458 */ 2459 if (intel_crtc_supports_double_wide(crtc) && 2460 pipe_mode->crtc_clock > clock_limit) { 2461 clock_limit = display->cdclk.max_dotclk_freq; 2462 crtc_state->double_wide = true; 2463 } 2464 } 2465 2466 if (pipe_mode->crtc_clock > clock_limit) { 2467 drm_dbg_kms(display->drm, 2468 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2469 crtc->base.base.id, crtc->base.name, 2470 pipe_mode->crtc_clock, clock_limit, 2471 str_yes_no(crtc_state->double_wide)); 2472 return -EINVAL; 2473 } 2474 2475 return 0; 2476 } 2477 2478 static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state) 2479 { 2480 struct intel_display *display = to_intel_display(crtc_state); 2481 int set_context_latency = 0; 2482 2483 if (!HAS_DSB(display)) 2484 return 0; 2485 2486 set_context_latency = max(set_context_latency, 2487 intel_psr_min_set_context_latency(crtc_state)); 2488 2489 return set_context_latency; 2490 } 2491 2492 static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state, 2493 struct intel_crtc *crtc) 2494 { 2495 struct intel_display *display = to_intel_display(state); 2496 struct intel_crtc_state *crtc_state = 2497 intel_atomic_get_new_crtc_state(state, crtc); 2498 struct drm_display_mode *adjusted_mode = 2499 &crtc_state->hw.adjusted_mode; 2500 int set_context_latency, max_vblank_delay; 2501 2502 set_context_latency = intel_crtc_set_context_latency(crtc_state); 2503 2504 max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1; 2505 2506 if (set_context_latency > max_vblank_delay) { 2507 drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n", 2508 crtc->base.base.id, crtc->base.name, 2509 set_context_latency, 2510 max_vblank_delay); 2511 return -EINVAL; 2512 } 2513 2514 crtc_state->set_context_latency = set_context_latency; 2515 adjusted_mode->crtc_vblank_start += set_context_latency; 2516 2517 return 0; 2518 } 2519 2520 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2521 struct intel_crtc *crtc) 2522 { 2523 struct intel_crtc_state *crtc_state = 2524 intel_atomic_get_new_crtc_state(state, crtc); 2525 int ret; 2526 2527 ret = intel_dpll_crtc_compute_clock(state, crtc); 2528 if (ret) 2529 return ret; 2530 2531 ret = intel_crtc_compute_set_context_latency(state, crtc); 2532 if (ret) 2533 return ret; 2534 2535 ret = intel_crtc_compute_pipe_src(crtc_state); 2536 if (ret) 2537 return ret; 2538 2539 ret = intel_crtc_compute_pipe_mode(crtc_state); 2540 if (ret) 2541 return ret; 2542 2543 intel_crtc_compute_pixel_rate(crtc_state); 2544 2545 if (crtc_state->has_pch_encoder) 2546 return ilk_fdi_compute_config(crtc, crtc_state); 2547 2548 intel_vrr_compute_guardband(crtc_state); 2549 2550 return 0; 2551 } 2552 2553 static void 2554 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2555 { 2556 while (*num > DATA_LINK_M_N_MASK || 2557 *den > DATA_LINK_M_N_MASK) { 2558 *num >>= 1; 2559 *den >>= 1; 2560 } 2561 } 2562 2563 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2564 u32 m, u32 n, u32 constant_n) 2565 { 2566 if (constant_n) 2567 *ret_n = constant_n; 2568 else 2569 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2570 2571 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2572 intel_reduce_m_n_ratio(ret_m, ret_n); 2573 } 2574 2575 void 2576 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 2577 int pixel_clock, int link_clock, 2578 int bw_overhead, 2579 struct intel_link_m_n *m_n) 2580 { 2581 u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); 2582 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, 2583 bw_overhead); 2584 u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); 2585 2586 /* 2587 * Windows/BIOS uses fixed M/N values always. Follow suit. 2588 * 2589 * Also several DP dongles in particular seem to be fussy 2590 * about too large link M/N values. Presumably the 20bit 2591 * value used by Windows/BIOS is acceptable to everyone. 2592 */ 2593 m_n->tu = 64; 2594 compute_m_n(&m_n->data_m, &m_n->data_n, 2595 data_m, data_n, 2596 0x8000000); 2597 2598 compute_m_n(&m_n->link_m, &m_n->link_n, 2599 pixel_clock, link_symbol_clock, 2600 0x80000); 2601 } 2602 2603 void intel_panel_sanitize_ssc(struct intel_display *display) 2604 { 2605 /* 2606 * There may be no VBT; and if the BIOS enabled SSC we can 2607 * just keep using it to avoid unnecessary flicker. Whereas if the 2608 * BIOS isn't using it, don't assume it will work even if the VBT 2609 * indicates as much. 2610 */ 2611 if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { 2612 bool bios_lvds_use_ssc = intel_de_read(display, 2613 PCH_DREF_CONTROL) & 2614 DREF_SSC1_ENABLE; 2615 2616 if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2617 drm_dbg_kms(display->drm, 2618 "SSC %s by BIOS, overriding VBT which says %s\n", 2619 str_enabled_disabled(bios_lvds_use_ssc), 2620 str_enabled_disabled(display->vbt.lvds_use_ssc)); 2621 display->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2622 } 2623 } 2624 } 2625 2626 void intel_zero_m_n(struct intel_link_m_n *m_n) 2627 { 2628 /* corresponds to 0 register value */ 2629 memset(m_n, 0, sizeof(*m_n)); 2630 m_n->tu = 1; 2631 } 2632 2633 void intel_set_m_n(struct intel_display *display, 2634 const struct intel_link_m_n *m_n, 2635 intel_reg_t data_m_reg, intel_reg_t data_n_reg, 2636 intel_reg_t link_m_reg, intel_reg_t link_n_reg) 2637 { 2638 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2639 intel_de_write(display, data_n_reg, m_n->data_n); 2640 intel_de_write(display, link_m_reg, m_n->link_m); 2641 /* 2642 * On BDW+ writing LINK_N arms the double buffered update 2643 * of all the M/N registers, so it must be written last. 2644 */ 2645 intel_de_write(display, link_n_reg, m_n->link_n); 2646 } 2647 2648 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 2649 enum transcoder transcoder) 2650 { 2651 if (display->platform.haswell) 2652 return transcoder == TRANSCODER_EDP; 2653 2654 return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; 2655 } 2656 2657 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2658 enum transcoder transcoder, 2659 const struct intel_link_m_n *m_n) 2660 { 2661 struct intel_display *display = to_intel_display(crtc); 2662 enum pipe pipe = crtc->pipe; 2663 2664 if (DISPLAY_VER(display) >= 5) 2665 intel_set_m_n(display, m_n, 2666 PIPE_DATA_M1(display, transcoder), 2667 PIPE_DATA_N1(display, transcoder), 2668 PIPE_LINK_M1(display, transcoder), 2669 PIPE_LINK_N1(display, transcoder)); 2670 else 2671 intel_set_m_n(display, m_n, 2672 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2673 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2674 } 2675 2676 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2677 enum transcoder transcoder, 2678 const struct intel_link_m_n *m_n) 2679 { 2680 struct intel_display *display = to_intel_display(crtc); 2681 2682 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 2683 return; 2684 2685 intel_set_m_n(display, m_n, 2686 PIPE_DATA_M2(display, transcoder), 2687 PIPE_DATA_N2(display, transcoder), 2688 PIPE_LINK_M2(display, transcoder), 2689 PIPE_LINK_N2(display, transcoder)); 2690 } 2691 2692 static bool 2693 transcoder_has_vrr(const struct intel_crtc_state *crtc_state) 2694 { 2695 struct intel_display *display = to_intel_display(crtc_state); 2696 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2697 2698 return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder); 2699 } 2700 2701 void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state, 2702 enum transcoder transcoder) 2703 { 2704 struct intel_display *display = to_intel_display(crtc_state); 2705 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2706 enum pipe pipe = crtc->pipe; 2707 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2708 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2709 int vsyncshift = 0; 2710 2711 drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder)); 2712 2713 /* We need to be careful not to changed the adjusted mode, for otherwise 2714 * the hw state checker will get angry at the mismatch. */ 2715 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2716 crtc_vtotal = adjusted_mode->crtc_vtotal; 2717 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2718 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2719 2720 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2721 /* the chip adds 2 halflines automatically */ 2722 crtc_vtotal -= 1; 2723 crtc_vblank_end -= 1; 2724 2725 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2726 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2727 else 2728 vsyncshift = adjusted_mode->crtc_hsync_start - 2729 adjusted_mode->crtc_htotal / 2; 2730 if (vsyncshift < 0) 2731 vsyncshift += adjusted_mode->crtc_htotal; 2732 } 2733 2734 /* 2735 * VBLANK_START no longer works on ADL+, instead we must use 2736 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2737 */ 2738 if (DISPLAY_VER(display) >= 13) { 2739 intel_de_write(display, 2740 TRANS_SET_CONTEXT_LATENCY(display, transcoder), 2741 crtc_state->set_context_latency); 2742 2743 /* 2744 * VBLANK_START not used by hw, just clear it 2745 * to make it stand out in register dumps. 2746 */ 2747 crtc_vblank_start = 1; 2748 } else if (DISPLAY_VER(display) == 12) { 2749 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2750 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2751 } 2752 2753 if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35) 2754 intel_de_write(display, 2755 TRANS_VSYNCSHIFT(display, transcoder), 2756 vsyncshift); 2757 2758 intel_de_write(display, TRANS_HTOTAL(display, transcoder), 2759 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2760 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2761 intel_de_write(display, TRANS_HBLANK(display, transcoder), 2762 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2763 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2764 intel_de_write(display, TRANS_HSYNC(display, transcoder), 2765 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2766 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2767 2768 if (display->platform.novalake && 2769 IS_DISPLAY_STEP(display, STEP_A0, STEP_C0)) 2770 crtc_vtotal = 1; 2771 2772 intel_de_write(display, TRANS_VTOTAL(display, transcoder), 2773 VACTIVE(crtc_vdisplay - 1) | 2774 VTOTAL(crtc_vtotal - 1)); 2775 intel_de_write(display, TRANS_VBLANK(display, transcoder), 2776 VBLANK_START(crtc_vblank_start - 1) | 2777 VBLANK_END(crtc_vblank_end - 1)); 2778 intel_de_write(display, TRANS_VSYNC(display, transcoder), 2779 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2780 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2781 2782 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2783 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2784 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2785 * bits. */ 2786 if (display->platform.haswell && transcoder == TRANSCODER_EDP && 2787 (pipe == PIPE_B || pipe == PIPE_C)) 2788 intel_de_write(display, TRANS_VTOTAL(display, pipe), 2789 VACTIVE(crtc_vdisplay - 1) | 2790 VTOTAL(crtc_vtotal - 1)); 2791 2792 if (DISPLAY_VER(display) >= 30 && 2793 transcoder != TRANSCODER_CMTG0 && 2794 transcoder != TRANSCODER_CMTG1) { 2795 /* 2796 * Address issues for resolutions with high refresh rate that 2797 * have small Hblank, specifically where Hblank is smaller than 2798 * one MTP. Simulations indicate this will address the 2799 * jitter issues that currently causes BS to be immediately 2800 * followed by BE which DPRX devices are unable to handle. 2801 * https://groups.vesa.org/wg/DP/document/20494 2802 */ 2803 intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder), 2804 crtc_state->min_hblank); 2805 } 2806 } 2807 2808 void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state, 2809 enum transcoder transcoder) 2810 { 2811 struct intel_display *display = to_intel_display(crtc_state); 2812 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2813 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2814 2815 drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder)); 2816 2817 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2818 crtc_vtotal = adjusted_mode->crtc_vtotal; 2819 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2820 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2821 2822 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2823 /* the chip adds 2 halflines automatically */ 2824 crtc_vtotal -= 1; 2825 crtc_vblank_end -= 1; 2826 } 2827 2828 if (DISPLAY_VER(display) >= 13) { 2829 intel_de_write(display, 2830 TRANS_SET_CONTEXT_LATENCY(display, transcoder), 2831 crtc_state->set_context_latency); 2832 2833 /* 2834 * VBLANK_START not used by hw, just clear it 2835 * to make it stand out in register dumps. 2836 */ 2837 crtc_vblank_start = 1; 2838 } else if (DISPLAY_VER(display) == 12) { 2839 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2840 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2841 } 2842 2843 /* 2844 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. 2845 * But let's write it anyway to keep the state checker happy. 2846 */ 2847 intel_de_write(display, TRANS_VBLANK(display, transcoder), 2848 VBLANK_START(crtc_vblank_start - 1) | 2849 VBLANK_END(crtc_vblank_end - 1)); 2850 2851 /* 2852 * DP doesn't have vertical sync, so TRANS_VSYNC only affects 2853 * the position of the vsync interrupt (and does so even when 2854 * using the VRR timing generator!). Thus updating TRANS_VSYNC 2855 * here seems fine even if it isn't double buffered. 2856 */ 2857 intel_de_write(display, TRANS_VSYNC(display, transcoder), 2858 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2859 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2860 2861 /* 2862 * The double buffer latch point for TRANS_VTOTAL 2863 * is the transcoder's undelayed vblank. 2864 */ 2865 if (display->platform.novalake && 2866 IS_DISPLAY_STEP(display, STEP_A0, STEP_C0)) 2867 crtc_vtotal = 1; 2868 2869 intel_de_write(display, TRANS_VTOTAL(display, transcoder), 2870 VACTIVE(crtc_vdisplay - 1) | 2871 VTOTAL(crtc_vtotal - 1)); 2872 } 2873 2874 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2875 { 2876 struct intel_display *display = to_intel_display(crtc_state); 2877 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2878 int width = drm_rect_width(&crtc_state->pipe_src); 2879 int height = drm_rect_height(&crtc_state->pipe_src); 2880 enum pipe pipe = crtc->pipe; 2881 2882 /* pipesrc controls the size that is scaled from, which should 2883 * always be the user's requested size. 2884 */ 2885 intel_de_write(display, PIPESRC(display, pipe), 2886 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2887 } 2888 2889 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2890 { 2891 struct intel_display *display = to_intel_display(crtc_state); 2892 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2893 2894 if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35) 2895 return false; 2896 2897 if (DISPLAY_VER(display) >= 9 || 2898 display->platform.broadwell || display->platform.haswell) 2899 return intel_de_read(display, 2900 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2901 else 2902 return intel_de_read(display, 2903 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2904 } 2905 2906 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2907 struct intel_crtc_state *pipe_config) 2908 { 2909 struct intel_display *display = to_intel_display(crtc); 2910 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2911 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2912 u32 tmp; 2913 2914 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); 2915 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2916 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2917 2918 if (!transcoder_is_dsi(cpu_transcoder)) { 2919 tmp = intel_de_read(display, 2920 TRANS_HBLANK(display, cpu_transcoder)); 2921 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2922 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2923 } 2924 2925 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); 2926 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2927 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2928 2929 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); 2930 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2931 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2932 2933 /* FIXME TGL+ DSI transcoders have this! */ 2934 if (!transcoder_is_dsi(cpu_transcoder)) { 2935 tmp = intel_de_read(display, 2936 TRANS_VBLANK(display, cpu_transcoder)); 2937 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2938 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2939 } 2940 tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)); 2941 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2942 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2943 2944 if (intel_pipe_is_interlaced(pipe_config)) { 2945 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2946 adjusted_mode->crtc_vtotal += 1; 2947 adjusted_mode->crtc_vblank_end += 1; 2948 } 2949 2950 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) { 2951 pipe_config->set_context_latency = 2952 intel_de_read(display, 2953 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); 2954 adjusted_mode->crtc_vblank_start = 2955 adjusted_mode->crtc_vdisplay + 2956 pipe_config->set_context_latency; 2957 } else if (DISPLAY_VER(display) == 12) { 2958 /* 2959 * TGL doesn't have a dedicated register for SCL. 2960 * Instead, the hardware derives SCL from the difference between 2961 * TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive. 2962 * To reflect the HW behaviour, readout the value for SCL as 2963 * Vblank start - Vactive. 2964 */ 2965 pipe_config->set_context_latency = 2966 adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 2967 } 2968 2969 if (DISPLAY_VER(display) >= 30) 2970 pipe_config->min_hblank = intel_de_read(display, 2971 DP_MIN_HBLANK_CTL(cpu_transcoder)); 2972 } 2973 2974 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2975 { 2976 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2977 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2978 enum pipe primary_pipe, pipe = crtc->pipe; 2979 int width; 2980 2981 if (num_pipes == 1) 2982 return; 2983 2984 primary_pipe = joiner_primary_pipe(crtc_state); 2985 width = drm_rect_width(&crtc_state->pipe_src); 2986 2987 drm_rect_translate_to(&crtc_state->pipe_src, 2988 (pipe - primary_pipe) * width, 0); 2989 } 2990 2991 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2992 struct intel_crtc_state *pipe_config) 2993 { 2994 struct intel_display *display = to_intel_display(crtc); 2995 u32 tmp; 2996 2997 tmp = intel_de_read(display, PIPESRC(display, crtc->pipe)); 2998 2999 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3000 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3001 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3002 3003 intel_joiner_adjust_pipe_src(pipe_config); 3004 } 3005 3006 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3007 { 3008 struct intel_display *display = to_intel_display(crtc_state); 3009 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3010 u32 val = 0; 3011 3012 /* 3013 * - We keep both pipes enabled on 830 3014 * - During modeset the pipe is still disabled and must remain so 3015 * - During fastset the pipe is already enabled and must remain so 3016 */ 3017 if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state)) 3018 val |= TRANSCONF_ENABLE; 3019 3020 if (crtc_state->double_wide) 3021 val |= TRANSCONF_DOUBLE_WIDE; 3022 3023 /* only g4x and later have fancy bpc/dither controls */ 3024 if (display->platform.g4x || display->platform.valleyview || 3025 display->platform.cherryview) { 3026 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3027 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3028 val |= TRANSCONF_DITHER_EN | 3029 TRANSCONF_DITHER_TYPE_SP; 3030 3031 switch (crtc_state->pipe_bpp) { 3032 default: 3033 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3034 MISSING_CASE(crtc_state->pipe_bpp); 3035 fallthrough; 3036 case 18: 3037 val |= TRANSCONF_BPC_6; 3038 break; 3039 case 24: 3040 val |= TRANSCONF_BPC_8; 3041 break; 3042 case 30: 3043 val |= TRANSCONF_BPC_10; 3044 break; 3045 } 3046 } 3047 3048 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3049 if (DISPLAY_VER(display) < 4 || 3050 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3051 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 3052 else 3053 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 3054 } else { 3055 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 3056 } 3057 3058 if ((display->platform.valleyview || display->platform.cherryview) && 3059 crtc_state->limited_color_range) 3060 val |= TRANSCONF_COLOR_RANGE_SELECT; 3061 3062 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3063 3064 if (crtc_state->wgc_enable) 3065 val |= TRANSCONF_WGC_ENABLE; 3066 3067 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3068 3069 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3070 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3071 } 3072 3073 static enum intel_output_format 3074 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 3075 { 3076 struct intel_display *display = to_intel_display(crtc); 3077 u32 tmp; 3078 3079 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3080 3081 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3082 /* 3083 * We support 4:2:0 in full blend mode only. 3084 * For xe3_lpd+ this is implied in YUV420 Enable bit. 3085 * Ensure the same for prior platforms in YUV420 Mode bit. 3086 */ 3087 if (DISPLAY_VER(display) < 30) 3088 drm_WARN_ON(display->drm, 3089 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3090 3091 return INTEL_OUTPUT_FORMAT_YCBCR420; 3092 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 3093 return INTEL_OUTPUT_FORMAT_YCBCR444; 3094 } else { 3095 return INTEL_OUTPUT_FORMAT_RGB; 3096 } 3097 } 3098 3099 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3100 struct intel_crtc_state *pipe_config) 3101 { 3102 struct intel_display *display = to_intel_display(crtc); 3103 enum intel_display_power_domain power_domain; 3104 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3105 struct ref_tracker *wakeref; 3106 bool ret = false; 3107 u32 tmp; 3108 3109 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3110 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3111 if (!wakeref) 3112 return false; 3113 3114 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3115 if (!(tmp & TRANSCONF_ENABLE)) 3116 goto out; 3117 3118 pipe_config->cpu_transcoder = cpu_transcoder; 3119 3120 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3121 pipe_config->sink_format = pipe_config->output_format; 3122 3123 if (display->platform.g4x || display->platform.valleyview || 3124 display->platform.cherryview) { 3125 switch (tmp & TRANSCONF_BPC_MASK) { 3126 case TRANSCONF_BPC_6: 3127 pipe_config->pipe_bpp = 18; 3128 break; 3129 case TRANSCONF_BPC_8: 3130 pipe_config->pipe_bpp = 24; 3131 break; 3132 case TRANSCONF_BPC_10: 3133 pipe_config->pipe_bpp = 30; 3134 break; 3135 default: 3136 MISSING_CASE(tmp); 3137 break; 3138 } 3139 } 3140 3141 if ((display->platform.valleyview || display->platform.cherryview) && 3142 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3143 pipe_config->limited_color_range = true; 3144 3145 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3146 3147 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3148 3149 if ((display->platform.valleyview || display->platform.cherryview) && 3150 (tmp & TRANSCONF_WGC_ENABLE)) 3151 pipe_config->wgc_enable = true; 3152 3153 intel_color_get_config(pipe_config); 3154 3155 if (HAS_DOUBLE_WIDE(display)) 3156 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3157 3158 intel_get_transcoder_timings(crtc, pipe_config); 3159 intel_get_pipe_src_size(crtc, pipe_config); 3160 3161 i9xx_pfit_get_config(pipe_config); 3162 3163 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); 3164 3165 if (DISPLAY_VER(display) >= 4) { 3166 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; 3167 pipe_config->pixel_multiplier = 3168 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3169 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3170 } else if (display->platform.i945g || display->platform.i945gm || 3171 display->platform.g33 || display->platform.pineview) { 3172 tmp = pipe_config->dpll_hw_state.i9xx.dpll; 3173 pipe_config->pixel_multiplier = 3174 ((tmp & SDVO_MULTIPLIER_MASK) 3175 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3176 } else { 3177 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3178 * port and will be fixed up in the encoder->get_config 3179 * function. */ 3180 pipe_config->pixel_multiplier = 1; 3181 } 3182 3183 if (display->platform.cherryview) 3184 chv_crtc_clock_get(pipe_config); 3185 else if (display->platform.valleyview) 3186 vlv_crtc_clock_get(pipe_config); 3187 else 3188 i9xx_crtc_clock_get(pipe_config); 3189 3190 /* 3191 * Normally the dotclock is filled in by the encoder .get_config() 3192 * but in case the pipe is enabled w/o any ports we need a sane 3193 * default. 3194 */ 3195 pipe_config->hw.adjusted_mode.crtc_clock = 3196 pipe_config->port_clock / pipe_config->pixel_multiplier; 3197 3198 ret = true; 3199 3200 out: 3201 intel_display_power_put(display, power_domain, wakeref); 3202 3203 return ret; 3204 } 3205 3206 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3207 { 3208 struct intel_display *display = to_intel_display(crtc_state); 3209 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3210 u32 val = 0; 3211 3212 /* 3213 * - During modeset the pipe is still disabled and must remain so 3214 * - During fastset the pipe is already enabled and must remain so 3215 */ 3216 if (!intel_crtc_needs_modeset(crtc_state)) 3217 val |= TRANSCONF_ENABLE; 3218 3219 switch (crtc_state->pipe_bpp) { 3220 default: 3221 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3222 MISSING_CASE(crtc_state->pipe_bpp); 3223 fallthrough; 3224 case 18: 3225 val |= TRANSCONF_BPC_6; 3226 break; 3227 case 24: 3228 val |= TRANSCONF_BPC_8; 3229 break; 3230 case 30: 3231 val |= TRANSCONF_BPC_10; 3232 break; 3233 case 36: 3234 val |= TRANSCONF_BPC_12; 3235 break; 3236 } 3237 3238 if (crtc_state->dither) 3239 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3240 3241 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3242 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3243 else 3244 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3245 3246 /* 3247 * This would end up with an odd purple hue over 3248 * the entire display. Make sure we don't do it. 3249 */ 3250 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 3251 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3252 3253 if (crtc_state->limited_color_range && 3254 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3255 val |= TRANSCONF_COLOR_RANGE_SELECT; 3256 3257 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3258 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3259 3260 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3261 3262 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3263 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3264 3265 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3266 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3267 } 3268 3269 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3270 { 3271 struct intel_display *display = to_intel_display(crtc_state); 3272 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3273 u32 val = 0; 3274 3275 /* 3276 * - During modeset the pipe is still disabled and must remain so 3277 * - During fastset the pipe is already enabled and must remain so 3278 */ 3279 if (!intel_crtc_needs_modeset(crtc_state)) 3280 val |= TRANSCONF_ENABLE; 3281 3282 if (display->platform.haswell && crtc_state->dither) 3283 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3284 3285 if (DISPLAY_VER(display) < 35) { 3286 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3287 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3288 else 3289 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3290 } 3291 3292 if (display->platform.haswell && 3293 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3294 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3295 3296 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3297 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3298 } 3299 3300 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 3301 const struct intel_crtc_state *crtc_state) 3302 { 3303 struct intel_display *display = to_intel_display(crtc_state); 3304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3305 u32 val = 0; 3306 3307 switch (crtc_state->pipe_bpp) { 3308 case 18: 3309 val |= PIPE_MISC_BPC_6; 3310 break; 3311 case 24: 3312 val |= PIPE_MISC_BPC_8; 3313 break; 3314 case 30: 3315 val |= PIPE_MISC_BPC_10; 3316 break; 3317 case 36: 3318 /* Port output 12BPC defined for ADLP+ */ 3319 if (DISPLAY_VER(display) >= 13) 3320 val |= PIPE_MISC_BPC_12_ADLP; 3321 break; 3322 default: 3323 MISSING_CASE(crtc_state->pipe_bpp); 3324 break; 3325 } 3326 3327 if (crtc_state->dither) 3328 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3329 3330 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3331 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3332 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3333 3334 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3335 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : 3336 PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND; 3337 3338 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) 3339 val |= PIPE_MISC_HDR_MODE_PRECISION; 3340 3341 if (DISPLAY_VER(display) >= 12) 3342 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3343 3344 /* allow PSR with sprite enabled */ 3345 if (display->platform.broadwell) 3346 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3347 3348 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val); 3349 } 3350 3351 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3352 { 3353 struct intel_display *display = to_intel_display(crtc); 3354 u32 tmp; 3355 3356 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3357 3358 switch (tmp & PIPE_MISC_BPC_MASK) { 3359 case PIPE_MISC_BPC_6: 3360 return 18; 3361 case PIPE_MISC_BPC_8: 3362 return 24; 3363 case PIPE_MISC_BPC_10: 3364 return 30; 3365 /* 3366 * PORT OUTPUT 12 BPC defined for ADLP+. 3367 * 3368 * TODO: 3369 * For previous platforms with DSI interface, bits 5:7 3370 * are used for storing pipe_bpp irrespective of dithering. 3371 * Since the value of 12 BPC is not defined for these bits 3372 * on older platforms, need to find a workaround for 12 BPC 3373 * MIPI DSI HW readout. 3374 */ 3375 case PIPE_MISC_BPC_12_ADLP: 3376 if (DISPLAY_VER(display) >= 13) 3377 return 36; 3378 fallthrough; 3379 default: 3380 MISSING_CASE(tmp); 3381 return 0; 3382 } 3383 } 3384 3385 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3386 { 3387 /* 3388 * Account for spread spectrum to avoid 3389 * oversubscribing the link. Max center spread 3390 * is 2.5%; use 5% for safety's sake. 3391 */ 3392 u32 bps = target_clock * bpp * 21 / 20; 3393 return DIV_ROUND_UP(bps, link_bw * 8); 3394 } 3395 3396 void intel_get_m_n(struct intel_display *display, 3397 struct intel_link_m_n *m_n, 3398 intel_reg_t data_m_reg, intel_reg_t data_n_reg, 3399 intel_reg_t link_m_reg, intel_reg_t link_n_reg) 3400 { 3401 m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; 3402 m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; 3403 m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; 3404 m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; 3405 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; 3406 } 3407 3408 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3409 enum transcoder transcoder, 3410 struct intel_link_m_n *m_n) 3411 { 3412 struct intel_display *display = to_intel_display(crtc); 3413 enum pipe pipe = crtc->pipe; 3414 3415 if (DISPLAY_VER(display) >= 5) 3416 intel_get_m_n(display, m_n, 3417 PIPE_DATA_M1(display, transcoder), 3418 PIPE_DATA_N1(display, transcoder), 3419 PIPE_LINK_M1(display, transcoder), 3420 PIPE_LINK_N1(display, transcoder)); 3421 else 3422 intel_get_m_n(display, m_n, 3423 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3424 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3425 } 3426 3427 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3428 enum transcoder transcoder, 3429 struct intel_link_m_n *m_n) 3430 { 3431 struct intel_display *display = to_intel_display(crtc); 3432 3433 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 3434 return; 3435 3436 intel_get_m_n(display, m_n, 3437 PIPE_DATA_M2(display, transcoder), 3438 PIPE_DATA_N2(display, transcoder), 3439 PIPE_LINK_M2(display, transcoder), 3440 PIPE_LINK_N2(display, transcoder)); 3441 } 3442 3443 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3444 struct intel_crtc_state *pipe_config) 3445 { 3446 struct intel_display *display = to_intel_display(crtc); 3447 enum intel_display_power_domain power_domain; 3448 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3449 struct ref_tracker *wakeref; 3450 bool ret = false; 3451 u32 tmp; 3452 3453 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3454 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3455 if (!wakeref) 3456 return false; 3457 3458 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3459 if (!(tmp & TRANSCONF_ENABLE)) 3460 goto out; 3461 3462 pipe_config->cpu_transcoder = cpu_transcoder; 3463 3464 switch (tmp & TRANSCONF_BPC_MASK) { 3465 case TRANSCONF_BPC_6: 3466 pipe_config->pipe_bpp = 18; 3467 break; 3468 case TRANSCONF_BPC_8: 3469 pipe_config->pipe_bpp = 24; 3470 break; 3471 case TRANSCONF_BPC_10: 3472 pipe_config->pipe_bpp = 30; 3473 break; 3474 case TRANSCONF_BPC_12: 3475 pipe_config->pipe_bpp = 36; 3476 break; 3477 default: 3478 break; 3479 } 3480 3481 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3482 pipe_config->limited_color_range = true; 3483 3484 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3485 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3486 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3487 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3488 break; 3489 default: 3490 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3491 break; 3492 } 3493 3494 pipe_config->sink_format = pipe_config->output_format; 3495 3496 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3497 3498 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3499 3500 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3501 3502 intel_color_get_config(pipe_config); 3503 3504 pipe_config->pixel_multiplier = 1; 3505 3506 ilk_pch_get_config(pipe_config); 3507 3508 intel_get_transcoder_timings(crtc, pipe_config); 3509 intel_get_pipe_src_size(crtc, pipe_config); 3510 3511 ilk_pfit_get_config(pipe_config); 3512 3513 ret = true; 3514 3515 out: 3516 intel_display_power_put(display, power_domain, wakeref); 3517 3518 return ret; 3519 } 3520 3521 static u8 joiner_pipes(struct intel_display *display) 3522 { 3523 u8 pipes; 3524 3525 if (DISPLAY_VER(display) >= 12) 3526 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3527 else if (DISPLAY_VER(display) >= 11) 3528 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3529 else 3530 pipes = 0; 3531 3532 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; 3533 } 3534 3535 static bool transcoder_ddi_func_is_enabled(struct intel_display *display, 3536 enum transcoder cpu_transcoder) 3537 { 3538 enum intel_display_power_domain power_domain; 3539 u32 tmp = 0; 3540 3541 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3542 3543 with_intel_display_power_if_enabled(display, power_domain) 3544 tmp = intel_de_read(display, 3545 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3546 3547 return tmp & TRANS_DDI_FUNC_ENABLE; 3548 } 3549 3550 static void enabled_uncompressed_joiner_pipes(struct intel_display *display, 3551 u8 *primary_pipes, u8 *secondary_pipes) 3552 { 3553 struct intel_crtc *crtc; 3554 3555 *primary_pipes = 0; 3556 *secondary_pipes = 0; 3557 3558 if (!HAS_UNCOMPRESSED_JOINER(display)) 3559 return; 3560 3561 for_each_intel_crtc_in_pipe_mask(display, crtc, 3562 joiner_pipes(display)) { 3563 enum intel_display_power_domain power_domain; 3564 enum pipe pipe = crtc->pipe; 3565 3566 power_domain = POWER_DOMAIN_PIPE(pipe); 3567 with_intel_display_power_if_enabled(display, power_domain) { 3568 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3569 3570 if (tmp & UNCOMPRESSED_JOINER_PRIMARY) 3571 *primary_pipes |= BIT(pipe); 3572 if (tmp & UNCOMPRESSED_JOINER_SECONDARY) 3573 *secondary_pipes |= BIT(pipe); 3574 } 3575 } 3576 } 3577 3578 static void enabled_bigjoiner_pipes(struct intel_display *display, 3579 u8 *primary_pipes, u8 *secondary_pipes) 3580 { 3581 struct intel_crtc *crtc; 3582 3583 *primary_pipes = 0; 3584 *secondary_pipes = 0; 3585 3586 if (!HAS_BIGJOINER(display)) 3587 return; 3588 3589 for_each_intel_crtc_in_pipe_mask(display, crtc, 3590 joiner_pipes(display)) { 3591 enum intel_display_power_domain power_domain; 3592 enum pipe pipe = crtc->pipe; 3593 3594 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3595 with_intel_display_power_if_enabled(display, power_domain) { 3596 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3597 3598 if (!(tmp & BIG_JOINER_ENABLE)) 3599 continue; 3600 3601 if (tmp & PRIMARY_BIG_JOINER_ENABLE) 3602 *primary_pipes |= BIT(pipe); 3603 else 3604 *secondary_pipes |= BIT(pipe); 3605 } 3606 } 3607 } 3608 3609 static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes) 3610 { 3611 u8 secondary_pipes = 0; 3612 3613 for (int i = 1; i < num_pipes; i++) 3614 secondary_pipes |= primary_pipes << i; 3615 3616 return secondary_pipes; 3617 } 3618 3619 static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes) 3620 { 3621 return expected_secondary_pipes(uncompjoiner_primary_pipes, 2); 3622 } 3623 3624 static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes) 3625 { 3626 return expected_secondary_pipes(bigjoiner_primary_pipes, 2); 3627 } 3628 3629 static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes) 3630 { 3631 primary_pipes &= GENMASK(pipe, 0); 3632 3633 return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0; 3634 } 3635 3636 static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes) 3637 { 3638 return expected_secondary_pipes(ultrajoiner_primary_pipes, 4); 3639 } 3640 3641 static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes, 3642 u8 ultrajoiner_secondary_pipes) 3643 { 3644 return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3; 3645 } 3646 3647 static void enabled_ultrajoiner_pipes(struct intel_display *display, 3648 u8 *primary_pipes, u8 *secondary_pipes) 3649 { 3650 struct intel_crtc *crtc; 3651 3652 *primary_pipes = 0; 3653 *secondary_pipes = 0; 3654 3655 if (!HAS_ULTRAJOINER(display)) 3656 return; 3657 3658 for_each_intel_crtc_in_pipe_mask(display, crtc, 3659 joiner_pipes(display)) { 3660 enum intel_display_power_domain power_domain; 3661 enum pipe pipe = crtc->pipe; 3662 3663 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3664 with_intel_display_power_if_enabled(display, power_domain) { 3665 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3666 3667 if (!(tmp & ULTRA_JOINER_ENABLE)) 3668 continue; 3669 3670 if (tmp & PRIMARY_ULTRA_JOINER_ENABLE) 3671 *primary_pipes |= BIT(pipe); 3672 else 3673 *secondary_pipes |= BIT(pipe); 3674 } 3675 } 3676 } 3677 3678 static void enabled_joiner_pipes(struct intel_display *display, 3679 enum pipe pipe, 3680 u8 *primary_pipe, u8 *secondary_pipes) 3681 { 3682 u8 primary_ultrajoiner_pipes; 3683 u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes; 3684 u8 secondary_ultrajoiner_pipes; 3685 u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes; 3686 u8 ultrajoiner_pipes; 3687 u8 uncompressed_joiner_pipes, bigjoiner_pipes; 3688 3689 enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes, 3690 &secondary_ultrajoiner_pipes); 3691 /* 3692 * For some strange reason the last pipe in the set of four 3693 * shouldn't have ultrajoiner enable bit set in hardware. 3694 * Set the bit anyway to make life easier. 3695 */ 3696 drm_WARN_ON(display->drm, 3697 expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != 3698 secondary_ultrajoiner_pipes); 3699 secondary_ultrajoiner_pipes = 3700 fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes, 3701 secondary_ultrajoiner_pipes); 3702 3703 drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); 3704 3705 enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes, 3706 &secondary_uncompressed_joiner_pipes); 3707 3708 drm_WARN_ON(display->drm, 3709 (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0); 3710 3711 enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes, 3712 &secondary_bigjoiner_pipes); 3713 3714 drm_WARN_ON(display->drm, 3715 (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0); 3716 3717 ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes; 3718 uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes | 3719 secondary_uncompressed_joiner_pipes; 3720 bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes; 3721 3722 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes, 3723 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n", 3724 ultrajoiner_pipes, bigjoiner_pipes); 3725 3726 drm_WARN(display->drm, secondary_ultrajoiner_pipes != 3727 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3728 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n", 3729 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3730 secondary_ultrajoiner_pipes); 3731 3732 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0, 3733 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n", 3734 uncompressed_joiner_pipes, bigjoiner_pipes); 3735 3736 drm_WARN(display->drm, secondary_bigjoiner_pipes != 3737 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3738 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n", 3739 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3740 secondary_bigjoiner_pipes); 3741 3742 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes != 3743 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3744 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n", 3745 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3746 secondary_uncompressed_joiner_pipes); 3747 3748 *primary_pipe = 0; 3749 *secondary_pipes = 0; 3750 3751 if (ultrajoiner_pipes & BIT(pipe)) { 3752 *primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes); 3753 *secondary_pipes = secondary_ultrajoiner_pipes & 3754 expected_ultrajoiner_secondary_pipes(*primary_pipe); 3755 3756 drm_WARN(display->drm, 3757 expected_ultrajoiner_secondary_pipes(*primary_pipe) != 3758 *secondary_pipes, 3759 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3760 *primary_pipe, 3761 expected_ultrajoiner_secondary_pipes(*primary_pipe), 3762 *secondary_pipes); 3763 return; 3764 } 3765 3766 if (uncompressed_joiner_pipes & BIT(pipe)) { 3767 *primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes); 3768 *secondary_pipes = secondary_uncompressed_joiner_pipes & 3769 expected_uncompressed_joiner_secondary_pipes(*primary_pipe); 3770 3771 drm_WARN(display->drm, 3772 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) != 3773 *secondary_pipes, 3774 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3775 *primary_pipe, 3776 expected_uncompressed_joiner_secondary_pipes(*primary_pipe), 3777 *secondary_pipes); 3778 return; 3779 } 3780 3781 if (bigjoiner_pipes & BIT(pipe)) { 3782 *primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes); 3783 *secondary_pipes = secondary_bigjoiner_pipes & 3784 expected_bigjoiner_secondary_pipes(*primary_pipe); 3785 3786 drm_WARN(display->drm, 3787 expected_bigjoiner_secondary_pipes(*primary_pipe) != 3788 *secondary_pipes, 3789 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3790 *primary_pipe, 3791 expected_bigjoiner_secondary_pipes(*primary_pipe), 3792 *secondary_pipes); 3793 return; 3794 } 3795 } 3796 3797 static u16 hsw_panel_transcoders(struct intel_display *display) 3798 { 3799 u16 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3800 3801 if (DISPLAY_VER(display) >= 11) 3802 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3803 3804 return panel_transcoder_mask; 3805 } 3806 3807 static u16 hsw_enabled_transcoders(struct intel_crtc *crtc) 3808 { 3809 struct intel_display *display = to_intel_display(crtc); 3810 u16 panel_transcoder_mask = hsw_panel_transcoders(display); 3811 enum transcoder cpu_transcoder; 3812 u8 primary_pipe, secondary_pipes; 3813 u16 enabled_transcoders = 0; 3814 3815 /* 3816 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3817 * consistency and less surprising code; it's in always on power). 3818 */ 3819 for_each_cpu_transcoder_masked(display, cpu_transcoder, 3820 panel_transcoder_mask) { 3821 enum intel_display_power_domain power_domain; 3822 enum pipe trans_pipe; 3823 u32 tmp = 0; 3824 3825 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3826 with_intel_display_power_if_enabled(display, power_domain) 3827 tmp = intel_de_read(display, 3828 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3829 3830 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3831 continue; 3832 3833 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3834 default: 3835 drm_WARN(display->drm, 1, 3836 "unknown pipe linked to transcoder %s\n", 3837 transcoder_name(cpu_transcoder)); 3838 fallthrough; 3839 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3840 case TRANS_DDI_EDP_INPUT_A_ON: 3841 trans_pipe = PIPE_A; 3842 break; 3843 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3844 trans_pipe = PIPE_B; 3845 break; 3846 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3847 trans_pipe = PIPE_C; 3848 break; 3849 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3850 trans_pipe = PIPE_D; 3851 break; 3852 } 3853 3854 if (trans_pipe == crtc->pipe) 3855 enabled_transcoders |= BIT(cpu_transcoder); 3856 } 3857 3858 /* single pipe or joiner primary */ 3859 cpu_transcoder = (enum transcoder) crtc->pipe; 3860 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3861 enabled_transcoders |= BIT(cpu_transcoder); 3862 3863 /* joiner secondary -> consider the primary pipe's transcoder as well */ 3864 enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes); 3865 if (secondary_pipes & BIT(crtc->pipe)) { 3866 cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1; 3867 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3868 enabled_transcoders |= BIT(cpu_transcoder); 3869 } 3870 3871 return enabled_transcoders; 3872 } 3873 3874 static bool has_edp_transcoders(u16 enabled_transcoders) 3875 { 3876 return enabled_transcoders & BIT(TRANSCODER_EDP); 3877 } 3878 3879 static bool has_dsi_transcoders(u16 enabled_transcoders) 3880 { 3881 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3882 BIT(TRANSCODER_DSI_1)); 3883 } 3884 3885 static bool has_pipe_transcoders(u16 enabled_transcoders) 3886 { 3887 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3888 BIT(TRANSCODER_DSI_0) | 3889 BIT(TRANSCODER_DSI_1)); 3890 } 3891 3892 static void assert_enabled_transcoders(struct intel_display *display, 3893 u16 enabled_transcoders) 3894 { 3895 /* Only one type of transcoder please */ 3896 drm_WARN_ON(display->drm, 3897 has_edp_transcoders(enabled_transcoders) + 3898 has_dsi_transcoders(enabled_transcoders) + 3899 has_pipe_transcoders(enabled_transcoders) > 1); 3900 3901 /* Only DSI transcoders can be ganged */ 3902 drm_WARN_ON(display->drm, 3903 !has_dsi_transcoders(enabled_transcoders) && 3904 !is_power_of_2(enabled_transcoders)); 3905 } 3906 3907 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3908 struct intel_crtc_state *pipe_config, 3909 struct intel_display_power_domain_set *power_domain_set) 3910 { 3911 struct intel_display *display = to_intel_display(crtc); 3912 unsigned long enabled_transcoders; 3913 u32 tmp; 3914 3915 enabled_transcoders = hsw_enabled_transcoders(crtc); 3916 if (!enabled_transcoders) 3917 return false; 3918 3919 assert_enabled_transcoders(display, enabled_transcoders); 3920 3921 /* 3922 * With the exception of DSI we should only ever have 3923 * a single enabled transcoder. With DSI let's just 3924 * pick the first one. 3925 */ 3926 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3927 3928 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3929 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3930 return false; 3931 3932 if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) { 3933 tmp = intel_de_read(display, 3934 TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder)); 3935 3936 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3937 pipe_config->pch_pfit.force_thru = true; 3938 } 3939 3940 tmp = intel_de_read(display, 3941 TRANSCONF(display, pipe_config->cpu_transcoder)); 3942 3943 return tmp & TRANSCONF_ENABLE; 3944 } 3945 3946 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3947 struct intel_crtc_state *pipe_config, 3948 struct intel_display_power_domain_set *power_domain_set) 3949 { 3950 struct intel_display *display = to_intel_display(crtc); 3951 enum transcoder cpu_transcoder; 3952 enum port port; 3953 u32 tmp; 3954 3955 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3956 if (port == PORT_A) 3957 cpu_transcoder = TRANSCODER_DSI_A; 3958 else 3959 cpu_transcoder = TRANSCODER_DSI_C; 3960 3961 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3962 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3963 continue; 3964 3965 /* 3966 * The PLL needs to be enabled with a valid divider 3967 * configuration, otherwise accessing DSI registers will hang 3968 * the machine. See BSpec North Display Engine 3969 * registers/MIPI[BXT]. We can break out here early, since we 3970 * need the same DSI PLL to be enabled for both DSI ports. 3971 */ 3972 if (!bxt_dsi_pll_is_enabled(display)) 3973 break; 3974 3975 /* XXX: this works for video mode only */ 3976 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); 3977 if (!(tmp & DPI_ENABLE)) 3978 continue; 3979 3980 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 3981 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3982 continue; 3983 3984 pipe_config->cpu_transcoder = cpu_transcoder; 3985 break; 3986 } 3987 3988 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3989 } 3990 3991 static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) 3992 { 3993 struct intel_display *display = to_intel_display(crtc_state); 3994 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3995 u8 primary_pipe, secondary_pipes; 3996 enum pipe pipe = crtc->pipe; 3997 3998 enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes); 3999 4000 if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0) 4001 return; 4002 4003 crtc_state->joiner_pipes = primary_pipe | secondary_pipes; 4004 } 4005 4006 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4007 struct intel_crtc_state *pipe_config) 4008 { 4009 struct intel_display *display = to_intel_display(crtc); 4010 bool active; 4011 u32 tmp; 4012 4013 if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 4014 POWER_DOMAIN_PIPE(crtc->pipe))) 4015 return false; 4016 4017 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 4018 4019 if ((display->platform.geminilake || display->platform.broxton) && 4020 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 4021 drm_WARN_ON(display->drm, active); 4022 active = true; 4023 } 4024 4025 if (!active) 4026 goto out; 4027 4028 intel_joiner_get_config(pipe_config); 4029 intel_dsc_get_config(pipe_config); 4030 4031 /* intel_vrr_get_config() depends on .framestart_delay */ 4032 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4033 tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); 4034 4035 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4036 } else { 4037 /* no idea if this is correct */ 4038 pipe_config->framestart_delay = 1; 4039 } 4040 4041 /* 4042 * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY 4043 * readout done by intel_get_transcoder_timings(). 4044 */ 4045 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4046 DISPLAY_VER(display) >= 11) 4047 intel_get_transcoder_timings(crtc, pipe_config); 4048 4049 if (transcoder_has_vrr(pipe_config)) 4050 intel_vrr_get_config(pipe_config); 4051 4052 intel_get_pipe_src_size(crtc, pipe_config); 4053 4054 if (display->platform.haswell) { 4055 u32 tmp = intel_de_read(display, 4056 TRANSCONF(display, pipe_config->cpu_transcoder)); 4057 4058 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 4059 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4060 else 4061 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4062 } else { 4063 pipe_config->output_format = 4064 bdw_get_pipe_misc_output_format(crtc); 4065 } 4066 4067 pipe_config->sink_format = pipe_config->output_format; 4068 4069 intel_color_get_config(pipe_config); 4070 4071 tmp = intel_de_read(display, WM_LINETIME(crtc->pipe)); 4072 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4073 if (display->platform.broadwell || display->platform.haswell) 4074 pipe_config->ips_linetime = 4075 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4076 4077 if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 4078 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4079 if (DISPLAY_VER(display) >= 9) 4080 skl_scaler_get_config(pipe_config); 4081 else 4082 ilk_pfit_get_config(pipe_config); 4083 } 4084 4085 hsw_ips_get_config(pipe_config); 4086 4087 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4088 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4089 pipe_config->pixel_multiplier = 4090 intel_de_read(display, 4091 TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1; 4092 } else { 4093 pipe_config->pixel_multiplier = 1; 4094 } 4095 4096 out: 4097 intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); 4098 4099 return active; 4100 } 4101 4102 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4103 { 4104 struct intel_display *display = to_intel_display(crtc_state); 4105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4106 4107 if (!display->modeset.funcs->get_pipe_config(crtc, crtc_state)) 4108 return false; 4109 4110 crtc_state->hw.active = true; 4111 4112 intel_crtc_readout_derived_state(crtc_state); 4113 4114 return true; 4115 } 4116 4117 int intel_dotclock_calculate(int link_freq, 4118 const struct intel_link_m_n *m_n) 4119 { 4120 /* 4121 * The calculation for the data clock -> pixel clock is: 4122 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4123 * But we want to avoid losing precision if possible, so: 4124 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4125 * 4126 * and for link freq (10kbs units) -> pixel clock it is: 4127 * link_symbol_clock = link_freq * 10 / link_symbol_size 4128 * pixel_clock = (m * link_symbol_clock) / n 4129 * or for more precision: 4130 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) 4131 */ 4132 4133 if (!m_n->link_n) 4134 return 0; 4135 4136 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), 4137 m_n->link_n * intel_dp_link_symbol_size(link_freq)); 4138 } 4139 4140 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4141 { 4142 int dotclock; 4143 4144 if (intel_crtc_has_dp_encoder(pipe_config)) 4145 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4146 &pipe_config->dp_m_n); 4147 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4148 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4149 pipe_config->pipe_bpp); 4150 else 4151 dotclock = pipe_config->port_clock; 4152 4153 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4154 !intel_crtc_has_dp_encoder(pipe_config)) 4155 dotclock *= 2; 4156 4157 if (pipe_config->pixel_multiplier) 4158 dotclock /= pipe_config->pixel_multiplier; 4159 4160 return dotclock; 4161 } 4162 4163 /* Returns the currently programmed mode of the given encoder. */ 4164 struct drm_display_mode * 4165 intel_encoder_current_mode(struct intel_encoder *encoder) 4166 { 4167 struct intel_display *display = to_intel_display(encoder); 4168 struct intel_crtc_state *crtc_state; 4169 struct drm_display_mode *mode; 4170 struct intel_crtc *crtc; 4171 enum pipe pipe; 4172 4173 if (!encoder->get_hw_state(encoder, &pipe)) 4174 return NULL; 4175 4176 crtc = intel_crtc_for_pipe(display, pipe); 4177 4178 mode = kzalloc_obj(*mode); 4179 if (!mode) 4180 return NULL; 4181 4182 crtc_state = intel_crtc_state_alloc(crtc); 4183 if (!crtc_state) { 4184 kfree(mode); 4185 return NULL; 4186 } 4187 4188 if (!intel_crtc_get_pipe_config(crtc_state)) { 4189 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4190 kfree(mode); 4191 return NULL; 4192 } 4193 4194 intel_encoder_get_config(encoder, crtc_state); 4195 4196 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4197 4198 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4199 4200 return mode; 4201 } 4202 4203 static bool encoders_cloneable(const struct intel_encoder *a, 4204 const struct intel_encoder *b) 4205 { 4206 /* masks could be asymmetric, so check both ways */ 4207 return a == b || (a->cloneable & BIT(b->type) && 4208 b->cloneable & BIT(a->type)); 4209 } 4210 4211 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4212 struct intel_crtc *crtc, 4213 struct intel_encoder *encoder) 4214 { 4215 struct intel_encoder *source_encoder; 4216 struct drm_connector *connector; 4217 struct drm_connector_state *connector_state; 4218 int i; 4219 4220 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4221 if (connector_state->crtc != &crtc->base) 4222 continue; 4223 4224 source_encoder = 4225 to_intel_encoder(connector_state->best_encoder); 4226 if (!encoders_cloneable(encoder, source_encoder)) 4227 return false; 4228 } 4229 4230 return true; 4231 } 4232 4233 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4234 { 4235 const struct drm_display_mode *pipe_mode = 4236 &crtc_state->hw.pipe_mode; 4237 int linetime_wm; 4238 4239 if (!crtc_state->hw.enable) 4240 return 0; 4241 4242 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4243 pipe_mode->crtc_clock); 4244 4245 return min(linetime_wm, 0x1ff); 4246 } 4247 4248 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4249 const struct intel_cdclk_state *cdclk_state) 4250 { 4251 const struct drm_display_mode *pipe_mode = 4252 &crtc_state->hw.pipe_mode; 4253 int linetime_wm; 4254 4255 if (!crtc_state->hw.enable) 4256 return 0; 4257 4258 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4259 intel_cdclk_logical(cdclk_state)); 4260 4261 return min(linetime_wm, 0x1ff); 4262 } 4263 4264 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4265 { 4266 struct intel_display *display = to_intel_display(crtc_state); 4267 const struct drm_display_mode *pipe_mode = 4268 &crtc_state->hw.pipe_mode; 4269 int linetime_wm; 4270 4271 if (!crtc_state->hw.enable) 4272 return 0; 4273 4274 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4275 crtc_state->pixel_rate); 4276 4277 /* Display WA #1135: BXT:ALL GLK:ALL */ 4278 if ((display->platform.geminilake || display->platform.broxton) && 4279 skl_watermark_ipc_enabled(display)) 4280 linetime_wm /= 2; 4281 4282 return min(linetime_wm, 0x1ff); 4283 } 4284 4285 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4286 struct intel_crtc *crtc) 4287 { 4288 struct intel_display *display = to_intel_display(state); 4289 struct intel_crtc_state *crtc_state = 4290 intel_atomic_get_new_crtc_state(state, crtc); 4291 const struct intel_cdclk_state *cdclk_state; 4292 4293 if (DISPLAY_VER(display) >= 9) 4294 crtc_state->linetime = skl_linetime_wm(crtc_state); 4295 else 4296 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4297 4298 if (!hsw_crtc_supports_ips(crtc)) 4299 return 0; 4300 4301 cdclk_state = intel_atomic_get_cdclk_state(state); 4302 if (IS_ERR(cdclk_state)) 4303 return PTR_ERR(cdclk_state); 4304 4305 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4306 cdclk_state); 4307 4308 return 0; 4309 } 4310 4311 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4312 struct intel_crtc *crtc) 4313 { 4314 struct intel_display *display = to_intel_display(crtc); 4315 struct intel_crtc_state *crtc_state = 4316 intel_atomic_get_new_crtc_state(state, crtc); 4317 int ret; 4318 4319 if (DISPLAY_VER(display) < 5 && !display->platform.g4x && 4320 intel_crtc_needs_modeset(crtc_state) && 4321 !crtc_state->hw.active) 4322 crtc_state->update_wm_post = true; 4323 4324 if (intel_crtc_needs_modeset(crtc_state)) { 4325 ret = intel_dpll_crtc_get_dpll(state, crtc); 4326 if (ret) 4327 return ret; 4328 } 4329 4330 ret = intel_color_check(state, crtc); 4331 if (ret) 4332 return ret; 4333 4334 ret = intel_wm_compute(state, crtc); 4335 if (ret) { 4336 drm_dbg_kms(display->drm, 4337 "[CRTC:%d:%s] watermarks are invalid\n", 4338 crtc->base.base.id, crtc->base.name); 4339 return ret; 4340 } 4341 4342 if (DISPLAY_VER(display) >= 9) { 4343 if (intel_crtc_needs_modeset(crtc_state) || 4344 intel_crtc_needs_fastset(crtc_state)) { 4345 ret = skl_update_scaler_crtc(crtc_state); 4346 if (ret) 4347 return ret; 4348 } 4349 4350 ret = intel_atomic_setup_scalers(state, crtc); 4351 if (ret) 4352 return ret; 4353 } 4354 4355 if (HAS_IPS(display)) { 4356 ret = hsw_ips_compute_config(state, crtc); 4357 if (ret) 4358 return ret; 4359 } 4360 4361 if (DISPLAY_VER(display) >= 9 || 4362 display->platform.broadwell || display->platform.haswell) { 4363 ret = hsw_compute_linetime_wm(state, crtc); 4364 if (ret) 4365 return ret; 4366 4367 } 4368 4369 ret = intel_psr2_sel_fetch_update(state, crtc); 4370 if (ret) 4371 return ret; 4372 4373 return 0; 4374 } 4375 4376 static int bpc_to_bpp(int bpc) 4377 { 4378 switch (bpc) { 4379 case 6 ... 7: 4380 return 6 * 3; 4381 case 8 ... 9: 4382 return 8 * 3; 4383 case 10 ... 11: 4384 return 10 * 3; 4385 case 12 ... 16: 4386 return 12 * 3; 4387 default: 4388 MISSING_CASE(bpc); 4389 return -EINVAL; 4390 } 4391 } 4392 4393 static int 4394 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4395 struct intel_crtc_state *crtc_state) 4396 { 4397 struct intel_display *display = to_intel_display(crtc_state); 4398 struct drm_connector *connector = conn_state->connector; 4399 const struct drm_display_info *info = &connector->display_info; 4400 int edid_bpc = info->bpc ? : 8; 4401 int target_pipe_bpp; 4402 int max_edid_bpp; 4403 4404 max_edid_bpp = bpc_to_bpp(edid_bpc); 4405 if (max_edid_bpp < 0) 4406 return max_edid_bpp; 4407 4408 target_pipe_bpp = bpc_to_bpp(conn_state->max_bpc); 4409 if (target_pipe_bpp < 0) 4410 return target_pipe_bpp; 4411 4412 /* 4413 * The maximum pipe BPP is the minimum of the max platform BPP and 4414 * the max EDID BPP. 4415 */ 4416 crtc_state->max_pipe_bpp = min(crtc_state->pipe_bpp, max_edid_bpp); 4417 4418 if (target_pipe_bpp < crtc_state->pipe_bpp) { 4419 drm_dbg_kms(display->drm, 4420 "[CONNECTOR:%d:%s] Limiting target display pipe bpp to %d " 4421 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4422 connector->base.id, connector->name, 4423 target_pipe_bpp, 3 * info->bpc, 4424 3 * conn_state->max_requested_bpc, 4425 crtc_state->pipe_bpp); 4426 4427 crtc_state->pipe_bpp = target_pipe_bpp; 4428 } 4429 4430 return 0; 4431 } 4432 4433 int intel_display_min_pipe_bpp(void) 4434 { 4435 return 6 * 3; 4436 } 4437 4438 int intel_display_max_pipe_bpp(struct intel_display *display) 4439 { 4440 if (display->platform.g4x || display->platform.valleyview || 4441 display->platform.cherryview) 4442 return 10*3; 4443 else if (DISPLAY_VER(display) >= 5) 4444 return 12*3; 4445 else 4446 return 8*3; 4447 } 4448 4449 static int 4450 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4451 struct intel_crtc *crtc) 4452 { 4453 struct intel_display *display = to_intel_display(crtc); 4454 struct intel_crtc_state *crtc_state = 4455 intel_atomic_get_new_crtc_state(state, crtc); 4456 struct drm_connector *connector; 4457 struct drm_connector_state *connector_state; 4458 int i; 4459 4460 crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display); 4461 4462 /* Clamp display bpp to connector max bpp */ 4463 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4464 int ret; 4465 4466 if (connector_state->crtc != &crtc->base) 4467 continue; 4468 4469 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4470 if (ret) 4471 return ret; 4472 } 4473 4474 return 0; 4475 } 4476 4477 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4478 { 4479 struct intel_display *display = to_intel_display(state); 4480 struct drm_connector *connector; 4481 struct drm_connector_list_iter conn_iter; 4482 unsigned int used_ports = 0; 4483 unsigned int used_mst_ports = 0; 4484 bool ret = true; 4485 4486 /* 4487 * We're going to peek into connector->state, 4488 * hence connection_mutex must be held. 4489 */ 4490 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 4491 4492 /* 4493 * Walk the connector list instead of the encoder 4494 * list to detect the problem on ddi platforms 4495 * where there's just one encoder per digital port. 4496 */ 4497 drm_connector_list_iter_begin(display->drm, &conn_iter); 4498 drm_for_each_connector_iter(connector, &conn_iter) { 4499 struct drm_connector_state *connector_state; 4500 struct intel_encoder *encoder; 4501 4502 connector_state = 4503 drm_atomic_get_new_connector_state(&state->base, 4504 connector); 4505 if (!connector_state) 4506 connector_state = connector->state; 4507 4508 if (!connector_state->best_encoder) 4509 continue; 4510 4511 encoder = to_intel_encoder(connector_state->best_encoder); 4512 4513 drm_WARN_ON(display->drm, !connector_state->crtc); 4514 4515 switch (encoder->type) { 4516 case INTEL_OUTPUT_DDI: 4517 if (drm_WARN_ON(display->drm, !HAS_DDI(display))) 4518 break; 4519 fallthrough; 4520 case INTEL_OUTPUT_DP: 4521 case INTEL_OUTPUT_HDMI: 4522 case INTEL_OUTPUT_EDP: 4523 /* the same port mustn't appear more than once */ 4524 if (used_ports & BIT(encoder->port)) 4525 ret = false; 4526 4527 used_ports |= BIT(encoder->port); 4528 break; 4529 case INTEL_OUTPUT_DP_MST: 4530 used_mst_ports |= 4531 1 << encoder->port; 4532 break; 4533 default: 4534 break; 4535 } 4536 } 4537 drm_connector_list_iter_end(&conn_iter); 4538 4539 /* can't mix MST and SST/HDMI on the same port */ 4540 if (used_ports & used_mst_ports) 4541 return false; 4542 4543 return ret; 4544 } 4545 4546 static void 4547 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4548 struct intel_crtc *crtc) 4549 { 4550 struct intel_crtc_state *crtc_state = 4551 intel_atomic_get_new_crtc_state(state, crtc); 4552 4553 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4554 4555 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4556 crtc_state->uapi.degamma_lut); 4557 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4558 crtc_state->uapi.gamma_lut); 4559 drm_property_replace_blob(&crtc_state->hw.ctm, 4560 crtc_state->uapi.ctm); 4561 crtc_state->hw.background_color = 4562 intel_color_background_color_drm_to_hw(crtc_state->uapi.background_color); 4563 } 4564 4565 static void 4566 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4567 struct intel_crtc *crtc) 4568 { 4569 struct intel_crtc_state *crtc_state = 4570 intel_atomic_get_new_crtc_state(state, crtc); 4571 4572 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4573 4574 crtc_state->hw.enable = crtc_state->uapi.enable; 4575 crtc_state->hw.active = crtc_state->uapi.active; 4576 drm_mode_copy(&crtc_state->hw.mode, 4577 &crtc_state->uapi.mode); 4578 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4579 &crtc_state->uapi.adjusted_mode); 4580 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4581 crtc_state->hw.sharpness_strength = crtc_state->uapi.sharpness_strength; 4582 4583 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4584 } 4585 4586 static void 4587 copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4588 struct intel_crtc *secondary_crtc) 4589 { 4590 struct intel_crtc_state *secondary_crtc_state = 4591 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4592 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4593 const struct intel_crtc_state *primary_crtc_state = 4594 intel_atomic_get_new_crtc_state(state, primary_crtc); 4595 4596 drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut, 4597 primary_crtc_state->hw.degamma_lut); 4598 drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut, 4599 primary_crtc_state->hw.gamma_lut); 4600 drm_property_replace_blob(&secondary_crtc_state->hw.ctm, 4601 primary_crtc_state->hw.ctm); 4602 secondary_crtc_state->hw.background_color = primary_crtc_state->hw.background_color; 4603 4604 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed; 4605 } 4606 4607 static int 4608 copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, 4609 struct intel_crtc *secondary_crtc) 4610 { 4611 struct intel_crtc_state *secondary_crtc_state = 4612 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4613 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4614 const struct intel_crtc_state *primary_crtc_state = 4615 intel_atomic_get_new_crtc_state(state, primary_crtc); 4616 struct intel_crtc_state *saved_state; 4617 4618 WARN_ON(primary_crtc_state->joiner_pipes != 4619 secondary_crtc_state->joiner_pipes); 4620 4621 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4622 if (!saved_state) 4623 return -ENOMEM; 4624 4625 /* preserve some things from the slave's original crtc state */ 4626 saved_state->uapi = secondary_crtc_state->uapi; 4627 saved_state->scaler_state = secondary_crtc_state->scaler_state; 4628 saved_state->intel_dpll = secondary_crtc_state->intel_dpll; 4629 saved_state->crc_enabled = secondary_crtc_state->crc_enabled; 4630 4631 intel_crtc_free_hw_state(secondary_crtc_state); 4632 if (secondary_crtc_state->dp_tunnel_ref.tunnel) 4633 drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref); 4634 memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state)); 4635 kfree(saved_state); 4636 4637 /* Re-init hw state */ 4638 memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw)); 4639 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable; 4640 secondary_crtc_state->hw.active = primary_crtc_state->hw.active; 4641 drm_mode_copy(&secondary_crtc_state->hw.mode, 4642 &primary_crtc_state->hw.mode); 4643 drm_mode_copy(&secondary_crtc_state->hw.pipe_mode, 4644 &primary_crtc_state->hw.pipe_mode); 4645 drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, 4646 &primary_crtc_state->hw.adjusted_mode); 4647 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; 4648 secondary_crtc_state->hw.sharpness_strength = primary_crtc_state->hw.sharpness_strength; 4649 4650 if (primary_crtc_state->dp_tunnel_ref.tunnel) 4651 drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, 4652 &secondary_crtc_state->dp_tunnel_ref); 4653 4654 copy_joiner_crtc_state_nomodeset(state, secondary_crtc); 4655 4656 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed; 4657 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed; 4658 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed; 4659 4660 WARN_ON(primary_crtc_state->joiner_pipes != 4661 secondary_crtc_state->joiner_pipes); 4662 4663 return 0; 4664 } 4665 4666 static int 4667 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4668 struct intel_crtc *crtc) 4669 { 4670 struct intel_display *display = to_intel_display(state); 4671 struct intel_crtc_state *crtc_state = 4672 intel_atomic_get_new_crtc_state(state, crtc); 4673 struct intel_crtc_state *saved_state; 4674 int err; 4675 4676 saved_state = intel_crtc_state_alloc(crtc); 4677 if (!saved_state) 4678 return -ENOMEM; 4679 4680 /* free the old crtc_state->hw members */ 4681 intel_crtc_free_hw_state(crtc_state); 4682 4683 err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4684 if (err) { 4685 kfree(saved_state); 4686 4687 return err; 4688 } 4689 4690 /* FIXME: before the switch to atomic started, a new pipe_config was 4691 * kzalloc'd. Code that depends on any field being zero should be 4692 * fixed, so that the crtc_state can be safely duplicated. For now, 4693 * only fields that are know to not cause problems are preserved. */ 4694 4695 saved_state->uapi = crtc_state->uapi; 4696 saved_state->inherited = crtc_state->inherited; 4697 saved_state->scaler_state = crtc_state->scaler_state; 4698 saved_state->intel_dpll = crtc_state->intel_dpll; 4699 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4700 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4701 sizeof(saved_state->icl_port_dplls)); 4702 saved_state->crc_enabled = crtc_state->crc_enabled; 4703 if (display->platform.g4x || 4704 display->platform.valleyview || display->platform.cherryview) 4705 saved_state->wm = crtc_state->wm; 4706 4707 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4708 kfree(saved_state); 4709 4710 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4711 4712 return 0; 4713 } 4714 4715 static int 4716 intel_modeset_pipe_config(struct intel_atomic_state *state, 4717 struct intel_crtc *crtc, 4718 const struct intel_link_bw_limits *limits) 4719 { 4720 struct intel_display *display = to_intel_display(crtc); 4721 struct intel_crtc_state *crtc_state = 4722 intel_atomic_get_new_crtc_state(state, crtc); 4723 struct drm_connector *connector; 4724 struct drm_connector_state *connector_state; 4725 int pipe_src_w, pipe_src_h; 4726 int base_bpp, ret, i; 4727 4728 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4729 4730 crtc_state->framestart_delay = 1; 4731 4732 /* 4733 * Sanitize sync polarity flags based on requested ones. If neither 4734 * positive or negative polarity is requested, treat this as meaning 4735 * negative polarity. 4736 */ 4737 if (!(crtc_state->hw.adjusted_mode.flags & 4738 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4739 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4740 4741 if (!(crtc_state->hw.adjusted_mode.flags & 4742 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4743 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4744 4745 ret = compute_baseline_pipe_bpp(state, crtc); 4746 if (ret) 4747 return ret; 4748 4749 crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe); 4750 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; 4751 4752 if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) { 4753 drm_dbg_kms(display->drm, 4754 "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n", 4755 crtc->base.base.id, crtc->base.name, 4756 FXP_Q4_ARGS(crtc_state->max_link_bpp_x16)); 4757 crtc_state->bw_constrained = true; 4758 } 4759 4760 base_bpp = crtc_state->pipe_bpp; 4761 4762 /* 4763 * Determine the real pipe dimensions. Note that stereo modes can 4764 * increase the actual pipe size due to the frame doubling and 4765 * insertion of additional space for blanks between the frame. This 4766 * is stored in the crtc timings. We use the requested mode to do this 4767 * computation to clearly distinguish it from the adjusted mode, which 4768 * can be changed by the connectors in the below retry loop. 4769 */ 4770 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4771 &pipe_src_w, &pipe_src_h); 4772 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4773 pipe_src_w, pipe_src_h); 4774 4775 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4776 struct intel_encoder *encoder = 4777 to_intel_encoder(connector_state->best_encoder); 4778 4779 if (connector_state->crtc != &crtc->base) 4780 continue; 4781 4782 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4783 drm_dbg_kms(display->drm, 4784 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4785 encoder->base.base.id, encoder->base.name); 4786 return -EINVAL; 4787 } 4788 4789 /* 4790 * Determine output_types before calling the .compute_config() 4791 * hooks so that the hooks can use this information safely. 4792 */ 4793 if (encoder->compute_output_type) 4794 crtc_state->output_types |= 4795 BIT(encoder->compute_output_type(encoder, crtc_state, 4796 connector_state)); 4797 else 4798 crtc_state->output_types |= BIT(encoder->type); 4799 } 4800 4801 /* Ensure the port clock defaults are reset when retrying. */ 4802 crtc_state->port_clock = 0; 4803 crtc_state->pixel_multiplier = 1; 4804 4805 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4806 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4807 CRTC_STEREO_DOUBLE); 4808 4809 /* Pass our mode to the connectors and the CRTC to give them a chance to 4810 * adjust it according to limitations or connector properties, and also 4811 * a chance to reject the mode entirely. 4812 */ 4813 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4814 struct intel_encoder *encoder = 4815 to_intel_encoder(connector_state->best_encoder); 4816 4817 if (connector_state->crtc != &crtc->base) 4818 continue; 4819 4820 ret = encoder->compute_config(state, encoder, crtc_state, 4821 connector_state); 4822 if (ret == -EDEADLK) 4823 return ret; 4824 if (ret < 0) { 4825 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n", 4826 encoder->base.base.id, encoder->base.name, ret); 4827 return ret; 4828 } 4829 } 4830 4831 /* Set default port clock if not overwritten by the encoder. Needs to be 4832 * done afterwards in case the encoder adjusts the mode. */ 4833 if (!crtc_state->port_clock) 4834 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4835 * crtc_state->pixel_multiplier; 4836 4837 ret = intel_crtc_compute_config(state, crtc); 4838 if (ret == -EDEADLK) 4839 return ret; 4840 if (ret < 0) { 4841 drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n", 4842 crtc->base.base.id, crtc->base.name, ret); 4843 return ret; 4844 } 4845 4846 /* Dithering seems to not pass-through bits correctly when it should, so 4847 * only enable it on 6bpc panels and when its not a compliance 4848 * test requesting 6bpc video pattern. 4849 */ 4850 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4851 !crtc_state->dither_force_disable; 4852 drm_dbg_kms(display->drm, 4853 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4854 crtc->base.base.id, crtc->base.name, 4855 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4856 4857 return 0; 4858 } 4859 4860 static int 4861 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4862 struct intel_crtc *crtc) 4863 { 4864 struct intel_crtc_state *crtc_state = 4865 intel_atomic_get_new_crtc_state(state, crtc); 4866 struct drm_connector_state *conn_state; 4867 struct drm_connector *connector; 4868 int i; 4869 4870 for_each_new_connector_in_state(&state->base, connector, 4871 conn_state, i) { 4872 struct intel_encoder *encoder = 4873 to_intel_encoder(conn_state->best_encoder); 4874 int ret; 4875 4876 if (conn_state->crtc != &crtc->base || 4877 !encoder->compute_config_late) 4878 continue; 4879 4880 ret = encoder->compute_config_late(state, encoder, crtc_state, 4881 conn_state); 4882 if (ret) 4883 return ret; 4884 } 4885 4886 return 0; 4887 } 4888 4889 bool intel_fuzzy_clock_check(int clock1, int clock2) 4890 { 4891 int diff; 4892 4893 if (clock1 == clock2) 4894 return true; 4895 4896 if (!clock1 || !clock2) 4897 return false; 4898 4899 diff = abs(clock1 - clock2); 4900 4901 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4902 return true; 4903 4904 return false; 4905 } 4906 4907 static bool 4908 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4909 const struct intel_link_m_n *m2_n2) 4910 { 4911 return m_n->tu == m2_n2->tu && 4912 m_n->data_m == m2_n2->data_m && 4913 m_n->data_n == m2_n2->data_n && 4914 m_n->link_m == m2_n2->link_m && 4915 m_n->link_n == m2_n2->link_n; 4916 } 4917 4918 static bool 4919 intel_compare_infoframe(const union hdmi_infoframe *a, 4920 const union hdmi_infoframe *b) 4921 { 4922 return memcmp(a, b, sizeof(*a)) == 0; 4923 } 4924 4925 static bool 4926 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4927 const struct drm_dp_vsc_sdp *b) 4928 { 4929 return a->pixelformat == b->pixelformat && 4930 a->colorimetry == b->colorimetry && 4931 a->bpc == b->bpc && 4932 a->dynamic_range == b->dynamic_range && 4933 a->content_type == b->content_type; 4934 } 4935 4936 static bool 4937 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, 4938 const struct drm_dp_as_sdp *b) 4939 { 4940 return a->sdp_type == b->sdp_type && 4941 a->revision == b->revision && 4942 a->length == b->length && 4943 a->vtotal == b->vtotal && 4944 a->target_rr == b->target_rr && 4945 a->duration_incr_ms == b->duration_incr_ms && 4946 a->duration_decr_ms == b->duration_decr_ms && 4947 a->target_rr_divider == b->target_rr_divider && 4948 a->mode == b->mode && 4949 a->coasting_vtotal == b->coasting_vtotal; 4950 } 4951 4952 static bool 4953 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4954 { 4955 return memcmp(a, b, len) == 0; 4956 } 4957 4958 static void __printf(5, 6) 4959 pipe_config_mismatch(struct drm_printer *p, bool fastset, 4960 const struct intel_crtc *crtc, 4961 const char *name, const char *format, ...) 4962 { 4963 struct va_format vaf; 4964 va_list args; 4965 4966 va_start(args, format); 4967 vaf.fmt = format; 4968 vaf.va = &args; 4969 4970 if (fastset) 4971 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4972 crtc->base.base.id, crtc->base.name, name, &vaf); 4973 else 4974 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n", 4975 crtc->base.base.id, crtc->base.name, name, &vaf); 4976 4977 va_end(args); 4978 } 4979 4980 static void 4981 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, 4982 const struct intel_crtc *crtc, 4983 const char *name, 4984 const union hdmi_infoframe *a, 4985 const union hdmi_infoframe *b) 4986 { 4987 struct intel_display *display = to_intel_display(crtc); 4988 const char *loglevel; 4989 4990 if (fastset) { 4991 if (!drm_debug_enabled(DRM_UT_KMS)) 4992 return; 4993 4994 loglevel = KERN_DEBUG; 4995 } else { 4996 loglevel = KERN_ERR; 4997 } 4998 4999 pipe_config_mismatch(p, fastset, crtc, name, "infoframe"); 5000 5001 drm_printf(p, "expected:\n"); 5002 hdmi_infoframe_log(loglevel, display->drm->dev, a); 5003 drm_printf(p, "found:\n"); 5004 hdmi_infoframe_log(loglevel, display->drm->dev, b); 5005 } 5006 5007 static void 5008 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset, 5009 const struct intel_crtc *crtc, 5010 const char *name, 5011 const struct drm_dp_vsc_sdp *a, 5012 const struct drm_dp_vsc_sdp *b) 5013 { 5014 pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp"); 5015 5016 drm_printf(p, "expected:\n"); 5017 drm_dp_vsc_sdp_log(p, a); 5018 drm_printf(p, "found:\n"); 5019 drm_dp_vsc_sdp_log(p, b); 5020 } 5021 5022 static void 5023 pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset, 5024 const struct intel_crtc *crtc, 5025 const char *name, 5026 const struct drm_dp_as_sdp *a, 5027 const struct drm_dp_as_sdp *b) 5028 { 5029 pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp"); 5030 5031 drm_printf(p, "expected:\n"); 5032 drm_dp_as_sdp_log(p, a); 5033 drm_printf(p, "found:\n"); 5034 drm_dp_as_sdp_log(p, b); 5035 } 5036 5037 /* Returns the length up to and including the last differing byte */ 5038 static size_t 5039 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 5040 { 5041 int i; 5042 5043 for (i = len - 1; i >= 0; i--) { 5044 if (a[i] != b[i]) 5045 return i + 1; 5046 } 5047 5048 return 0; 5049 } 5050 5051 static void 5052 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset, 5053 const struct intel_crtc *crtc, 5054 const char *name, 5055 const u8 *a, const u8 *b, size_t len) 5056 { 5057 pipe_config_mismatch(p, fastset, crtc, name, "buffer"); 5058 5059 /* only dump up to the last difference */ 5060 len = memcmp_diff_len(a, b, len); 5061 5062 drm_print_hex_dump(p, "expected: ", a, len); 5063 drm_print_hex_dump(p, "found: ", b, len); 5064 } 5065 5066 static void 5067 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, 5068 const struct intel_crtc *crtc, 5069 const char *name, 5070 const struct intel_dpll_hw_state *a, 5071 const struct intel_dpll_hw_state *b) 5072 { 5073 struct intel_display *display = to_intel_display(crtc); 5074 5075 pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */ 5076 5077 drm_printf(p, "expected:\n"); 5078 intel_dpll_dump_hw_state(display, p, a); 5079 drm_printf(p, "found:\n"); 5080 intel_dpll_dump_hw_state(display, p, b); 5081 } 5082 5083 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) 5084 { 5085 struct intel_display *display = to_intel_display(old_crtc_state); 5086 5087 /* 5088 * Allow fastboot to fix up vblank delay (handled via LRR 5089 * codepaths), a bit dodgy as the registers aren't 5090 * double buffered but seems to be working more or less... 5091 * 5092 * Also allow this when the VRR timing generator is always on, 5093 * and optimized guardband is used. In such cases, 5094 * vblank delay may vary even without inherited state, but it's 5095 * still safe as VRR guardband is still same. 5096 */ 5097 return HAS_LRR(display) && 5098 (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) && 5099 !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI); 5100 } 5101 5102 bool 5103 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5104 const struct intel_crtc_state *pipe_config, 5105 bool fastset) 5106 { 5107 struct intel_display *display = to_intel_display(current_config); 5108 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5109 struct drm_printer p; 5110 u32 exclude_infoframes = 0; 5111 bool ret = true; 5112 5113 if (fastset) 5114 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 5115 else 5116 p = drm_err_printer(display->drm, NULL); 5117 5118 #define PIPE_CONF_CHECK_X(name) do { \ 5119 if (current_config->name != pipe_config->name) { \ 5120 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5121 __stringify(name) " is bool"); \ 5122 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5123 "(expected 0x%08x, found 0x%08x)", \ 5124 current_config->name, \ 5125 pipe_config->name); \ 5126 ret = false; \ 5127 } \ 5128 } while (0) 5129 5130 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5131 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5132 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5133 __stringify(name) " is bool"); \ 5134 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5135 "(expected 0x%08x, found 0x%08x)", \ 5136 current_config->name & (mask), \ 5137 pipe_config->name & (mask)); \ 5138 ret = false; \ 5139 } \ 5140 } while (0) 5141 5142 #define PIPE_CONF_CHECK_I(name) do { \ 5143 if (current_config->name != pipe_config->name) { \ 5144 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5145 __stringify(name) " is bool"); \ 5146 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5147 "(expected %i, found %i)", \ 5148 current_config->name, \ 5149 pipe_config->name); \ 5150 ret = false; \ 5151 } \ 5152 } while (0) 5153 5154 #define PIPE_CONF_CHECK_LLI(name) do { \ 5155 if (current_config->name != pipe_config->name) { \ 5156 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5157 "(expected %lli, found %lli)", \ 5158 current_config->name, \ 5159 pipe_config->name); \ 5160 ret = false; \ 5161 } \ 5162 } while (0) 5163 5164 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5165 if (current_config->name != pipe_config->name) { \ 5166 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ 5167 __stringify(name) " is not bool"); \ 5168 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5169 "(expected %s, found %s)", \ 5170 str_yes_no(current_config->name), \ 5171 str_yes_no(pipe_config->name)); \ 5172 ret = false; \ 5173 } \ 5174 } while (0) 5175 5176 #define PIPE_CONF_CHECK_P(name) do { \ 5177 if (current_config->name != pipe_config->name) { \ 5178 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5179 "(expected %p, found %p)", \ 5180 current_config->name, \ 5181 pipe_config->name); \ 5182 ret = false; \ 5183 } \ 5184 } while (0) 5185 5186 #define PIPE_CONF_CHECK_M_N(name) do { \ 5187 if (!intel_compare_link_m_n(¤t_config->name, \ 5188 &pipe_config->name)) { \ 5189 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5190 "(expected tu %i data %i/%i link %i/%i, " \ 5191 "found tu %i, data %i/%i link %i/%i)", \ 5192 current_config->name.tu, \ 5193 current_config->name.data_m, \ 5194 current_config->name.data_n, \ 5195 current_config->name.link_m, \ 5196 current_config->name.link_n, \ 5197 pipe_config->name.tu, \ 5198 pipe_config->name.data_m, \ 5199 pipe_config->name.data_n, \ 5200 pipe_config->name.link_m, \ 5201 pipe_config->name.link_n); \ 5202 ret = false; \ 5203 } \ 5204 } while (0) 5205 5206 #define PIPE_CONF_CHECK_PLL(name) do { \ 5207 if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \ 5208 &pipe_config->name)) { \ 5209 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5210 ¤t_config->name, \ 5211 &pipe_config->name); \ 5212 ret = false; \ 5213 } \ 5214 } while (0) 5215 5216 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5217 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5218 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5219 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5220 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5221 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5222 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5223 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5224 if (!fastset || !allow_vblank_delay_fastset(current_config)) \ 5225 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5226 if (!fastset || !pipe_config->update_lrr) { \ 5227 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5228 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5229 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5230 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5231 } \ 5232 } while (0) 5233 5234 #define PIPE_CONF_CHECK_RECT(name) do { \ 5235 PIPE_CONF_CHECK_I(name.x1); \ 5236 PIPE_CONF_CHECK_I(name.x2); \ 5237 PIPE_CONF_CHECK_I(name.y1); \ 5238 PIPE_CONF_CHECK_I(name.y2); \ 5239 } while (0) 5240 5241 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5242 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5243 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5244 "(%x) (expected %i, found %i)", \ 5245 (mask), \ 5246 current_config->name & (mask), \ 5247 pipe_config->name & (mask)); \ 5248 ret = false; \ 5249 } \ 5250 } while (0) 5251 5252 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5253 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5254 &pipe_config->infoframes.name)) { \ 5255 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \ 5256 ¤t_config->infoframes.name, \ 5257 &pipe_config->infoframes.name); \ 5258 ret = false; \ 5259 } \ 5260 } while (0) 5261 5262 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5263 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5264 &pipe_config->infoframes.name)) { \ 5265 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5266 ¤t_config->infoframes.name, \ 5267 &pipe_config->infoframes.name); \ 5268 ret = false; \ 5269 } \ 5270 } while (0) 5271 5272 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ 5273 if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \ 5274 &pipe_config->infoframes.name)) { \ 5275 pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5276 ¤t_config->infoframes.name, \ 5277 &pipe_config->infoframes.name); \ 5278 ret = false; \ 5279 } \ 5280 } while (0) 5281 5282 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5283 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5284 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5285 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5286 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \ 5287 current_config->name, \ 5288 pipe_config->name, \ 5289 (len)); \ 5290 ret = false; \ 5291 } \ 5292 } while (0) 5293 5294 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5295 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5296 !intel_color_lut_equal(current_config, \ 5297 current_config->lut, pipe_config->lut, \ 5298 is_pre_csc_lut)) { \ 5299 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \ 5300 "hw_state doesn't match sw_state"); \ 5301 ret = false; \ 5302 } \ 5303 } while (0) 5304 5305 #define PIPE_CONF_CHECK_CSC(name) do { \ 5306 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5307 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5308 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5309 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5310 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5311 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5312 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5313 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5314 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5315 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5316 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5317 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5318 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5319 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5320 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5321 } while (0) 5322 5323 #define PIPE_CONF_QUIRK(quirk) \ 5324 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5325 5326 PIPE_CONF_CHECK_BOOL(hw.enable); 5327 PIPE_CONF_CHECK_BOOL(hw.active); 5328 5329 PIPE_CONF_CHECK_I(cpu_transcoder); 5330 PIPE_CONF_CHECK_I(mst_master_transcoder); 5331 5332 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5333 PIPE_CONF_CHECK_I(fdi_lanes); 5334 PIPE_CONF_CHECK_M_N(fdi_m_n); 5335 5336 PIPE_CONF_CHECK_I(lane_count); 5337 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5338 5339 PIPE_CONF_CHECK_I(min_hblank); 5340 5341 if (HAS_DOUBLE_BUFFERED_M_N(display)) { 5342 if (!fastset || !pipe_config->update_m_n) 5343 PIPE_CONF_CHECK_M_N(dp_m_n); 5344 } else { 5345 PIPE_CONF_CHECK_M_N(dp_m_n); 5346 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5347 } 5348 5349 PIPE_CONF_CHECK_X(output_types); 5350 5351 PIPE_CONF_CHECK_I(framestart_delay); 5352 PIPE_CONF_CHECK_I(msa_timing_delay); 5353 5354 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5355 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5356 5357 PIPE_CONF_CHECK_I(pixel_multiplier); 5358 5359 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5360 DRM_MODE_FLAG_INTERLACE); 5361 5362 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5363 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5364 DRM_MODE_FLAG_PHSYNC); 5365 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5366 DRM_MODE_FLAG_NHSYNC); 5367 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5368 DRM_MODE_FLAG_PVSYNC); 5369 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5370 DRM_MODE_FLAG_NVSYNC); 5371 } 5372 5373 PIPE_CONF_CHECK_I(output_format); 5374 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5375 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || 5376 display->platform.valleyview || display->platform.cherryview) 5377 PIPE_CONF_CHECK_BOOL(limited_color_range); 5378 5379 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5380 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5381 PIPE_CONF_CHECK_BOOL(has_infoframe); 5382 PIPE_CONF_CHECK_BOOL(enhanced_framing); 5383 PIPE_CONF_CHECK_BOOL(fec_enable); 5384 5385 if (!fastset) { 5386 PIPE_CONF_CHECK_BOOL(has_audio); 5387 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5388 } 5389 5390 PIPE_CONF_CHECK_X(gmch_pfit.control); 5391 /* pfit ratios are autocomputed by the hw on gen4+ */ 5392 if (DISPLAY_VER(display) < 4) 5393 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5394 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5395 5396 /* 5397 * Changing the EDP transcoder input mux 5398 * (A_ONOFF vs. A_ON) requires a full modeset. 5399 */ 5400 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5401 5402 if (!fastset) { 5403 PIPE_CONF_CHECK_RECT(pipe_src); 5404 5405 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5406 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5407 PIPE_CONF_CHECK_BOOL(pch_pfit.casf.enable); 5408 PIPE_CONF_CHECK_I(pch_pfit.casf.win_size); 5409 PIPE_CONF_CHECK_I(pch_pfit.casf.strength); 5410 5411 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5412 PIPE_CONF_CHECK_I(pixel_rate_cdclk); 5413 PIPE_CONF_CHECK_I(pixel_rate); 5414 5415 PIPE_CONF_CHECK_X(gamma_mode); 5416 if (display->platform.cherryview) 5417 PIPE_CONF_CHECK_X(cgm_mode); 5418 else 5419 PIPE_CONF_CHECK_X(csc_mode); 5420 PIPE_CONF_CHECK_BOOL(gamma_enable); 5421 5422 PIPE_CONF_CHECK_X(hw.background_color); 5423 PIPE_CONF_CHECK_BOOL(csc_enable); 5424 PIPE_CONF_CHECK_BOOL(wgc_enable); 5425 5426 PIPE_CONF_CHECK_I(linetime); 5427 PIPE_CONF_CHECK_I(ips_linetime); 5428 5429 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5430 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5431 5432 PIPE_CONF_CHECK_CSC(csc); 5433 PIPE_CONF_CHECK_CSC(output_csc); 5434 } 5435 5436 PIPE_CONF_CHECK_BOOL(double_wide); 5437 5438 if (display->dpll.mgr) 5439 PIPE_CONF_CHECK_P(intel_dpll); 5440 5441 /* FIXME convert everything over the dpll_mgr */ 5442 if (display->dpll.mgr || HAS_GMCH(display)) 5443 PIPE_CONF_CHECK_PLL(dpll_hw_state); 5444 5445 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5446 PIPE_CONF_CHECK_X(dsi_pll.div); 5447 5448 if (display->platform.g4x || DISPLAY_VER(display) >= 5) 5449 PIPE_CONF_CHECK_I(pipe_bpp); 5450 5451 if (!fastset || !pipe_config->update_m_n) { 5452 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5453 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5454 } 5455 PIPE_CONF_CHECK_I(port_clock); 5456 5457 PIPE_CONF_CHECK_I(min_voltage_level); 5458 5459 if (current_config->has_psr || pipe_config->has_psr) 5460 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 5461 5462 if (current_config->vrr.enable || pipe_config->vrr.enable) 5463 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 5464 5465 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes); 5466 PIPE_CONF_CHECK_X(infoframes.gcp); 5467 PIPE_CONF_CHECK_INFOFRAME(avi); 5468 PIPE_CONF_CHECK_INFOFRAME(spd); 5469 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5470 if (!fastset) { 5471 PIPE_CONF_CHECK_INFOFRAME(drm); 5472 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); 5473 } 5474 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5475 5476 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5477 PIPE_CONF_CHECK_I(master_transcoder); 5478 PIPE_CONF_CHECK_X(joiner_pipes); 5479 5480 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); 5481 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); 5482 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422); 5483 PIPE_CONF_CHECK_BOOL(dsc.config.native_422); 5484 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); 5485 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable); 5486 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth); 5487 PIPE_CONF_CHECK_I(dsc.config.bits_per_component); 5488 PIPE_CONF_CHECK_I(dsc.config.pic_width); 5489 PIPE_CONF_CHECK_I(dsc.config.pic_height); 5490 PIPE_CONF_CHECK_I(dsc.config.slice_width); 5491 PIPE_CONF_CHECK_I(dsc.config.slice_height); 5492 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay); 5493 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay); 5494 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval); 5495 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval); 5496 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value); 5497 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset); 5498 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp); 5499 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp); 5500 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset); 5501 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset); 5502 PIPE_CONF_CHECK_I(dsc.config.initial_offset); 5503 PIPE_CONF_CHECK_I(dsc.config.final_offset); 5504 PIPE_CONF_CHECK_I(dsc.config.rc_model_size); 5505 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0); 5506 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1); 5507 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size); 5508 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset); 5509 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); 5510 5511 PIPE_CONF_CHECK_BOOL(dsc.compression_enable); 5512 PIPE_CONF_CHECK_I(dsc.slice_config.streams_per_pipe); 5513 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); 5514 5515 PIPE_CONF_CHECK_BOOL(splitter.enable); 5516 PIPE_CONF_CHECK_I(splitter.link_count); 5517 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5518 5519 if (!fastset) { 5520 PIPE_CONF_CHECK_BOOL(vrr.enable); 5521 PIPE_CONF_CHECK_I(vrr.vmin); 5522 PIPE_CONF_CHECK_I(vrr.vmax); 5523 PIPE_CONF_CHECK_I(vrr.flipline); 5524 PIPE_CONF_CHECK_I(vrr.vsync_start); 5525 PIPE_CONF_CHECK_I(vrr.vsync_end); 5526 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); 5527 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); 5528 PIPE_CONF_CHECK_BOOL(cmrr.enable); 5529 PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); 5530 PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); 5531 PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); 5532 PIPE_CONF_CHECK_I(vrr.dc_balance.slope); 5533 PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); 5534 PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); 5535 PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); 5536 } 5537 5538 if (!fastset || intel_vrr_always_use_vrr_tg(display)) { 5539 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5540 PIPE_CONF_CHECK_I(vrr.guardband); 5541 } 5542 5543 PIPE_CONF_CHECK_I(set_context_latency); 5544 5545 #undef PIPE_CONF_CHECK_X 5546 #undef PIPE_CONF_CHECK_I 5547 #undef PIPE_CONF_CHECK_LLI 5548 #undef PIPE_CONF_CHECK_BOOL 5549 #undef PIPE_CONF_CHECK_P 5550 #undef PIPE_CONF_CHECK_FLAGS 5551 #undef PIPE_CONF_CHECK_COLOR_LUT 5552 #undef PIPE_CONF_CHECK_TIMINGS 5553 #undef PIPE_CONF_CHECK_RECT 5554 #undef PIPE_CONF_QUIRK 5555 5556 return ret; 5557 } 5558 5559 static void 5560 intel_verify_planes(struct intel_atomic_state *state) 5561 { 5562 struct intel_plane *plane; 5563 const struct intel_plane_state *plane_state; 5564 int i; 5565 5566 for_each_new_intel_plane_in_state(state, plane, 5567 plane_state, i) 5568 assert_plane(plane, plane_state->is_y_plane || 5569 plane_state->uapi.visible); 5570 } 5571 5572 static int intel_modeset_pipe(struct intel_atomic_state *state, 5573 struct intel_crtc_state *crtc_state, 5574 const char *reason) 5575 { 5576 struct intel_display *display = to_intel_display(state); 5577 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5578 int ret; 5579 5580 drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5581 crtc->base.base.id, crtc->base.name, reason); 5582 5583 ret = drm_atomic_add_affected_connectors(&state->base, 5584 &crtc->base); 5585 if (ret) 5586 return ret; 5587 5588 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc); 5589 if (ret) 5590 return ret; 5591 5592 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5593 if (ret) 5594 return ret; 5595 5596 ret = intel_plane_add_affected(state, crtc); 5597 if (ret) 5598 return ret; 5599 5600 crtc_state->uapi.mode_changed = true; 5601 5602 return 0; 5603 } 5604 5605 /** 5606 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes 5607 * @state: intel atomic state 5608 * @reason: the reason for the full modeset 5609 * @mask: mask of pipes to modeset 5610 * 5611 * Add pipes in @mask to @state and force a full modeset on the enabled ones 5612 * due to the description in @reason. 5613 * This function can be called only before new plane states are computed. 5614 * 5615 * Returns 0 in case of success, negative error code otherwise. 5616 */ 5617 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 5618 const char *reason, u8 mask) 5619 { 5620 struct intel_display *display = to_intel_display(state); 5621 struct intel_crtc *crtc; 5622 5623 for_each_intel_crtc_in_pipe_mask(display, crtc, mask) { 5624 struct intel_crtc_state *crtc_state; 5625 int ret; 5626 5627 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5628 if (IS_ERR(crtc_state)) 5629 return PTR_ERR(crtc_state); 5630 5631 if (!crtc_state->hw.enable || 5632 intel_crtc_needs_modeset(crtc_state)) 5633 continue; 5634 5635 ret = intel_modeset_pipe(state, crtc_state, reason); 5636 if (ret) 5637 return ret; 5638 } 5639 5640 return 0; 5641 } 5642 5643 static void 5644 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) 5645 { 5646 crtc_state->uapi.mode_changed = true; 5647 5648 crtc_state->update_pipe = false; 5649 crtc_state->update_m_n = false; 5650 crtc_state->update_lrr = false; 5651 } 5652 5653 /** 5654 * intel_modeset_all_pipes_late - force a full modeset on all pipes 5655 * @state: intel atomic state 5656 * @reason: the reason for the full modeset 5657 * 5658 * Add all pipes to @state and force a full modeset on the active ones due to 5659 * the description in @reason. 5660 * This function can be called only after new plane states are computed already. 5661 * 5662 * Returns 0 in case of success, negative error code otherwise. 5663 */ 5664 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 5665 const char *reason) 5666 { 5667 struct intel_display *display = to_intel_display(state); 5668 struct intel_crtc *crtc; 5669 5670 for_each_intel_crtc(display, crtc) { 5671 struct intel_crtc_state *crtc_state; 5672 int ret; 5673 5674 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5675 if (IS_ERR(crtc_state)) 5676 return PTR_ERR(crtc_state); 5677 5678 if (!crtc_state->hw.active || 5679 intel_crtc_needs_modeset(crtc_state)) 5680 continue; 5681 5682 ret = intel_modeset_pipe(state, crtc_state, reason); 5683 if (ret) 5684 return ret; 5685 5686 intel_crtc_flag_modeset(crtc_state); 5687 5688 crtc_state->update_planes |= crtc_state->active_planes; 5689 crtc_state->async_flip_planes = 0; 5690 crtc_state->do_async_flip = false; 5691 } 5692 5693 return 0; 5694 } 5695 5696 int intel_modeset_commit_pipes_for_atomic_state(struct intel_atomic_state *state, 5697 u8 pipe_mask, 5698 struct drm_modeset_acquire_ctx *ctx) 5699 { 5700 struct intel_display *display = to_intel_display(state); 5701 struct intel_crtc *crtc; 5702 5703 state->base.acquire_ctx = ctx; 5704 state->internal = true; 5705 5706 for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) { 5707 struct intel_crtc_state *crtc_state = 5708 intel_atomic_get_crtc_state(&state->base, crtc); 5709 5710 if (IS_ERR(crtc_state)) 5711 return PTR_ERR(crtc_state); 5712 5713 crtc_state->uapi.connectors_changed = true; 5714 } 5715 5716 return drm_atomic_commit(&state->base); 5717 } 5718 5719 int intel_modeset_commit_pipes(struct intel_display *display, 5720 u8 pipe_mask, 5721 struct drm_modeset_acquire_ctx *ctx) 5722 { 5723 struct drm_atomic_commit *state; 5724 int ret; 5725 5726 state = drm_atomic_commit_alloc(display->drm); 5727 if (!state) 5728 return -ENOMEM; 5729 5730 ret = intel_modeset_commit_pipes_for_atomic_state(to_intel_atomic_state(state), 5731 pipe_mask, ctx); 5732 5733 drm_atomic_commit_put(state); 5734 5735 return ret; 5736 } 5737 5738 /* 5739 * This implements the workaround described in the "notes" section of the mode 5740 * set sequence documentation. When going from no pipes or single pipe to 5741 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5742 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5743 */ 5744 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5745 { 5746 struct intel_display *display = to_intel_display(state); 5747 struct intel_crtc_state *crtc_state; 5748 struct intel_crtc *crtc; 5749 struct intel_crtc_state *first_crtc_state = NULL; 5750 struct intel_crtc_state *other_crtc_state = NULL; 5751 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5752 5753 /* look at all crtc's that are going to be enabled in during modeset */ 5754 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5755 if (!crtc_state->hw.active || 5756 !intel_crtc_needs_modeset(crtc_state)) 5757 continue; 5758 5759 if (first_crtc_state) { 5760 other_crtc_state = crtc_state; 5761 break; 5762 } else { 5763 first_crtc_state = crtc_state; 5764 first_pipe = crtc->pipe; 5765 } 5766 } 5767 5768 /* No workaround needed? */ 5769 if (!first_crtc_state) 5770 return 0; 5771 5772 /* w/a possibly needed, check how many crtc's are already enabled. */ 5773 for_each_intel_crtc(display, crtc) { 5774 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5775 if (IS_ERR(crtc_state)) 5776 return PTR_ERR(crtc_state); 5777 5778 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5779 5780 if (!crtc_state->hw.active || 5781 intel_crtc_needs_modeset(crtc_state)) 5782 continue; 5783 5784 /* 2 or more enabled crtcs means no need for w/a */ 5785 if (enabled_pipe != INVALID_PIPE) 5786 return 0; 5787 5788 enabled_pipe = crtc->pipe; 5789 } 5790 5791 if (enabled_pipe != INVALID_PIPE) 5792 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5793 else if (other_crtc_state) 5794 other_crtc_state->hsw_workaround_pipe = first_pipe; 5795 5796 return 0; 5797 } 5798 5799 u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, 5800 u8 enabled_pipes) 5801 { 5802 const struct intel_crtc_state *crtc_state; 5803 struct intel_crtc *crtc; 5804 5805 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5806 if (crtc_state->hw.enable) 5807 enabled_pipes |= BIT(crtc->pipe); 5808 else 5809 enabled_pipes &= ~BIT(crtc->pipe); 5810 } 5811 5812 return enabled_pipes; 5813 } 5814 5815 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5816 u8 active_pipes) 5817 { 5818 const struct intel_crtc_state *crtc_state; 5819 struct intel_crtc *crtc; 5820 5821 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5822 if (crtc_state->hw.active) 5823 active_pipes |= BIT(crtc->pipe); 5824 else 5825 active_pipes &= ~BIT(crtc->pipe); 5826 } 5827 5828 return active_pipes; 5829 } 5830 5831 static int intel_modeset_checks(struct intel_atomic_state *state) 5832 { 5833 struct intel_display *display = to_intel_display(state); 5834 5835 state->modeset = true; 5836 5837 if (display->platform.haswell) 5838 return hsw_mode_set_planes_workaround(state); 5839 5840 return 0; 5841 } 5842 5843 static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state, 5844 const struct intel_crtc_state *new_crtc_state) 5845 { 5846 const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode; 5847 const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode; 5848 5849 return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start || 5850 old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end || 5851 old_adjusted_mode->crtc_vsync_start != new_adjusted_mode->crtc_vsync_start || 5852 old_adjusted_mode->crtc_vsync_end != new_adjusted_mode->crtc_vsync_end || 5853 old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal || 5854 old_crtc_state->set_context_latency != new_crtc_state->set_context_latency; 5855 } 5856 5857 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5858 struct intel_crtc_state *new_crtc_state) 5859 { 5860 struct intel_display *display = to_intel_display(new_crtc_state); 5861 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 5862 5863 /* only allow LRR when the timings stay within the VRR range */ 5864 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range) 5865 new_crtc_state->update_lrr = false; 5866 5867 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5868 drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", 5869 crtc->base.base.id, crtc->base.name); 5870 } else { 5871 if (allow_vblank_delay_fastset(old_crtc_state)) 5872 new_crtc_state->update_lrr = true; 5873 new_crtc_state->uapi.mode_changed = false; 5874 } 5875 5876 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, 5877 &new_crtc_state->dp_m_n)) 5878 new_crtc_state->update_m_n = false; 5879 5880 if (!lrr_params_changed(old_crtc_state, new_crtc_state)) 5881 new_crtc_state->update_lrr = false; 5882 5883 if (intel_crtc_needs_modeset(new_crtc_state)) 5884 intel_crtc_flag_modeset(new_crtc_state); 5885 else 5886 new_crtc_state->update_pipe = true; 5887 } 5888 5889 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5890 { 5891 struct intel_display *display = to_intel_display(state); 5892 struct intel_crtc_state __maybe_unused *crtc_state; 5893 struct intel_crtc *crtc; 5894 5895 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 5896 int ret; 5897 5898 ret = intel_crtc_atomic_check(state, crtc); 5899 if (ret) { 5900 drm_dbg_atomic(display->drm, 5901 "[CRTC:%d:%s] atomic driver check failed\n", 5902 crtc->base.base.id, crtc->base.name); 5903 return ret; 5904 } 5905 } 5906 5907 return 0; 5908 } 5909 5910 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5911 u16 transcoders) 5912 { 5913 const struct intel_crtc_state *new_crtc_state; 5914 struct intel_crtc *crtc; 5915 5916 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 5917 if (new_crtc_state->hw.enable && 5918 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5919 intel_crtc_needs_modeset(new_crtc_state)) 5920 return true; 5921 } 5922 5923 return false; 5924 } 5925 5926 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5927 u8 pipes) 5928 { 5929 const struct intel_crtc_state *new_crtc_state; 5930 struct intel_crtc *crtc; 5931 5932 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 5933 if (new_crtc_state->hw.enable && 5934 pipes & BIT(crtc->pipe) && 5935 intel_crtc_needs_modeset(new_crtc_state)) 5936 return true; 5937 } 5938 5939 return false; 5940 } 5941 5942 static int intel_atomic_check_joiner(struct intel_atomic_state *state, 5943 struct intel_crtc *primary_crtc) 5944 { 5945 struct intel_display *display = to_intel_display(state); 5946 struct intel_crtc_state *primary_crtc_state = 5947 intel_atomic_get_new_crtc_state(state, primary_crtc); 5948 struct intel_crtc *secondary_crtc; 5949 5950 if (!primary_crtc_state->joiner_pipes) 5951 return 0; 5952 5953 /* sanity check */ 5954 if (drm_WARN_ON(display->drm, 5955 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) 5956 return -EINVAL; 5957 5958 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) { 5959 drm_dbg_kms(display->drm, 5960 "[CRTC:%d:%s] Cannot act as joiner primary " 5961 "(need 0x%x as pipes, only 0x%x possible)\n", 5962 primary_crtc->base.base.id, primary_crtc->base.name, 5963 primary_crtc_state->joiner_pipes, joiner_pipes(display)); 5964 return -EINVAL; 5965 } 5966 5967 for_each_intel_crtc_in_pipe_mask(display, secondary_crtc, 5968 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5969 struct intel_crtc_state *secondary_crtc_state; 5970 int ret; 5971 5972 secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc); 5973 if (IS_ERR(secondary_crtc_state)) 5974 return PTR_ERR(secondary_crtc_state); 5975 5976 /* primary being enabled, secondary was already configured? */ 5977 if (secondary_crtc_state->uapi.enable) { 5978 drm_dbg_kms(display->drm, 5979 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " 5980 "[CRTC:%d:%s] claiming this CRTC for joiner.\n", 5981 secondary_crtc->base.base.id, secondary_crtc->base.name, 5982 primary_crtc->base.base.id, primary_crtc->base.name); 5983 return -EINVAL; 5984 } 5985 5986 drm_dbg_kms(display->drm, 5987 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", 5988 secondary_crtc->base.base.id, secondary_crtc->base.name, 5989 primary_crtc->base.base.id, primary_crtc->base.name); 5990 5991 secondary_crtc_state->joiner_pipes = 5992 primary_crtc_state->joiner_pipes; 5993 5994 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc); 5995 if (ret) 5996 return ret; 5997 } 5998 5999 return 0; 6000 } 6001 6002 static void kill_joiner_secondaries(struct intel_atomic_state *state, 6003 struct intel_crtc *primary_crtc) 6004 { 6005 struct intel_display *display = to_intel_display(state); 6006 struct intel_crtc_state *primary_crtc_state = 6007 intel_atomic_get_new_crtc_state(state, primary_crtc); 6008 struct intel_crtc *secondary_crtc; 6009 6010 for_each_intel_crtc_in_pipe_mask(display, secondary_crtc, 6011 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 6012 struct intel_crtc_state *secondary_crtc_state = 6013 intel_atomic_get_new_crtc_state(state, secondary_crtc); 6014 6015 secondary_crtc_state->joiner_pipes = 0; 6016 6017 intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc); 6018 } 6019 6020 primary_crtc_state->joiner_pipes = 0; 6021 } 6022 6023 /** 6024 * DOC: asynchronous flip implementation 6025 * 6026 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6027 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6028 * Correspondingly, support is currently added for primary plane only. 6029 * 6030 * Async flip can only change the plane surface address, so anything else 6031 * changing is rejected from the intel_async_flip_check_hw() function. 6032 * Once this check is cleared, flip done interrupt is enabled using 6033 * the intel_crtc_enable_flip_done() function. 6034 * 6035 * As soon as the surface address register is written, flip done interrupt is 6036 * generated and the requested events are sent to the userspace in the interrupt 6037 * handler itself. The timestamp and sequence sent during the flip done event 6038 * correspond to the last vblank and have no relation to the actual time when 6039 * the flip done event was sent. 6040 */ 6041 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6042 struct intel_crtc *crtc) 6043 { 6044 struct intel_display *display = to_intel_display(state); 6045 const struct intel_crtc_state *new_crtc_state = 6046 intel_atomic_get_new_crtc_state(state, crtc); 6047 const struct intel_plane_state *old_plane_state; 6048 struct intel_plane_state *new_plane_state; 6049 struct intel_plane *plane; 6050 int i; 6051 6052 if (!new_crtc_state->uapi.async_flip) 6053 return 0; 6054 6055 if (!new_crtc_state->uapi.active) { 6056 drm_dbg_kms(display->drm, 6057 "[CRTC:%d:%s] not active\n", 6058 crtc->base.base.id, crtc->base.name); 6059 return -EINVAL; 6060 } 6061 6062 if (intel_crtc_needs_modeset(new_crtc_state)) { 6063 drm_dbg_kms(display->drm, 6064 "[CRTC:%d:%s] modeset required\n", 6065 crtc->base.base.id, crtc->base.name); 6066 return -EINVAL; 6067 } 6068 6069 /* 6070 * FIXME: joiner+async flip is busted currently. 6071 * Remove this check once the issues are fixed. 6072 */ 6073 if (new_crtc_state->joiner_pipes) { 6074 drm_dbg_kms(display->drm, 6075 "[CRTC:%d:%s] async flip disallowed with joiner\n", 6076 crtc->base.base.id, crtc->base.name); 6077 return -EINVAL; 6078 } 6079 6080 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6081 new_plane_state, i) { 6082 if (plane->pipe != crtc->pipe) 6083 continue; 6084 6085 /* 6086 * TODO: Async flip is only supported through the page flip IOCTL 6087 * as of now. So support currently added for primary plane only. 6088 * Support for other planes on platforms on which supports 6089 * this(vlv/chv and icl+) should be added when async flip is 6090 * enabled in the atomic IOCTL path. 6091 */ 6092 if (!plane->async_flip) { 6093 drm_dbg_kms(display->drm, 6094 "[PLANE:%d:%s] async flip not supported\n", 6095 plane->base.base.id, plane->base.name); 6096 return -EINVAL; 6097 } 6098 6099 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6100 drm_dbg_kms(display->drm, 6101 "[PLANE:%d:%s] no old or new framebuffer\n", 6102 plane->base.base.id, plane->base.name); 6103 return -EINVAL; 6104 } 6105 } 6106 6107 return 0; 6108 } 6109 6110 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6111 { 6112 struct intel_display *display = to_intel_display(state); 6113 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6114 const struct intel_plane_state *new_plane_state, *old_plane_state; 6115 struct intel_plane *plane; 6116 int i; 6117 6118 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6119 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6120 6121 if (!new_crtc_state->uapi.async_flip) 6122 return 0; 6123 6124 if (!new_crtc_state->hw.active) { 6125 drm_dbg_kms(display->drm, 6126 "[CRTC:%d:%s] not active\n", 6127 crtc->base.base.id, crtc->base.name); 6128 return -EINVAL; 6129 } 6130 6131 if (intel_crtc_needs_modeset(new_crtc_state)) { 6132 drm_dbg_kms(display->drm, 6133 "[CRTC:%d:%s] modeset required\n", 6134 crtc->base.base.id, crtc->base.name); 6135 return -EINVAL; 6136 } 6137 6138 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6139 drm_dbg_kms(display->drm, 6140 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6141 crtc->base.base.id, crtc->base.name); 6142 return -EINVAL; 6143 } 6144 6145 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6146 new_plane_state, i) { 6147 if (plane->pipe != crtc->pipe) 6148 continue; 6149 6150 /* 6151 * Only async flip capable planes should be in the state 6152 * if we're really about to ask the hardware to perform 6153 * an async flip. We should never get this far otherwise. 6154 */ 6155 if (drm_WARN_ON(display->drm, 6156 new_crtc_state->do_async_flip && !plane->async_flip)) 6157 return -EINVAL; 6158 6159 /* 6160 * Only check async flip capable planes other planes 6161 * may be involved in the initial commit due to 6162 * the wm0/ddb optimization. 6163 * 6164 * TODO maybe should track which planes actually 6165 * were requested to do the async flip... 6166 */ 6167 if (!plane->async_flip) 6168 continue; 6169 6170 if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format, 6171 new_plane_state->hw.fb->modifier)) { 6172 drm_dbg_kms(display->drm, 6173 "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", 6174 plane->base.base.id, plane->base.name, 6175 &new_plane_state->hw.fb->format->format, 6176 new_plane_state->hw.fb->modifier); 6177 return -EINVAL; 6178 } 6179 6180 /* 6181 * We turn the first async flip request into a sync flip 6182 * so that we can reconfigure the plane (eg. change modifier). 6183 */ 6184 if (!new_crtc_state->do_async_flip) 6185 continue; 6186 6187 if (old_plane_state->view.color_plane[0].mapping_stride != 6188 new_plane_state->view.color_plane[0].mapping_stride) { 6189 drm_dbg_kms(display->drm, 6190 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6191 plane->base.base.id, plane->base.name); 6192 return -EINVAL; 6193 } 6194 6195 if (old_plane_state->hw.fb->modifier != 6196 new_plane_state->hw.fb->modifier) { 6197 drm_dbg_kms(display->drm, 6198 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6199 plane->base.base.id, plane->base.name); 6200 return -EINVAL; 6201 } 6202 6203 if (old_plane_state->hw.fb->format != 6204 new_plane_state->hw.fb->format) { 6205 drm_dbg_kms(display->drm, 6206 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6207 plane->base.base.id, plane->base.name); 6208 return -EINVAL; 6209 } 6210 6211 if (old_plane_state->hw.rotation != 6212 new_plane_state->hw.rotation) { 6213 drm_dbg_kms(display->drm, 6214 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6215 plane->base.base.id, plane->base.name); 6216 return -EINVAL; 6217 } 6218 6219 if (skl_plane_aux_dist(old_plane_state, 0) != 6220 skl_plane_aux_dist(new_plane_state, 0)) { 6221 drm_dbg_kms(display->drm, 6222 "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n", 6223 plane->base.base.id, plane->base.name); 6224 return -EINVAL; 6225 } 6226 6227 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6228 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6229 drm_dbg_kms(display->drm, 6230 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6231 plane->base.base.id, plane->base.name); 6232 return -EINVAL; 6233 } 6234 6235 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6236 drm_dbg_kms(display->drm, 6237 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6238 plane->base.base.id, plane->base.name); 6239 return -EINVAL; 6240 } 6241 6242 if (old_plane_state->hw.pixel_blend_mode != 6243 new_plane_state->hw.pixel_blend_mode) { 6244 drm_dbg_kms(display->drm, 6245 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6246 plane->base.base.id, plane->base.name); 6247 return -EINVAL; 6248 } 6249 6250 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6251 drm_dbg_kms(display->drm, 6252 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6253 plane->base.base.id, plane->base.name); 6254 return -EINVAL; 6255 } 6256 6257 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6258 drm_dbg_kms(display->drm, 6259 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6260 plane->base.base.id, plane->base.name); 6261 return -EINVAL; 6262 } 6263 6264 /* plane decryption is allow to change only in synchronous flips */ 6265 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6266 drm_dbg_kms(display->drm, 6267 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6268 plane->base.base.id, plane->base.name); 6269 return -EINVAL; 6270 } 6271 } 6272 6273 return 0; 6274 } 6275 6276 static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) 6277 { 6278 struct intel_display *display = to_intel_display(state); 6279 const struct intel_plane_state *plane_state; 6280 struct intel_crtc_state *crtc_state; 6281 struct intel_plane *plane; 6282 struct intel_crtc *crtc; 6283 u8 affected_pipes = 0; 6284 u8 modeset_pipes = 0; 6285 int i; 6286 6287 /* 6288 * Any plane which is in use by the joiner needs its crtc. 6289 * Pull those in first as this will not have happened yet 6290 * if the plane remains disabled according to uapi. 6291 */ 6292 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6293 crtc = to_intel_crtc(plane_state->hw.crtc); 6294 if (!crtc) 6295 continue; 6296 6297 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6298 if (IS_ERR(crtc_state)) 6299 return PTR_ERR(crtc_state); 6300 } 6301 6302 /* Now pull in all joined crtcs */ 6303 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 6304 affected_pipes |= crtc_state->joiner_pipes; 6305 if (intel_crtc_needs_modeset(crtc_state)) 6306 modeset_pipes |= crtc_state->joiner_pipes; 6307 } 6308 6309 for_each_intel_crtc_in_pipe_mask(display, crtc, affected_pipes) { 6310 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6311 if (IS_ERR(crtc_state)) 6312 return PTR_ERR(crtc_state); 6313 } 6314 6315 for_each_intel_crtc_in_pipe_mask(display, crtc, modeset_pipes) { 6316 int ret; 6317 6318 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6319 6320 crtc_state->uapi.mode_changed = true; 6321 6322 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6323 if (ret) 6324 return ret; 6325 6326 ret = intel_plane_add_affected(state, crtc); 6327 if (ret) 6328 return ret; 6329 } 6330 6331 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 6332 /* Kill old joiner link, we may re-establish afterwards */ 6333 if (intel_crtc_needs_modeset(crtc_state) && 6334 intel_crtc_is_joiner_primary(crtc_state)) 6335 kill_joiner_secondaries(state, crtc); 6336 } 6337 6338 return 0; 6339 } 6340 6341 static int intel_atomic_check_config(struct intel_atomic_state *state, 6342 struct intel_link_bw_limits *limits, 6343 enum pipe *failed_pipe) 6344 { 6345 struct intel_display *display = to_intel_display(state); 6346 struct intel_crtc_state *new_crtc_state; 6347 struct intel_crtc *crtc; 6348 int ret; 6349 6350 *failed_pipe = INVALID_PIPE; 6351 6352 ret = intel_joiner_add_affected_crtcs(state); 6353 if (ret) 6354 return ret; 6355 6356 ret = intel_fdi_add_affected_crtcs(state); 6357 if (ret) 6358 return ret; 6359 6360 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6361 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6362 if (!intel_crtc_is_joiner_secondary(new_crtc_state)) 6363 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6364 continue; 6365 } 6366 6367 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6368 continue; 6369 6370 ret = intel_crtc_prepare_cleared_state(state, crtc); 6371 if (ret) 6372 goto fail; 6373 6374 if (!new_crtc_state->hw.enable) 6375 continue; 6376 6377 ret = intel_modeset_pipe_config(state, crtc, limits); 6378 if (ret) 6379 goto fail; 6380 } 6381 6382 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6383 if (!intel_crtc_needs_modeset(new_crtc_state)) 6384 continue; 6385 6386 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6387 continue; 6388 6389 if (!new_crtc_state->hw.enable) 6390 continue; 6391 6392 ret = intel_modeset_pipe_config_late(state, crtc); 6393 if (ret) 6394 goto fail; 6395 } 6396 6397 fail: 6398 if (ret) 6399 *failed_pipe = crtc->pipe; 6400 6401 return ret; 6402 } 6403 6404 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) 6405 { 6406 struct intel_link_bw_limits new_limits; 6407 struct intel_link_bw_limits old_limits; 6408 int ret; 6409 6410 intel_link_bw_init_limits(state, &new_limits); 6411 old_limits = new_limits; 6412 6413 while (true) { 6414 enum pipe failed_pipe; 6415 6416 ret = intel_atomic_check_config(state, &new_limits, 6417 &failed_pipe); 6418 if (ret) { 6419 /* 6420 * The bpp limit for a pipe is below the minimum it supports, set the 6421 * limit to the minimum and recalculate the config. 6422 */ 6423 if (ret == -EINVAL && 6424 intel_link_bw_set_bpp_limit_for_pipe(state, 6425 &old_limits, 6426 &new_limits, 6427 failed_pipe)) 6428 continue; 6429 6430 break; 6431 } 6432 6433 old_limits = new_limits; 6434 6435 ret = intel_link_bw_atomic_check(state, &new_limits); 6436 if (ret != -EAGAIN) 6437 break; 6438 } 6439 6440 return ret; 6441 } 6442 /** 6443 * intel_atomic_check - validate state object 6444 * @dev: drm device 6445 * @_state: state to validate 6446 */ 6447 int intel_atomic_check(struct drm_device *dev, 6448 struct drm_atomic_commit *_state) 6449 { 6450 struct intel_display *display = to_intel_display(dev); 6451 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6452 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6453 struct intel_crtc *crtc; 6454 int ret; 6455 6456 if (!intel_display_driver_check_access(display)) 6457 return -ENODEV; 6458 6459 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6460 /* 6461 * crtc's state no longer considered to be inherited 6462 * after the first userspace/client initiated commit. 6463 */ 6464 if (!state->internal) 6465 new_crtc_state->inherited = false; 6466 6467 if (new_crtc_state->inherited != old_crtc_state->inherited) 6468 new_crtc_state->uapi.mode_changed = true; 6469 6470 if (new_crtc_state->uapi.scaling_filter != 6471 old_crtc_state->uapi.scaling_filter) 6472 new_crtc_state->uapi.mode_changed = true; 6473 6474 if (new_crtc_state->uapi.sharpness_strength != 6475 old_crtc_state->uapi.sharpness_strength) 6476 new_crtc_state->uapi.mode_changed = true; 6477 } 6478 6479 intel_vrr_check_modeset(state); 6480 6481 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6482 if (ret) 6483 goto fail; 6484 6485 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6486 ret = intel_async_flip_check_uapi(state, crtc); 6487 if (ret) 6488 return ret; 6489 } 6490 6491 ret = intel_atomic_check_config_and_link(state); 6492 if (ret) 6493 goto fail; 6494 6495 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6496 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6497 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6498 copy_joiner_crtc_state_nomodeset(state, crtc); 6499 continue; 6500 } 6501 6502 if (intel_crtc_is_joiner_secondary(new_crtc_state)) { 6503 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable); 6504 continue; 6505 } 6506 6507 ret = intel_atomic_check_joiner(state, crtc); 6508 if (ret) 6509 goto fail; 6510 } 6511 6512 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6513 if (!intel_crtc_needs_modeset(new_crtc_state)) 6514 continue; 6515 6516 intel_joiner_adjust_pipe_src(new_crtc_state); 6517 6518 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6519 } 6520 6521 /** 6522 * Check if fastset is allowed by external dependencies like other 6523 * pipes and transcoders. 6524 * 6525 * Right now it only forces a fullmodeset when the MST master 6526 * transcoder did not changed but the pipe of the master transcoder 6527 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6528 * in case of port synced crtcs, if one of the synced crtcs 6529 * needs a full modeset, all other synced crtcs should be 6530 * forced a full modeset. 6531 */ 6532 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 6533 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6534 continue; 6535 6536 if (intel_dp_mst_crtc_needs_modeset(state, crtc)) 6537 intel_crtc_flag_modeset(new_crtc_state); 6538 6539 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6540 enum transcoder master = new_crtc_state->mst_master_transcoder; 6541 6542 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) 6543 intel_crtc_flag_modeset(new_crtc_state); 6544 } 6545 6546 if (is_trans_port_sync_mode(new_crtc_state)) { 6547 u16 trans = new_crtc_state->sync_mode_slaves_mask; 6548 6549 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6550 trans |= BIT(new_crtc_state->master_transcoder); 6551 6552 if (intel_cpu_transcoders_need_modeset(state, trans)) 6553 intel_crtc_flag_modeset(new_crtc_state); 6554 } 6555 6556 if (new_crtc_state->joiner_pipes) { 6557 if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes)) 6558 intel_crtc_flag_modeset(new_crtc_state); 6559 } 6560 } 6561 6562 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6563 if (!intel_crtc_needs_modeset(new_crtc_state)) 6564 continue; 6565 6566 intel_dpll_release(state, crtc); 6567 } 6568 6569 if (intel_any_crtc_needs_modeset(state) && !check_digital_port_conflicts(state)) { 6570 drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n"); 6571 ret = -EINVAL; 6572 goto fail; 6573 } 6574 6575 ret = intel_plane_atomic_check(state); 6576 if (ret) 6577 goto fail; 6578 6579 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 6580 new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state); 6581 6582 ret = intel_compute_global_watermarks(state); 6583 if (ret) 6584 goto fail; 6585 6586 ret = intel_bw_atomic_check(state); 6587 if (ret) 6588 goto fail; 6589 6590 ret = intel_cdclk_atomic_check(state); 6591 if (ret) 6592 goto fail; 6593 6594 if (intel_any_crtc_needs_modeset(state)) { 6595 ret = intel_modeset_checks(state); 6596 if (ret) 6597 goto fail; 6598 } 6599 6600 ret = intel_pmdemand_atomic_check(state); 6601 if (ret) 6602 goto fail; 6603 6604 ret = intel_atomic_check_crtcs(state); 6605 if (ret) 6606 goto fail; 6607 6608 ret = intel_fbc_atomic_check(state); 6609 if (ret) 6610 goto fail; 6611 6612 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6613 intel_color_assert_luts(new_crtc_state); 6614 6615 ret = intel_async_flip_check_hw(state, crtc); 6616 if (ret) 6617 goto fail; 6618 6619 /* Either full modeset or fastset (or neither), never both */ 6620 drm_WARN_ON(display->drm, 6621 intel_crtc_needs_modeset(new_crtc_state) && 6622 intel_crtc_needs_fastset(new_crtc_state)); 6623 6624 if (!intel_crtc_needs_modeset(new_crtc_state) && 6625 !intel_crtc_needs_fastset(new_crtc_state)) 6626 continue; 6627 6628 intel_crtc_state_dump(new_crtc_state, state, 6629 intel_crtc_needs_modeset(new_crtc_state) ? 6630 "modeset" : "fastset"); 6631 } 6632 6633 return 0; 6634 6635 fail: 6636 if (ret == -EDEADLK) 6637 return ret; 6638 6639 /* 6640 * FIXME would probably be nice to know which crtc specifically 6641 * caused the failure, in cases where we can pinpoint it. 6642 */ 6643 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) 6644 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6645 6646 return ret; 6647 } 6648 6649 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6650 { 6651 int ret; 6652 6653 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6654 if (ret < 0) 6655 return ret; 6656 6657 return 0; 6658 } 6659 6660 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6661 struct intel_crtc_state *crtc_state) 6662 { 6663 struct intel_display *display = to_intel_display(crtc); 6664 6665 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) 6666 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 6667 6668 if (crtc_state->has_pch_encoder) { 6669 enum pipe pch_transcoder = 6670 intel_crtc_pch_transcoder(crtc); 6671 6672 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true); 6673 } 6674 } 6675 6676 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6677 const struct intel_crtc_state *new_crtc_state) 6678 { 6679 struct intel_display *display = to_intel_display(new_crtc_state); 6680 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6681 6682 /* 6683 * Update pipe size and adjust fitter if needed: the reason for this is 6684 * that in compute_mode_changes we check the native mode (not the pfit 6685 * mode) to see if we can flip rather than do a full mode set. In the 6686 * fastboot case, we'll flip, but if we don't update the pipesrc and 6687 * pfit state, we'll end up with a big fb scanned out into the wrong 6688 * sized surface. 6689 */ 6690 intel_set_pipe_src_size(new_crtc_state); 6691 6692 /* on skylake this is done by detaching scalers */ 6693 if (DISPLAY_VER(display) >= 9) { 6694 if (new_crtc_state->pch_pfit.enabled) 6695 skl_pfit_enable(new_crtc_state); 6696 } else if (HAS_PCH_SPLIT(display)) { 6697 if (new_crtc_state->pch_pfit.enabled) 6698 ilk_pfit_enable(new_crtc_state); 6699 else if (old_crtc_state->pch_pfit.enabled) 6700 ilk_pfit_disable(old_crtc_state); 6701 } 6702 6703 /* 6704 * The register is supposedly single buffered so perhaps 6705 * not 100% correct to do this here. But SKL+ calculate 6706 * this based on the adjust pixel rate so pfit changes do 6707 * affect it and so it must be updated for fastsets. 6708 * HSW/BDW only really need this here for fastboot, after 6709 * that the value should not change without a full modeset. 6710 */ 6711 if (DISPLAY_VER(display) >= 9 || 6712 display->platform.broadwell || display->platform.haswell) 6713 hsw_set_linetime_wm(new_crtc_state); 6714 6715 if (new_crtc_state->update_m_n) { 6716 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6717 &new_crtc_state->dp_m_n); 6718 intel_cmtg_set_m_n(new_crtc_state); 6719 } 6720 6721 if (new_crtc_state->update_lrr) { 6722 intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder); 6723 intel_cmtg_set_timings(new_crtc_state, LRR); 6724 intel_vrr_set_fixed_rr_timings(new_crtc_state, new_crtc_state->cpu_transcoder); 6725 intel_cmtg_set_vrr_timings(new_crtc_state); 6726 intel_vrr_transcoder_enable(new_crtc_state); 6727 } 6728 } 6729 6730 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6731 struct intel_crtc *crtc) 6732 { 6733 struct intel_display *display = to_intel_display(state); 6734 const struct intel_crtc_state *old_crtc_state = 6735 intel_atomic_get_old_crtc_state(state, crtc); 6736 const struct intel_crtc_state *new_crtc_state = 6737 intel_atomic_get_new_crtc_state(state, crtc); 6738 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6739 6740 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6741 6742 /* 6743 * During modesets pipe configuration was programmed as the 6744 * CRTC was enabled. 6745 */ 6746 if (!modeset) { 6747 if (intel_crtc_needs_color_update(new_crtc_state)) 6748 intel_color_commit_arm(NULL, new_crtc_state); 6749 6750 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 6751 bdw_set_pipe_misc(NULL, new_crtc_state); 6752 6753 if (intel_crtc_needs_fastset(new_crtc_state)) 6754 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6755 } 6756 6757 intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); 6758 6759 intel_atomic_update_watermarks(state, crtc); 6760 } 6761 6762 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6763 struct intel_crtc *crtc) 6764 { 6765 struct intel_display *display = to_intel_display(state); 6766 const struct intel_crtc_state *new_crtc_state = 6767 intel_atomic_get_new_crtc_state(state, crtc); 6768 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6769 6770 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6771 6772 /* 6773 * Disable the scaler(s) after the plane(s) so that we don't 6774 * get a catastrophic underrun even if the two operations 6775 * end up happening in two different frames. 6776 */ 6777 if (DISPLAY_VER(display) >= 9 && !modeset) 6778 skl_detach_scalers(NULL, new_crtc_state); 6779 6780 if (!modeset && 6781 intel_crtc_needs_color_update(new_crtc_state) && 6782 !intel_color_uses_dsb(new_crtc_state) && 6783 HAS_DOUBLE_BUFFERED_LUT(display)) 6784 intel_color_load_luts(new_crtc_state); 6785 6786 if (intel_crtc_vrr_enabling(state, crtc)) 6787 intel_vrr_enable(new_crtc_state); 6788 } 6789 6790 static void intel_enable_crtc(struct intel_atomic_state *state, 6791 struct intel_crtc *crtc) 6792 { 6793 struct intel_display *display = to_intel_display(state); 6794 const struct intel_crtc_state *new_crtc_state = 6795 intel_atomic_get_new_crtc_state(state, crtc); 6796 struct intel_crtc *pipe_crtc; 6797 6798 if (!intel_crtc_needs_modeset(new_crtc_state)) 6799 return; 6800 6801 for_each_intel_crtc_in_pipe_mask_reverse(display, pipe_crtc, 6802 intel_crtc_joined_pipe_mask(new_crtc_state)) { 6803 const struct intel_crtc_state *pipe_crtc_state = 6804 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6805 6806 /* VRR will be enable later, if required */ 6807 intel_crtc_update_active_timings(pipe_crtc_state, false); 6808 } 6809 6810 intel_psr_notify_pipe_change(state, crtc, true); 6811 6812 display->modeset.funcs->crtc_enable(state, crtc); 6813 6814 intel_crtc_wait_for_next_vblank(crtc); 6815 6816 /* vblanks work again, re-enable pipe CRC. */ 6817 intel_crtc_enable_pipe_crc(crtc); 6818 } 6819 6820 static void intel_pre_update_crtc(struct intel_atomic_state *state, 6821 struct intel_crtc *crtc) 6822 { 6823 struct intel_display *display = to_intel_display(state); 6824 const struct intel_crtc_state *old_crtc_state = 6825 intel_atomic_get_old_crtc_state(state, crtc); 6826 struct intel_crtc_state *new_crtc_state = 6827 intel_atomic_get_new_crtc_state(state, crtc); 6828 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6829 6830 if (old_crtc_state->inherited || 6831 intel_crtc_needs_modeset(new_crtc_state)) { 6832 if (HAS_DPT(display)) 6833 intel_dpt_configure(crtc); 6834 } 6835 6836 if (!modeset) { 6837 if (new_crtc_state->preload_luts && 6838 intel_crtc_needs_color_update(new_crtc_state)) 6839 intel_color_load_luts(new_crtc_state); 6840 6841 intel_pre_plane_update(state, crtc); 6842 6843 if (intel_crtc_needs_fastset(new_crtc_state)) 6844 intel_encoders_update_pipe(state, crtc); 6845 6846 if (DISPLAY_VER(display) >= 11 && 6847 intel_crtc_needs_fastset(new_crtc_state)) 6848 icl_set_pipe_chicken(new_crtc_state); 6849 6850 if (vrr_params_changed(old_crtc_state, new_crtc_state) || 6851 cmrr_params_changed(old_crtc_state, new_crtc_state)) 6852 intel_vrr_set_transcoder_timings(new_crtc_state); 6853 } 6854 6855 intel_fbc_update(state, crtc); 6856 6857 drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); 6858 6859 if (!modeset && 6860 intel_crtc_needs_color_update(new_crtc_state) && 6861 !new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6862 intel_color_commit_noarm(NULL, new_crtc_state); 6863 6864 if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6865 intel_crtc_planes_update_noarm(NULL, state, crtc); 6866 } 6867 6868 static void intel_update_crtc(struct intel_atomic_state *state, 6869 struct intel_crtc *crtc) 6870 { 6871 const struct intel_crtc_state *old_crtc_state = 6872 intel_atomic_get_old_crtc_state(state, crtc); 6873 struct intel_crtc_state *new_crtc_state = 6874 intel_atomic_get_new_crtc_state(state, crtc); 6875 6876 if (new_crtc_state->use_flipq) { 6877 intel_flipq_enable(new_crtc_state); 6878 6879 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event); 6880 6881 intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0, 6882 new_crtc_state->dsb_commit); 6883 } else if (new_crtc_state->use_dsb) { 6884 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); 6885 6886 intel_dsb_commit(new_crtc_state->dsb_commit); 6887 } else { 6888 /* Perform vblank evasion around commit operation */ 6889 intel_pipe_update_start(state, crtc); 6890 6891 if (new_crtc_state->dsb_commit) 6892 intel_dsb_commit(new_crtc_state->dsb_commit); 6893 6894 commit_pipe_pre_planes(state, crtc); 6895 6896 intel_crtc_planes_update_arm(NULL, state, crtc); 6897 6898 commit_pipe_post_planes(state, crtc); 6899 6900 intel_pipe_update_end(state, crtc); 6901 } 6902 6903 /* 6904 * VRR/Seamless M/N update may need to update frame timings. 6905 * 6906 * FIXME Should be synchronized with the start of vblank somehow... 6907 */ 6908 if (intel_crtc_vrr_enabling(state, crtc) || 6909 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 6910 intel_crtc_update_active_timings(new_crtc_state, 6911 new_crtc_state->vrr.enable); 6912 6913 if (new_crtc_state->vrr.dc_balance.enable) 6914 intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); 6915 6916 /* 6917 * We usually enable FIFO underrun interrupts as part of the 6918 * CRTC enable sequence during modesets. But when we inherit a 6919 * valid pipe configuration from the BIOS we need to take care 6920 * of enabling them on the CRTC's first fastset. 6921 */ 6922 if (intel_crtc_needs_fastset(new_crtc_state) && 6923 old_crtc_state->inherited) 6924 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6925 6926 if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc) && 6927 intel_cmtg_is_allowed(new_crtc_state)) { 6928 intel_cmtg_set_clk_select(new_crtc_state); 6929 intel_cmtg_disable(new_crtc_state); 6930 } 6931 } 6932 6933 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6934 struct intel_crtc *crtc) 6935 { 6936 struct intel_display *display = to_intel_display(state); 6937 const struct intel_crtc_state *old_crtc_state = 6938 intel_atomic_get_old_crtc_state(state, crtc); 6939 struct intel_crtc *pipe_crtc; 6940 6941 /* 6942 * We need to disable pipe CRC before disabling the pipe, 6943 * or we race against vblank off. 6944 */ 6945 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 6946 intel_crtc_joined_pipe_mask(old_crtc_state)) 6947 intel_crtc_disable_pipe_crc(pipe_crtc); 6948 6949 intel_psr_notify_pipe_change(state, crtc, false); 6950 6951 display->modeset.funcs->crtc_disable(state, crtc); 6952 6953 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 6954 intel_crtc_joined_pipe_mask(old_crtc_state)) { 6955 const struct intel_crtc_state *new_pipe_crtc_state = 6956 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6957 6958 pipe_crtc->active = false; 6959 intel_fbc_disable(pipe_crtc); 6960 6961 if (!new_pipe_crtc_state->hw.active) 6962 intel_initial_watermarks(state, pipe_crtc); 6963 } 6964 } 6965 6966 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6967 { 6968 struct intel_display *display = to_intel_display(state); 6969 const struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6970 struct intel_crtc *crtc; 6971 u8 disable_pipes = 0; 6972 6973 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 6974 if (!intel_crtc_needs_modeset(new_crtc_state)) 6975 continue; 6976 6977 /* 6978 * Needs to be done even for pipes 6979 * that weren't enabled previously. 6980 */ 6981 intel_pre_plane_update(state, crtc); 6982 6983 if (!old_crtc_state->hw.active) 6984 continue; 6985 6986 disable_pipes |= BIT(crtc->pipe); 6987 } 6988 6989 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) { 6990 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6991 continue; 6992 6993 intel_crtc_disable_planes(state, crtc); 6994 6995 drm_vblank_work_flush_all(&crtc->base); 6996 } 6997 6998 /* Only disable port sync and MST slaves */ 6999 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) { 7000 if ((disable_pipes & BIT(crtc->pipe)) == 0) 7001 continue; 7002 7003 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 7004 continue; 7005 7006 /* In case of Transcoder port Sync master slave CRTCs can be 7007 * assigned in any order and we need to make sure that 7008 * slave CRTCs are disabled first and then master CRTC since 7009 * Slave vblanks are masked till Master Vblanks. 7010 */ 7011 if (!is_trans_port_sync_slave(old_crtc_state) && 7012 !intel_dp_mst_is_slave_trans(old_crtc_state)) 7013 continue; 7014 7015 intel_old_crtc_state_disables(state, crtc); 7016 7017 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 7018 } 7019 7020 /* Disable everything else left on */ 7021 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) { 7022 if ((disable_pipes & BIT(crtc->pipe)) == 0) 7023 continue; 7024 7025 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 7026 continue; 7027 7028 intel_old_crtc_state_disables(state, crtc); 7029 7030 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 7031 } 7032 7033 drm_WARN_ON(display->drm, disable_pipes); 7034 } 7035 7036 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7037 { 7038 struct intel_crtc_state *new_crtc_state; 7039 struct intel_crtc *crtc; 7040 7041 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7042 if (!new_crtc_state->hw.active) 7043 continue; 7044 7045 intel_enable_crtc(state, crtc); 7046 intel_pre_update_crtc(state, crtc); 7047 } 7048 7049 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7050 if (!new_crtc_state->hw.active) 7051 continue; 7052 7053 intel_update_crtc(state, crtc); 7054 } 7055 } 7056 7057 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7058 { 7059 struct intel_display *display = to_intel_display(state); 7060 struct intel_crtc *crtc; 7061 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7062 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7063 u8 update_pipes = 0, modeset_pipes = 0; 7064 7065 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7066 enum pipe pipe = crtc->pipe; 7067 7068 if (!new_crtc_state->hw.active) 7069 continue; 7070 7071 /* ignore allocations for crtc's that have been turned off. */ 7072 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7073 entries[pipe] = old_crtc_state->wm.skl.ddb; 7074 update_pipes |= BIT(pipe); 7075 } else { 7076 modeset_pipes |= BIT(pipe); 7077 } 7078 } 7079 7080 /* 7081 * Whenever the number of active pipes changes, we need to make sure we 7082 * update the pipes in the right order so that their ddb allocations 7083 * never overlap with each other between CRTC updates. Otherwise we'll 7084 * cause pipe underruns and other bad stuff. 7085 * 7086 * So first lets enable all pipes that do not need a fullmodeset as 7087 * those don't have any external dependency. 7088 */ 7089 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7090 enum pipe pipe = crtc->pipe; 7091 7092 if ((update_pipes & BIT(pipe)) == 0) 7093 continue; 7094 7095 intel_pre_update_crtc(state, crtc); 7096 } 7097 7098 intel_dbuf_mbus_pre_ddb_update(state); 7099 7100 while (update_pipes) { 7101 /* 7102 * Commit in reverse order to make joiner primary 7103 * send the uapi events after secondaries are done. 7104 */ 7105 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, new_crtc_state) { 7106 enum pipe pipe = crtc->pipe; 7107 7108 if ((update_pipes & BIT(pipe)) == 0) 7109 continue; 7110 7111 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7112 entries, I915_MAX_PIPES, pipe)) 7113 continue; 7114 7115 entries[pipe] = new_crtc_state->wm.skl.ddb; 7116 update_pipes &= ~BIT(pipe); 7117 7118 intel_update_crtc(state, crtc); 7119 7120 /* 7121 * If this is an already active pipe, it's DDB changed, 7122 * and this isn't the last pipe that needs updating 7123 * then we need to wait for a vblank to pass for the 7124 * new ddb allocation to take effect. 7125 */ 7126 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7127 &old_crtc_state->wm.skl.ddb) && 7128 (update_pipes | modeset_pipes)) 7129 intel_crtc_wait_for_next_vblank(crtc); 7130 } 7131 } 7132 7133 intel_dbuf_mbus_post_ddb_update(state); 7134 7135 update_pipes = modeset_pipes; 7136 7137 /* 7138 * Enable all pipes that needs a modeset and do not depends on other 7139 * pipes 7140 */ 7141 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7142 enum pipe pipe = crtc->pipe; 7143 7144 if ((modeset_pipes & BIT(pipe)) == 0) 7145 continue; 7146 7147 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7148 continue; 7149 7150 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7151 is_trans_port_sync_master(new_crtc_state)) 7152 continue; 7153 7154 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7155 7156 intel_enable_crtc(state, crtc); 7157 } 7158 7159 /* 7160 * Then we enable all remaining pipes that depend on other 7161 * pipes: MST slaves and port sync masters 7162 */ 7163 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7164 enum pipe pipe = crtc->pipe; 7165 7166 if ((modeset_pipes & BIT(pipe)) == 0) 7167 continue; 7168 7169 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7170 continue; 7171 7172 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7173 7174 intel_enable_crtc(state, crtc); 7175 } 7176 7177 /* 7178 * Finally we do the plane updates/etc. for all pipes that got enabled. 7179 */ 7180 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7181 enum pipe pipe = crtc->pipe; 7182 7183 if ((update_pipes & BIT(pipe)) == 0) 7184 continue; 7185 7186 intel_pre_update_crtc(state, crtc); 7187 } 7188 7189 /* 7190 * Commit in reverse order to make joiner primary 7191 * send the uapi events after secondaries are done. 7192 */ 7193 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state) { 7194 enum pipe pipe = crtc->pipe; 7195 7196 if ((update_pipes & BIT(pipe)) == 0) 7197 continue; 7198 7199 drm_WARN_ON(display->drm, 7200 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7201 entries, I915_MAX_PIPES, pipe)); 7202 7203 entries[pipe] = new_crtc_state->wm.skl.ddb; 7204 update_pipes &= ~BIT(pipe); 7205 7206 intel_update_crtc(state, crtc); 7207 } 7208 7209 drm_WARN_ON(display->drm, modeset_pipes); 7210 drm_WARN_ON(display->drm, update_pipes); 7211 } 7212 7213 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7214 { 7215 struct drm_plane *plane; 7216 struct drm_plane_state *new_plane_state; 7217 long ret; 7218 int i; 7219 7220 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) { 7221 if (new_plane_state->fence) { 7222 ret = dma_fence_wait_timeout(new_plane_state->fence, false, 7223 i915_fence_timeout()); 7224 if (ret <= 0) 7225 break; 7226 7227 dma_fence_put(new_plane_state->fence); 7228 new_plane_state->fence = NULL; 7229 } 7230 } 7231 } 7232 7233 static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state) 7234 { 7235 if (crtc_state->dsb_commit) 7236 intel_dsb_wait(crtc_state->dsb_commit); 7237 7238 intel_color_wait_commit(crtc_state); 7239 } 7240 7241 static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state) 7242 { 7243 if (crtc_state->dsb_commit) { 7244 intel_dsb_cleanup(crtc_state->dsb_commit); 7245 crtc_state->dsb_commit = NULL; 7246 } 7247 7248 intel_color_cleanup_commit(crtc_state); 7249 } 7250 7251 static void intel_atomic_cleanup_work(struct work_struct *work) 7252 { 7253 struct intel_atomic_state *state = 7254 container_of(work, struct intel_atomic_state, cleanup_work); 7255 struct intel_display *display = to_intel_display(state); 7256 struct intel_crtc_state *old_crtc_state; 7257 struct intel_crtc *crtc; 7258 7259 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state) 7260 intel_atomic_dsb_cleanup(old_crtc_state); 7261 7262 drm_atomic_helper_cleanup_planes(display->drm, &state->base); 7263 drm_atomic_helper_commit_cleanup_done(&state->base); 7264 drm_atomic_commit_put(&state->base); 7265 } 7266 7267 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7268 { 7269 struct intel_display *display = to_intel_display(state); 7270 struct intel_plane *plane; 7271 struct intel_plane_state *plane_state; 7272 int i; 7273 7274 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7275 struct drm_framebuffer *fb = plane_state->hw.fb; 7276 int cc_plane; 7277 int ret; 7278 7279 if (!fb) 7280 continue; 7281 7282 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7283 if (cc_plane < 0) 7284 continue; 7285 7286 /* 7287 * The layout of the fast clear color value expected by HW 7288 * (the DRM ABI requiring this value to be located in fb at 7289 * offset 0 of cc plane, plane #2 previous generations or 7290 * plane #1 for flat ccs): 7291 * - 4 x 4 bytes per-channel value 7292 * (in surface type specific float/int format provided by the fb user) 7293 * - 8 bytes native color value used by the display 7294 * (converted/written by GPU during a fast clear operation using the 7295 * above per-channel values) 7296 * 7297 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7298 * caller made sure that the object is synced wrt. the related color clear value 7299 * GPU write on it. 7300 */ 7301 ret = intel_bo_read_from_page(intel_fb_bo(fb), 7302 fb->offsets[cc_plane] + 16, 7303 &plane_state->ccval, 7304 sizeof(plane_state->ccval)); 7305 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7306 drm_WARN_ON(display->drm, ret); 7307 } 7308 } 7309 7310 static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, 7311 struct intel_crtc *crtc) 7312 { 7313 struct intel_display *display = to_intel_display(state); 7314 struct intel_crtc_state *new_crtc_state = 7315 intel_atomic_get_new_crtc_state(state, crtc); 7316 7317 if (!new_crtc_state->hw.active) 7318 return; 7319 7320 if (state->base.legacy_cursor_update) 7321 return; 7322 7323 /* FIXME deal with everything */ 7324 new_crtc_state->use_flipq = 7325 intel_flipq_supported(display) && 7326 !new_crtc_state->do_async_flip && 7327 !new_crtc_state->vrr.enable && 7328 !new_crtc_state->has_psr && 7329 !intel_crtc_needs_modeset(new_crtc_state) && 7330 !intel_crtc_needs_fastset(new_crtc_state) && 7331 !intel_crtc_needs_color_update(new_crtc_state); 7332 7333 new_crtc_state->use_dsb = 7334 !new_crtc_state->use_flipq && 7335 !new_crtc_state->do_async_flip && 7336 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && 7337 !intel_crtc_needs_modeset(new_crtc_state) && 7338 !intel_crtc_needs_fastset(new_crtc_state); 7339 7340 intel_color_prepare_commit(state, crtc); 7341 } 7342 7343 static void intel_atomic_dsb_finish(struct intel_atomic_state *state, 7344 struct intel_crtc *crtc) 7345 { 7346 struct intel_display *display = to_intel_display(state); 7347 struct intel_crtc_state *new_crtc_state = 7348 intel_atomic_get_new_crtc_state(state, crtc); 7349 unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024; 7350 7351 if (!new_crtc_state->use_flipq && 7352 !new_crtc_state->use_dsb && 7353 !new_crtc_state->dsb_color) 7354 return; 7355 7356 /* 7357 * Rough estimate: 7358 * ~64 registers per each plane * 8 planes = 512 7359 * Double that for pipe stuff and other overhead. 7360 * ~4913 registers for 3DLUT 7361 * ~200 color registers * 3 HDR planes 7362 */ 7363 new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 7364 new_crtc_state->use_dsb || 7365 new_crtc_state->use_flipq ? size : 16); 7366 if (!new_crtc_state->dsb_commit) { 7367 new_crtc_state->use_flipq = false; 7368 new_crtc_state->use_dsb = false; 7369 intel_color_cleanup_commit(new_crtc_state); 7370 return; 7371 } 7372 7373 if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) { 7374 /* Wa_18034343758 */ 7375 if (new_crtc_state->use_flipq) 7376 intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); 7377 7378 if (new_crtc_state->vrr.dc_balance.enable) { 7379 /* 7380 * Pause the DMC DC balancing for the remainder of 7381 * the commit so that vmin/vmax won't change after 7382 * we've baked them into the DSB vblank evasion 7383 * commands. 7384 * 7385 * FIXME maybe need a small delay here to make sure 7386 * DMC has finished updating the values? Or we need 7387 * a better DMC<->driver protocol that gives is real 7388 * guarantees about that... 7389 */ 7390 intel_pipedmc_dcb_disable(NULL, crtc); 7391 } 7392 7393 if (intel_crtc_needs_color_update(new_crtc_state)) 7394 intel_color_commit_noarm(new_crtc_state->dsb_commit, 7395 new_crtc_state); 7396 intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, 7397 state, crtc); 7398 7399 /* 7400 * Ensure we have "Frame Change" event when PSR state is 7401 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank 7402 * evasion hangs as PIPEDSL is reading as 0. 7403 */ 7404 intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, 7405 state, crtc); 7406 7407 if (new_crtc_state->use_dsb) 7408 intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); 7409 7410 if (intel_crtc_needs_color_update(new_crtc_state)) 7411 intel_color_commit_arm(new_crtc_state->dsb_commit, 7412 new_crtc_state); 7413 bdw_set_pipe_misc(new_crtc_state->dsb_commit, 7414 new_crtc_state); 7415 intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, 7416 new_crtc_state); 7417 intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, 7418 state, crtc); 7419 7420 if (DISPLAY_VER(display) >= 9) 7421 skl_detach_scalers(new_crtc_state->dsb_commit, 7422 new_crtc_state); 7423 7424 /* Wa_18034343758 */ 7425 if (new_crtc_state->use_flipq) 7426 intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc); 7427 } 7428 7429 if (intel_color_uses_chained_dsb(new_crtc_state)) 7430 intel_dsb_chain(state, new_crtc_state->dsb_commit, 7431 new_crtc_state->dsb_color, true); 7432 else if (intel_color_uses_gosub_dsb(new_crtc_state)) 7433 intel_dsb_gosub(new_crtc_state->dsb_commit, 7434 new_crtc_state->dsb_color); 7435 7436 if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { 7437 /* 7438 * Dsb wait vblank may or may not skip. Let's remove it for PSR 7439 * trans push case to ensure we are not waiting two vblanks 7440 */ 7441 if (!intel_psr_use_trans_push(new_crtc_state)) 7442 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); 7443 7444 intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); 7445 7446 /* 7447 * Wait for idle is needed for corner case where PSR HW 7448 * is transitioning into DEEP_SLEEP/SRDENT_OFF when 7449 * new Frame Change event comes in. It is ok to do it 7450 * here for both Frame Change mechanism (trans push 7451 * and register write). 7452 */ 7453 intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit, 7454 new_crtc_state); 7455 7456 /* 7457 * In case PSR uses trans push as a "frame change" event and 7458 * VRR is not in use we need to wait vblank. Otherwise we may 7459 * miss selective updates. DSB skips all waits while PSR is 7460 * active. Check push send is skipped as well because trans push 7461 * send bit is not reset by the HW if VRR is not 7462 * enabled -> we may start configuring new selective 7463 * update while previous is not complete. 7464 */ 7465 if (intel_psr_use_trans_push(new_crtc_state)) 7466 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); 7467 7468 intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); 7469 intel_vrr_check_push_sent(new_crtc_state->dsb_commit, 7470 new_crtc_state); 7471 7472 if (new_crtc_state->vrr.dc_balance.enable) 7473 intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); 7474 7475 intel_dsb_interrupt(new_crtc_state->dsb_commit); 7476 } 7477 7478 intel_dsb_finish(new_crtc_state->dsb_commit); 7479 } 7480 7481 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7482 { 7483 struct intel_display *display = to_intel_display(state); 7484 struct intel_uncore *uncore = to_intel_uncore(display->drm); 7485 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7486 struct intel_crtc *crtc; 7487 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7488 struct ref_tracker *wakeref = NULL; 7489 int power_async_delay; 7490 7491 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7492 intel_atomic_dsb_prepare(state, crtc); 7493 7494 intel_atomic_commit_fence_wait(state); 7495 7496 intel_td_flush(display); 7497 7498 intel_atomic_prepare_plane_clear_colors(state); 7499 7500 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7501 intel_fbc_prepare_dirty_rect(state, crtc); 7502 7503 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7504 intel_atomic_dsb_finish(state, crtc); 7505 7506 drm_atomic_helper_wait_for_dependencies(&state->base); 7507 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7508 intel_atomic_global_state_wait_for_dependencies(state); 7509 7510 /* 7511 * During full modesets we write a lot of registers, wait 7512 * for PLLs, etc. Doing that while DC states are enabled 7513 * is not a good idea. 7514 * 7515 * During fastsets and other updates we also need to 7516 * disable DC states due to the following scenario: 7517 * 1. DC5 exit and PSR exit happen 7518 * 2. Some or all _noarm() registers are written 7519 * 3. Due to some long delay PSR is re-entered 7520 * 4. DC5 entry -> DMC saves the already written new 7521 * _noarm() registers and the old not yet written 7522 * _arm() registers 7523 * 5. DC5 exit -> DMC restores a mixture of old and 7524 * new register values and arms the update 7525 * 6. PSR exit -> hardware latches a mixture of old and 7526 * new register values -> corrupted frame, or worse 7527 * 7. New _arm() registers are finally written 7528 * 8. Hardware finally latches a complete set of new 7529 * register values, and subsequent frames will be OK again 7530 * 7531 * Also note that due to the pipe CSC hardware issues on 7532 * SKL/GLK DC states must remain off until the pipe CSC 7533 * state readout has happened. Otherwise we risk corrupting 7534 * the CSC latched register values with the readout (see 7535 * skl_read_csc() and skl_color_commit_noarm()). 7536 */ 7537 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); 7538 7539 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7540 if (intel_crtc_needs_modeset(new_crtc_state) || 7541 intel_crtc_needs_fastset(new_crtc_state)) 7542 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7543 } 7544 7545 intel_commit_modeset_disables(state); 7546 7547 intel_dp_tunnel_atomic_alloc_bw(state); 7548 7549 /* FIXME: Eventually get rid of our crtc->config pointer */ 7550 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7551 crtc->config = new_crtc_state; 7552 7553 /* 7554 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7555 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7556 * index, cdclk/ddiclk frequencies are supposed to be configured before 7557 * the cdclk config is set. 7558 */ 7559 intel_pmdemand_pre_plane_update(state); 7560 7561 if (state->modeset) 7562 drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base); 7563 7564 intel_set_cdclk_pre_plane_update(state); 7565 7566 if (state->modeset) 7567 intel_modeset_verify_disabled(state); 7568 7569 intel_sagv_pre_plane_update(state); 7570 7571 /* Complete the events for pipes that have now been disabled */ 7572 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7573 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7574 7575 /* Complete events for now disable pipes here. */ 7576 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7577 spin_lock_irq(&display->drm->event_lock); 7578 drm_crtc_send_vblank_event(&crtc->base, 7579 new_crtc_state->uapi.event); 7580 spin_unlock_irq(&display->drm->event_lock); 7581 7582 new_crtc_state->uapi.event = NULL; 7583 } 7584 } 7585 7586 intel_encoders_update_prepare(state); 7587 7588 intel_dbuf_pre_plane_update(state); 7589 7590 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7591 if (new_crtc_state->do_async_flip) 7592 intel_crtc_enable_flip_done(state, crtc); 7593 } 7594 7595 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7596 display->modeset.funcs->commit_modeset_enables(state); 7597 7598 intel_display_power_dc3co_compute(state); 7599 7600 /* FIXME probably need to sequence this properly */ 7601 intel_program_dpkgc_latency(state); 7602 7603 if (intel_display_power_dc3co_allowed(display)) 7604 intel_cmtg_program(state); 7605 7606 intel_wait_for_vblank_workers(state); 7607 7608 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7609 * already, but still need the state for the delayed optimization. To 7610 * fix this: 7611 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7612 * - schedule that vblank worker _before_ calling hw_done 7613 * - at the start of commit_tail, cancel it _synchrously 7614 * - switch over to the vblank wait helper in the core after that since 7615 * we don't need out special handling any more. 7616 */ 7617 drm_atomic_helper_wait_for_flip_done(display->drm, &state->base); 7618 7619 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) { 7620 if (new_crtc_state->do_async_flip) 7621 intel_crtc_disable_flip_done(state, crtc); 7622 7623 intel_atomic_dsb_wait_commit(new_crtc_state); 7624 7625 if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb) 7626 intel_vrr_check_push_sent(NULL, new_crtc_state); 7627 7628 if (new_crtc_state->use_flipq) 7629 intel_flipq_disable(new_crtc_state); 7630 } 7631 7632 /* 7633 * Now that the vblank has passed, we can go ahead and program the 7634 * optimal watermarks on platforms that need two-step watermark 7635 * programming. 7636 * 7637 * TODO: Move this (and other cleanup) to an async worker eventually. 7638 */ 7639 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7640 /* 7641 * Gen2 reports pipe underruns whenever all planes are disabled. 7642 * So re-enable underrun reporting after some planes get enabled. 7643 * 7644 * We do this before .optimize_watermarks() so that we have a 7645 * chance of catching underruns with the intermediate watermarks 7646 * vs. the new plane configuration. 7647 */ 7648 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7649 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 7650 7651 intel_optimize_watermarks(state, crtc); 7652 } 7653 7654 intel_dbuf_post_plane_update(state); 7655 7656 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 7657 intel_post_plane_update(state, crtc); 7658 7659 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7660 7661 intel_modeset_verify_crtc(state, crtc); 7662 7663 intel_post_plane_update_after_readout(state, crtc); 7664 7665 /* 7666 * DSB cleanup is done in cleanup_work aligning with framebuffer 7667 * cleanup. So copy and reset the dsb structure to sync with 7668 * commit_done and later do dsb cleanup in cleanup_work. 7669 * 7670 * FIXME get rid of this funny new->old swapping 7671 */ 7672 old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color); 7673 old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); 7674 } 7675 7676 /* Underruns don't always raise interrupts, so check manually */ 7677 intel_check_cpu_fifo_underruns(display); 7678 intel_check_pch_fifo_underruns(display); 7679 7680 if (state->modeset) 7681 intel_verify_planes(state); 7682 7683 intel_sagv_post_plane_update(state); 7684 intel_set_cdclk_post_plane_update(state); 7685 intel_pmdemand_post_plane_update(state); 7686 7687 drm_atomic_helper_commit_hw_done(&state->base); 7688 intel_atomic_global_state_commit_done(state); 7689 7690 if (state->modeset) { 7691 /* As one of the primary mmio accessors, KMS has a high 7692 * likelihood of triggering bugs in unclaimed access. After we 7693 * finish modesetting, see if an error has been flagged, and if 7694 * so enable debugging for the next modeset - and hope we catch 7695 * the culprit. 7696 */ 7697 intel_uncore_arm_unclaimed_mmio_detection(uncore); 7698 } 7699 7700 power_async_delay = intel_display_power_select_target_dc_state(state); 7701 7702 intel_display_power_put_async_delay(display, 7703 POWER_DOMAIN_DC_OFF, wakeref, power_async_delay); 7704 7705 intel_display_rpm_put(display, state->wakeref); 7706 7707 /* 7708 * Defer the cleanup of the old state to a separate worker to not 7709 * impede the current task (userspace for blocking modesets) that 7710 * are executed inline. For out-of-line asynchronous modesets/flips, 7711 * deferring to a new worker seems overkill, but we would place a 7712 * schedule point (cond_resched()) here anyway to keep latencies 7713 * down. 7714 */ 7715 INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work); 7716 queue_work(display->wq.cleanup, &state->cleanup_work); 7717 } 7718 7719 static void intel_atomic_commit_work(struct work_struct *work) 7720 { 7721 struct intel_atomic_state *state = 7722 container_of(work, struct intel_atomic_state, base.commit_work); 7723 7724 intel_atomic_commit_tail(state); 7725 } 7726 7727 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7728 { 7729 struct intel_plane_state *old_plane_state, *new_plane_state; 7730 struct intel_plane *plane; 7731 int i; 7732 7733 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7734 new_plane_state, i) 7735 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7736 to_intel_frontbuffer(new_plane_state->hw.fb), 7737 plane->frontbuffer_bit); 7738 } 7739 7740 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock) 7741 { 7742 int ret; 7743 7744 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7745 if (ret) 7746 return ret; 7747 7748 ret = intel_atomic_global_state_setup_commit(state); 7749 if (ret) 7750 return ret; 7751 7752 return 0; 7753 } 7754 7755 static int intel_atomic_swap_state(struct intel_atomic_state *state) 7756 { 7757 int ret; 7758 7759 ret = drm_atomic_helper_swap_state(&state->base, true); 7760 if (ret) 7761 return ret; 7762 7763 intel_atomic_swap_global_state(state); 7764 7765 intel_dpll_swap_state(state); 7766 7767 intel_atomic_track_fbs(state); 7768 7769 return 0; 7770 } 7771 7772 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_commit *_state, 7773 bool nonblock) 7774 { 7775 struct intel_display *display = to_intel_display(dev); 7776 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7777 int ret = 0; 7778 7779 state->wakeref = intel_display_rpm_get(display); 7780 7781 /* 7782 * The intel_legacy_cursor_update() fast path takes care 7783 * of avoiding the vblank waits for simple cursor 7784 * movement and flips. For cursor on/off and size changes, 7785 * we want to perform the vblank waits so that watermark 7786 * updates happen during the correct frames. Gen9+ have 7787 * double buffered watermarks and so shouldn't need this. 7788 * 7789 * Unset state->legacy_cursor_update before the call to 7790 * drm_atomic_helper_setup_commit() because otherwise 7791 * drm_atomic_helper_wait_for_flip_done() is a noop and 7792 * we get FIFO underruns because we didn't wait 7793 * for vblank. 7794 * 7795 * FIXME doing watermarks and fb cleanup from a vblank worker 7796 * (assuming we had any) would solve these problems. 7797 */ 7798 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { 7799 struct intel_crtc_state *new_crtc_state; 7800 struct intel_crtc *crtc; 7801 7802 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) 7803 if (new_crtc_state->wm.need_postvbl_update || 7804 new_crtc_state->update_wm_post) 7805 state->base.legacy_cursor_update = false; 7806 } 7807 7808 ret = intel_atomic_prepare_commit(state); 7809 if (ret) { 7810 drm_dbg_atomic(display->drm, 7811 "Preparing state failed with %i\n", ret); 7812 intel_display_rpm_put(display, state->wakeref); 7813 return ret; 7814 } 7815 7816 ret = intel_atomic_setup_commit(state, nonblock); 7817 if (!ret) 7818 ret = intel_atomic_swap_state(state); 7819 7820 if (ret) { 7821 drm_atomic_helper_unprepare_planes(dev, &state->base); 7822 intel_display_rpm_put(display, state->wakeref); 7823 return ret; 7824 } 7825 7826 drm_atomic_commit_get(&state->base); 7827 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7828 7829 if (nonblock && state->modeset) { 7830 queue_work(display->wq.modeset, &state->base.commit_work); 7831 } else if (nonblock) { 7832 queue_work(display->wq.flip, &state->base.commit_work); 7833 } else { 7834 if (state->modeset) 7835 flush_workqueue(display->wq.modeset); 7836 intel_atomic_commit_tail(state); 7837 } 7838 7839 return 0; 7840 } 7841 7842 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7843 { 7844 struct intel_display *display = to_intel_display(encoder); 7845 struct intel_encoder *source_encoder; 7846 u32 possible_clones = 0; 7847 7848 for_each_intel_encoder(display->drm, source_encoder) { 7849 if (encoders_cloneable(encoder, source_encoder)) 7850 possible_clones |= drm_encoder_mask(&source_encoder->base); 7851 } 7852 7853 return possible_clones; 7854 } 7855 7856 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7857 { 7858 struct intel_display *display = to_intel_display(encoder); 7859 struct intel_crtc *crtc; 7860 u32 possible_crtcs = 0; 7861 7862 for_each_intel_crtc_in_pipe_mask(display, crtc, encoder->pipe_mask) 7863 possible_crtcs |= drm_crtc_mask(&crtc->base); 7864 7865 return possible_crtcs; 7866 } 7867 7868 static bool ilk_has_edp_a(struct intel_display *display) 7869 { 7870 if (!display->platform.mobile) 7871 return false; 7872 7873 if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0) 7874 return false; 7875 7876 if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7877 return false; 7878 7879 return true; 7880 } 7881 7882 static bool intel_ddi_crt_present(struct intel_display *display) 7883 { 7884 if (DISPLAY_VER(display) >= 9) 7885 return false; 7886 7887 if (display->platform.haswell_ult || display->platform.broadwell_ult) 7888 return false; 7889 7890 if (HAS_PCH_LPT_H(display) && 7891 intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7892 return false; 7893 7894 /* DDI E can't be used if DDI A requires 4 lanes */ 7895 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7896 return false; 7897 7898 if (!display->vbt.int_crt_support) 7899 return false; 7900 7901 return true; 7902 } 7903 7904 bool assert_port_valid(struct intel_display *display, enum port port) 7905 { 7906 return !drm_WARN(display->drm, 7907 !(port >= 0 && DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)), 7908 "Platform does not support port %c\n", port_name(port)); 7909 } 7910 7911 void intel_setup_outputs(struct intel_display *display) 7912 { 7913 struct intel_encoder *encoder; 7914 bool dpd_is_edp = false; 7915 7916 intel_pps_unlock_regs_wa(display); 7917 7918 if (!HAS_DISPLAY(display)) 7919 return; 7920 7921 if (HAS_DDI(display)) { 7922 if (intel_ddi_crt_present(display)) 7923 intel_crt_init(display); 7924 7925 intel_bios_for_each_encoder(display, intel_ddi_init); 7926 7927 if (display->platform.geminilake || display->platform.broxton) 7928 vlv_dsi_init(display); 7929 } else if (HAS_PCH_SPLIT(display)) { 7930 int found; 7931 7932 /* 7933 * intel_edp_init_connector() depends on this completing first, 7934 * to prevent the registration of both eDP and LVDS and the 7935 * incorrect sharing of the PPS. 7936 */ 7937 intel_lvds_init(display); 7938 intel_crt_init(display); 7939 7940 dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); 7941 7942 if (ilk_has_edp_a(display)) 7943 g4x_dp_init(display, DP_A, PORT_A); 7944 7945 if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) { 7946 /* PCH SDVOB multiplex with HDMIB */ 7947 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); 7948 if (!found) 7949 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); 7950 if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED)) 7951 g4x_dp_init(display, PCH_DP_B, PORT_B); 7952 } 7953 7954 if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED) 7955 g4x_hdmi_init(display, PCH_HDMIC, PORT_C); 7956 7957 if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED) 7958 g4x_hdmi_init(display, PCH_HDMID, PORT_D); 7959 7960 if (intel_de_read(display, PCH_DP_C) & DP_DETECTED) 7961 g4x_dp_init(display, PCH_DP_C, PORT_C); 7962 7963 if (intel_de_read(display, PCH_DP_D) & DP_DETECTED) 7964 g4x_dp_init(display, PCH_DP_D, PORT_D); 7965 } else if (display->platform.valleyview || display->platform.cherryview) { 7966 bool has_edp, has_port; 7967 7968 if (display->platform.valleyview && display->vbt.int_crt_support) 7969 intel_crt_init(display); 7970 7971 /* 7972 * The DP_DETECTED bit is the latched state of the DDC 7973 * SDA pin at boot. However since eDP doesn't require DDC 7974 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7975 * eDP ports may have been muxed to an alternate function. 7976 * Thus we can't rely on the DP_DETECTED bit alone to detect 7977 * eDP ports. Consult the VBT as well as DP_DETECTED to 7978 * detect eDP ports. 7979 * 7980 * Sadly the straps seem to be missing sometimes even for HDMI 7981 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7982 * and VBT for the presence of the port. Additionally we can't 7983 * trust the port type the VBT declares as we've seen at least 7984 * HDMI ports that the VBT claim are DP or eDP. 7985 */ 7986 has_edp = intel_dp_is_port_edp(display, PORT_B); 7987 has_port = intel_bios_is_port_present(display, PORT_B); 7988 if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port) 7989 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); 7990 if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7991 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); 7992 7993 has_edp = intel_dp_is_port_edp(display, PORT_C); 7994 has_port = intel_bios_is_port_present(display, PORT_C); 7995 if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port) 7996 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); 7997 if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7998 g4x_hdmi_init(display, VLV_HDMIC, PORT_C); 7999 8000 if (display->platform.cherryview) { 8001 /* 8002 * eDP not supported on port D, 8003 * so no need to worry about it 8004 */ 8005 has_port = intel_bios_is_port_present(display, PORT_D); 8006 if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port) 8007 g4x_dp_init(display, CHV_DP_D, PORT_D); 8008 if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port) 8009 g4x_hdmi_init(display, CHV_HDMID, PORT_D); 8010 } 8011 8012 vlv_dsi_init(display); 8013 } else if (display->platform.pineview) { 8014 intel_lvds_init(display); 8015 intel_crt_init(display); 8016 } else if (IS_DISPLAY_VER(display, 3, 4)) { 8017 bool found = false; 8018 8019 if (display->platform.mobile) 8020 intel_lvds_init(display); 8021 8022 intel_crt_init(display); 8023 8024 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 8025 drm_dbg_kms(display->drm, "probing SDVOB\n"); 8026 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); 8027 if (!found && display->platform.g4x) { 8028 drm_dbg_kms(display->drm, 8029 "probing HDMI on SDVOB\n"); 8030 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); 8031 } 8032 8033 if (!found && display->platform.g4x) 8034 g4x_dp_init(display, DP_B, PORT_B); 8035 } 8036 8037 /* Before G4X SDVOC doesn't have its own detect register */ 8038 8039 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 8040 drm_dbg_kms(display->drm, "probing SDVOC\n"); 8041 found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); 8042 } 8043 8044 if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) { 8045 8046 if (display->platform.g4x) { 8047 drm_dbg_kms(display->drm, 8048 "probing HDMI on SDVOC\n"); 8049 g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); 8050 } 8051 if (display->platform.g4x) 8052 g4x_dp_init(display, DP_C, PORT_C); 8053 } 8054 8055 if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED)) 8056 g4x_dp_init(display, DP_D, PORT_D); 8057 8058 if (SUPPORTS_TV(display)) 8059 intel_tv_init(display); 8060 } else if (DISPLAY_VER(display) == 2) { 8061 if (display->platform.i85x) 8062 intel_lvds_init(display); 8063 8064 intel_crt_init(display); 8065 intel_dvo_init(display); 8066 } 8067 8068 for_each_intel_encoder(display->drm, encoder) { 8069 encoder->base.possible_crtcs = 8070 intel_encoder_possible_crtcs(encoder); 8071 encoder->base.possible_clones = 8072 intel_encoder_possible_clones(encoder); 8073 } 8074 8075 intel_init_pch_refclk(display); 8076 8077 drm_helper_move_panel_connectors_to_head(display->drm); 8078 } 8079 8080 int intel_max_uncompressed_dotclock(struct intel_display *display) 8081 { 8082 int max_dotclock = display->cdclk.max_dotclk_freq; 8083 int limit = max_dotclock; 8084 8085 if (DISPLAY_VERx100(display) == 3002) 8086 limit = 937500; 8087 else if (DISPLAY_VER(display) >= 30) 8088 limit = 1350000; 8089 /* 8090 * Note: For other platforms though there are limits given 8091 * in the Bspec, however the limit is intentionally not 8092 * enforced to avoid regressions, unless real issues are 8093 * observed. 8094 */ 8095 8096 return min(max_dotclock, limit); 8097 } 8098 8099 static int max_dotclock(struct intel_display *display) 8100 { 8101 int max_dotclock = display->cdclk.max_dotclk_freq; 8102 8103 if (HAS_ULTRAJOINER(display)) 8104 max_dotclock *= 4; 8105 else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display)) 8106 max_dotclock *= 2; 8107 8108 return max_dotclock; 8109 } 8110 8111 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 8112 const struct drm_display_mode *mode) 8113 { 8114 struct intel_display *display = to_intel_display(dev); 8115 int hdisplay_max, htotal_max; 8116 int vdisplay_max, vtotal_max; 8117 8118 /* 8119 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8120 * of DBLSCAN modes to the output's mode list when they detect 8121 * the scaling mode property on the connector. And they don't 8122 * ask the kernel to validate those modes in any way until 8123 * modeset time at which point the client gets a protocol error. 8124 * So in order to not upset those clients we silently ignore the 8125 * DBLSCAN flag on such connectors. For other connectors we will 8126 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8127 * And we always reject DBLSCAN modes in connector->mode_valid() 8128 * as we never want such modes on the connector's mode list. 8129 */ 8130 8131 if (mode->vscan > 1) 8132 return MODE_NO_VSCAN; 8133 8134 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8135 return MODE_H_ILLEGAL; 8136 8137 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8138 DRM_MODE_FLAG_NCSYNC | 8139 DRM_MODE_FLAG_PCSYNC)) 8140 return MODE_HSYNC; 8141 8142 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8143 DRM_MODE_FLAG_PIXMUX | 8144 DRM_MODE_FLAG_CLKDIV2)) 8145 return MODE_BAD; 8146 8147 /* 8148 * Reject clearly excessive dotclocks early to 8149 * avoid having to worry about huge integers later. 8150 */ 8151 if (mode->clock > max_dotclock(display)) 8152 return MODE_CLOCK_HIGH; 8153 8154 /* Transcoder timing limits */ 8155 if (DISPLAY_VER(display) >= 11) { 8156 hdisplay_max = 16384; 8157 vdisplay_max = 8192; 8158 htotal_max = 16384; 8159 vtotal_max = 8192; 8160 } else if (DISPLAY_VER(display) >= 9 || 8161 display->platform.broadwell || display->platform.haswell) { 8162 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8163 vdisplay_max = 4096; 8164 htotal_max = 8192; 8165 vtotal_max = 8192; 8166 } else if (DISPLAY_VER(display) >= 3) { 8167 hdisplay_max = 4096; 8168 vdisplay_max = 4096; 8169 htotal_max = 8192; 8170 vtotal_max = 8192; 8171 } else { 8172 hdisplay_max = 2048; 8173 vdisplay_max = 2048; 8174 htotal_max = 4096; 8175 vtotal_max = 4096; 8176 } 8177 8178 if (mode->hdisplay > hdisplay_max || 8179 mode->hsync_start > htotal_max || 8180 mode->hsync_end > htotal_max || 8181 mode->htotal > htotal_max) 8182 return MODE_H_ILLEGAL; 8183 8184 if (mode->vdisplay > vdisplay_max || 8185 mode->vsync_start > vtotal_max || 8186 mode->vsync_end > vtotal_max || 8187 mode->vtotal > vtotal_max) 8188 return MODE_V_ILLEGAL; 8189 8190 /* 8191 * WM_LINETIME only goes up to (almost) 64 usec, and also 8192 * knowing that the linetime is always bounded will ease the 8193 * mind during various calculations. 8194 */ 8195 if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64) 8196 return MODE_H_ILLEGAL; 8197 8198 return MODE_OK; 8199 } 8200 8201 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display, 8202 const struct drm_display_mode *mode) 8203 { 8204 /* 8205 * Additional transcoder timing limits, 8206 * excluding BXT/GLK DSI transcoders. 8207 */ 8208 if (DISPLAY_VER(display) >= 5) { 8209 if (mode->hdisplay < 64 || 8210 mode->htotal - mode->hdisplay < 32) 8211 return MODE_H_ILLEGAL; 8212 8213 if (mode->vtotal - mode->vdisplay < 5) 8214 return MODE_V_ILLEGAL; 8215 } else { 8216 if (mode->htotal - mode->hdisplay < 32) 8217 return MODE_H_ILLEGAL; 8218 8219 if (mode->vtotal - mode->vdisplay < 3) 8220 return MODE_V_ILLEGAL; 8221 } 8222 8223 /* 8224 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8225 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8226 */ 8227 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && 8228 mode->hsync_start == mode->hdisplay) 8229 return MODE_H_ILLEGAL; 8230 8231 return MODE_OK; 8232 } 8233 8234 enum drm_mode_status 8235 intel_mode_valid_max_plane_size(struct intel_display *display, 8236 const struct drm_display_mode *mode, 8237 int num_joined_pipes) 8238 { 8239 int plane_width_max, plane_height_max; 8240 8241 /* 8242 * intel_mode_valid() should be 8243 * sufficient on older platforms. 8244 */ 8245 if (DISPLAY_VER(display) < 9) 8246 return MODE_OK; 8247 8248 /* 8249 * Most people will probably want a fullscreen 8250 * plane so let's not advertize modes that are 8251 * too big for that. 8252 */ 8253 if (DISPLAY_VER(display) >= 30) { 8254 plane_width_max = 6144 * num_joined_pipes; 8255 plane_height_max = 4800; 8256 } else if (DISPLAY_VER(display) >= 11) { 8257 plane_width_max = 5120 * num_joined_pipes; 8258 plane_height_max = 4320; 8259 } else { 8260 plane_width_max = 5120; 8261 plane_height_max = 4096; 8262 } 8263 8264 if (mode->hdisplay > plane_width_max) 8265 return MODE_H_ILLEGAL; 8266 8267 if (mode->vdisplay > plane_height_max) 8268 return MODE_V_ILLEGAL; 8269 8270 return MODE_OK; 8271 } 8272 8273 static const struct intel_modeset_funcs skl_display_funcs = { 8274 .get_pipe_config = hsw_get_pipe_config, 8275 .crtc_enable = hsw_crtc_enable, 8276 .crtc_disable = hsw_crtc_disable, 8277 .commit_modeset_enables = skl_commit_modeset_enables, 8278 .get_initial_plane_config = skl_get_initial_plane_config, 8279 .fixup_initial_plane_config = skl_fixup_initial_plane_config, 8280 }; 8281 8282 static const struct intel_modeset_funcs ddi_display_funcs = { 8283 .get_pipe_config = hsw_get_pipe_config, 8284 .crtc_enable = hsw_crtc_enable, 8285 .crtc_disable = hsw_crtc_disable, 8286 .commit_modeset_enables = intel_commit_modeset_enables, 8287 .get_initial_plane_config = i9xx_get_initial_plane_config, 8288 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8289 }; 8290 8291 static const struct intel_modeset_funcs pch_split_display_funcs = { 8292 .get_pipe_config = ilk_get_pipe_config, 8293 .crtc_enable = ilk_crtc_enable, 8294 .crtc_disable = ilk_crtc_disable, 8295 .commit_modeset_enables = intel_commit_modeset_enables, 8296 .get_initial_plane_config = i9xx_get_initial_plane_config, 8297 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8298 }; 8299 8300 static const struct intel_modeset_funcs vlv_display_funcs = { 8301 .get_pipe_config = i9xx_get_pipe_config, 8302 .crtc_enable = valleyview_crtc_enable, 8303 .crtc_disable = i9xx_crtc_disable, 8304 .commit_modeset_enables = intel_commit_modeset_enables, 8305 .get_initial_plane_config = i9xx_get_initial_plane_config, 8306 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8307 }; 8308 8309 static const struct intel_modeset_funcs i9xx_display_funcs = { 8310 .get_pipe_config = i9xx_get_pipe_config, 8311 .crtc_enable = i9xx_crtc_enable, 8312 .crtc_disable = i9xx_crtc_disable, 8313 .commit_modeset_enables = intel_commit_modeset_enables, 8314 .get_initial_plane_config = i9xx_get_initial_plane_config, 8315 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8316 }; 8317 8318 /** 8319 * intel_init_display_hooks - initialize the display modesetting hooks 8320 * @display: display device private 8321 */ 8322 void intel_init_display_hooks(struct intel_display *display) 8323 { 8324 if (DISPLAY_VER(display) >= 9) { 8325 display->modeset.funcs = &skl_display_funcs; 8326 } else if (HAS_DDI(display)) { 8327 display->modeset.funcs = &ddi_display_funcs; 8328 } else if (HAS_PCH_SPLIT(display)) { 8329 display->modeset.funcs = &pch_split_display_funcs; 8330 } else if (display->platform.cherryview || 8331 display->platform.valleyview) { 8332 display->modeset.funcs = &vlv_display_funcs; 8333 } else { 8334 display->modeset.funcs = &i9xx_display_funcs; 8335 } 8336 } 8337 8338 int intel_initial_commit(struct intel_display *display) 8339 { 8340 struct drm_atomic_commit *state = NULL; 8341 struct drm_modeset_acquire_ctx ctx; 8342 struct intel_crtc *crtc; 8343 int ret = 0; 8344 8345 state = drm_atomic_commit_alloc(display->drm); 8346 if (!state) 8347 return -ENOMEM; 8348 8349 drm_modeset_acquire_init(&ctx, 0); 8350 8351 state->acquire_ctx = &ctx; 8352 to_intel_atomic_state(state)->internal = true; 8353 8354 retry: 8355 for_each_intel_crtc(display, crtc) { 8356 struct intel_crtc_state *crtc_state = 8357 intel_atomic_get_crtc_state(state, crtc); 8358 8359 if (IS_ERR(crtc_state)) { 8360 ret = PTR_ERR(crtc_state); 8361 goto out; 8362 } 8363 8364 if (!crtc_state->hw.active) 8365 crtc_state->inherited = false; 8366 8367 if (crtc_state->hw.active) { 8368 struct intel_encoder *encoder; 8369 8370 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8371 if (ret) 8372 goto out; 8373 8374 /* 8375 * FIXME hack to force a LUT update to avoid the 8376 * plane update forcing the pipe gamma on without 8377 * having a proper LUT loaded. Remove once we 8378 * have readout for pipe gamma enable. 8379 */ 8380 crtc_state->uapi.color_mgmt_changed = true; 8381 8382 for_each_intel_encoder_mask(display->drm, encoder, 8383 crtc_state->uapi.encoder_mask) { 8384 if (encoder->initial_fastset_check && 8385 !encoder->initial_fastset_check(encoder, crtc_state)) { 8386 ret = drm_atomic_add_affected_connectors(state, 8387 &crtc->base); 8388 if (ret) 8389 goto out; 8390 } 8391 } 8392 } 8393 } 8394 8395 ret = drm_atomic_commit(state); 8396 8397 out: 8398 if (ret == -EDEADLK) { 8399 drm_atomic_commit_clear(state); 8400 drm_modeset_backoff(&ctx); 8401 goto retry; 8402 } 8403 8404 drm_atomic_commit_put(state); 8405 8406 drm_modeset_drop_locks(&ctx); 8407 drm_modeset_acquire_fini(&ctx); 8408 8409 return ret; 8410 } 8411 8412 void i830_enable_pipe(struct intel_display *display, enum pipe pipe) 8413 { 8414 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8415 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8416 /* 640x480@60Hz, ~25175 kHz */ 8417 struct dpll clock = { 8418 .m1 = 18, 8419 .m2 = 7, 8420 .p1 = 13, 8421 .p2 = 4, 8422 .n = 2, 8423 }; 8424 u32 dpll, fp; 8425 int i; 8426 8427 drm_WARN_ON(display->drm, 8428 i9xx_calc_dpll_params(48000, &clock) != 25154); 8429 8430 drm_dbg_kms(display->drm, 8431 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8432 pipe_name(pipe), clock.vco, clock.dot); 8433 8434 fp = i9xx_dpll_compute_fp(&clock); 8435 dpll = DPLL_DVO_2X_MODE | 8436 DPLL_VGA_MODE_DIS | 8437 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8438 PLL_P2_DIVIDE_BY_4 | 8439 PLL_REF_INPUT_DREFCLK | 8440 DPLL_VCO_ENABLE; 8441 8442 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), 8443 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8444 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), 8445 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8446 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), 8447 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8448 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 8449 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8450 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 8451 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8452 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), 8453 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8454 intel_de_write(display, PIPESRC(display, pipe), 8455 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8456 8457 intel_de_write(display, FP0(pipe), fp); 8458 intel_de_write(display, FP1(pipe), fp); 8459 8460 /* 8461 * Apparently we need to have VGA mode enabled prior to changing 8462 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8463 * dividers, even though the register value does change. 8464 */ 8465 intel_de_write(display, DPLL(display, pipe), 8466 dpll & ~DPLL_VGA_MODE_DIS); 8467 intel_de_write(display, DPLL(display, pipe), dpll); 8468 8469 /* Wait for the clocks to stabilize. */ 8470 intel_de_posting_read(display, DPLL(display, pipe)); 8471 udelay(150); 8472 8473 /* The pixel multiplier can only be updated once the 8474 * DPLL is enabled and the clocks are stable. 8475 * 8476 * So write it again. 8477 */ 8478 intel_de_write(display, DPLL(display, pipe), dpll); 8479 8480 /* We do this three times for luck */ 8481 for (i = 0; i < 3 ; i++) { 8482 intel_de_write(display, DPLL(display, pipe), dpll); 8483 intel_de_posting_read(display, DPLL(display, pipe)); 8484 udelay(150); /* wait for warmup */ 8485 } 8486 8487 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); 8488 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8489 8490 intel_wait_for_pipe_scanline_moving(crtc); 8491 } 8492 8493 void i830_disable_pipe(struct intel_display *display, enum pipe pipe) 8494 { 8495 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8496 8497 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", 8498 pipe_name(pipe)); 8499 8500 drm_WARN_ON(display->drm, 8501 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); 8502 drm_WARN_ON(display->drm, 8503 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); 8504 drm_WARN_ON(display->drm, 8505 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); 8506 drm_WARN_ON(display->drm, 8507 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); 8508 drm_WARN_ON(display->drm, 8509 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); 8510 8511 intel_de_write(display, TRANSCONF(display, pipe), 0); 8512 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8513 8514 intel_wait_for_pipe_scanline_stopped(crtc); 8515 8516 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); 8517 intel_de_posting_read(display, DPLL(display, pipe)); 8518 } 8519 8520 bool intel_scanout_needs_vtd_wa(struct intel_display *display) 8521 { 8522 return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display); 8523 } 8524