1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DE_H__ 7 #define __INTEL_DE_H__ 8 9 #include "i915_drv.h" 10 #include "i915_trace.h" 11 #include "intel_uncore.h" 12 13 static inline u32 14 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) 15 { 16 return intel_uncore_read(&i915->uncore, reg); 17 } 18 19 static inline u8 20 intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg) 21 { 22 return intel_uncore_read8(&i915->uncore, reg); 23 } 24 25 static inline u64 26 intel_de_read64_2x32(struct drm_i915_private *i915, 27 i915_reg_t lower_reg, i915_reg_t upper_reg) 28 { 29 return intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg); 30 } 31 32 static inline void 33 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) 34 { 35 intel_uncore_posting_read(&i915->uncore, reg); 36 } 37 38 static inline void 39 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) 40 { 41 intel_uncore_write(&i915->uncore, reg, val); 42 } 43 44 static inline u32 45 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) 46 { 47 return intel_uncore_rmw(&i915->uncore, reg, clear, set); 48 } 49 50 static inline int 51 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, 52 u32 mask, u32 value, unsigned int timeout) 53 { 54 return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); 55 } 56 57 static inline int 58 intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg, 59 u32 mask, u32 value, unsigned int timeout) 60 { 61 return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout); 62 } 63 64 static inline int 65 __intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, 66 u32 mask, u32 value, 67 unsigned int fast_timeout_us, 68 unsigned int slow_timeout_ms, u32 *out_value) 69 { 70 return __intel_wait_for_register(&i915->uncore, reg, mask, value, 71 fast_timeout_us, slow_timeout_ms, out_value); 72 } 73 74 static inline int 75 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, 76 u32 mask, unsigned int timeout) 77 { 78 return intel_de_wait_for_register(i915, reg, mask, mask, timeout); 79 } 80 81 static inline int 82 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, 83 u32 mask, unsigned int timeout) 84 { 85 return intel_de_wait_for_register(i915, reg, mask, 0, timeout); 86 } 87 88 /* 89 * Unlocked mmio-accessors, think carefully before using these. 90 * 91 * Certain architectures will die if the same cacheline is concurrently accessed 92 * by different clients (e.g. on Ivybridge). Access to registers should 93 * therefore generally be serialised, by either the dev_priv->uncore.lock or 94 * a more localised lock guarding all access to that bank of registers. 95 */ 96 static inline u32 97 intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg) 98 { 99 u32 val; 100 101 val = intel_uncore_read_fw(&i915->uncore, reg); 102 trace_i915_reg_rw(false, reg, val, sizeof(val), true); 103 104 return val; 105 } 106 107 static inline void 108 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) 109 { 110 trace_i915_reg_rw(true, reg, val, sizeof(val), true); 111 intel_uncore_write_fw(&i915->uncore, reg, val); 112 } 113 114 static inline u32 115 intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg) 116 { 117 return intel_uncore_read_notrace(&i915->uncore, reg); 118 } 119 120 static inline void 121 intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val) 122 { 123 intel_uncore_write_notrace(&i915->uncore, reg, val); 124 } 125 126 #endif /* __INTEL_DE_H__ */ 127