1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DE_H__ 7 #define __INTEL_DE_H__ 8 9 #include "i915_drv.h" 10 #include "i915_trace.h" 11 #include "intel_dsb.h" 12 #include "intel_uncore.h" 13 14 static inline struct intel_uncore *__to_uncore(struct intel_display *display) 15 { 16 return &to_i915(display->drm)->uncore; 17 } 18 19 static inline u32 20 __intel_de_read(struct intel_display *display, i915_reg_t reg) 21 { 22 u32 val; 23 24 intel_dmc_wl_get(display, reg); 25 26 val = intel_uncore_read(__to_uncore(display), reg); 27 28 intel_dmc_wl_put(display, reg); 29 30 return val; 31 } 32 #define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__) 33 34 static inline u8 35 __intel_de_read8(struct intel_display *display, i915_reg_t reg) 36 { 37 u8 val; 38 39 intel_dmc_wl_get(display, reg); 40 41 val = intel_uncore_read8(__to_uncore(display), reg); 42 43 intel_dmc_wl_put(display, reg); 44 45 return val; 46 } 47 #define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__) 48 49 static inline u64 50 __intel_de_read64_2x32(struct intel_display *display, 51 i915_reg_t lower_reg, i915_reg_t upper_reg) 52 { 53 u64 val; 54 55 intel_dmc_wl_get(display, lower_reg); 56 intel_dmc_wl_get(display, upper_reg); 57 58 val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg, 59 upper_reg); 60 61 intel_dmc_wl_put(display, upper_reg); 62 intel_dmc_wl_put(display, lower_reg); 63 64 return val; 65 } 66 #define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__) 67 68 static inline void 69 __intel_de_posting_read(struct intel_display *display, i915_reg_t reg) 70 { 71 intel_dmc_wl_get(display, reg); 72 73 intel_uncore_posting_read(__to_uncore(display), reg); 74 75 intel_dmc_wl_put(display, reg); 76 } 77 #define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__) 78 79 static inline void 80 __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) 81 { 82 intel_dmc_wl_get(display, reg); 83 84 intel_uncore_write(__to_uncore(display), reg, val); 85 86 intel_dmc_wl_put(display, reg); 87 } 88 #define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__) 89 90 static inline u32 91 ____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg, 92 u32 clear, u32 set) 93 { 94 return intel_uncore_rmw(__to_uncore(display), reg, clear, set); 95 } 96 #define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__) 97 98 static inline u32 99 __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, 100 u32 set) 101 { 102 u32 val; 103 104 intel_dmc_wl_get(display, reg); 105 106 val = __intel_de_rmw_nowl(display, reg, clear, set); 107 108 intel_dmc_wl_put(display, reg); 109 110 return val; 111 } 112 #define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__) 113 114 static inline int 115 ____intel_de_wait_for_register_nowl(struct intel_display *display, 116 i915_reg_t reg, 117 u32 mask, u32 value, unsigned int timeout) 118 { 119 return intel_wait_for_register(__to_uncore(display), reg, mask, 120 value, timeout); 121 } 122 #define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__) 123 124 static inline int 125 __intel_de_wait(struct intel_display *display, i915_reg_t reg, 126 u32 mask, u32 value, unsigned int timeout) 127 { 128 int ret; 129 130 intel_dmc_wl_get(display, reg); 131 132 ret = __intel_de_wait_for_register_nowl(display, reg, mask, value, 133 timeout); 134 135 intel_dmc_wl_put(display, reg); 136 137 return ret; 138 } 139 #define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__) 140 141 static inline int 142 __intel_de_wait_fw(struct intel_display *display, i915_reg_t reg, 143 u32 mask, u32 value, unsigned int timeout) 144 { 145 int ret; 146 147 intel_dmc_wl_get(display, reg); 148 149 ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask, 150 value, timeout); 151 152 intel_dmc_wl_put(display, reg); 153 154 return ret; 155 } 156 #define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__) 157 158 static inline int 159 __intel_de_wait_custom(struct intel_display *display, i915_reg_t reg, 160 u32 mask, u32 value, 161 unsigned int fast_timeout_us, 162 unsigned int slow_timeout_ms, u32 *out_value) 163 { 164 int ret; 165 166 intel_dmc_wl_get(display, reg); 167 168 ret = __intel_wait_for_register(__to_uncore(display), reg, mask, 169 value, 170 fast_timeout_us, slow_timeout_ms, out_value); 171 172 intel_dmc_wl_put(display, reg); 173 174 return ret; 175 } 176 #define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__) 177 178 static inline int 179 __intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, 180 u32 mask, unsigned int timeout) 181 { 182 return intel_de_wait(display, reg, mask, mask, timeout); 183 } 184 #define intel_de_wait_for_set(p,...) __intel_de_wait_for_set(__to_intel_display(p), __VA_ARGS__) 185 186 static inline int 187 __intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, 188 u32 mask, unsigned int timeout) 189 { 190 return intel_de_wait(display, reg, mask, 0, timeout); 191 } 192 #define intel_de_wait_for_clear(p,...) __intel_de_wait_for_clear(__to_intel_display(p), __VA_ARGS__) 193 194 /* 195 * Unlocked mmio-accessors, think carefully before using these. 196 * 197 * Certain architectures will die if the same cacheline is concurrently accessed 198 * by different clients (e.g. on Ivybridge). Access to registers should 199 * therefore generally be serialised, by either the dev_priv->uncore.lock or 200 * a more localised lock guarding all access to that bank of registers. 201 */ 202 static inline u32 203 __intel_de_read_fw(struct intel_display *display, i915_reg_t reg) 204 { 205 u32 val; 206 207 val = intel_uncore_read_fw(__to_uncore(display), reg); 208 trace_i915_reg_rw(false, reg, val, sizeof(val), true); 209 210 return val; 211 } 212 #define intel_de_read_fw(p,...) __intel_de_read_fw(__to_intel_display(p), __VA_ARGS__) 213 214 static inline void 215 __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) 216 { 217 trace_i915_reg_rw(true, reg, val, sizeof(val), true); 218 intel_uncore_write_fw(__to_uncore(display), reg, val); 219 } 220 #define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__) 221 222 static inline u32 223 __intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) 224 { 225 return intel_uncore_read_notrace(__to_uncore(display), reg); 226 } 227 #define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__) 228 229 static inline void 230 __intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, 231 u32 val) 232 { 233 intel_uncore_write_notrace(__to_uncore(display), reg, val); 234 } 235 #define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__) 236 237 static __always_inline void 238 intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb, 239 i915_reg_t reg, u32 val) 240 { 241 if (dsb) 242 intel_dsb_reg_write(dsb, reg, val); 243 else 244 intel_de_write_fw(display, reg, val); 245 } 246 247 #endif /* __INTEL_DE_H__ */ 248