1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DE_H__ 7 #define __INTEL_DE_H__ 8 9 #include "intel_display_core.h" 10 #include "intel_dmc_wl.h" 11 #include "intel_dsb.h" 12 #include "intel_uncore.h" 13 #include "intel_uncore_trace.h" 14 15 static inline struct intel_uncore *__to_uncore(struct intel_display *display) 16 { 17 return to_intel_uncore(display->drm); 18 } 19 20 u8 intel_de_read8(struct intel_display *display, i915_reg_t reg); 21 void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val); 22 23 static inline u32 24 intel_de_read(struct intel_display *display, i915_reg_t reg) 25 { 26 u32 val; 27 28 intel_dmc_wl_get(display, reg); 29 30 val = intel_uncore_read(__to_uncore(display), reg); 31 32 intel_dmc_wl_put(display, reg); 33 34 return val; 35 } 36 37 static inline u64 38 intel_de_read64_2x32(struct intel_display *display, 39 i915_reg_t lower_reg, i915_reg_t upper_reg) 40 { 41 u64 val; 42 43 intel_dmc_wl_get(display, lower_reg); 44 intel_dmc_wl_get(display, upper_reg); 45 46 val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg, 47 upper_reg); 48 49 intel_dmc_wl_put(display, upper_reg); 50 intel_dmc_wl_put(display, lower_reg); 51 52 return val; 53 } 54 55 static inline void 56 intel_de_posting_read(struct intel_display *display, i915_reg_t reg) 57 { 58 intel_dmc_wl_get(display, reg); 59 60 intel_uncore_posting_read(__to_uncore(display), reg); 61 62 intel_dmc_wl_put(display, reg); 63 } 64 65 static inline void 66 intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) 67 { 68 intel_dmc_wl_get(display, reg); 69 70 intel_uncore_write(__to_uncore(display), reg, val); 71 72 intel_dmc_wl_put(display, reg); 73 } 74 75 static inline u32 76 intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) 77 { 78 u32 val; 79 80 intel_dmc_wl_get(display, reg); 81 82 val = intel_uncore_rmw(__to_uncore(display), reg, clear, set); 83 84 intel_dmc_wl_put(display, reg); 85 86 return val; 87 } 88 89 int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, 90 u32 mask, u32 value, unsigned int timeout_us, 91 u32 *out_value); 92 int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, 93 u32 mask, u32 value, unsigned int timeout_ms, 94 u32 *out_value); 95 int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, 96 u32 mask, u32 value, unsigned int timeout_ms, 97 u32 *out_value); 98 int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, 99 u32 mask, u32 value, unsigned int timeout_us, 100 u32 *out_value); 101 int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg, 102 u32 mask, unsigned int timeout_us); 103 int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg, 104 u32 mask, unsigned int timeout_us); 105 int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg, 106 u32 mask, unsigned int timeout_ms); 107 int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, 108 u32 mask, unsigned int timeout_ms); 109 110 /* 111 * Unlocked mmio-accessors, think carefully before using these. 112 * 113 * Certain architectures will die if the same cacheline is concurrently accessed 114 * by different clients (e.g. on Ivybridge). Access to registers should 115 * therefore generally be serialised, by either the dev_priv->uncore.lock or 116 * a more localised lock guarding all access to that bank of registers. 117 */ 118 static inline u32 119 intel_de_read_fw(struct intel_display *display, i915_reg_t reg) 120 { 121 u32 val; 122 123 val = intel_uncore_read_fw(__to_uncore(display), reg); 124 trace_i915_reg_rw(false, reg, val, sizeof(val), true); 125 126 return val; 127 } 128 129 static inline void 130 intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) 131 { 132 trace_i915_reg_rw(true, reg, val, sizeof(val), true); 133 intel_uncore_write_fw(__to_uncore(display), reg, val); 134 } 135 136 static inline u32 137 intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) 138 { 139 u32 old, val; 140 141 old = intel_de_read_fw(display, reg); 142 val = (old & ~clear) | set; 143 intel_de_write_fw(display, reg, val); 144 145 return old; 146 } 147 148 static inline u32 149 intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) 150 { 151 return intel_uncore_read_notrace(__to_uncore(display), reg); 152 } 153 154 static inline void 155 intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val) 156 { 157 intel_uncore_write_notrace(__to_uncore(display), reg, val); 158 } 159 160 static __always_inline void 161 intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb, 162 i915_reg_t reg, u32 val) 163 { 164 if (dsb) 165 intel_dsb_reg_write(dsb, reg, val); 166 else 167 intel_de_write_fw(display, reg, val); 168 } 169 170 #endif /* __INTEL_DE_H__ */ 171