1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DE_H__ 7 #define __INTEL_DE_H__ 8 9 #include <drm/drm_print.h> 10 11 #include "intel_display_core.h" 12 #include "intel_dmc_wl.h" 13 #include "intel_dsb.h" 14 #include "intel_uncore.h" 15 #include "intel_uncore_trace.h" 16 17 static inline struct intel_uncore *__to_uncore(struct intel_display *display) 18 { 19 return to_intel_uncore(display->drm); 20 } 21 22 static inline u32 23 intel_de_read(struct intel_display *display, i915_reg_t reg) 24 { 25 u32 val; 26 27 intel_dmc_wl_get(display, reg); 28 29 val = intel_uncore_read(__to_uncore(display), reg); 30 31 intel_dmc_wl_put(display, reg); 32 33 return val; 34 } 35 36 static inline u8 37 intel_de_read8(struct intel_display *display, i915_reg_t reg) 38 { 39 /* this is only used on VGA registers (possible on pre-g4x) */ 40 drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x); 41 42 return intel_uncore_read8(__to_uncore(display), reg); 43 } 44 45 static inline void 46 intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val) 47 { 48 drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x); 49 50 intel_uncore_write8(__to_uncore(display), reg, val); 51 } 52 53 static inline u64 54 intel_de_read64_2x32(struct intel_display *display, 55 i915_reg_t lower_reg, i915_reg_t upper_reg) 56 { 57 u64 val; 58 59 intel_dmc_wl_get(display, lower_reg); 60 intel_dmc_wl_get(display, upper_reg); 61 62 val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg, 63 upper_reg); 64 65 intel_dmc_wl_put(display, upper_reg); 66 intel_dmc_wl_put(display, lower_reg); 67 68 return val; 69 } 70 71 static inline void 72 intel_de_posting_read(struct intel_display *display, i915_reg_t reg) 73 { 74 intel_dmc_wl_get(display, reg); 75 76 intel_uncore_posting_read(__to_uncore(display), reg); 77 78 intel_dmc_wl_put(display, reg); 79 } 80 81 static inline void 82 intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) 83 { 84 intel_dmc_wl_get(display, reg); 85 86 intel_uncore_write(__to_uncore(display), reg, val); 87 88 intel_dmc_wl_put(display, reg); 89 } 90 91 static inline u32 92 intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) 93 { 94 u32 val; 95 96 intel_dmc_wl_get(display, reg); 97 98 val = intel_uncore_rmw(__to_uncore(display), reg, clear, set); 99 100 intel_dmc_wl_put(display, reg); 101 102 return val; 103 } 104 105 static inline int 106 intel_de_wait_us(struct intel_display *display, i915_reg_t reg, 107 u32 mask, u32 value, unsigned int timeout_us, 108 u32 *out_value) 109 { 110 int ret; 111 112 intel_dmc_wl_get(display, reg); 113 114 ret = __intel_wait_for_register(__to_uncore(display), reg, mask, 115 value, timeout_us, 0, out_value); 116 117 intel_dmc_wl_put(display, reg); 118 119 return ret; 120 } 121 122 static inline int 123 intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, 124 u32 mask, u32 value, unsigned int timeout_ms, 125 u32 *out_value) 126 { 127 int ret; 128 129 intel_dmc_wl_get(display, reg); 130 131 ret = __intel_wait_for_register(__to_uncore(display), reg, mask, 132 value, 2, timeout_ms, out_value); 133 134 intel_dmc_wl_put(display, reg); 135 136 return ret; 137 } 138 139 static inline int 140 intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, 141 u32 mask, u32 value, unsigned int timeout_ms, 142 u32 *out_value) 143 { 144 return __intel_wait_for_register_fw(__to_uncore(display), reg, mask, 145 value, 2, timeout_ms, out_value); 146 } 147 148 static inline int 149 intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, 150 u32 mask, u32 value, unsigned int timeout_us, 151 u32 *out_value) 152 { 153 return __intel_wait_for_register_fw(__to_uncore(display), reg, mask, 154 value, timeout_us, 0, out_value); 155 } 156 157 static inline int 158 intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg, 159 u32 mask, unsigned int timeout_us) 160 { 161 return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL); 162 } 163 164 static inline int 165 intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg, 166 u32 mask, unsigned int timeout_us) 167 { 168 return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL); 169 } 170 171 static inline int 172 intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg, 173 u32 mask, unsigned int timeout_ms) 174 { 175 return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL); 176 } 177 178 static inline int 179 intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, 180 u32 mask, unsigned int timeout_ms) 181 { 182 return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL); 183 } 184 185 /* 186 * Unlocked mmio-accessors, think carefully before using these. 187 * 188 * Certain architectures will die if the same cacheline is concurrently accessed 189 * by different clients (e.g. on Ivybridge). Access to registers should 190 * therefore generally be serialised, by either the dev_priv->uncore.lock or 191 * a more localised lock guarding all access to that bank of registers. 192 */ 193 static inline u32 194 intel_de_read_fw(struct intel_display *display, i915_reg_t reg) 195 { 196 u32 val; 197 198 val = intel_uncore_read_fw(__to_uncore(display), reg); 199 trace_i915_reg_rw(false, reg, val, sizeof(val), true); 200 201 return val; 202 } 203 204 static inline void 205 intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) 206 { 207 trace_i915_reg_rw(true, reg, val, sizeof(val), true); 208 intel_uncore_write_fw(__to_uncore(display), reg, val); 209 } 210 211 static inline u32 212 intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) 213 { 214 u32 old, val; 215 216 old = intel_de_read_fw(display, reg); 217 val = (old & ~clear) | set; 218 intel_de_write_fw(display, reg, val); 219 220 return old; 221 } 222 223 static inline u32 224 intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) 225 { 226 return intel_uncore_read_notrace(__to_uncore(display), reg); 227 } 228 229 static inline void 230 intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val) 231 { 232 intel_uncore_write_notrace(__to_uncore(display), reg, val); 233 } 234 235 static __always_inline void 236 intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb, 237 i915_reg_t reg, u32 val) 238 { 239 if (dsb) 240 intel_dsb_reg_write(dsb, reg, val); 241 else 242 intel_de_write_fw(display, reg, val); 243 } 244 245 #endif /* __INTEL_DE_H__ */ 246