1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dp_tunnel.h" 58 #include "intel_dpio_phy.h" 59 #include "intel_dsi.h" 60 #include "intel_fdi.h" 61 #include "intel_fifo_underrun.h" 62 #include "intel_gmbus.h" 63 #include "intel_hdcp.h" 64 #include "intel_hdmi.h" 65 #include "intel_hotplug.h" 66 #include "intel_hti.h" 67 #include "intel_lspcon.h" 68 #include "intel_mg_phy_regs.h" 69 #include "intel_modeset_lock.h" 70 #include "intel_pps.h" 71 #include "intel_psr.h" 72 #include "intel_quirks.h" 73 #include "intel_snps_phy.h" 74 #include "intel_tc.h" 75 #include "intel_vdsc.h" 76 #include "intel_vdsc_regs.h" 77 #include "skl_scaler.h" 78 #include "skl_universal_plane.h" 79 80 static const u8 index_to_dp_signal_levels[] = { 81 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 82 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 83 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 84 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 85 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 86 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 87 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 88 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 91 }; 92 93 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 94 const struct intel_ddi_buf_trans *trans) 95 { 96 int level; 97 98 level = intel_bios_hdmi_level_shift(encoder->devdata); 99 if (level < 0) 100 level = trans->hdmi_default_entry; 101 102 return level; 103 } 104 105 static bool has_buf_trans_select(struct drm_i915_private *i915) 106 { 107 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 108 } 109 110 static bool has_iboost(struct drm_i915_private *i915) 111 { 112 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 113 } 114 115 /* 116 * Starting with Haswell, DDI port buffers must be programmed with correct 117 * values in advance. This function programs the correct values for 118 * DP/eDP/FDI use cases. 119 */ 120 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 121 const struct intel_crtc_state *crtc_state) 122 { 123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 124 u32 iboost_bit = 0; 125 int i, n_entries; 126 enum port port = encoder->port; 127 const struct intel_ddi_buf_trans *trans; 128 129 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 130 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 131 return; 132 133 /* If we're boosting the current, set bit 31 of trans1 */ 134 if (has_iboost(dev_priv) && 135 intel_bios_dp_boost_level(encoder->devdata)) 136 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 137 138 for (i = 0; i < n_entries; i++) { 139 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 140 trans->entries[i].hsw.trans1 | iboost_bit); 141 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 142 trans->entries[i].hsw.trans2); 143 } 144 } 145 146 /* 147 * Starting with Haswell, DDI port buffers must be programmed with correct 148 * values in advance. This function programs the correct values for 149 * HDMI/DVI use cases. 150 */ 151 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 152 const struct intel_crtc_state *crtc_state) 153 { 154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 155 int level = intel_ddi_level(encoder, crtc_state, 0); 156 u32 iboost_bit = 0; 157 int n_entries; 158 enum port port = encoder->port; 159 const struct intel_ddi_buf_trans *trans; 160 161 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 162 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 163 return; 164 165 /* If we're boosting the current, set bit 31 of trans1 */ 166 if (has_iboost(dev_priv) && 167 intel_bios_hdmi_boost_level(encoder->devdata)) 168 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 169 170 /* Entry 9 is for HDMI: */ 171 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 172 trans->entries[level].hsw.trans1 | iboost_bit); 173 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 174 trans->entries[level].hsw.trans2); 175 } 176 177 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 178 { 179 int ret; 180 181 /* FIXME: find out why Bspec's 100us timeout is too short */ 182 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 183 XELPDP_PORT_BUF_PHY_IDLE), 10000); 184 if (ret) 185 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 186 port_name(port)); 187 } 188 189 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 190 enum port port) 191 { 192 if (IS_BROXTON(dev_priv)) { 193 udelay(16); 194 return; 195 } 196 197 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 198 DDI_BUF_IS_IDLE), 8)) 199 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 200 port_name(port)); 201 } 202 203 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 204 { 205 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 206 enum port port = encoder->port; 207 int timeout_us; 208 int ret; 209 210 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 211 if (DISPLAY_VER(dev_priv) < 10) { 212 usleep_range(518, 1000); 213 return; 214 } 215 216 if (DISPLAY_VER(dev_priv) >= 14) { 217 timeout_us = 10000; 218 } else if (IS_DG2(dev_priv)) { 219 timeout_us = 1200; 220 } else if (DISPLAY_VER(dev_priv) >= 12) { 221 if (intel_encoder_is_tc(encoder)) 222 timeout_us = 3000; 223 else 224 timeout_us = 1000; 225 } else { 226 timeout_us = 500; 227 } 228 229 if (DISPLAY_VER(dev_priv) >= 14) 230 ret = _wait_for(!(intel_de_read(dev_priv, 231 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 232 XELPDP_PORT_BUF_PHY_IDLE), 233 timeout_us, 10, 10); 234 else 235 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 236 timeout_us, 10, 10); 237 238 if (ret) 239 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 240 port_name(port)); 241 } 242 243 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 244 { 245 switch (pll->info->id) { 246 case DPLL_ID_WRPLL1: 247 return PORT_CLK_SEL_WRPLL1; 248 case DPLL_ID_WRPLL2: 249 return PORT_CLK_SEL_WRPLL2; 250 case DPLL_ID_SPLL: 251 return PORT_CLK_SEL_SPLL; 252 case DPLL_ID_LCPLL_810: 253 return PORT_CLK_SEL_LCPLL_810; 254 case DPLL_ID_LCPLL_1350: 255 return PORT_CLK_SEL_LCPLL_1350; 256 case DPLL_ID_LCPLL_2700: 257 return PORT_CLK_SEL_LCPLL_2700; 258 default: 259 MISSING_CASE(pll->info->id); 260 return PORT_CLK_SEL_NONE; 261 } 262 } 263 264 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 265 const struct intel_crtc_state *crtc_state) 266 { 267 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 268 int clock = crtc_state->port_clock; 269 const enum intel_dpll_id id = pll->info->id; 270 271 switch (id) { 272 default: 273 /* 274 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 275 * here, so do warn if this get passed in 276 */ 277 MISSING_CASE(id); 278 return DDI_CLK_SEL_NONE; 279 case DPLL_ID_ICL_TBTPLL: 280 switch (clock) { 281 case 162000: 282 return DDI_CLK_SEL_TBT_162; 283 case 270000: 284 return DDI_CLK_SEL_TBT_270; 285 case 540000: 286 return DDI_CLK_SEL_TBT_540; 287 case 810000: 288 return DDI_CLK_SEL_TBT_810; 289 default: 290 MISSING_CASE(clock); 291 return DDI_CLK_SEL_NONE; 292 } 293 case DPLL_ID_ICL_MGPLL1: 294 case DPLL_ID_ICL_MGPLL2: 295 case DPLL_ID_ICL_MGPLL3: 296 case DPLL_ID_ICL_MGPLL4: 297 case DPLL_ID_TGL_MGPLL5: 298 case DPLL_ID_TGL_MGPLL6: 299 return DDI_CLK_SEL_MG; 300 } 301 } 302 303 static u32 ddi_buf_phy_link_rate(int port_clock) 304 { 305 switch (port_clock) { 306 case 162000: 307 return DDI_BUF_PHY_LINK_RATE(0); 308 case 216000: 309 return DDI_BUF_PHY_LINK_RATE(4); 310 case 243000: 311 return DDI_BUF_PHY_LINK_RATE(5); 312 case 270000: 313 return DDI_BUF_PHY_LINK_RATE(1); 314 case 324000: 315 return DDI_BUF_PHY_LINK_RATE(6); 316 case 432000: 317 return DDI_BUF_PHY_LINK_RATE(7); 318 case 540000: 319 return DDI_BUF_PHY_LINK_RATE(2); 320 case 810000: 321 return DDI_BUF_PHY_LINK_RATE(3); 322 default: 323 MISSING_CASE(port_clock); 324 return DDI_BUF_PHY_LINK_RATE(0); 325 } 326 } 327 328 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 329 const struct intel_crtc_state *crtc_state) 330 { 331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 332 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 333 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 334 335 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 336 intel_dp->DP = dig_port->saved_port_bits | 337 DDI_PORT_WIDTH(crtc_state->lane_count) | 338 DDI_BUF_TRANS_SELECT(0); 339 340 if (DISPLAY_VER(i915) >= 14) { 341 if (intel_dp_is_uhbr(crtc_state)) 342 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 343 else 344 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 345 } 346 347 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 348 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 349 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 350 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 351 } 352 } 353 354 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 355 enum port port) 356 { 357 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 358 359 switch (val) { 360 case DDI_CLK_SEL_NONE: 361 return 0; 362 case DDI_CLK_SEL_TBT_162: 363 return 162000; 364 case DDI_CLK_SEL_TBT_270: 365 return 270000; 366 case DDI_CLK_SEL_TBT_540: 367 return 540000; 368 case DDI_CLK_SEL_TBT_810: 369 return 810000; 370 default: 371 MISSING_CASE(val); 372 return 0; 373 } 374 } 375 376 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 377 { 378 /* CRT dotclock is determined via other means */ 379 if (pipe_config->has_pch_encoder) 380 return; 381 382 pipe_config->hw.adjusted_mode.crtc_clock = 383 intel_crtc_dotclock(pipe_config); 384 } 385 386 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 387 const struct drm_connector_state *conn_state) 388 { 389 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 392 u32 temp; 393 394 if (!intel_crtc_has_dp_encoder(crtc_state)) 395 return; 396 397 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 398 399 temp = DP_MSA_MISC_SYNC_CLOCK; 400 401 switch (crtc_state->pipe_bpp) { 402 case 18: 403 temp |= DP_MSA_MISC_6_BPC; 404 break; 405 case 24: 406 temp |= DP_MSA_MISC_8_BPC; 407 break; 408 case 30: 409 temp |= DP_MSA_MISC_10_BPC; 410 break; 411 case 36: 412 temp |= DP_MSA_MISC_12_BPC; 413 break; 414 default: 415 MISSING_CASE(crtc_state->pipe_bpp); 416 break; 417 } 418 419 /* nonsense combination */ 420 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 421 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 422 423 if (crtc_state->limited_color_range) 424 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 425 426 /* 427 * As per DP 1.2 spec section 2.3.4.3 while sending 428 * YCBCR 444 signals we should program MSA MISC1/0 fields with 429 * colorspace information. 430 */ 431 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 432 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 433 434 /* 435 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 436 * of Color Encoding Format and Content Color Gamut] while sending 437 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 438 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 439 */ 440 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 441 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 442 443 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 444 } 445 446 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 447 { 448 if (master_transcoder == TRANSCODER_EDP) 449 return 0; 450 else 451 return master_transcoder + 1; 452 } 453 454 static void 455 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 456 const struct intel_crtc_state *crtc_state) 457 { 458 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 460 u32 val = 0; 461 462 if (intel_dp_is_uhbr(crtc_state)) 463 val = TRANS_DP2_128B132B_CHANNEL_CODING; 464 465 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 466 } 467 468 /* 469 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 470 * 471 * Only intended to be used by intel_ddi_enable_transcoder_func() and 472 * intel_ddi_config_transcoder_func(). 473 */ 474 static u32 475 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 476 const struct intel_crtc_state *crtc_state) 477 { 478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 480 enum pipe pipe = crtc->pipe; 481 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 482 enum port port = encoder->port; 483 u32 temp; 484 485 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 486 temp = TRANS_DDI_FUNC_ENABLE; 487 if (DISPLAY_VER(dev_priv) >= 12) 488 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 489 else 490 temp |= TRANS_DDI_SELECT_PORT(port); 491 492 switch (crtc_state->pipe_bpp) { 493 default: 494 MISSING_CASE(crtc_state->pipe_bpp); 495 fallthrough; 496 case 18: 497 temp |= TRANS_DDI_BPC_6; 498 break; 499 case 24: 500 temp |= TRANS_DDI_BPC_8; 501 break; 502 case 30: 503 temp |= TRANS_DDI_BPC_10; 504 break; 505 case 36: 506 temp |= TRANS_DDI_BPC_12; 507 break; 508 } 509 510 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 511 temp |= TRANS_DDI_PVSYNC; 512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 513 temp |= TRANS_DDI_PHSYNC; 514 515 if (cpu_transcoder == TRANSCODER_EDP) { 516 switch (pipe) { 517 default: 518 MISSING_CASE(pipe); 519 fallthrough; 520 case PIPE_A: 521 /* On Haswell, can only use the always-on power well for 522 * eDP when not using the panel fitter, and when not 523 * using motion blur mitigation (which we don't 524 * support). */ 525 if (crtc_state->pch_pfit.force_thru) 526 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 527 else 528 temp |= TRANS_DDI_EDP_INPUT_A_ON; 529 break; 530 case PIPE_B: 531 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 532 break; 533 case PIPE_C: 534 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 535 break; 536 } 537 } 538 539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 540 if (crtc_state->has_hdmi_sink) 541 temp |= TRANS_DDI_MODE_SELECT_HDMI; 542 else 543 temp |= TRANS_DDI_MODE_SELECT_DVI; 544 545 if (crtc_state->hdmi_scrambling) 546 temp |= TRANS_DDI_HDMI_SCRAMBLING; 547 if (crtc_state->hdmi_high_tmds_clock_ratio) 548 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 549 if (DISPLAY_VER(dev_priv) >= 14) 550 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 551 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 552 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 553 temp |= (crtc_state->fdi_lanes - 1) << 1; 554 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 555 if (intel_dp_is_uhbr(crtc_state)) 556 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 557 else 558 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 559 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 560 561 if (DISPLAY_VER(dev_priv) >= 12) { 562 enum transcoder master; 563 564 master = crtc_state->mst_master_transcoder; 565 drm_WARN_ON(&dev_priv->drm, 566 master == INVALID_TRANSCODER); 567 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 568 } 569 } else { 570 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 } 573 574 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 575 crtc_state->master_transcoder != INVALID_TRANSCODER) { 576 u8 master_select = 577 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 578 579 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 580 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 581 } 582 583 return temp; 584 } 585 586 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 587 const struct intel_crtc_state *crtc_state) 588 { 589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 592 593 if (DISPLAY_VER(dev_priv) >= 11) { 594 enum transcoder master_transcoder = crtc_state->master_transcoder; 595 u32 ctl2 = 0; 596 597 if (master_transcoder != INVALID_TRANSCODER) { 598 u8 master_select = 599 bdw_trans_port_sync_master_select(master_transcoder); 600 601 ctl2 |= PORT_SYNC_MODE_ENABLE | 602 PORT_SYNC_MODE_MASTER_SELECT(master_select); 603 } 604 605 intel_de_write(dev_priv, 606 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 607 } 608 609 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 610 intel_ddi_transcoder_func_reg_val_get(encoder, 611 crtc_state)); 612 } 613 614 /* 615 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 616 * bit. 617 */ 618 static void 619 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 620 const struct intel_crtc_state *crtc_state) 621 { 622 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 624 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 625 u32 ctl; 626 627 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 628 ctl &= ~TRANS_DDI_FUNC_ENABLE; 629 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 630 } 631 632 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 633 { 634 struct intel_display *display = to_intel_display(crtc_state); 635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 637 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 638 u32 ctl; 639 640 if (DISPLAY_VER(dev_priv) >= 11) 641 intel_de_write(dev_priv, 642 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 643 644 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 645 646 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 647 648 ctl &= ~TRANS_DDI_FUNC_ENABLE; 649 650 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 651 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 652 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 653 654 if (DISPLAY_VER(dev_priv) >= 12) { 655 if (!intel_dp_mst_is_master_trans(crtc_state)) { 656 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 657 TRANS_DDI_MODE_SELECT_MASK); 658 } 659 } else { 660 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 661 } 662 663 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 664 665 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 666 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 667 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 668 /* Quirk time at 100ms for reliable operation */ 669 msleep(100); 670 } 671 } 672 673 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 674 enum transcoder cpu_transcoder, 675 bool enable, u32 hdcp_mask) 676 { 677 struct drm_device *dev = intel_encoder->base.dev; 678 struct drm_i915_private *dev_priv = to_i915(dev); 679 intel_wakeref_t wakeref; 680 int ret = 0; 681 682 wakeref = intel_display_power_get_if_enabled(dev_priv, 683 intel_encoder->power_domain); 684 if (drm_WARN_ON(dev, !wakeref)) 685 return -ENXIO; 686 687 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 688 hdcp_mask, enable ? hdcp_mask : 0); 689 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 690 return ret; 691 } 692 693 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 694 { 695 struct drm_device *dev = intel_connector->base.dev; 696 struct drm_i915_private *dev_priv = to_i915(dev); 697 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 698 int type = intel_connector->base.connector_type; 699 enum port port = encoder->port; 700 enum transcoder cpu_transcoder; 701 intel_wakeref_t wakeref; 702 enum pipe pipe = 0; 703 u32 tmp; 704 bool ret; 705 706 wakeref = intel_display_power_get_if_enabled(dev_priv, 707 encoder->power_domain); 708 if (!wakeref) 709 return false; 710 711 if (!encoder->get_hw_state(encoder, &pipe)) { 712 ret = false; 713 goto out; 714 } 715 716 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 717 cpu_transcoder = TRANSCODER_EDP; 718 else 719 cpu_transcoder = (enum transcoder) pipe; 720 721 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 722 723 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 724 case TRANS_DDI_MODE_SELECT_HDMI: 725 case TRANS_DDI_MODE_SELECT_DVI: 726 ret = type == DRM_MODE_CONNECTOR_HDMIA; 727 break; 728 729 case TRANS_DDI_MODE_SELECT_DP_SST: 730 ret = type == DRM_MODE_CONNECTOR_eDP || 731 type == DRM_MODE_CONNECTOR_DisplayPort; 732 break; 733 734 case TRANS_DDI_MODE_SELECT_DP_MST: 735 /* if the transcoder is in MST state then 736 * connector isn't connected */ 737 ret = false; 738 break; 739 740 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 741 if (HAS_DP20(dev_priv)) 742 /* 128b/132b */ 743 ret = false; 744 else 745 /* FDI */ 746 ret = type == DRM_MODE_CONNECTOR_VGA; 747 break; 748 749 default: 750 ret = false; 751 break; 752 } 753 754 out: 755 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 756 757 return ret; 758 } 759 760 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 761 u8 *pipe_mask, bool *is_dp_mst) 762 { 763 struct drm_device *dev = encoder->base.dev; 764 struct drm_i915_private *dev_priv = to_i915(dev); 765 enum port port = encoder->port; 766 intel_wakeref_t wakeref; 767 enum pipe p; 768 u32 tmp; 769 u8 mst_pipe_mask; 770 771 *pipe_mask = 0; 772 *is_dp_mst = false; 773 774 wakeref = intel_display_power_get_if_enabled(dev_priv, 775 encoder->power_domain); 776 if (!wakeref) 777 return; 778 779 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 780 if (!(tmp & DDI_BUF_CTL_ENABLE)) 781 goto out; 782 783 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 784 tmp = intel_de_read(dev_priv, 785 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 786 787 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 788 default: 789 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 790 fallthrough; 791 case TRANS_DDI_EDP_INPUT_A_ON: 792 case TRANS_DDI_EDP_INPUT_A_ONOFF: 793 *pipe_mask = BIT(PIPE_A); 794 break; 795 case TRANS_DDI_EDP_INPUT_B_ONOFF: 796 *pipe_mask = BIT(PIPE_B); 797 break; 798 case TRANS_DDI_EDP_INPUT_C_ONOFF: 799 *pipe_mask = BIT(PIPE_C); 800 break; 801 } 802 803 goto out; 804 } 805 806 mst_pipe_mask = 0; 807 for_each_pipe(dev_priv, p) { 808 enum transcoder cpu_transcoder = (enum transcoder)p; 809 unsigned int port_mask, ddi_select; 810 intel_wakeref_t trans_wakeref; 811 812 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 813 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 814 if (!trans_wakeref) 815 continue; 816 817 if (DISPLAY_VER(dev_priv) >= 12) { 818 port_mask = TGL_TRANS_DDI_PORT_MASK; 819 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 820 } else { 821 port_mask = TRANS_DDI_PORT_MASK; 822 ddi_select = TRANS_DDI_SELECT_PORT(port); 823 } 824 825 tmp = intel_de_read(dev_priv, 826 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 827 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 828 trans_wakeref); 829 830 if ((tmp & port_mask) != ddi_select) 831 continue; 832 833 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 834 (HAS_DP20(dev_priv) && 835 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 836 mst_pipe_mask |= BIT(p); 837 838 *pipe_mask |= BIT(p); 839 } 840 841 if (!*pipe_mask) 842 drm_dbg_kms(&dev_priv->drm, 843 "No pipe for [ENCODER:%d:%s] found\n", 844 encoder->base.base.id, encoder->base.name); 845 846 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 847 drm_dbg_kms(&dev_priv->drm, 848 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 849 encoder->base.base.id, encoder->base.name, 850 *pipe_mask); 851 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 852 } 853 854 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 855 drm_dbg_kms(&dev_priv->drm, 856 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 857 encoder->base.base.id, encoder->base.name, 858 *pipe_mask, mst_pipe_mask); 859 else 860 *is_dp_mst = mst_pipe_mask; 861 862 out: 863 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 864 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 865 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 866 BXT_PHY_LANE_POWERDOWN_ACK | 867 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 868 drm_err(&dev_priv->drm, 869 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 870 encoder->base.base.id, encoder->base.name, tmp); 871 } 872 873 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 874 } 875 876 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 877 enum pipe *pipe) 878 { 879 u8 pipe_mask; 880 bool is_mst; 881 882 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 883 884 if (is_mst || !pipe_mask) 885 return false; 886 887 *pipe = ffs(pipe_mask) - 1; 888 889 return true; 890 } 891 892 static enum intel_display_power_domain 893 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 894 const struct intel_crtc_state *crtc_state) 895 { 896 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 897 898 /* 899 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 900 * DC states enabled at the same time, while for driver initiated AUX 901 * transfers we need the same AUX IOs to be powered but with DC states 902 * disabled. Accordingly use the AUX_IO_<port> power domain here which 903 * leaves DC states enabled. 904 * 905 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 906 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 907 * well, so we can acquire a wider AUX_<port> power domain reference 908 * instead of a specific AUX_IO_<port> reference without powering up any 909 * extra wells. 910 */ 911 if (intel_encoder_can_psr(&dig_port->base)) 912 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 913 else if (DISPLAY_VER(i915) < 14 && 914 (intel_crtc_has_dp_encoder(crtc_state) || 915 intel_encoder_is_tc(&dig_port->base))) 916 return intel_aux_power_domain(dig_port); 917 else 918 return POWER_DOMAIN_INVALID; 919 } 920 921 static void 922 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 923 const struct intel_crtc_state *crtc_state) 924 { 925 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 926 enum intel_display_power_domain domain = 927 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 928 929 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 930 931 if (domain == POWER_DOMAIN_INVALID) 932 return; 933 934 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 935 } 936 937 static void 938 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 939 const struct intel_crtc_state *crtc_state) 940 { 941 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 942 enum intel_display_power_domain domain = 943 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 944 intel_wakeref_t wf; 945 946 wf = fetch_and_zero(&dig_port->aux_wakeref); 947 if (!wf) 948 return; 949 950 intel_display_power_put(i915, domain, wf); 951 } 952 953 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 954 struct intel_crtc_state *crtc_state) 955 { 956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 957 struct intel_digital_port *dig_port; 958 959 /* 960 * TODO: Add support for MST encoders. Atm, the following should never 961 * happen since fake-MST encoders don't set their get_power_domains() 962 * hook. 963 */ 964 if (drm_WARN_ON(&dev_priv->drm, 965 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 966 return; 967 968 dig_port = enc_to_dig_port(encoder); 969 970 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 971 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 972 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 973 dig_port->ddi_io_power_domain); 974 } 975 976 main_link_aux_power_domain_get(dig_port, crtc_state); 977 } 978 979 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 980 const struct intel_crtc_state *crtc_state) 981 { 982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 983 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 984 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 985 enum phy phy = intel_encoder_to_phy(encoder); 986 u32 val; 987 988 if (cpu_transcoder == TRANSCODER_EDP) 989 return; 990 991 if (DISPLAY_VER(dev_priv) >= 13) 992 val = TGL_TRANS_CLK_SEL_PORT(phy); 993 else if (DISPLAY_VER(dev_priv) >= 12) 994 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 995 else 996 val = TRANS_CLK_SEL_PORT(encoder->port); 997 998 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 999 } 1000 1001 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1002 { 1003 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1004 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1005 u32 val; 1006 1007 if (cpu_transcoder == TRANSCODER_EDP) 1008 return; 1009 1010 if (DISPLAY_VER(dev_priv) >= 12) 1011 val = TGL_TRANS_CLK_SEL_DISABLED; 1012 else 1013 val = TRANS_CLK_SEL_DISABLED; 1014 1015 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1016 } 1017 1018 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1019 enum port port, u8 iboost) 1020 { 1021 u32 tmp; 1022 1023 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1024 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1025 if (iboost) 1026 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1027 else 1028 tmp |= BALANCE_LEG_DISABLE(port); 1029 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1030 } 1031 1032 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1033 const struct intel_crtc_state *crtc_state, 1034 int level) 1035 { 1036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1038 u8 iboost; 1039 1040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1041 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1042 else 1043 iboost = intel_bios_dp_boost_level(encoder->devdata); 1044 1045 if (iboost == 0) { 1046 const struct intel_ddi_buf_trans *trans; 1047 int n_entries; 1048 1049 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1050 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1051 return; 1052 1053 iboost = trans->entries[level].hsw.i_boost; 1054 } 1055 1056 /* Make sure that the requested I_boost is valid */ 1057 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1058 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1059 return; 1060 } 1061 1062 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1063 1064 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1065 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1066 } 1067 1068 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1069 const struct intel_crtc_state *crtc_state) 1070 { 1071 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1073 int n_entries; 1074 1075 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1076 1077 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1078 n_entries = 1; 1079 if (drm_WARN_ON(&dev_priv->drm, 1080 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1081 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1082 1083 return index_to_dp_signal_levels[n_entries - 1] & 1084 DP_TRAIN_VOLTAGE_SWING_MASK; 1085 } 1086 1087 /* 1088 * We assume that the full set of pre-emphasis values can be 1089 * used on all DDI platforms. Should that change we need to 1090 * rethink this code. 1091 */ 1092 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1093 { 1094 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1095 } 1096 1097 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1098 int lane) 1099 { 1100 if (crtc_state->port_clock > 600000) 1101 return 0; 1102 1103 if (crtc_state->lane_count == 4) 1104 return lane >= 1 ? LOADGEN_SELECT : 0; 1105 else 1106 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1107 } 1108 1109 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1110 const struct intel_crtc_state *crtc_state) 1111 { 1112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1113 const struct intel_ddi_buf_trans *trans; 1114 enum phy phy = intel_encoder_to_phy(encoder); 1115 int n_entries, ln; 1116 u32 val; 1117 1118 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1119 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1120 return; 1121 1122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1123 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1124 1125 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1126 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1127 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1128 intel_dp->hobl_active ? val : 0); 1129 } 1130 1131 /* Set PORT_TX_DW5 */ 1132 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1133 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1134 TAP2_DISABLE | TAP3_DISABLE); 1135 val |= SCALING_MODE_SEL(0x2); 1136 val |= RTERM_SELECT(0x6); 1137 val |= TAP3_DISABLE; 1138 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1139 1140 /* Program PORT_TX_DW2 */ 1141 for (ln = 0; ln < 4; ln++) { 1142 int level = intel_ddi_level(encoder, crtc_state, ln); 1143 1144 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1145 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1146 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1147 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1148 RCOMP_SCALAR(0x98)); 1149 } 1150 1151 /* Program PORT_TX_DW4 */ 1152 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1153 for (ln = 0; ln < 4; ln++) { 1154 int level = intel_ddi_level(encoder, crtc_state, ln); 1155 1156 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1157 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1158 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1159 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1160 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1161 } 1162 1163 /* Program PORT_TX_DW7 */ 1164 for (ln = 0; ln < 4; ln++) { 1165 int level = intel_ddi_level(encoder, crtc_state, ln); 1166 1167 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1168 N_SCALAR_MASK, 1169 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1170 } 1171 } 1172 1173 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1174 const struct intel_crtc_state *crtc_state) 1175 { 1176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1177 enum phy phy = intel_encoder_to_phy(encoder); 1178 u32 val; 1179 int ln; 1180 1181 /* 1182 * 1. If port type is eDP or DP, 1183 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1184 * else clear to 0b. 1185 */ 1186 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1187 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1188 val &= ~COMMON_KEEPER_EN; 1189 else 1190 val |= COMMON_KEEPER_EN; 1191 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1192 1193 /* 2. Program loadgen select */ 1194 /* 1195 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1196 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1197 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1198 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1199 */ 1200 for (ln = 0; ln < 4; ln++) { 1201 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1202 LOADGEN_SELECT, 1203 icl_combo_phy_loadgen_select(crtc_state, ln)); 1204 } 1205 1206 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1207 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1208 0, SUS_CLOCK_CONFIG); 1209 1210 /* 4. Clear training enable to change swing values */ 1211 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1212 val &= ~TX_TRAINING_EN; 1213 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1214 1215 /* 5. Program swing and de-emphasis */ 1216 icl_ddi_combo_vswing_program(encoder, crtc_state); 1217 1218 /* 6. Set training enable to trigger update */ 1219 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1220 val |= TX_TRAINING_EN; 1221 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1222 } 1223 1224 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1225 const struct intel_crtc_state *crtc_state) 1226 { 1227 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1228 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1229 const struct intel_ddi_buf_trans *trans; 1230 int n_entries, ln; 1231 1232 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1233 return; 1234 1235 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1236 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1237 return; 1238 1239 for (ln = 0; ln < 2; ln++) { 1240 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1241 CRI_USE_FS32, 0); 1242 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1243 CRI_USE_FS32, 0); 1244 } 1245 1246 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1247 for (ln = 0; ln < 2; ln++) { 1248 int level; 1249 1250 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1251 1252 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1253 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1254 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1255 1256 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1257 1258 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1259 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1260 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1261 } 1262 1263 /* Program MG_TX_DRVCTRL with values from vswing table */ 1264 for (ln = 0; ln < 2; ln++) { 1265 int level; 1266 1267 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1268 1269 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1270 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1271 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1272 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1273 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1274 CRI_TXDEEMPH_OVERRIDE_EN); 1275 1276 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1277 1278 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1279 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1280 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1281 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1282 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1283 CRI_TXDEEMPH_OVERRIDE_EN); 1284 1285 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1286 } 1287 1288 /* 1289 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1290 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1291 * values from table for which TX1 and TX2 enabled. 1292 */ 1293 for (ln = 0; ln < 2; ln++) { 1294 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1295 CFG_LOW_RATE_LKREN_EN, 1296 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1297 } 1298 1299 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1300 for (ln = 0; ln < 2; ln++) { 1301 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1302 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1303 CFG_AMI_CK_DIV_OVERRIDE_EN, 1304 crtc_state->port_clock > 500000 ? 1305 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1306 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1307 1308 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1309 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1310 CFG_AMI_CK_DIV_OVERRIDE_EN, 1311 crtc_state->port_clock > 500000 ? 1312 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1313 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1314 } 1315 1316 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1317 for (ln = 0; ln < 2; ln++) { 1318 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1319 0, CRI_CALCINIT); 1320 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1321 0, CRI_CALCINIT); 1322 } 1323 } 1324 1325 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state) 1327 { 1328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1329 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1330 const struct intel_ddi_buf_trans *trans; 1331 int n_entries, ln; 1332 1333 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1334 return; 1335 1336 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1337 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1338 return; 1339 1340 for (ln = 0; ln < 2; ln++) { 1341 int level; 1342 1343 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1344 1345 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1346 1347 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1348 DKL_TX_PRESHOOT_COEFF_MASK | 1349 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1350 DKL_TX_VSWING_CONTROL_MASK, 1351 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1352 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1353 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1354 1355 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1356 1357 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1358 DKL_TX_PRESHOOT_COEFF_MASK | 1359 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1360 DKL_TX_VSWING_CONTROL_MASK, 1361 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1362 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1363 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1364 1365 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1366 DKL_TX_DP20BITMODE, 0); 1367 1368 if (IS_ALDERLAKE_P(dev_priv)) { 1369 u32 val; 1370 1371 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1372 if (ln == 0) { 1373 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1374 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1375 } else { 1376 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1377 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1378 } 1379 } else { 1380 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1381 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1382 } 1383 1384 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1385 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1386 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1387 val); 1388 } 1389 } 1390 } 1391 1392 static int translate_signal_level(struct intel_dp *intel_dp, 1393 u8 signal_levels) 1394 { 1395 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1396 int i; 1397 1398 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1399 if (index_to_dp_signal_levels[i] == signal_levels) 1400 return i; 1401 } 1402 1403 drm_WARN(&i915->drm, 1, 1404 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1405 signal_levels); 1406 1407 return 0; 1408 } 1409 1410 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1411 const struct intel_crtc_state *crtc_state, 1412 int lane) 1413 { 1414 u8 train_set = intel_dp->train_set[lane]; 1415 1416 if (intel_dp_is_uhbr(crtc_state)) { 1417 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1418 } else { 1419 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1420 DP_TRAIN_PRE_EMPHASIS_MASK); 1421 1422 return translate_signal_level(intel_dp, signal_levels); 1423 } 1424 } 1425 1426 int intel_ddi_level(struct intel_encoder *encoder, 1427 const struct intel_crtc_state *crtc_state, 1428 int lane) 1429 { 1430 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1431 const struct intel_ddi_buf_trans *trans; 1432 int level, n_entries; 1433 1434 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1435 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1436 return 0; 1437 1438 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1439 level = intel_ddi_hdmi_level(encoder, trans); 1440 else 1441 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1442 lane); 1443 1444 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1445 level = n_entries - 1; 1446 1447 return level; 1448 } 1449 1450 static void 1451 hsw_set_signal_levels(struct intel_encoder *encoder, 1452 const struct intel_crtc_state *crtc_state) 1453 { 1454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1456 int level = intel_ddi_level(encoder, crtc_state, 0); 1457 enum port port = encoder->port; 1458 u32 signal_levels; 1459 1460 if (has_iboost(dev_priv)) 1461 skl_ddi_set_iboost(encoder, crtc_state, level); 1462 1463 /* HDMI ignores the rest */ 1464 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1465 return; 1466 1467 signal_levels = DDI_BUF_TRANS_SELECT(level); 1468 1469 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1470 signal_levels); 1471 1472 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1473 intel_dp->DP |= signal_levels; 1474 1475 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1476 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1477 } 1478 1479 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1480 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1481 { 1482 mutex_lock(&i915->display.dpll.lock); 1483 1484 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1485 1486 /* 1487 * "This step and the step before must be 1488 * done with separate register writes." 1489 */ 1490 intel_de_rmw(i915, reg, clk_off, 0); 1491 1492 mutex_unlock(&i915->display.dpll.lock); 1493 } 1494 1495 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1496 u32 clk_off) 1497 { 1498 mutex_lock(&i915->display.dpll.lock); 1499 1500 intel_de_rmw(i915, reg, 0, clk_off); 1501 1502 mutex_unlock(&i915->display.dpll.lock); 1503 } 1504 1505 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1506 u32 clk_off) 1507 { 1508 return !(intel_de_read(i915, reg) & clk_off); 1509 } 1510 1511 static struct intel_shared_dpll * 1512 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1513 u32 clk_sel_mask, u32 clk_sel_shift) 1514 { 1515 enum intel_dpll_id id; 1516 1517 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1518 1519 return intel_get_shared_dpll_by_id(i915, id); 1520 } 1521 1522 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1523 const struct intel_crtc_state *crtc_state) 1524 { 1525 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1526 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1527 enum phy phy = intel_encoder_to_phy(encoder); 1528 1529 if (drm_WARN_ON(&i915->drm, !pll)) 1530 return; 1531 1532 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1533 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1534 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1535 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1536 } 1537 1538 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1539 { 1540 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1541 enum phy phy = intel_encoder_to_phy(encoder); 1542 1543 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1544 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1545 } 1546 1547 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1548 { 1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1550 enum phy phy = intel_encoder_to_phy(encoder); 1551 1552 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1553 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1554 } 1555 1556 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1557 { 1558 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1559 enum phy phy = intel_encoder_to_phy(encoder); 1560 1561 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1562 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1563 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1564 } 1565 1566 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1567 const struct intel_crtc_state *crtc_state) 1568 { 1569 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1570 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1571 enum phy phy = intel_encoder_to_phy(encoder); 1572 1573 if (drm_WARN_ON(&i915->drm, !pll)) 1574 return; 1575 1576 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1578 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1579 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1580 } 1581 1582 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1583 { 1584 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1585 enum phy phy = intel_encoder_to_phy(encoder); 1586 1587 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1588 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1589 } 1590 1591 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1592 { 1593 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1594 enum phy phy = intel_encoder_to_phy(encoder); 1595 1596 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1597 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1598 } 1599 1600 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1601 { 1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1603 enum phy phy = intel_encoder_to_phy(encoder); 1604 1605 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1606 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1607 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1608 } 1609 1610 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1611 const struct intel_crtc_state *crtc_state) 1612 { 1613 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1614 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1615 enum phy phy = intel_encoder_to_phy(encoder); 1616 1617 if (drm_WARN_ON(&i915->drm, !pll)) 1618 return; 1619 1620 /* 1621 * If we fail this, something went very wrong: first 2 PLLs should be 1622 * used by first 2 phys and last 2 PLLs by last phys 1623 */ 1624 if (drm_WARN_ON(&i915->drm, 1625 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1626 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1627 return; 1628 1629 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1630 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1631 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1632 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1633 } 1634 1635 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1636 { 1637 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1638 enum phy phy = intel_encoder_to_phy(encoder); 1639 1640 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1641 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1642 } 1643 1644 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1645 { 1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1647 enum phy phy = intel_encoder_to_phy(encoder); 1648 1649 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1650 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1651 } 1652 1653 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1654 { 1655 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 enum intel_dpll_id id; 1658 u32 val; 1659 1660 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1661 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1662 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1663 id = val; 1664 1665 /* 1666 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1667 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1668 * bit for phy C and D. 1669 */ 1670 if (phy >= PHY_C) 1671 id += DPLL_ID_DG1_DPLL2; 1672 1673 return intel_get_shared_dpll_by_id(i915, id); 1674 } 1675 1676 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1677 const struct intel_crtc_state *crtc_state) 1678 { 1679 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1680 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1681 enum phy phy = intel_encoder_to_phy(encoder); 1682 1683 if (drm_WARN_ON(&i915->drm, !pll)) 1684 return; 1685 1686 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1688 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1689 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1690 } 1691 1692 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 enum phy phy = intel_encoder_to_phy(encoder); 1696 1697 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1698 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1699 } 1700 1701 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1702 { 1703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1704 enum phy phy = intel_encoder_to_phy(encoder); 1705 1706 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1707 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1708 } 1709 1710 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1711 { 1712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1713 enum phy phy = intel_encoder_to_phy(encoder); 1714 1715 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1716 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1717 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1718 } 1719 1720 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1721 const struct intel_crtc_state *crtc_state) 1722 { 1723 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1724 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1725 enum port port = encoder->port; 1726 1727 if (drm_WARN_ON(&i915->drm, !pll)) 1728 return; 1729 1730 /* 1731 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1732 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1733 */ 1734 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1735 1736 icl_ddi_combo_enable_clock(encoder, crtc_state); 1737 } 1738 1739 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1740 { 1741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1742 enum port port = encoder->port; 1743 1744 icl_ddi_combo_disable_clock(encoder); 1745 1746 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1747 } 1748 1749 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1750 { 1751 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1752 enum port port = encoder->port; 1753 u32 tmp; 1754 1755 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1756 1757 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1758 return false; 1759 1760 return icl_ddi_combo_is_clock_enabled(encoder); 1761 } 1762 1763 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1764 const struct intel_crtc_state *crtc_state) 1765 { 1766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1767 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1768 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1769 enum port port = encoder->port; 1770 1771 if (drm_WARN_ON(&i915->drm, !pll)) 1772 return; 1773 1774 intel_de_write(i915, DDI_CLK_SEL(port), 1775 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1776 1777 mutex_lock(&i915->display.dpll.lock); 1778 1779 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1780 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1781 1782 mutex_unlock(&i915->display.dpll.lock); 1783 } 1784 1785 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1786 { 1787 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1788 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1789 enum port port = encoder->port; 1790 1791 mutex_lock(&i915->display.dpll.lock); 1792 1793 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1794 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1795 1796 mutex_unlock(&i915->display.dpll.lock); 1797 1798 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1799 } 1800 1801 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1802 { 1803 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1804 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1805 enum port port = encoder->port; 1806 u32 tmp; 1807 1808 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1809 1810 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1811 return false; 1812 1813 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1814 1815 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1816 } 1817 1818 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1819 { 1820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1821 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1822 enum port port = encoder->port; 1823 enum intel_dpll_id id; 1824 u32 tmp; 1825 1826 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1827 1828 switch (tmp & DDI_CLK_SEL_MASK) { 1829 case DDI_CLK_SEL_TBT_162: 1830 case DDI_CLK_SEL_TBT_270: 1831 case DDI_CLK_SEL_TBT_540: 1832 case DDI_CLK_SEL_TBT_810: 1833 id = DPLL_ID_ICL_TBTPLL; 1834 break; 1835 case DDI_CLK_SEL_MG: 1836 id = icl_tc_port_to_pll_id(tc_port); 1837 break; 1838 default: 1839 MISSING_CASE(tmp); 1840 fallthrough; 1841 case DDI_CLK_SEL_NONE: 1842 return NULL; 1843 } 1844 1845 return intel_get_shared_dpll_by_id(i915, id); 1846 } 1847 1848 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1849 { 1850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1851 enum intel_dpll_id id; 1852 1853 switch (encoder->port) { 1854 case PORT_A: 1855 id = DPLL_ID_SKL_DPLL0; 1856 break; 1857 case PORT_B: 1858 id = DPLL_ID_SKL_DPLL1; 1859 break; 1860 case PORT_C: 1861 id = DPLL_ID_SKL_DPLL2; 1862 break; 1863 default: 1864 MISSING_CASE(encoder->port); 1865 return NULL; 1866 } 1867 1868 return intel_get_shared_dpll_by_id(i915, id); 1869 } 1870 1871 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1872 const struct intel_crtc_state *crtc_state) 1873 { 1874 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1875 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1876 enum port port = encoder->port; 1877 1878 if (drm_WARN_ON(&i915->drm, !pll)) 1879 return; 1880 1881 mutex_lock(&i915->display.dpll.lock); 1882 1883 intel_de_rmw(i915, DPLL_CTRL2, 1884 DPLL_CTRL2_DDI_CLK_OFF(port) | 1885 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1886 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1887 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1888 1889 mutex_unlock(&i915->display.dpll.lock); 1890 } 1891 1892 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1893 { 1894 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1895 enum port port = encoder->port; 1896 1897 mutex_lock(&i915->display.dpll.lock); 1898 1899 intel_de_rmw(i915, DPLL_CTRL2, 1900 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1901 1902 mutex_unlock(&i915->display.dpll.lock); 1903 } 1904 1905 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1906 { 1907 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1908 enum port port = encoder->port; 1909 1910 /* 1911 * FIXME Not sure if the override affects both 1912 * the PLL selection and the CLK_OFF bit. 1913 */ 1914 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1915 } 1916 1917 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1918 { 1919 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1920 enum port port = encoder->port; 1921 enum intel_dpll_id id; 1922 u32 tmp; 1923 1924 tmp = intel_de_read(i915, DPLL_CTRL2); 1925 1926 /* 1927 * FIXME Not sure if the override affects both 1928 * the PLL selection and the CLK_OFF bit. 1929 */ 1930 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1931 return NULL; 1932 1933 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1934 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1935 1936 return intel_get_shared_dpll_by_id(i915, id); 1937 } 1938 1939 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1940 const struct intel_crtc_state *crtc_state) 1941 { 1942 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1943 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1944 enum port port = encoder->port; 1945 1946 if (drm_WARN_ON(&i915->drm, !pll)) 1947 return; 1948 1949 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1950 } 1951 1952 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1953 { 1954 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1955 enum port port = encoder->port; 1956 1957 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1958 } 1959 1960 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1961 { 1962 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1963 enum port port = encoder->port; 1964 1965 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1966 } 1967 1968 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 enum port port = encoder->port; 1972 enum intel_dpll_id id; 1973 u32 tmp; 1974 1975 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1976 1977 switch (tmp & PORT_CLK_SEL_MASK) { 1978 case PORT_CLK_SEL_WRPLL1: 1979 id = DPLL_ID_WRPLL1; 1980 break; 1981 case PORT_CLK_SEL_WRPLL2: 1982 id = DPLL_ID_WRPLL2; 1983 break; 1984 case PORT_CLK_SEL_SPLL: 1985 id = DPLL_ID_SPLL; 1986 break; 1987 case PORT_CLK_SEL_LCPLL_810: 1988 id = DPLL_ID_LCPLL_810; 1989 break; 1990 case PORT_CLK_SEL_LCPLL_1350: 1991 id = DPLL_ID_LCPLL_1350; 1992 break; 1993 case PORT_CLK_SEL_LCPLL_2700: 1994 id = DPLL_ID_LCPLL_2700; 1995 break; 1996 default: 1997 MISSING_CASE(tmp); 1998 fallthrough; 1999 case PORT_CLK_SEL_NONE: 2000 return NULL; 2001 } 2002 2003 return intel_get_shared_dpll_by_id(i915, id); 2004 } 2005 2006 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2007 const struct intel_crtc_state *crtc_state) 2008 { 2009 if (encoder->enable_clock) 2010 encoder->enable_clock(encoder, crtc_state); 2011 } 2012 2013 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2014 { 2015 if (encoder->disable_clock) 2016 encoder->disable_clock(encoder); 2017 } 2018 2019 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2020 { 2021 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2022 u32 port_mask; 2023 bool ddi_clk_needed; 2024 2025 /* 2026 * In case of DP MST, we sanitize the primary encoder only, not the 2027 * virtual ones. 2028 */ 2029 if (encoder->type == INTEL_OUTPUT_DP_MST) 2030 return; 2031 2032 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2033 u8 pipe_mask; 2034 bool is_mst; 2035 2036 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2037 /* 2038 * In the unlikely case that BIOS enables DP in MST mode, just 2039 * warn since our MST HW readout is incomplete. 2040 */ 2041 if (drm_WARN_ON(&i915->drm, is_mst)) 2042 return; 2043 } 2044 2045 port_mask = BIT(encoder->port); 2046 ddi_clk_needed = encoder->base.crtc; 2047 2048 if (encoder->type == INTEL_OUTPUT_DSI) { 2049 struct intel_encoder *other_encoder; 2050 2051 port_mask = intel_dsi_encoder_ports(encoder); 2052 /* 2053 * Sanity check that we haven't incorrectly registered another 2054 * encoder using any of the ports of this DSI encoder. 2055 */ 2056 for_each_intel_encoder(&i915->drm, other_encoder) { 2057 if (other_encoder == encoder) 2058 continue; 2059 2060 if (drm_WARN_ON(&i915->drm, 2061 port_mask & BIT(other_encoder->port))) 2062 return; 2063 } 2064 /* 2065 * For DSI we keep the ddi clocks gated 2066 * except during enable/disable sequence. 2067 */ 2068 ddi_clk_needed = false; 2069 } 2070 2071 if (ddi_clk_needed || !encoder->is_clock_enabled || 2072 !encoder->is_clock_enabled(encoder)) 2073 return; 2074 2075 drm_notice(&i915->drm, 2076 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2077 encoder->base.base.id, encoder->base.name); 2078 2079 encoder->disable_clock(encoder); 2080 } 2081 2082 static void 2083 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2084 const struct intel_crtc_state *crtc_state) 2085 { 2086 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2087 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2088 u32 ln0, ln1, pin_assignment; 2089 u8 width; 2090 2091 if (DISPLAY_VER(dev_priv) >= 14) 2092 return; 2093 2094 if (!intel_encoder_is_tc(&dig_port->base) || 2095 intel_tc_port_in_tbt_alt_mode(dig_port)) 2096 return; 2097 2098 if (DISPLAY_VER(dev_priv) >= 12) { 2099 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2100 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2101 } else { 2102 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2103 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2104 } 2105 2106 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2107 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2108 2109 /* DPPATC */ 2110 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2111 width = crtc_state->lane_count; 2112 2113 switch (pin_assignment) { 2114 case 0x0: 2115 drm_WARN_ON(&dev_priv->drm, 2116 !intel_tc_port_in_legacy_mode(dig_port)); 2117 if (width == 1) { 2118 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2119 } else { 2120 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2121 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2122 } 2123 break; 2124 case 0x1: 2125 if (width == 4) { 2126 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2127 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2128 } 2129 break; 2130 case 0x2: 2131 if (width == 2) { 2132 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2133 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2134 } 2135 break; 2136 case 0x3: 2137 case 0x5: 2138 if (width == 1) { 2139 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2140 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2141 } else { 2142 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2143 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2144 } 2145 break; 2146 case 0x4: 2147 case 0x6: 2148 if (width == 1) { 2149 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2150 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2151 } else { 2152 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2153 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2154 } 2155 break; 2156 default: 2157 MISSING_CASE(pin_assignment); 2158 } 2159 2160 if (DISPLAY_VER(dev_priv) >= 12) { 2161 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2162 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2163 } else { 2164 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2165 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2166 } 2167 } 2168 2169 static enum transcoder 2170 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2171 { 2172 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2173 return crtc_state->mst_master_transcoder; 2174 else 2175 return crtc_state->cpu_transcoder; 2176 } 2177 2178 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2179 const struct intel_crtc_state *crtc_state) 2180 { 2181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2182 2183 if (DISPLAY_VER(dev_priv) >= 12) 2184 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2185 else 2186 return DP_TP_CTL(encoder->port); 2187 } 2188 2189 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2190 const struct intel_crtc_state *crtc_state) 2191 { 2192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2193 2194 if (DISPLAY_VER(dev_priv) >= 12) 2195 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2196 else 2197 return DP_TP_STATUS(encoder->port); 2198 } 2199 2200 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2201 const struct intel_crtc_state *crtc_state, 2202 bool enable) 2203 { 2204 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2205 2206 if (!crtc_state->vrr.enable) 2207 return; 2208 2209 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2210 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2211 drm_dbg_kms(&i915->drm, 2212 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2213 str_enable_disable(enable)); 2214 } 2215 2216 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2217 const struct intel_crtc_state *crtc_state, 2218 bool enable) 2219 { 2220 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2221 2222 if (!crtc_state->fec_enable) 2223 return; 2224 2225 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2226 enable ? DP_FEC_READY : 0) <= 0) 2227 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2228 enable ? "enabled" : "disabled"); 2229 2230 if (enable && 2231 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2232 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2233 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2234 } 2235 2236 static int read_fec_detected_status(struct drm_dp_aux *aux) 2237 { 2238 int ret; 2239 u8 status; 2240 2241 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2242 if (ret < 0) 2243 return ret; 2244 2245 return status; 2246 } 2247 2248 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2249 { 2250 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2251 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2252 int status; 2253 int err; 2254 2255 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2256 status & mask || status < 0, 2257 10000, 200000); 2258 2259 if (!err && status >= 0) 2260 return; 2261 2262 if (err == -ETIMEDOUT) 2263 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2264 str_enabled_disabled(enabled)); 2265 else 2266 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2267 } 2268 2269 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2270 const struct intel_crtc_state *crtc_state, 2271 bool enabled) 2272 { 2273 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2274 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2275 int ret; 2276 2277 if (!crtc_state->fec_enable) 2278 return; 2279 2280 if (enabled) 2281 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2282 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2283 else 2284 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2285 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2286 2287 if (ret) 2288 drm_err(&i915->drm, 2289 "Timeout waiting for FEC live state to get %s\n", 2290 str_enabled_disabled(enabled)); 2291 2292 /* 2293 * At least the Synoptics MST hub doesn't set the detected flag for 2294 * FEC decoding disabling so skip waiting for that. 2295 */ 2296 if (enabled) 2297 wait_for_fec_detected(&intel_dp->aux, enabled); 2298 } 2299 2300 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2301 const struct intel_crtc_state *crtc_state) 2302 { 2303 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2304 2305 if (!crtc_state->fec_enable) 2306 return; 2307 2308 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2309 0, DP_TP_CTL_FEC_ENABLE); 2310 } 2311 2312 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2313 const struct intel_crtc_state *crtc_state) 2314 { 2315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2316 2317 if (!crtc_state->fec_enable) 2318 return; 2319 2320 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2321 DP_TP_CTL_FEC_ENABLE, 0); 2322 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2323 } 2324 2325 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2326 const struct intel_crtc_state *crtc_state) 2327 { 2328 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2329 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2330 2331 if (intel_encoder_is_combo(encoder)) { 2332 enum phy phy = intel_encoder_to_phy(encoder); 2333 bool lane_reversal = 2334 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2335 2336 intel_combo_phy_power_up_lanes(i915, phy, false, 2337 crtc_state->lane_count, 2338 lane_reversal); 2339 } 2340 } 2341 2342 /* 2343 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2344 * platforms. 2345 */ 2346 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2347 { 2348 if (DISPLAY_VER(i915) > 20) 2349 return ~0; 2350 else if (IS_ALDERLAKE_P(i915)) 2351 return BIT(PIPE_A) | BIT(PIPE_B); 2352 else 2353 return BIT(PIPE_A); 2354 } 2355 2356 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2357 struct intel_crtc_state *pipe_config) 2358 { 2359 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2361 enum pipe pipe = crtc->pipe; 2362 u32 dss1; 2363 2364 if (!HAS_MSO(i915)) 2365 return; 2366 2367 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2368 2369 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2370 if (!pipe_config->splitter.enable) 2371 return; 2372 2373 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2374 pipe_config->splitter.enable = false; 2375 return; 2376 } 2377 2378 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2379 default: 2380 drm_WARN(&i915->drm, true, 2381 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2382 fallthrough; 2383 case SPLITTER_CONFIGURATION_2_SEGMENT: 2384 pipe_config->splitter.link_count = 2; 2385 break; 2386 case SPLITTER_CONFIGURATION_4_SEGMENT: 2387 pipe_config->splitter.link_count = 4; 2388 break; 2389 } 2390 2391 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2392 } 2393 2394 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2395 { 2396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2397 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2398 enum pipe pipe = crtc->pipe; 2399 u32 dss1 = 0; 2400 2401 if (!HAS_MSO(i915)) 2402 return; 2403 2404 if (crtc_state->splitter.enable) { 2405 dss1 |= SPLITTER_ENABLE; 2406 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2407 if (crtc_state->splitter.link_count == 2) 2408 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2409 else 2410 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2411 } 2412 2413 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2414 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2415 OVERLAP_PIXELS_MASK, dss1); 2416 } 2417 2418 static u8 mtl_get_port_width(u8 lane_count) 2419 { 2420 switch (lane_count) { 2421 case 1: 2422 return 0; 2423 case 2: 2424 return 1; 2425 case 3: 2426 return 4; 2427 case 4: 2428 return 3; 2429 default: 2430 MISSING_CASE(lane_count); 2431 return 4; 2432 } 2433 } 2434 2435 static void 2436 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2437 { 2438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2439 enum port port = encoder->port; 2440 i915_reg_t reg; 2441 u32 set_bits, wait_bits; 2442 2443 if (DISPLAY_VER(dev_priv) >= 20) { 2444 reg = DDI_BUF_CTL(port); 2445 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2446 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2447 } else { 2448 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2449 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2450 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2451 } 2452 2453 intel_de_rmw(dev_priv, reg, 0, set_bits); 2454 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2455 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2456 port_name(port)); 2457 } 2458 } 2459 2460 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2461 const struct intel_crtc_state *crtc_state) 2462 { 2463 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2464 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2465 enum port port = encoder->port; 2466 u32 val; 2467 2468 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2469 val &= ~XELPDP_PORT_WIDTH_MASK; 2470 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2471 2472 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2473 if (intel_dp_is_uhbr(crtc_state)) 2474 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2475 else 2476 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2477 2478 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2479 val |= XELPDP_PORT_REVERSAL; 2480 2481 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2482 } 2483 2484 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2485 { 2486 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2487 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2488 u32 val; 2489 2490 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2491 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2492 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2493 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2494 } 2495 2496 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2497 struct intel_encoder *encoder, 2498 const struct intel_crtc_state *crtc_state, 2499 const struct drm_connector_state *conn_state) 2500 { 2501 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2502 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2503 2504 intel_dp_set_link_params(intel_dp, 2505 crtc_state->port_clock, 2506 crtc_state->lane_count); 2507 2508 /* 2509 * We only configure what the register value will be here. Actual 2510 * enabling happens during link training farther down. 2511 */ 2512 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2513 2514 /* 2515 * 1. Enable Power Wells 2516 * 2517 * This was handled at the beginning of intel_atomic_commit_tail(), 2518 * before we called down into this function. 2519 */ 2520 2521 /* 2. PMdemand was already set */ 2522 2523 /* 3. Select Thunderbolt */ 2524 mtl_port_buf_ctl_io_selection(encoder); 2525 2526 /* 4. Enable Panel Power if PPS is required */ 2527 intel_pps_on(intel_dp); 2528 2529 /* 5. Enable the port PLL */ 2530 intel_ddi_enable_clock(encoder, crtc_state); 2531 2532 /* 2533 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2534 * Transcoder. 2535 */ 2536 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2537 2538 /* 2539 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2540 */ 2541 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2542 2543 /* 2544 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2545 * Transport Select 2546 */ 2547 intel_ddi_config_transcoder_func(encoder, crtc_state); 2548 2549 /* 2550 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2551 */ 2552 intel_ddi_mso_configure(crtc_state); 2553 2554 if (!is_mst) 2555 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2556 2557 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2558 if (!is_mst) 2559 intel_dp_sink_enable_decompression(state, 2560 to_intel_connector(conn_state->connector), 2561 crtc_state); 2562 2563 /* 2564 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2565 * in the FEC_CONFIGURATION register to 1 before initiating link 2566 * training 2567 */ 2568 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2569 2570 intel_dp_check_frl_training(intel_dp); 2571 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2572 2573 /* 2574 * 6. The rest of the below are substeps under the bspec's "Enable and 2575 * Train Display Port" step. Note that steps that are specific to 2576 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2577 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2578 * us when active_mst_links==0, so any steps designated for "single 2579 * stream or multi-stream master transcoder" can just be performed 2580 * unconditionally here. 2581 * 2582 * mtl_ddi_prepare_link_retrain() that is called by 2583 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2584 * 6.i and 6.j 2585 * 2586 * 6.k Follow DisplayPort specification training sequence (see notes for 2587 * failure handling) 2588 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2589 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2590 * (timeout after 800 us) 2591 */ 2592 intel_dp_start_link_train(intel_dp, crtc_state); 2593 2594 /* 6.n Set DP_TP_CTL link training to Normal */ 2595 if (!is_trans_port_sync_mode(crtc_state)) 2596 intel_dp_stop_link_train(intel_dp, crtc_state); 2597 2598 /* 6.o Configure and enable FEC if needed */ 2599 intel_ddi_enable_fec(encoder, crtc_state); 2600 2601 if (!is_mst) 2602 intel_dsc_dp_pps_write(encoder, crtc_state); 2603 } 2604 2605 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2606 struct intel_encoder *encoder, 2607 const struct intel_crtc_state *crtc_state, 2608 const struct drm_connector_state *conn_state) 2609 { 2610 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2612 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2613 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2614 2615 intel_dp_set_link_params(intel_dp, 2616 crtc_state->port_clock, 2617 crtc_state->lane_count); 2618 2619 /* 2620 * We only configure what the register value will be here. Actual 2621 * enabling happens during link training farther down. 2622 */ 2623 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2624 2625 /* 2626 * 1. Enable Power Wells 2627 * 2628 * This was handled at the beginning of intel_atomic_commit_tail(), 2629 * before we called down into this function. 2630 */ 2631 2632 /* 2. Enable Panel Power if PPS is required */ 2633 intel_pps_on(intel_dp); 2634 2635 /* 2636 * 3. For non-TBT Type-C ports, set FIA lane count 2637 * (DFLEXDPSP.DPX4TXLATC) 2638 * 2639 * This was done before tgl_ddi_pre_enable_dp by 2640 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2641 */ 2642 2643 /* 2644 * 4. Enable the port PLL. 2645 * 2646 * The PLL enabling itself was already done before this function by 2647 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2648 * configure the PLL to port mapping here. 2649 */ 2650 intel_ddi_enable_clock(encoder, crtc_state); 2651 2652 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2653 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2654 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2655 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2656 dig_port->ddi_io_power_domain); 2657 } 2658 2659 /* 6. Program DP_MODE */ 2660 icl_program_mg_dp_mode(dig_port, crtc_state); 2661 2662 /* 2663 * 7. The rest of the below are substeps under the bspec's "Enable and 2664 * Train Display Port" step. Note that steps that are specific to 2665 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2666 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2667 * us when active_mst_links==0, so any steps designated for "single 2668 * stream or multi-stream master transcoder" can just be performed 2669 * unconditionally here. 2670 */ 2671 2672 /* 2673 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2674 * Transcoder. 2675 */ 2676 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2677 2678 if (HAS_DP20(dev_priv)) 2679 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2680 2681 /* 2682 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2683 * Transport Select 2684 */ 2685 intel_ddi_config_transcoder_func(encoder, crtc_state); 2686 2687 /* 2688 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2689 * selected 2690 * 2691 * This will be handled by the intel_dp_start_link_train() farther 2692 * down this function. 2693 */ 2694 2695 /* 7.e Configure voltage swing and related IO settings */ 2696 encoder->set_signal_levels(encoder, crtc_state); 2697 2698 /* 2699 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2700 * the used lanes of the DDI. 2701 */ 2702 intel_ddi_power_up_lanes(encoder, crtc_state); 2703 2704 /* 2705 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2706 */ 2707 intel_ddi_mso_configure(crtc_state); 2708 2709 if (!is_mst) 2710 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2711 2712 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2713 if (!is_mst) 2714 intel_dp_sink_enable_decompression(state, 2715 to_intel_connector(conn_state->connector), 2716 crtc_state); 2717 /* 2718 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2719 * in the FEC_CONFIGURATION register to 1 before initiating link 2720 * training 2721 */ 2722 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2723 2724 intel_dp_check_frl_training(intel_dp); 2725 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2726 2727 /* 2728 * 7.i Follow DisplayPort specification training sequence (see notes for 2729 * failure handling) 2730 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2731 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2732 * (timeout after 800 us) 2733 */ 2734 intel_dp_start_link_train(intel_dp, crtc_state); 2735 2736 /* 7.k Set DP_TP_CTL link training to Normal */ 2737 if (!is_trans_port_sync_mode(crtc_state)) 2738 intel_dp_stop_link_train(intel_dp, crtc_state); 2739 2740 /* 7.l Configure and enable FEC if needed */ 2741 intel_ddi_enable_fec(encoder, crtc_state); 2742 2743 if (!is_mst) 2744 intel_dsc_dp_pps_write(encoder, crtc_state); 2745 } 2746 2747 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2748 struct intel_encoder *encoder, 2749 const struct intel_crtc_state *crtc_state, 2750 const struct drm_connector_state *conn_state) 2751 { 2752 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2753 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2754 enum port port = encoder->port; 2755 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2756 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2757 2758 if (DISPLAY_VER(dev_priv) < 11) 2759 drm_WARN_ON(&dev_priv->drm, 2760 is_mst && (port == PORT_A || port == PORT_E)); 2761 else 2762 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2763 2764 intel_dp_set_link_params(intel_dp, 2765 crtc_state->port_clock, 2766 crtc_state->lane_count); 2767 2768 /* 2769 * We only configure what the register value will be here. Actual 2770 * enabling happens during link training farther down. 2771 */ 2772 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2773 2774 intel_pps_on(intel_dp); 2775 2776 intel_ddi_enable_clock(encoder, crtc_state); 2777 2778 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2779 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2780 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2781 dig_port->ddi_io_power_domain); 2782 } 2783 2784 icl_program_mg_dp_mode(dig_port, crtc_state); 2785 2786 if (has_buf_trans_select(dev_priv)) 2787 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2788 2789 encoder->set_signal_levels(encoder, crtc_state); 2790 2791 intel_ddi_power_up_lanes(encoder, crtc_state); 2792 2793 if (!is_mst) 2794 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2795 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2796 if (!is_mst) 2797 intel_dp_sink_enable_decompression(state, 2798 to_intel_connector(conn_state->connector), 2799 crtc_state); 2800 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2801 intel_dp_start_link_train(intel_dp, crtc_state); 2802 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2803 !is_trans_port_sync_mode(crtc_state)) 2804 intel_dp_stop_link_train(intel_dp, crtc_state); 2805 2806 intel_ddi_enable_fec(encoder, crtc_state); 2807 2808 if (!is_mst) { 2809 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2810 intel_dsc_dp_pps_write(encoder, crtc_state); 2811 } 2812 } 2813 2814 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2815 struct intel_encoder *encoder, 2816 const struct intel_crtc_state *crtc_state, 2817 const struct drm_connector_state *conn_state) 2818 { 2819 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2820 2821 if (HAS_DP20(dev_priv)) 2822 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2823 crtc_state); 2824 2825 /* Panel replay has to be enabled in sink dpcd before link training. */ 2826 if (crtc_state->has_panel_replay) 2827 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2828 2829 if (DISPLAY_VER(dev_priv) >= 14) 2830 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2831 else if (DISPLAY_VER(dev_priv) >= 12) 2832 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2833 else 2834 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2835 2836 /* MST will call a setting of MSA after an allocating of Virtual Channel 2837 * from MST encoder pre_enable callback. 2838 */ 2839 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2840 intel_ddi_set_dp_msa(crtc_state, conn_state); 2841 } 2842 2843 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2844 struct intel_encoder *encoder, 2845 const struct intel_crtc_state *crtc_state, 2846 const struct drm_connector_state *conn_state) 2847 { 2848 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2849 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2851 2852 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2853 intel_ddi_enable_clock(encoder, crtc_state); 2854 2855 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2856 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2857 dig_port->ddi_io_power_domain); 2858 2859 icl_program_mg_dp_mode(dig_port, crtc_state); 2860 2861 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2862 2863 dig_port->set_infoframes(encoder, 2864 crtc_state->has_infoframe, 2865 crtc_state, conn_state); 2866 } 2867 2868 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2869 struct intel_encoder *encoder, 2870 const struct intel_crtc_state *crtc_state, 2871 const struct drm_connector_state *conn_state) 2872 { 2873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2875 enum pipe pipe = crtc->pipe; 2876 2877 /* 2878 * When called from DP MST code: 2879 * - conn_state will be NULL 2880 * - encoder will be the main encoder (ie. mst->primary) 2881 * - the main connector associated with this port 2882 * won't be active or linked to a crtc 2883 * - crtc_state will be the state of the first stream to 2884 * be activated on this port, and it may not be the same 2885 * stream that will be deactivated last, but each stream 2886 * should have a state that is identical when it comes to 2887 * the DP link parameteres 2888 */ 2889 2890 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2891 2892 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2893 2894 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2895 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2896 conn_state); 2897 } else { 2898 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2899 2900 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2901 conn_state); 2902 2903 /* FIXME precompute everything properly */ 2904 /* FIXME how do we turn infoframes off again? */ 2905 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2906 dig_port->set_infoframes(encoder, 2907 crtc_state->has_infoframe, 2908 crtc_state, conn_state); 2909 } 2910 } 2911 2912 static void 2913 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2914 { 2915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2916 enum port port = encoder->port; 2917 i915_reg_t reg; 2918 u32 clr_bits, wait_bits; 2919 2920 if (DISPLAY_VER(dev_priv) >= 20) { 2921 reg = DDI_BUF_CTL(port); 2922 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2923 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2924 } else { 2925 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2926 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2927 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2928 } 2929 2930 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2931 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2932 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2933 port_name(port)); 2934 } 2935 2936 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2937 const struct intel_crtc_state *crtc_state) 2938 { 2939 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2940 enum port port = encoder->port; 2941 u32 val; 2942 2943 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2944 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2945 if (val & DDI_BUF_CTL_ENABLE) { 2946 val &= ~DDI_BUF_CTL_ENABLE; 2947 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2948 2949 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2950 mtl_wait_ddi_buf_idle(dev_priv, port); 2951 } 2952 2953 /* 3.d Disable D2D Link */ 2954 mtl_ddi_disable_d2d_link(encoder); 2955 2956 /* 3.e Disable DP_TP_CTL */ 2957 if (intel_crtc_has_dp_encoder(crtc_state)) { 2958 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2959 DP_TP_CTL_ENABLE, 0); 2960 } 2961 } 2962 2963 static void disable_ddi_buf(struct intel_encoder *encoder, 2964 const struct intel_crtc_state *crtc_state) 2965 { 2966 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2967 enum port port = encoder->port; 2968 bool wait = false; 2969 u32 val; 2970 2971 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2972 if (val & DDI_BUF_CTL_ENABLE) { 2973 val &= ~DDI_BUF_CTL_ENABLE; 2974 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2975 wait = true; 2976 } 2977 2978 if (intel_crtc_has_dp_encoder(crtc_state)) 2979 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2980 DP_TP_CTL_ENABLE, 0); 2981 2982 intel_ddi_disable_fec(encoder, crtc_state); 2983 2984 if (wait) 2985 intel_wait_ddi_buf_idle(dev_priv, port); 2986 } 2987 2988 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2989 const struct intel_crtc_state *crtc_state) 2990 { 2991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2992 2993 if (DISPLAY_VER(dev_priv) >= 14) { 2994 mtl_disable_ddi_buf(encoder, crtc_state); 2995 2996 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2997 intel_ddi_disable_fec(encoder, crtc_state); 2998 } else { 2999 disable_ddi_buf(encoder, crtc_state); 3000 } 3001 3002 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3003 } 3004 3005 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3006 struct intel_encoder *encoder, 3007 const struct intel_crtc_state *old_crtc_state, 3008 const struct drm_connector_state *old_conn_state) 3009 { 3010 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3011 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3012 struct intel_dp *intel_dp = &dig_port->dp; 3013 intel_wakeref_t wakeref; 3014 bool is_mst = intel_crtc_has_type(old_crtc_state, 3015 INTEL_OUTPUT_DP_MST); 3016 3017 if (!is_mst) 3018 intel_dp_set_infoframes(encoder, false, 3019 old_crtc_state, old_conn_state); 3020 3021 /* 3022 * Power down sink before disabling the port, otherwise we end 3023 * up getting interrupts from the sink on detecting link loss. 3024 */ 3025 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3026 3027 if (DISPLAY_VER(dev_priv) >= 12) { 3028 if (is_mst) { 3029 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3030 3031 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 3032 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3033 0); 3034 } 3035 } else { 3036 if (!is_mst) 3037 intel_ddi_disable_transcoder_clock(old_crtc_state); 3038 } 3039 3040 intel_disable_ddi_buf(encoder, old_crtc_state); 3041 3042 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3043 3044 /* 3045 * From TGL spec: "If single stream or multi-stream master transcoder: 3046 * Configure Transcoder Clock select to direct no clock to the 3047 * transcoder" 3048 */ 3049 if (DISPLAY_VER(dev_priv) >= 12) 3050 intel_ddi_disable_transcoder_clock(old_crtc_state); 3051 3052 intel_pps_vdd_on(intel_dp); 3053 intel_pps_off(intel_dp); 3054 3055 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3056 3057 if (wakeref) 3058 intel_display_power_put(dev_priv, 3059 dig_port->ddi_io_power_domain, 3060 wakeref); 3061 3062 intel_ddi_disable_clock(encoder); 3063 3064 /* De-select Thunderbolt */ 3065 if (DISPLAY_VER(dev_priv) >= 14) 3066 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3067 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3068 } 3069 3070 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3071 struct intel_encoder *encoder, 3072 const struct intel_crtc_state *old_crtc_state, 3073 const struct drm_connector_state *old_conn_state) 3074 { 3075 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3076 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3077 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3078 intel_wakeref_t wakeref; 3079 3080 dig_port->set_infoframes(encoder, false, 3081 old_crtc_state, old_conn_state); 3082 3083 if (DISPLAY_VER(dev_priv) < 12) 3084 intel_ddi_disable_transcoder_clock(old_crtc_state); 3085 3086 intel_disable_ddi_buf(encoder, old_crtc_state); 3087 3088 if (DISPLAY_VER(dev_priv) >= 12) 3089 intel_ddi_disable_transcoder_clock(old_crtc_state); 3090 3091 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3092 if (wakeref) 3093 intel_display_power_put(dev_priv, 3094 dig_port->ddi_io_power_domain, 3095 wakeref); 3096 3097 intel_ddi_disable_clock(encoder); 3098 3099 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3100 } 3101 3102 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3103 struct intel_encoder *encoder, 3104 const struct intel_crtc_state *old_crtc_state, 3105 const struct drm_connector_state *old_conn_state) 3106 { 3107 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3108 struct intel_crtc *pipe_crtc; 3109 3110 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3111 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3112 const struct intel_crtc_state *old_pipe_crtc_state = 3113 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3114 3115 intel_crtc_vblank_off(old_pipe_crtc_state); 3116 } 3117 3118 intel_disable_transcoder(old_crtc_state); 3119 3120 intel_ddi_disable_transcoder_func(old_crtc_state); 3121 3122 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3123 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3124 const struct intel_crtc_state *old_pipe_crtc_state = 3125 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3126 3127 intel_dsc_disable(old_pipe_crtc_state); 3128 3129 if (DISPLAY_VER(dev_priv) >= 9) 3130 skl_scaler_disable(old_pipe_crtc_state); 3131 else 3132 ilk_pfit_disable(old_pipe_crtc_state); 3133 } 3134 } 3135 3136 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3137 struct intel_encoder *encoder, 3138 const struct intel_crtc_state *old_crtc_state, 3139 const struct drm_connector_state *old_conn_state) 3140 { 3141 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3142 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3143 old_conn_state); 3144 3145 /* 3146 * When called from DP MST code: 3147 * - old_conn_state will be NULL 3148 * - encoder will be the main encoder (ie. mst->primary) 3149 * - the main connector associated with this port 3150 * won't be active or linked to a crtc 3151 * - old_crtc_state will be the state of the last stream to 3152 * be deactivated on this port, and it may not be the same 3153 * stream that was activated last, but each stream 3154 * should have a state that is identical when it comes to 3155 * the DP link parameteres 3156 */ 3157 3158 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3159 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3160 old_conn_state); 3161 else 3162 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3163 old_conn_state); 3164 } 3165 3166 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3167 struct intel_encoder *encoder, 3168 const struct intel_crtc_state *old_crtc_state, 3169 const struct drm_connector_state *old_conn_state) 3170 { 3171 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3172 3173 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3174 3175 if (intel_encoder_is_tc(encoder)) 3176 intel_tc_port_put_link(dig_port); 3177 } 3178 3179 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3180 struct intel_encoder *encoder, 3181 const struct intel_crtc_state *crtc_state) 3182 { 3183 const struct drm_connector_state *conn_state; 3184 struct drm_connector *conn; 3185 int i; 3186 3187 if (!crtc_state->sync_mode_slaves_mask) 3188 return; 3189 3190 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3191 struct intel_encoder *slave_encoder = 3192 to_intel_encoder(conn_state->best_encoder); 3193 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3194 const struct intel_crtc_state *slave_crtc_state; 3195 3196 if (!slave_crtc) 3197 continue; 3198 3199 slave_crtc_state = 3200 intel_atomic_get_new_crtc_state(state, slave_crtc); 3201 3202 if (slave_crtc_state->master_transcoder != 3203 crtc_state->cpu_transcoder) 3204 continue; 3205 3206 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3207 slave_crtc_state); 3208 } 3209 3210 usleep_range(200, 400); 3211 3212 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3213 crtc_state); 3214 } 3215 3216 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3217 struct intel_encoder *encoder, 3218 const struct intel_crtc_state *crtc_state, 3219 const struct drm_connector_state *conn_state) 3220 { 3221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3222 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3223 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3224 enum port port = encoder->port; 3225 3226 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3227 intel_dp_stop_link_train(intel_dp, crtc_state); 3228 3229 drm_connector_update_privacy_screen(conn_state); 3230 intel_edp_backlight_on(crtc_state, conn_state); 3231 3232 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3233 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3234 3235 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3236 } 3237 3238 /* FIXME bad home for this function */ 3239 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3240 enum transcoder cpu_transcoder) 3241 { 3242 return DISPLAY_VER(i915) >= 14 ? 3243 MTL_CHICKEN_TRANS(cpu_transcoder) : 3244 CHICKEN_TRANS(cpu_transcoder); 3245 } 3246 3247 static i915_reg_t 3248 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3249 enum port port) 3250 { 3251 static const enum transcoder trans[] = { 3252 [PORT_A] = TRANSCODER_EDP, 3253 [PORT_B] = TRANSCODER_A, 3254 [PORT_C] = TRANSCODER_B, 3255 [PORT_D] = TRANSCODER_C, 3256 [PORT_E] = TRANSCODER_A, 3257 }; 3258 3259 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3260 3261 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3262 port = PORT_A; 3263 3264 return CHICKEN_TRANS(trans[port]); 3265 } 3266 3267 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3268 struct intel_encoder *encoder, 3269 const struct intel_crtc_state *crtc_state, 3270 const struct drm_connector_state *conn_state) 3271 { 3272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3273 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3274 struct drm_connector *connector = conn_state->connector; 3275 enum port port = encoder->port; 3276 u32 buf_ctl; 3277 3278 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3279 crtc_state->hdmi_high_tmds_clock_ratio, 3280 crtc_state->hdmi_scrambling)) 3281 drm_dbg_kms(&dev_priv->drm, 3282 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3283 connector->base.id, connector->name); 3284 3285 if (has_buf_trans_select(dev_priv)) 3286 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3287 3288 /* e. Enable D2D Link for C10/C20 Phy */ 3289 if (DISPLAY_VER(dev_priv) >= 14) 3290 mtl_ddi_enable_d2d(encoder); 3291 3292 encoder->set_signal_levels(encoder, crtc_state); 3293 3294 /* Display WA #1143: skl,kbl,cfl */ 3295 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3296 /* 3297 * For some reason these chicken bits have been 3298 * stuffed into a transcoder register, event though 3299 * the bits affect a specific DDI port rather than 3300 * a specific transcoder. 3301 */ 3302 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3303 u32 val; 3304 3305 val = intel_de_read(dev_priv, reg); 3306 3307 if (port == PORT_E) 3308 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3309 DDIE_TRAINING_OVERRIDE_VALUE; 3310 else 3311 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3312 DDI_TRAINING_OVERRIDE_VALUE; 3313 3314 intel_de_write(dev_priv, reg, val); 3315 intel_de_posting_read(dev_priv, reg); 3316 3317 udelay(1); 3318 3319 if (port == PORT_E) 3320 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3321 DDIE_TRAINING_OVERRIDE_VALUE); 3322 else 3323 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3324 DDI_TRAINING_OVERRIDE_VALUE); 3325 3326 intel_de_write(dev_priv, reg, val); 3327 } 3328 3329 intel_ddi_power_up_lanes(encoder, crtc_state); 3330 3331 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3332 * are ignored so nothing special needs to be done besides 3333 * enabling the port. 3334 * 3335 * On ADL_P the PHY link rate and lane count must be programmed but 3336 * these are both 0 for HDMI. 3337 * 3338 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3339 * is filled with lane count, already set in the crtc_state. 3340 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3341 */ 3342 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3343 if (DISPLAY_VER(dev_priv) >= 14) { 3344 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3345 u32 port_buf = 0; 3346 3347 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3348 3349 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3350 port_buf |= XELPDP_PORT_REVERSAL; 3351 3352 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3353 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3354 3355 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3356 3357 if (DISPLAY_VER(dev_priv) >= 20) 3358 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3359 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3360 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3361 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3362 } 3363 3364 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3365 3366 intel_wait_ddi_buf_active(encoder); 3367 } 3368 3369 static void intel_enable_ddi(struct intel_atomic_state *state, 3370 struct intel_encoder *encoder, 3371 const struct intel_crtc_state *crtc_state, 3372 const struct drm_connector_state *conn_state) 3373 { 3374 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3375 struct intel_crtc *pipe_crtc; 3376 3377 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3378 3379 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3380 intel_audio_sdp_split_update(crtc_state); 3381 3382 intel_enable_transcoder(crtc_state); 3383 3384 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3385 3386 for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, 3387 intel_crtc_joined_pipe_mask(crtc_state)) { 3388 const struct intel_crtc_state *pipe_crtc_state = 3389 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3390 3391 intel_crtc_vblank_on(pipe_crtc_state); 3392 } 3393 3394 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3395 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3396 else 3397 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3398 3399 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3400 3401 } 3402 3403 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3404 struct intel_encoder *encoder, 3405 const struct intel_crtc_state *old_crtc_state, 3406 const struct drm_connector_state *old_conn_state) 3407 { 3408 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3409 struct intel_connector *connector = 3410 to_intel_connector(old_conn_state->connector); 3411 3412 intel_dp->link_trained = false; 3413 3414 intel_psr_disable(intel_dp, old_crtc_state); 3415 intel_edp_backlight_off(old_conn_state); 3416 /* Disable the decompression in DP Sink */ 3417 intel_dp_sink_disable_decompression(state, 3418 connector, old_crtc_state); 3419 /* Disable Ignore_MSA bit in DP Sink */ 3420 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3421 false); 3422 } 3423 3424 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3425 struct intel_encoder *encoder, 3426 const struct intel_crtc_state *old_crtc_state, 3427 const struct drm_connector_state *old_conn_state) 3428 { 3429 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3430 struct drm_connector *connector = old_conn_state->connector; 3431 3432 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3433 false, false)) 3434 drm_dbg_kms(&i915->drm, 3435 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3436 connector->base.id, connector->name); 3437 } 3438 3439 static void intel_disable_ddi(struct intel_atomic_state *state, 3440 struct intel_encoder *encoder, 3441 const struct intel_crtc_state *old_crtc_state, 3442 const struct drm_connector_state *old_conn_state) 3443 { 3444 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3445 3446 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3447 3448 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3449 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3450 old_conn_state); 3451 else 3452 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3453 old_conn_state); 3454 } 3455 3456 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3457 struct intel_encoder *encoder, 3458 const struct intel_crtc_state *crtc_state, 3459 const struct drm_connector_state *conn_state) 3460 { 3461 intel_ddi_set_dp_msa(crtc_state, conn_state); 3462 3463 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3464 3465 intel_backlight_update(state, encoder, crtc_state, conn_state); 3466 drm_connector_update_privacy_screen(conn_state); 3467 } 3468 3469 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3470 struct intel_encoder *encoder, 3471 const struct intel_crtc_state *crtc_state, 3472 const struct drm_connector_state *conn_state) 3473 { 3474 3475 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3476 !intel_encoder_is_mst(encoder)) 3477 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3478 conn_state); 3479 3480 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3481 } 3482 3483 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3484 struct intel_encoder *encoder, 3485 struct intel_crtc *crtc) 3486 { 3487 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3488 const struct intel_crtc_state *crtc_state = 3489 intel_atomic_get_new_crtc_state(state, crtc); 3490 struct intel_crtc *pipe_crtc; 3491 3492 /* FIXME: Add MTL pll_mgr */ 3493 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3494 return; 3495 3496 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3497 intel_crtc_joined_pipe_mask(crtc_state)) 3498 intel_update_active_dpll(state, pipe_crtc, encoder); 3499 } 3500 3501 static void 3502 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3503 struct intel_encoder *encoder, 3504 const struct intel_crtc_state *crtc_state, 3505 const struct drm_connector_state *conn_state) 3506 { 3507 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3508 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3509 bool is_tc_port = intel_encoder_is_tc(encoder); 3510 3511 if (is_tc_port) { 3512 struct intel_crtc *master_crtc = 3513 to_intel_crtc(crtc_state->uapi.crtc); 3514 3515 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3516 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3517 } 3518 3519 main_link_aux_power_domain_get(dig_port, crtc_state); 3520 3521 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3522 /* 3523 * Program the lane count for static/dynamic connections on 3524 * Type-C ports. Skip this step for TBT. 3525 */ 3526 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3527 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3528 bxt_dpio_phy_set_lane_optim_mask(encoder, 3529 crtc_state->lane_lat_optim_mask); 3530 } 3531 3532 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3533 { 3534 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3535 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3536 int ln; 3537 3538 for (ln = 0; ln < 2; ln++) 3539 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3540 } 3541 3542 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3543 const struct intel_crtc_state *crtc_state) 3544 { 3545 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3546 struct intel_encoder *encoder = &dig_port->base; 3547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3548 enum port port = encoder->port; 3549 u32 dp_tp_ctl; 3550 3551 /* 3552 * TODO: To train with only a different voltage swing entry is not 3553 * necessary disable and enable port 3554 */ 3555 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3556 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3557 mtl_disable_ddi_buf(encoder, crtc_state); 3558 3559 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3560 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3561 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3562 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3563 } else { 3564 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3565 if (crtc_state->enhanced_framing) 3566 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3567 } 3568 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3569 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3570 3571 /* 6.f Enable D2D Link */ 3572 mtl_ddi_enable_d2d(encoder); 3573 3574 /* 6.g Configure voltage swing and related IO settings */ 3575 encoder->set_signal_levels(encoder, crtc_state); 3576 3577 /* 6.h Configure PORT_BUF_CTL1 */ 3578 mtl_port_buf_ctl_program(encoder, crtc_state); 3579 3580 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3581 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3582 if (DISPLAY_VER(dev_priv) >= 20) 3583 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3584 3585 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3586 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3587 3588 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3589 intel_wait_ddi_buf_active(encoder); 3590 } 3591 3592 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3593 const struct intel_crtc_state *crtc_state) 3594 { 3595 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3596 struct intel_encoder *encoder = &dig_port->base; 3597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3598 enum port port = encoder->port; 3599 u32 dp_tp_ctl, ddi_buf_ctl; 3600 bool wait = false; 3601 3602 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3603 3604 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3605 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3606 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3607 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3608 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3609 wait = true; 3610 } 3611 3612 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3613 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3614 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3615 3616 if (wait) 3617 intel_wait_ddi_buf_idle(dev_priv, port); 3618 } 3619 3620 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3621 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3622 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3623 } else { 3624 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3625 if (crtc_state->enhanced_framing) 3626 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3627 } 3628 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3629 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3630 3631 if (IS_ALDERLAKE_P(dev_priv) && 3632 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3633 adlp_tbt_to_dp_alt_switch_wa(encoder); 3634 3635 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3636 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3637 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3638 3639 intel_wait_ddi_buf_active(encoder); 3640 } 3641 3642 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3643 const struct intel_crtc_state *crtc_state, 3644 u8 dp_train_pat) 3645 { 3646 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3648 u32 temp; 3649 3650 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3651 3652 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3653 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3654 case DP_TRAINING_PATTERN_DISABLE: 3655 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3656 break; 3657 case DP_TRAINING_PATTERN_1: 3658 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3659 break; 3660 case DP_TRAINING_PATTERN_2: 3661 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3662 break; 3663 case DP_TRAINING_PATTERN_3: 3664 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3665 break; 3666 case DP_TRAINING_PATTERN_4: 3667 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3668 break; 3669 } 3670 3671 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3672 } 3673 3674 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3675 const struct intel_crtc_state *crtc_state) 3676 { 3677 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3678 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3679 enum port port = encoder->port; 3680 3681 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3682 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3683 3684 /* 3685 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3686 * reason we need to set idle transmission mode is to work around a HW 3687 * issue where we enable the pipe while not in idle link-training mode. 3688 * In this case there is requirement to wait for a minimum number of 3689 * idle patterns to be sent. 3690 */ 3691 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3692 return; 3693 3694 if (intel_de_wait_for_set(dev_priv, 3695 dp_tp_status_reg(encoder, crtc_state), 3696 DP_TP_STATUS_IDLE_DONE, 2)) 3697 drm_err(&dev_priv->drm, 3698 "Timed out waiting for DP idle patterns\n"); 3699 } 3700 3701 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3702 enum transcoder cpu_transcoder) 3703 { 3704 if (cpu_transcoder == TRANSCODER_EDP) 3705 return false; 3706 3707 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3708 return false; 3709 3710 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3711 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3712 } 3713 3714 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3715 { 3716 if (crtc_state->port_clock > 594000) 3717 return 2; 3718 else 3719 return 0; 3720 } 3721 3722 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3723 { 3724 if (crtc_state->port_clock > 594000) 3725 return 3; 3726 else 3727 return 0; 3728 } 3729 3730 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3731 { 3732 if (crtc_state->port_clock > 594000) 3733 return 1; 3734 else 3735 return 0; 3736 } 3737 3738 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3739 { 3740 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3741 3742 if (DISPLAY_VER(dev_priv) >= 14) 3743 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3744 else if (DISPLAY_VER(dev_priv) >= 12) 3745 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3746 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3747 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3748 else if (DISPLAY_VER(dev_priv) >= 11) 3749 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3750 } 3751 3752 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3753 enum transcoder cpu_transcoder) 3754 { 3755 u32 master_select; 3756 3757 if (DISPLAY_VER(dev_priv) >= 11) { 3758 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3759 3760 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3761 return INVALID_TRANSCODER; 3762 3763 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3764 } else { 3765 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3766 3767 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3768 return INVALID_TRANSCODER; 3769 3770 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3771 } 3772 3773 if (master_select == 0) 3774 return TRANSCODER_EDP; 3775 else 3776 return master_select - 1; 3777 } 3778 3779 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3780 { 3781 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3782 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3783 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3784 enum transcoder cpu_transcoder; 3785 3786 crtc_state->master_transcoder = 3787 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3788 3789 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3790 enum intel_display_power_domain power_domain; 3791 intel_wakeref_t trans_wakeref; 3792 3793 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3794 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3795 power_domain); 3796 3797 if (!trans_wakeref) 3798 continue; 3799 3800 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3801 crtc_state->cpu_transcoder) 3802 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3803 3804 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3805 } 3806 3807 drm_WARN_ON(&dev_priv->drm, 3808 crtc_state->master_transcoder != INVALID_TRANSCODER && 3809 crtc_state->sync_mode_slaves_mask); 3810 } 3811 3812 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3813 struct intel_crtc_state *pipe_config) 3814 { 3815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3816 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3817 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3818 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3819 u32 temp, flags = 0; 3820 3821 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3822 if (temp & TRANS_DDI_PHSYNC) 3823 flags |= DRM_MODE_FLAG_PHSYNC; 3824 else 3825 flags |= DRM_MODE_FLAG_NHSYNC; 3826 if (temp & TRANS_DDI_PVSYNC) 3827 flags |= DRM_MODE_FLAG_PVSYNC; 3828 else 3829 flags |= DRM_MODE_FLAG_NVSYNC; 3830 3831 pipe_config->hw.adjusted_mode.flags |= flags; 3832 3833 switch (temp & TRANS_DDI_BPC_MASK) { 3834 case TRANS_DDI_BPC_6: 3835 pipe_config->pipe_bpp = 18; 3836 break; 3837 case TRANS_DDI_BPC_8: 3838 pipe_config->pipe_bpp = 24; 3839 break; 3840 case TRANS_DDI_BPC_10: 3841 pipe_config->pipe_bpp = 30; 3842 break; 3843 case TRANS_DDI_BPC_12: 3844 pipe_config->pipe_bpp = 36; 3845 break; 3846 default: 3847 break; 3848 } 3849 3850 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3851 case TRANS_DDI_MODE_SELECT_HDMI: 3852 pipe_config->has_hdmi_sink = true; 3853 3854 pipe_config->infoframes.enable |= 3855 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3856 3857 if (pipe_config->infoframes.enable) 3858 pipe_config->has_infoframe = true; 3859 3860 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3861 pipe_config->hdmi_scrambling = true; 3862 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3863 pipe_config->hdmi_high_tmds_clock_ratio = true; 3864 fallthrough; 3865 case TRANS_DDI_MODE_SELECT_DVI: 3866 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3867 if (DISPLAY_VER(dev_priv) >= 14) 3868 pipe_config->lane_count = 3869 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3870 else 3871 pipe_config->lane_count = 4; 3872 break; 3873 case TRANS_DDI_MODE_SELECT_DP_SST: 3874 if (encoder->type == INTEL_OUTPUT_EDP) 3875 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3876 else 3877 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3878 pipe_config->lane_count = 3879 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3880 3881 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3882 &pipe_config->dp_m_n); 3883 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3884 &pipe_config->dp_m2_n2); 3885 3886 pipe_config->enhanced_framing = 3887 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3888 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3889 3890 if (DISPLAY_VER(dev_priv) >= 11) 3891 pipe_config->fec_enable = 3892 intel_de_read(dev_priv, 3893 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3894 3895 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3896 pipe_config->infoframes.enable |= 3897 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3898 else 3899 pipe_config->infoframes.enable |= 3900 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3901 break; 3902 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3903 if (!HAS_DP20(dev_priv)) { 3904 /* FDI */ 3905 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3906 pipe_config->enhanced_framing = 3907 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3908 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3909 break; 3910 } 3911 fallthrough; /* 128b/132b */ 3912 case TRANS_DDI_MODE_SELECT_DP_MST: 3913 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3914 pipe_config->lane_count = 3915 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3916 3917 if (DISPLAY_VER(dev_priv) >= 12) 3918 pipe_config->mst_master_transcoder = 3919 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3920 3921 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3922 &pipe_config->dp_m_n); 3923 3924 if (DISPLAY_VER(dev_priv) >= 11) 3925 pipe_config->fec_enable = 3926 intel_de_read(dev_priv, 3927 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3928 3929 pipe_config->infoframes.enable |= 3930 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3931 break; 3932 default: 3933 break; 3934 } 3935 } 3936 3937 static void intel_ddi_get_config(struct intel_encoder *encoder, 3938 struct intel_crtc_state *pipe_config) 3939 { 3940 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3941 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3942 3943 /* XXX: DSI transcoder paranoia */ 3944 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3945 return; 3946 3947 intel_ddi_read_func_ctl(encoder, pipe_config); 3948 3949 intel_ddi_mso_get_config(encoder, pipe_config); 3950 3951 pipe_config->has_audio = 3952 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3953 3954 if (encoder->type == INTEL_OUTPUT_EDP) 3955 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3956 3957 ddi_dotclock_get(pipe_config); 3958 3959 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3960 pipe_config->lane_lat_optim_mask = 3961 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 3962 3963 intel_ddi_compute_min_voltage_level(pipe_config); 3964 3965 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3966 3967 intel_read_infoframe(encoder, pipe_config, 3968 HDMI_INFOFRAME_TYPE_AVI, 3969 &pipe_config->infoframes.avi); 3970 intel_read_infoframe(encoder, pipe_config, 3971 HDMI_INFOFRAME_TYPE_SPD, 3972 &pipe_config->infoframes.spd); 3973 intel_read_infoframe(encoder, pipe_config, 3974 HDMI_INFOFRAME_TYPE_VENDOR, 3975 &pipe_config->infoframes.hdmi); 3976 intel_read_infoframe(encoder, pipe_config, 3977 HDMI_INFOFRAME_TYPE_DRM, 3978 &pipe_config->infoframes.drm); 3979 3980 if (DISPLAY_VER(dev_priv) >= 8) 3981 bdw_get_trans_port_sync_config(pipe_config); 3982 3983 intel_psr_get_config(encoder, pipe_config); 3984 3985 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3986 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3987 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 3988 3989 intel_audio_codec_get_config(encoder, pipe_config); 3990 } 3991 3992 void intel_ddi_get_clock(struct intel_encoder *encoder, 3993 struct intel_crtc_state *crtc_state, 3994 struct intel_shared_dpll *pll) 3995 { 3996 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3997 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3998 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3999 bool pll_active; 4000 4001 if (drm_WARN_ON(&i915->drm, !pll)) 4002 return; 4003 4004 port_dpll->pll = pll; 4005 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4006 drm_WARN_ON(&i915->drm, !pll_active); 4007 4008 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4009 4010 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4011 &crtc_state->dpll_hw_state); 4012 } 4013 4014 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4015 struct intel_crtc_state *crtc_state) 4016 { 4017 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4018 4019 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 4020 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4021 } else { 4022 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4023 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4024 } 4025 4026 intel_ddi_get_config(encoder, crtc_state); 4027 } 4028 4029 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4030 struct intel_crtc_state *crtc_state) 4031 { 4032 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4033 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4034 4035 intel_ddi_get_config(encoder, crtc_state); 4036 } 4037 4038 static void adls_ddi_get_config(struct intel_encoder *encoder, 4039 struct intel_crtc_state *crtc_state) 4040 { 4041 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4042 intel_ddi_get_config(encoder, crtc_state); 4043 } 4044 4045 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4046 struct intel_crtc_state *crtc_state) 4047 { 4048 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4049 intel_ddi_get_config(encoder, crtc_state); 4050 } 4051 4052 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4053 struct intel_crtc_state *crtc_state) 4054 { 4055 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4056 intel_ddi_get_config(encoder, crtc_state); 4057 } 4058 4059 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4060 struct intel_crtc_state *crtc_state) 4061 { 4062 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4063 intel_ddi_get_config(encoder, crtc_state); 4064 } 4065 4066 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4067 { 4068 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4069 } 4070 4071 static enum icl_port_dpll_id 4072 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4073 const struct intel_crtc_state *crtc_state) 4074 { 4075 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4076 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4077 4078 if (drm_WARN_ON(&i915->drm, !pll)) 4079 return ICL_PORT_DPLL_DEFAULT; 4080 4081 if (icl_ddi_tc_pll_is_tbt(pll)) 4082 return ICL_PORT_DPLL_DEFAULT; 4083 else 4084 return ICL_PORT_DPLL_MG_PHY; 4085 } 4086 4087 enum icl_port_dpll_id 4088 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4089 const struct intel_crtc_state *crtc_state) 4090 { 4091 if (!encoder->port_pll_type) 4092 return ICL_PORT_DPLL_DEFAULT; 4093 4094 return encoder->port_pll_type(encoder, crtc_state); 4095 } 4096 4097 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4098 struct intel_crtc_state *crtc_state, 4099 struct intel_shared_dpll *pll) 4100 { 4101 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4102 enum icl_port_dpll_id port_dpll_id; 4103 struct icl_port_dpll *port_dpll; 4104 bool pll_active; 4105 4106 if (drm_WARN_ON(&i915->drm, !pll)) 4107 return; 4108 4109 if (icl_ddi_tc_pll_is_tbt(pll)) 4110 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4111 else 4112 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4113 4114 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4115 4116 port_dpll->pll = pll; 4117 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4118 drm_WARN_ON(&i915->drm, !pll_active); 4119 4120 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4121 4122 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4123 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4124 else 4125 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4126 &crtc_state->dpll_hw_state); 4127 } 4128 4129 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4130 struct intel_crtc_state *crtc_state) 4131 { 4132 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4133 intel_ddi_get_config(encoder, crtc_state); 4134 } 4135 4136 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4137 struct intel_crtc_state *crtc_state) 4138 { 4139 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4140 intel_ddi_get_config(encoder, crtc_state); 4141 } 4142 4143 static void skl_ddi_get_config(struct intel_encoder *encoder, 4144 struct intel_crtc_state *crtc_state) 4145 { 4146 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4147 intel_ddi_get_config(encoder, crtc_state); 4148 } 4149 4150 void hsw_ddi_get_config(struct intel_encoder *encoder, 4151 struct intel_crtc_state *crtc_state) 4152 { 4153 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4154 intel_ddi_get_config(encoder, crtc_state); 4155 } 4156 4157 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4158 const struct intel_crtc_state *crtc_state) 4159 { 4160 if (intel_encoder_is_tc(encoder)) 4161 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4162 crtc_state); 4163 4164 if (intel_encoder_is_dp(encoder)) 4165 intel_dp_sync_state(encoder, crtc_state); 4166 } 4167 4168 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4169 struct intel_crtc_state *crtc_state) 4170 { 4171 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4172 bool fastset = true; 4173 4174 if (intel_encoder_is_tc(encoder)) { 4175 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4176 encoder->base.base.id, encoder->base.name); 4177 crtc_state->uapi.mode_changed = true; 4178 fastset = false; 4179 } 4180 4181 if (intel_crtc_has_dp_encoder(crtc_state) && 4182 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4183 fastset = false; 4184 4185 return fastset; 4186 } 4187 4188 static enum intel_output_type 4189 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4190 struct intel_crtc_state *crtc_state, 4191 struct drm_connector_state *conn_state) 4192 { 4193 switch (conn_state->connector->connector_type) { 4194 case DRM_MODE_CONNECTOR_HDMIA: 4195 return INTEL_OUTPUT_HDMI; 4196 case DRM_MODE_CONNECTOR_eDP: 4197 return INTEL_OUTPUT_EDP; 4198 case DRM_MODE_CONNECTOR_DisplayPort: 4199 return INTEL_OUTPUT_DP; 4200 default: 4201 MISSING_CASE(conn_state->connector->connector_type); 4202 return INTEL_OUTPUT_UNUSED; 4203 } 4204 } 4205 4206 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4207 struct intel_crtc_state *pipe_config, 4208 struct drm_connector_state *conn_state) 4209 { 4210 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4211 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4212 enum port port = encoder->port; 4213 int ret; 4214 4215 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4216 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4217 4218 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4219 pipe_config->has_hdmi_sink = 4220 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4221 4222 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4223 } else { 4224 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4225 } 4226 4227 if (ret) 4228 return ret; 4229 4230 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4231 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4232 pipe_config->pch_pfit.force_thru = 4233 pipe_config->pch_pfit.enabled || 4234 pipe_config->crc_enabled; 4235 4236 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4237 pipe_config->lane_lat_optim_mask = 4238 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4239 4240 intel_ddi_compute_min_voltage_level(pipe_config); 4241 4242 return 0; 4243 } 4244 4245 static bool mode_equal(const struct drm_display_mode *mode1, 4246 const struct drm_display_mode *mode2) 4247 { 4248 return drm_mode_match(mode1, mode2, 4249 DRM_MODE_MATCH_TIMINGS | 4250 DRM_MODE_MATCH_FLAGS | 4251 DRM_MODE_MATCH_3D_FLAGS) && 4252 mode1->clock == mode2->clock; /* we want an exact match */ 4253 } 4254 4255 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4256 const struct intel_link_m_n *m_n_2) 4257 { 4258 return m_n_1->tu == m_n_2->tu && 4259 m_n_1->data_m == m_n_2->data_m && 4260 m_n_1->data_n == m_n_2->data_n && 4261 m_n_1->link_m == m_n_2->link_m && 4262 m_n_1->link_n == m_n_2->link_n; 4263 } 4264 4265 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4266 const struct intel_crtc_state *crtc_state2) 4267 { 4268 /* 4269 * FIXME the modeset sequence is currently wrong and 4270 * can't deal with bigjoiner + port sync at the same time. 4271 */ 4272 return crtc_state1->hw.active && crtc_state2->hw.active && 4273 !crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes && 4274 crtc_state1->output_types == crtc_state2->output_types && 4275 crtc_state1->output_format == crtc_state2->output_format && 4276 crtc_state1->lane_count == crtc_state2->lane_count && 4277 crtc_state1->port_clock == crtc_state2->port_clock && 4278 mode_equal(&crtc_state1->hw.adjusted_mode, 4279 &crtc_state2->hw.adjusted_mode) && 4280 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4281 } 4282 4283 static u8 4284 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4285 int tile_group_id) 4286 { 4287 struct drm_connector *connector; 4288 const struct drm_connector_state *conn_state; 4289 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4290 struct intel_atomic_state *state = 4291 to_intel_atomic_state(ref_crtc_state->uapi.state); 4292 u8 transcoders = 0; 4293 int i; 4294 4295 /* 4296 * We don't enable port sync on BDW due to missing w/as and 4297 * due to not having adjusted the modeset sequence appropriately. 4298 */ 4299 if (DISPLAY_VER(dev_priv) < 9) 4300 return 0; 4301 4302 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4303 return 0; 4304 4305 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4306 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4307 const struct intel_crtc_state *crtc_state; 4308 4309 if (!crtc) 4310 continue; 4311 4312 if (!connector->has_tile || 4313 connector->tile_group->id != 4314 tile_group_id) 4315 continue; 4316 crtc_state = intel_atomic_get_new_crtc_state(state, 4317 crtc); 4318 if (!crtcs_port_sync_compatible(ref_crtc_state, 4319 crtc_state)) 4320 continue; 4321 transcoders |= BIT(crtc_state->cpu_transcoder); 4322 } 4323 4324 return transcoders; 4325 } 4326 4327 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4328 struct intel_crtc_state *crtc_state, 4329 struct drm_connector_state *conn_state) 4330 { 4331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4332 struct drm_connector *connector = conn_state->connector; 4333 u8 port_sync_transcoders = 0; 4334 4335 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4336 encoder->base.base.id, encoder->base.name, 4337 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4338 4339 if (connector->has_tile) 4340 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4341 connector->tile_group->id); 4342 4343 /* 4344 * EDP Transcoders cannot be ensalved 4345 * make them a master always when present 4346 */ 4347 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4348 crtc_state->master_transcoder = TRANSCODER_EDP; 4349 else 4350 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4351 4352 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4353 crtc_state->master_transcoder = INVALID_TRANSCODER; 4354 crtc_state->sync_mode_slaves_mask = 4355 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4356 } 4357 4358 return 0; 4359 } 4360 4361 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4362 { 4363 struct drm_i915_private *i915 = to_i915(encoder->dev); 4364 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4365 4366 intel_dp_encoder_flush_work(encoder); 4367 if (intel_encoder_is_tc(&dig_port->base)) 4368 intel_tc_port_cleanup(dig_port); 4369 intel_display_power_flush_work(i915); 4370 4371 drm_encoder_cleanup(encoder); 4372 kfree(dig_port->hdcp_port_data.streams); 4373 kfree(dig_port); 4374 } 4375 4376 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4377 { 4378 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4379 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4380 4381 intel_dp->reset_link_params = true; 4382 4383 intel_pps_encoder_reset(intel_dp); 4384 4385 if (intel_encoder_is_tc(&dig_port->base)) 4386 intel_tc_port_init_mode(dig_port); 4387 } 4388 4389 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4390 { 4391 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4392 4393 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4394 4395 return 0; 4396 } 4397 4398 static const struct drm_encoder_funcs intel_ddi_funcs = { 4399 .reset = intel_ddi_encoder_reset, 4400 .destroy = intel_ddi_encoder_destroy, 4401 .late_register = intel_ddi_encoder_late_register, 4402 }; 4403 4404 static struct intel_connector * 4405 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4406 { 4407 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4408 struct intel_connector *connector; 4409 enum port port = dig_port->base.port; 4410 4411 connector = intel_connector_alloc(); 4412 if (!connector) 4413 return NULL; 4414 4415 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4416 if (DISPLAY_VER(i915) >= 14) 4417 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4418 else 4419 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4420 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4421 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4422 4423 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4424 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4425 4426 if (!intel_dp_init_connector(dig_port, connector)) { 4427 kfree(connector); 4428 return NULL; 4429 } 4430 4431 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4432 struct drm_device *dev = dig_port->base.base.dev; 4433 struct drm_privacy_screen *privacy_screen; 4434 4435 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4436 if (!IS_ERR(privacy_screen)) { 4437 drm_connector_attach_privacy_screen_provider(&connector->base, 4438 privacy_screen); 4439 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4440 drm_warn(dev, "Error getting privacy-screen\n"); 4441 } 4442 } 4443 4444 return connector; 4445 } 4446 4447 static int modeset_pipe(struct drm_crtc *crtc, 4448 struct drm_modeset_acquire_ctx *ctx) 4449 { 4450 struct drm_atomic_state *state; 4451 struct drm_crtc_state *crtc_state; 4452 int ret; 4453 4454 state = drm_atomic_state_alloc(crtc->dev); 4455 if (!state) 4456 return -ENOMEM; 4457 4458 state->acquire_ctx = ctx; 4459 to_intel_atomic_state(state)->internal = true; 4460 4461 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4462 if (IS_ERR(crtc_state)) { 4463 ret = PTR_ERR(crtc_state); 4464 goto out; 4465 } 4466 4467 crtc_state->connectors_changed = true; 4468 4469 ret = drm_atomic_commit(state); 4470 out: 4471 drm_atomic_state_put(state); 4472 4473 return ret; 4474 } 4475 4476 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4477 struct drm_modeset_acquire_ctx *ctx) 4478 { 4479 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4480 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4481 struct intel_connector *connector = hdmi->attached_connector; 4482 struct i2c_adapter *ddc = connector->base.ddc; 4483 struct drm_connector_state *conn_state; 4484 struct intel_crtc_state *crtc_state; 4485 struct intel_crtc *crtc; 4486 u8 config; 4487 int ret; 4488 4489 if (connector->base.status != connector_status_connected) 4490 return 0; 4491 4492 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4493 ctx); 4494 if (ret) 4495 return ret; 4496 4497 conn_state = connector->base.state; 4498 4499 crtc = to_intel_crtc(conn_state->crtc); 4500 if (!crtc) 4501 return 0; 4502 4503 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4504 if (ret) 4505 return ret; 4506 4507 crtc_state = to_intel_crtc_state(crtc->base.state); 4508 4509 drm_WARN_ON(&dev_priv->drm, 4510 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4511 4512 if (!crtc_state->hw.active) 4513 return 0; 4514 4515 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4516 !crtc_state->hdmi_scrambling) 4517 return 0; 4518 4519 if (conn_state->commit && 4520 !try_wait_for_completion(&conn_state->commit->hw_done)) 4521 return 0; 4522 4523 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4524 if (ret < 0) { 4525 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4526 connector->base.base.id, connector->base.name, ret); 4527 return 0; 4528 } 4529 4530 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4531 crtc_state->hdmi_high_tmds_clock_ratio && 4532 !!(config & SCDC_SCRAMBLING_ENABLE) == 4533 crtc_state->hdmi_scrambling) 4534 return 0; 4535 4536 /* 4537 * HDMI 2.0 says that one should not send scrambled data 4538 * prior to configuring the sink scrambling, and that 4539 * TMDS clock/data transmission should be suspended when 4540 * changing the TMDS clock rate in the sink. So let's 4541 * just do a full modeset here, even though some sinks 4542 * would be perfectly happy if were to just reconfigure 4543 * the SCDC settings on the fly. 4544 */ 4545 return modeset_pipe(&crtc->base, ctx); 4546 } 4547 4548 static enum intel_hotplug_state 4549 intel_ddi_hotplug(struct intel_encoder *encoder, 4550 struct intel_connector *connector) 4551 { 4552 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4553 struct intel_dp *intel_dp = &dig_port->dp; 4554 bool is_tc = intel_encoder_is_tc(encoder); 4555 struct drm_modeset_acquire_ctx ctx; 4556 enum intel_hotplug_state state; 4557 int ret; 4558 4559 if (intel_dp->compliance.test_active && 4560 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4561 intel_dp_phy_test(encoder); 4562 /* just do the PHY test and nothing else */ 4563 return INTEL_HOTPLUG_UNCHANGED; 4564 } 4565 4566 state = intel_encoder_hotplug(encoder, connector); 4567 4568 if (!intel_tc_port_link_reset(dig_port)) { 4569 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4570 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4571 ret = intel_hdmi_reset_link(encoder, &ctx); 4572 else 4573 ret = intel_dp_retrain_link(encoder, &ctx); 4574 } 4575 4576 drm_WARN_ON(encoder->base.dev, ret); 4577 } 4578 4579 /* 4580 * Unpowered type-c dongles can take some time to boot and be 4581 * responsible, so here giving some time to those dongles to power up 4582 * and then retrying the probe. 4583 * 4584 * On many platforms the HDMI live state signal is known to be 4585 * unreliable, so we can't use it to detect if a sink is connected or 4586 * not. Instead we detect if it's connected based on whether we can 4587 * read the EDID or not. That in turn has a problem during disconnect, 4588 * since the HPD interrupt may be raised before the DDC lines get 4589 * disconnected (due to how the required length of DDC vs. HPD 4590 * connector pins are specified) and so we'll still be able to get a 4591 * valid EDID. To solve this schedule another detection cycle if this 4592 * time around we didn't detect any change in the sink's connection 4593 * status. 4594 * 4595 * Type-c connectors which get their HPD signal deasserted then 4596 * reasserted, without unplugging/replugging the sink from the 4597 * connector, introduce a delay until the AUX channel communication 4598 * becomes functional. Retry the detection for 5 seconds on type-c 4599 * connectors to account for this delay. 4600 */ 4601 if (state == INTEL_HOTPLUG_UNCHANGED && 4602 connector->hotplug_retries < (is_tc ? 5 : 1) && 4603 !dig_port->dp.is_mst) 4604 state = INTEL_HOTPLUG_RETRY; 4605 4606 return state; 4607 } 4608 4609 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4610 { 4611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4612 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4613 4614 return intel_de_read(dev_priv, SDEISR) & bit; 4615 } 4616 4617 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4618 { 4619 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4620 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4621 4622 return intel_de_read(dev_priv, DEISR) & bit; 4623 } 4624 4625 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4626 { 4627 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4628 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4629 4630 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4631 } 4632 4633 static struct intel_connector * 4634 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4635 { 4636 struct intel_connector *connector; 4637 enum port port = dig_port->base.port; 4638 4639 connector = intel_connector_alloc(); 4640 if (!connector) 4641 return NULL; 4642 4643 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4644 intel_hdmi_init_connector(dig_port, connector); 4645 4646 return connector; 4647 } 4648 4649 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4650 { 4651 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4652 4653 if (dig_port->base.port != PORT_A) 4654 return false; 4655 4656 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4657 return false; 4658 4659 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4660 * supported configuration 4661 */ 4662 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4663 return true; 4664 4665 return false; 4666 } 4667 4668 static int 4669 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4670 { 4671 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4672 enum port port = dig_port->base.port; 4673 int max_lanes = 4; 4674 4675 if (DISPLAY_VER(dev_priv) >= 11) 4676 return max_lanes; 4677 4678 if (port == PORT_A || port == PORT_E) { 4679 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4680 max_lanes = port == PORT_A ? 4 : 0; 4681 else 4682 /* Both A and E share 2 lanes */ 4683 max_lanes = 2; 4684 } 4685 4686 /* 4687 * Some BIOS might fail to set this bit on port A if eDP 4688 * wasn't lit up at boot. Force this bit set when needed 4689 * so we use the proper lane count for our calculations. 4690 */ 4691 if (intel_ddi_a_force_4_lanes(dig_port)) { 4692 drm_dbg_kms(&dev_priv->drm, 4693 "Forcing DDI_A_4_LANES for port A\n"); 4694 dig_port->saved_port_bits |= DDI_A_4_LANES; 4695 max_lanes = 4; 4696 } 4697 4698 return max_lanes; 4699 } 4700 4701 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4702 enum port port) 4703 { 4704 if (port >= PORT_D_XELPD) 4705 return HPD_PORT_D + port - PORT_D_XELPD; 4706 else if (port >= PORT_TC1) 4707 return HPD_PORT_TC1 + port - PORT_TC1; 4708 else 4709 return HPD_PORT_A + port - PORT_A; 4710 } 4711 4712 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4713 enum port port) 4714 { 4715 if (port >= PORT_TC1) 4716 return HPD_PORT_C + port - PORT_TC1; 4717 else 4718 return HPD_PORT_A + port - PORT_A; 4719 } 4720 4721 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4722 enum port port) 4723 { 4724 if (port >= PORT_TC1) 4725 return HPD_PORT_TC1 + port - PORT_TC1; 4726 else 4727 return HPD_PORT_A + port - PORT_A; 4728 } 4729 4730 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4731 enum port port) 4732 { 4733 if (HAS_PCH_TGP(dev_priv)) 4734 return tgl_hpd_pin(dev_priv, port); 4735 4736 if (port >= PORT_TC1) 4737 return HPD_PORT_C + port - PORT_TC1; 4738 else 4739 return HPD_PORT_A + port - PORT_A; 4740 } 4741 4742 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4743 enum port port) 4744 { 4745 if (port >= PORT_C) 4746 return HPD_PORT_TC1 + port - PORT_C; 4747 else 4748 return HPD_PORT_A + port - PORT_A; 4749 } 4750 4751 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4752 enum port port) 4753 { 4754 if (port == PORT_D) 4755 return HPD_PORT_A; 4756 4757 if (HAS_PCH_TGP(dev_priv)) 4758 return icl_hpd_pin(dev_priv, port); 4759 4760 return HPD_PORT_A + port - PORT_A; 4761 } 4762 4763 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4764 { 4765 if (HAS_PCH_TGP(dev_priv)) 4766 return icl_hpd_pin(dev_priv, port); 4767 4768 return HPD_PORT_A + port - PORT_A; 4769 } 4770 4771 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4772 { 4773 if (DISPLAY_VER(i915) >= 12) 4774 return port >= PORT_TC1; 4775 else if (DISPLAY_VER(i915) >= 11) 4776 return port >= PORT_C; 4777 else 4778 return false; 4779 } 4780 4781 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4782 { 4783 intel_dp_encoder_suspend(encoder); 4784 } 4785 4786 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4787 { 4788 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4789 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4790 4791 intel_tc_port_suspend(dig_port); 4792 } 4793 4794 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4795 { 4796 intel_dp_encoder_shutdown(encoder); 4797 intel_hdmi_encoder_shutdown(encoder); 4798 } 4799 4800 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4801 { 4802 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4803 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4804 4805 intel_tc_port_cleanup(dig_port); 4806 } 4807 4808 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4809 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4810 4811 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4812 { 4813 /* straps not used on skl+ */ 4814 if (DISPLAY_VER(i915) >= 9) 4815 return true; 4816 4817 switch (port) { 4818 case PORT_A: 4819 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4820 case PORT_B: 4821 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4822 case PORT_C: 4823 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4824 case PORT_D: 4825 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4826 case PORT_E: 4827 return true; /* no strap for DDI-E */ 4828 default: 4829 MISSING_CASE(port); 4830 return false; 4831 } 4832 } 4833 4834 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4835 { 4836 return init_dp || intel_encoder_is_tc(encoder); 4837 } 4838 4839 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4840 { 4841 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4842 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4843 "Platform does not support DSI\n"); 4844 } 4845 4846 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4847 { 4848 struct intel_encoder *encoder; 4849 4850 for_each_intel_encoder(&i915->drm, encoder) { 4851 /* FIXME what about second port for dual link DSI? */ 4852 if (encoder->port == port) 4853 return true; 4854 } 4855 4856 return false; 4857 } 4858 4859 void intel_ddi_init(struct drm_i915_private *dev_priv, 4860 const struct intel_bios_encoder_data *devdata) 4861 { 4862 struct intel_digital_port *dig_port; 4863 struct intel_encoder *encoder; 4864 bool init_hdmi, init_dp; 4865 enum port port; 4866 enum phy phy; 4867 4868 port = intel_bios_encoder_port(devdata); 4869 if (port == PORT_NONE) 4870 return; 4871 4872 if (!port_strap_detected(dev_priv, port)) { 4873 drm_dbg_kms(&dev_priv->drm, 4874 "Port %c strap not detected\n", port_name(port)); 4875 return; 4876 } 4877 4878 if (!assert_port_valid(dev_priv, port)) 4879 return; 4880 4881 if (port_in_use(dev_priv, port)) { 4882 drm_dbg_kms(&dev_priv->drm, 4883 "Port %c already claimed\n", port_name(port)); 4884 return; 4885 } 4886 4887 if (intel_bios_encoder_supports_dsi(devdata)) { 4888 /* BXT/GLK handled elsewhere, for now at least */ 4889 if (!assert_has_icl_dsi(dev_priv)) 4890 return; 4891 4892 icl_dsi_init(dev_priv, devdata); 4893 return; 4894 } 4895 4896 phy = intel_port_to_phy(dev_priv, port); 4897 4898 /* 4899 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4900 * have taken over some of the PHYs and made them unavailable to the 4901 * driver. In that case we should skip initializing the corresponding 4902 * outputs. 4903 */ 4904 if (intel_hti_uses_phy(dev_priv, phy)) { 4905 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4906 port_name(port), phy_name(phy)); 4907 return; 4908 } 4909 4910 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4911 intel_bios_encoder_supports_hdmi(devdata); 4912 init_dp = intel_bios_encoder_supports_dp(devdata); 4913 4914 if (intel_bios_encoder_is_lspcon(devdata)) { 4915 /* 4916 * Lspcon device needs to be driven with DP connector 4917 * with special detection sequence. So make sure DP 4918 * is initialized before lspcon. 4919 */ 4920 init_dp = true; 4921 init_hdmi = false; 4922 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4923 port_name(port)); 4924 } 4925 4926 if (!init_dp && !init_hdmi) { 4927 drm_dbg_kms(&dev_priv->drm, 4928 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4929 port_name(port)); 4930 return; 4931 } 4932 4933 if (intel_phy_is_snps(dev_priv, phy) && 4934 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4935 drm_dbg_kms(&dev_priv->drm, 4936 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4937 phy_name(phy)); 4938 } 4939 4940 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4941 if (!dig_port) 4942 return; 4943 4944 dig_port->aux_ch = AUX_CH_NONE; 4945 4946 encoder = &dig_port->base; 4947 encoder->devdata = devdata; 4948 4949 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4950 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4951 DRM_MODE_ENCODER_TMDS, 4952 "DDI %c/PHY %c", 4953 port_name(port - PORT_D_XELPD + PORT_D), 4954 phy_name(phy)); 4955 } else if (DISPLAY_VER(dev_priv) >= 12) { 4956 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4957 4958 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4959 DRM_MODE_ENCODER_TMDS, 4960 "DDI %s%c/PHY %s%c", 4961 port >= PORT_TC1 ? "TC" : "", 4962 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4963 tc_port != TC_PORT_NONE ? "TC" : "", 4964 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4965 } else if (DISPLAY_VER(dev_priv) >= 11) { 4966 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4967 4968 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4969 DRM_MODE_ENCODER_TMDS, 4970 "DDI %c%s/PHY %s%c", 4971 port_name(port), 4972 port >= PORT_C ? " (TC)" : "", 4973 tc_port != TC_PORT_NONE ? "TC" : "", 4974 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4975 } else { 4976 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4977 DRM_MODE_ENCODER_TMDS, 4978 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4979 } 4980 4981 mutex_init(&dig_port->hdcp_mutex); 4982 dig_port->num_hdcp_streams = 0; 4983 4984 encoder->hotplug = intel_ddi_hotplug; 4985 encoder->compute_output_type = intel_ddi_compute_output_type; 4986 encoder->compute_config = intel_ddi_compute_config; 4987 encoder->compute_config_late = intel_ddi_compute_config_late; 4988 encoder->enable = intel_enable_ddi; 4989 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4990 encoder->pre_enable = intel_ddi_pre_enable; 4991 encoder->disable = intel_disable_ddi; 4992 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4993 encoder->post_disable = intel_ddi_post_disable; 4994 encoder->update_pipe = intel_ddi_update_pipe; 4995 encoder->audio_enable = intel_audio_codec_enable; 4996 encoder->audio_disable = intel_audio_codec_disable; 4997 encoder->get_hw_state = intel_ddi_get_hw_state; 4998 encoder->sync_state = intel_ddi_sync_state; 4999 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5000 encoder->suspend = intel_ddi_encoder_suspend; 5001 encoder->shutdown = intel_ddi_encoder_shutdown; 5002 encoder->get_power_domains = intel_ddi_get_power_domains; 5003 5004 encoder->type = INTEL_OUTPUT_DDI; 5005 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5006 encoder->port = port; 5007 encoder->cloneable = 0; 5008 encoder->pipe_mask = ~0; 5009 5010 if (DISPLAY_VER(dev_priv) >= 14) { 5011 encoder->enable_clock = intel_mtl_pll_enable; 5012 encoder->disable_clock = intel_mtl_pll_disable; 5013 encoder->port_pll_type = intel_mtl_port_pll_type; 5014 encoder->get_config = mtl_ddi_get_config; 5015 } else if (IS_DG2(dev_priv)) { 5016 encoder->enable_clock = intel_mpllb_enable; 5017 encoder->disable_clock = intel_mpllb_disable; 5018 encoder->get_config = dg2_ddi_get_config; 5019 } else if (IS_ALDERLAKE_S(dev_priv)) { 5020 encoder->enable_clock = adls_ddi_enable_clock; 5021 encoder->disable_clock = adls_ddi_disable_clock; 5022 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5023 encoder->get_config = adls_ddi_get_config; 5024 } else if (IS_ROCKETLAKE(dev_priv)) { 5025 encoder->enable_clock = rkl_ddi_enable_clock; 5026 encoder->disable_clock = rkl_ddi_disable_clock; 5027 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5028 encoder->get_config = rkl_ddi_get_config; 5029 } else if (IS_DG1(dev_priv)) { 5030 encoder->enable_clock = dg1_ddi_enable_clock; 5031 encoder->disable_clock = dg1_ddi_disable_clock; 5032 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5033 encoder->get_config = dg1_ddi_get_config; 5034 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5035 if (intel_ddi_is_tc(dev_priv, port)) { 5036 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5037 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5038 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5039 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5040 encoder->get_config = icl_ddi_combo_get_config; 5041 } else { 5042 encoder->enable_clock = icl_ddi_combo_enable_clock; 5043 encoder->disable_clock = icl_ddi_combo_disable_clock; 5044 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5045 encoder->get_config = icl_ddi_combo_get_config; 5046 } 5047 } else if (DISPLAY_VER(dev_priv) >= 11) { 5048 if (intel_ddi_is_tc(dev_priv, port)) { 5049 encoder->enable_clock = icl_ddi_tc_enable_clock; 5050 encoder->disable_clock = icl_ddi_tc_disable_clock; 5051 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5052 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5053 encoder->get_config = icl_ddi_tc_get_config; 5054 } else { 5055 encoder->enable_clock = icl_ddi_combo_enable_clock; 5056 encoder->disable_clock = icl_ddi_combo_disable_clock; 5057 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5058 encoder->get_config = icl_ddi_combo_get_config; 5059 } 5060 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5061 /* BXT/GLK have fixed PLL->port mapping */ 5062 encoder->get_config = bxt_ddi_get_config; 5063 } else if (DISPLAY_VER(dev_priv) == 9) { 5064 encoder->enable_clock = skl_ddi_enable_clock; 5065 encoder->disable_clock = skl_ddi_disable_clock; 5066 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5067 encoder->get_config = skl_ddi_get_config; 5068 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5069 encoder->enable_clock = hsw_ddi_enable_clock; 5070 encoder->disable_clock = hsw_ddi_disable_clock; 5071 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5072 encoder->get_config = hsw_ddi_get_config; 5073 } 5074 5075 if (DISPLAY_VER(dev_priv) >= 14) { 5076 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5077 } else if (IS_DG2(dev_priv)) { 5078 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5079 } else if (DISPLAY_VER(dev_priv) >= 12) { 5080 if (intel_encoder_is_combo(encoder)) 5081 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5082 else 5083 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5084 } else if (DISPLAY_VER(dev_priv) >= 11) { 5085 if (intel_encoder_is_combo(encoder)) 5086 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5087 else 5088 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5089 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5090 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5091 } else { 5092 encoder->set_signal_levels = hsw_set_signal_levels; 5093 } 5094 5095 intel_ddi_buf_trans_init(encoder); 5096 5097 if (DISPLAY_VER(dev_priv) >= 13) 5098 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5099 else if (IS_DG1(dev_priv)) 5100 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5101 else if (IS_ROCKETLAKE(dev_priv)) 5102 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5103 else if (DISPLAY_VER(dev_priv) >= 12) 5104 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5105 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5106 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5107 else if (DISPLAY_VER(dev_priv) == 11) 5108 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5109 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5110 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5111 else 5112 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5113 5114 if (DISPLAY_VER(dev_priv) >= 11) 5115 dig_port->saved_port_bits = 5116 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5117 & DDI_BUF_PORT_REVERSAL; 5118 else 5119 dig_port->saved_port_bits = 5120 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5121 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5122 5123 if (intel_bios_encoder_lane_reversal(devdata)) 5124 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5125 5126 dig_port->dp.output_reg = INVALID_MMIO_REG; 5127 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5128 5129 if (need_aux_ch(encoder, init_dp)) { 5130 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5131 if (dig_port->aux_ch == AUX_CH_NONE) 5132 goto err; 5133 } 5134 5135 if (intel_encoder_is_tc(encoder)) { 5136 bool is_legacy = 5137 !intel_bios_encoder_supports_typec_usb(devdata) && 5138 !intel_bios_encoder_supports_tbt(devdata); 5139 5140 if (!is_legacy && init_hdmi) { 5141 is_legacy = !init_dp; 5142 5143 drm_dbg_kms(&dev_priv->drm, 5144 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5145 port_name(port), 5146 str_yes_no(init_dp), 5147 is_legacy ? "legacy" : "non-legacy"); 5148 } 5149 5150 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5151 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5152 5153 dig_port->lock = intel_tc_port_lock; 5154 dig_port->unlock = intel_tc_port_unlock; 5155 5156 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5157 goto err; 5158 } 5159 5160 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5161 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5162 5163 if (DISPLAY_VER(dev_priv) >= 11) { 5164 if (intel_encoder_is_tc(encoder)) 5165 dig_port->connected = intel_tc_port_connected; 5166 else 5167 dig_port->connected = lpt_digital_port_connected; 5168 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5169 dig_port->connected = bdw_digital_port_connected; 5170 } else if (DISPLAY_VER(dev_priv) == 9) { 5171 dig_port->connected = lpt_digital_port_connected; 5172 } else if (IS_BROADWELL(dev_priv)) { 5173 if (port == PORT_A) 5174 dig_port->connected = bdw_digital_port_connected; 5175 else 5176 dig_port->connected = lpt_digital_port_connected; 5177 } else if (IS_HASWELL(dev_priv)) { 5178 if (port == PORT_A) 5179 dig_port->connected = hsw_digital_port_connected; 5180 else 5181 dig_port->connected = lpt_digital_port_connected; 5182 } 5183 5184 intel_infoframe_init(dig_port); 5185 5186 if (init_dp) { 5187 if (!intel_ddi_init_dp_connector(dig_port)) 5188 goto err; 5189 5190 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5191 5192 if (dig_port->dp.mso_link_count) 5193 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5194 } 5195 5196 /* 5197 * In theory we don't need the encoder->type check, 5198 * but leave it just in case we have some really bad VBTs... 5199 */ 5200 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5201 if (!intel_ddi_init_hdmi_connector(dig_port)) 5202 goto err; 5203 } 5204 5205 return; 5206 5207 err: 5208 drm_encoder_cleanup(&encoder->base); 5209 kfree(dig_port); 5210 } 5211