1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_privacy_screen_consumer.h> 35 36 #include "i915_reg.h" 37 #include "i915_utils.h" 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_dkl_phy.h" 56 #include "intel_dkl_phy_regs.h" 57 #include "intel_dp.h" 58 #include "intel_dp_aux.h" 59 #include "intel_dp_link_training.h" 60 #include "intel_dp_mst.h" 61 #include "intel_dp_test.h" 62 #include "intel_dp_tunnel.h" 63 #include "intel_dpio_phy.h" 64 #include "intel_dsi.h" 65 #include "intel_encoder.h" 66 #include "intel_fdi.h" 67 #include "intel_fifo_underrun.h" 68 #include "intel_gmbus.h" 69 #include "intel_hdcp.h" 70 #include "intel_hdmi.h" 71 #include "intel_hotplug.h" 72 #include "intel_hti.h" 73 #include "intel_lspcon.h" 74 #include "intel_mg_phy_regs.h" 75 #include "intel_modeset_lock.h" 76 #include "intel_pfit.h" 77 #include "intel_pps.h" 78 #include "intel_psr.h" 79 #include "intel_quirks.h" 80 #include "intel_snps_phy.h" 81 #include "intel_tc.h" 82 #include "intel_vdsc.h" 83 #include "intel_vdsc_regs.h" 84 #include "intel_vrr.h" 85 #include "skl_scaler.h" 86 #include "skl_universal_plane.h" 87 88 static const u8 index_to_dp_signal_levels[] = { 89 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 90 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 91 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 92 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 93 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 95 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 96 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 97 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 98 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 99 }; 100 101 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 102 const struct intel_ddi_buf_trans *trans) 103 { 104 int level; 105 106 level = intel_bios_hdmi_level_shift(encoder->devdata); 107 if (level < 0) 108 level = trans->hdmi_default_entry; 109 110 return level; 111 } 112 113 static bool has_buf_trans_select(struct intel_display *display) 114 { 115 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 116 } 117 118 static bool has_iboost(struct intel_display *display) 119 { 120 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 121 } 122 123 /* 124 * Starting with Haswell, DDI port buffers must be programmed with correct 125 * values in advance. This function programs the correct values for 126 * DP/eDP/FDI use cases. 127 */ 128 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 129 const struct intel_crtc_state *crtc_state) 130 { 131 struct intel_display *display = to_intel_display(encoder); 132 u32 iboost_bit = 0; 133 int i, n_entries; 134 enum port port = encoder->port; 135 const struct intel_ddi_buf_trans *trans; 136 137 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 138 if (drm_WARN_ON_ONCE(display->drm, !trans)) 139 return; 140 141 /* If we're boosting the current, set bit 31 of trans1 */ 142 if (has_iboost(display) && 143 intel_bios_dp_boost_level(encoder->devdata)) 144 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 145 146 for (i = 0; i < n_entries; i++) { 147 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 148 trans->entries[i].hsw.trans1 | iboost_bit); 149 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 150 trans->entries[i].hsw.trans2); 151 } 152 } 153 154 /* 155 * Starting with Haswell, DDI port buffers must be programmed with correct 156 * values in advance. This function programs the correct values for 157 * HDMI/DVI use cases. 158 */ 159 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 160 const struct intel_crtc_state *crtc_state) 161 { 162 struct intel_display *display = to_intel_display(encoder); 163 int level = intel_ddi_level(encoder, crtc_state, 0); 164 u32 iboost_bit = 0; 165 int n_entries; 166 enum port port = encoder->port; 167 const struct intel_ddi_buf_trans *trans; 168 169 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 170 if (drm_WARN_ON_ONCE(display->drm, !trans)) 171 return; 172 173 /* If we're boosting the current, set bit 31 of trans1 */ 174 if (has_iboost(display) && 175 intel_bios_hdmi_boost_level(encoder->devdata)) 176 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 177 178 /* Entry 9 is for HDMI: */ 179 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 180 trans->entries[level].hsw.trans1 | iboost_bit); 181 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 182 trans->entries[level].hsw.trans2); 183 } 184 185 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 186 { 187 if (DISPLAY_VER(display) >= 14) 188 return XELPDP_PORT_BUF_CTL1(display, port); 189 else 190 return DDI_BUF_CTL(port); 191 } 192 193 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 194 { 195 /* 196 * Bspec's platform specific timeouts: 197 * MTL+ : 100 us 198 * BXT : fixed 16 us 199 * HSW-ADL: 8 us 200 * 201 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 202 */ 203 if (display->platform.broxton) { 204 udelay(16); 205 return; 206 } 207 208 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 209 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 210 DDI_BUF_IS_IDLE, 10)) 211 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 212 port_name(port)); 213 } 214 215 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 216 { 217 struct intel_display *display = to_intel_display(encoder); 218 enum port port = encoder->port; 219 220 /* 221 * Bspec's platform specific timeouts: 222 * MTL+ : 10000 us 223 * DG2 : 1200 us 224 * TGL-ADL combo PHY: 1000 us 225 * TGL-ADL TypeC PHY: 3000 us 226 * HSW-ICL : fixed 518 us 227 */ 228 if (DISPLAY_VER(display) < 10) { 229 usleep_range(518, 1000); 230 return; 231 } 232 233 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 234 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 235 DDI_BUF_IS_IDLE, 10)) 236 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 237 port_name(port)); 238 } 239 240 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 241 { 242 switch (pll->info->id) { 243 case DPLL_ID_WRPLL1: 244 return PORT_CLK_SEL_WRPLL1; 245 case DPLL_ID_WRPLL2: 246 return PORT_CLK_SEL_WRPLL2; 247 case DPLL_ID_SPLL: 248 return PORT_CLK_SEL_SPLL; 249 case DPLL_ID_LCPLL_810: 250 return PORT_CLK_SEL_LCPLL_810; 251 case DPLL_ID_LCPLL_1350: 252 return PORT_CLK_SEL_LCPLL_1350; 253 case DPLL_ID_LCPLL_2700: 254 return PORT_CLK_SEL_LCPLL_2700; 255 default: 256 MISSING_CASE(pll->info->id); 257 return PORT_CLK_SEL_NONE; 258 } 259 } 260 261 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 262 const struct intel_crtc_state *crtc_state) 263 { 264 const struct intel_dpll *pll = crtc_state->intel_dpll; 265 int clock = crtc_state->port_clock; 266 const enum intel_dpll_id id = pll->info->id; 267 268 switch (id) { 269 default: 270 /* 271 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 272 * here, so do warn if this get passed in 273 */ 274 MISSING_CASE(id); 275 return DDI_CLK_SEL_NONE; 276 case DPLL_ID_ICL_TBTPLL: 277 switch (clock) { 278 case 162000: 279 return DDI_CLK_SEL_TBT_162; 280 case 270000: 281 return DDI_CLK_SEL_TBT_270; 282 case 540000: 283 return DDI_CLK_SEL_TBT_540; 284 case 810000: 285 return DDI_CLK_SEL_TBT_810; 286 default: 287 MISSING_CASE(clock); 288 return DDI_CLK_SEL_NONE; 289 } 290 case DPLL_ID_ICL_MGPLL1: 291 case DPLL_ID_ICL_MGPLL2: 292 case DPLL_ID_ICL_MGPLL3: 293 case DPLL_ID_ICL_MGPLL4: 294 case DPLL_ID_TGL_MGPLL5: 295 case DPLL_ID_TGL_MGPLL6: 296 return DDI_CLK_SEL_MG; 297 } 298 } 299 300 static u32 ddi_buf_phy_link_rate(int port_clock) 301 { 302 switch (port_clock) { 303 case 162000: 304 return DDI_BUF_PHY_LINK_RATE(0); 305 case 216000: 306 return DDI_BUF_PHY_LINK_RATE(4); 307 case 243000: 308 return DDI_BUF_PHY_LINK_RATE(5); 309 case 270000: 310 return DDI_BUF_PHY_LINK_RATE(1); 311 case 324000: 312 return DDI_BUF_PHY_LINK_RATE(6); 313 case 432000: 314 return DDI_BUF_PHY_LINK_RATE(7); 315 case 540000: 316 return DDI_BUF_PHY_LINK_RATE(2); 317 case 810000: 318 return DDI_BUF_PHY_LINK_RATE(3); 319 default: 320 MISSING_CASE(port_clock); 321 return DDI_BUF_PHY_LINK_RATE(0); 322 } 323 } 324 325 static int dp_phy_lane_stagger_delay(int port_clock) 326 { 327 /* 328 * Return the number of symbol clocks delay used to stagger the 329 * assertion/desassertion of the port lane enables. The target delay 330 * time is 100 ns or greater, return the number of symbols specific to 331 * the provided port_clock (aka link clock) corresponding to this delay 332 * time, i.e. so that 333 * 334 * number_of_symbols * duration_of_one_symbol >= 100 ns 335 * 336 * The delay must be applied only on TypeC DP outputs, for everything else 337 * the delay must be set to 0. 338 * 339 * Return the number of link symbols per 100 ns: 340 * port_clock (10 kHz) -> bits / 100 us 341 * / symbol_size -> symbols / 100 us 342 * / 1000 -> symbols / 100 ns 343 */ 344 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 345 } 346 347 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state) 349 { 350 struct intel_display *display = to_intel_display(encoder); 351 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 352 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 353 354 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 355 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 356 DDI_BUF_TRANS_SELECT(0); 357 358 if (dig_port->lane_reversal) 359 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 360 if (dig_port->ddi_a_4_lanes) 361 intel_dp->DP |= DDI_A_4_LANES; 362 363 if (DISPLAY_VER(display) >= 14) { 364 if (intel_dp_is_uhbr(crtc_state)) 365 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 366 else 367 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 368 } 369 370 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 371 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 372 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 373 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 374 } 375 376 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 377 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 378 379 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 380 } 381 } 382 383 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 384 { 385 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 386 387 switch (val) { 388 case DDI_CLK_SEL_NONE: 389 return 0; 390 case DDI_CLK_SEL_TBT_162: 391 return 162000; 392 case DDI_CLK_SEL_TBT_270: 393 return 270000; 394 case DDI_CLK_SEL_TBT_540: 395 return 540000; 396 case DDI_CLK_SEL_TBT_810: 397 return 810000; 398 default: 399 MISSING_CASE(val); 400 return 0; 401 } 402 } 403 404 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 405 { 406 /* CRT dotclock is determined via other means */ 407 if (pipe_config->has_pch_encoder) 408 return; 409 410 pipe_config->hw.adjusted_mode.crtc_clock = 411 intel_crtc_dotclock(pipe_config); 412 } 413 414 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 415 const struct drm_connector_state *conn_state) 416 { 417 struct intel_display *display = to_intel_display(crtc_state); 418 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 419 u32 temp; 420 421 if (!intel_crtc_has_dp_encoder(crtc_state)) 422 return; 423 424 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 425 426 temp = DP_MSA_MISC_SYNC_CLOCK; 427 428 switch (crtc_state->pipe_bpp) { 429 case 18: 430 temp |= DP_MSA_MISC_6_BPC; 431 break; 432 case 24: 433 temp |= DP_MSA_MISC_8_BPC; 434 break; 435 case 30: 436 temp |= DP_MSA_MISC_10_BPC; 437 break; 438 case 36: 439 temp |= DP_MSA_MISC_12_BPC; 440 break; 441 default: 442 MISSING_CASE(crtc_state->pipe_bpp); 443 break; 444 } 445 446 /* nonsense combination */ 447 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 448 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 449 450 if (crtc_state->limited_color_range) 451 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 452 453 /* 454 * As per DP 1.2 spec section 2.3.4.3 while sending 455 * YCBCR 444 signals we should program MSA MISC1/0 fields with 456 * colorspace information. 457 */ 458 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 459 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 460 461 /* 462 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 463 * of Color Encoding Format and Content Color Gamut] while sending 464 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 465 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 466 */ 467 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 468 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 469 470 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 471 temp); 472 } 473 474 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 475 { 476 if (master_transcoder == TRANSCODER_EDP) 477 return 0; 478 else 479 return master_transcoder + 1; 480 } 481 482 static void 483 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 484 bool enable) 485 { 486 struct intel_display *display = to_intel_display(crtc_state); 487 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 488 u32 val = 0; 489 490 if (!HAS_DP20(display)) 491 return; 492 493 if (enable && intel_dp_is_uhbr(crtc_state)) 494 val = TRANS_DP2_128B132B_CHANNEL_CODING; 495 496 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 497 } 498 499 /* 500 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 501 * 502 * Only intended to be used by intel_ddi_enable_transcoder_func() and 503 * intel_ddi_config_transcoder_func(). 504 */ 505 static u32 506 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 507 const struct intel_crtc_state *crtc_state) 508 { 509 struct intel_display *display = to_intel_display(crtc_state); 510 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 511 enum pipe pipe = crtc->pipe; 512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 513 enum port port = encoder->port; 514 u32 temp; 515 516 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 517 temp = TRANS_DDI_FUNC_ENABLE; 518 if (DISPLAY_VER(display) >= 12) 519 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 520 else 521 temp |= TRANS_DDI_SELECT_PORT(port); 522 523 switch (crtc_state->pipe_bpp) { 524 default: 525 MISSING_CASE(crtc_state->pipe_bpp); 526 fallthrough; 527 case 18: 528 temp |= TRANS_DDI_BPC_6; 529 break; 530 case 24: 531 temp |= TRANS_DDI_BPC_8; 532 break; 533 case 30: 534 temp |= TRANS_DDI_BPC_10; 535 break; 536 case 36: 537 temp |= TRANS_DDI_BPC_12; 538 break; 539 } 540 541 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 542 temp |= TRANS_DDI_PVSYNC; 543 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 544 temp |= TRANS_DDI_PHSYNC; 545 546 if (cpu_transcoder == TRANSCODER_EDP) { 547 switch (pipe) { 548 default: 549 MISSING_CASE(pipe); 550 fallthrough; 551 case PIPE_A: 552 /* On Haswell, can only use the always-on power well for 553 * eDP when not using the panel fitter, and when not 554 * using motion blur mitigation (which we don't 555 * support). */ 556 if (crtc_state->pch_pfit.force_thru) 557 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 558 else 559 temp |= TRANS_DDI_EDP_INPUT_A_ON; 560 break; 561 case PIPE_B: 562 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 563 break; 564 case PIPE_C: 565 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 566 break; 567 } 568 } 569 570 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 571 if (crtc_state->has_hdmi_sink) 572 temp |= TRANS_DDI_MODE_SELECT_HDMI; 573 else 574 temp |= TRANS_DDI_MODE_SELECT_DVI; 575 576 if (crtc_state->hdmi_scrambling) 577 temp |= TRANS_DDI_HDMI_SCRAMBLING; 578 if (crtc_state->hdmi_high_tmds_clock_ratio) 579 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 580 if (DISPLAY_VER(display) >= 14) 581 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 582 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 583 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 584 temp |= (crtc_state->fdi_lanes - 1) << 1; 585 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 586 intel_dp_is_uhbr(crtc_state)) { 587 if (intel_dp_is_uhbr(crtc_state)) 588 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 589 else 590 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 591 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 592 593 if (DISPLAY_VER(display) >= 12) { 594 enum transcoder master; 595 596 master = crtc_state->mst_master_transcoder; 597 drm_WARN_ON(display->drm, 598 master == INVALID_TRANSCODER); 599 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 600 } 601 } else { 602 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 603 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 604 } 605 606 if (IS_DISPLAY_VER(display, 8, 10) && 607 crtc_state->master_transcoder != INVALID_TRANSCODER) { 608 u8 master_select = 609 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 610 611 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 612 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 613 } 614 615 return temp; 616 } 617 618 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 619 const struct intel_crtc_state *crtc_state) 620 { 621 struct intel_display *display = to_intel_display(crtc_state); 622 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 623 624 if (DISPLAY_VER(display) >= 11) { 625 enum transcoder master_transcoder = crtc_state->master_transcoder; 626 u32 ctl2 = 0; 627 628 if (master_transcoder != INVALID_TRANSCODER) { 629 u8 master_select = 630 bdw_trans_port_sync_master_select(master_transcoder); 631 632 ctl2 |= PORT_SYNC_MODE_ENABLE | 633 PORT_SYNC_MODE_MASTER_SELECT(master_select); 634 } 635 636 intel_de_write(display, 637 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 638 ctl2); 639 } 640 641 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 642 intel_ddi_transcoder_func_reg_val_get(encoder, 643 crtc_state)); 644 } 645 646 /* 647 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 648 * bit for the DDI function and enables the DP2 configuration. Called for all 649 * transcoder types. 650 */ 651 void 652 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 653 const struct intel_crtc_state *crtc_state) 654 { 655 struct intel_display *display = to_intel_display(crtc_state); 656 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 657 u32 ctl; 658 659 intel_ddi_config_transcoder_dp2(crtc_state, true); 660 661 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 662 ctl &= ~TRANS_DDI_FUNC_ENABLE; 663 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 664 ctl); 665 } 666 667 /* 668 * Disable the DDI function and port syncing. 669 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 670 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 671 * transcoders these are done later in intel_ddi_post_disable_dp(). 672 */ 673 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 674 { 675 struct intel_display *display = to_intel_display(crtc_state); 676 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 677 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 678 u32 ctl; 679 680 if (DISPLAY_VER(display) >= 11) 681 intel_de_write(display, 682 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 683 0); 684 685 ctl = intel_de_read(display, 686 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 687 688 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 689 690 ctl &= ~TRANS_DDI_FUNC_ENABLE; 691 692 if (IS_DISPLAY_VER(display, 8, 10)) 693 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 694 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 695 696 if (DISPLAY_VER(display) >= 12) { 697 if (!intel_dp_mst_is_master_trans(crtc_state)) { 698 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 699 TRANS_DDI_MODE_SELECT_MASK); 700 } 701 } else { 702 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 703 } 704 705 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 706 ctl); 707 708 if (intel_dp_mst_is_slave_trans(crtc_state)) 709 intel_ddi_config_transcoder_dp2(crtc_state, false); 710 711 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 712 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 713 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 714 /* Quirk time at 100ms for reliable operation */ 715 msleep(100); 716 } 717 } 718 719 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 720 enum transcoder cpu_transcoder, 721 bool enable, u32 hdcp_mask) 722 { 723 struct intel_display *display = to_intel_display(intel_encoder); 724 intel_wakeref_t wakeref; 725 int ret = 0; 726 727 wakeref = intel_display_power_get_if_enabled(display, 728 intel_encoder->power_domain); 729 if (drm_WARN_ON(display->drm, !wakeref)) 730 return -ENXIO; 731 732 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 733 hdcp_mask, enable ? hdcp_mask : 0); 734 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 735 return ret; 736 } 737 738 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 739 { 740 struct intel_display *display = to_intel_display(intel_connector); 741 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 742 int type = intel_connector->base.connector_type; 743 enum port port = encoder->port; 744 enum transcoder cpu_transcoder; 745 intel_wakeref_t wakeref; 746 enum pipe pipe = 0; 747 u32 ddi_mode; 748 bool ret; 749 750 wakeref = intel_display_power_get_if_enabled(display, 751 encoder->power_domain); 752 if (!wakeref) 753 return false; 754 755 /* Note: This returns false for DP MST primary encoders. */ 756 if (!encoder->get_hw_state(encoder, &pipe)) { 757 ret = false; 758 goto out; 759 } 760 761 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 762 cpu_transcoder = TRANSCODER_EDP; 763 else 764 cpu_transcoder = (enum transcoder) pipe; 765 766 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 767 TRANS_DDI_MODE_SELECT_MASK; 768 769 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 770 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 771 ret = type == DRM_MODE_CONNECTOR_HDMIA; 772 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 773 ret = type == DRM_MODE_CONNECTOR_VGA; 774 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 775 ret = type == DRM_MODE_CONNECTOR_eDP || 776 type == DRM_MODE_CONNECTOR_DisplayPort; 777 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 778 /* 779 * encoder->get_hw_state() should have bailed out on MST. This 780 * must be SST and non-eDP. 781 */ 782 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 783 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 784 /* encoder->get_hw_state() should have bailed out on MST. */ 785 ret = false; 786 } else { 787 ret = false; 788 } 789 790 out: 791 intel_display_power_put(display, encoder->power_domain, wakeref); 792 793 return ret; 794 } 795 796 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 797 u8 *pipe_mask, bool *is_dp_mst) 798 { 799 struct intel_display *display = to_intel_display(encoder); 800 enum port port = encoder->port; 801 intel_wakeref_t wakeref; 802 enum pipe p; 803 u32 tmp; 804 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 805 806 *pipe_mask = 0; 807 *is_dp_mst = false; 808 809 wakeref = intel_display_power_get_if_enabled(display, 810 encoder->power_domain); 811 if (!wakeref) 812 return; 813 814 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 815 if (!(tmp & DDI_BUF_CTL_ENABLE)) 816 goto out; 817 818 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 819 tmp = intel_de_read(display, 820 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 821 822 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 823 default: 824 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 825 fallthrough; 826 case TRANS_DDI_EDP_INPUT_A_ON: 827 case TRANS_DDI_EDP_INPUT_A_ONOFF: 828 *pipe_mask = BIT(PIPE_A); 829 break; 830 case TRANS_DDI_EDP_INPUT_B_ONOFF: 831 *pipe_mask = BIT(PIPE_B); 832 break; 833 case TRANS_DDI_EDP_INPUT_C_ONOFF: 834 *pipe_mask = BIT(PIPE_C); 835 break; 836 } 837 838 goto out; 839 } 840 841 for_each_pipe(display, p) { 842 enum transcoder cpu_transcoder = (enum transcoder)p; 843 u32 port_mask, ddi_select, ddi_mode; 844 intel_wakeref_t trans_wakeref; 845 846 trans_wakeref = intel_display_power_get_if_enabled(display, 847 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 848 if (!trans_wakeref) 849 continue; 850 851 if (DISPLAY_VER(display) >= 12) { 852 port_mask = TGL_TRANS_DDI_PORT_MASK; 853 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 854 } else { 855 port_mask = TRANS_DDI_PORT_MASK; 856 ddi_select = TRANS_DDI_SELECT_PORT(port); 857 } 858 859 tmp = intel_de_read(display, 860 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 861 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 862 trans_wakeref); 863 864 if ((tmp & port_mask) != ddi_select) 865 continue; 866 867 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 868 869 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 870 mst_pipe_mask |= BIT(p); 871 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 872 dp128b132b_pipe_mask |= BIT(p); 873 874 *pipe_mask |= BIT(p); 875 } 876 877 if (!*pipe_mask) 878 drm_dbg_kms(display->drm, 879 "No pipe for [ENCODER:%d:%s] found\n", 880 encoder->base.base.id, encoder->base.name); 881 882 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 883 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 884 885 /* 886 * If we don't have 8b/10b MST, but have more than one 887 * transcoder in 128b/132b mode, we know it must be 128b/132b 888 * MST. 889 * 890 * Otherwise, we fall back to checking the current MST 891 * state. It's not accurate for hardware takeover at probe, but 892 * we don't expect MST to have been enabled at that point, and 893 * can assume it's SST. 894 */ 895 if (hweight8(dp128b132b_pipe_mask) > 1 || 896 intel_dp_mst_active_streams(intel_dp)) 897 mst_pipe_mask = dp128b132b_pipe_mask; 898 } 899 900 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 901 drm_dbg_kms(display->drm, 902 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 903 encoder->base.base.id, encoder->base.name, 904 *pipe_mask); 905 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 906 } 907 908 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 909 drm_dbg_kms(display->drm, 910 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 911 encoder->base.base.id, encoder->base.name, 912 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 913 else 914 *is_dp_mst = mst_pipe_mask; 915 916 out: 917 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 918 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 919 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 920 BXT_PHY_LANE_POWERDOWN_ACK | 921 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 922 drm_err(display->drm, 923 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 924 encoder->base.base.id, encoder->base.name, tmp); 925 } 926 927 intel_display_power_put(display, encoder->power_domain, wakeref); 928 } 929 930 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 931 enum pipe *pipe) 932 { 933 u8 pipe_mask; 934 bool is_mst; 935 936 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 937 938 if (is_mst || !pipe_mask) 939 return false; 940 941 *pipe = ffs(pipe_mask) - 1; 942 943 return true; 944 } 945 946 static enum intel_display_power_domain 947 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 948 const struct intel_crtc_state *crtc_state) 949 { 950 struct intel_display *display = to_intel_display(dig_port); 951 952 /* 953 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 954 * DC states enabled at the same time, while for driver initiated AUX 955 * transfers we need the same AUX IOs to be powered but with DC states 956 * disabled. Accordingly use the AUX_IO_<port> power domain here which 957 * leaves DC states enabled. 958 * 959 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 960 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 961 * well, so we can acquire a wider AUX_<port> power domain reference 962 * instead of a specific AUX_IO_<port> reference without powering up any 963 * extra wells. 964 */ 965 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 966 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 967 else if (DISPLAY_VER(display) < 14 && 968 (intel_crtc_has_dp_encoder(crtc_state) || 969 intel_encoder_is_tc(&dig_port->base))) 970 return intel_aux_power_domain(dig_port); 971 else 972 return POWER_DOMAIN_INVALID; 973 } 974 975 static void 976 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 977 const struct intel_crtc_state *crtc_state) 978 { 979 struct intel_display *display = to_intel_display(dig_port); 980 enum intel_display_power_domain domain = 981 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 982 983 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 984 985 if (domain == POWER_DOMAIN_INVALID) 986 return; 987 988 dig_port->aux_wakeref = intel_display_power_get(display, domain); 989 } 990 991 static void 992 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 993 const struct intel_crtc_state *crtc_state) 994 { 995 struct intel_display *display = to_intel_display(dig_port); 996 enum intel_display_power_domain domain = 997 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 998 intel_wakeref_t wf; 999 1000 wf = fetch_and_zero(&dig_port->aux_wakeref); 1001 if (!wf) 1002 return; 1003 1004 intel_display_power_put(display, domain, wf); 1005 } 1006 1007 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1008 struct intel_crtc_state *crtc_state) 1009 { 1010 struct intel_display *display = to_intel_display(encoder); 1011 struct intel_digital_port *dig_port; 1012 1013 /* 1014 * TODO: Add support for MST encoders. Atm, the following should never 1015 * happen since fake-MST encoders don't set their get_power_domains() 1016 * hook. 1017 */ 1018 if (drm_WARN_ON(display->drm, 1019 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1020 return; 1021 1022 dig_port = enc_to_dig_port(encoder); 1023 1024 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1025 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1026 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1027 dig_port->ddi_io_power_domain); 1028 } 1029 1030 main_link_aux_power_domain_get(dig_port, crtc_state); 1031 } 1032 1033 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1034 const struct intel_crtc_state *crtc_state) 1035 { 1036 struct intel_display *display = to_intel_display(crtc_state); 1037 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1038 enum phy phy = intel_encoder_to_phy(encoder); 1039 u32 val; 1040 1041 if (cpu_transcoder == TRANSCODER_EDP) 1042 return; 1043 1044 if (DISPLAY_VER(display) >= 13) 1045 val = TGL_TRANS_CLK_SEL_PORT(phy); 1046 else if (DISPLAY_VER(display) >= 12) 1047 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1048 else 1049 val = TRANS_CLK_SEL_PORT(encoder->port); 1050 1051 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1052 } 1053 1054 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1055 { 1056 struct intel_display *display = to_intel_display(crtc_state); 1057 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1058 u32 val; 1059 1060 if (cpu_transcoder == TRANSCODER_EDP) 1061 return; 1062 1063 if (DISPLAY_VER(display) >= 12) 1064 val = TGL_TRANS_CLK_SEL_DISABLED; 1065 else 1066 val = TRANS_CLK_SEL_DISABLED; 1067 1068 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1069 } 1070 1071 static void _skl_ddi_set_iboost(struct intel_display *display, 1072 enum port port, u8 iboost) 1073 { 1074 u32 tmp; 1075 1076 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1077 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1078 if (iboost) 1079 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1080 else 1081 tmp |= BALANCE_LEG_DISABLE(port); 1082 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1083 } 1084 1085 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1086 const struct intel_crtc_state *crtc_state, 1087 int level) 1088 { 1089 struct intel_display *display = to_intel_display(encoder); 1090 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1091 u8 iboost; 1092 1093 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1094 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1095 else 1096 iboost = intel_bios_dp_boost_level(encoder->devdata); 1097 1098 if (iboost == 0) { 1099 const struct intel_ddi_buf_trans *trans; 1100 int n_entries; 1101 1102 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1103 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1104 return; 1105 1106 iboost = trans->entries[level].hsw.i_boost; 1107 } 1108 1109 /* Make sure that the requested I_boost is valid */ 1110 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1111 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1112 return; 1113 } 1114 1115 _skl_ddi_set_iboost(display, encoder->port, iboost); 1116 1117 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1118 _skl_ddi_set_iboost(display, PORT_E, iboost); 1119 } 1120 1121 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1122 const struct intel_crtc_state *crtc_state) 1123 { 1124 struct intel_display *display = to_intel_display(intel_dp); 1125 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1126 int n_entries; 1127 1128 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1129 1130 if (drm_WARN_ON(display->drm, n_entries < 1)) 1131 n_entries = 1; 1132 if (drm_WARN_ON(display->drm, 1133 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1134 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1135 1136 return index_to_dp_signal_levels[n_entries - 1] & 1137 DP_TRAIN_VOLTAGE_SWING_MASK; 1138 } 1139 1140 /* 1141 * We assume that the full set of pre-emphasis values can be 1142 * used on all DDI platforms. Should that change we need to 1143 * rethink this code. 1144 */ 1145 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1146 { 1147 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1148 } 1149 1150 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1151 int lane) 1152 { 1153 if (crtc_state->port_clock > 600000) 1154 return 0; 1155 1156 if (crtc_state->lane_count == 4) 1157 return lane >= 1 ? LOADGEN_SELECT : 0; 1158 else 1159 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1160 } 1161 1162 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1163 const struct intel_crtc_state *crtc_state) 1164 { 1165 struct intel_display *display = to_intel_display(encoder); 1166 const struct intel_ddi_buf_trans *trans; 1167 enum phy phy = intel_encoder_to_phy(encoder); 1168 int n_entries, ln; 1169 u32 val; 1170 1171 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1172 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1173 return; 1174 1175 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1176 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1177 1178 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1179 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1180 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1181 intel_dp->hobl_active ? val : 0); 1182 } 1183 1184 /* Set PORT_TX_DW5 */ 1185 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1186 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1187 COEFF_POLARITY | CURSOR_PROGRAM | 1188 TAP2_DISABLE | TAP3_DISABLE); 1189 val |= SCALING_MODE_SEL(0x2); 1190 val |= RTERM_SELECT(0x6); 1191 val |= TAP3_DISABLE; 1192 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1193 1194 /* Program PORT_TX_DW2 */ 1195 for (ln = 0; ln < 4; ln++) { 1196 int level = intel_ddi_level(encoder, crtc_state, ln); 1197 1198 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1199 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1200 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1201 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1202 RCOMP_SCALAR(0x98)); 1203 } 1204 1205 /* Program PORT_TX_DW4 */ 1206 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1207 for (ln = 0; ln < 4; ln++) { 1208 int level = intel_ddi_level(encoder, crtc_state, ln); 1209 1210 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1211 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1212 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1213 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1214 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1215 } 1216 1217 /* Program PORT_TX_DW7 */ 1218 for (ln = 0; ln < 4; ln++) { 1219 int level = intel_ddi_level(encoder, crtc_state, ln); 1220 1221 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1222 N_SCALAR_MASK, 1223 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1224 } 1225 } 1226 1227 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1228 const struct intel_crtc_state *crtc_state) 1229 { 1230 struct intel_display *display = to_intel_display(encoder); 1231 enum phy phy = intel_encoder_to_phy(encoder); 1232 u32 val; 1233 int ln; 1234 1235 /* 1236 * 1. If port type is eDP or DP, 1237 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1238 * else clear to 0b. 1239 */ 1240 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1241 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1242 val &= ~COMMON_KEEPER_EN; 1243 else 1244 val |= COMMON_KEEPER_EN; 1245 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1246 1247 /* 2. Program loadgen select */ 1248 /* 1249 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1250 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1251 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1252 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1253 */ 1254 for (ln = 0; ln < 4; ln++) { 1255 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1256 LOADGEN_SELECT, 1257 icl_combo_phy_loadgen_select(crtc_state, ln)); 1258 } 1259 1260 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1261 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1262 0, SUS_CLOCK_CONFIG); 1263 1264 /* 4. Clear training enable to change swing values */ 1265 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1266 val &= ~TX_TRAINING_EN; 1267 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1268 1269 /* 5. Program swing and de-emphasis */ 1270 icl_ddi_combo_vswing_program(encoder, crtc_state); 1271 1272 /* 6. Set training enable to trigger update */ 1273 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1274 val |= TX_TRAINING_EN; 1275 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1276 } 1277 1278 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1279 const struct intel_crtc_state *crtc_state) 1280 { 1281 struct intel_display *display = to_intel_display(encoder); 1282 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1283 const struct intel_ddi_buf_trans *trans; 1284 int n_entries, ln; 1285 1286 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1287 return; 1288 1289 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1290 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1291 return; 1292 1293 for (ln = 0; ln < 2; ln++) { 1294 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1295 CRI_USE_FS32, 0); 1296 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1297 CRI_USE_FS32, 0); 1298 } 1299 1300 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1301 for (ln = 0; ln < 2; ln++) { 1302 int level; 1303 1304 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1305 1306 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1307 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1308 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1309 1310 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1311 1312 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1313 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1314 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1315 } 1316 1317 /* Program MG_TX_DRVCTRL with values from vswing table */ 1318 for (ln = 0; ln < 2; ln++) { 1319 int level; 1320 1321 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1322 1323 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1324 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1325 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1326 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1327 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1328 CRI_TXDEEMPH_OVERRIDE_EN); 1329 1330 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1331 1332 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1333 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1334 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1335 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1336 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1337 CRI_TXDEEMPH_OVERRIDE_EN); 1338 1339 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1340 } 1341 1342 /* 1343 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1344 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1345 * values from table for which TX1 and TX2 enabled. 1346 */ 1347 for (ln = 0; ln < 2; ln++) { 1348 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1349 CFG_LOW_RATE_LKREN_EN, 1350 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1351 } 1352 1353 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1354 for (ln = 0; ln < 2; ln++) { 1355 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1356 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1357 CFG_AMI_CK_DIV_OVERRIDE_EN, 1358 crtc_state->port_clock > 500000 ? 1359 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1360 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1361 1362 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1363 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1364 CFG_AMI_CK_DIV_OVERRIDE_EN, 1365 crtc_state->port_clock > 500000 ? 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1367 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1368 } 1369 1370 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1371 for (ln = 0; ln < 2; ln++) { 1372 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1373 0, CRI_CALCINIT); 1374 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1375 0, CRI_CALCINIT); 1376 } 1377 } 1378 1379 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1380 const struct intel_crtc_state *crtc_state) 1381 { 1382 struct intel_display *display = to_intel_display(encoder); 1383 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1384 const struct intel_ddi_buf_trans *trans; 1385 int n_entries, ln; 1386 1387 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1388 return; 1389 1390 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1391 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1392 return; 1393 1394 for (ln = 0; ln < 2; ln++) { 1395 int level; 1396 1397 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1398 1399 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1400 1401 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1402 DKL_TX_PRESHOOT_COEFF_MASK | 1403 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1404 DKL_TX_VSWING_CONTROL_MASK, 1405 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1406 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1407 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1408 1409 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1410 1411 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1412 DKL_TX_PRESHOOT_COEFF_MASK | 1413 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1414 DKL_TX_VSWING_CONTROL_MASK, 1415 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1416 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1417 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1418 1419 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1420 DKL_TX_DP20BITMODE, 0); 1421 1422 if (display->platform.alderlake_p) { 1423 u32 val; 1424 1425 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1426 if (ln == 0) { 1427 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1428 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1429 } else { 1430 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1431 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1432 } 1433 } else { 1434 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1435 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1436 } 1437 1438 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1439 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1440 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1441 val); 1442 } 1443 } 1444 } 1445 1446 static int translate_signal_level(struct intel_dp *intel_dp, 1447 u8 signal_levels) 1448 { 1449 struct intel_display *display = to_intel_display(intel_dp); 1450 int i; 1451 1452 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1453 if (index_to_dp_signal_levels[i] == signal_levels) 1454 return i; 1455 } 1456 1457 drm_WARN(display->drm, 1, 1458 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1459 signal_levels); 1460 1461 return 0; 1462 } 1463 1464 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1465 const struct intel_crtc_state *crtc_state, 1466 int lane) 1467 { 1468 u8 train_set = intel_dp->train_set[lane]; 1469 1470 if (intel_dp_is_uhbr(crtc_state)) { 1471 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1472 } else { 1473 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1474 DP_TRAIN_PRE_EMPHASIS_MASK); 1475 1476 return translate_signal_level(intel_dp, signal_levels); 1477 } 1478 } 1479 1480 int intel_ddi_level(struct intel_encoder *encoder, 1481 const struct intel_crtc_state *crtc_state, 1482 int lane) 1483 { 1484 struct intel_display *display = to_intel_display(encoder); 1485 const struct intel_ddi_buf_trans *trans; 1486 int level, n_entries; 1487 1488 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1489 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1490 return 0; 1491 1492 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1493 level = intel_ddi_hdmi_level(encoder, trans); 1494 else 1495 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1496 lane); 1497 1498 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1499 level = n_entries - 1; 1500 1501 return level; 1502 } 1503 1504 static void 1505 hsw_set_signal_levels(struct intel_encoder *encoder, 1506 const struct intel_crtc_state *crtc_state) 1507 { 1508 struct intel_display *display = to_intel_display(encoder); 1509 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1510 int level = intel_ddi_level(encoder, crtc_state, 0); 1511 enum port port = encoder->port; 1512 u32 signal_levels; 1513 1514 if (has_iboost(display)) 1515 skl_ddi_set_iboost(encoder, crtc_state, level); 1516 1517 /* HDMI ignores the rest */ 1518 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1519 return; 1520 1521 signal_levels = DDI_BUF_TRANS_SELECT(level); 1522 1523 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1524 signal_levels); 1525 1526 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1527 intel_dp->DP |= signal_levels; 1528 1529 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1530 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1531 } 1532 1533 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1534 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1535 { 1536 mutex_lock(&display->dpll.lock); 1537 1538 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1539 1540 /* 1541 * "This step and the step before must be 1542 * done with separate register writes." 1543 */ 1544 intel_de_rmw(display, reg, clk_off, 0); 1545 1546 mutex_unlock(&display->dpll.lock); 1547 } 1548 1549 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1550 u32 clk_off) 1551 { 1552 mutex_lock(&display->dpll.lock); 1553 1554 intel_de_rmw(display, reg, 0, clk_off); 1555 1556 mutex_unlock(&display->dpll.lock); 1557 } 1558 1559 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1560 u32 clk_off) 1561 { 1562 return !(intel_de_read(display, reg) & clk_off); 1563 } 1564 1565 static struct intel_dpll * 1566 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1567 u32 clk_sel_mask, u32 clk_sel_shift) 1568 { 1569 enum intel_dpll_id id; 1570 1571 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1572 1573 return intel_get_dpll_by_id(display, id); 1574 } 1575 1576 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1577 const struct intel_crtc_state *crtc_state) 1578 { 1579 struct intel_display *display = to_intel_display(encoder); 1580 const struct intel_dpll *pll = crtc_state->intel_dpll; 1581 enum phy phy = intel_encoder_to_phy(encoder); 1582 1583 if (drm_WARN_ON(display->drm, !pll)) 1584 return; 1585 1586 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1587 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1588 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1589 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1590 } 1591 1592 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1593 { 1594 struct intel_display *display = to_intel_display(encoder); 1595 enum phy phy = intel_encoder_to_phy(encoder); 1596 1597 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1598 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1599 } 1600 1601 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1602 { 1603 struct intel_display *display = to_intel_display(encoder); 1604 enum phy phy = intel_encoder_to_phy(encoder); 1605 1606 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1607 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1608 } 1609 1610 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1611 { 1612 struct intel_display *display = to_intel_display(encoder); 1613 enum phy phy = intel_encoder_to_phy(encoder); 1614 1615 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1616 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1617 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1618 } 1619 1620 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1621 const struct intel_crtc_state *crtc_state) 1622 { 1623 struct intel_display *display = to_intel_display(encoder); 1624 const struct intel_dpll *pll = crtc_state->intel_dpll; 1625 enum phy phy = intel_encoder_to_phy(encoder); 1626 1627 if (drm_WARN_ON(display->drm, !pll)) 1628 return; 1629 1630 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1631 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1632 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1633 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1634 } 1635 1636 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1637 { 1638 struct intel_display *display = to_intel_display(encoder); 1639 enum phy phy = intel_encoder_to_phy(encoder); 1640 1641 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1642 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1643 } 1644 1645 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1646 { 1647 struct intel_display *display = to_intel_display(encoder); 1648 enum phy phy = intel_encoder_to_phy(encoder); 1649 1650 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1651 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1652 } 1653 1654 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1655 { 1656 struct intel_display *display = to_intel_display(encoder); 1657 enum phy phy = intel_encoder_to_phy(encoder); 1658 1659 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1661 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1662 } 1663 1664 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1665 const struct intel_crtc_state *crtc_state) 1666 { 1667 struct intel_display *display = to_intel_display(encoder); 1668 const struct intel_dpll *pll = crtc_state->intel_dpll; 1669 enum phy phy = intel_encoder_to_phy(encoder); 1670 1671 if (drm_WARN_ON(display->drm, !pll)) 1672 return; 1673 1674 /* 1675 * If we fail this, something went very wrong: first 2 PLLs should be 1676 * used by first 2 phys and last 2 PLLs by last phys 1677 */ 1678 if (drm_WARN_ON(display->drm, 1679 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1680 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1681 return; 1682 1683 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1684 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1685 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1686 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1687 } 1688 1689 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1690 { 1691 struct intel_display *display = to_intel_display(encoder); 1692 enum phy phy = intel_encoder_to_phy(encoder); 1693 1694 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1695 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1696 } 1697 1698 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1699 { 1700 struct intel_display *display = to_intel_display(encoder); 1701 enum phy phy = intel_encoder_to_phy(encoder); 1702 1703 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1704 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1705 } 1706 1707 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1708 { 1709 struct intel_display *display = to_intel_display(encoder); 1710 enum phy phy = intel_encoder_to_phy(encoder); 1711 enum intel_dpll_id id; 1712 u32 val; 1713 1714 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1715 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1716 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1717 id = val; 1718 1719 /* 1720 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1721 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1722 * bit for phy C and D. 1723 */ 1724 if (phy >= PHY_C) 1725 id += DPLL_ID_DG1_DPLL2; 1726 1727 return intel_get_dpll_by_id(display, id); 1728 } 1729 1730 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1731 const struct intel_crtc_state *crtc_state) 1732 { 1733 struct intel_display *display = to_intel_display(encoder); 1734 const struct intel_dpll *pll = crtc_state->intel_dpll; 1735 enum phy phy = intel_encoder_to_phy(encoder); 1736 1737 if (drm_WARN_ON(display->drm, !pll)) 1738 return; 1739 1740 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1741 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1742 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1743 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1744 } 1745 1746 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1747 { 1748 struct intel_display *display = to_intel_display(encoder); 1749 enum phy phy = intel_encoder_to_phy(encoder); 1750 1751 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1752 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1753 } 1754 1755 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1756 { 1757 struct intel_display *display = to_intel_display(encoder); 1758 enum phy phy = intel_encoder_to_phy(encoder); 1759 1760 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1761 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1762 } 1763 1764 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1765 { 1766 struct intel_display *display = to_intel_display(encoder); 1767 enum phy phy = intel_encoder_to_phy(encoder); 1768 1769 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1771 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1772 } 1773 1774 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1775 const struct intel_crtc_state *crtc_state) 1776 { 1777 struct intel_display *display = to_intel_display(encoder); 1778 const struct intel_dpll *pll = crtc_state->intel_dpll; 1779 enum port port = encoder->port; 1780 1781 if (drm_WARN_ON(display->drm, !pll)) 1782 return; 1783 1784 /* 1785 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1786 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1787 */ 1788 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1789 1790 icl_ddi_combo_enable_clock(encoder, crtc_state); 1791 } 1792 1793 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1794 { 1795 struct intel_display *display = to_intel_display(encoder); 1796 enum port port = encoder->port; 1797 1798 icl_ddi_combo_disable_clock(encoder); 1799 1800 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1801 } 1802 1803 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1804 { 1805 struct intel_display *display = to_intel_display(encoder); 1806 enum port port = encoder->port; 1807 u32 tmp; 1808 1809 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1810 1811 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1812 return false; 1813 1814 return icl_ddi_combo_is_clock_enabled(encoder); 1815 } 1816 1817 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1818 const struct intel_crtc_state *crtc_state) 1819 { 1820 struct intel_display *display = to_intel_display(encoder); 1821 const struct intel_dpll *pll = crtc_state->intel_dpll; 1822 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1823 enum port port = encoder->port; 1824 1825 if (drm_WARN_ON(display->drm, !pll)) 1826 return; 1827 1828 intel_de_write(display, DDI_CLK_SEL(port), 1829 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1830 1831 mutex_lock(&display->dpll.lock); 1832 1833 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1834 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1835 1836 mutex_unlock(&display->dpll.lock); 1837 } 1838 1839 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1840 { 1841 struct intel_display *display = to_intel_display(encoder); 1842 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1843 enum port port = encoder->port; 1844 1845 mutex_lock(&display->dpll.lock); 1846 1847 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1848 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1849 1850 mutex_unlock(&display->dpll.lock); 1851 1852 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1853 } 1854 1855 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1856 { 1857 struct intel_display *display = to_intel_display(encoder); 1858 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1859 enum port port = encoder->port; 1860 u32 tmp; 1861 1862 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1863 1864 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1865 return false; 1866 1867 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1868 1869 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1870 } 1871 1872 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1873 { 1874 struct intel_display *display = to_intel_display(encoder); 1875 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1876 enum port port = encoder->port; 1877 enum intel_dpll_id id; 1878 u32 tmp; 1879 1880 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1881 1882 switch (tmp & DDI_CLK_SEL_MASK) { 1883 case DDI_CLK_SEL_TBT_162: 1884 case DDI_CLK_SEL_TBT_270: 1885 case DDI_CLK_SEL_TBT_540: 1886 case DDI_CLK_SEL_TBT_810: 1887 id = DPLL_ID_ICL_TBTPLL; 1888 break; 1889 case DDI_CLK_SEL_MG: 1890 id = icl_tc_port_to_pll_id(tc_port); 1891 break; 1892 default: 1893 MISSING_CASE(tmp); 1894 fallthrough; 1895 case DDI_CLK_SEL_NONE: 1896 return NULL; 1897 } 1898 1899 return intel_get_dpll_by_id(display, id); 1900 } 1901 1902 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1903 { 1904 struct intel_display *display = to_intel_display(encoder->base.dev); 1905 enum intel_dpll_id id; 1906 1907 switch (encoder->port) { 1908 case PORT_A: 1909 id = DPLL_ID_SKL_DPLL0; 1910 break; 1911 case PORT_B: 1912 id = DPLL_ID_SKL_DPLL1; 1913 break; 1914 case PORT_C: 1915 id = DPLL_ID_SKL_DPLL2; 1916 break; 1917 default: 1918 MISSING_CASE(encoder->port); 1919 return NULL; 1920 } 1921 1922 return intel_get_dpll_by_id(display, id); 1923 } 1924 1925 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1926 const struct intel_crtc_state *crtc_state) 1927 { 1928 struct intel_display *display = to_intel_display(encoder); 1929 const struct intel_dpll *pll = crtc_state->intel_dpll; 1930 enum port port = encoder->port; 1931 1932 if (drm_WARN_ON(display->drm, !pll)) 1933 return; 1934 1935 mutex_lock(&display->dpll.lock); 1936 1937 intel_de_rmw(display, DPLL_CTRL2, 1938 DPLL_CTRL2_DDI_CLK_OFF(port) | 1939 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1940 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1941 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1942 1943 mutex_unlock(&display->dpll.lock); 1944 } 1945 1946 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1947 { 1948 struct intel_display *display = to_intel_display(encoder); 1949 enum port port = encoder->port; 1950 1951 mutex_lock(&display->dpll.lock); 1952 1953 intel_de_rmw(display, DPLL_CTRL2, 1954 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1955 1956 mutex_unlock(&display->dpll.lock); 1957 } 1958 1959 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1960 { 1961 struct intel_display *display = to_intel_display(encoder); 1962 enum port port = encoder->port; 1963 1964 /* 1965 * FIXME Not sure if the override affects both 1966 * the PLL selection and the CLK_OFF bit. 1967 */ 1968 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1969 } 1970 1971 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1972 { 1973 struct intel_display *display = to_intel_display(encoder); 1974 enum port port = encoder->port; 1975 enum intel_dpll_id id; 1976 u32 tmp; 1977 1978 tmp = intel_de_read(display, DPLL_CTRL2); 1979 1980 /* 1981 * FIXME Not sure if the override affects both 1982 * the PLL selection and the CLK_OFF bit. 1983 */ 1984 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1985 return NULL; 1986 1987 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1988 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1989 1990 return intel_get_dpll_by_id(display, id); 1991 } 1992 1993 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1994 const struct intel_crtc_state *crtc_state) 1995 { 1996 struct intel_display *display = to_intel_display(encoder); 1997 const struct intel_dpll *pll = crtc_state->intel_dpll; 1998 enum port port = encoder->port; 1999 2000 if (drm_WARN_ON(display->drm, !pll)) 2001 return; 2002 2003 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2004 } 2005 2006 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2007 { 2008 struct intel_display *display = to_intel_display(encoder); 2009 enum port port = encoder->port; 2010 2011 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2012 } 2013 2014 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2015 { 2016 struct intel_display *display = to_intel_display(encoder); 2017 enum port port = encoder->port; 2018 2019 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2020 } 2021 2022 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2023 { 2024 struct intel_display *display = to_intel_display(encoder); 2025 enum port port = encoder->port; 2026 enum intel_dpll_id id; 2027 u32 tmp; 2028 2029 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2030 2031 switch (tmp & PORT_CLK_SEL_MASK) { 2032 case PORT_CLK_SEL_WRPLL1: 2033 id = DPLL_ID_WRPLL1; 2034 break; 2035 case PORT_CLK_SEL_WRPLL2: 2036 id = DPLL_ID_WRPLL2; 2037 break; 2038 case PORT_CLK_SEL_SPLL: 2039 id = DPLL_ID_SPLL; 2040 break; 2041 case PORT_CLK_SEL_LCPLL_810: 2042 id = DPLL_ID_LCPLL_810; 2043 break; 2044 case PORT_CLK_SEL_LCPLL_1350: 2045 id = DPLL_ID_LCPLL_1350; 2046 break; 2047 case PORT_CLK_SEL_LCPLL_2700: 2048 id = DPLL_ID_LCPLL_2700; 2049 break; 2050 default: 2051 MISSING_CASE(tmp); 2052 fallthrough; 2053 case PORT_CLK_SEL_NONE: 2054 return NULL; 2055 } 2056 2057 return intel_get_dpll_by_id(display, id); 2058 } 2059 2060 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2061 const struct intel_crtc_state *crtc_state) 2062 { 2063 if (encoder->enable_clock) 2064 encoder->enable_clock(encoder, crtc_state); 2065 } 2066 2067 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2068 { 2069 if (encoder->disable_clock) 2070 encoder->disable_clock(encoder); 2071 } 2072 2073 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2074 { 2075 struct intel_display *display = to_intel_display(encoder); 2076 u32 port_mask; 2077 bool ddi_clk_needed; 2078 2079 /* 2080 * In case of DP MST, we sanitize the primary encoder only, not the 2081 * virtual ones. 2082 */ 2083 if (encoder->type == INTEL_OUTPUT_DP_MST) 2084 return; 2085 2086 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2087 u8 pipe_mask; 2088 bool is_mst; 2089 2090 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2091 /* 2092 * In the unlikely case that BIOS enables DP in MST mode, just 2093 * warn since our MST HW readout is incomplete. 2094 */ 2095 if (drm_WARN_ON(display->drm, is_mst)) 2096 return; 2097 } 2098 2099 port_mask = BIT(encoder->port); 2100 ddi_clk_needed = encoder->base.crtc; 2101 2102 if (encoder->type == INTEL_OUTPUT_DSI) { 2103 struct intel_encoder *other_encoder; 2104 2105 port_mask = intel_dsi_encoder_ports(encoder); 2106 /* 2107 * Sanity check that we haven't incorrectly registered another 2108 * encoder using any of the ports of this DSI encoder. 2109 */ 2110 for_each_intel_encoder(display->drm, other_encoder) { 2111 if (other_encoder == encoder) 2112 continue; 2113 2114 if (drm_WARN_ON(display->drm, 2115 port_mask & BIT(other_encoder->port))) 2116 return; 2117 } 2118 /* 2119 * For DSI we keep the ddi clocks gated 2120 * except during enable/disable sequence. 2121 */ 2122 ddi_clk_needed = false; 2123 } 2124 2125 if (ddi_clk_needed || !encoder->is_clock_enabled || 2126 !encoder->is_clock_enabled(encoder)) 2127 return; 2128 2129 drm_dbg_kms(display->drm, 2130 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2131 encoder->base.base.id, encoder->base.name); 2132 2133 encoder->disable_clock(encoder); 2134 } 2135 2136 static void 2137 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2138 enum tc_port tc_port, u32 ln0, u32 ln1) 2139 { 2140 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2141 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2142 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2143 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2144 } 2145 2146 static void 2147 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2148 const struct intel_crtc_state *crtc_state) 2149 { 2150 struct intel_display *display = to_intel_display(crtc_state); 2151 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2152 u32 ln0, ln1, pin_assignment; 2153 u8 width; 2154 2155 if (DISPLAY_VER(display) >= 14) 2156 return; 2157 2158 if (!intel_encoder_is_tc(&dig_port->base) || 2159 intel_tc_port_in_tbt_alt_mode(dig_port)) 2160 return; 2161 2162 if (DISPLAY_VER(display) >= 12) { 2163 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2164 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2165 } else { 2166 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2167 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2168 } 2169 2170 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2171 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2172 2173 /* DPPATC */ 2174 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2175 width = crtc_state->lane_count; 2176 2177 switch (pin_assignment) { 2178 case 0x0: 2179 drm_WARN_ON(display->drm, 2180 !intel_tc_port_in_legacy_mode(dig_port)); 2181 if (width == 1) { 2182 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2183 } else { 2184 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2185 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2186 } 2187 break; 2188 case 0x1: 2189 if (width == 4) { 2190 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2191 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2192 } 2193 break; 2194 case 0x2: 2195 if (width == 2) { 2196 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2197 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2198 } 2199 break; 2200 case 0x3: 2201 case 0x5: 2202 if (width == 1) { 2203 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2204 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2205 } else { 2206 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2207 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2208 } 2209 break; 2210 case 0x4: 2211 case 0x6: 2212 if (width == 1) { 2213 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2214 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2215 } else { 2216 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2217 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2218 } 2219 break; 2220 default: 2221 MISSING_CASE(pin_assignment); 2222 } 2223 2224 if (DISPLAY_VER(display) >= 12) { 2225 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2226 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2227 /* WA_14018221282 */ 2228 if (IS_DISPLAY_VER(display, 12, 13)) 2229 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2230 2231 } else { 2232 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2233 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2234 } 2235 } 2236 2237 static enum transcoder 2238 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2239 { 2240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2241 return crtc_state->mst_master_transcoder; 2242 else 2243 return crtc_state->cpu_transcoder; 2244 } 2245 2246 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2247 const struct intel_crtc_state *crtc_state) 2248 { 2249 struct intel_display *display = to_intel_display(encoder); 2250 2251 if (DISPLAY_VER(display) >= 12) 2252 return TGL_DP_TP_CTL(display, 2253 tgl_dp_tp_transcoder(crtc_state)); 2254 else 2255 return DP_TP_CTL(encoder->port); 2256 } 2257 2258 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2259 const struct intel_crtc_state *crtc_state) 2260 { 2261 struct intel_display *display = to_intel_display(encoder); 2262 2263 if (DISPLAY_VER(display) >= 12) 2264 return TGL_DP_TP_STATUS(display, 2265 tgl_dp_tp_transcoder(crtc_state)); 2266 else 2267 return DP_TP_STATUS(encoder->port); 2268 } 2269 2270 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2271 const struct intel_crtc_state *crtc_state) 2272 { 2273 struct intel_display *display = to_intel_display(encoder); 2274 2275 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2276 DP_TP_STATUS_ACT_SENT); 2277 } 2278 2279 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2280 const struct intel_crtc_state *crtc_state) 2281 { 2282 struct intel_display *display = to_intel_display(encoder); 2283 2284 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2285 DP_TP_STATUS_ACT_SENT, 1)) 2286 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2287 } 2288 2289 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2290 const struct intel_crtc_state *crtc_state, 2291 bool enable) 2292 { 2293 struct intel_display *display = to_intel_display(intel_dp); 2294 2295 if (!crtc_state->vrr.enable) 2296 return; 2297 2298 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2299 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2300 drm_dbg_kms(display->drm, 2301 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2302 str_enable_disable(enable)); 2303 } 2304 2305 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2306 const struct intel_crtc_state *crtc_state, 2307 bool enable) 2308 { 2309 struct intel_display *display = to_intel_display(intel_dp); 2310 2311 if (!crtc_state->fec_enable) 2312 return; 2313 2314 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2315 enable ? DP_FEC_READY : 0) <= 0) 2316 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2317 str_enabled_disabled(enable)); 2318 2319 if (enable && 2320 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2321 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2322 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2323 } 2324 2325 static int read_fec_detected_status(struct drm_dp_aux *aux) 2326 { 2327 int ret; 2328 u8 status; 2329 2330 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2331 if (ret < 0) 2332 return ret; 2333 2334 return status; 2335 } 2336 2337 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2338 { 2339 struct intel_display *display = to_intel_display(aux->drm_dev); 2340 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2341 int status; 2342 int err; 2343 2344 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2345 status & mask || status < 0, 2346 10000, 200000); 2347 2348 if (err || status < 0) { 2349 drm_dbg_kms(display->drm, 2350 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2351 str_enabled_disabled(enabled), err, status); 2352 return err ? err : status; 2353 } 2354 2355 return 0; 2356 } 2357 2358 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2359 const struct intel_crtc_state *crtc_state, 2360 bool enabled) 2361 { 2362 struct intel_display *display = to_intel_display(encoder); 2363 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2364 int ret; 2365 2366 if (!crtc_state->fec_enable) 2367 return 0; 2368 2369 if (enabled) 2370 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2371 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2372 else 2373 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2374 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2375 2376 if (ret) { 2377 drm_err(display->drm, 2378 "Timeout waiting for FEC live state to get %s\n", 2379 str_enabled_disabled(enabled)); 2380 return ret; 2381 } 2382 /* 2383 * At least the Synoptics MST hub doesn't set the detected flag for 2384 * FEC decoding disabling so skip waiting for that. 2385 */ 2386 if (enabled) { 2387 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2388 if (ret) 2389 return ret; 2390 } 2391 2392 return 0; 2393 } 2394 2395 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2396 const struct intel_crtc_state *crtc_state) 2397 { 2398 struct intel_display *display = to_intel_display(encoder); 2399 int i; 2400 int ret; 2401 2402 if (!crtc_state->fec_enable) 2403 return; 2404 2405 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2406 0, DP_TP_CTL_FEC_ENABLE); 2407 2408 if (DISPLAY_VER(display) < 30) 2409 return; 2410 2411 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2412 if (!ret) 2413 return; 2414 2415 for (i = 0; i < 3; i++) { 2416 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2417 2418 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2419 DP_TP_CTL_FEC_ENABLE, 0); 2420 2421 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2422 if (ret) 2423 continue; 2424 2425 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2426 0, DP_TP_CTL_FEC_ENABLE); 2427 2428 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2429 if (!ret) 2430 return; 2431 } 2432 2433 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2434 } 2435 2436 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2437 const struct intel_crtc_state *crtc_state) 2438 { 2439 struct intel_display *display = to_intel_display(encoder); 2440 2441 if (!crtc_state->fec_enable) 2442 return; 2443 2444 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2445 DP_TP_CTL_FEC_ENABLE, 0); 2446 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2447 } 2448 2449 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2450 const struct intel_crtc_state *crtc_state) 2451 { 2452 struct intel_display *display = to_intel_display(encoder); 2453 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2454 2455 if (intel_encoder_is_combo(encoder)) { 2456 enum phy phy = intel_encoder_to_phy(encoder); 2457 2458 intel_combo_phy_power_up_lanes(display, phy, false, 2459 crtc_state->lane_count, 2460 dig_port->lane_reversal); 2461 } 2462 } 2463 2464 /* 2465 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2466 * platforms. 2467 */ 2468 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2469 { 2470 if (DISPLAY_VER(display) > 20) 2471 return ~0; 2472 else if (display->platform.alderlake_p) 2473 return BIT(PIPE_A) | BIT(PIPE_B); 2474 else 2475 return BIT(PIPE_A); 2476 } 2477 2478 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2479 struct intel_crtc_state *pipe_config) 2480 { 2481 struct intel_display *display = to_intel_display(pipe_config); 2482 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2483 enum pipe pipe = crtc->pipe; 2484 u32 dss1; 2485 2486 if (!HAS_MSO(display)) 2487 return; 2488 2489 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2490 2491 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2492 if (!pipe_config->splitter.enable) 2493 return; 2494 2495 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2496 pipe_config->splitter.enable = false; 2497 return; 2498 } 2499 2500 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2501 default: 2502 drm_WARN(display->drm, true, 2503 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2504 fallthrough; 2505 case SPLITTER_CONFIGURATION_2_SEGMENT: 2506 pipe_config->splitter.link_count = 2; 2507 break; 2508 case SPLITTER_CONFIGURATION_4_SEGMENT: 2509 pipe_config->splitter.link_count = 4; 2510 break; 2511 } 2512 2513 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2514 } 2515 2516 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2517 { 2518 struct intel_display *display = to_intel_display(crtc_state); 2519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2520 enum pipe pipe = crtc->pipe; 2521 u32 dss1 = 0; 2522 2523 if (!HAS_MSO(display)) 2524 return; 2525 2526 if (crtc_state->splitter.enable) { 2527 dss1 |= SPLITTER_ENABLE; 2528 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2529 if (crtc_state->splitter.link_count == 2) 2530 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2531 else 2532 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2533 } 2534 2535 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2536 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2537 OVERLAP_PIXELS_MASK, dss1); 2538 } 2539 2540 static void 2541 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2542 { 2543 struct intel_display *display = to_intel_display(encoder); 2544 enum port port = encoder->port; 2545 i915_reg_t reg; 2546 u32 set_bits, wait_bits; 2547 2548 if (DISPLAY_VER(display) < 14) 2549 return; 2550 2551 if (DISPLAY_VER(display) >= 20) { 2552 reg = DDI_BUF_CTL(port); 2553 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2554 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2555 } else { 2556 reg = XELPDP_PORT_BUF_CTL1(display, port); 2557 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2558 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2559 } 2560 2561 intel_de_rmw(display, reg, 0, set_bits); 2562 if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { 2563 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2564 port_name(port)); 2565 } 2566 } 2567 2568 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2569 const struct intel_crtc_state *crtc_state) 2570 { 2571 struct intel_display *display = to_intel_display(encoder); 2572 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2573 enum port port = encoder->port; 2574 u32 val = 0; 2575 2576 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2577 2578 if (intel_dp_is_uhbr(crtc_state)) 2579 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2580 else 2581 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2582 2583 if (dig_port->lane_reversal) 2584 val |= XELPDP_PORT_REVERSAL; 2585 2586 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2587 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2588 val); 2589 } 2590 2591 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2592 { 2593 struct intel_display *display = to_intel_display(encoder); 2594 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2595 u32 val; 2596 2597 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2598 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2599 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2600 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2601 } 2602 2603 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2604 struct intel_encoder *encoder, 2605 const struct intel_crtc_state *crtc_state, 2606 const struct drm_connector_state *conn_state) 2607 { 2608 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2609 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2610 bool transparent_mode; 2611 int ret; 2612 2613 intel_dp_set_link_params(intel_dp, 2614 crtc_state->port_clock, 2615 crtc_state->lane_count); 2616 2617 /* 2618 * We only configure what the register value will be here. Actual 2619 * enabling happens during link training farther down. 2620 */ 2621 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2622 2623 /* 2624 * 1. Enable Power Wells 2625 * 2626 * This was handled at the beginning of intel_atomic_commit_tail(), 2627 * before we called down into this function. 2628 */ 2629 2630 /* 2. PMdemand was already set */ 2631 2632 /* 3. Select Thunderbolt */ 2633 mtl_port_buf_ctl_io_selection(encoder); 2634 2635 /* 4. Enable Panel Power if PPS is required */ 2636 intel_pps_on(intel_dp); 2637 2638 /* 5. Enable the port PLL */ 2639 intel_ddi_enable_clock(encoder, crtc_state); 2640 2641 /* 2642 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2643 * Transcoder. 2644 */ 2645 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2646 2647 /* 2648 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2649 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2650 * Transport Select 2651 */ 2652 intel_ddi_config_transcoder_func(encoder, crtc_state); 2653 2654 /* 2655 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2656 */ 2657 intel_ddi_mso_configure(crtc_state); 2658 2659 if (!is_mst) 2660 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2661 2662 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2663 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2664 2665 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2666 if (!is_mst) 2667 intel_dp_sink_enable_decompression(state, 2668 to_intel_connector(conn_state->connector), 2669 crtc_state); 2670 2671 /* 2672 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2673 * in the FEC_CONFIGURATION register to 1 before initiating link 2674 * training 2675 */ 2676 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2677 2678 intel_dp_check_frl_training(intel_dp); 2679 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2680 2681 /* 2682 * 6. The rest of the below are substeps under the bspec's "Enable and 2683 * Train Display Port" step. Note that steps that are specific to 2684 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2685 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2686 * us when active_mst_links==0, so any steps designated for "single 2687 * stream or multi-stream master transcoder" can just be performed 2688 * unconditionally here. 2689 * 2690 * mtl_ddi_prepare_link_retrain() that is called by 2691 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2692 * 6.i and 6.j 2693 * 2694 * 6.k Follow DisplayPort specification training sequence (see notes for 2695 * failure handling) 2696 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2697 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2698 * (timeout after 800 us) 2699 */ 2700 intel_dp_start_link_train(state, intel_dp, crtc_state); 2701 2702 /* 6.n Set DP_TP_CTL link training to Normal */ 2703 if (!is_trans_port_sync_mode(crtc_state)) 2704 intel_dp_stop_link_train(intel_dp, crtc_state); 2705 2706 /* 6.o Configure and enable FEC if needed */ 2707 intel_ddi_enable_fec(encoder, crtc_state); 2708 2709 /* 7.a 128b/132b SST. */ 2710 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2711 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2712 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2713 if (ret < 0) 2714 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2715 } 2716 2717 if (!is_mst) 2718 intel_dsc_dp_pps_write(encoder, crtc_state); 2719 } 2720 2721 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2722 struct intel_encoder *encoder, 2723 const struct intel_crtc_state *crtc_state, 2724 const struct drm_connector_state *conn_state) 2725 { 2726 struct intel_display *display = to_intel_display(encoder); 2727 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2728 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2729 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2730 int ret; 2731 2732 intel_dp_set_link_params(intel_dp, 2733 crtc_state->port_clock, 2734 crtc_state->lane_count); 2735 2736 /* 2737 * We only configure what the register value will be here. Actual 2738 * enabling happens during link training farther down. 2739 */ 2740 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2741 2742 /* 2743 * 1. Enable Power Wells 2744 * 2745 * This was handled at the beginning of intel_atomic_commit_tail(), 2746 * before we called down into this function. 2747 */ 2748 2749 /* 2. Enable Panel Power if PPS is required */ 2750 intel_pps_on(intel_dp); 2751 2752 /* 2753 * 3. For non-TBT Type-C ports, set FIA lane count 2754 * (DFLEXDPSP.DPX4TXLATC) 2755 * 2756 * This was done before tgl_ddi_pre_enable_dp by 2757 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2758 */ 2759 2760 /* 2761 * 4. Enable the port PLL. 2762 * 2763 * The PLL enabling itself was already done before this function by 2764 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2765 * configure the PLL to port mapping here. 2766 */ 2767 intel_ddi_enable_clock(encoder, crtc_state); 2768 2769 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2770 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2771 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2772 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2773 dig_port->ddi_io_power_domain); 2774 } 2775 2776 /* 6. Program DP_MODE */ 2777 icl_program_mg_dp_mode(dig_port, crtc_state); 2778 2779 /* 2780 * 7. The rest of the below are substeps under the bspec's "Enable and 2781 * Train Display Port" step. Note that steps that are specific to 2782 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2783 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2784 * us when active_mst_links==0, so any steps designated for "single 2785 * stream or multi-stream master transcoder" can just be performed 2786 * unconditionally here. 2787 */ 2788 2789 /* 2790 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2791 * Transcoder. 2792 */ 2793 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2794 2795 /* 2796 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2797 * Transport Select 2798 */ 2799 intel_ddi_config_transcoder_func(encoder, crtc_state); 2800 2801 /* 2802 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2803 * selected 2804 * 2805 * This will be handled by the intel_dp_start_link_train() farther 2806 * down this function. 2807 */ 2808 2809 /* 7.e Configure voltage swing and related IO settings */ 2810 encoder->set_signal_levels(encoder, crtc_state); 2811 2812 /* 2813 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2814 * the used lanes of the DDI. 2815 */ 2816 intel_ddi_power_up_lanes(encoder, crtc_state); 2817 2818 /* 2819 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2820 */ 2821 intel_ddi_mso_configure(crtc_state); 2822 2823 if (!is_mst) 2824 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2825 2826 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2827 if (!is_mst) 2828 intel_dp_sink_enable_decompression(state, 2829 to_intel_connector(conn_state->connector), 2830 crtc_state); 2831 /* 2832 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2833 * in the FEC_CONFIGURATION register to 1 before initiating link 2834 * training 2835 */ 2836 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2837 2838 intel_dp_check_frl_training(intel_dp); 2839 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2840 2841 /* 2842 * 7.i Follow DisplayPort specification training sequence (see notes for 2843 * failure handling) 2844 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2845 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2846 * (timeout after 800 us) 2847 */ 2848 intel_dp_start_link_train(state, intel_dp, crtc_state); 2849 2850 /* 7.k Set DP_TP_CTL link training to Normal */ 2851 if (!is_trans_port_sync_mode(crtc_state)) 2852 intel_dp_stop_link_train(intel_dp, crtc_state); 2853 2854 /* 7.l Configure and enable FEC if needed */ 2855 intel_ddi_enable_fec(encoder, crtc_state); 2856 2857 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2858 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2859 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2860 if (ret < 0) 2861 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2862 } 2863 2864 if (!is_mst) 2865 intel_dsc_dp_pps_write(encoder, crtc_state); 2866 } 2867 2868 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2869 struct intel_encoder *encoder, 2870 const struct intel_crtc_state *crtc_state, 2871 const struct drm_connector_state *conn_state) 2872 { 2873 struct intel_display *display = to_intel_display(encoder); 2874 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2875 enum port port = encoder->port; 2876 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2877 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2878 2879 if (DISPLAY_VER(display) < 11) 2880 drm_WARN_ON(display->drm, 2881 is_mst && (port == PORT_A || port == PORT_E)); 2882 else 2883 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2884 2885 intel_dp_set_link_params(intel_dp, 2886 crtc_state->port_clock, 2887 crtc_state->lane_count); 2888 2889 /* 2890 * We only configure what the register value will be here. Actual 2891 * enabling happens during link training farther down. 2892 */ 2893 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2894 2895 intel_pps_on(intel_dp); 2896 2897 intel_ddi_enable_clock(encoder, crtc_state); 2898 2899 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2900 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2901 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2902 dig_port->ddi_io_power_domain); 2903 } 2904 2905 icl_program_mg_dp_mode(dig_port, crtc_state); 2906 2907 if (has_buf_trans_select(display)) 2908 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2909 2910 encoder->set_signal_levels(encoder, crtc_state); 2911 2912 intel_ddi_power_up_lanes(encoder, crtc_state); 2913 2914 if (!is_mst) 2915 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2916 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2917 if (!is_mst) 2918 intel_dp_sink_enable_decompression(state, 2919 to_intel_connector(conn_state->connector), 2920 crtc_state); 2921 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2922 intel_dp_start_link_train(state, intel_dp, crtc_state); 2923 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2924 !is_trans_port_sync_mode(crtc_state)) 2925 intel_dp_stop_link_train(intel_dp, crtc_state); 2926 2927 intel_ddi_enable_fec(encoder, crtc_state); 2928 2929 if (!is_mst) { 2930 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2931 intel_dsc_dp_pps_write(encoder, crtc_state); 2932 } 2933 } 2934 2935 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2936 struct intel_encoder *encoder, 2937 const struct intel_crtc_state *crtc_state, 2938 const struct drm_connector_state *conn_state) 2939 { 2940 struct intel_display *display = to_intel_display(encoder); 2941 2942 if (HAS_DP20(display)) 2943 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2944 crtc_state); 2945 2946 /* Panel replay has to be enabled in sink dpcd before link training. */ 2947 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2948 2949 if (DISPLAY_VER(display) >= 14) 2950 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2951 else if (DISPLAY_VER(display) >= 12) 2952 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2953 else 2954 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2955 2956 /* MST will call a setting of MSA after an allocating of Virtual Channel 2957 * from MST encoder pre_enable callback. 2958 */ 2959 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2960 intel_ddi_set_dp_msa(crtc_state, conn_state); 2961 } 2962 2963 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2964 struct intel_encoder *encoder, 2965 const struct intel_crtc_state *crtc_state, 2966 const struct drm_connector_state *conn_state) 2967 { 2968 struct intel_display *display = to_intel_display(encoder); 2969 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2970 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2971 2972 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2973 intel_ddi_enable_clock(encoder, crtc_state); 2974 2975 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2976 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2977 dig_port->ddi_io_power_domain); 2978 2979 icl_program_mg_dp_mode(dig_port, crtc_state); 2980 2981 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2982 2983 dig_port->set_infoframes(encoder, 2984 crtc_state->has_infoframe, 2985 crtc_state, conn_state); 2986 } 2987 2988 /* 2989 * Note: Also called from the ->pre_enable of the first active MST stream 2990 * encoder on its primary encoder. 2991 * 2992 * When called from DP MST code: 2993 * 2994 * - conn_state will be NULL 2995 * 2996 * - encoder will be the primary encoder (i.e. mst->primary) 2997 * 2998 * - the main connector associated with this port won't be active or linked to a 2999 * crtc 3000 * 3001 * - crtc_state will be the state of the first stream to be activated on this 3002 * port, and it may not be the same stream that will be deactivated last, but 3003 * each stream should have a state that is identical when it comes to the DP 3004 * link parameters. 3005 */ 3006 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3007 struct intel_encoder *encoder, 3008 const struct intel_crtc_state *crtc_state, 3009 const struct drm_connector_state *conn_state) 3010 { 3011 struct intel_display *display = to_intel_display(state); 3012 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3013 enum pipe pipe = crtc->pipe; 3014 3015 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3016 3017 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3018 3019 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3020 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3021 conn_state); 3022 } else { 3023 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3024 3025 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3026 conn_state); 3027 3028 /* FIXME precompute everything properly */ 3029 /* FIXME how do we turn infoframes off again? */ 3030 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3031 dig_port->set_infoframes(encoder, 3032 crtc_state->has_infoframe, 3033 crtc_state, conn_state); 3034 } 3035 } 3036 3037 static void 3038 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3039 { 3040 struct intel_display *display = to_intel_display(encoder); 3041 enum port port = encoder->port; 3042 i915_reg_t reg; 3043 u32 clr_bits, wait_bits; 3044 3045 if (DISPLAY_VER(display) < 14) 3046 return; 3047 3048 if (DISPLAY_VER(display) >= 20) { 3049 reg = DDI_BUF_CTL(port); 3050 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3051 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3052 } else { 3053 reg = XELPDP_PORT_BUF_CTL1(display, port); 3054 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3055 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3056 } 3057 3058 intel_de_rmw(display, reg, clr_bits, 0); 3059 if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) 3060 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3061 port_name(port)); 3062 } 3063 3064 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3065 { 3066 struct intel_display *display = to_intel_display(encoder); 3067 enum port port = encoder->port; 3068 3069 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3070 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3071 3072 intel_wait_ddi_buf_active(encoder); 3073 } 3074 3075 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3076 const struct intel_crtc_state *crtc_state) 3077 { 3078 struct intel_display *display = to_intel_display(encoder); 3079 enum port port = encoder->port; 3080 3081 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3082 3083 if (DISPLAY_VER(display) >= 14) 3084 intel_wait_ddi_buf_idle(display, port); 3085 3086 mtl_ddi_disable_d2d(encoder); 3087 3088 if (intel_crtc_has_dp_encoder(crtc_state)) { 3089 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3090 DP_TP_CTL_ENABLE, 0); 3091 } 3092 3093 intel_ddi_disable_fec(encoder, crtc_state); 3094 3095 if (DISPLAY_VER(display) < 14) 3096 intel_wait_ddi_buf_idle(display, port); 3097 3098 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3099 } 3100 3101 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3102 struct intel_encoder *encoder, 3103 const struct intel_crtc_state *old_crtc_state, 3104 const struct drm_connector_state *old_conn_state) 3105 { 3106 struct intel_display *display = to_intel_display(encoder); 3107 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3108 struct intel_dp *intel_dp = &dig_port->dp; 3109 intel_wakeref_t wakeref; 3110 bool is_mst = intel_crtc_has_type(old_crtc_state, 3111 INTEL_OUTPUT_DP_MST); 3112 3113 if (!is_mst) 3114 intel_dp_set_infoframes(encoder, false, 3115 old_crtc_state, old_conn_state); 3116 3117 /* 3118 * Power down sink before disabling the port, otherwise we end 3119 * up getting interrupts from the sink on detecting link loss. 3120 */ 3121 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3122 3123 if (DISPLAY_VER(display) >= 12) { 3124 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3125 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3126 3127 intel_de_rmw(display, 3128 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3129 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3130 0); 3131 } 3132 } else { 3133 if (!is_mst) 3134 intel_ddi_disable_transcoder_clock(old_crtc_state); 3135 } 3136 3137 intel_ddi_buf_disable(encoder, old_crtc_state); 3138 3139 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3140 3141 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3142 3143 /* 3144 * From TGL spec: "If single stream or multi-stream master transcoder: 3145 * Configure Transcoder Clock select to direct no clock to the 3146 * transcoder" 3147 */ 3148 if (DISPLAY_VER(display) >= 12) 3149 intel_ddi_disable_transcoder_clock(old_crtc_state); 3150 3151 intel_pps_vdd_on(intel_dp); 3152 intel_pps_off(intel_dp); 3153 3154 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3155 3156 if (wakeref) 3157 intel_display_power_put(display, 3158 dig_port->ddi_io_power_domain, 3159 wakeref); 3160 3161 intel_ddi_disable_clock(encoder); 3162 3163 /* De-select Thunderbolt */ 3164 if (DISPLAY_VER(display) >= 14) 3165 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3166 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3167 } 3168 3169 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3170 struct intel_encoder *encoder, 3171 const struct intel_crtc_state *old_crtc_state, 3172 const struct drm_connector_state *old_conn_state) 3173 { 3174 struct intel_display *display = to_intel_display(encoder); 3175 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3176 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3177 intel_wakeref_t wakeref; 3178 3179 dig_port->set_infoframes(encoder, false, 3180 old_crtc_state, old_conn_state); 3181 3182 if (DISPLAY_VER(display) < 12) 3183 intel_ddi_disable_transcoder_clock(old_crtc_state); 3184 3185 intel_ddi_buf_disable(encoder, old_crtc_state); 3186 3187 if (DISPLAY_VER(display) >= 12) 3188 intel_ddi_disable_transcoder_clock(old_crtc_state); 3189 3190 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3191 if (wakeref) 3192 intel_display_power_put(display, 3193 dig_port->ddi_io_power_domain, 3194 wakeref); 3195 3196 intel_ddi_disable_clock(encoder); 3197 3198 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3199 } 3200 3201 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3202 struct intel_encoder *encoder, 3203 const struct intel_crtc_state *old_crtc_state, 3204 const struct drm_connector_state *old_conn_state) 3205 { 3206 struct intel_display *display = to_intel_display(encoder); 3207 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3208 struct intel_crtc *pipe_crtc; 3209 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3210 int i; 3211 3212 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3213 const struct intel_crtc_state *old_pipe_crtc_state = 3214 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3215 3216 intel_crtc_vblank_off(old_pipe_crtc_state); 3217 } 3218 3219 intel_disable_transcoder(old_crtc_state); 3220 3221 /* 128b/132b SST */ 3222 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3223 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3224 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3225 3226 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3227 3228 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3229 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3230 3231 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3232 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3233 } 3234 3235 intel_vrr_transcoder_disable(old_crtc_state); 3236 3237 intel_ddi_disable_transcoder_func(old_crtc_state); 3238 3239 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3240 const struct intel_crtc_state *old_pipe_crtc_state = 3241 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3242 3243 intel_dsc_disable(old_pipe_crtc_state); 3244 3245 if (DISPLAY_VER(display) >= 9) 3246 skl_scaler_disable(old_pipe_crtc_state); 3247 else 3248 ilk_pfit_disable(old_pipe_crtc_state); 3249 } 3250 } 3251 3252 /* 3253 * Note: Also called from the ->post_disable of the last active MST stream 3254 * encoder on its primary encoder. See also the comment for 3255 * intel_ddi_pre_enable(). 3256 */ 3257 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3258 struct intel_encoder *encoder, 3259 const struct intel_crtc_state *old_crtc_state, 3260 const struct drm_connector_state *old_conn_state) 3261 { 3262 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3263 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3264 old_conn_state); 3265 3266 /* 3267 * When called from DP MST code: 3268 * - old_conn_state will be NULL 3269 * - encoder will be the main encoder (ie. mst->primary) 3270 * - the main connector associated with this port 3271 * won't be active or linked to a crtc 3272 * - old_crtc_state will be the state of the last stream to 3273 * be deactivated on this port, and it may not be the same 3274 * stream that was activated last, but each stream 3275 * should have a state that is identical when it comes to 3276 * the DP link parameters 3277 */ 3278 3279 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3280 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3281 old_conn_state); 3282 else 3283 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3284 old_conn_state); 3285 } 3286 3287 /* 3288 * Note: Also called from the ->post_pll_disable of the last active MST stream 3289 * encoder on its primary encoder. See also the comment for 3290 * intel_ddi_pre_enable(). 3291 */ 3292 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3293 struct intel_encoder *encoder, 3294 const struct intel_crtc_state *old_crtc_state, 3295 const struct drm_connector_state *old_conn_state) 3296 { 3297 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3298 3299 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3300 3301 if (intel_encoder_is_tc(encoder)) 3302 intel_tc_port_put_link(dig_port); 3303 } 3304 3305 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3306 struct intel_encoder *encoder, 3307 const struct intel_crtc_state *crtc_state) 3308 { 3309 const struct drm_connector_state *conn_state; 3310 struct drm_connector *conn; 3311 int i; 3312 3313 if (!crtc_state->sync_mode_slaves_mask) 3314 return; 3315 3316 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3317 struct intel_encoder *slave_encoder = 3318 to_intel_encoder(conn_state->best_encoder); 3319 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3320 const struct intel_crtc_state *slave_crtc_state; 3321 3322 if (!slave_crtc) 3323 continue; 3324 3325 slave_crtc_state = 3326 intel_atomic_get_new_crtc_state(state, slave_crtc); 3327 3328 if (slave_crtc_state->master_transcoder != 3329 crtc_state->cpu_transcoder) 3330 continue; 3331 3332 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3333 slave_crtc_state); 3334 } 3335 3336 usleep_range(200, 400); 3337 3338 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3339 crtc_state); 3340 } 3341 3342 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3343 struct intel_encoder *encoder, 3344 const struct intel_crtc_state *crtc_state, 3345 const struct drm_connector_state *conn_state) 3346 { 3347 struct intel_display *display = to_intel_display(encoder); 3348 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3349 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3350 enum port port = encoder->port; 3351 3352 if (port == PORT_A && DISPLAY_VER(display) < 9) 3353 intel_dp_stop_link_train(intel_dp, crtc_state); 3354 3355 drm_connector_update_privacy_screen(conn_state); 3356 intel_edp_backlight_on(crtc_state, conn_state); 3357 3358 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3359 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3360 3361 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3362 } 3363 3364 static i915_reg_t 3365 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3366 { 3367 static const enum transcoder trans[] = { 3368 [PORT_A] = TRANSCODER_EDP, 3369 [PORT_B] = TRANSCODER_A, 3370 [PORT_C] = TRANSCODER_B, 3371 [PORT_D] = TRANSCODER_C, 3372 [PORT_E] = TRANSCODER_A, 3373 }; 3374 3375 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3376 3377 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3378 port = PORT_A; 3379 3380 return CHICKEN_TRANS(display, trans[port]); 3381 } 3382 3383 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3384 struct intel_encoder *encoder, 3385 const struct intel_crtc_state *crtc_state, 3386 const struct drm_connector_state *conn_state) 3387 { 3388 struct intel_display *display = to_intel_display(encoder); 3389 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3390 struct drm_connector *connector = conn_state->connector; 3391 enum port port = encoder->port; 3392 u32 buf_ctl = 0; 3393 3394 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3395 crtc_state->hdmi_high_tmds_clock_ratio, 3396 crtc_state->hdmi_scrambling)) 3397 drm_dbg_kms(display->drm, 3398 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3399 connector->base.id, connector->name); 3400 3401 if (has_buf_trans_select(display)) 3402 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3403 3404 /* e. Enable D2D Link for C10/C20 Phy */ 3405 mtl_ddi_enable_d2d(encoder); 3406 3407 encoder->set_signal_levels(encoder, crtc_state); 3408 3409 /* Display WA #1143: skl,kbl,cfl */ 3410 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3411 /* 3412 * For some reason these chicken bits have been 3413 * stuffed into a transcoder register, event though 3414 * the bits affect a specific DDI port rather than 3415 * a specific transcoder. 3416 */ 3417 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3418 u32 val; 3419 3420 val = intel_de_read(display, reg); 3421 3422 if (port == PORT_E) 3423 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3424 DDIE_TRAINING_OVERRIDE_VALUE; 3425 else 3426 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3427 DDI_TRAINING_OVERRIDE_VALUE; 3428 3429 intel_de_write(display, reg, val); 3430 intel_de_posting_read(display, reg); 3431 3432 udelay(1); 3433 3434 if (port == PORT_E) 3435 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3436 DDIE_TRAINING_OVERRIDE_VALUE); 3437 else 3438 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3439 DDI_TRAINING_OVERRIDE_VALUE); 3440 3441 intel_de_write(display, reg, val); 3442 } 3443 3444 intel_ddi_power_up_lanes(encoder, crtc_state); 3445 3446 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3447 * are ignored so nothing special needs to be done besides 3448 * enabling the port. 3449 * 3450 * On ADL_P the PHY link rate and lane count must be programmed but 3451 * these are both 0 for HDMI. 3452 * 3453 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3454 * is filled with lane count, already set in the crtc_state. 3455 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3456 */ 3457 if (dig_port->lane_reversal) 3458 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3459 if (dig_port->ddi_a_4_lanes) 3460 buf_ctl |= DDI_A_4_LANES; 3461 3462 if (DISPLAY_VER(display) >= 14) { 3463 u32 port_buf = 0; 3464 3465 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3466 3467 if (dig_port->lane_reversal) 3468 port_buf |= XELPDP_PORT_REVERSAL; 3469 3470 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3471 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3472 3473 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3474 3475 if (DISPLAY_VER(display) >= 20) 3476 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3477 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3478 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3479 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3480 } 3481 3482 intel_ddi_buf_enable(encoder, buf_ctl); 3483 } 3484 3485 static void intel_ddi_enable(struct intel_atomic_state *state, 3486 struct intel_encoder *encoder, 3487 const struct intel_crtc_state *crtc_state, 3488 const struct drm_connector_state *conn_state) 3489 { 3490 struct intel_display *display = to_intel_display(encoder); 3491 struct intel_crtc *pipe_crtc; 3492 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3493 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3494 int i; 3495 3496 /* 128b/132b SST */ 3497 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3498 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3499 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3500 3501 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3502 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3503 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3504 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3505 } 3506 3507 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3508 3509 intel_vrr_transcoder_enable(crtc_state); 3510 3511 /* 128b/132b SST */ 3512 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3513 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3514 3515 intel_ddi_clear_act_sent(encoder, crtc_state); 3516 3517 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3518 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3519 3520 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3521 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3522 } 3523 3524 intel_enable_transcoder(crtc_state); 3525 3526 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3527 3528 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3529 const struct intel_crtc_state *pipe_crtc_state = 3530 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3531 3532 intel_crtc_vblank_on(pipe_crtc_state); 3533 } 3534 3535 if (is_hdmi) 3536 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3537 else 3538 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3539 3540 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3541 3542 } 3543 3544 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3545 struct intel_encoder *encoder, 3546 const struct intel_crtc_state *old_crtc_state, 3547 const struct drm_connector_state *old_conn_state) 3548 { 3549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3550 struct intel_connector *connector = 3551 to_intel_connector(old_conn_state->connector); 3552 3553 intel_dp->link.active = false; 3554 3555 intel_psr_disable(intel_dp, old_crtc_state); 3556 intel_alpm_disable(intel_dp); 3557 intel_edp_backlight_off(old_conn_state); 3558 /* Disable the decompression in DP Sink */ 3559 intel_dp_sink_disable_decompression(state, 3560 connector, old_crtc_state); 3561 /* Disable Ignore_MSA bit in DP Sink */ 3562 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3563 false); 3564 } 3565 3566 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3567 struct intel_encoder *encoder, 3568 const struct intel_crtc_state *old_crtc_state, 3569 const struct drm_connector_state *old_conn_state) 3570 { 3571 struct intel_display *display = to_intel_display(encoder); 3572 struct drm_connector *connector = old_conn_state->connector; 3573 3574 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3575 false, false)) 3576 drm_dbg_kms(display->drm, 3577 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3578 connector->base.id, connector->name); 3579 } 3580 3581 static void intel_ddi_disable(struct intel_atomic_state *state, 3582 struct intel_encoder *encoder, 3583 const struct intel_crtc_state *old_crtc_state, 3584 const struct drm_connector_state *old_conn_state) 3585 { 3586 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3587 3588 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3589 3590 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3591 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3592 old_conn_state); 3593 else 3594 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3595 old_conn_state); 3596 } 3597 3598 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3599 struct intel_encoder *encoder, 3600 const struct intel_crtc_state *crtc_state, 3601 const struct drm_connector_state *conn_state) 3602 { 3603 intel_ddi_set_dp_msa(crtc_state, conn_state); 3604 3605 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3606 3607 intel_backlight_update(state, encoder, crtc_state, conn_state); 3608 drm_connector_update_privacy_screen(conn_state); 3609 } 3610 3611 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3612 const struct intel_crtc_state *crtc_state, 3613 const struct drm_connector_state *conn_state) 3614 { 3615 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3616 } 3617 3618 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3619 struct intel_encoder *encoder, 3620 const struct intel_crtc_state *crtc_state, 3621 const struct drm_connector_state *conn_state) 3622 { 3623 3624 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3625 !intel_encoder_is_mst(encoder)) 3626 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3627 conn_state); 3628 3629 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3630 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3631 conn_state); 3632 3633 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3634 } 3635 3636 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3637 struct intel_encoder *encoder, 3638 struct intel_crtc *crtc) 3639 { 3640 struct intel_display *display = to_intel_display(encoder); 3641 const struct intel_crtc_state *crtc_state = 3642 intel_atomic_get_new_crtc_state(state, crtc); 3643 struct intel_crtc *pipe_crtc; 3644 3645 /* FIXME: Add MTL pll_mgr */ 3646 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3647 return; 3648 3649 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3650 intel_crtc_joined_pipe_mask(crtc_state)) 3651 intel_dpll_update_active(state, pipe_crtc, encoder); 3652 } 3653 3654 /* 3655 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3656 * encoder on its primary encoder. See also the comment for 3657 * intel_ddi_pre_enable(). 3658 */ 3659 static void 3660 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3661 struct intel_encoder *encoder, 3662 const struct intel_crtc_state *crtc_state, 3663 const struct drm_connector_state *conn_state) 3664 { 3665 struct intel_display *display = to_intel_display(encoder); 3666 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3667 bool is_tc_port = intel_encoder_is_tc(encoder); 3668 3669 if (is_tc_port) { 3670 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3671 3672 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3673 intel_ddi_update_active_dpll(state, encoder, crtc); 3674 } 3675 3676 main_link_aux_power_domain_get(dig_port, crtc_state); 3677 3678 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3679 /* 3680 * Program the lane count for static/dynamic connections on 3681 * Type-C ports. Skip this step for TBT. 3682 */ 3683 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3684 else if (display->platform.geminilake || display->platform.broxton) 3685 bxt_dpio_phy_set_lane_optim_mask(encoder, 3686 crtc_state->lane_lat_optim_mask); 3687 } 3688 3689 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3690 { 3691 struct intel_display *display = to_intel_display(encoder); 3692 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3693 int ln; 3694 3695 for (ln = 0; ln < 2; ln++) 3696 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3697 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3698 } 3699 3700 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3701 const struct intel_crtc_state *crtc_state) 3702 { 3703 struct intel_display *display = to_intel_display(crtc_state); 3704 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3705 struct intel_encoder *encoder = &dig_port->base; 3706 u32 dp_tp_ctl; 3707 3708 /* 3709 * TODO: To train with only a different voltage swing entry is not 3710 * necessary disable and enable port 3711 */ 3712 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3713 3714 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3715 3716 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3717 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3718 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3719 intel_dp_is_uhbr(crtc_state)) { 3720 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3721 } else { 3722 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3723 if (crtc_state->enhanced_framing) 3724 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3725 } 3726 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3727 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3728 3729 /* 6.f Enable D2D Link */ 3730 mtl_ddi_enable_d2d(encoder); 3731 3732 /* 6.g Configure voltage swing and related IO settings */ 3733 encoder->set_signal_levels(encoder, crtc_state); 3734 3735 /* 6.h Configure PORT_BUF_CTL1 */ 3736 mtl_port_buf_ctl_program(encoder, crtc_state); 3737 3738 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3739 if (DISPLAY_VER(display) >= 20) 3740 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3741 3742 intel_ddi_buf_enable(encoder, intel_dp->DP); 3743 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3744 3745 /* 3746 * 6.k If AUX-Less ALPM is going to be enabled: 3747 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3748 */ 3749 intel_alpm_port_configure(intel_dp, crtc_state); 3750 3751 /* 3752 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3753 * register 3754 */ 3755 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3756 } 3757 3758 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3759 const struct intel_crtc_state *crtc_state) 3760 { 3761 struct intel_display *display = to_intel_display(intel_dp); 3762 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3763 struct intel_encoder *encoder = &dig_port->base; 3764 u32 dp_tp_ctl; 3765 3766 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3767 3768 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3769 3770 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3771 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3772 intel_dp_is_uhbr(crtc_state)) { 3773 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3774 } else { 3775 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3776 if (crtc_state->enhanced_framing) 3777 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3778 } 3779 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3780 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3781 3782 if (display->platform.alderlake_p && 3783 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3784 adlp_tbt_to_dp_alt_switch_wa(encoder); 3785 3786 intel_ddi_buf_enable(encoder, intel_dp->DP); 3787 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3788 } 3789 3790 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3791 const struct intel_crtc_state *crtc_state, 3792 u8 dp_train_pat) 3793 { 3794 struct intel_display *display = to_intel_display(intel_dp); 3795 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3796 u32 temp; 3797 3798 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3799 3800 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3801 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3802 case DP_TRAINING_PATTERN_DISABLE: 3803 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3804 break; 3805 case DP_TRAINING_PATTERN_1: 3806 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3807 break; 3808 case DP_TRAINING_PATTERN_2: 3809 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3810 break; 3811 case DP_TRAINING_PATTERN_3: 3812 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3813 break; 3814 case DP_TRAINING_PATTERN_4: 3815 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3816 break; 3817 } 3818 3819 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3820 } 3821 3822 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3823 const struct intel_crtc_state *crtc_state) 3824 { 3825 struct intel_display *display = to_intel_display(intel_dp); 3826 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3827 enum port port = encoder->port; 3828 3829 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3830 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3831 3832 /* 3833 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3834 * reason we need to set idle transmission mode is to work around a HW 3835 * issue where we enable the pipe while not in idle link-training mode. 3836 * In this case there is requirement to wait for a minimum number of 3837 * idle patterns to be sent. 3838 */ 3839 if (port == PORT_A && DISPLAY_VER(display) < 12) 3840 return; 3841 3842 if (intel_de_wait_for_set(display, 3843 dp_tp_status_reg(encoder, crtc_state), 3844 DP_TP_STATUS_IDLE_DONE, 2)) 3845 drm_err(display->drm, 3846 "Timed out waiting for DP idle patterns\n"); 3847 } 3848 3849 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3850 enum transcoder cpu_transcoder) 3851 { 3852 if (cpu_transcoder == TRANSCODER_EDP) 3853 return false; 3854 3855 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3856 return false; 3857 3858 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3859 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3860 } 3861 3862 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3863 { 3864 if (crtc_state->port_clock > 594000) 3865 return 2; 3866 else 3867 return 0; 3868 } 3869 3870 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3871 { 3872 if (crtc_state->port_clock > 594000) 3873 return 3; 3874 else 3875 return 0; 3876 } 3877 3878 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3879 { 3880 if (crtc_state->port_clock > 594000) 3881 return 1; 3882 else 3883 return 0; 3884 } 3885 3886 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3887 { 3888 struct intel_display *display = to_intel_display(crtc_state); 3889 3890 if (DISPLAY_VER(display) >= 14) 3891 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3892 else if (DISPLAY_VER(display) >= 12) 3893 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3894 else if (display->platform.jasperlake || display->platform.elkhartlake) 3895 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3896 else if (DISPLAY_VER(display) >= 11) 3897 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3898 } 3899 3900 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3901 enum transcoder cpu_transcoder) 3902 { 3903 u32 master_select; 3904 3905 if (DISPLAY_VER(display) >= 11) { 3906 u32 ctl2 = intel_de_read(display, 3907 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3908 3909 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3910 return INVALID_TRANSCODER; 3911 3912 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3913 } else { 3914 u32 ctl = intel_de_read(display, 3915 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3916 3917 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3918 return INVALID_TRANSCODER; 3919 3920 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3921 } 3922 3923 if (master_select == 0) 3924 return TRANSCODER_EDP; 3925 else 3926 return master_select - 1; 3927 } 3928 3929 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3930 { 3931 struct intel_display *display = to_intel_display(crtc_state); 3932 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3933 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3934 enum transcoder cpu_transcoder; 3935 3936 crtc_state->master_transcoder = 3937 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3938 3939 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3940 enum intel_display_power_domain power_domain; 3941 intel_wakeref_t trans_wakeref; 3942 3943 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3944 trans_wakeref = intel_display_power_get_if_enabled(display, 3945 power_domain); 3946 3947 if (!trans_wakeref) 3948 continue; 3949 3950 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3951 crtc_state->cpu_transcoder) 3952 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3953 3954 intel_display_power_put(display, power_domain, trans_wakeref); 3955 } 3956 3957 drm_WARN_ON(display->drm, 3958 crtc_state->master_transcoder != INVALID_TRANSCODER && 3959 crtc_state->sync_mode_slaves_mask); 3960 } 3961 3962 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3963 struct intel_crtc_state *crtc_state, 3964 u32 ddi_func_ctl) 3965 { 3966 struct intel_display *display = to_intel_display(encoder); 3967 3968 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3969 if (DISPLAY_VER(display) >= 14) 3970 crtc_state->lane_count = 3971 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3972 else 3973 crtc_state->lane_count = 4; 3974 } 3975 3976 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3977 struct intel_crtc_state *crtc_state, 3978 u32 ddi_func_ctl) 3979 { 3980 crtc_state->has_hdmi_sink = true; 3981 3982 crtc_state->infoframes.enable |= 3983 intel_hdmi_infoframes_enabled(encoder, crtc_state); 3984 3985 if (crtc_state->infoframes.enable) 3986 crtc_state->has_infoframe = true; 3987 3988 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 3989 crtc_state->hdmi_scrambling = true; 3990 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3991 crtc_state->hdmi_high_tmds_clock_ratio = true; 3992 3993 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 3994 } 3995 3996 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 3997 struct intel_crtc_state *crtc_state, 3998 u32 ddi_func_ctl) 3999 { 4000 struct intel_display *display = to_intel_display(encoder); 4001 4002 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4003 crtc_state->enhanced_framing = 4004 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4005 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4006 } 4007 4008 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4009 struct intel_crtc_state *crtc_state, 4010 u32 ddi_func_ctl) 4011 { 4012 struct intel_display *display = to_intel_display(encoder); 4013 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4014 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4015 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4016 4017 if (encoder->type == INTEL_OUTPUT_EDP) 4018 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4019 else 4020 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4021 crtc_state->lane_count = 4022 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4023 4024 if (DISPLAY_VER(display) >= 12 && 4025 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4026 crtc_state->mst_master_transcoder = 4027 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4028 4029 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4030 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4031 4032 crtc_state->enhanced_framing = 4033 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4034 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4035 4036 if (DISPLAY_VER(display) >= 11) 4037 crtc_state->fec_enable = 4038 intel_de_read(display, 4039 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4040 4041 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4042 crtc_state->infoframes.enable |= 4043 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4044 else 4045 crtc_state->infoframes.enable |= 4046 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4047 } 4048 4049 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4050 struct intel_crtc_state *crtc_state, 4051 u32 ddi_func_ctl) 4052 { 4053 struct intel_display *display = to_intel_display(encoder); 4054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4055 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4056 4057 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4058 crtc_state->lane_count = 4059 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4060 4061 if (DISPLAY_VER(display) >= 12) 4062 crtc_state->mst_master_transcoder = 4063 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4064 4065 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4066 4067 if (DISPLAY_VER(display) >= 11) 4068 crtc_state->fec_enable = 4069 intel_de_read(display, 4070 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4071 4072 crtc_state->infoframes.enable |= 4073 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4074 } 4075 4076 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4077 struct intel_crtc_state *pipe_config) 4078 { 4079 struct intel_display *display = to_intel_display(encoder); 4080 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4081 u32 ddi_func_ctl, ddi_mode, flags = 0; 4082 4083 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4084 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4085 flags |= DRM_MODE_FLAG_PHSYNC; 4086 else 4087 flags |= DRM_MODE_FLAG_NHSYNC; 4088 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4089 flags |= DRM_MODE_FLAG_PVSYNC; 4090 else 4091 flags |= DRM_MODE_FLAG_NVSYNC; 4092 4093 pipe_config->hw.adjusted_mode.flags |= flags; 4094 4095 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4096 case TRANS_DDI_BPC_6: 4097 pipe_config->pipe_bpp = 18; 4098 break; 4099 case TRANS_DDI_BPC_8: 4100 pipe_config->pipe_bpp = 24; 4101 break; 4102 case TRANS_DDI_BPC_10: 4103 pipe_config->pipe_bpp = 30; 4104 break; 4105 case TRANS_DDI_BPC_12: 4106 pipe_config->pipe_bpp = 36; 4107 break; 4108 default: 4109 break; 4110 } 4111 4112 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4113 4114 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4115 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4116 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4117 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4118 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4119 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4120 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4121 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4122 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4123 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4124 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4125 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4126 4127 /* 4128 * If this is true, we know we're being called from mst stream 4129 * encoder's ->get_config(). 4130 */ 4131 if (intel_dp_mst_active_streams(intel_dp)) 4132 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4133 else 4134 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4135 } 4136 } 4137 4138 /* 4139 * Note: Also called from the ->get_config of the MST stream encoders on their 4140 * primary encoder, via the platform specific hooks here. See also the comment 4141 * for intel_ddi_pre_enable(). 4142 */ 4143 static void intel_ddi_get_config(struct intel_encoder *encoder, 4144 struct intel_crtc_state *pipe_config) 4145 { 4146 struct intel_display *display = to_intel_display(encoder); 4147 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4148 4149 /* XXX: DSI transcoder paranoia */ 4150 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4151 return; 4152 4153 intel_ddi_read_func_ctl(encoder, pipe_config); 4154 4155 intel_ddi_mso_get_config(encoder, pipe_config); 4156 4157 pipe_config->has_audio = 4158 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4159 4160 if (encoder->type == INTEL_OUTPUT_EDP) 4161 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4162 4163 ddi_dotclock_get(pipe_config); 4164 4165 if (display->platform.geminilake || display->platform.broxton) 4166 pipe_config->lane_lat_optim_mask = 4167 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4168 4169 intel_ddi_compute_min_voltage_level(pipe_config); 4170 4171 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4172 4173 intel_read_infoframe(encoder, pipe_config, 4174 HDMI_INFOFRAME_TYPE_AVI, 4175 &pipe_config->infoframes.avi); 4176 intel_read_infoframe(encoder, pipe_config, 4177 HDMI_INFOFRAME_TYPE_SPD, 4178 &pipe_config->infoframes.spd); 4179 intel_read_infoframe(encoder, pipe_config, 4180 HDMI_INFOFRAME_TYPE_VENDOR, 4181 &pipe_config->infoframes.hdmi); 4182 intel_read_infoframe(encoder, pipe_config, 4183 HDMI_INFOFRAME_TYPE_DRM, 4184 &pipe_config->infoframes.drm); 4185 4186 if (DISPLAY_VER(display) >= 8) 4187 bdw_get_trans_port_sync_config(pipe_config); 4188 4189 intel_psr_get_config(encoder, pipe_config); 4190 4191 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4192 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4193 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4194 4195 intel_audio_codec_get_config(encoder, pipe_config); 4196 } 4197 4198 void intel_ddi_get_clock(struct intel_encoder *encoder, 4199 struct intel_crtc_state *crtc_state, 4200 struct intel_dpll *pll) 4201 { 4202 struct intel_display *display = to_intel_display(encoder); 4203 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4204 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4205 bool pll_active; 4206 4207 if (drm_WARN_ON(display->drm, !pll)) 4208 return; 4209 4210 port_dpll->pll = pll; 4211 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4212 drm_WARN_ON(display->drm, !pll_active); 4213 4214 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4215 4216 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4217 &crtc_state->dpll_hw_state); 4218 } 4219 4220 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4221 struct intel_crtc_state *crtc_state) 4222 { 4223 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4224 4225 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4226 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4227 else 4228 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4229 4230 intel_ddi_get_config(encoder, crtc_state); 4231 } 4232 4233 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4234 struct intel_crtc_state *crtc_state) 4235 { 4236 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4237 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4238 4239 intel_ddi_get_config(encoder, crtc_state); 4240 } 4241 4242 static void adls_ddi_get_config(struct intel_encoder *encoder, 4243 struct intel_crtc_state *crtc_state) 4244 { 4245 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4246 intel_ddi_get_config(encoder, crtc_state); 4247 } 4248 4249 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4250 struct intel_crtc_state *crtc_state) 4251 { 4252 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4253 intel_ddi_get_config(encoder, crtc_state); 4254 } 4255 4256 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4257 struct intel_crtc_state *crtc_state) 4258 { 4259 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4260 intel_ddi_get_config(encoder, crtc_state); 4261 } 4262 4263 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4264 struct intel_crtc_state *crtc_state) 4265 { 4266 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4267 intel_ddi_get_config(encoder, crtc_state); 4268 } 4269 4270 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4271 { 4272 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4273 } 4274 4275 static enum icl_port_dpll_id 4276 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4277 const struct intel_crtc_state *crtc_state) 4278 { 4279 struct intel_display *display = to_intel_display(encoder); 4280 const struct intel_dpll *pll = crtc_state->intel_dpll; 4281 4282 if (drm_WARN_ON(display->drm, !pll)) 4283 return ICL_PORT_DPLL_DEFAULT; 4284 4285 if (icl_ddi_tc_pll_is_tbt(pll)) 4286 return ICL_PORT_DPLL_DEFAULT; 4287 else 4288 return ICL_PORT_DPLL_MG_PHY; 4289 } 4290 4291 enum icl_port_dpll_id 4292 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4293 const struct intel_crtc_state *crtc_state) 4294 { 4295 if (!encoder->port_pll_type) 4296 return ICL_PORT_DPLL_DEFAULT; 4297 4298 return encoder->port_pll_type(encoder, crtc_state); 4299 } 4300 4301 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4302 struct intel_crtc_state *crtc_state, 4303 struct intel_dpll *pll) 4304 { 4305 struct intel_display *display = to_intel_display(encoder); 4306 enum icl_port_dpll_id port_dpll_id; 4307 struct icl_port_dpll *port_dpll; 4308 bool pll_active; 4309 4310 if (drm_WARN_ON(display->drm, !pll)) 4311 return; 4312 4313 if (icl_ddi_tc_pll_is_tbt(pll)) 4314 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4315 else 4316 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4317 4318 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4319 4320 port_dpll->pll = pll; 4321 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4322 drm_WARN_ON(display->drm, !pll_active); 4323 4324 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4325 4326 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4327 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4328 else 4329 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4330 &crtc_state->dpll_hw_state); 4331 } 4332 4333 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4334 struct intel_crtc_state *crtc_state) 4335 { 4336 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4337 intel_ddi_get_config(encoder, crtc_state); 4338 } 4339 4340 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4341 struct intel_crtc_state *crtc_state) 4342 { 4343 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4344 intel_ddi_get_config(encoder, crtc_state); 4345 } 4346 4347 static void skl_ddi_get_config(struct intel_encoder *encoder, 4348 struct intel_crtc_state *crtc_state) 4349 { 4350 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4351 intel_ddi_get_config(encoder, crtc_state); 4352 } 4353 4354 void hsw_ddi_get_config(struct intel_encoder *encoder, 4355 struct intel_crtc_state *crtc_state) 4356 { 4357 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4358 intel_ddi_get_config(encoder, crtc_state); 4359 } 4360 4361 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4362 const struct intel_crtc_state *crtc_state) 4363 { 4364 if (intel_encoder_is_tc(encoder)) 4365 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4366 crtc_state); 4367 4368 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4369 (!crtc_state && intel_encoder_is_dp(encoder))) 4370 intel_dp_sync_state(encoder, crtc_state); 4371 } 4372 4373 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4374 struct intel_crtc_state *crtc_state) 4375 { 4376 struct intel_display *display = to_intel_display(encoder); 4377 bool fastset = true; 4378 4379 if (intel_encoder_is_tc(encoder)) { 4380 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4381 encoder->base.base.id, encoder->base.name); 4382 crtc_state->uapi.mode_changed = true; 4383 fastset = false; 4384 } 4385 4386 if (intel_crtc_has_dp_encoder(crtc_state) && 4387 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4388 fastset = false; 4389 4390 return fastset; 4391 } 4392 4393 static enum intel_output_type 4394 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4395 struct intel_crtc_state *crtc_state, 4396 struct drm_connector_state *conn_state) 4397 { 4398 switch (conn_state->connector->connector_type) { 4399 case DRM_MODE_CONNECTOR_HDMIA: 4400 return INTEL_OUTPUT_HDMI; 4401 case DRM_MODE_CONNECTOR_eDP: 4402 return INTEL_OUTPUT_EDP; 4403 case DRM_MODE_CONNECTOR_DisplayPort: 4404 return INTEL_OUTPUT_DP; 4405 default: 4406 MISSING_CASE(conn_state->connector->connector_type); 4407 return INTEL_OUTPUT_UNUSED; 4408 } 4409 } 4410 4411 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4412 struct intel_crtc_state *pipe_config, 4413 struct drm_connector_state *conn_state) 4414 { 4415 struct intel_display *display = to_intel_display(encoder); 4416 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4417 enum port port = encoder->port; 4418 int ret; 4419 4420 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4421 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4422 4423 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4424 pipe_config->has_hdmi_sink = 4425 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4426 4427 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4428 } else { 4429 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4430 } 4431 4432 if (ret) 4433 return ret; 4434 4435 if (display->platform.haswell && crtc->pipe == PIPE_A && 4436 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4437 pipe_config->pch_pfit.force_thru = 4438 pipe_config->pch_pfit.enabled || 4439 pipe_config->crc_enabled; 4440 4441 if (display->platform.geminilake || display->platform.broxton) 4442 pipe_config->lane_lat_optim_mask = 4443 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4444 4445 intel_ddi_compute_min_voltage_level(pipe_config); 4446 4447 return 0; 4448 } 4449 4450 static bool mode_equal(const struct drm_display_mode *mode1, 4451 const struct drm_display_mode *mode2) 4452 { 4453 return drm_mode_match(mode1, mode2, 4454 DRM_MODE_MATCH_TIMINGS | 4455 DRM_MODE_MATCH_FLAGS | 4456 DRM_MODE_MATCH_3D_FLAGS) && 4457 mode1->clock == mode2->clock; /* we want an exact match */ 4458 } 4459 4460 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4461 const struct intel_link_m_n *m_n_2) 4462 { 4463 return m_n_1->tu == m_n_2->tu && 4464 m_n_1->data_m == m_n_2->data_m && 4465 m_n_1->data_n == m_n_2->data_n && 4466 m_n_1->link_m == m_n_2->link_m && 4467 m_n_1->link_n == m_n_2->link_n; 4468 } 4469 4470 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4471 const struct intel_crtc_state *crtc_state2) 4472 { 4473 /* 4474 * FIXME the modeset sequence is currently wrong and 4475 * can't deal with joiner + port sync at the same time. 4476 */ 4477 return crtc_state1->hw.active && crtc_state2->hw.active && 4478 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4479 crtc_state1->output_types == crtc_state2->output_types && 4480 crtc_state1->output_format == crtc_state2->output_format && 4481 crtc_state1->lane_count == crtc_state2->lane_count && 4482 crtc_state1->port_clock == crtc_state2->port_clock && 4483 mode_equal(&crtc_state1->hw.adjusted_mode, 4484 &crtc_state2->hw.adjusted_mode) && 4485 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4486 } 4487 4488 static u8 4489 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4490 int tile_group_id) 4491 { 4492 struct intel_display *display = to_intel_display(ref_crtc_state); 4493 struct drm_connector *connector; 4494 const struct drm_connector_state *conn_state; 4495 struct intel_atomic_state *state = 4496 to_intel_atomic_state(ref_crtc_state->uapi.state); 4497 u8 transcoders = 0; 4498 int i; 4499 4500 /* 4501 * We don't enable port sync on BDW due to missing w/as and 4502 * due to not having adjusted the modeset sequence appropriately. 4503 */ 4504 if (DISPLAY_VER(display) < 9) 4505 return 0; 4506 4507 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4508 return 0; 4509 4510 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4511 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4512 const struct intel_crtc_state *crtc_state; 4513 4514 if (!crtc) 4515 continue; 4516 4517 if (!connector->has_tile || 4518 connector->tile_group->id != 4519 tile_group_id) 4520 continue; 4521 crtc_state = intel_atomic_get_new_crtc_state(state, 4522 crtc); 4523 if (!crtcs_port_sync_compatible(ref_crtc_state, 4524 crtc_state)) 4525 continue; 4526 transcoders |= BIT(crtc_state->cpu_transcoder); 4527 } 4528 4529 return transcoders; 4530 } 4531 4532 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4533 struct intel_crtc_state *crtc_state, 4534 struct drm_connector_state *conn_state) 4535 { 4536 struct intel_display *display = to_intel_display(encoder); 4537 struct drm_connector *connector = conn_state->connector; 4538 u8 port_sync_transcoders = 0; 4539 4540 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4541 encoder->base.base.id, encoder->base.name, 4542 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4543 4544 if (connector->has_tile) 4545 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4546 connector->tile_group->id); 4547 4548 /* 4549 * EDP Transcoders cannot be ensalved 4550 * make them a master always when present 4551 */ 4552 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4553 crtc_state->master_transcoder = TRANSCODER_EDP; 4554 else 4555 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4556 4557 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4558 crtc_state->master_transcoder = INVALID_TRANSCODER; 4559 crtc_state->sync_mode_slaves_mask = 4560 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4561 } 4562 4563 return 0; 4564 } 4565 4566 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4567 { 4568 struct intel_display *display = to_intel_display(encoder->dev); 4569 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4570 4571 intel_dp_encoder_flush_work(encoder); 4572 if (intel_encoder_is_tc(&dig_port->base)) 4573 intel_tc_port_cleanup(dig_port); 4574 intel_display_power_flush_work(display); 4575 4576 drm_encoder_cleanup(encoder); 4577 kfree(dig_port->hdcp.port_data.streams); 4578 kfree(dig_port); 4579 } 4580 4581 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4582 { 4583 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4584 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4585 4586 intel_dp->reset_link_params = true; 4587 intel_dp_invalidate_source_oui(intel_dp); 4588 4589 intel_pps_encoder_reset(intel_dp); 4590 4591 if (intel_encoder_is_tc(&dig_port->base)) 4592 intel_tc_port_init_mode(dig_port); 4593 } 4594 4595 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4596 { 4597 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4598 4599 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4600 4601 return 0; 4602 } 4603 4604 static const struct drm_encoder_funcs intel_ddi_funcs = { 4605 .reset = intel_ddi_encoder_reset, 4606 .destroy = intel_ddi_encoder_destroy, 4607 .late_register = intel_ddi_encoder_late_register, 4608 }; 4609 4610 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4611 { 4612 struct intel_display *display = to_intel_display(dig_port); 4613 struct intel_connector *connector; 4614 enum port port = dig_port->base.port; 4615 4616 connector = intel_connector_alloc(); 4617 if (!connector) 4618 return -ENOMEM; 4619 4620 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4621 if (DISPLAY_VER(display) >= 14) 4622 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4623 else 4624 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4625 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4626 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4627 4628 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4629 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4630 4631 if (!intel_dp_init_connector(dig_port, connector)) { 4632 kfree(connector); 4633 return -EINVAL; 4634 } 4635 4636 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4637 struct drm_privacy_screen *privacy_screen; 4638 4639 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4640 if (!IS_ERR(privacy_screen)) { 4641 drm_connector_attach_privacy_screen_provider(&connector->base, 4642 privacy_screen); 4643 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4644 drm_warn(display->drm, "Error getting privacy-screen\n"); 4645 } 4646 } 4647 4648 return 0; 4649 } 4650 4651 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4652 struct drm_modeset_acquire_ctx *ctx) 4653 { 4654 struct intel_display *display = to_intel_display(encoder); 4655 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4656 struct intel_connector *connector = hdmi->attached_connector; 4657 struct i2c_adapter *ddc = connector->base.ddc; 4658 struct drm_connector_state *conn_state; 4659 struct intel_crtc_state *crtc_state; 4660 struct intel_crtc *crtc; 4661 u8 config; 4662 int ret; 4663 4664 if (connector->base.status != connector_status_connected) 4665 return 0; 4666 4667 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4668 ctx); 4669 if (ret) 4670 return ret; 4671 4672 conn_state = connector->base.state; 4673 4674 crtc = to_intel_crtc(conn_state->crtc); 4675 if (!crtc) 4676 return 0; 4677 4678 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4679 if (ret) 4680 return ret; 4681 4682 crtc_state = to_intel_crtc_state(crtc->base.state); 4683 4684 drm_WARN_ON(display->drm, 4685 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4686 4687 if (!crtc_state->hw.active) 4688 return 0; 4689 4690 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4691 !crtc_state->hdmi_scrambling) 4692 return 0; 4693 4694 if (conn_state->commit && 4695 !try_wait_for_completion(&conn_state->commit->hw_done)) 4696 return 0; 4697 4698 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4699 if (ret < 0) { 4700 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4701 connector->base.base.id, connector->base.name, ret); 4702 return 0; 4703 } 4704 4705 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4706 crtc_state->hdmi_high_tmds_clock_ratio && 4707 !!(config & SCDC_SCRAMBLING_ENABLE) == 4708 crtc_state->hdmi_scrambling) 4709 return 0; 4710 4711 /* 4712 * HDMI 2.0 says that one should not send scrambled data 4713 * prior to configuring the sink scrambling, and that 4714 * TMDS clock/data transmission should be suspended when 4715 * changing the TMDS clock rate in the sink. So let's 4716 * just do a full modeset here, even though some sinks 4717 * would be perfectly happy if were to just reconfigure 4718 * the SCDC settings on the fly. 4719 */ 4720 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4721 } 4722 4723 static void intel_ddi_link_check(struct intel_encoder *encoder) 4724 { 4725 struct intel_display *display = to_intel_display(encoder); 4726 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4727 4728 /* TODO: Move checking the HDMI link state here as well. */ 4729 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4730 4731 intel_dp_link_check(encoder); 4732 } 4733 4734 static enum intel_hotplug_state 4735 intel_ddi_hotplug(struct intel_encoder *encoder, 4736 struct intel_connector *connector) 4737 { 4738 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4739 struct intel_dp *intel_dp = &dig_port->dp; 4740 bool is_tc = intel_encoder_is_tc(encoder); 4741 struct drm_modeset_acquire_ctx ctx; 4742 enum intel_hotplug_state state; 4743 int ret; 4744 4745 if (intel_dp_test_phy(intel_dp)) 4746 return INTEL_HOTPLUG_UNCHANGED; 4747 4748 state = intel_encoder_hotplug(encoder, connector); 4749 4750 if (!intel_tc_port_link_reset(dig_port)) { 4751 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4752 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4753 ret = intel_hdmi_reset_link(encoder, &ctx); 4754 drm_WARN_ON(encoder->base.dev, ret); 4755 } else { 4756 intel_dp_check_link_state(intel_dp); 4757 } 4758 } 4759 4760 /* 4761 * Unpowered type-c dongles can take some time to boot and be 4762 * responsible, so here giving some time to those dongles to power up 4763 * and then retrying the probe. 4764 * 4765 * On many platforms the HDMI live state signal is known to be 4766 * unreliable, so we can't use it to detect if a sink is connected or 4767 * not. Instead we detect if it's connected based on whether we can 4768 * read the EDID or not. That in turn has a problem during disconnect, 4769 * since the HPD interrupt may be raised before the DDC lines get 4770 * disconnected (due to how the required length of DDC vs. HPD 4771 * connector pins are specified) and so we'll still be able to get a 4772 * valid EDID. To solve this schedule another detection cycle if this 4773 * time around we didn't detect any change in the sink's connection 4774 * status. 4775 * 4776 * Type-c connectors which get their HPD signal deasserted then 4777 * reasserted, without unplugging/replugging the sink from the 4778 * connector, introduce a delay until the AUX channel communication 4779 * becomes functional. Retry the detection for 5 seconds on type-c 4780 * connectors to account for this delay. 4781 */ 4782 if (state == INTEL_HOTPLUG_UNCHANGED && 4783 connector->hotplug_retries < (is_tc ? 5 : 1) && 4784 !dig_port->dp.is_mst) 4785 state = INTEL_HOTPLUG_RETRY; 4786 4787 return state; 4788 } 4789 4790 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4791 { 4792 struct intel_display *display = to_intel_display(encoder); 4793 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4794 4795 return intel_de_read(display, SDEISR) & bit; 4796 } 4797 4798 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4799 { 4800 struct intel_display *display = to_intel_display(encoder); 4801 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4802 4803 return intel_de_read(display, DEISR) & bit; 4804 } 4805 4806 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4807 { 4808 struct intel_display *display = to_intel_display(encoder); 4809 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4810 4811 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4812 } 4813 4814 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4815 { 4816 struct intel_connector *connector; 4817 enum port port = dig_port->base.port; 4818 4819 connector = intel_connector_alloc(); 4820 if (!connector) 4821 return -ENOMEM; 4822 4823 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4824 4825 if (!intel_hdmi_init_connector(dig_port, connector)) { 4826 /* 4827 * HDMI connector init failures may just mean conflicting DDC 4828 * pins or not having enough lanes. Handle them gracefully, but 4829 * don't fail the entire DDI init. 4830 */ 4831 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4832 kfree(connector); 4833 } 4834 4835 return 0; 4836 } 4837 4838 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4839 { 4840 struct intel_display *display = to_intel_display(dig_port); 4841 4842 if (dig_port->base.port != PORT_A) 4843 return false; 4844 4845 if (dig_port->ddi_a_4_lanes) 4846 return false; 4847 4848 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4849 * supported configuration 4850 */ 4851 if (display->platform.geminilake || display->platform.broxton) 4852 return true; 4853 4854 return false; 4855 } 4856 4857 static int 4858 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4859 { 4860 struct intel_display *display = to_intel_display(dig_port); 4861 enum port port = dig_port->base.port; 4862 int max_lanes = 4; 4863 4864 if (DISPLAY_VER(display) >= 11) 4865 return max_lanes; 4866 4867 if (port == PORT_A || port == PORT_E) { 4868 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4869 max_lanes = port == PORT_A ? 4 : 0; 4870 else 4871 /* Both A and E share 2 lanes */ 4872 max_lanes = 2; 4873 } 4874 4875 /* 4876 * Some BIOS might fail to set this bit on port A if eDP 4877 * wasn't lit up at boot. Force this bit set when needed 4878 * so we use the proper lane count for our calculations. 4879 */ 4880 if (intel_ddi_a_force_4_lanes(dig_port)) { 4881 drm_dbg_kms(display->drm, 4882 "Forcing DDI_A_4_LANES for port A\n"); 4883 dig_port->ddi_a_4_lanes = true; 4884 max_lanes = 4; 4885 } 4886 4887 return max_lanes; 4888 } 4889 4890 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4891 { 4892 if (port >= PORT_D_XELPD) 4893 return HPD_PORT_D + port - PORT_D_XELPD; 4894 else if (port >= PORT_TC1) 4895 return HPD_PORT_TC1 + port - PORT_TC1; 4896 else 4897 return HPD_PORT_A + port - PORT_A; 4898 } 4899 4900 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4901 { 4902 if (port >= PORT_TC1) 4903 return HPD_PORT_C + port - PORT_TC1; 4904 else 4905 return HPD_PORT_A + port - PORT_A; 4906 } 4907 4908 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4909 { 4910 if (port >= PORT_TC1) 4911 return HPD_PORT_TC1 + port - PORT_TC1; 4912 else 4913 return HPD_PORT_A + port - PORT_A; 4914 } 4915 4916 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4917 { 4918 if (HAS_PCH_TGP(display)) 4919 return tgl_hpd_pin(display, port); 4920 4921 if (port >= PORT_TC1) 4922 return HPD_PORT_C + port - PORT_TC1; 4923 else 4924 return HPD_PORT_A + port - PORT_A; 4925 } 4926 4927 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4928 { 4929 if (port >= PORT_C) 4930 return HPD_PORT_TC1 + port - PORT_C; 4931 else 4932 return HPD_PORT_A + port - PORT_A; 4933 } 4934 4935 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4936 { 4937 if (port == PORT_D) 4938 return HPD_PORT_A; 4939 4940 if (HAS_PCH_TGP(display)) 4941 return icl_hpd_pin(display, port); 4942 4943 return HPD_PORT_A + port - PORT_A; 4944 } 4945 4946 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4947 { 4948 if (HAS_PCH_TGP(display)) 4949 return icl_hpd_pin(display, port); 4950 4951 return HPD_PORT_A + port - PORT_A; 4952 } 4953 4954 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 4955 { 4956 if (DISPLAY_VER(display) >= 12) 4957 return port >= PORT_TC1; 4958 else if (DISPLAY_VER(display) >= 11) 4959 return port >= PORT_C; 4960 else 4961 return false; 4962 } 4963 4964 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4965 { 4966 intel_dp_encoder_suspend(encoder); 4967 } 4968 4969 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4970 { 4971 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4973 4974 /* 4975 * TODO: Move this to intel_dp_encoder_suspend(), 4976 * once modeset locking around that is removed. 4977 */ 4978 intel_encoder_link_check_flush_work(encoder); 4979 intel_tc_port_suspend(dig_port); 4980 } 4981 4982 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4983 { 4984 if (intel_encoder_is_dp(encoder)) 4985 intel_dp_encoder_shutdown(encoder); 4986 if (intel_encoder_is_hdmi(encoder)) 4987 intel_hdmi_encoder_shutdown(encoder); 4988 } 4989 4990 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4991 { 4992 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4993 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4994 4995 intel_tc_port_cleanup(dig_port); 4996 } 4997 4998 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4999 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5000 5001 static bool port_strap_detected(struct intel_display *display, enum port port) 5002 { 5003 /* straps not used on skl+ */ 5004 if (DISPLAY_VER(display) >= 9) 5005 return true; 5006 5007 switch (port) { 5008 case PORT_A: 5009 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5010 case PORT_B: 5011 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5012 case PORT_C: 5013 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5014 case PORT_D: 5015 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5016 case PORT_E: 5017 return true; /* no strap for DDI-E */ 5018 default: 5019 MISSING_CASE(port); 5020 return false; 5021 } 5022 } 5023 5024 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5025 { 5026 return init_dp || intel_encoder_is_tc(encoder); 5027 } 5028 5029 static bool assert_has_icl_dsi(struct intel_display *display) 5030 { 5031 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5032 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5033 "Platform does not support DSI\n"); 5034 } 5035 5036 static bool port_in_use(struct intel_display *display, enum port port) 5037 { 5038 struct intel_encoder *encoder; 5039 5040 for_each_intel_encoder(display->drm, encoder) { 5041 /* FIXME what about second port for dual link DSI? */ 5042 if (encoder->port == port) 5043 return true; 5044 } 5045 5046 return false; 5047 } 5048 5049 void intel_ddi_init(struct intel_display *display, 5050 const struct intel_bios_encoder_data *devdata) 5051 { 5052 struct intel_digital_port *dig_port; 5053 struct intel_encoder *encoder; 5054 bool init_hdmi, init_dp; 5055 enum port port; 5056 enum phy phy; 5057 u32 ddi_buf_ctl; 5058 5059 port = intel_bios_encoder_port(devdata); 5060 if (port == PORT_NONE) 5061 return; 5062 5063 if (!port_strap_detected(display, port)) { 5064 drm_dbg_kms(display->drm, 5065 "Port %c strap not detected\n", port_name(port)); 5066 return; 5067 } 5068 5069 if (!assert_port_valid(display, port)) 5070 return; 5071 5072 if (port_in_use(display, port)) { 5073 drm_dbg_kms(display->drm, 5074 "Port %c already claimed\n", port_name(port)); 5075 return; 5076 } 5077 5078 if (intel_bios_encoder_supports_dsi(devdata)) { 5079 /* BXT/GLK handled elsewhere, for now at least */ 5080 if (!assert_has_icl_dsi(display)) 5081 return; 5082 5083 icl_dsi_init(display, devdata); 5084 return; 5085 } 5086 5087 phy = intel_port_to_phy(display, port); 5088 5089 /* 5090 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5091 * have taken over some of the PHYs and made them unavailable to the 5092 * driver. In that case we should skip initializing the corresponding 5093 * outputs. 5094 */ 5095 if (intel_hti_uses_phy(display, phy)) { 5096 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5097 port_name(port), phy_name(phy)); 5098 return; 5099 } 5100 5101 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5102 intel_bios_encoder_supports_hdmi(devdata); 5103 init_dp = intel_bios_encoder_supports_dp(devdata); 5104 5105 if (intel_bios_encoder_is_lspcon(devdata)) { 5106 /* 5107 * Lspcon device needs to be driven with DP connector 5108 * with special detection sequence. So make sure DP 5109 * is initialized before lspcon. 5110 */ 5111 init_dp = true; 5112 init_hdmi = false; 5113 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5114 port_name(port)); 5115 } 5116 5117 if (!init_dp && !init_hdmi) { 5118 drm_dbg_kms(display->drm, 5119 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5120 port_name(port)); 5121 return; 5122 } 5123 5124 if (intel_phy_is_snps(display, phy) && 5125 display->snps.phy_failed_calibration & BIT(phy)) { 5126 drm_dbg_kms(display->drm, 5127 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5128 phy_name(phy)); 5129 } 5130 5131 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5132 if (!dig_port) 5133 return; 5134 5135 dig_port->aux_ch = AUX_CH_NONE; 5136 5137 encoder = &dig_port->base; 5138 encoder->devdata = devdata; 5139 5140 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5141 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5142 DRM_MODE_ENCODER_TMDS, 5143 "DDI %c/PHY %c", 5144 port_name(port - PORT_D_XELPD + PORT_D), 5145 phy_name(phy)); 5146 } else if (DISPLAY_VER(display) >= 12) { 5147 enum tc_port tc_port = intel_port_to_tc(display, port); 5148 5149 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5150 DRM_MODE_ENCODER_TMDS, 5151 "DDI %s%c/PHY %s%c", 5152 port >= PORT_TC1 ? "TC" : "", 5153 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5154 tc_port != TC_PORT_NONE ? "TC" : "", 5155 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5156 } else if (DISPLAY_VER(display) >= 11) { 5157 enum tc_port tc_port = intel_port_to_tc(display, port); 5158 5159 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5160 DRM_MODE_ENCODER_TMDS, 5161 "DDI %c%s/PHY %s%c", 5162 port_name(port), 5163 port >= PORT_C ? " (TC)" : "", 5164 tc_port != TC_PORT_NONE ? "TC" : "", 5165 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5166 } else { 5167 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5168 DRM_MODE_ENCODER_TMDS, 5169 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5170 } 5171 5172 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5173 5174 mutex_init(&dig_port->hdcp.mutex); 5175 dig_port->hdcp.num_streams = 0; 5176 5177 encoder->hotplug = intel_ddi_hotplug; 5178 encoder->compute_output_type = intel_ddi_compute_output_type; 5179 encoder->compute_config = intel_ddi_compute_config; 5180 encoder->compute_config_late = intel_ddi_compute_config_late; 5181 encoder->enable = intel_ddi_enable; 5182 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5183 encoder->pre_enable = intel_ddi_pre_enable; 5184 encoder->disable = intel_ddi_disable; 5185 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5186 encoder->post_disable = intel_ddi_post_disable; 5187 encoder->update_pipe = intel_ddi_update_pipe; 5188 encoder->audio_enable = intel_audio_codec_enable; 5189 encoder->audio_disable = intel_audio_codec_disable; 5190 encoder->get_hw_state = intel_ddi_get_hw_state; 5191 encoder->sync_state = intel_ddi_sync_state; 5192 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5193 encoder->suspend = intel_ddi_encoder_suspend; 5194 encoder->shutdown = intel_ddi_encoder_shutdown; 5195 encoder->get_power_domains = intel_ddi_get_power_domains; 5196 5197 encoder->type = INTEL_OUTPUT_DDI; 5198 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5199 encoder->port = port; 5200 encoder->cloneable = 0; 5201 encoder->pipe_mask = ~0; 5202 5203 if (DISPLAY_VER(display) >= 14) { 5204 encoder->enable_clock = intel_mtl_pll_enable; 5205 encoder->disable_clock = intel_mtl_pll_disable; 5206 encoder->port_pll_type = intel_mtl_port_pll_type; 5207 encoder->get_config = mtl_ddi_get_config; 5208 } else if (display->platform.dg2) { 5209 encoder->enable_clock = intel_mpllb_enable; 5210 encoder->disable_clock = intel_mpllb_disable; 5211 encoder->get_config = dg2_ddi_get_config; 5212 } else if (display->platform.alderlake_s) { 5213 encoder->enable_clock = adls_ddi_enable_clock; 5214 encoder->disable_clock = adls_ddi_disable_clock; 5215 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5216 encoder->get_config = adls_ddi_get_config; 5217 } else if (display->platform.rocketlake) { 5218 encoder->enable_clock = rkl_ddi_enable_clock; 5219 encoder->disable_clock = rkl_ddi_disable_clock; 5220 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5221 encoder->get_config = rkl_ddi_get_config; 5222 } else if (display->platform.dg1) { 5223 encoder->enable_clock = dg1_ddi_enable_clock; 5224 encoder->disable_clock = dg1_ddi_disable_clock; 5225 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5226 encoder->get_config = dg1_ddi_get_config; 5227 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5228 if (intel_ddi_is_tc(display, port)) { 5229 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5230 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5231 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5232 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5233 encoder->get_config = icl_ddi_combo_get_config; 5234 } else { 5235 encoder->enable_clock = icl_ddi_combo_enable_clock; 5236 encoder->disable_clock = icl_ddi_combo_disable_clock; 5237 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5238 encoder->get_config = icl_ddi_combo_get_config; 5239 } 5240 } else if (DISPLAY_VER(display) >= 11) { 5241 if (intel_ddi_is_tc(display, port)) { 5242 encoder->enable_clock = icl_ddi_tc_enable_clock; 5243 encoder->disable_clock = icl_ddi_tc_disable_clock; 5244 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5245 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5246 encoder->get_config = icl_ddi_tc_get_config; 5247 } else { 5248 encoder->enable_clock = icl_ddi_combo_enable_clock; 5249 encoder->disable_clock = icl_ddi_combo_disable_clock; 5250 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5251 encoder->get_config = icl_ddi_combo_get_config; 5252 } 5253 } else if (display->platform.geminilake || display->platform.broxton) { 5254 /* BXT/GLK have fixed PLL->port mapping */ 5255 encoder->get_config = bxt_ddi_get_config; 5256 } else if (DISPLAY_VER(display) == 9) { 5257 encoder->enable_clock = skl_ddi_enable_clock; 5258 encoder->disable_clock = skl_ddi_disable_clock; 5259 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5260 encoder->get_config = skl_ddi_get_config; 5261 } else if (display->platform.broadwell || display->platform.haswell) { 5262 encoder->enable_clock = hsw_ddi_enable_clock; 5263 encoder->disable_clock = hsw_ddi_disable_clock; 5264 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5265 encoder->get_config = hsw_ddi_get_config; 5266 } 5267 5268 if (DISPLAY_VER(display) >= 14) { 5269 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5270 } else if (display->platform.dg2) { 5271 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5272 } else if (DISPLAY_VER(display) >= 12) { 5273 if (intel_encoder_is_combo(encoder)) 5274 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5275 else 5276 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5277 } else if (DISPLAY_VER(display) >= 11) { 5278 if (intel_encoder_is_combo(encoder)) 5279 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5280 else 5281 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5282 } else if (display->platform.geminilake || display->platform.broxton) { 5283 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5284 } else { 5285 encoder->set_signal_levels = hsw_set_signal_levels; 5286 } 5287 5288 intel_ddi_buf_trans_init(encoder); 5289 5290 if (DISPLAY_VER(display) >= 13) 5291 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5292 else if (display->platform.dg1) 5293 encoder->hpd_pin = dg1_hpd_pin(display, port); 5294 else if (display->platform.rocketlake) 5295 encoder->hpd_pin = rkl_hpd_pin(display, port); 5296 else if (DISPLAY_VER(display) >= 12) 5297 encoder->hpd_pin = tgl_hpd_pin(display, port); 5298 else if (display->platform.jasperlake || display->platform.elkhartlake) 5299 encoder->hpd_pin = ehl_hpd_pin(display, port); 5300 else if (DISPLAY_VER(display) == 11) 5301 encoder->hpd_pin = icl_hpd_pin(display, port); 5302 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5303 encoder->hpd_pin = skl_hpd_pin(display, port); 5304 else 5305 encoder->hpd_pin = intel_hpd_pin_default(port); 5306 5307 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5308 5309 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5310 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5311 5312 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5313 5314 dig_port->dp.output_reg = INVALID_MMIO_REG; 5315 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5316 5317 if (need_aux_ch(encoder, init_dp)) { 5318 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5319 if (dig_port->aux_ch == AUX_CH_NONE) 5320 goto err; 5321 } 5322 5323 if (intel_encoder_is_tc(encoder)) { 5324 bool is_legacy = 5325 !intel_bios_encoder_supports_typec_usb(devdata) && 5326 !intel_bios_encoder_supports_tbt(devdata); 5327 5328 if (!is_legacy && init_hdmi) { 5329 is_legacy = !init_dp; 5330 5331 drm_dbg_kms(display->drm, 5332 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5333 port_name(port), 5334 str_yes_no(init_dp), 5335 is_legacy ? "legacy" : "non-legacy"); 5336 } 5337 5338 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5339 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5340 5341 dig_port->lock = intel_tc_port_lock; 5342 dig_port->unlock = intel_tc_port_unlock; 5343 5344 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5345 goto err; 5346 } 5347 5348 drm_WARN_ON(display->drm, port > PORT_I); 5349 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5350 5351 if (DISPLAY_VER(display) >= 11) { 5352 if (intel_encoder_is_tc(encoder)) 5353 dig_port->connected = intel_tc_port_connected; 5354 else 5355 dig_port->connected = lpt_digital_port_connected; 5356 } else if (display->platform.geminilake || display->platform.broxton) { 5357 dig_port->connected = bdw_digital_port_connected; 5358 } else if (DISPLAY_VER(display) == 9) { 5359 dig_port->connected = lpt_digital_port_connected; 5360 } else if (display->platform.broadwell) { 5361 if (port == PORT_A) 5362 dig_port->connected = bdw_digital_port_connected; 5363 else 5364 dig_port->connected = lpt_digital_port_connected; 5365 } else if (display->platform.haswell) { 5366 if (port == PORT_A) 5367 dig_port->connected = hsw_digital_port_connected; 5368 else 5369 dig_port->connected = lpt_digital_port_connected; 5370 } 5371 5372 intel_infoframe_init(dig_port); 5373 5374 if (init_dp) { 5375 if (intel_ddi_init_dp_connector(dig_port)) 5376 goto err; 5377 5378 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5379 5380 if (dig_port->dp.mso_link_count) 5381 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5382 } 5383 5384 /* 5385 * In theory we don't need the encoder->type check, 5386 * but leave it just in case we have some really bad VBTs... 5387 */ 5388 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5389 if (intel_ddi_init_hdmi_connector(dig_port)) 5390 goto err; 5391 } 5392 5393 return; 5394 5395 err: 5396 drm_encoder_cleanup(&encoder->base); 5397 kfree(dig_port); 5398 } 5399