1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_privacy_screen_consumer.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "icl_dsi.h" 38 #include "intel_audio.h" 39 #include "intel_audio_regs.h" 40 #include "intel_backlight.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_cx0_phy.h" 46 #include "intel_cx0_phy_regs.h" 47 #include "intel_ddi.h" 48 #include "intel_ddi_buf_trans.h" 49 #include "intel_de.h" 50 #include "intel_display_power.h" 51 #include "intel_display_types.h" 52 #include "intel_dkl_phy.h" 53 #include "intel_dkl_phy_regs.h" 54 #include "intel_dp.h" 55 #include "intel_dp_aux.h" 56 #include "intel_dp_link_training.h" 57 #include "intel_dp_mst.h" 58 #include "intel_dp_test.h" 59 #include "intel_dp_tunnel.h" 60 #include "intel_dpio_phy.h" 61 #include "intel_dsi.h" 62 #include "intel_encoder.h" 63 #include "intel_fdi.h" 64 #include "intel_fifo_underrun.h" 65 #include "intel_gmbus.h" 66 #include "intel_hdcp.h" 67 #include "intel_hdmi.h" 68 #include "intel_hotplug.h" 69 #include "intel_hti.h" 70 #include "intel_lspcon.h" 71 #include "intel_mg_phy_regs.h" 72 #include "intel_modeset_lock.h" 73 #include "intel_pps.h" 74 #include "intel_psr.h" 75 #include "intel_quirks.h" 76 #include "intel_snps_phy.h" 77 #include "intel_tc.h" 78 #include "intel_vdsc.h" 79 #include "intel_vdsc_regs.h" 80 #include "skl_scaler.h" 81 #include "skl_universal_plane.h" 82 83 static const u8 index_to_dp_signal_levels[] = { 84 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 88 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 91 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 }; 95 96 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 97 const struct intel_ddi_buf_trans *trans) 98 { 99 int level; 100 101 level = intel_bios_hdmi_level_shift(encoder->devdata); 102 if (level < 0) 103 level = trans->hdmi_default_entry; 104 105 return level; 106 } 107 108 static bool has_buf_trans_select(struct drm_i915_private *i915) 109 { 110 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 111 } 112 113 static bool has_iboost(struct drm_i915_private *i915) 114 { 115 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 116 } 117 118 /* 119 * Starting with Haswell, DDI port buffers must be programmed with correct 120 * values in advance. This function programs the correct values for 121 * DP/eDP/FDI use cases. 122 */ 123 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 124 const struct intel_crtc_state *crtc_state) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 u32 iboost_bit = 0; 128 int i, n_entries; 129 enum port port = encoder->port; 130 const struct intel_ddi_buf_trans *trans; 131 132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 134 return; 135 136 /* If we're boosting the current, set bit 31 of trans1 */ 137 if (has_iboost(dev_priv) && 138 intel_bios_dp_boost_level(encoder->devdata)) 139 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 140 141 for (i = 0; i < n_entries; i++) { 142 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 143 trans->entries[i].hsw.trans1 | iboost_bit); 144 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 145 trans->entries[i].hsw.trans2); 146 } 147 } 148 149 /* 150 * Starting with Haswell, DDI port buffers must be programmed with correct 151 * values in advance. This function programs the correct values for 152 * HDMI/DVI use cases. 153 */ 154 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 155 const struct intel_crtc_state *crtc_state) 156 { 157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 158 int level = intel_ddi_level(encoder, crtc_state, 0); 159 u32 iboost_bit = 0; 160 int n_entries; 161 enum port port = encoder->port; 162 const struct intel_ddi_buf_trans *trans; 163 164 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 165 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 166 return; 167 168 /* If we're boosting the current, set bit 31 of trans1 */ 169 if (has_iboost(dev_priv) && 170 intel_bios_hdmi_boost_level(encoder->devdata)) 171 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 172 173 /* Entry 9 is for HDMI: */ 174 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 175 trans->entries[level].hsw.trans1 | iboost_bit); 176 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 177 trans->entries[level].hsw.trans2); 178 } 179 180 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 181 { 182 int ret; 183 184 /* FIXME: find out why Bspec's 100us timeout is too short */ 185 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 186 XELPDP_PORT_BUF_PHY_IDLE), 10000); 187 if (ret) 188 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 189 port_name(port)); 190 } 191 192 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 193 enum port port) 194 { 195 if (IS_BROXTON(dev_priv)) { 196 udelay(16); 197 return; 198 } 199 200 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 201 DDI_BUF_IS_IDLE), 8)) 202 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 203 port_name(port)); 204 } 205 206 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 207 { 208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 209 enum port port = encoder->port; 210 int timeout_us; 211 int ret; 212 213 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 214 if (DISPLAY_VER(dev_priv) < 10) { 215 usleep_range(518, 1000); 216 return; 217 } 218 219 if (DISPLAY_VER(dev_priv) >= 14) { 220 timeout_us = 10000; 221 } else if (IS_DG2(dev_priv)) { 222 timeout_us = 1200; 223 } else if (DISPLAY_VER(dev_priv) >= 12) { 224 if (intel_encoder_is_tc(encoder)) 225 timeout_us = 3000; 226 else 227 timeout_us = 1000; 228 } else { 229 timeout_us = 500; 230 } 231 232 if (DISPLAY_VER(dev_priv) >= 14) 233 ret = _wait_for(!(intel_de_read(dev_priv, 234 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 235 XELPDP_PORT_BUF_PHY_IDLE), 236 timeout_us, 10, 10); 237 else 238 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 239 timeout_us, 10, 10); 240 241 if (ret) 242 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state) 333 { 334 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 336 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 337 338 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 339 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 340 DDI_BUF_TRANS_SELECT(0); 341 342 if (dig_port->lane_reversal) 343 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 344 if (dig_port->ddi_a_4_lanes) 345 intel_dp->DP |= DDI_A_4_LANES; 346 347 if (DISPLAY_VER(i915) >= 14) { 348 if (intel_dp_is_uhbr(crtc_state)) 349 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 350 else 351 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 352 } 353 354 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 355 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 356 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 357 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 358 } 359 } 360 361 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 362 enum port port) 363 { 364 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 365 366 switch (val) { 367 case DDI_CLK_SEL_NONE: 368 return 0; 369 case DDI_CLK_SEL_TBT_162: 370 return 162000; 371 case DDI_CLK_SEL_TBT_270: 372 return 270000; 373 case DDI_CLK_SEL_TBT_540: 374 return 540000; 375 case DDI_CLK_SEL_TBT_810: 376 return 810000; 377 default: 378 MISSING_CASE(val); 379 return 0; 380 } 381 } 382 383 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 384 { 385 /* CRT dotclock is determined via other means */ 386 if (pipe_config->has_pch_encoder) 387 return; 388 389 pipe_config->hw.adjusted_mode.crtc_clock = 390 intel_crtc_dotclock(pipe_config); 391 } 392 393 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 394 const struct drm_connector_state *conn_state) 395 { 396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 398 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 399 u32 temp; 400 401 if (!intel_crtc_has_dp_encoder(crtc_state)) 402 return; 403 404 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 405 406 temp = DP_MSA_MISC_SYNC_CLOCK; 407 408 switch (crtc_state->pipe_bpp) { 409 case 18: 410 temp |= DP_MSA_MISC_6_BPC; 411 break; 412 case 24: 413 temp |= DP_MSA_MISC_8_BPC; 414 break; 415 case 30: 416 temp |= DP_MSA_MISC_10_BPC; 417 break; 418 case 36: 419 temp |= DP_MSA_MISC_12_BPC; 420 break; 421 default: 422 MISSING_CASE(crtc_state->pipe_bpp); 423 break; 424 } 425 426 /* nonsense combination */ 427 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 428 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 429 430 if (crtc_state->limited_color_range) 431 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 432 433 /* 434 * As per DP 1.2 spec section 2.3.4.3 while sending 435 * YCBCR 444 signals we should program MSA MISC1/0 fields with 436 * colorspace information. 437 */ 438 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 439 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 440 441 /* 442 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 443 * of Color Encoding Format and Content Color Gamut] while sending 444 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 445 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 446 */ 447 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 448 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 449 450 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 451 temp); 452 } 453 454 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 455 { 456 if (master_transcoder == TRANSCODER_EDP) 457 return 0; 458 else 459 return master_transcoder + 1; 460 } 461 462 static void 463 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 464 bool enable) 465 { 466 struct intel_display *display = to_intel_display(crtc_state); 467 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 468 u32 val = 0; 469 470 if (!HAS_DP20(display)) 471 return; 472 473 if (enable && intel_dp_is_uhbr(crtc_state)) 474 val = TRANS_DP2_128B132B_CHANNEL_CODING; 475 476 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 477 } 478 479 /* 480 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 481 * 482 * Only intended to be used by intel_ddi_enable_transcoder_func() and 483 * intel_ddi_config_transcoder_func(). 484 */ 485 static u32 486 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 487 const struct intel_crtc_state *crtc_state) 488 { 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 enum pipe pipe = crtc->pipe; 492 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 493 enum port port = encoder->port; 494 u32 temp; 495 496 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 497 temp = TRANS_DDI_FUNC_ENABLE; 498 if (DISPLAY_VER(dev_priv) >= 12) 499 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 500 else 501 temp |= TRANS_DDI_SELECT_PORT(port); 502 503 switch (crtc_state->pipe_bpp) { 504 default: 505 MISSING_CASE(crtc_state->pipe_bpp); 506 fallthrough; 507 case 18: 508 temp |= TRANS_DDI_BPC_6; 509 break; 510 case 24: 511 temp |= TRANS_DDI_BPC_8; 512 break; 513 case 30: 514 temp |= TRANS_DDI_BPC_10; 515 break; 516 case 36: 517 temp |= TRANS_DDI_BPC_12; 518 break; 519 } 520 521 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 522 temp |= TRANS_DDI_PVSYNC; 523 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 524 temp |= TRANS_DDI_PHSYNC; 525 526 if (cpu_transcoder == TRANSCODER_EDP) { 527 switch (pipe) { 528 default: 529 MISSING_CASE(pipe); 530 fallthrough; 531 case PIPE_A: 532 /* On Haswell, can only use the always-on power well for 533 * eDP when not using the panel fitter, and when not 534 * using motion blur mitigation (which we don't 535 * support). */ 536 if (crtc_state->pch_pfit.force_thru) 537 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 538 else 539 temp |= TRANS_DDI_EDP_INPUT_A_ON; 540 break; 541 case PIPE_B: 542 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 543 break; 544 case PIPE_C: 545 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 546 break; 547 } 548 } 549 550 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 551 if (crtc_state->has_hdmi_sink) 552 temp |= TRANS_DDI_MODE_SELECT_HDMI; 553 else 554 temp |= TRANS_DDI_MODE_SELECT_DVI; 555 556 if (crtc_state->hdmi_scrambling) 557 temp |= TRANS_DDI_HDMI_SCRAMBLING; 558 if (crtc_state->hdmi_high_tmds_clock_ratio) 559 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 560 if (DISPLAY_VER(dev_priv) >= 14) 561 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 562 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 563 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 564 temp |= (crtc_state->fdi_lanes - 1) << 1; 565 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 566 intel_dp_is_uhbr(crtc_state)) { 567 if (intel_dp_is_uhbr(crtc_state)) 568 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 569 else 570 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 573 if (DISPLAY_VER(dev_priv) >= 12) { 574 enum transcoder master; 575 576 master = crtc_state->mst_master_transcoder; 577 drm_WARN_ON(&dev_priv->drm, 578 master == INVALID_TRANSCODER); 579 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 580 } 581 } else { 582 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 583 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 584 } 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 587 crtc_state->master_transcoder != INVALID_TRANSCODER) { 588 u8 master_select = 589 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 590 591 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 592 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 593 } 594 595 return temp; 596 } 597 598 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 599 const struct intel_crtc_state *crtc_state) 600 { 601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 603 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 604 605 if (DISPLAY_VER(dev_priv) >= 11) { 606 enum transcoder master_transcoder = crtc_state->master_transcoder; 607 u32 ctl2 = 0; 608 609 if (master_transcoder != INVALID_TRANSCODER) { 610 u8 master_select = 611 bdw_trans_port_sync_master_select(master_transcoder); 612 613 ctl2 |= PORT_SYNC_MODE_ENABLE | 614 PORT_SYNC_MODE_MASTER_SELECT(master_select); 615 } 616 617 intel_de_write(dev_priv, 618 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 619 ctl2); 620 } 621 622 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 623 intel_ddi_transcoder_func_reg_val_get(encoder, 624 crtc_state)); 625 } 626 627 /* 628 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 629 * bit for the DDI function and enables the DP2 configuration. Called for all 630 * transcoder types. 631 */ 632 void 633 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 634 const struct intel_crtc_state *crtc_state) 635 { 636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 638 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 639 u32 ctl; 640 641 intel_ddi_config_transcoder_dp2(crtc_state, true); 642 643 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 644 ctl &= ~TRANS_DDI_FUNC_ENABLE; 645 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 646 ctl); 647 } 648 649 /* 650 * Disable the DDI function and port syncing. 651 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 652 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 653 * transcoders these are done later in intel_ddi_post_disable_dp(). 654 */ 655 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 656 { 657 struct intel_display *display = to_intel_display(crtc_state); 658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 660 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 661 u32 ctl; 662 663 if (DISPLAY_VER(dev_priv) >= 11) 664 intel_de_write(dev_priv, 665 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 666 0); 667 668 ctl = intel_de_read(dev_priv, 669 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 670 671 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 672 673 ctl &= ~TRANS_DDI_FUNC_ENABLE; 674 675 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 676 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 677 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 678 679 if (DISPLAY_VER(dev_priv) >= 12) { 680 if (!intel_dp_mst_is_master_trans(crtc_state)) { 681 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 682 TRANS_DDI_MODE_SELECT_MASK); 683 } 684 } else { 685 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 686 } 687 688 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 689 ctl); 690 691 if (intel_dp_mst_is_slave_trans(crtc_state)) 692 intel_ddi_config_transcoder_dp2(crtc_state, false); 693 694 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 695 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 696 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 697 /* Quirk time at 100ms for reliable operation */ 698 msleep(100); 699 } 700 } 701 702 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 703 enum transcoder cpu_transcoder, 704 bool enable, u32 hdcp_mask) 705 { 706 struct drm_device *dev = intel_encoder->base.dev; 707 struct drm_i915_private *dev_priv = to_i915(dev); 708 intel_wakeref_t wakeref; 709 int ret = 0; 710 711 wakeref = intel_display_power_get_if_enabled(dev_priv, 712 intel_encoder->power_domain); 713 if (drm_WARN_ON(dev, !wakeref)) 714 return -ENXIO; 715 716 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 717 hdcp_mask, enable ? hdcp_mask : 0); 718 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 719 return ret; 720 } 721 722 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 723 { 724 struct intel_display *display = to_intel_display(intel_connector); 725 struct drm_i915_private *dev_priv = to_i915(display->drm); 726 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 727 int type = intel_connector->base.connector_type; 728 enum port port = encoder->port; 729 enum transcoder cpu_transcoder; 730 intel_wakeref_t wakeref; 731 enum pipe pipe = 0; 732 u32 ddi_mode; 733 bool ret; 734 735 wakeref = intel_display_power_get_if_enabled(dev_priv, 736 encoder->power_domain); 737 if (!wakeref) 738 return false; 739 740 /* Note: This returns false for DP MST primary encoders. */ 741 if (!encoder->get_hw_state(encoder, &pipe)) { 742 ret = false; 743 goto out; 744 } 745 746 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 747 cpu_transcoder = TRANSCODER_EDP; 748 else 749 cpu_transcoder = (enum transcoder) pipe; 750 751 ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 752 TRANS_DDI_MODE_SELECT_MASK; 753 754 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 755 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 756 ret = type == DRM_MODE_CONNECTOR_HDMIA; 757 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 758 ret = type == DRM_MODE_CONNECTOR_VGA; 759 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 760 ret = type == DRM_MODE_CONNECTOR_eDP || 761 type == DRM_MODE_CONNECTOR_DisplayPort; 762 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 763 /* 764 * encoder->get_hw_state() should have bailed out on MST. This 765 * must be SST and non-eDP. 766 */ 767 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 768 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 769 /* encoder->get_hw_state() should have bailed out on MST. */ 770 ret = false; 771 } else { 772 ret = false; 773 } 774 775 out: 776 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 777 778 return ret; 779 } 780 781 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 782 u8 *pipe_mask, bool *is_dp_mst) 783 { 784 struct intel_display *display = to_intel_display(encoder); 785 struct drm_i915_private *dev_priv = to_i915(display->drm); 786 enum port port = encoder->port; 787 intel_wakeref_t wakeref; 788 enum pipe p; 789 u32 tmp; 790 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 791 792 *pipe_mask = 0; 793 *is_dp_mst = false; 794 795 wakeref = intel_display_power_get_if_enabled(dev_priv, 796 encoder->power_domain); 797 if (!wakeref) 798 return; 799 800 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 801 if (!(tmp & DDI_BUF_CTL_ENABLE)) 802 goto out; 803 804 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 805 tmp = intel_de_read(dev_priv, 806 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 807 808 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 809 default: 810 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 811 fallthrough; 812 case TRANS_DDI_EDP_INPUT_A_ON: 813 case TRANS_DDI_EDP_INPUT_A_ONOFF: 814 *pipe_mask = BIT(PIPE_A); 815 break; 816 case TRANS_DDI_EDP_INPUT_B_ONOFF: 817 *pipe_mask = BIT(PIPE_B); 818 break; 819 case TRANS_DDI_EDP_INPUT_C_ONOFF: 820 *pipe_mask = BIT(PIPE_C); 821 break; 822 } 823 824 goto out; 825 } 826 827 for_each_pipe(dev_priv, p) { 828 enum transcoder cpu_transcoder = (enum transcoder)p; 829 u32 port_mask, ddi_select, ddi_mode; 830 intel_wakeref_t trans_wakeref; 831 832 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 833 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 834 if (!trans_wakeref) 835 continue; 836 837 if (DISPLAY_VER(dev_priv) >= 12) { 838 port_mask = TGL_TRANS_DDI_PORT_MASK; 839 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 840 } else { 841 port_mask = TRANS_DDI_PORT_MASK; 842 ddi_select = TRANS_DDI_SELECT_PORT(port); 843 } 844 845 tmp = intel_de_read(dev_priv, 846 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 847 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 848 trans_wakeref); 849 850 if ((tmp & port_mask) != ddi_select) 851 continue; 852 853 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 854 855 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 856 mst_pipe_mask |= BIT(p); 857 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 858 dp128b132b_pipe_mask |= BIT(p); 859 860 *pipe_mask |= BIT(p); 861 } 862 863 if (!*pipe_mask) 864 drm_dbg_kms(&dev_priv->drm, 865 "No pipe for [ENCODER:%d:%s] found\n", 866 encoder->base.base.id, encoder->base.name); 867 868 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 869 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 870 871 /* 872 * If we don't have 8b/10b MST, but have more than one 873 * transcoder in 128b/132b mode, we know it must be 128b/132b 874 * MST. 875 * 876 * Otherwise, we fall back to checking the current MST 877 * state. It's not accurate for hardware takeover at probe, but 878 * we don't expect MST to have been enabled at that point, and 879 * can assume it's SST. 880 */ 881 if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst) 882 mst_pipe_mask = dp128b132b_pipe_mask; 883 } 884 885 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 886 drm_dbg_kms(&dev_priv->drm, 887 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 888 encoder->base.base.id, encoder->base.name, 889 *pipe_mask); 890 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 891 } 892 893 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 894 drm_dbg_kms(&dev_priv->drm, 895 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 896 encoder->base.base.id, encoder->base.name, 897 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 898 else 899 *is_dp_mst = mst_pipe_mask; 900 901 out: 902 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 903 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 904 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 905 BXT_PHY_LANE_POWERDOWN_ACK | 906 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 907 drm_err(&dev_priv->drm, 908 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 909 encoder->base.base.id, encoder->base.name, tmp); 910 } 911 912 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 913 } 914 915 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 916 enum pipe *pipe) 917 { 918 u8 pipe_mask; 919 bool is_mst; 920 921 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 922 923 if (is_mst || !pipe_mask) 924 return false; 925 926 *pipe = ffs(pipe_mask) - 1; 927 928 return true; 929 } 930 931 static enum intel_display_power_domain 932 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 933 const struct intel_crtc_state *crtc_state) 934 { 935 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 936 937 /* 938 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 939 * DC states enabled at the same time, while for driver initiated AUX 940 * transfers we need the same AUX IOs to be powered but with DC states 941 * disabled. Accordingly use the AUX_IO_<port> power domain here which 942 * leaves DC states enabled. 943 * 944 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 945 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 946 * well, so we can acquire a wider AUX_<port> power domain reference 947 * instead of a specific AUX_IO_<port> reference without powering up any 948 * extra wells. 949 */ 950 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 951 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 952 else if (DISPLAY_VER(i915) < 14 && 953 (intel_crtc_has_dp_encoder(crtc_state) || 954 intel_encoder_is_tc(&dig_port->base))) 955 return intel_aux_power_domain(dig_port); 956 else 957 return POWER_DOMAIN_INVALID; 958 } 959 960 static void 961 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 962 const struct intel_crtc_state *crtc_state) 963 { 964 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 965 enum intel_display_power_domain domain = 966 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 967 968 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 969 970 if (domain == POWER_DOMAIN_INVALID) 971 return; 972 973 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 974 } 975 976 static void 977 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 978 const struct intel_crtc_state *crtc_state) 979 { 980 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 981 enum intel_display_power_domain domain = 982 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 983 intel_wakeref_t wf; 984 985 wf = fetch_and_zero(&dig_port->aux_wakeref); 986 if (!wf) 987 return; 988 989 intel_display_power_put(i915, domain, wf); 990 } 991 992 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 993 struct intel_crtc_state *crtc_state) 994 { 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 struct intel_digital_port *dig_port; 997 998 /* 999 * TODO: Add support for MST encoders. Atm, the following should never 1000 * happen since fake-MST encoders don't set their get_power_domains() 1001 * hook. 1002 */ 1003 if (drm_WARN_ON(&dev_priv->drm, 1004 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1005 return; 1006 1007 dig_port = enc_to_dig_port(encoder); 1008 1009 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1010 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 1011 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 1012 dig_port->ddi_io_power_domain); 1013 } 1014 1015 main_link_aux_power_domain_get(dig_port, crtc_state); 1016 } 1017 1018 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1019 const struct intel_crtc_state *crtc_state) 1020 { 1021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1024 enum phy phy = intel_encoder_to_phy(encoder); 1025 u32 val; 1026 1027 if (cpu_transcoder == TRANSCODER_EDP) 1028 return; 1029 1030 if (DISPLAY_VER(dev_priv) >= 13) 1031 val = TGL_TRANS_CLK_SEL_PORT(phy); 1032 else if (DISPLAY_VER(dev_priv) >= 12) 1033 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1034 else 1035 val = TRANS_CLK_SEL_PORT(encoder->port); 1036 1037 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1038 } 1039 1040 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1041 { 1042 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1043 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1044 u32 val; 1045 1046 if (cpu_transcoder == TRANSCODER_EDP) 1047 return; 1048 1049 if (DISPLAY_VER(dev_priv) >= 12) 1050 val = TGL_TRANS_CLK_SEL_DISABLED; 1051 else 1052 val = TRANS_CLK_SEL_DISABLED; 1053 1054 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1055 } 1056 1057 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1058 enum port port, u8 iboost) 1059 { 1060 u32 tmp; 1061 1062 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1063 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1064 if (iboost) 1065 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1066 else 1067 tmp |= BALANCE_LEG_DISABLE(port); 1068 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1069 } 1070 1071 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1072 const struct intel_crtc_state *crtc_state, 1073 int level) 1074 { 1075 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1077 u8 iboost; 1078 1079 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1080 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1081 else 1082 iboost = intel_bios_dp_boost_level(encoder->devdata); 1083 1084 if (iboost == 0) { 1085 const struct intel_ddi_buf_trans *trans; 1086 int n_entries; 1087 1088 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1089 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1090 return; 1091 1092 iboost = trans->entries[level].hsw.i_boost; 1093 } 1094 1095 /* Make sure that the requested I_boost is valid */ 1096 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1097 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1098 return; 1099 } 1100 1101 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1102 1103 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1104 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1105 } 1106 1107 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1108 const struct intel_crtc_state *crtc_state) 1109 { 1110 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 int n_entries; 1113 1114 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1115 1116 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1117 n_entries = 1; 1118 if (drm_WARN_ON(&dev_priv->drm, 1119 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1120 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1121 1122 return index_to_dp_signal_levels[n_entries - 1] & 1123 DP_TRAIN_VOLTAGE_SWING_MASK; 1124 } 1125 1126 /* 1127 * We assume that the full set of pre-emphasis values can be 1128 * used on all DDI platforms. Should that change we need to 1129 * rethink this code. 1130 */ 1131 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1132 { 1133 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1134 } 1135 1136 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1137 int lane) 1138 { 1139 if (crtc_state->port_clock > 600000) 1140 return 0; 1141 1142 if (crtc_state->lane_count == 4) 1143 return lane >= 1 ? LOADGEN_SELECT : 0; 1144 else 1145 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1146 } 1147 1148 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1149 const struct intel_crtc_state *crtc_state) 1150 { 1151 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1152 const struct intel_ddi_buf_trans *trans; 1153 enum phy phy = intel_encoder_to_phy(encoder); 1154 int n_entries, ln; 1155 u32 val; 1156 1157 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1158 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1159 return; 1160 1161 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1162 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1163 1164 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1165 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1166 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1167 intel_dp->hobl_active ? val : 0); 1168 } 1169 1170 /* Set PORT_TX_DW5 */ 1171 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1172 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1173 TAP2_DISABLE | TAP3_DISABLE); 1174 val |= SCALING_MODE_SEL(0x2); 1175 val |= RTERM_SELECT(0x6); 1176 val |= TAP3_DISABLE; 1177 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1178 1179 /* Program PORT_TX_DW2 */ 1180 for (ln = 0; ln < 4; ln++) { 1181 int level = intel_ddi_level(encoder, crtc_state, ln); 1182 1183 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1184 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1185 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1186 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1187 RCOMP_SCALAR(0x98)); 1188 } 1189 1190 /* Program PORT_TX_DW4 */ 1191 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1192 for (ln = 0; ln < 4; ln++) { 1193 int level = intel_ddi_level(encoder, crtc_state, ln); 1194 1195 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1196 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1197 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1198 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1199 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1200 } 1201 1202 /* Program PORT_TX_DW7 */ 1203 for (ln = 0; ln < 4; ln++) { 1204 int level = intel_ddi_level(encoder, crtc_state, ln); 1205 1206 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1207 N_SCALAR_MASK, 1208 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1209 } 1210 } 1211 1212 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1213 const struct intel_crtc_state *crtc_state) 1214 { 1215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1216 enum phy phy = intel_encoder_to_phy(encoder); 1217 u32 val; 1218 int ln; 1219 1220 /* 1221 * 1. If port type is eDP or DP, 1222 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1223 * else clear to 0b. 1224 */ 1225 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1226 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1227 val &= ~COMMON_KEEPER_EN; 1228 else 1229 val |= COMMON_KEEPER_EN; 1230 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1231 1232 /* 2. Program loadgen select */ 1233 /* 1234 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1235 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1236 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1237 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1238 */ 1239 for (ln = 0; ln < 4; ln++) { 1240 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1241 LOADGEN_SELECT, 1242 icl_combo_phy_loadgen_select(crtc_state, ln)); 1243 } 1244 1245 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1246 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1247 0, SUS_CLOCK_CONFIG); 1248 1249 /* 4. Clear training enable to change swing values */ 1250 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1251 val &= ~TX_TRAINING_EN; 1252 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1253 1254 /* 5. Program swing and de-emphasis */ 1255 icl_ddi_combo_vswing_program(encoder, crtc_state); 1256 1257 /* 6. Set training enable to trigger update */ 1258 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1259 val |= TX_TRAINING_EN; 1260 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1261 } 1262 1263 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1264 const struct intel_crtc_state *crtc_state) 1265 { 1266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1267 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1268 const struct intel_ddi_buf_trans *trans; 1269 int n_entries, ln; 1270 1271 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1272 return; 1273 1274 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1275 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1276 return; 1277 1278 for (ln = 0; ln < 2; ln++) { 1279 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1280 CRI_USE_FS32, 0); 1281 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1282 CRI_USE_FS32, 0); 1283 } 1284 1285 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1286 for (ln = 0; ln < 2; ln++) { 1287 int level; 1288 1289 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1290 1291 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1292 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1293 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1294 1295 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1296 1297 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1298 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1299 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1300 } 1301 1302 /* Program MG_TX_DRVCTRL with values from vswing table */ 1303 for (ln = 0; ln < 2; ln++) { 1304 int level; 1305 1306 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1307 1308 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1309 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1310 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1311 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1312 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1313 CRI_TXDEEMPH_OVERRIDE_EN); 1314 1315 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1316 1317 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1318 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1319 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1320 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1321 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1322 CRI_TXDEEMPH_OVERRIDE_EN); 1323 1324 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1325 } 1326 1327 /* 1328 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1329 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1330 * values from table for which TX1 and TX2 enabled. 1331 */ 1332 for (ln = 0; ln < 2; ln++) { 1333 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1334 CFG_LOW_RATE_LKREN_EN, 1335 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1336 } 1337 1338 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1339 for (ln = 0; ln < 2; ln++) { 1340 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1341 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1342 CFG_AMI_CK_DIV_OVERRIDE_EN, 1343 crtc_state->port_clock > 500000 ? 1344 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1345 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1346 1347 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1348 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1349 CFG_AMI_CK_DIV_OVERRIDE_EN, 1350 crtc_state->port_clock > 500000 ? 1351 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1352 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1353 } 1354 1355 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1356 for (ln = 0; ln < 2; ln++) { 1357 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1358 0, CRI_CALCINIT); 1359 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1360 0, CRI_CALCINIT); 1361 } 1362 } 1363 1364 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1365 const struct intel_crtc_state *crtc_state) 1366 { 1367 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1368 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1369 const struct intel_ddi_buf_trans *trans; 1370 int n_entries, ln; 1371 1372 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1373 return; 1374 1375 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1376 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1377 return; 1378 1379 for (ln = 0; ln < 2; ln++) { 1380 int level; 1381 1382 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1383 1384 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1385 1386 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1387 DKL_TX_PRESHOOT_COEFF_MASK | 1388 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1389 DKL_TX_VSWING_CONTROL_MASK, 1390 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1391 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1392 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1393 1394 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1395 1396 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1397 DKL_TX_PRESHOOT_COEFF_MASK | 1398 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1399 DKL_TX_VSWING_CONTROL_MASK, 1400 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1401 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1402 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1403 1404 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1405 DKL_TX_DP20BITMODE, 0); 1406 1407 if (IS_ALDERLAKE_P(dev_priv)) { 1408 u32 val; 1409 1410 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1411 if (ln == 0) { 1412 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1413 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1414 } else { 1415 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1416 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1417 } 1418 } else { 1419 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1420 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1421 } 1422 1423 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1424 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1425 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1426 val); 1427 } 1428 } 1429 } 1430 1431 static int translate_signal_level(struct intel_dp *intel_dp, 1432 u8 signal_levels) 1433 { 1434 struct intel_display *display = to_intel_display(intel_dp); 1435 int i; 1436 1437 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1438 if (index_to_dp_signal_levels[i] == signal_levels) 1439 return i; 1440 } 1441 1442 drm_WARN(display->drm, 1, 1443 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1444 signal_levels); 1445 1446 return 0; 1447 } 1448 1449 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1450 const struct intel_crtc_state *crtc_state, 1451 int lane) 1452 { 1453 u8 train_set = intel_dp->train_set[lane]; 1454 1455 if (intel_dp_is_uhbr(crtc_state)) { 1456 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1457 } else { 1458 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1459 DP_TRAIN_PRE_EMPHASIS_MASK); 1460 1461 return translate_signal_level(intel_dp, signal_levels); 1462 } 1463 } 1464 1465 int intel_ddi_level(struct intel_encoder *encoder, 1466 const struct intel_crtc_state *crtc_state, 1467 int lane) 1468 { 1469 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1470 const struct intel_ddi_buf_trans *trans; 1471 int level, n_entries; 1472 1473 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1474 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1475 return 0; 1476 1477 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1478 level = intel_ddi_hdmi_level(encoder, trans); 1479 else 1480 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1481 lane); 1482 1483 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1484 level = n_entries - 1; 1485 1486 return level; 1487 } 1488 1489 static void 1490 hsw_set_signal_levels(struct intel_encoder *encoder, 1491 const struct intel_crtc_state *crtc_state) 1492 { 1493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1494 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1495 int level = intel_ddi_level(encoder, crtc_state, 0); 1496 enum port port = encoder->port; 1497 u32 signal_levels; 1498 1499 if (has_iboost(dev_priv)) 1500 skl_ddi_set_iboost(encoder, crtc_state, level); 1501 1502 /* HDMI ignores the rest */ 1503 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1504 return; 1505 1506 signal_levels = DDI_BUF_TRANS_SELECT(level); 1507 1508 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1509 signal_levels); 1510 1511 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1512 intel_dp->DP |= signal_levels; 1513 1514 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1515 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1516 } 1517 1518 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1519 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1520 { 1521 mutex_lock(&i915->display.dpll.lock); 1522 1523 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1524 1525 /* 1526 * "This step and the step before must be 1527 * done with separate register writes." 1528 */ 1529 intel_de_rmw(i915, reg, clk_off, 0); 1530 1531 mutex_unlock(&i915->display.dpll.lock); 1532 } 1533 1534 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1535 u32 clk_off) 1536 { 1537 mutex_lock(&i915->display.dpll.lock); 1538 1539 intel_de_rmw(i915, reg, 0, clk_off); 1540 1541 mutex_unlock(&i915->display.dpll.lock); 1542 } 1543 1544 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1545 u32 clk_off) 1546 { 1547 return !(intel_de_read(i915, reg) & clk_off); 1548 } 1549 1550 static struct intel_shared_dpll * 1551 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1552 u32 clk_sel_mask, u32 clk_sel_shift) 1553 { 1554 enum intel_dpll_id id; 1555 1556 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1557 1558 return intel_get_shared_dpll_by_id(i915, id); 1559 } 1560 1561 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1562 const struct intel_crtc_state *crtc_state) 1563 { 1564 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1565 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1566 enum phy phy = intel_encoder_to_phy(encoder); 1567 1568 if (drm_WARN_ON(&i915->drm, !pll)) 1569 return; 1570 1571 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1572 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1573 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1574 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1575 } 1576 1577 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1578 { 1579 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1580 enum phy phy = intel_encoder_to_phy(encoder); 1581 1582 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1583 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1584 } 1585 1586 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1587 { 1588 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1589 enum phy phy = intel_encoder_to_phy(encoder); 1590 1591 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1592 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1593 } 1594 1595 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1596 { 1597 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1598 enum phy phy = intel_encoder_to_phy(encoder); 1599 1600 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1601 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1602 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1603 } 1604 1605 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1606 const struct intel_crtc_state *crtc_state) 1607 { 1608 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1609 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1610 enum phy phy = intel_encoder_to_phy(encoder); 1611 1612 if (drm_WARN_ON(&i915->drm, !pll)) 1613 return; 1614 1615 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1616 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1617 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1618 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1619 } 1620 1621 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1622 { 1623 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1624 enum phy phy = intel_encoder_to_phy(encoder); 1625 1626 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1627 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1628 } 1629 1630 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1631 { 1632 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1633 enum phy phy = intel_encoder_to_phy(encoder); 1634 1635 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1636 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1637 } 1638 1639 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1640 { 1641 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1642 enum phy phy = intel_encoder_to_phy(encoder); 1643 1644 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1645 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1646 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1647 } 1648 1649 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1650 const struct intel_crtc_state *crtc_state) 1651 { 1652 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1653 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1654 enum phy phy = intel_encoder_to_phy(encoder); 1655 1656 if (drm_WARN_ON(&i915->drm, !pll)) 1657 return; 1658 1659 /* 1660 * If we fail this, something went very wrong: first 2 PLLs should be 1661 * used by first 2 phys and last 2 PLLs by last phys 1662 */ 1663 if (drm_WARN_ON(&i915->drm, 1664 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1665 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1666 return; 1667 1668 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1669 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1670 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1671 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1672 } 1673 1674 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1675 { 1676 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1677 enum phy phy = intel_encoder_to_phy(encoder); 1678 1679 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1680 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1681 } 1682 1683 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1684 { 1685 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1686 enum phy phy = intel_encoder_to_phy(encoder); 1687 1688 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1689 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1690 } 1691 1692 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 enum phy phy = intel_encoder_to_phy(encoder); 1696 enum intel_dpll_id id; 1697 u32 val; 1698 1699 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1700 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1701 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1702 id = val; 1703 1704 /* 1705 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1706 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1707 * bit for phy C and D. 1708 */ 1709 if (phy >= PHY_C) 1710 id += DPLL_ID_DG1_DPLL2; 1711 1712 return intel_get_shared_dpll_by_id(i915, id); 1713 } 1714 1715 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1716 const struct intel_crtc_state *crtc_state) 1717 { 1718 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1719 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1720 enum phy phy = intel_encoder_to_phy(encoder); 1721 1722 if (drm_WARN_ON(&i915->drm, !pll)) 1723 return; 1724 1725 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1726 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1727 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1728 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1729 } 1730 1731 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1732 { 1733 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1734 enum phy phy = intel_encoder_to_phy(encoder); 1735 1736 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1737 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1738 } 1739 1740 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1741 { 1742 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1743 enum phy phy = intel_encoder_to_phy(encoder); 1744 1745 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1746 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1747 } 1748 1749 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1750 { 1751 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1752 enum phy phy = intel_encoder_to_phy(encoder); 1753 1754 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1755 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1756 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1757 } 1758 1759 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1760 const struct intel_crtc_state *crtc_state) 1761 { 1762 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1763 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1764 enum port port = encoder->port; 1765 1766 if (drm_WARN_ON(&i915->drm, !pll)) 1767 return; 1768 1769 /* 1770 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1771 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1772 */ 1773 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1774 1775 icl_ddi_combo_enable_clock(encoder, crtc_state); 1776 } 1777 1778 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1779 { 1780 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1781 enum port port = encoder->port; 1782 1783 icl_ddi_combo_disable_clock(encoder); 1784 1785 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1786 } 1787 1788 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1789 { 1790 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1791 enum port port = encoder->port; 1792 u32 tmp; 1793 1794 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1795 1796 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1797 return false; 1798 1799 return icl_ddi_combo_is_clock_enabled(encoder); 1800 } 1801 1802 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1803 const struct intel_crtc_state *crtc_state) 1804 { 1805 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1806 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1807 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1808 enum port port = encoder->port; 1809 1810 if (drm_WARN_ON(&i915->drm, !pll)) 1811 return; 1812 1813 intel_de_write(i915, DDI_CLK_SEL(port), 1814 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1815 1816 mutex_lock(&i915->display.dpll.lock); 1817 1818 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1819 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1820 1821 mutex_unlock(&i915->display.dpll.lock); 1822 } 1823 1824 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1825 { 1826 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1827 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1828 enum port port = encoder->port; 1829 1830 mutex_lock(&i915->display.dpll.lock); 1831 1832 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1833 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1834 1835 mutex_unlock(&i915->display.dpll.lock); 1836 1837 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1838 } 1839 1840 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1841 { 1842 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1843 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1844 enum port port = encoder->port; 1845 u32 tmp; 1846 1847 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1848 1849 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1850 return false; 1851 1852 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1853 1854 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1855 } 1856 1857 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1858 { 1859 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1860 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1861 enum port port = encoder->port; 1862 enum intel_dpll_id id; 1863 u32 tmp; 1864 1865 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1866 1867 switch (tmp & DDI_CLK_SEL_MASK) { 1868 case DDI_CLK_SEL_TBT_162: 1869 case DDI_CLK_SEL_TBT_270: 1870 case DDI_CLK_SEL_TBT_540: 1871 case DDI_CLK_SEL_TBT_810: 1872 id = DPLL_ID_ICL_TBTPLL; 1873 break; 1874 case DDI_CLK_SEL_MG: 1875 id = icl_tc_port_to_pll_id(tc_port); 1876 break; 1877 default: 1878 MISSING_CASE(tmp); 1879 fallthrough; 1880 case DDI_CLK_SEL_NONE: 1881 return NULL; 1882 } 1883 1884 return intel_get_shared_dpll_by_id(i915, id); 1885 } 1886 1887 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1888 { 1889 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1890 enum intel_dpll_id id; 1891 1892 switch (encoder->port) { 1893 case PORT_A: 1894 id = DPLL_ID_SKL_DPLL0; 1895 break; 1896 case PORT_B: 1897 id = DPLL_ID_SKL_DPLL1; 1898 break; 1899 case PORT_C: 1900 id = DPLL_ID_SKL_DPLL2; 1901 break; 1902 default: 1903 MISSING_CASE(encoder->port); 1904 return NULL; 1905 } 1906 1907 return intel_get_shared_dpll_by_id(i915, id); 1908 } 1909 1910 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1911 const struct intel_crtc_state *crtc_state) 1912 { 1913 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1914 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1915 enum port port = encoder->port; 1916 1917 if (drm_WARN_ON(&i915->drm, !pll)) 1918 return; 1919 1920 mutex_lock(&i915->display.dpll.lock); 1921 1922 intel_de_rmw(i915, DPLL_CTRL2, 1923 DPLL_CTRL2_DDI_CLK_OFF(port) | 1924 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1925 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1926 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1927 1928 mutex_unlock(&i915->display.dpll.lock); 1929 } 1930 1931 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1932 { 1933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1934 enum port port = encoder->port; 1935 1936 mutex_lock(&i915->display.dpll.lock); 1937 1938 intel_de_rmw(i915, DPLL_CTRL2, 1939 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1940 1941 mutex_unlock(&i915->display.dpll.lock); 1942 } 1943 1944 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1945 { 1946 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1947 enum port port = encoder->port; 1948 1949 /* 1950 * FIXME Not sure if the override affects both 1951 * the PLL selection and the CLK_OFF bit. 1952 */ 1953 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1954 } 1955 1956 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1957 { 1958 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1959 enum port port = encoder->port; 1960 enum intel_dpll_id id; 1961 u32 tmp; 1962 1963 tmp = intel_de_read(i915, DPLL_CTRL2); 1964 1965 /* 1966 * FIXME Not sure if the override affects both 1967 * the PLL selection and the CLK_OFF bit. 1968 */ 1969 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1970 return NULL; 1971 1972 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1973 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1974 1975 return intel_get_shared_dpll_by_id(i915, id); 1976 } 1977 1978 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1979 const struct intel_crtc_state *crtc_state) 1980 { 1981 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1982 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1983 enum port port = encoder->port; 1984 1985 if (drm_WARN_ON(&i915->drm, !pll)) 1986 return; 1987 1988 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1989 } 1990 1991 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1992 { 1993 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1994 enum port port = encoder->port; 1995 1996 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1997 } 1998 1999 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2000 { 2001 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2002 enum port port = encoder->port; 2003 2004 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2005 } 2006 2007 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2008 { 2009 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2010 enum port port = encoder->port; 2011 enum intel_dpll_id id; 2012 u32 tmp; 2013 2014 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2015 2016 switch (tmp & PORT_CLK_SEL_MASK) { 2017 case PORT_CLK_SEL_WRPLL1: 2018 id = DPLL_ID_WRPLL1; 2019 break; 2020 case PORT_CLK_SEL_WRPLL2: 2021 id = DPLL_ID_WRPLL2; 2022 break; 2023 case PORT_CLK_SEL_SPLL: 2024 id = DPLL_ID_SPLL; 2025 break; 2026 case PORT_CLK_SEL_LCPLL_810: 2027 id = DPLL_ID_LCPLL_810; 2028 break; 2029 case PORT_CLK_SEL_LCPLL_1350: 2030 id = DPLL_ID_LCPLL_1350; 2031 break; 2032 case PORT_CLK_SEL_LCPLL_2700: 2033 id = DPLL_ID_LCPLL_2700; 2034 break; 2035 default: 2036 MISSING_CASE(tmp); 2037 fallthrough; 2038 case PORT_CLK_SEL_NONE: 2039 return NULL; 2040 } 2041 2042 return intel_get_shared_dpll_by_id(i915, id); 2043 } 2044 2045 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2046 const struct intel_crtc_state *crtc_state) 2047 { 2048 if (encoder->enable_clock) 2049 encoder->enable_clock(encoder, crtc_state); 2050 } 2051 2052 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2053 { 2054 if (encoder->disable_clock) 2055 encoder->disable_clock(encoder); 2056 } 2057 2058 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2059 { 2060 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2061 u32 port_mask; 2062 bool ddi_clk_needed; 2063 2064 /* 2065 * In case of DP MST, we sanitize the primary encoder only, not the 2066 * virtual ones. 2067 */ 2068 if (encoder->type == INTEL_OUTPUT_DP_MST) 2069 return; 2070 2071 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2072 u8 pipe_mask; 2073 bool is_mst; 2074 2075 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2076 /* 2077 * In the unlikely case that BIOS enables DP in MST mode, just 2078 * warn since our MST HW readout is incomplete. 2079 */ 2080 if (drm_WARN_ON(&i915->drm, is_mst)) 2081 return; 2082 } 2083 2084 port_mask = BIT(encoder->port); 2085 ddi_clk_needed = encoder->base.crtc; 2086 2087 if (encoder->type == INTEL_OUTPUT_DSI) { 2088 struct intel_encoder *other_encoder; 2089 2090 port_mask = intel_dsi_encoder_ports(encoder); 2091 /* 2092 * Sanity check that we haven't incorrectly registered another 2093 * encoder using any of the ports of this DSI encoder. 2094 */ 2095 for_each_intel_encoder(&i915->drm, other_encoder) { 2096 if (other_encoder == encoder) 2097 continue; 2098 2099 if (drm_WARN_ON(&i915->drm, 2100 port_mask & BIT(other_encoder->port))) 2101 return; 2102 } 2103 /* 2104 * For DSI we keep the ddi clocks gated 2105 * except during enable/disable sequence. 2106 */ 2107 ddi_clk_needed = false; 2108 } 2109 2110 if (ddi_clk_needed || !encoder->is_clock_enabled || 2111 !encoder->is_clock_enabled(encoder)) 2112 return; 2113 2114 drm_dbg_kms(&i915->drm, 2115 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2116 encoder->base.base.id, encoder->base.name); 2117 2118 encoder->disable_clock(encoder); 2119 } 2120 2121 static void 2122 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2123 const struct intel_crtc_state *crtc_state) 2124 { 2125 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2126 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2127 u32 ln0, ln1, pin_assignment; 2128 u8 width; 2129 2130 if (DISPLAY_VER(dev_priv) >= 14) 2131 return; 2132 2133 if (!intel_encoder_is_tc(&dig_port->base) || 2134 intel_tc_port_in_tbt_alt_mode(dig_port)) 2135 return; 2136 2137 if (DISPLAY_VER(dev_priv) >= 12) { 2138 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2139 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2140 } else { 2141 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2142 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2143 } 2144 2145 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2146 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2147 2148 /* DPPATC */ 2149 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2150 width = crtc_state->lane_count; 2151 2152 switch (pin_assignment) { 2153 case 0x0: 2154 drm_WARN_ON(&dev_priv->drm, 2155 !intel_tc_port_in_legacy_mode(dig_port)); 2156 if (width == 1) { 2157 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2158 } else { 2159 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2160 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2161 } 2162 break; 2163 case 0x1: 2164 if (width == 4) { 2165 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2166 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2167 } 2168 break; 2169 case 0x2: 2170 if (width == 2) { 2171 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2172 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2173 } 2174 break; 2175 case 0x3: 2176 case 0x5: 2177 if (width == 1) { 2178 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2179 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2180 } else { 2181 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2182 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2183 } 2184 break; 2185 case 0x4: 2186 case 0x6: 2187 if (width == 1) { 2188 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2189 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2190 } else { 2191 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2192 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2193 } 2194 break; 2195 default: 2196 MISSING_CASE(pin_assignment); 2197 } 2198 2199 if (DISPLAY_VER(dev_priv) >= 12) { 2200 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2201 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2202 } else { 2203 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2204 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2205 } 2206 } 2207 2208 static enum transcoder 2209 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2210 { 2211 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2212 return crtc_state->mst_master_transcoder; 2213 else 2214 return crtc_state->cpu_transcoder; 2215 } 2216 2217 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2218 const struct intel_crtc_state *crtc_state) 2219 { 2220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2221 2222 if (DISPLAY_VER(dev_priv) >= 12) 2223 return TGL_DP_TP_CTL(dev_priv, 2224 tgl_dp_tp_transcoder(crtc_state)); 2225 else 2226 return DP_TP_CTL(encoder->port); 2227 } 2228 2229 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2230 const struct intel_crtc_state *crtc_state) 2231 { 2232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2233 2234 if (DISPLAY_VER(dev_priv) >= 12) 2235 return TGL_DP_TP_STATUS(dev_priv, 2236 tgl_dp_tp_transcoder(crtc_state)); 2237 else 2238 return DP_TP_STATUS(encoder->port); 2239 } 2240 2241 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2242 const struct intel_crtc_state *crtc_state) 2243 { 2244 struct intel_display *display = to_intel_display(encoder); 2245 2246 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2247 DP_TP_STATUS_ACT_SENT); 2248 } 2249 2250 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2251 const struct intel_crtc_state *crtc_state) 2252 { 2253 struct intel_display *display = to_intel_display(encoder); 2254 2255 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2256 DP_TP_STATUS_ACT_SENT, 1)) 2257 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2258 } 2259 2260 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2261 const struct intel_crtc_state *crtc_state, 2262 bool enable) 2263 { 2264 struct intel_display *display = to_intel_display(intel_dp); 2265 2266 if (!crtc_state->vrr.enable) 2267 return; 2268 2269 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2270 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2271 drm_dbg_kms(display->drm, 2272 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2273 str_enable_disable(enable)); 2274 } 2275 2276 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2277 const struct intel_crtc_state *crtc_state, 2278 bool enable) 2279 { 2280 struct intel_display *display = to_intel_display(intel_dp); 2281 2282 if (!crtc_state->fec_enable) 2283 return; 2284 2285 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2286 enable ? DP_FEC_READY : 0) <= 0) 2287 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2288 str_enabled_disabled(enable)); 2289 2290 if (enable && 2291 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2292 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2293 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2294 } 2295 2296 static int read_fec_detected_status(struct drm_dp_aux *aux) 2297 { 2298 int ret; 2299 u8 status; 2300 2301 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2302 if (ret < 0) 2303 return ret; 2304 2305 return status; 2306 } 2307 2308 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2309 { 2310 struct intel_display *display = to_intel_display(aux->drm_dev); 2311 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2312 int status; 2313 int err; 2314 2315 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2316 status & mask || status < 0, 2317 10000, 200000); 2318 2319 if (err || status < 0) { 2320 drm_dbg_kms(display->drm, 2321 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2322 str_enabled_disabled(enabled), err, status); 2323 return err ? err : status; 2324 } 2325 2326 return 0; 2327 } 2328 2329 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2330 const struct intel_crtc_state *crtc_state, 2331 bool enabled) 2332 { 2333 struct intel_display *display = to_intel_display(encoder); 2334 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2335 int ret; 2336 2337 if (!crtc_state->fec_enable) 2338 return 0; 2339 2340 if (enabled) 2341 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2342 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2343 else 2344 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2345 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2346 2347 if (ret) { 2348 drm_err(display->drm, 2349 "Timeout waiting for FEC live state to get %s\n", 2350 str_enabled_disabled(enabled)); 2351 return ret; 2352 } 2353 /* 2354 * At least the Synoptics MST hub doesn't set the detected flag for 2355 * FEC decoding disabling so skip waiting for that. 2356 */ 2357 if (enabled) { 2358 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2359 if (ret) 2360 return ret; 2361 } 2362 2363 return 0; 2364 } 2365 2366 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2367 const struct intel_crtc_state *crtc_state) 2368 { 2369 struct intel_display *display = to_intel_display(encoder); 2370 int i; 2371 int ret; 2372 2373 if (!crtc_state->fec_enable) 2374 return; 2375 2376 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2377 0, DP_TP_CTL_FEC_ENABLE); 2378 2379 if (DISPLAY_VER(display) < 30) 2380 return; 2381 2382 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2383 if (!ret) 2384 return; 2385 2386 for (i = 0; i < 3; i++) { 2387 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2388 2389 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2390 DP_TP_CTL_FEC_ENABLE, 0); 2391 2392 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2393 if (ret) 2394 continue; 2395 2396 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2397 0, DP_TP_CTL_FEC_ENABLE); 2398 2399 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2400 if (!ret) 2401 return; 2402 } 2403 2404 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2405 } 2406 2407 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2408 const struct intel_crtc_state *crtc_state) 2409 { 2410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2411 2412 if (!crtc_state->fec_enable) 2413 return; 2414 2415 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2416 DP_TP_CTL_FEC_ENABLE, 0); 2417 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2418 } 2419 2420 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2421 const struct intel_crtc_state *crtc_state) 2422 { 2423 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2424 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2425 2426 if (intel_encoder_is_combo(encoder)) { 2427 enum phy phy = intel_encoder_to_phy(encoder); 2428 2429 intel_combo_phy_power_up_lanes(i915, phy, false, 2430 crtc_state->lane_count, 2431 dig_port->lane_reversal); 2432 } 2433 } 2434 2435 /* 2436 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2437 * platforms. 2438 */ 2439 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2440 { 2441 if (DISPLAY_VER(i915) > 20) 2442 return ~0; 2443 else if (IS_ALDERLAKE_P(i915)) 2444 return BIT(PIPE_A) | BIT(PIPE_B); 2445 else 2446 return BIT(PIPE_A); 2447 } 2448 2449 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2450 struct intel_crtc_state *pipe_config) 2451 { 2452 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2453 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2454 enum pipe pipe = crtc->pipe; 2455 u32 dss1; 2456 2457 if (!HAS_MSO(i915)) 2458 return; 2459 2460 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2461 2462 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2463 if (!pipe_config->splitter.enable) 2464 return; 2465 2466 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2467 pipe_config->splitter.enable = false; 2468 return; 2469 } 2470 2471 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2472 default: 2473 drm_WARN(&i915->drm, true, 2474 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2475 fallthrough; 2476 case SPLITTER_CONFIGURATION_2_SEGMENT: 2477 pipe_config->splitter.link_count = 2; 2478 break; 2479 case SPLITTER_CONFIGURATION_4_SEGMENT: 2480 pipe_config->splitter.link_count = 4; 2481 break; 2482 } 2483 2484 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2485 } 2486 2487 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2488 { 2489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2490 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2491 enum pipe pipe = crtc->pipe; 2492 u32 dss1 = 0; 2493 2494 if (!HAS_MSO(i915)) 2495 return; 2496 2497 if (crtc_state->splitter.enable) { 2498 dss1 |= SPLITTER_ENABLE; 2499 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2500 if (crtc_state->splitter.link_count == 2) 2501 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2502 else 2503 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2504 } 2505 2506 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2507 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2508 OVERLAP_PIXELS_MASK, dss1); 2509 } 2510 2511 static u8 mtl_get_port_width(u8 lane_count) 2512 { 2513 switch (lane_count) { 2514 case 1: 2515 return 0; 2516 case 2: 2517 return 1; 2518 case 3: 2519 return 4; 2520 case 4: 2521 return 3; 2522 default: 2523 MISSING_CASE(lane_count); 2524 return 4; 2525 } 2526 } 2527 2528 static void 2529 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2530 { 2531 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2532 enum port port = encoder->port; 2533 i915_reg_t reg; 2534 u32 set_bits, wait_bits; 2535 2536 if (DISPLAY_VER(dev_priv) >= 20) { 2537 reg = DDI_BUF_CTL(port); 2538 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2539 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2540 } else { 2541 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2542 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2543 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2544 } 2545 2546 intel_de_rmw(dev_priv, reg, 0, set_bits); 2547 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2548 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2549 port_name(port)); 2550 } 2551 } 2552 2553 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2554 const struct intel_crtc_state *crtc_state) 2555 { 2556 struct intel_display *display = to_intel_display(encoder); 2557 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2558 enum port port = encoder->port; 2559 u32 val = 0; 2560 2561 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2562 2563 if (intel_dp_is_uhbr(crtc_state)) 2564 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2565 else 2566 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2567 2568 if (dig_port->lane_reversal) 2569 val |= XELPDP_PORT_REVERSAL; 2570 2571 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2572 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2573 val); 2574 } 2575 2576 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2577 { 2578 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2579 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2580 u32 val; 2581 2582 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2583 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2584 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2585 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2586 } 2587 2588 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2589 struct intel_encoder *encoder, 2590 const struct intel_crtc_state *crtc_state, 2591 const struct drm_connector_state *conn_state) 2592 { 2593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2594 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2595 bool transparent_mode; 2596 int ret; 2597 2598 intel_dp_set_link_params(intel_dp, 2599 crtc_state->port_clock, 2600 crtc_state->lane_count); 2601 2602 /* 2603 * We only configure what the register value will be here. Actual 2604 * enabling happens during link training farther down. 2605 */ 2606 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2607 2608 /* 2609 * 1. Enable Power Wells 2610 * 2611 * This was handled at the beginning of intel_atomic_commit_tail(), 2612 * before we called down into this function. 2613 */ 2614 2615 /* 2. PMdemand was already set */ 2616 2617 /* 3. Select Thunderbolt */ 2618 mtl_port_buf_ctl_io_selection(encoder); 2619 2620 /* 4. Enable Panel Power if PPS is required */ 2621 intel_pps_on(intel_dp); 2622 2623 /* 5. Enable the port PLL */ 2624 intel_ddi_enable_clock(encoder, crtc_state); 2625 2626 /* 2627 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2628 * Transcoder. 2629 */ 2630 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2631 2632 /* 2633 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2634 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2635 * Transport Select 2636 */ 2637 intel_ddi_config_transcoder_func(encoder, crtc_state); 2638 2639 /* 2640 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2641 */ 2642 intel_ddi_mso_configure(crtc_state); 2643 2644 if (!is_mst) 2645 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2646 2647 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2648 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2649 2650 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2651 if (!is_mst) 2652 intel_dp_sink_enable_decompression(state, 2653 to_intel_connector(conn_state->connector), 2654 crtc_state); 2655 2656 /* 2657 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2658 * in the FEC_CONFIGURATION register to 1 before initiating link 2659 * training 2660 */ 2661 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2662 2663 intel_dp_check_frl_training(intel_dp); 2664 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2665 2666 /* 2667 * 6. The rest of the below are substeps under the bspec's "Enable and 2668 * Train Display Port" step. Note that steps that are specific to 2669 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2670 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2671 * us when active_mst_links==0, so any steps designated for "single 2672 * stream or multi-stream master transcoder" can just be performed 2673 * unconditionally here. 2674 * 2675 * mtl_ddi_prepare_link_retrain() that is called by 2676 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2677 * 6.i and 6.j 2678 * 2679 * 6.k Follow DisplayPort specification training sequence (see notes for 2680 * failure handling) 2681 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2682 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2683 * (timeout after 800 us) 2684 */ 2685 intel_dp_start_link_train(state, intel_dp, crtc_state); 2686 2687 /* 6.n Set DP_TP_CTL link training to Normal */ 2688 if (!is_trans_port_sync_mode(crtc_state)) 2689 intel_dp_stop_link_train(intel_dp, crtc_state); 2690 2691 /* 6.o Configure and enable FEC if needed */ 2692 intel_ddi_enable_fec(encoder, crtc_state); 2693 2694 /* 7.a 128b/132b SST. */ 2695 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2696 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2697 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2698 if (ret < 0) 2699 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2700 } 2701 2702 if (!is_mst) 2703 intel_dsc_dp_pps_write(encoder, crtc_state); 2704 } 2705 2706 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2707 struct intel_encoder *encoder, 2708 const struct intel_crtc_state *crtc_state, 2709 const struct drm_connector_state *conn_state) 2710 { 2711 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2713 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2714 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2715 int ret; 2716 2717 intel_dp_set_link_params(intel_dp, 2718 crtc_state->port_clock, 2719 crtc_state->lane_count); 2720 2721 /* 2722 * We only configure what the register value will be here. Actual 2723 * enabling happens during link training farther down. 2724 */ 2725 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2726 2727 /* 2728 * 1. Enable Power Wells 2729 * 2730 * This was handled at the beginning of intel_atomic_commit_tail(), 2731 * before we called down into this function. 2732 */ 2733 2734 /* 2. Enable Panel Power if PPS is required */ 2735 intel_pps_on(intel_dp); 2736 2737 /* 2738 * 3. For non-TBT Type-C ports, set FIA lane count 2739 * (DFLEXDPSP.DPX4TXLATC) 2740 * 2741 * This was done before tgl_ddi_pre_enable_dp by 2742 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2743 */ 2744 2745 /* 2746 * 4. Enable the port PLL. 2747 * 2748 * The PLL enabling itself was already done before this function by 2749 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2750 * configure the PLL to port mapping here. 2751 */ 2752 intel_ddi_enable_clock(encoder, crtc_state); 2753 2754 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2755 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2756 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2757 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2758 dig_port->ddi_io_power_domain); 2759 } 2760 2761 /* 6. Program DP_MODE */ 2762 icl_program_mg_dp_mode(dig_port, crtc_state); 2763 2764 /* 2765 * 7. The rest of the below are substeps under the bspec's "Enable and 2766 * Train Display Port" step. Note that steps that are specific to 2767 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2768 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2769 * us when active_mst_links==0, so any steps designated for "single 2770 * stream or multi-stream master transcoder" can just be performed 2771 * unconditionally here. 2772 */ 2773 2774 /* 2775 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2776 * Transcoder. 2777 */ 2778 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2779 2780 /* 2781 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2782 * Transport Select 2783 */ 2784 intel_ddi_config_transcoder_func(encoder, crtc_state); 2785 2786 /* 2787 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2788 * selected 2789 * 2790 * This will be handled by the intel_dp_start_link_train() farther 2791 * down this function. 2792 */ 2793 2794 /* 7.e Configure voltage swing and related IO settings */ 2795 encoder->set_signal_levels(encoder, crtc_state); 2796 2797 /* 2798 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2799 * the used lanes of the DDI. 2800 */ 2801 intel_ddi_power_up_lanes(encoder, crtc_state); 2802 2803 /* 2804 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2805 */ 2806 intel_ddi_mso_configure(crtc_state); 2807 2808 if (!is_mst) 2809 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2810 2811 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2812 if (!is_mst) 2813 intel_dp_sink_enable_decompression(state, 2814 to_intel_connector(conn_state->connector), 2815 crtc_state); 2816 /* 2817 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2818 * in the FEC_CONFIGURATION register to 1 before initiating link 2819 * training 2820 */ 2821 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2822 2823 intel_dp_check_frl_training(intel_dp); 2824 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2825 2826 /* 2827 * 7.i Follow DisplayPort specification training sequence (see notes for 2828 * failure handling) 2829 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2830 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2831 * (timeout after 800 us) 2832 */ 2833 intel_dp_start_link_train(state, intel_dp, crtc_state); 2834 2835 /* 7.k Set DP_TP_CTL link training to Normal */ 2836 if (!is_trans_port_sync_mode(crtc_state)) 2837 intel_dp_stop_link_train(intel_dp, crtc_state); 2838 2839 /* 7.l Configure and enable FEC if needed */ 2840 intel_ddi_enable_fec(encoder, crtc_state); 2841 2842 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2843 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2844 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2845 if (ret < 0) 2846 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2847 } 2848 2849 if (!is_mst) 2850 intel_dsc_dp_pps_write(encoder, crtc_state); 2851 } 2852 2853 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2854 struct intel_encoder *encoder, 2855 const struct intel_crtc_state *crtc_state, 2856 const struct drm_connector_state *conn_state) 2857 { 2858 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2859 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2860 enum port port = encoder->port; 2861 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2862 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2863 2864 if (DISPLAY_VER(dev_priv) < 11) 2865 drm_WARN_ON(&dev_priv->drm, 2866 is_mst && (port == PORT_A || port == PORT_E)); 2867 else 2868 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2869 2870 intel_dp_set_link_params(intel_dp, 2871 crtc_state->port_clock, 2872 crtc_state->lane_count); 2873 2874 /* 2875 * We only configure what the register value will be here. Actual 2876 * enabling happens during link training farther down. 2877 */ 2878 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2879 2880 intel_pps_on(intel_dp); 2881 2882 intel_ddi_enable_clock(encoder, crtc_state); 2883 2884 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2885 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2886 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2887 dig_port->ddi_io_power_domain); 2888 } 2889 2890 icl_program_mg_dp_mode(dig_port, crtc_state); 2891 2892 if (has_buf_trans_select(dev_priv)) 2893 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2894 2895 encoder->set_signal_levels(encoder, crtc_state); 2896 2897 intel_ddi_power_up_lanes(encoder, crtc_state); 2898 2899 if (!is_mst) 2900 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2901 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2902 if (!is_mst) 2903 intel_dp_sink_enable_decompression(state, 2904 to_intel_connector(conn_state->connector), 2905 crtc_state); 2906 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2907 intel_dp_start_link_train(state, intel_dp, crtc_state); 2908 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2909 !is_trans_port_sync_mode(crtc_state)) 2910 intel_dp_stop_link_train(intel_dp, crtc_state); 2911 2912 intel_ddi_enable_fec(encoder, crtc_state); 2913 2914 if (!is_mst) { 2915 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2916 intel_dsc_dp_pps_write(encoder, crtc_state); 2917 } 2918 } 2919 2920 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2921 struct intel_encoder *encoder, 2922 const struct intel_crtc_state *crtc_state, 2923 const struct drm_connector_state *conn_state) 2924 { 2925 struct intel_display *display = to_intel_display(encoder); 2926 2927 if (HAS_DP20(display)) 2928 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2929 crtc_state); 2930 2931 /* Panel replay has to be enabled in sink dpcd before link training. */ 2932 if (crtc_state->has_panel_replay) 2933 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2934 2935 if (DISPLAY_VER(display) >= 14) 2936 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2937 else if (DISPLAY_VER(display) >= 12) 2938 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2939 else 2940 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2941 2942 /* MST will call a setting of MSA after an allocating of Virtual Channel 2943 * from MST encoder pre_enable callback. 2944 */ 2945 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2946 intel_ddi_set_dp_msa(crtc_state, conn_state); 2947 } 2948 2949 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2950 struct intel_encoder *encoder, 2951 const struct intel_crtc_state *crtc_state, 2952 const struct drm_connector_state *conn_state) 2953 { 2954 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2955 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2957 2958 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2959 intel_ddi_enable_clock(encoder, crtc_state); 2960 2961 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2962 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2963 dig_port->ddi_io_power_domain); 2964 2965 icl_program_mg_dp_mode(dig_port, crtc_state); 2966 2967 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2968 2969 dig_port->set_infoframes(encoder, 2970 crtc_state->has_infoframe, 2971 crtc_state, conn_state); 2972 } 2973 2974 /* 2975 * Note: Also called from the ->pre_enable of the first active MST stream 2976 * encoder on its primary encoder. 2977 * 2978 * When called from DP MST code: 2979 * 2980 * - conn_state will be NULL 2981 * 2982 * - encoder will be the primary encoder (i.e. mst->primary) 2983 * 2984 * - the main connector associated with this port won't be active or linked to a 2985 * crtc 2986 * 2987 * - crtc_state will be the state of the first stream to be activated on this 2988 * port, and it may not be the same stream that will be deactivated last, but 2989 * each stream should have a state that is identical when it comes to the DP 2990 * link parameteres 2991 */ 2992 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2993 struct intel_encoder *encoder, 2994 const struct intel_crtc_state *crtc_state, 2995 const struct drm_connector_state *conn_state) 2996 { 2997 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2998 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2999 enum pipe pipe = crtc->pipe; 3000 3001 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3002 3003 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3004 3005 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3006 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3007 conn_state); 3008 } else { 3009 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3010 3011 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3012 conn_state); 3013 3014 /* FIXME precompute everything properly */ 3015 /* FIXME how do we turn infoframes off again? */ 3016 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3017 dig_port->set_infoframes(encoder, 3018 crtc_state->has_infoframe, 3019 crtc_state, conn_state); 3020 } 3021 } 3022 3023 static void 3024 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 3025 { 3026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3027 enum port port = encoder->port; 3028 i915_reg_t reg; 3029 u32 clr_bits, wait_bits; 3030 3031 if (DISPLAY_VER(dev_priv) >= 20) { 3032 reg = DDI_BUF_CTL(port); 3033 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3034 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3035 } else { 3036 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 3037 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3038 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3039 } 3040 3041 intel_de_rmw(dev_priv, reg, clr_bits, 0); 3042 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 3043 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3044 port_name(port)); 3045 } 3046 3047 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 3048 const struct intel_crtc_state *crtc_state) 3049 { 3050 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3051 enum port port = encoder->port; 3052 u32 val; 3053 3054 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 3055 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3056 if (val & DDI_BUF_CTL_ENABLE) { 3057 val &= ~DDI_BUF_CTL_ENABLE; 3058 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3059 3060 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 3061 mtl_wait_ddi_buf_idle(dev_priv, port); 3062 } 3063 3064 /* 3.d Disable D2D Link */ 3065 mtl_ddi_disable_d2d_link(encoder); 3066 3067 /* 3.e Disable DP_TP_CTL */ 3068 if (intel_crtc_has_dp_encoder(crtc_state)) { 3069 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3070 DP_TP_CTL_ENABLE, 0); 3071 } 3072 } 3073 3074 static void disable_ddi_buf(struct intel_encoder *encoder, 3075 const struct intel_crtc_state *crtc_state) 3076 { 3077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3078 enum port port = encoder->port; 3079 bool wait = false; 3080 u32 val; 3081 3082 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3083 if (val & DDI_BUF_CTL_ENABLE) { 3084 val &= ~DDI_BUF_CTL_ENABLE; 3085 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3086 wait = true; 3087 } 3088 3089 if (intel_crtc_has_dp_encoder(crtc_state)) 3090 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3091 DP_TP_CTL_ENABLE, 0); 3092 3093 intel_ddi_disable_fec(encoder, crtc_state); 3094 3095 if (wait) 3096 intel_wait_ddi_buf_idle(dev_priv, port); 3097 } 3098 3099 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3100 const struct intel_crtc_state *crtc_state) 3101 { 3102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3103 3104 if (DISPLAY_VER(dev_priv) >= 14) { 3105 mtl_disable_ddi_buf(encoder, crtc_state); 3106 3107 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3108 intel_ddi_disable_fec(encoder, crtc_state); 3109 } else { 3110 disable_ddi_buf(encoder, crtc_state); 3111 } 3112 3113 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3114 } 3115 3116 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3117 struct intel_encoder *encoder, 3118 const struct intel_crtc_state *old_crtc_state, 3119 const struct drm_connector_state *old_conn_state) 3120 { 3121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3122 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3123 struct intel_dp *intel_dp = &dig_port->dp; 3124 intel_wakeref_t wakeref; 3125 bool is_mst = intel_crtc_has_type(old_crtc_state, 3126 INTEL_OUTPUT_DP_MST); 3127 3128 if (!is_mst) 3129 intel_dp_set_infoframes(encoder, false, 3130 old_crtc_state, old_conn_state); 3131 3132 /* 3133 * Power down sink before disabling the port, otherwise we end 3134 * up getting interrupts from the sink on detecting link loss. 3135 */ 3136 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3137 3138 if (DISPLAY_VER(dev_priv) >= 12) { 3139 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3140 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3141 3142 intel_de_rmw(dev_priv, 3143 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3144 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3145 0); 3146 } 3147 } else { 3148 if (!is_mst) 3149 intel_ddi_disable_transcoder_clock(old_crtc_state); 3150 } 3151 3152 intel_disable_ddi_buf(encoder, old_crtc_state); 3153 3154 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3155 3156 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3157 3158 /* 3159 * From TGL spec: "If single stream or multi-stream master transcoder: 3160 * Configure Transcoder Clock select to direct no clock to the 3161 * transcoder" 3162 */ 3163 if (DISPLAY_VER(dev_priv) >= 12) 3164 intel_ddi_disable_transcoder_clock(old_crtc_state); 3165 3166 intel_pps_vdd_on(intel_dp); 3167 intel_pps_off(intel_dp); 3168 3169 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3170 3171 if (wakeref) 3172 intel_display_power_put(dev_priv, 3173 dig_port->ddi_io_power_domain, 3174 wakeref); 3175 3176 intel_ddi_disable_clock(encoder); 3177 3178 /* De-select Thunderbolt */ 3179 if (DISPLAY_VER(dev_priv) >= 14) 3180 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3181 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3182 } 3183 3184 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3185 struct intel_encoder *encoder, 3186 const struct intel_crtc_state *old_crtc_state, 3187 const struct drm_connector_state *old_conn_state) 3188 { 3189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3190 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3191 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3192 intel_wakeref_t wakeref; 3193 3194 dig_port->set_infoframes(encoder, false, 3195 old_crtc_state, old_conn_state); 3196 3197 if (DISPLAY_VER(dev_priv) < 12) 3198 intel_ddi_disable_transcoder_clock(old_crtc_state); 3199 3200 intel_disable_ddi_buf(encoder, old_crtc_state); 3201 3202 if (DISPLAY_VER(dev_priv) >= 12) 3203 intel_ddi_disable_transcoder_clock(old_crtc_state); 3204 3205 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3206 if (wakeref) 3207 intel_display_power_put(dev_priv, 3208 dig_port->ddi_io_power_domain, 3209 wakeref); 3210 3211 intel_ddi_disable_clock(encoder); 3212 3213 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3214 } 3215 3216 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3217 struct intel_encoder *encoder, 3218 const struct intel_crtc_state *old_crtc_state, 3219 const struct drm_connector_state *old_conn_state) 3220 { 3221 struct intel_display *display = to_intel_display(encoder); 3222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3223 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3224 struct intel_crtc *pipe_crtc; 3225 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3226 int i; 3227 3228 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3229 const struct intel_crtc_state *old_pipe_crtc_state = 3230 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3231 3232 intel_crtc_vblank_off(old_pipe_crtc_state); 3233 } 3234 3235 intel_disable_transcoder(old_crtc_state); 3236 3237 /* 128b/132b SST */ 3238 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3239 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3240 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3241 3242 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3243 3244 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3245 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3246 3247 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3248 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3249 } 3250 3251 intel_ddi_disable_transcoder_func(old_crtc_state); 3252 3253 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3254 const struct intel_crtc_state *old_pipe_crtc_state = 3255 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3256 3257 intel_dsc_disable(old_pipe_crtc_state); 3258 3259 if (DISPLAY_VER(dev_priv) >= 9) 3260 skl_scaler_disable(old_pipe_crtc_state); 3261 else 3262 ilk_pfit_disable(old_pipe_crtc_state); 3263 } 3264 } 3265 3266 /* 3267 * Note: Also called from the ->post_disable of the last active MST stream 3268 * encoder on its primary encoder. See also the comment for 3269 * intel_ddi_pre_enable(). 3270 */ 3271 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3272 struct intel_encoder *encoder, 3273 const struct intel_crtc_state *old_crtc_state, 3274 const struct drm_connector_state *old_conn_state) 3275 { 3276 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3277 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3278 old_conn_state); 3279 3280 /* 3281 * When called from DP MST code: 3282 * - old_conn_state will be NULL 3283 * - encoder will be the main encoder (ie. mst->primary) 3284 * - the main connector associated with this port 3285 * won't be active or linked to a crtc 3286 * - old_crtc_state will be the state of the last stream to 3287 * be deactivated on this port, and it may not be the same 3288 * stream that was activated last, but each stream 3289 * should have a state that is identical when it comes to 3290 * the DP link parameteres 3291 */ 3292 3293 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3294 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3295 old_conn_state); 3296 else 3297 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3298 old_conn_state); 3299 } 3300 3301 /* 3302 * Note: Also called from the ->post_pll_disable of the last active MST stream 3303 * encoder on its primary encoder. See also the comment for 3304 * intel_ddi_pre_enable(). 3305 */ 3306 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3307 struct intel_encoder *encoder, 3308 const struct intel_crtc_state *old_crtc_state, 3309 const struct drm_connector_state *old_conn_state) 3310 { 3311 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3312 3313 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3314 3315 if (intel_encoder_is_tc(encoder)) 3316 intel_tc_port_put_link(dig_port); 3317 } 3318 3319 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3320 struct intel_encoder *encoder, 3321 const struct intel_crtc_state *crtc_state) 3322 { 3323 const struct drm_connector_state *conn_state; 3324 struct drm_connector *conn; 3325 int i; 3326 3327 if (!crtc_state->sync_mode_slaves_mask) 3328 return; 3329 3330 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3331 struct intel_encoder *slave_encoder = 3332 to_intel_encoder(conn_state->best_encoder); 3333 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3334 const struct intel_crtc_state *slave_crtc_state; 3335 3336 if (!slave_crtc) 3337 continue; 3338 3339 slave_crtc_state = 3340 intel_atomic_get_new_crtc_state(state, slave_crtc); 3341 3342 if (slave_crtc_state->master_transcoder != 3343 crtc_state->cpu_transcoder) 3344 continue; 3345 3346 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3347 slave_crtc_state); 3348 } 3349 3350 usleep_range(200, 400); 3351 3352 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3353 crtc_state); 3354 } 3355 3356 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3357 struct intel_encoder *encoder, 3358 const struct intel_crtc_state *crtc_state, 3359 const struct drm_connector_state *conn_state) 3360 { 3361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3362 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3363 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3364 enum port port = encoder->port; 3365 3366 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3367 intel_dp_stop_link_train(intel_dp, crtc_state); 3368 3369 drm_connector_update_privacy_screen(conn_state); 3370 intel_edp_backlight_on(crtc_state, conn_state); 3371 3372 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3373 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3374 3375 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3376 } 3377 3378 static i915_reg_t 3379 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3380 { 3381 static const enum transcoder trans[] = { 3382 [PORT_A] = TRANSCODER_EDP, 3383 [PORT_B] = TRANSCODER_A, 3384 [PORT_C] = TRANSCODER_B, 3385 [PORT_D] = TRANSCODER_C, 3386 [PORT_E] = TRANSCODER_A, 3387 }; 3388 3389 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3390 3391 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3392 port = PORT_A; 3393 3394 return CHICKEN_TRANS(display, trans[port]); 3395 } 3396 3397 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3398 struct intel_encoder *encoder, 3399 const struct intel_crtc_state *crtc_state, 3400 const struct drm_connector_state *conn_state) 3401 { 3402 struct intel_display *display = to_intel_display(encoder); 3403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3404 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3405 struct drm_connector *connector = conn_state->connector; 3406 enum port port = encoder->port; 3407 u32 buf_ctl; 3408 3409 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3410 crtc_state->hdmi_high_tmds_clock_ratio, 3411 crtc_state->hdmi_scrambling)) 3412 drm_dbg_kms(&dev_priv->drm, 3413 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3414 connector->base.id, connector->name); 3415 3416 if (has_buf_trans_select(dev_priv)) 3417 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3418 3419 /* e. Enable D2D Link for C10/C20 Phy */ 3420 if (DISPLAY_VER(dev_priv) >= 14) 3421 mtl_ddi_enable_d2d(encoder); 3422 3423 encoder->set_signal_levels(encoder, crtc_state); 3424 3425 /* Display WA #1143: skl,kbl,cfl */ 3426 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3427 /* 3428 * For some reason these chicken bits have been 3429 * stuffed into a transcoder register, event though 3430 * the bits affect a specific DDI port rather than 3431 * a specific transcoder. 3432 */ 3433 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3434 u32 val; 3435 3436 val = intel_de_read(dev_priv, reg); 3437 3438 if (port == PORT_E) 3439 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3440 DDIE_TRAINING_OVERRIDE_VALUE; 3441 else 3442 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3443 DDI_TRAINING_OVERRIDE_VALUE; 3444 3445 intel_de_write(dev_priv, reg, val); 3446 intel_de_posting_read(dev_priv, reg); 3447 3448 udelay(1); 3449 3450 if (port == PORT_E) 3451 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3452 DDIE_TRAINING_OVERRIDE_VALUE); 3453 else 3454 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3455 DDI_TRAINING_OVERRIDE_VALUE); 3456 3457 intel_de_write(dev_priv, reg, val); 3458 } 3459 3460 intel_ddi_power_up_lanes(encoder, crtc_state); 3461 3462 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3463 * are ignored so nothing special needs to be done besides 3464 * enabling the port. 3465 * 3466 * On ADL_P the PHY link rate and lane count must be programmed but 3467 * these are both 0 for HDMI. 3468 * 3469 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3470 * is filled with lane count, already set in the crtc_state. 3471 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3472 */ 3473 buf_ctl = DDI_BUF_CTL_ENABLE; 3474 3475 if (dig_port->lane_reversal) 3476 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3477 if (dig_port->ddi_a_4_lanes) 3478 buf_ctl |= DDI_A_4_LANES; 3479 3480 if (DISPLAY_VER(dev_priv) >= 14) { 3481 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3482 u32 port_buf = 0; 3483 3484 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3485 3486 if (dig_port->lane_reversal) 3487 port_buf |= XELPDP_PORT_REVERSAL; 3488 3489 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3490 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3491 3492 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3493 3494 if (DISPLAY_VER(dev_priv) >= 20) 3495 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3496 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3497 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3498 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3499 } 3500 3501 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3502 3503 intel_wait_ddi_buf_active(encoder); 3504 } 3505 3506 static void intel_ddi_enable(struct intel_atomic_state *state, 3507 struct intel_encoder *encoder, 3508 const struct intel_crtc_state *crtc_state, 3509 const struct drm_connector_state *conn_state) 3510 { 3511 struct intel_display *display = to_intel_display(encoder); 3512 struct intel_crtc *pipe_crtc; 3513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3514 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3515 int i; 3516 3517 /* 128b/132b SST */ 3518 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3519 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3520 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3521 3522 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3523 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3524 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3525 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3526 } 3527 3528 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3529 3530 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3531 intel_audio_sdp_split_update(crtc_state); 3532 3533 /* 128b/132b SST */ 3534 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3536 3537 intel_ddi_clear_act_sent(encoder, crtc_state); 3538 3539 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3540 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3541 3542 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3543 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3544 } 3545 3546 intel_enable_transcoder(crtc_state); 3547 3548 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3549 3550 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3551 const struct intel_crtc_state *pipe_crtc_state = 3552 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3553 3554 intel_crtc_vblank_on(pipe_crtc_state); 3555 } 3556 3557 if (is_hdmi) 3558 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3559 else 3560 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3561 3562 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3563 3564 } 3565 3566 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3567 struct intel_encoder *encoder, 3568 const struct intel_crtc_state *old_crtc_state, 3569 const struct drm_connector_state *old_conn_state) 3570 { 3571 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3572 struct intel_connector *connector = 3573 to_intel_connector(old_conn_state->connector); 3574 3575 intel_dp->link_trained = false; 3576 3577 intel_psr_disable(intel_dp, old_crtc_state); 3578 intel_edp_backlight_off(old_conn_state); 3579 /* Disable the decompression in DP Sink */ 3580 intel_dp_sink_disable_decompression(state, 3581 connector, old_crtc_state); 3582 /* Disable Ignore_MSA bit in DP Sink */ 3583 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3584 false); 3585 } 3586 3587 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3588 struct intel_encoder *encoder, 3589 const struct intel_crtc_state *old_crtc_state, 3590 const struct drm_connector_state *old_conn_state) 3591 { 3592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3593 struct drm_connector *connector = old_conn_state->connector; 3594 3595 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3596 false, false)) 3597 drm_dbg_kms(&i915->drm, 3598 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3599 connector->base.id, connector->name); 3600 } 3601 3602 static void intel_ddi_disable(struct intel_atomic_state *state, 3603 struct intel_encoder *encoder, 3604 const struct intel_crtc_state *old_crtc_state, 3605 const struct drm_connector_state *old_conn_state) 3606 { 3607 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3608 3609 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3610 3611 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3612 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3613 old_conn_state); 3614 else 3615 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3616 old_conn_state); 3617 } 3618 3619 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3620 struct intel_encoder *encoder, 3621 const struct intel_crtc_state *crtc_state, 3622 const struct drm_connector_state *conn_state) 3623 { 3624 intel_ddi_set_dp_msa(crtc_state, conn_state); 3625 3626 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3627 3628 intel_backlight_update(state, encoder, crtc_state, conn_state); 3629 drm_connector_update_privacy_screen(conn_state); 3630 } 3631 3632 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3633 const struct intel_crtc_state *crtc_state, 3634 const struct drm_connector_state *conn_state) 3635 { 3636 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3637 } 3638 3639 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3640 struct intel_encoder *encoder, 3641 const struct intel_crtc_state *crtc_state, 3642 const struct drm_connector_state *conn_state) 3643 { 3644 3645 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3646 !intel_encoder_is_mst(encoder)) 3647 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3648 conn_state); 3649 3650 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3651 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3652 conn_state); 3653 3654 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3655 } 3656 3657 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3658 struct intel_encoder *encoder, 3659 struct intel_crtc *crtc) 3660 { 3661 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3662 const struct intel_crtc_state *crtc_state = 3663 intel_atomic_get_new_crtc_state(state, crtc); 3664 struct intel_crtc *pipe_crtc; 3665 3666 /* FIXME: Add MTL pll_mgr */ 3667 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3668 return; 3669 3670 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3671 intel_crtc_joined_pipe_mask(crtc_state)) 3672 intel_update_active_dpll(state, pipe_crtc, encoder); 3673 } 3674 3675 /* 3676 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3677 * encoder on its primary encoder. See also the comment for 3678 * intel_ddi_pre_enable(). 3679 */ 3680 static void 3681 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3682 struct intel_encoder *encoder, 3683 const struct intel_crtc_state *crtc_state, 3684 const struct drm_connector_state *conn_state) 3685 { 3686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3687 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3688 bool is_tc_port = intel_encoder_is_tc(encoder); 3689 3690 if (is_tc_port) { 3691 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3692 3693 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3694 intel_ddi_update_active_dpll(state, encoder, crtc); 3695 } 3696 3697 main_link_aux_power_domain_get(dig_port, crtc_state); 3698 3699 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3700 /* 3701 * Program the lane count for static/dynamic connections on 3702 * Type-C ports. Skip this step for TBT. 3703 */ 3704 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3705 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3706 bxt_dpio_phy_set_lane_optim_mask(encoder, 3707 crtc_state->lane_lat_optim_mask); 3708 } 3709 3710 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3711 { 3712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3713 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3714 int ln; 3715 3716 for (ln = 0; ln < 2; ln++) 3717 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3718 } 3719 3720 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3721 const struct intel_crtc_state *crtc_state) 3722 { 3723 struct intel_display *display = to_intel_display(crtc_state); 3724 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3725 struct intel_encoder *encoder = &dig_port->base; 3726 enum port port = encoder->port; 3727 u32 dp_tp_ctl; 3728 3729 /* 3730 * TODO: To train with only a different voltage swing entry is not 3731 * necessary disable and enable port 3732 */ 3733 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3734 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3735 mtl_disable_ddi_buf(encoder, crtc_state); 3736 3737 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3738 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3739 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3740 intel_dp_is_uhbr(crtc_state)) { 3741 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3742 } else { 3743 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3744 if (crtc_state->enhanced_framing) 3745 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3746 } 3747 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3748 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3749 3750 /* 6.f Enable D2D Link */ 3751 mtl_ddi_enable_d2d(encoder); 3752 3753 /* 6.g Configure voltage swing and related IO settings */ 3754 encoder->set_signal_levels(encoder, crtc_state); 3755 3756 /* 6.h Configure PORT_BUF_CTL1 */ 3757 mtl_port_buf_ctl_program(encoder, crtc_state); 3758 3759 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3760 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3761 if (DISPLAY_VER(display) >= 20) 3762 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3763 3764 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 3765 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3766 3767 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3768 intel_wait_ddi_buf_active(encoder); 3769 } 3770 3771 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3772 const struct intel_crtc_state *crtc_state) 3773 { 3774 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3775 struct intel_encoder *encoder = &dig_port->base; 3776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3777 enum port port = encoder->port; 3778 u32 dp_tp_ctl, ddi_buf_ctl; 3779 bool wait = false; 3780 3781 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3782 3783 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3784 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3785 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3786 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3787 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3788 wait = true; 3789 } 3790 3791 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3792 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3793 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3794 3795 if (wait) 3796 intel_wait_ddi_buf_idle(dev_priv, port); 3797 } 3798 3799 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3800 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3801 intel_dp_is_uhbr(crtc_state)) { 3802 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3803 } else { 3804 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3805 if (crtc_state->enhanced_framing) 3806 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3807 } 3808 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3809 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3810 3811 if (IS_ALDERLAKE_P(dev_priv) && 3812 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3813 adlp_tbt_to_dp_alt_switch_wa(encoder); 3814 3815 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3816 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3817 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3818 3819 intel_wait_ddi_buf_active(encoder); 3820 } 3821 3822 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3823 const struct intel_crtc_state *crtc_state, 3824 u8 dp_train_pat) 3825 { 3826 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3827 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3828 u32 temp; 3829 3830 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3831 3832 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3833 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3834 case DP_TRAINING_PATTERN_DISABLE: 3835 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3836 break; 3837 case DP_TRAINING_PATTERN_1: 3838 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3839 break; 3840 case DP_TRAINING_PATTERN_2: 3841 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3842 break; 3843 case DP_TRAINING_PATTERN_3: 3844 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3845 break; 3846 case DP_TRAINING_PATTERN_4: 3847 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3848 break; 3849 } 3850 3851 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3852 } 3853 3854 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3855 const struct intel_crtc_state *crtc_state) 3856 { 3857 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3859 enum port port = encoder->port; 3860 3861 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3862 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3863 3864 /* 3865 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3866 * reason we need to set idle transmission mode is to work around a HW 3867 * issue where we enable the pipe while not in idle link-training mode. 3868 * In this case there is requirement to wait for a minimum number of 3869 * idle patterns to be sent. 3870 */ 3871 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3872 return; 3873 3874 if (intel_de_wait_for_set(dev_priv, 3875 dp_tp_status_reg(encoder, crtc_state), 3876 DP_TP_STATUS_IDLE_DONE, 2)) 3877 drm_err(&dev_priv->drm, 3878 "Timed out waiting for DP idle patterns\n"); 3879 } 3880 3881 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3882 enum transcoder cpu_transcoder) 3883 { 3884 if (cpu_transcoder == TRANSCODER_EDP) 3885 return false; 3886 3887 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3888 return false; 3889 3890 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3891 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3892 } 3893 3894 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3895 { 3896 if (crtc_state->port_clock > 594000) 3897 return 2; 3898 else 3899 return 0; 3900 } 3901 3902 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3903 { 3904 if (crtc_state->port_clock > 594000) 3905 return 3; 3906 else 3907 return 0; 3908 } 3909 3910 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3911 { 3912 if (crtc_state->port_clock > 594000) 3913 return 1; 3914 else 3915 return 0; 3916 } 3917 3918 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3919 { 3920 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3921 3922 if (DISPLAY_VER(dev_priv) >= 14) 3923 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3924 else if (DISPLAY_VER(dev_priv) >= 12) 3925 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3926 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3927 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3928 else if (DISPLAY_VER(dev_priv) >= 11) 3929 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3930 } 3931 3932 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3933 enum transcoder cpu_transcoder) 3934 { 3935 u32 master_select; 3936 3937 if (DISPLAY_VER(dev_priv) >= 11) { 3938 u32 ctl2 = intel_de_read(dev_priv, 3939 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3940 3941 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3942 return INVALID_TRANSCODER; 3943 3944 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3945 } else { 3946 u32 ctl = intel_de_read(dev_priv, 3947 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3948 3949 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3950 return INVALID_TRANSCODER; 3951 3952 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3953 } 3954 3955 if (master_select == 0) 3956 return TRANSCODER_EDP; 3957 else 3958 return master_select - 1; 3959 } 3960 3961 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3962 { 3963 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3964 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3965 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3966 enum transcoder cpu_transcoder; 3967 3968 crtc_state->master_transcoder = 3969 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3970 3971 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3972 enum intel_display_power_domain power_domain; 3973 intel_wakeref_t trans_wakeref; 3974 3975 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3976 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3977 power_domain); 3978 3979 if (!trans_wakeref) 3980 continue; 3981 3982 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3983 crtc_state->cpu_transcoder) 3984 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3985 3986 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3987 } 3988 3989 drm_WARN_ON(&dev_priv->drm, 3990 crtc_state->master_transcoder != INVALID_TRANSCODER && 3991 crtc_state->sync_mode_slaves_mask); 3992 } 3993 3994 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3995 struct intel_crtc_state *crtc_state, 3996 u32 ddi_func_ctl) 3997 { 3998 struct intel_display *display = to_intel_display(encoder); 3999 4000 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 4001 if (DISPLAY_VER(display) >= 14) 4002 crtc_state->lane_count = 4003 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4004 else 4005 crtc_state->lane_count = 4; 4006 } 4007 4008 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4009 struct intel_crtc_state *crtc_state, 4010 u32 ddi_func_ctl) 4011 { 4012 crtc_state->has_hdmi_sink = true; 4013 4014 crtc_state->infoframes.enable |= 4015 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4016 4017 if (crtc_state->infoframes.enable) 4018 crtc_state->has_infoframe = true; 4019 4020 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4021 crtc_state->hdmi_scrambling = true; 4022 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4023 crtc_state->hdmi_high_tmds_clock_ratio = true; 4024 4025 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4026 } 4027 4028 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4029 struct intel_crtc_state *crtc_state, 4030 u32 ddi_func_ctl) 4031 { 4032 struct intel_display *display = to_intel_display(encoder); 4033 4034 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4035 crtc_state->enhanced_framing = 4036 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4037 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4038 } 4039 4040 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4041 struct intel_crtc_state *crtc_state, 4042 u32 ddi_func_ctl) 4043 { 4044 struct intel_display *display = to_intel_display(encoder); 4045 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4046 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4047 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4048 4049 if (encoder->type == INTEL_OUTPUT_EDP) 4050 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4051 else 4052 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4053 crtc_state->lane_count = 4054 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4055 4056 if (DISPLAY_VER(display) >= 12 && 4057 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4058 crtc_state->mst_master_transcoder = 4059 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4060 4061 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4062 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4063 4064 crtc_state->enhanced_framing = 4065 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4066 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4067 4068 if (DISPLAY_VER(display) >= 11) 4069 crtc_state->fec_enable = 4070 intel_de_read(display, 4071 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4072 4073 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 4074 crtc_state->infoframes.enable |= 4075 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4076 else 4077 crtc_state->infoframes.enable |= 4078 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4079 } 4080 4081 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4082 struct intel_crtc_state *crtc_state, 4083 u32 ddi_func_ctl) 4084 { 4085 struct intel_display *display = to_intel_display(encoder); 4086 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4087 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4088 4089 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4090 crtc_state->lane_count = 4091 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4092 4093 if (DISPLAY_VER(display) >= 12) 4094 crtc_state->mst_master_transcoder = 4095 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4096 4097 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4098 4099 if (DISPLAY_VER(display) >= 11) 4100 crtc_state->fec_enable = 4101 intel_de_read(display, 4102 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4103 4104 crtc_state->infoframes.enable |= 4105 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4106 } 4107 4108 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4109 struct intel_crtc_state *pipe_config) 4110 { 4111 struct intel_display *display = to_intel_display(encoder); 4112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4113 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4114 u32 ddi_func_ctl, ddi_mode, flags = 0; 4115 4116 ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 4117 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4118 flags |= DRM_MODE_FLAG_PHSYNC; 4119 else 4120 flags |= DRM_MODE_FLAG_NHSYNC; 4121 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4122 flags |= DRM_MODE_FLAG_PVSYNC; 4123 else 4124 flags |= DRM_MODE_FLAG_NVSYNC; 4125 4126 pipe_config->hw.adjusted_mode.flags |= flags; 4127 4128 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4129 case TRANS_DDI_BPC_6: 4130 pipe_config->pipe_bpp = 18; 4131 break; 4132 case TRANS_DDI_BPC_8: 4133 pipe_config->pipe_bpp = 24; 4134 break; 4135 case TRANS_DDI_BPC_10: 4136 pipe_config->pipe_bpp = 30; 4137 break; 4138 case TRANS_DDI_BPC_12: 4139 pipe_config->pipe_bpp = 36; 4140 break; 4141 default: 4142 break; 4143 } 4144 4145 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4146 4147 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4148 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4150 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4152 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4153 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4154 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4155 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4156 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4157 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4158 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4159 4160 /* 4161 * If this is true, we know we're being called from mst stream 4162 * encoder's ->get_config(). 4163 */ 4164 if (intel_dp->is_mst) 4165 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4166 else 4167 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4168 } 4169 } 4170 4171 /* 4172 * Note: Also called from the ->get_config of the MST stream encoders on their 4173 * primary encoder, via the platform specific hooks here. See also the comment 4174 * for intel_ddi_pre_enable(). 4175 */ 4176 static void intel_ddi_get_config(struct intel_encoder *encoder, 4177 struct intel_crtc_state *pipe_config) 4178 { 4179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4180 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4181 4182 /* XXX: DSI transcoder paranoia */ 4183 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4184 return; 4185 4186 intel_ddi_read_func_ctl(encoder, pipe_config); 4187 4188 intel_ddi_mso_get_config(encoder, pipe_config); 4189 4190 pipe_config->has_audio = 4191 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4192 4193 if (encoder->type == INTEL_OUTPUT_EDP) 4194 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4195 4196 ddi_dotclock_get(pipe_config); 4197 4198 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4199 pipe_config->lane_lat_optim_mask = 4200 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4201 4202 intel_ddi_compute_min_voltage_level(pipe_config); 4203 4204 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4205 4206 intel_read_infoframe(encoder, pipe_config, 4207 HDMI_INFOFRAME_TYPE_AVI, 4208 &pipe_config->infoframes.avi); 4209 intel_read_infoframe(encoder, pipe_config, 4210 HDMI_INFOFRAME_TYPE_SPD, 4211 &pipe_config->infoframes.spd); 4212 intel_read_infoframe(encoder, pipe_config, 4213 HDMI_INFOFRAME_TYPE_VENDOR, 4214 &pipe_config->infoframes.hdmi); 4215 intel_read_infoframe(encoder, pipe_config, 4216 HDMI_INFOFRAME_TYPE_DRM, 4217 &pipe_config->infoframes.drm); 4218 4219 if (DISPLAY_VER(dev_priv) >= 8) 4220 bdw_get_trans_port_sync_config(pipe_config); 4221 4222 intel_psr_get_config(encoder, pipe_config); 4223 4224 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4225 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4226 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4227 4228 intel_audio_codec_get_config(encoder, pipe_config); 4229 } 4230 4231 void intel_ddi_get_clock(struct intel_encoder *encoder, 4232 struct intel_crtc_state *crtc_state, 4233 struct intel_shared_dpll *pll) 4234 { 4235 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4236 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4237 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4238 bool pll_active; 4239 4240 if (drm_WARN_ON(&i915->drm, !pll)) 4241 return; 4242 4243 port_dpll->pll = pll; 4244 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4245 drm_WARN_ON(&i915->drm, !pll_active); 4246 4247 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4248 4249 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4250 &crtc_state->dpll_hw_state); 4251 } 4252 4253 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4254 struct intel_crtc_state *crtc_state) 4255 { 4256 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4257 4258 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4259 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4260 else 4261 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4262 4263 intel_ddi_get_config(encoder, crtc_state); 4264 } 4265 4266 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4267 struct intel_crtc_state *crtc_state) 4268 { 4269 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4270 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4271 4272 intel_ddi_get_config(encoder, crtc_state); 4273 } 4274 4275 static void adls_ddi_get_config(struct intel_encoder *encoder, 4276 struct intel_crtc_state *crtc_state) 4277 { 4278 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4279 intel_ddi_get_config(encoder, crtc_state); 4280 } 4281 4282 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4283 struct intel_crtc_state *crtc_state) 4284 { 4285 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4286 intel_ddi_get_config(encoder, crtc_state); 4287 } 4288 4289 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4290 struct intel_crtc_state *crtc_state) 4291 { 4292 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4293 intel_ddi_get_config(encoder, crtc_state); 4294 } 4295 4296 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4297 struct intel_crtc_state *crtc_state) 4298 { 4299 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4300 intel_ddi_get_config(encoder, crtc_state); 4301 } 4302 4303 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4304 { 4305 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4306 } 4307 4308 static enum icl_port_dpll_id 4309 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4310 const struct intel_crtc_state *crtc_state) 4311 { 4312 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4313 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4314 4315 if (drm_WARN_ON(&i915->drm, !pll)) 4316 return ICL_PORT_DPLL_DEFAULT; 4317 4318 if (icl_ddi_tc_pll_is_tbt(pll)) 4319 return ICL_PORT_DPLL_DEFAULT; 4320 else 4321 return ICL_PORT_DPLL_MG_PHY; 4322 } 4323 4324 enum icl_port_dpll_id 4325 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4326 const struct intel_crtc_state *crtc_state) 4327 { 4328 if (!encoder->port_pll_type) 4329 return ICL_PORT_DPLL_DEFAULT; 4330 4331 return encoder->port_pll_type(encoder, crtc_state); 4332 } 4333 4334 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4335 struct intel_crtc_state *crtc_state, 4336 struct intel_shared_dpll *pll) 4337 { 4338 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4339 enum icl_port_dpll_id port_dpll_id; 4340 struct icl_port_dpll *port_dpll; 4341 bool pll_active; 4342 4343 if (drm_WARN_ON(&i915->drm, !pll)) 4344 return; 4345 4346 if (icl_ddi_tc_pll_is_tbt(pll)) 4347 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4348 else 4349 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4350 4351 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4352 4353 port_dpll->pll = pll; 4354 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4355 drm_WARN_ON(&i915->drm, !pll_active); 4356 4357 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4358 4359 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4360 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4361 else 4362 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4363 &crtc_state->dpll_hw_state); 4364 } 4365 4366 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4367 struct intel_crtc_state *crtc_state) 4368 { 4369 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4370 intel_ddi_get_config(encoder, crtc_state); 4371 } 4372 4373 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4374 struct intel_crtc_state *crtc_state) 4375 { 4376 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4377 intel_ddi_get_config(encoder, crtc_state); 4378 } 4379 4380 static void skl_ddi_get_config(struct intel_encoder *encoder, 4381 struct intel_crtc_state *crtc_state) 4382 { 4383 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4384 intel_ddi_get_config(encoder, crtc_state); 4385 } 4386 4387 void hsw_ddi_get_config(struct intel_encoder *encoder, 4388 struct intel_crtc_state *crtc_state) 4389 { 4390 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4391 intel_ddi_get_config(encoder, crtc_state); 4392 } 4393 4394 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4395 const struct intel_crtc_state *crtc_state) 4396 { 4397 if (intel_encoder_is_tc(encoder)) 4398 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4399 crtc_state); 4400 4401 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4402 (!crtc_state && intel_encoder_is_dp(encoder))) 4403 intel_dp_sync_state(encoder, crtc_state); 4404 } 4405 4406 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4407 struct intel_crtc_state *crtc_state) 4408 { 4409 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4410 bool fastset = true; 4411 4412 if (intel_encoder_is_tc(encoder)) { 4413 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4414 encoder->base.base.id, encoder->base.name); 4415 crtc_state->uapi.mode_changed = true; 4416 fastset = false; 4417 } 4418 4419 if (intel_crtc_has_dp_encoder(crtc_state) && 4420 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4421 fastset = false; 4422 4423 return fastset; 4424 } 4425 4426 static enum intel_output_type 4427 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4428 struct intel_crtc_state *crtc_state, 4429 struct drm_connector_state *conn_state) 4430 { 4431 switch (conn_state->connector->connector_type) { 4432 case DRM_MODE_CONNECTOR_HDMIA: 4433 return INTEL_OUTPUT_HDMI; 4434 case DRM_MODE_CONNECTOR_eDP: 4435 return INTEL_OUTPUT_EDP; 4436 case DRM_MODE_CONNECTOR_DisplayPort: 4437 return INTEL_OUTPUT_DP; 4438 default: 4439 MISSING_CASE(conn_state->connector->connector_type); 4440 return INTEL_OUTPUT_UNUSED; 4441 } 4442 } 4443 4444 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4445 struct intel_crtc_state *pipe_config, 4446 struct drm_connector_state *conn_state) 4447 { 4448 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4450 enum port port = encoder->port; 4451 int ret; 4452 4453 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4454 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4455 4456 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4457 pipe_config->has_hdmi_sink = 4458 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4459 4460 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4461 } else { 4462 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4463 } 4464 4465 if (ret) 4466 return ret; 4467 4468 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4469 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4470 pipe_config->pch_pfit.force_thru = 4471 pipe_config->pch_pfit.enabled || 4472 pipe_config->crc_enabled; 4473 4474 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4475 pipe_config->lane_lat_optim_mask = 4476 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4477 4478 intel_ddi_compute_min_voltage_level(pipe_config); 4479 4480 return 0; 4481 } 4482 4483 static bool mode_equal(const struct drm_display_mode *mode1, 4484 const struct drm_display_mode *mode2) 4485 { 4486 return drm_mode_match(mode1, mode2, 4487 DRM_MODE_MATCH_TIMINGS | 4488 DRM_MODE_MATCH_FLAGS | 4489 DRM_MODE_MATCH_3D_FLAGS) && 4490 mode1->clock == mode2->clock; /* we want an exact match */ 4491 } 4492 4493 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4494 const struct intel_link_m_n *m_n_2) 4495 { 4496 return m_n_1->tu == m_n_2->tu && 4497 m_n_1->data_m == m_n_2->data_m && 4498 m_n_1->data_n == m_n_2->data_n && 4499 m_n_1->link_m == m_n_2->link_m && 4500 m_n_1->link_n == m_n_2->link_n; 4501 } 4502 4503 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4504 const struct intel_crtc_state *crtc_state2) 4505 { 4506 /* 4507 * FIXME the modeset sequence is currently wrong and 4508 * can't deal with joiner + port sync at the same time. 4509 */ 4510 return crtc_state1->hw.active && crtc_state2->hw.active && 4511 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4512 crtc_state1->output_types == crtc_state2->output_types && 4513 crtc_state1->output_format == crtc_state2->output_format && 4514 crtc_state1->lane_count == crtc_state2->lane_count && 4515 crtc_state1->port_clock == crtc_state2->port_clock && 4516 mode_equal(&crtc_state1->hw.adjusted_mode, 4517 &crtc_state2->hw.adjusted_mode) && 4518 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4519 } 4520 4521 static u8 4522 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4523 int tile_group_id) 4524 { 4525 struct drm_connector *connector; 4526 const struct drm_connector_state *conn_state; 4527 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4528 struct intel_atomic_state *state = 4529 to_intel_atomic_state(ref_crtc_state->uapi.state); 4530 u8 transcoders = 0; 4531 int i; 4532 4533 /* 4534 * We don't enable port sync on BDW due to missing w/as and 4535 * due to not having adjusted the modeset sequence appropriately. 4536 */ 4537 if (DISPLAY_VER(dev_priv) < 9) 4538 return 0; 4539 4540 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4541 return 0; 4542 4543 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4544 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4545 const struct intel_crtc_state *crtc_state; 4546 4547 if (!crtc) 4548 continue; 4549 4550 if (!connector->has_tile || 4551 connector->tile_group->id != 4552 tile_group_id) 4553 continue; 4554 crtc_state = intel_atomic_get_new_crtc_state(state, 4555 crtc); 4556 if (!crtcs_port_sync_compatible(ref_crtc_state, 4557 crtc_state)) 4558 continue; 4559 transcoders |= BIT(crtc_state->cpu_transcoder); 4560 } 4561 4562 return transcoders; 4563 } 4564 4565 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4566 struct intel_crtc_state *crtc_state, 4567 struct drm_connector_state *conn_state) 4568 { 4569 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4570 struct drm_connector *connector = conn_state->connector; 4571 u8 port_sync_transcoders = 0; 4572 4573 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4574 encoder->base.base.id, encoder->base.name, 4575 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4576 4577 if (connector->has_tile) 4578 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4579 connector->tile_group->id); 4580 4581 /* 4582 * EDP Transcoders cannot be ensalved 4583 * make them a master always when present 4584 */ 4585 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4586 crtc_state->master_transcoder = TRANSCODER_EDP; 4587 else 4588 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4589 4590 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4591 crtc_state->master_transcoder = INVALID_TRANSCODER; 4592 crtc_state->sync_mode_slaves_mask = 4593 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4594 } 4595 4596 return 0; 4597 } 4598 4599 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4600 { 4601 struct drm_i915_private *i915 = to_i915(encoder->dev); 4602 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4603 4604 intel_dp_encoder_flush_work(encoder); 4605 if (intel_encoder_is_tc(&dig_port->base)) 4606 intel_tc_port_cleanup(dig_port); 4607 intel_display_power_flush_work(i915); 4608 4609 drm_encoder_cleanup(encoder); 4610 kfree(dig_port->hdcp_port_data.streams); 4611 kfree(dig_port); 4612 } 4613 4614 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4615 { 4616 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4617 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4618 4619 intel_dp->reset_link_params = true; 4620 intel_dp_invalidate_source_oui(intel_dp); 4621 4622 intel_pps_encoder_reset(intel_dp); 4623 4624 if (intel_encoder_is_tc(&dig_port->base)) 4625 intel_tc_port_init_mode(dig_port); 4626 } 4627 4628 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4629 { 4630 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4631 4632 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4633 4634 return 0; 4635 } 4636 4637 static const struct drm_encoder_funcs intel_ddi_funcs = { 4638 .reset = intel_ddi_encoder_reset, 4639 .destroy = intel_ddi_encoder_destroy, 4640 .late_register = intel_ddi_encoder_late_register, 4641 }; 4642 4643 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4644 { 4645 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4646 struct intel_connector *connector; 4647 enum port port = dig_port->base.port; 4648 4649 connector = intel_connector_alloc(); 4650 if (!connector) 4651 return -ENOMEM; 4652 4653 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4654 if (DISPLAY_VER(i915) >= 14) 4655 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4656 else 4657 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4658 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4659 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4660 4661 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4662 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4663 4664 if (!intel_dp_init_connector(dig_port, connector)) { 4665 kfree(connector); 4666 return -EINVAL; 4667 } 4668 4669 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4670 struct drm_device *dev = dig_port->base.base.dev; 4671 struct drm_privacy_screen *privacy_screen; 4672 4673 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4674 if (!IS_ERR(privacy_screen)) { 4675 drm_connector_attach_privacy_screen_provider(&connector->base, 4676 privacy_screen); 4677 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4678 drm_warn(dev, "Error getting privacy-screen\n"); 4679 } 4680 } 4681 4682 return 0; 4683 } 4684 4685 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4686 struct drm_modeset_acquire_ctx *ctx) 4687 { 4688 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4689 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4690 struct intel_connector *connector = hdmi->attached_connector; 4691 struct i2c_adapter *ddc = connector->base.ddc; 4692 struct drm_connector_state *conn_state; 4693 struct intel_crtc_state *crtc_state; 4694 struct intel_crtc *crtc; 4695 u8 config; 4696 int ret; 4697 4698 if (connector->base.status != connector_status_connected) 4699 return 0; 4700 4701 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4702 ctx); 4703 if (ret) 4704 return ret; 4705 4706 conn_state = connector->base.state; 4707 4708 crtc = to_intel_crtc(conn_state->crtc); 4709 if (!crtc) 4710 return 0; 4711 4712 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4713 if (ret) 4714 return ret; 4715 4716 crtc_state = to_intel_crtc_state(crtc->base.state); 4717 4718 drm_WARN_ON(&dev_priv->drm, 4719 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4720 4721 if (!crtc_state->hw.active) 4722 return 0; 4723 4724 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4725 !crtc_state->hdmi_scrambling) 4726 return 0; 4727 4728 if (conn_state->commit && 4729 !try_wait_for_completion(&conn_state->commit->hw_done)) 4730 return 0; 4731 4732 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4733 if (ret < 0) { 4734 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4735 connector->base.base.id, connector->base.name, ret); 4736 return 0; 4737 } 4738 4739 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4740 crtc_state->hdmi_high_tmds_clock_ratio && 4741 !!(config & SCDC_SCRAMBLING_ENABLE) == 4742 crtc_state->hdmi_scrambling) 4743 return 0; 4744 4745 /* 4746 * HDMI 2.0 says that one should not send scrambled data 4747 * prior to configuring the sink scrambling, and that 4748 * TMDS clock/data transmission should be suspended when 4749 * changing the TMDS clock rate in the sink. So let's 4750 * just do a full modeset here, even though some sinks 4751 * would be perfectly happy if were to just reconfigure 4752 * the SCDC settings on the fly. 4753 */ 4754 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4755 } 4756 4757 static void intel_ddi_link_check(struct intel_encoder *encoder) 4758 { 4759 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4760 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4761 4762 /* TODO: Move checking the HDMI link state here as well. */ 4763 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4764 4765 intel_dp_link_check(encoder); 4766 } 4767 4768 static enum intel_hotplug_state 4769 intel_ddi_hotplug(struct intel_encoder *encoder, 4770 struct intel_connector *connector) 4771 { 4772 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4773 struct intel_dp *intel_dp = &dig_port->dp; 4774 bool is_tc = intel_encoder_is_tc(encoder); 4775 struct drm_modeset_acquire_ctx ctx; 4776 enum intel_hotplug_state state; 4777 int ret; 4778 4779 if (intel_dp_test_phy(intel_dp)) 4780 return INTEL_HOTPLUG_UNCHANGED; 4781 4782 state = intel_encoder_hotplug(encoder, connector); 4783 4784 if (!intel_tc_port_link_reset(dig_port)) { 4785 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4786 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4787 ret = intel_hdmi_reset_link(encoder, &ctx); 4788 drm_WARN_ON(encoder->base.dev, ret); 4789 } else { 4790 intel_dp_check_link_state(intel_dp); 4791 } 4792 } 4793 4794 /* 4795 * Unpowered type-c dongles can take some time to boot and be 4796 * responsible, so here giving some time to those dongles to power up 4797 * and then retrying the probe. 4798 * 4799 * On many platforms the HDMI live state signal is known to be 4800 * unreliable, so we can't use it to detect if a sink is connected or 4801 * not. Instead we detect if it's connected based on whether we can 4802 * read the EDID or not. That in turn has a problem during disconnect, 4803 * since the HPD interrupt may be raised before the DDC lines get 4804 * disconnected (due to how the required length of DDC vs. HPD 4805 * connector pins are specified) and so we'll still be able to get a 4806 * valid EDID. To solve this schedule another detection cycle if this 4807 * time around we didn't detect any change in the sink's connection 4808 * status. 4809 * 4810 * Type-c connectors which get their HPD signal deasserted then 4811 * reasserted, without unplugging/replugging the sink from the 4812 * connector, introduce a delay until the AUX channel communication 4813 * becomes functional. Retry the detection for 5 seconds on type-c 4814 * connectors to account for this delay. 4815 */ 4816 if (state == INTEL_HOTPLUG_UNCHANGED && 4817 connector->hotplug_retries < (is_tc ? 5 : 1) && 4818 !dig_port->dp.is_mst) 4819 state = INTEL_HOTPLUG_RETRY; 4820 4821 return state; 4822 } 4823 4824 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4825 { 4826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4827 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4828 4829 return intel_de_read(dev_priv, SDEISR) & bit; 4830 } 4831 4832 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4833 { 4834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4835 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4836 4837 return intel_de_read(dev_priv, DEISR) & bit; 4838 } 4839 4840 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4841 { 4842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4843 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4844 4845 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4846 } 4847 4848 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4849 { 4850 struct intel_connector *connector; 4851 enum port port = dig_port->base.port; 4852 4853 connector = intel_connector_alloc(); 4854 if (!connector) 4855 return -ENOMEM; 4856 4857 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4858 4859 if (!intel_hdmi_init_connector(dig_port, connector)) { 4860 /* 4861 * HDMI connector init failures may just mean conflicting DDC 4862 * pins or not having enough lanes. Handle them gracefully, but 4863 * don't fail the entire DDI init. 4864 */ 4865 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4866 kfree(connector); 4867 } 4868 4869 return 0; 4870 } 4871 4872 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4873 { 4874 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4875 4876 if (dig_port->base.port != PORT_A) 4877 return false; 4878 4879 if (dig_port->ddi_a_4_lanes) 4880 return false; 4881 4882 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4883 * supported configuration 4884 */ 4885 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4886 return true; 4887 4888 return false; 4889 } 4890 4891 static int 4892 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4893 { 4894 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4895 enum port port = dig_port->base.port; 4896 int max_lanes = 4; 4897 4898 if (DISPLAY_VER(dev_priv) >= 11) 4899 return max_lanes; 4900 4901 if (port == PORT_A || port == PORT_E) { 4902 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4903 max_lanes = port == PORT_A ? 4 : 0; 4904 else 4905 /* Both A and E share 2 lanes */ 4906 max_lanes = 2; 4907 } 4908 4909 /* 4910 * Some BIOS might fail to set this bit on port A if eDP 4911 * wasn't lit up at boot. Force this bit set when needed 4912 * so we use the proper lane count for our calculations. 4913 */ 4914 if (intel_ddi_a_force_4_lanes(dig_port)) { 4915 drm_dbg_kms(&dev_priv->drm, 4916 "Forcing DDI_A_4_LANES for port A\n"); 4917 dig_port->ddi_a_4_lanes = true; 4918 max_lanes = 4; 4919 } 4920 4921 return max_lanes; 4922 } 4923 4924 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4925 enum port port) 4926 { 4927 if (port >= PORT_D_XELPD) 4928 return HPD_PORT_D + port - PORT_D_XELPD; 4929 else if (port >= PORT_TC1) 4930 return HPD_PORT_TC1 + port - PORT_TC1; 4931 else 4932 return HPD_PORT_A + port - PORT_A; 4933 } 4934 4935 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4936 enum port port) 4937 { 4938 if (port >= PORT_TC1) 4939 return HPD_PORT_C + port - PORT_TC1; 4940 else 4941 return HPD_PORT_A + port - PORT_A; 4942 } 4943 4944 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4945 enum port port) 4946 { 4947 if (port >= PORT_TC1) 4948 return HPD_PORT_TC1 + port - PORT_TC1; 4949 else 4950 return HPD_PORT_A + port - PORT_A; 4951 } 4952 4953 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4954 enum port port) 4955 { 4956 if (HAS_PCH_TGP(dev_priv)) 4957 return tgl_hpd_pin(dev_priv, port); 4958 4959 if (port >= PORT_TC1) 4960 return HPD_PORT_C + port - PORT_TC1; 4961 else 4962 return HPD_PORT_A + port - PORT_A; 4963 } 4964 4965 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4966 enum port port) 4967 { 4968 if (port >= PORT_C) 4969 return HPD_PORT_TC1 + port - PORT_C; 4970 else 4971 return HPD_PORT_A + port - PORT_A; 4972 } 4973 4974 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4975 enum port port) 4976 { 4977 if (port == PORT_D) 4978 return HPD_PORT_A; 4979 4980 if (HAS_PCH_TGP(dev_priv)) 4981 return icl_hpd_pin(dev_priv, port); 4982 4983 return HPD_PORT_A + port - PORT_A; 4984 } 4985 4986 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4987 { 4988 if (HAS_PCH_TGP(dev_priv)) 4989 return icl_hpd_pin(dev_priv, port); 4990 4991 return HPD_PORT_A + port - PORT_A; 4992 } 4993 4994 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4995 { 4996 if (DISPLAY_VER(i915) >= 12) 4997 return port >= PORT_TC1; 4998 else if (DISPLAY_VER(i915) >= 11) 4999 return port >= PORT_C; 5000 else 5001 return false; 5002 } 5003 5004 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5005 { 5006 intel_dp_encoder_suspend(encoder); 5007 } 5008 5009 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5010 { 5011 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5012 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5013 5014 /* 5015 * TODO: Move this to intel_dp_encoder_suspend(), 5016 * once modeset locking around that is removed. 5017 */ 5018 intel_encoder_link_check_flush_work(encoder); 5019 intel_tc_port_suspend(dig_port); 5020 } 5021 5022 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5023 { 5024 if (intel_encoder_is_dp(encoder)) 5025 intel_dp_encoder_shutdown(encoder); 5026 if (intel_encoder_is_hdmi(encoder)) 5027 intel_hdmi_encoder_shutdown(encoder); 5028 } 5029 5030 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5031 { 5032 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5033 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5034 5035 intel_tc_port_cleanup(dig_port); 5036 } 5037 5038 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5039 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5040 5041 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 5042 { 5043 /* straps not used on skl+ */ 5044 if (DISPLAY_VER(i915) >= 9) 5045 return true; 5046 5047 switch (port) { 5048 case PORT_A: 5049 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5050 case PORT_B: 5051 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5052 case PORT_C: 5053 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5054 case PORT_D: 5055 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5056 case PORT_E: 5057 return true; /* no strap for DDI-E */ 5058 default: 5059 MISSING_CASE(port); 5060 return false; 5061 } 5062 } 5063 5064 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5065 { 5066 return init_dp || intel_encoder_is_tc(encoder); 5067 } 5068 5069 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 5070 { 5071 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 5072 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 5073 "Platform does not support DSI\n"); 5074 } 5075 5076 static bool port_in_use(struct drm_i915_private *i915, enum port port) 5077 { 5078 struct intel_encoder *encoder; 5079 5080 for_each_intel_encoder(&i915->drm, encoder) { 5081 /* FIXME what about second port for dual link DSI? */ 5082 if (encoder->port == port) 5083 return true; 5084 } 5085 5086 return false; 5087 } 5088 5089 void intel_ddi_init(struct intel_display *display, 5090 const struct intel_bios_encoder_data *devdata) 5091 { 5092 struct drm_i915_private *dev_priv = to_i915(display->drm); 5093 struct intel_digital_port *dig_port; 5094 struct intel_encoder *encoder; 5095 bool init_hdmi, init_dp; 5096 enum port port; 5097 enum phy phy; 5098 u32 ddi_buf_ctl; 5099 5100 port = intel_bios_encoder_port(devdata); 5101 if (port == PORT_NONE) 5102 return; 5103 5104 if (!port_strap_detected(dev_priv, port)) { 5105 drm_dbg_kms(&dev_priv->drm, 5106 "Port %c strap not detected\n", port_name(port)); 5107 return; 5108 } 5109 5110 if (!assert_port_valid(dev_priv, port)) 5111 return; 5112 5113 if (port_in_use(dev_priv, port)) { 5114 drm_dbg_kms(&dev_priv->drm, 5115 "Port %c already claimed\n", port_name(port)); 5116 return; 5117 } 5118 5119 if (intel_bios_encoder_supports_dsi(devdata)) { 5120 /* BXT/GLK handled elsewhere, for now at least */ 5121 if (!assert_has_icl_dsi(dev_priv)) 5122 return; 5123 5124 icl_dsi_init(display, devdata); 5125 return; 5126 } 5127 5128 phy = intel_port_to_phy(dev_priv, port); 5129 5130 /* 5131 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5132 * have taken over some of the PHYs and made them unavailable to the 5133 * driver. In that case we should skip initializing the corresponding 5134 * outputs. 5135 */ 5136 if (intel_hti_uses_phy(display, phy)) { 5137 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5138 port_name(port), phy_name(phy)); 5139 return; 5140 } 5141 5142 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5143 intel_bios_encoder_supports_hdmi(devdata); 5144 init_dp = intel_bios_encoder_supports_dp(devdata); 5145 5146 if (intel_bios_encoder_is_lspcon(devdata)) { 5147 /* 5148 * Lspcon device needs to be driven with DP connector 5149 * with special detection sequence. So make sure DP 5150 * is initialized before lspcon. 5151 */ 5152 init_dp = true; 5153 init_hdmi = false; 5154 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5155 port_name(port)); 5156 } 5157 5158 if (!init_dp && !init_hdmi) { 5159 drm_dbg_kms(&dev_priv->drm, 5160 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5161 port_name(port)); 5162 return; 5163 } 5164 5165 if (intel_phy_is_snps(dev_priv, phy) && 5166 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 5167 drm_dbg_kms(&dev_priv->drm, 5168 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5169 phy_name(phy)); 5170 } 5171 5172 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5173 if (!dig_port) 5174 return; 5175 5176 dig_port->aux_ch = AUX_CH_NONE; 5177 5178 encoder = &dig_port->base; 5179 encoder->devdata = devdata; 5180 5181 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 5182 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5183 DRM_MODE_ENCODER_TMDS, 5184 "DDI %c/PHY %c", 5185 port_name(port - PORT_D_XELPD + PORT_D), 5186 phy_name(phy)); 5187 } else if (DISPLAY_VER(dev_priv) >= 12) { 5188 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5189 5190 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5191 DRM_MODE_ENCODER_TMDS, 5192 "DDI %s%c/PHY %s%c", 5193 port >= PORT_TC1 ? "TC" : "", 5194 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5195 tc_port != TC_PORT_NONE ? "TC" : "", 5196 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5197 } else if (DISPLAY_VER(dev_priv) >= 11) { 5198 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5199 5200 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5201 DRM_MODE_ENCODER_TMDS, 5202 "DDI %c%s/PHY %s%c", 5203 port_name(port), 5204 port >= PORT_C ? " (TC)" : "", 5205 tc_port != TC_PORT_NONE ? "TC" : "", 5206 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5207 } else { 5208 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5209 DRM_MODE_ENCODER_TMDS, 5210 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5211 } 5212 5213 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5214 5215 mutex_init(&dig_port->hdcp_mutex); 5216 dig_port->num_hdcp_streams = 0; 5217 5218 encoder->hotplug = intel_ddi_hotplug; 5219 encoder->compute_output_type = intel_ddi_compute_output_type; 5220 encoder->compute_config = intel_ddi_compute_config; 5221 encoder->compute_config_late = intel_ddi_compute_config_late; 5222 encoder->enable = intel_ddi_enable; 5223 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5224 encoder->pre_enable = intel_ddi_pre_enable; 5225 encoder->disable = intel_ddi_disable; 5226 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5227 encoder->post_disable = intel_ddi_post_disable; 5228 encoder->update_pipe = intel_ddi_update_pipe; 5229 encoder->audio_enable = intel_audio_codec_enable; 5230 encoder->audio_disable = intel_audio_codec_disable; 5231 encoder->get_hw_state = intel_ddi_get_hw_state; 5232 encoder->sync_state = intel_ddi_sync_state; 5233 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5234 encoder->suspend = intel_ddi_encoder_suspend; 5235 encoder->shutdown = intel_ddi_encoder_shutdown; 5236 encoder->get_power_domains = intel_ddi_get_power_domains; 5237 5238 encoder->type = INTEL_OUTPUT_DDI; 5239 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5240 encoder->port = port; 5241 encoder->cloneable = 0; 5242 encoder->pipe_mask = ~0; 5243 5244 if (DISPLAY_VER(dev_priv) >= 14) { 5245 encoder->enable_clock = intel_mtl_pll_enable; 5246 encoder->disable_clock = intel_mtl_pll_disable; 5247 encoder->port_pll_type = intel_mtl_port_pll_type; 5248 encoder->get_config = mtl_ddi_get_config; 5249 } else if (IS_DG2(dev_priv)) { 5250 encoder->enable_clock = intel_mpllb_enable; 5251 encoder->disable_clock = intel_mpllb_disable; 5252 encoder->get_config = dg2_ddi_get_config; 5253 } else if (IS_ALDERLAKE_S(dev_priv)) { 5254 encoder->enable_clock = adls_ddi_enable_clock; 5255 encoder->disable_clock = adls_ddi_disable_clock; 5256 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5257 encoder->get_config = adls_ddi_get_config; 5258 } else if (IS_ROCKETLAKE(dev_priv)) { 5259 encoder->enable_clock = rkl_ddi_enable_clock; 5260 encoder->disable_clock = rkl_ddi_disable_clock; 5261 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5262 encoder->get_config = rkl_ddi_get_config; 5263 } else if (IS_DG1(dev_priv)) { 5264 encoder->enable_clock = dg1_ddi_enable_clock; 5265 encoder->disable_clock = dg1_ddi_disable_clock; 5266 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5267 encoder->get_config = dg1_ddi_get_config; 5268 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5269 if (intel_ddi_is_tc(dev_priv, port)) { 5270 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5271 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5272 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5273 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5274 encoder->get_config = icl_ddi_combo_get_config; 5275 } else { 5276 encoder->enable_clock = icl_ddi_combo_enable_clock; 5277 encoder->disable_clock = icl_ddi_combo_disable_clock; 5278 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5279 encoder->get_config = icl_ddi_combo_get_config; 5280 } 5281 } else if (DISPLAY_VER(dev_priv) >= 11) { 5282 if (intel_ddi_is_tc(dev_priv, port)) { 5283 encoder->enable_clock = icl_ddi_tc_enable_clock; 5284 encoder->disable_clock = icl_ddi_tc_disable_clock; 5285 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5286 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5287 encoder->get_config = icl_ddi_tc_get_config; 5288 } else { 5289 encoder->enable_clock = icl_ddi_combo_enable_clock; 5290 encoder->disable_clock = icl_ddi_combo_disable_clock; 5291 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5292 encoder->get_config = icl_ddi_combo_get_config; 5293 } 5294 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5295 /* BXT/GLK have fixed PLL->port mapping */ 5296 encoder->get_config = bxt_ddi_get_config; 5297 } else if (DISPLAY_VER(dev_priv) == 9) { 5298 encoder->enable_clock = skl_ddi_enable_clock; 5299 encoder->disable_clock = skl_ddi_disable_clock; 5300 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5301 encoder->get_config = skl_ddi_get_config; 5302 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5303 encoder->enable_clock = hsw_ddi_enable_clock; 5304 encoder->disable_clock = hsw_ddi_disable_clock; 5305 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5306 encoder->get_config = hsw_ddi_get_config; 5307 } 5308 5309 if (DISPLAY_VER(dev_priv) >= 14) { 5310 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5311 } else if (IS_DG2(dev_priv)) { 5312 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5313 } else if (DISPLAY_VER(dev_priv) >= 12) { 5314 if (intel_encoder_is_combo(encoder)) 5315 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5316 else 5317 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5318 } else if (DISPLAY_VER(dev_priv) >= 11) { 5319 if (intel_encoder_is_combo(encoder)) 5320 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5321 else 5322 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5323 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5324 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5325 } else { 5326 encoder->set_signal_levels = hsw_set_signal_levels; 5327 } 5328 5329 intel_ddi_buf_trans_init(encoder); 5330 5331 if (DISPLAY_VER(dev_priv) >= 13) 5332 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5333 else if (IS_DG1(dev_priv)) 5334 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5335 else if (IS_ROCKETLAKE(dev_priv)) 5336 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5337 else if (DISPLAY_VER(dev_priv) >= 12) 5338 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5339 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5340 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5341 else if (DISPLAY_VER(dev_priv) == 11) 5342 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5343 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5344 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5345 else 5346 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5347 5348 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 5349 5350 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5351 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5352 5353 dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5354 5355 dig_port->dp.output_reg = INVALID_MMIO_REG; 5356 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5357 5358 if (need_aux_ch(encoder, init_dp)) { 5359 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5360 if (dig_port->aux_ch == AUX_CH_NONE) 5361 goto err; 5362 } 5363 5364 if (intel_encoder_is_tc(encoder)) { 5365 bool is_legacy = 5366 !intel_bios_encoder_supports_typec_usb(devdata) && 5367 !intel_bios_encoder_supports_tbt(devdata); 5368 5369 if (!is_legacy && init_hdmi) { 5370 is_legacy = !init_dp; 5371 5372 drm_dbg_kms(&dev_priv->drm, 5373 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5374 port_name(port), 5375 str_yes_no(init_dp), 5376 is_legacy ? "legacy" : "non-legacy"); 5377 } 5378 5379 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5380 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5381 5382 dig_port->lock = intel_tc_port_lock; 5383 dig_port->unlock = intel_tc_port_unlock; 5384 5385 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5386 goto err; 5387 } 5388 5389 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5390 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5391 5392 if (DISPLAY_VER(dev_priv) >= 11) { 5393 if (intel_encoder_is_tc(encoder)) 5394 dig_port->connected = intel_tc_port_connected; 5395 else 5396 dig_port->connected = lpt_digital_port_connected; 5397 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5398 dig_port->connected = bdw_digital_port_connected; 5399 } else if (DISPLAY_VER(dev_priv) == 9) { 5400 dig_port->connected = lpt_digital_port_connected; 5401 } else if (IS_BROADWELL(dev_priv)) { 5402 if (port == PORT_A) 5403 dig_port->connected = bdw_digital_port_connected; 5404 else 5405 dig_port->connected = lpt_digital_port_connected; 5406 } else if (IS_HASWELL(dev_priv)) { 5407 if (port == PORT_A) 5408 dig_port->connected = hsw_digital_port_connected; 5409 else 5410 dig_port->connected = lpt_digital_port_connected; 5411 } 5412 5413 intel_infoframe_init(dig_port); 5414 5415 if (init_dp) { 5416 if (intel_ddi_init_dp_connector(dig_port)) 5417 goto err; 5418 5419 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5420 5421 if (dig_port->dp.mso_link_count) 5422 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5423 } 5424 5425 /* 5426 * In theory we don't need the encoder->type check, 5427 * but leave it just in case we have some really bad VBTs... 5428 */ 5429 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5430 if (intel_ddi_init_hdmi_connector(dig_port)) 5431 goto err; 5432 } 5433 5434 return; 5435 5436 err: 5437 drm_encoder_cleanup(&encoder->base); 5438 kfree(dig_port); 5439 } 5440