1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_privacy_screen_consumer.h> 35 36 #include "i915_reg.h" 37 #include "i915_utils.h" 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_dkl_phy.h" 56 #include "intel_dkl_phy_regs.h" 57 #include "intel_dp.h" 58 #include "intel_dp_aux.h" 59 #include "intel_dp_link_training.h" 60 #include "intel_dp_mst.h" 61 #include "intel_dp_test.h" 62 #include "intel_dp_tunnel.h" 63 #include "intel_dpio_phy.h" 64 #include "intel_dsi.h" 65 #include "intel_encoder.h" 66 #include "intel_fdi.h" 67 #include "intel_fifo_underrun.h" 68 #include "intel_gmbus.h" 69 #include "intel_hdcp.h" 70 #include "intel_hdmi.h" 71 #include "intel_hotplug.h" 72 #include "intel_hti.h" 73 #include "intel_lspcon.h" 74 #include "intel_mg_phy_regs.h" 75 #include "intel_modeset_lock.h" 76 #include "intel_panel.h" 77 #include "intel_pfit.h" 78 #include "intel_pps.h" 79 #include "intel_psr.h" 80 #include "intel_quirks.h" 81 #include "intel_snps_phy.h" 82 #include "intel_step.h" 83 #include "intel_tc.h" 84 #include "intel_vdsc.h" 85 #include "intel_vdsc_regs.h" 86 #include "intel_vrr.h" 87 #include "skl_scaler.h" 88 #include "skl_universal_plane.h" 89 90 static const u8 index_to_dp_signal_levels[] = { 91 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 94 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 95 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 98 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 99 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 100 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 101 }; 102 103 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 104 const struct intel_ddi_buf_trans *trans) 105 { 106 int level; 107 108 level = intel_bios_hdmi_level_shift(encoder->devdata); 109 if (level < 0) 110 level = trans->hdmi_default_entry; 111 112 return level; 113 } 114 115 static bool has_buf_trans_select(struct intel_display *display) 116 { 117 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 118 } 119 120 static bool has_iboost(struct intel_display *display) 121 { 122 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 123 } 124 125 /* 126 * Starting with Haswell, DDI port buffers must be programmed with correct 127 * values in advance. This function programs the correct values for 128 * DP/eDP/FDI use cases. 129 */ 130 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 131 const struct intel_crtc_state *crtc_state) 132 { 133 struct intel_display *display = to_intel_display(encoder); 134 u32 iboost_bit = 0; 135 int i, n_entries; 136 enum port port = encoder->port; 137 const struct intel_ddi_buf_trans *trans; 138 139 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 140 if (drm_WARN_ON_ONCE(display->drm, !trans)) 141 return; 142 143 /* If we're boosting the current, set bit 31 of trans1 */ 144 if (has_iboost(display) && 145 intel_bios_dp_boost_level(encoder->devdata)) 146 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 147 148 for (i = 0; i < n_entries; i++) { 149 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 150 trans->entries[i].hsw.trans1 | iboost_bit); 151 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 152 trans->entries[i].hsw.trans2); 153 } 154 } 155 156 /* 157 * Starting with Haswell, DDI port buffers must be programmed with correct 158 * values in advance. This function programs the correct values for 159 * HDMI/DVI use cases. 160 */ 161 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 162 const struct intel_crtc_state *crtc_state) 163 { 164 struct intel_display *display = to_intel_display(encoder); 165 int level = intel_ddi_level(encoder, crtc_state, 0); 166 u32 iboost_bit = 0; 167 int n_entries; 168 enum port port = encoder->port; 169 const struct intel_ddi_buf_trans *trans; 170 171 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 172 if (drm_WARN_ON_ONCE(display->drm, !trans)) 173 return; 174 175 /* If we're boosting the current, set bit 31 of trans1 */ 176 if (has_iboost(display) && 177 intel_bios_hdmi_boost_level(encoder->devdata)) 178 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 179 180 /* Entry 9 is for HDMI: */ 181 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 182 trans->entries[level].hsw.trans1 | iboost_bit); 183 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 184 trans->entries[level].hsw.trans2); 185 } 186 187 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 188 { 189 if (DISPLAY_VER(display) >= 14) 190 return XELPDP_PORT_BUF_CTL1(display, port); 191 else 192 return DDI_BUF_CTL(port); 193 } 194 195 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 196 { 197 /* 198 * Bspec's platform specific timeouts: 199 * MTL+ : 100 us 200 * BXT : fixed 16 us 201 * HSW-ADL: 8 us 202 * 203 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 204 */ 205 if (display->platform.broxton) { 206 udelay(16); 207 return; 208 } 209 210 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 211 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 212 DDI_BUF_IS_IDLE, 10)) 213 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 214 port_name(port)); 215 } 216 217 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 218 { 219 struct intel_display *display = to_intel_display(encoder); 220 enum port port = encoder->port; 221 222 /* 223 * Bspec's platform specific timeouts: 224 * MTL+ : 10000 us 225 * DG2 : 1200 us 226 * TGL-ADL combo PHY: 1000 us 227 * TGL-ADL TypeC PHY: 3000 us 228 * HSW-ICL : fixed 518 us 229 */ 230 if (DISPLAY_VER(display) < 10) { 231 usleep_range(518, 1000); 232 return; 233 } 234 235 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 236 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 237 DDI_BUF_IS_IDLE, 10)) 238 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 239 port_name(port)); 240 } 241 242 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 243 { 244 switch (pll->info->id) { 245 case DPLL_ID_WRPLL1: 246 return PORT_CLK_SEL_WRPLL1; 247 case DPLL_ID_WRPLL2: 248 return PORT_CLK_SEL_WRPLL2; 249 case DPLL_ID_SPLL: 250 return PORT_CLK_SEL_SPLL; 251 case DPLL_ID_LCPLL_810: 252 return PORT_CLK_SEL_LCPLL_810; 253 case DPLL_ID_LCPLL_1350: 254 return PORT_CLK_SEL_LCPLL_1350; 255 case DPLL_ID_LCPLL_2700: 256 return PORT_CLK_SEL_LCPLL_2700; 257 default: 258 MISSING_CASE(pll->info->id); 259 return PORT_CLK_SEL_NONE; 260 } 261 } 262 263 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 264 const struct intel_crtc_state *crtc_state) 265 { 266 const struct intel_dpll *pll = crtc_state->intel_dpll; 267 int clock = crtc_state->port_clock; 268 const enum intel_dpll_id id = pll->info->id; 269 270 switch (id) { 271 default: 272 /* 273 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 274 * here, so do warn if this get passed in 275 */ 276 MISSING_CASE(id); 277 return DDI_CLK_SEL_NONE; 278 case DPLL_ID_ICL_TBTPLL: 279 switch (clock) { 280 case 162000: 281 return DDI_CLK_SEL_TBT_162; 282 case 270000: 283 return DDI_CLK_SEL_TBT_270; 284 case 540000: 285 return DDI_CLK_SEL_TBT_540; 286 case 810000: 287 return DDI_CLK_SEL_TBT_810; 288 default: 289 MISSING_CASE(clock); 290 return DDI_CLK_SEL_NONE; 291 } 292 case DPLL_ID_ICL_MGPLL1: 293 case DPLL_ID_ICL_MGPLL2: 294 case DPLL_ID_ICL_MGPLL3: 295 case DPLL_ID_ICL_MGPLL4: 296 case DPLL_ID_TGL_MGPLL5: 297 case DPLL_ID_TGL_MGPLL6: 298 return DDI_CLK_SEL_MG; 299 } 300 } 301 302 static u32 ddi_buf_phy_link_rate(int port_clock) 303 { 304 switch (port_clock) { 305 case 162000: 306 return DDI_BUF_PHY_LINK_RATE(0); 307 case 216000: 308 return DDI_BUF_PHY_LINK_RATE(4); 309 case 243000: 310 return DDI_BUF_PHY_LINK_RATE(5); 311 case 270000: 312 return DDI_BUF_PHY_LINK_RATE(1); 313 case 324000: 314 return DDI_BUF_PHY_LINK_RATE(6); 315 case 432000: 316 return DDI_BUF_PHY_LINK_RATE(7); 317 case 540000: 318 return DDI_BUF_PHY_LINK_RATE(2); 319 case 810000: 320 return DDI_BUF_PHY_LINK_RATE(3); 321 default: 322 MISSING_CASE(port_clock); 323 return DDI_BUF_PHY_LINK_RATE(0); 324 } 325 } 326 327 static int dp_phy_lane_stagger_delay(int port_clock) 328 { 329 /* 330 * Return the number of symbol clocks delay used to stagger the 331 * assertion/desassertion of the port lane enables. The target delay 332 * time is 100 ns or greater, return the number of symbols specific to 333 * the provided port_clock (aka link clock) corresponding to this delay 334 * time, i.e. so that 335 * 336 * number_of_symbols * duration_of_one_symbol >= 100 ns 337 * 338 * The delay must be applied only on TypeC DP outputs, for everything else 339 * the delay must be set to 0. 340 * 341 * Return the number of link symbols per 100 ns: 342 * port_clock (10 kHz) -> bits / 100 us 343 * / symbol_size -> symbols / 100 us 344 * / 1000 -> symbols / 100 ns 345 */ 346 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 347 } 348 349 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 350 const struct intel_crtc_state *crtc_state) 351 { 352 struct intel_display *display = to_intel_display(encoder); 353 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 354 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 355 356 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 357 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 358 DDI_BUF_TRANS_SELECT(0); 359 360 if (dig_port->lane_reversal) 361 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 362 if (dig_port->ddi_a_4_lanes) 363 intel_dp->DP |= DDI_A_4_LANES; 364 365 if (DISPLAY_VER(display) >= 14) { 366 if (intel_dp_is_uhbr(crtc_state)) 367 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 368 else 369 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 370 } 371 372 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 373 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 374 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 375 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 376 } 377 378 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 379 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 380 381 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 382 } 383 } 384 385 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 386 { 387 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 388 389 switch (val) { 390 case DDI_CLK_SEL_NONE: 391 return 0; 392 case DDI_CLK_SEL_TBT_162: 393 return 162000; 394 case DDI_CLK_SEL_TBT_270: 395 return 270000; 396 case DDI_CLK_SEL_TBT_540: 397 return 540000; 398 case DDI_CLK_SEL_TBT_810: 399 return 810000; 400 default: 401 MISSING_CASE(val); 402 return 0; 403 } 404 } 405 406 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 407 { 408 /* CRT dotclock is determined via other means */ 409 if (pipe_config->has_pch_encoder) 410 return; 411 412 pipe_config->hw.adjusted_mode.crtc_clock = 413 intel_crtc_dotclock(pipe_config); 414 } 415 416 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 417 const struct drm_connector_state *conn_state) 418 { 419 struct intel_display *display = to_intel_display(crtc_state); 420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 421 u32 temp; 422 423 if (!intel_crtc_has_dp_encoder(crtc_state)) 424 return; 425 426 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 427 428 temp = DP_MSA_MISC_SYNC_CLOCK; 429 430 switch (crtc_state->pipe_bpp) { 431 case 18: 432 temp |= DP_MSA_MISC_6_BPC; 433 break; 434 case 24: 435 temp |= DP_MSA_MISC_8_BPC; 436 break; 437 case 30: 438 temp |= DP_MSA_MISC_10_BPC; 439 break; 440 case 36: 441 temp |= DP_MSA_MISC_12_BPC; 442 break; 443 default: 444 MISSING_CASE(crtc_state->pipe_bpp); 445 break; 446 } 447 448 /* nonsense combination */ 449 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 450 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 451 452 if (crtc_state->limited_color_range) 453 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 454 455 /* 456 * As per DP 1.2 spec section 2.3.4.3 while sending 457 * YCBCR 444 signals we should program MSA MISC1/0 fields with 458 * colorspace information. 459 */ 460 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 461 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 462 463 /* 464 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 465 * of Color Encoding Format and Content Color Gamut] while sending 466 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 467 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 468 */ 469 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 470 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 471 472 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 473 temp); 474 } 475 476 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 477 { 478 if (master_transcoder == TRANSCODER_EDP) 479 return 0; 480 else 481 return master_transcoder + 1; 482 } 483 484 static void 485 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 486 bool enable) 487 { 488 struct intel_display *display = to_intel_display(crtc_state); 489 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 490 u32 val = 0; 491 492 if (!HAS_DP20(display)) 493 return; 494 495 if (enable && intel_dp_is_uhbr(crtc_state)) 496 val = TRANS_DP2_128B132B_CHANNEL_CODING; 497 498 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 499 } 500 501 /* 502 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 503 * 504 * Only intended to be used by intel_ddi_enable_transcoder_func() and 505 * intel_ddi_config_transcoder_func(). 506 */ 507 static u32 508 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 509 const struct intel_crtc_state *crtc_state) 510 { 511 struct intel_display *display = to_intel_display(crtc_state); 512 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 513 enum pipe pipe = crtc->pipe; 514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 515 enum port port = encoder->port; 516 u32 temp; 517 518 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 519 temp = TRANS_DDI_FUNC_ENABLE; 520 if (DISPLAY_VER(display) >= 12) 521 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 522 else 523 temp |= TRANS_DDI_SELECT_PORT(port); 524 525 switch (crtc_state->pipe_bpp) { 526 default: 527 MISSING_CASE(crtc_state->pipe_bpp); 528 fallthrough; 529 case 18: 530 temp |= TRANS_DDI_BPC_6; 531 break; 532 case 24: 533 temp |= TRANS_DDI_BPC_8; 534 break; 535 case 30: 536 temp |= TRANS_DDI_BPC_10; 537 break; 538 case 36: 539 temp |= TRANS_DDI_BPC_12; 540 break; 541 } 542 543 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 544 temp |= TRANS_DDI_PVSYNC; 545 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 546 temp |= TRANS_DDI_PHSYNC; 547 548 if (cpu_transcoder == TRANSCODER_EDP) { 549 switch (pipe) { 550 default: 551 MISSING_CASE(pipe); 552 fallthrough; 553 case PIPE_A: 554 /* On Haswell, can only use the always-on power well for 555 * eDP when not using the panel fitter, and when not 556 * using motion blur mitigation (which we don't 557 * support). */ 558 if (crtc_state->pch_pfit.force_thru) 559 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 560 else 561 temp |= TRANS_DDI_EDP_INPUT_A_ON; 562 break; 563 case PIPE_B: 564 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 565 break; 566 case PIPE_C: 567 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 568 break; 569 } 570 } 571 572 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 573 if (crtc_state->has_hdmi_sink) 574 temp |= TRANS_DDI_MODE_SELECT_HDMI; 575 else 576 temp |= TRANS_DDI_MODE_SELECT_DVI; 577 578 if (crtc_state->hdmi_scrambling) 579 temp |= TRANS_DDI_HDMI_SCRAMBLING; 580 if (crtc_state->hdmi_high_tmds_clock_ratio) 581 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 582 if (DISPLAY_VER(display) >= 14) 583 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 584 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 585 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 586 temp |= (crtc_state->fdi_lanes - 1) << 1; 587 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 588 intel_dp_is_uhbr(crtc_state)) { 589 if (intel_dp_is_uhbr(crtc_state)) 590 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 591 else 592 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 593 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 594 595 if (DISPLAY_VER(display) >= 12) { 596 enum transcoder master; 597 598 master = crtc_state->mst_master_transcoder; 599 if (drm_WARN_ON(display->drm, 600 master == INVALID_TRANSCODER)) 601 master = TRANSCODER_A; 602 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 603 } 604 } else { 605 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 606 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 607 } 608 609 if (IS_DISPLAY_VER(display, 8, 10) && 610 crtc_state->master_transcoder != INVALID_TRANSCODER) { 611 u8 master_select = 612 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 613 614 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 615 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 616 } 617 618 return temp; 619 } 620 621 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 622 const struct intel_crtc_state *crtc_state) 623 { 624 struct intel_display *display = to_intel_display(crtc_state); 625 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 626 627 if (DISPLAY_VER(display) >= 11) { 628 enum transcoder master_transcoder = crtc_state->master_transcoder; 629 u32 ctl2 = 0; 630 631 if (master_transcoder != INVALID_TRANSCODER) { 632 u8 master_select = 633 bdw_trans_port_sync_master_select(master_transcoder); 634 635 ctl2 |= PORT_SYNC_MODE_ENABLE | 636 PORT_SYNC_MODE_MASTER_SELECT(master_select); 637 } 638 639 intel_de_write(display, 640 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 641 ctl2); 642 } 643 644 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 645 intel_ddi_transcoder_func_reg_val_get(encoder, 646 crtc_state)); 647 } 648 649 /* 650 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 651 * bit for the DDI function and enables the DP2 configuration. Called for all 652 * transcoder types. 653 */ 654 void 655 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 656 const struct intel_crtc_state *crtc_state) 657 { 658 struct intel_display *display = to_intel_display(crtc_state); 659 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 660 u32 ctl; 661 662 intel_ddi_config_transcoder_dp2(crtc_state, true); 663 664 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 665 ctl &= ~TRANS_DDI_FUNC_ENABLE; 666 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 667 ctl); 668 } 669 670 /* 671 * Disable the DDI function and port syncing. 672 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 673 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 674 * transcoders these are done later in intel_ddi_post_disable_dp(). 675 */ 676 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 677 { 678 struct intel_display *display = to_intel_display(crtc_state); 679 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 680 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 681 u32 ctl; 682 683 if (DISPLAY_VER(display) >= 11) 684 intel_de_write(display, 685 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 686 0); 687 688 ctl = intel_de_read(display, 689 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 690 691 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 692 693 ctl &= ~TRANS_DDI_FUNC_ENABLE; 694 695 if (IS_DISPLAY_VER(display, 8, 10)) 696 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 697 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 698 699 if (DISPLAY_VER(display) >= 12) { 700 if (!intel_dp_mst_is_master_trans(crtc_state)) { 701 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 702 TRANS_DDI_MODE_SELECT_MASK); 703 } 704 } else { 705 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 706 } 707 708 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 709 ctl); 710 711 if (intel_dp_mst_is_slave_trans(crtc_state)) 712 intel_ddi_config_transcoder_dp2(crtc_state, false); 713 714 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 715 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 716 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 717 /* Quirk time at 100ms for reliable operation */ 718 msleep(100); 719 } 720 } 721 722 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 723 enum transcoder cpu_transcoder, 724 bool enable, u32 hdcp_mask) 725 { 726 struct intel_display *display = to_intel_display(intel_encoder); 727 intel_wakeref_t wakeref; 728 int ret = 0; 729 730 wakeref = intel_display_power_get_if_enabled(display, 731 intel_encoder->power_domain); 732 if (drm_WARN_ON(display->drm, !wakeref)) 733 return -ENXIO; 734 735 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 736 hdcp_mask, enable ? hdcp_mask : 0); 737 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 738 return ret; 739 } 740 741 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 742 { 743 struct intel_display *display = to_intel_display(intel_connector); 744 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 745 int type = intel_connector->base.connector_type; 746 enum port port = encoder->port; 747 enum transcoder cpu_transcoder; 748 intel_wakeref_t wakeref; 749 enum pipe pipe = 0; 750 u32 ddi_mode; 751 bool ret; 752 753 wakeref = intel_display_power_get_if_enabled(display, 754 encoder->power_domain); 755 if (!wakeref) 756 return false; 757 758 /* Note: This returns false for DP MST primary encoders. */ 759 if (!encoder->get_hw_state(encoder, &pipe)) { 760 ret = false; 761 goto out; 762 } 763 764 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 765 cpu_transcoder = TRANSCODER_EDP; 766 else 767 cpu_transcoder = (enum transcoder) pipe; 768 769 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 770 TRANS_DDI_MODE_SELECT_MASK; 771 772 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 773 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 774 ret = type == DRM_MODE_CONNECTOR_HDMIA; 775 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 776 ret = type == DRM_MODE_CONNECTOR_VGA; 777 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 778 ret = type == DRM_MODE_CONNECTOR_eDP || 779 type == DRM_MODE_CONNECTOR_DisplayPort; 780 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 781 /* 782 * encoder->get_hw_state() should have bailed out on MST. This 783 * must be SST and non-eDP. 784 */ 785 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 786 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 787 /* encoder->get_hw_state() should have bailed out on MST. */ 788 ret = false; 789 } else { 790 ret = false; 791 } 792 793 out: 794 intel_display_power_put(display, encoder->power_domain, wakeref); 795 796 return ret; 797 } 798 799 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 800 u8 *pipe_mask, bool *is_dp_mst) 801 { 802 struct intel_display *display = to_intel_display(encoder); 803 enum port port = encoder->port; 804 intel_wakeref_t wakeref; 805 enum pipe p; 806 u32 tmp; 807 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 808 809 *pipe_mask = 0; 810 *is_dp_mst = false; 811 812 wakeref = intel_display_power_get_if_enabled(display, 813 encoder->power_domain); 814 if (!wakeref) 815 return; 816 817 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 818 if (!(tmp & DDI_BUF_CTL_ENABLE)) 819 goto out; 820 821 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 822 tmp = intel_de_read(display, 823 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 824 825 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 826 default: 827 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 828 fallthrough; 829 case TRANS_DDI_EDP_INPUT_A_ON: 830 case TRANS_DDI_EDP_INPUT_A_ONOFF: 831 *pipe_mask = BIT(PIPE_A); 832 break; 833 case TRANS_DDI_EDP_INPUT_B_ONOFF: 834 *pipe_mask = BIT(PIPE_B); 835 break; 836 case TRANS_DDI_EDP_INPUT_C_ONOFF: 837 *pipe_mask = BIT(PIPE_C); 838 break; 839 } 840 841 goto out; 842 } 843 844 for_each_pipe(display, p) { 845 enum transcoder cpu_transcoder = (enum transcoder)p; 846 u32 port_mask, ddi_select, ddi_mode; 847 intel_wakeref_t trans_wakeref; 848 849 trans_wakeref = intel_display_power_get_if_enabled(display, 850 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 851 if (!trans_wakeref) 852 continue; 853 854 if (DISPLAY_VER(display) >= 12) { 855 port_mask = TGL_TRANS_DDI_PORT_MASK; 856 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 857 } else { 858 port_mask = TRANS_DDI_PORT_MASK; 859 ddi_select = TRANS_DDI_SELECT_PORT(port); 860 } 861 862 tmp = intel_de_read(display, 863 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 864 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 865 trans_wakeref); 866 867 if ((tmp & port_mask) != ddi_select) 868 continue; 869 870 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 871 872 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 873 mst_pipe_mask |= BIT(p); 874 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 875 dp128b132b_pipe_mask |= BIT(p); 876 877 *pipe_mask |= BIT(p); 878 } 879 880 if (!*pipe_mask) 881 drm_dbg_kms(display->drm, 882 "No pipe for [ENCODER:%d:%s] found\n", 883 encoder->base.base.id, encoder->base.name); 884 885 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 886 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 887 888 /* 889 * If we don't have 8b/10b MST, but have more than one 890 * transcoder in 128b/132b mode, we know it must be 128b/132b 891 * MST. 892 * 893 * Otherwise, we fall back to checking the current MST 894 * state. It's not accurate for hardware takeover at probe, but 895 * we don't expect MST to have been enabled at that point, and 896 * can assume it's SST. 897 */ 898 if (hweight8(dp128b132b_pipe_mask) > 1 || 899 intel_dp_mst_active_streams(intel_dp)) 900 mst_pipe_mask = dp128b132b_pipe_mask; 901 } 902 903 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 904 drm_dbg_kms(display->drm, 905 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 906 encoder->base.base.id, encoder->base.name, 907 *pipe_mask); 908 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 909 } 910 911 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 912 drm_dbg_kms(display->drm, 913 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 914 encoder->base.base.id, encoder->base.name, 915 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 916 else 917 *is_dp_mst = mst_pipe_mask; 918 919 out: 920 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 921 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 922 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 923 BXT_PHY_LANE_POWERDOWN_ACK | 924 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 925 drm_err(display->drm, 926 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 927 encoder->base.base.id, encoder->base.name, tmp); 928 } 929 930 intel_display_power_put(display, encoder->power_domain, wakeref); 931 } 932 933 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 934 enum pipe *pipe) 935 { 936 u8 pipe_mask; 937 bool is_mst; 938 939 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 940 941 if (is_mst || !pipe_mask) 942 return false; 943 944 *pipe = ffs(pipe_mask) - 1; 945 946 return true; 947 } 948 949 static enum intel_display_power_domain 950 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 951 const struct intel_crtc_state *crtc_state) 952 { 953 struct intel_display *display = to_intel_display(dig_port); 954 955 /* 956 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 957 * DC states enabled at the same time, while for driver initiated AUX 958 * transfers we need the same AUX IOs to be powered but with DC states 959 * disabled. Accordingly use the AUX_IO_<port> power domain here which 960 * leaves DC states enabled. 961 * 962 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 963 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 964 * well, so we can acquire a wider AUX_<port> power domain reference 965 * instead of a specific AUX_IO_<port> reference without powering up any 966 * extra wells. 967 */ 968 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 969 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 970 else if (DISPLAY_VER(display) < 14 && 971 (intel_crtc_has_dp_encoder(crtc_state) || 972 intel_encoder_is_tc(&dig_port->base))) 973 return intel_aux_power_domain(dig_port); 974 else 975 return POWER_DOMAIN_INVALID; 976 } 977 978 static void 979 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 980 const struct intel_crtc_state *crtc_state) 981 { 982 struct intel_display *display = to_intel_display(dig_port); 983 enum intel_display_power_domain domain = 984 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 985 986 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 987 988 if (domain == POWER_DOMAIN_INVALID) 989 return; 990 991 dig_port->aux_wakeref = intel_display_power_get(display, domain); 992 } 993 994 static void 995 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 996 const struct intel_crtc_state *crtc_state) 997 { 998 struct intel_display *display = to_intel_display(dig_port); 999 enum intel_display_power_domain domain = 1000 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1001 intel_wakeref_t wf; 1002 1003 wf = fetch_and_zero(&dig_port->aux_wakeref); 1004 if (!wf) 1005 return; 1006 1007 intel_display_power_put(display, domain, wf); 1008 } 1009 1010 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1011 struct intel_crtc_state *crtc_state) 1012 { 1013 struct intel_display *display = to_intel_display(encoder); 1014 struct intel_digital_port *dig_port; 1015 1016 /* 1017 * TODO: Add support for MST encoders. Atm, the following should never 1018 * happen since fake-MST encoders don't set their get_power_domains() 1019 * hook. 1020 */ 1021 if (drm_WARN_ON(display->drm, 1022 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1023 return; 1024 1025 dig_port = enc_to_dig_port(encoder); 1026 1027 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1028 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1029 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1030 dig_port->ddi_io_power_domain); 1031 } 1032 1033 main_link_aux_power_domain_get(dig_port, crtc_state); 1034 } 1035 1036 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1037 const struct intel_crtc_state *crtc_state) 1038 { 1039 struct intel_display *display = to_intel_display(crtc_state); 1040 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1041 enum phy phy = intel_encoder_to_phy(encoder); 1042 u32 val; 1043 1044 if (cpu_transcoder == TRANSCODER_EDP) 1045 return; 1046 1047 if (DISPLAY_VER(display) >= 13) 1048 val = TGL_TRANS_CLK_SEL_PORT(phy); 1049 else if (DISPLAY_VER(display) >= 12) 1050 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1051 else 1052 val = TRANS_CLK_SEL_PORT(encoder->port); 1053 1054 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1055 } 1056 1057 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1058 { 1059 struct intel_display *display = to_intel_display(crtc_state); 1060 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1061 u32 val; 1062 1063 if (cpu_transcoder == TRANSCODER_EDP) 1064 return; 1065 1066 if (DISPLAY_VER(display) >= 12) 1067 val = TGL_TRANS_CLK_SEL_DISABLED; 1068 else 1069 val = TRANS_CLK_SEL_DISABLED; 1070 1071 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1072 } 1073 1074 static void _skl_ddi_set_iboost(struct intel_display *display, 1075 enum port port, u8 iboost) 1076 { 1077 u32 tmp; 1078 1079 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1080 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1081 if (iboost) 1082 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1083 else 1084 tmp |= BALANCE_LEG_DISABLE(port); 1085 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1086 } 1087 1088 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1089 const struct intel_crtc_state *crtc_state, 1090 int level) 1091 { 1092 struct intel_display *display = to_intel_display(encoder); 1093 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1094 u8 iboost; 1095 1096 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1097 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1098 else 1099 iboost = intel_bios_dp_boost_level(encoder->devdata); 1100 1101 if (iboost == 0) { 1102 const struct intel_ddi_buf_trans *trans; 1103 int n_entries; 1104 1105 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1106 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1107 return; 1108 1109 iboost = trans->entries[level].hsw.i_boost; 1110 } 1111 1112 /* Make sure that the requested I_boost is valid */ 1113 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1114 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1115 return; 1116 } 1117 1118 _skl_ddi_set_iboost(display, encoder->port, iboost); 1119 1120 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1121 _skl_ddi_set_iboost(display, PORT_E, iboost); 1122 } 1123 1124 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1125 const struct intel_crtc_state *crtc_state) 1126 { 1127 struct intel_display *display = to_intel_display(intel_dp); 1128 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1129 int n_entries; 1130 1131 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1132 1133 if (drm_WARN_ON(display->drm, n_entries < 1)) 1134 n_entries = 1; 1135 if (drm_WARN_ON(display->drm, 1136 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1137 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1138 1139 return index_to_dp_signal_levels[n_entries - 1] & 1140 DP_TRAIN_VOLTAGE_SWING_MASK; 1141 } 1142 1143 /* 1144 * We assume that the full set of pre-emphasis values can be 1145 * used on all DDI platforms. Should that change we need to 1146 * rethink this code. 1147 */ 1148 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1149 { 1150 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1151 } 1152 1153 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1154 int lane) 1155 { 1156 if (crtc_state->port_clock > 600000) 1157 return 0; 1158 1159 if (crtc_state->lane_count == 4) 1160 return lane >= 1 ? LOADGEN_SELECT : 0; 1161 else 1162 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1163 } 1164 1165 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1166 const struct intel_crtc_state *crtc_state) 1167 { 1168 struct intel_display *display = to_intel_display(encoder); 1169 const struct intel_ddi_buf_trans *trans; 1170 enum phy phy = intel_encoder_to_phy(encoder); 1171 int n_entries, ln; 1172 u32 val; 1173 1174 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1175 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1176 return; 1177 1178 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1179 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1180 1181 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1182 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1183 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1184 intel_dp->hobl_active ? val : 0); 1185 } 1186 1187 /* Set PORT_TX_DW5 */ 1188 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1189 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1190 COEFF_POLARITY | CURSOR_PROGRAM | 1191 TAP2_DISABLE | TAP3_DISABLE); 1192 val |= SCALING_MODE_SEL(0x2); 1193 val |= RTERM_SELECT(0x6); 1194 val |= TAP3_DISABLE; 1195 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1196 1197 /* Program PORT_TX_DW2 */ 1198 for (ln = 0; ln < 4; ln++) { 1199 int level = intel_ddi_level(encoder, crtc_state, ln); 1200 1201 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1202 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1203 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1204 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1205 RCOMP_SCALAR(0x98)); 1206 } 1207 1208 /* Program PORT_TX_DW4 */ 1209 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1210 for (ln = 0; ln < 4; ln++) { 1211 int level = intel_ddi_level(encoder, crtc_state, ln); 1212 1213 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1214 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1215 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1216 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1217 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1218 } 1219 1220 /* Program PORT_TX_DW7 */ 1221 for (ln = 0; ln < 4; ln++) { 1222 int level = intel_ddi_level(encoder, crtc_state, ln); 1223 1224 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1225 N_SCALAR_MASK, 1226 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1227 } 1228 } 1229 1230 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1231 const struct intel_crtc_state *crtc_state) 1232 { 1233 struct intel_display *display = to_intel_display(encoder); 1234 enum phy phy = intel_encoder_to_phy(encoder); 1235 u32 val; 1236 int ln; 1237 1238 /* 1239 * 1. If port type is eDP or DP, 1240 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1241 * else clear to 0b. 1242 */ 1243 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1244 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1245 val &= ~COMMON_KEEPER_EN; 1246 else 1247 val |= COMMON_KEEPER_EN; 1248 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1249 1250 /* 2. Program loadgen select */ 1251 /* 1252 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1253 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1254 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1255 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1256 */ 1257 for (ln = 0; ln < 4; ln++) { 1258 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1259 LOADGEN_SELECT, 1260 icl_combo_phy_loadgen_select(crtc_state, ln)); 1261 } 1262 1263 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1264 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1265 0, SUS_CLOCK_CONFIG); 1266 1267 /* 4. Clear training enable to change swing values */ 1268 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1269 val &= ~TX_TRAINING_EN; 1270 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1271 1272 /* 5. Program swing and de-emphasis */ 1273 icl_ddi_combo_vswing_program(encoder, crtc_state); 1274 1275 /* 6. Set training enable to trigger update */ 1276 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1277 val |= TX_TRAINING_EN; 1278 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1279 } 1280 1281 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1282 const struct intel_crtc_state *crtc_state) 1283 { 1284 struct intel_display *display = to_intel_display(encoder); 1285 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1286 const struct intel_ddi_buf_trans *trans; 1287 int n_entries, ln; 1288 1289 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1290 return; 1291 1292 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1293 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1294 return; 1295 1296 for (ln = 0; ln < 2; ln++) { 1297 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1298 CRI_USE_FS32, 0); 1299 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1300 CRI_USE_FS32, 0); 1301 } 1302 1303 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1304 for (ln = 0; ln < 2; ln++) { 1305 int level; 1306 1307 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1308 1309 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1310 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1311 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1314 1315 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1316 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1317 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1318 } 1319 1320 /* Program MG_TX_DRVCTRL with values from vswing table */ 1321 for (ln = 0; ln < 2; ln++) { 1322 int level; 1323 1324 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1325 1326 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1327 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1328 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1329 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1330 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1331 CRI_TXDEEMPH_OVERRIDE_EN); 1332 1333 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1334 1335 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1336 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1337 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1338 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1339 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1340 CRI_TXDEEMPH_OVERRIDE_EN); 1341 1342 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1343 } 1344 1345 /* 1346 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1347 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1348 * values from table for which TX1 and TX2 enabled. 1349 */ 1350 for (ln = 0; ln < 2; ln++) { 1351 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1352 CFG_LOW_RATE_LKREN_EN, 1353 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1354 } 1355 1356 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1357 for (ln = 0; ln < 2; ln++) { 1358 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1359 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1360 CFG_AMI_CK_DIV_OVERRIDE_EN, 1361 crtc_state->port_clock > 500000 ? 1362 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1363 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1364 1365 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1367 CFG_AMI_CK_DIV_OVERRIDE_EN, 1368 crtc_state->port_clock > 500000 ? 1369 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1370 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1371 } 1372 1373 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1374 for (ln = 0; ln < 2; ln++) { 1375 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1376 0, CRI_CALCINIT); 1377 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1378 0, CRI_CALCINIT); 1379 } 1380 } 1381 1382 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1383 const struct intel_crtc_state *crtc_state) 1384 { 1385 struct intel_display *display = to_intel_display(encoder); 1386 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1387 const struct intel_ddi_buf_trans *trans; 1388 int n_entries, ln; 1389 1390 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1391 return; 1392 1393 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1394 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1395 return; 1396 1397 for (ln = 0; ln < 2; ln++) { 1398 int level; 1399 1400 /* Wa_16011342517:adl-p */ 1401 if (display->platform.alderlake_p && 1402 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) { 1403 if ((intel_encoder_is_hdmi(encoder) && 1404 crtc_state->port_clock == 594000) || 1405 (intel_encoder_is_dp(encoder) && 1406 crtc_state->port_clock == 162000)) { 1407 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1408 LOADGEN_SHARING_PMD_DISABLE, 1); 1409 } else { 1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1411 LOADGEN_SHARING_PMD_DISABLE, 0); 1412 } 1413 } 1414 1415 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1416 1417 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1418 1419 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1420 DKL_TX_PRESHOOT_COEFF_MASK | 1421 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1422 DKL_TX_VSWING_CONTROL_MASK, 1423 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1424 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1425 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1426 1427 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1428 1429 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1430 DKL_TX_PRESHOOT_COEFF_MASK | 1431 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1432 DKL_TX_VSWING_CONTROL_MASK, 1433 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1434 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1435 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1436 1437 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1438 DKL_TX_DP20BITMODE, 0); 1439 1440 if (display->platform.alderlake_p) { 1441 u32 val; 1442 1443 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1444 if (ln == 0) { 1445 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1446 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1447 } else { 1448 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1449 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1450 } 1451 } else { 1452 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1453 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1454 } 1455 1456 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1457 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1458 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1459 val); 1460 } 1461 } 1462 } 1463 1464 static int translate_signal_level(struct intel_dp *intel_dp, 1465 u8 signal_levels) 1466 { 1467 struct intel_display *display = to_intel_display(intel_dp); 1468 int i; 1469 1470 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1471 if (index_to_dp_signal_levels[i] == signal_levels) 1472 return i; 1473 } 1474 1475 drm_WARN(display->drm, 1, 1476 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1477 signal_levels); 1478 1479 return 0; 1480 } 1481 1482 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1483 const struct intel_crtc_state *crtc_state, 1484 int lane) 1485 { 1486 u8 train_set = intel_dp->train_set[lane]; 1487 1488 if (intel_dp_is_uhbr(crtc_state)) { 1489 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1490 } else { 1491 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1492 DP_TRAIN_PRE_EMPHASIS_MASK); 1493 1494 return translate_signal_level(intel_dp, signal_levels); 1495 } 1496 } 1497 1498 int intel_ddi_level(struct intel_encoder *encoder, 1499 const struct intel_crtc_state *crtc_state, 1500 int lane) 1501 { 1502 struct intel_display *display = to_intel_display(encoder); 1503 const struct intel_ddi_buf_trans *trans; 1504 int level, n_entries; 1505 1506 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1507 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1508 return 0; 1509 1510 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1511 level = intel_ddi_hdmi_level(encoder, trans); 1512 else 1513 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1514 lane); 1515 1516 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1517 level = n_entries - 1; 1518 1519 return level; 1520 } 1521 1522 static void 1523 hsw_set_signal_levels(struct intel_encoder *encoder, 1524 const struct intel_crtc_state *crtc_state) 1525 { 1526 struct intel_display *display = to_intel_display(encoder); 1527 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1528 int level = intel_ddi_level(encoder, crtc_state, 0); 1529 enum port port = encoder->port; 1530 u32 signal_levels; 1531 1532 if (has_iboost(display)) 1533 skl_ddi_set_iboost(encoder, crtc_state, level); 1534 1535 /* HDMI ignores the rest */ 1536 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1537 return; 1538 1539 signal_levels = DDI_BUF_TRANS_SELECT(level); 1540 1541 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1542 signal_levels); 1543 1544 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1545 intel_dp->DP |= signal_levels; 1546 1547 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1548 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1549 } 1550 1551 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1552 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1553 { 1554 mutex_lock(&display->dpll.lock); 1555 1556 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1557 1558 /* 1559 * "This step and the step before must be 1560 * done with separate register writes." 1561 */ 1562 intel_de_rmw(display, reg, clk_off, 0); 1563 1564 mutex_unlock(&display->dpll.lock); 1565 } 1566 1567 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1568 u32 clk_off) 1569 { 1570 mutex_lock(&display->dpll.lock); 1571 1572 intel_de_rmw(display, reg, 0, clk_off); 1573 1574 mutex_unlock(&display->dpll.lock); 1575 } 1576 1577 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1578 u32 clk_off) 1579 { 1580 return !(intel_de_read(display, reg) & clk_off); 1581 } 1582 1583 static struct intel_dpll * 1584 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1585 u32 clk_sel_mask, u32 clk_sel_shift) 1586 { 1587 enum intel_dpll_id id; 1588 1589 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1590 1591 return intel_get_dpll_by_id(display, id); 1592 } 1593 1594 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1595 const struct intel_crtc_state *crtc_state) 1596 { 1597 struct intel_display *display = to_intel_display(encoder); 1598 const struct intel_dpll *pll = crtc_state->intel_dpll; 1599 enum phy phy = intel_encoder_to_phy(encoder); 1600 1601 if (drm_WARN_ON(display->drm, !pll)) 1602 return; 1603 1604 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1605 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1606 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1607 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1608 } 1609 1610 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1611 { 1612 struct intel_display *display = to_intel_display(encoder); 1613 enum phy phy = intel_encoder_to_phy(encoder); 1614 1615 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1616 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1617 } 1618 1619 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1620 { 1621 struct intel_display *display = to_intel_display(encoder); 1622 enum phy phy = intel_encoder_to_phy(encoder); 1623 1624 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1625 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1626 } 1627 1628 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1629 { 1630 struct intel_display *display = to_intel_display(encoder); 1631 enum phy phy = intel_encoder_to_phy(encoder); 1632 1633 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1634 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1635 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1636 } 1637 1638 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1639 const struct intel_crtc_state *crtc_state) 1640 { 1641 struct intel_display *display = to_intel_display(encoder); 1642 const struct intel_dpll *pll = crtc_state->intel_dpll; 1643 enum phy phy = intel_encoder_to_phy(encoder); 1644 1645 if (drm_WARN_ON(display->drm, !pll)) 1646 return; 1647 1648 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1649 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1650 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1651 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1652 } 1653 1654 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1655 { 1656 struct intel_display *display = to_intel_display(encoder); 1657 enum phy phy = intel_encoder_to_phy(encoder); 1658 1659 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1661 } 1662 1663 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1664 { 1665 struct intel_display *display = to_intel_display(encoder); 1666 enum phy phy = intel_encoder_to_phy(encoder); 1667 1668 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1669 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1670 } 1671 1672 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1673 { 1674 struct intel_display *display = to_intel_display(encoder); 1675 enum phy phy = intel_encoder_to_phy(encoder); 1676 1677 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1678 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1679 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1680 } 1681 1682 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1683 const struct intel_crtc_state *crtc_state) 1684 { 1685 struct intel_display *display = to_intel_display(encoder); 1686 const struct intel_dpll *pll = crtc_state->intel_dpll; 1687 enum phy phy = intel_encoder_to_phy(encoder); 1688 1689 if (drm_WARN_ON(display->drm, !pll)) 1690 return; 1691 1692 /* 1693 * If we fail this, something went very wrong: first 2 PLLs should be 1694 * used by first 2 phys and last 2 PLLs by last phys 1695 */ 1696 if (drm_WARN_ON(display->drm, 1697 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1698 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1699 return; 1700 1701 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1702 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1703 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1704 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1705 } 1706 1707 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1708 { 1709 struct intel_display *display = to_intel_display(encoder); 1710 enum phy phy = intel_encoder_to_phy(encoder); 1711 1712 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1713 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1714 } 1715 1716 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1717 { 1718 struct intel_display *display = to_intel_display(encoder); 1719 enum phy phy = intel_encoder_to_phy(encoder); 1720 1721 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1722 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1723 } 1724 1725 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1726 { 1727 struct intel_display *display = to_intel_display(encoder); 1728 enum phy phy = intel_encoder_to_phy(encoder); 1729 enum intel_dpll_id id; 1730 u32 val; 1731 1732 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1733 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1734 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1735 id = val; 1736 1737 /* 1738 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1739 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1740 * bit for phy C and D. 1741 */ 1742 if (phy >= PHY_C) 1743 id += DPLL_ID_DG1_DPLL2; 1744 1745 return intel_get_dpll_by_id(display, id); 1746 } 1747 1748 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1749 const struct intel_crtc_state *crtc_state) 1750 { 1751 struct intel_display *display = to_intel_display(encoder); 1752 const struct intel_dpll *pll = crtc_state->intel_dpll; 1753 enum phy phy = intel_encoder_to_phy(encoder); 1754 1755 if (drm_WARN_ON(display->drm, !pll)) 1756 return; 1757 1758 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1759 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1760 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1761 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1762 } 1763 1764 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1765 { 1766 struct intel_display *display = to_intel_display(encoder); 1767 enum phy phy = intel_encoder_to_phy(encoder); 1768 1769 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1771 } 1772 1773 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1774 { 1775 struct intel_display *display = to_intel_display(encoder); 1776 enum phy phy = intel_encoder_to_phy(encoder); 1777 1778 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1779 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1780 } 1781 1782 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1783 { 1784 struct intel_display *display = to_intel_display(encoder); 1785 enum phy phy = intel_encoder_to_phy(encoder); 1786 1787 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1788 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1789 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1790 } 1791 1792 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1793 const struct intel_crtc_state *crtc_state) 1794 { 1795 struct intel_display *display = to_intel_display(encoder); 1796 const struct intel_dpll *pll = crtc_state->intel_dpll; 1797 enum port port = encoder->port; 1798 1799 if (drm_WARN_ON(display->drm, !pll)) 1800 return; 1801 1802 /* 1803 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1804 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1805 */ 1806 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1807 1808 icl_ddi_combo_enable_clock(encoder, crtc_state); 1809 } 1810 1811 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1812 { 1813 struct intel_display *display = to_intel_display(encoder); 1814 enum port port = encoder->port; 1815 1816 icl_ddi_combo_disable_clock(encoder); 1817 1818 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1819 } 1820 1821 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1822 { 1823 struct intel_display *display = to_intel_display(encoder); 1824 enum port port = encoder->port; 1825 u32 tmp; 1826 1827 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1828 1829 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1830 return false; 1831 1832 return icl_ddi_combo_is_clock_enabled(encoder); 1833 } 1834 1835 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1836 const struct intel_crtc_state *crtc_state) 1837 { 1838 struct intel_display *display = to_intel_display(encoder); 1839 const struct intel_dpll *pll = crtc_state->intel_dpll; 1840 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1841 enum port port = encoder->port; 1842 1843 if (drm_WARN_ON(display->drm, !pll)) 1844 return; 1845 1846 intel_de_write(display, DDI_CLK_SEL(port), 1847 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1848 1849 mutex_lock(&display->dpll.lock); 1850 1851 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1852 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1853 1854 mutex_unlock(&display->dpll.lock); 1855 } 1856 1857 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1858 { 1859 struct intel_display *display = to_intel_display(encoder); 1860 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1861 enum port port = encoder->port; 1862 1863 mutex_lock(&display->dpll.lock); 1864 1865 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1866 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1867 1868 mutex_unlock(&display->dpll.lock); 1869 1870 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1871 } 1872 1873 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1874 { 1875 struct intel_display *display = to_intel_display(encoder); 1876 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1877 enum port port = encoder->port; 1878 u32 tmp; 1879 1880 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1881 1882 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1883 return false; 1884 1885 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1886 1887 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1888 } 1889 1890 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1891 { 1892 struct intel_display *display = to_intel_display(encoder); 1893 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1894 enum port port = encoder->port; 1895 enum intel_dpll_id id; 1896 u32 tmp; 1897 1898 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1899 1900 switch (tmp & DDI_CLK_SEL_MASK) { 1901 case DDI_CLK_SEL_TBT_162: 1902 case DDI_CLK_SEL_TBT_270: 1903 case DDI_CLK_SEL_TBT_540: 1904 case DDI_CLK_SEL_TBT_810: 1905 id = DPLL_ID_ICL_TBTPLL; 1906 break; 1907 case DDI_CLK_SEL_MG: 1908 id = icl_tc_port_to_pll_id(tc_port); 1909 break; 1910 default: 1911 MISSING_CASE(tmp); 1912 fallthrough; 1913 case DDI_CLK_SEL_NONE: 1914 return NULL; 1915 } 1916 1917 return intel_get_dpll_by_id(display, id); 1918 } 1919 1920 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1921 { 1922 struct intel_display *display = to_intel_display(encoder->base.dev); 1923 enum intel_dpll_id id; 1924 1925 switch (encoder->port) { 1926 case PORT_A: 1927 id = DPLL_ID_SKL_DPLL0; 1928 break; 1929 case PORT_B: 1930 id = DPLL_ID_SKL_DPLL1; 1931 break; 1932 case PORT_C: 1933 id = DPLL_ID_SKL_DPLL2; 1934 break; 1935 default: 1936 MISSING_CASE(encoder->port); 1937 return NULL; 1938 } 1939 1940 return intel_get_dpll_by_id(display, id); 1941 } 1942 1943 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1944 const struct intel_crtc_state *crtc_state) 1945 { 1946 struct intel_display *display = to_intel_display(encoder); 1947 const struct intel_dpll *pll = crtc_state->intel_dpll; 1948 enum port port = encoder->port; 1949 1950 if (drm_WARN_ON(display->drm, !pll)) 1951 return; 1952 1953 mutex_lock(&display->dpll.lock); 1954 1955 intel_de_rmw(display, DPLL_CTRL2, 1956 DPLL_CTRL2_DDI_CLK_OFF(port) | 1957 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1958 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1959 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1960 1961 mutex_unlock(&display->dpll.lock); 1962 } 1963 1964 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1965 { 1966 struct intel_display *display = to_intel_display(encoder); 1967 enum port port = encoder->port; 1968 1969 mutex_lock(&display->dpll.lock); 1970 1971 intel_de_rmw(display, DPLL_CTRL2, 1972 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1973 1974 mutex_unlock(&display->dpll.lock); 1975 } 1976 1977 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1978 { 1979 struct intel_display *display = to_intel_display(encoder); 1980 enum port port = encoder->port; 1981 1982 /* 1983 * FIXME Not sure if the override affects both 1984 * the PLL selection and the CLK_OFF bit. 1985 */ 1986 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1987 } 1988 1989 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1990 { 1991 struct intel_display *display = to_intel_display(encoder); 1992 enum port port = encoder->port; 1993 enum intel_dpll_id id; 1994 u32 tmp; 1995 1996 tmp = intel_de_read(display, DPLL_CTRL2); 1997 1998 /* 1999 * FIXME Not sure if the override affects both 2000 * the PLL selection and the CLK_OFF bit. 2001 */ 2002 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2003 return NULL; 2004 2005 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2006 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2007 2008 return intel_get_dpll_by_id(display, id); 2009 } 2010 2011 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2012 const struct intel_crtc_state *crtc_state) 2013 { 2014 struct intel_display *display = to_intel_display(encoder); 2015 const struct intel_dpll *pll = crtc_state->intel_dpll; 2016 enum port port = encoder->port; 2017 2018 if (drm_WARN_ON(display->drm, !pll)) 2019 return; 2020 2021 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2022 } 2023 2024 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2025 { 2026 struct intel_display *display = to_intel_display(encoder); 2027 enum port port = encoder->port; 2028 2029 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2030 } 2031 2032 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2033 { 2034 struct intel_display *display = to_intel_display(encoder); 2035 enum port port = encoder->port; 2036 2037 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2038 } 2039 2040 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2041 { 2042 struct intel_display *display = to_intel_display(encoder); 2043 enum port port = encoder->port; 2044 enum intel_dpll_id id; 2045 u32 tmp; 2046 2047 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2048 2049 switch (tmp & PORT_CLK_SEL_MASK) { 2050 case PORT_CLK_SEL_WRPLL1: 2051 id = DPLL_ID_WRPLL1; 2052 break; 2053 case PORT_CLK_SEL_WRPLL2: 2054 id = DPLL_ID_WRPLL2; 2055 break; 2056 case PORT_CLK_SEL_SPLL: 2057 id = DPLL_ID_SPLL; 2058 break; 2059 case PORT_CLK_SEL_LCPLL_810: 2060 id = DPLL_ID_LCPLL_810; 2061 break; 2062 case PORT_CLK_SEL_LCPLL_1350: 2063 id = DPLL_ID_LCPLL_1350; 2064 break; 2065 case PORT_CLK_SEL_LCPLL_2700: 2066 id = DPLL_ID_LCPLL_2700; 2067 break; 2068 default: 2069 MISSING_CASE(tmp); 2070 fallthrough; 2071 case PORT_CLK_SEL_NONE: 2072 return NULL; 2073 } 2074 2075 return intel_get_dpll_by_id(display, id); 2076 } 2077 2078 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2079 const struct intel_crtc_state *crtc_state) 2080 { 2081 if (encoder->enable_clock) 2082 encoder->enable_clock(encoder, crtc_state); 2083 } 2084 2085 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2086 { 2087 if (encoder->disable_clock) 2088 encoder->disable_clock(encoder); 2089 } 2090 2091 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2092 { 2093 struct intel_display *display = to_intel_display(encoder); 2094 u32 port_mask; 2095 bool ddi_clk_needed; 2096 2097 /* 2098 * In case of DP MST, we sanitize the primary encoder only, not the 2099 * virtual ones. 2100 */ 2101 if (encoder->type == INTEL_OUTPUT_DP_MST) 2102 return; 2103 2104 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2105 u8 pipe_mask; 2106 bool is_mst; 2107 2108 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2109 /* 2110 * In the unlikely case that BIOS enables DP in MST mode, just 2111 * warn since our MST HW readout is incomplete. 2112 */ 2113 if (drm_WARN_ON(display->drm, is_mst)) 2114 return; 2115 } 2116 2117 port_mask = BIT(encoder->port); 2118 ddi_clk_needed = encoder->base.crtc; 2119 2120 if (encoder->type == INTEL_OUTPUT_DSI) { 2121 struct intel_encoder *other_encoder; 2122 2123 port_mask = intel_dsi_encoder_ports(encoder); 2124 /* 2125 * Sanity check that we haven't incorrectly registered another 2126 * encoder using any of the ports of this DSI encoder. 2127 */ 2128 for_each_intel_encoder(display->drm, other_encoder) { 2129 if (other_encoder == encoder) 2130 continue; 2131 2132 if (drm_WARN_ON(display->drm, 2133 port_mask & BIT(other_encoder->port))) 2134 return; 2135 } 2136 /* 2137 * For DSI we keep the ddi clocks gated 2138 * except during enable/disable sequence. 2139 */ 2140 ddi_clk_needed = false; 2141 } 2142 2143 if (ddi_clk_needed || !encoder->is_clock_enabled || 2144 !encoder->is_clock_enabled(encoder)) 2145 return; 2146 2147 drm_dbg_kms(display->drm, 2148 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2149 encoder->base.base.id, encoder->base.name); 2150 2151 encoder->disable_clock(encoder); 2152 } 2153 2154 static void 2155 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2156 enum tc_port tc_port, u32 ln0, u32 ln1) 2157 { 2158 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2159 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2160 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2161 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2162 } 2163 2164 static void 2165 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2166 const struct intel_crtc_state *crtc_state) 2167 { 2168 struct intel_display *display = to_intel_display(crtc_state); 2169 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2170 u32 ln0, ln1, pin_assignment; 2171 u8 width; 2172 2173 if (DISPLAY_VER(display) >= 14) 2174 return; 2175 2176 if (!intel_encoder_is_tc(&dig_port->base) || 2177 intel_tc_port_in_tbt_alt_mode(dig_port)) 2178 return; 2179 2180 if (DISPLAY_VER(display) >= 12) { 2181 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2182 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2183 } else { 2184 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2185 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2186 } 2187 2188 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2189 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2190 2191 /* DPPATC */ 2192 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2193 width = crtc_state->lane_count; 2194 2195 switch (pin_assignment) { 2196 case 0x0: 2197 drm_WARN_ON(display->drm, 2198 !intel_tc_port_in_legacy_mode(dig_port)); 2199 if (width == 1) { 2200 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2201 } else { 2202 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2203 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2204 } 2205 break; 2206 case 0x1: 2207 if (width == 4) { 2208 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2209 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2210 } 2211 break; 2212 case 0x2: 2213 if (width == 2) { 2214 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2215 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2216 } 2217 break; 2218 case 0x3: 2219 case 0x5: 2220 if (width == 1) { 2221 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2222 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2223 } else { 2224 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2225 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 } 2227 break; 2228 case 0x4: 2229 case 0x6: 2230 if (width == 1) { 2231 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2232 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2233 } else { 2234 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2235 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2236 } 2237 break; 2238 default: 2239 MISSING_CASE(pin_assignment); 2240 } 2241 2242 if (DISPLAY_VER(display) >= 12) { 2243 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2244 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2245 /* WA_14018221282 */ 2246 if (IS_DISPLAY_VER(display, 12, 13)) 2247 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2248 2249 } else { 2250 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2251 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2252 } 2253 } 2254 2255 static enum transcoder 2256 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2257 { 2258 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2259 return crtc_state->mst_master_transcoder; 2260 else 2261 return crtc_state->cpu_transcoder; 2262 } 2263 2264 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2265 const struct intel_crtc_state *crtc_state) 2266 { 2267 struct intel_display *display = to_intel_display(encoder); 2268 2269 if (DISPLAY_VER(display) >= 12) 2270 return TGL_DP_TP_CTL(display, 2271 tgl_dp_tp_transcoder(crtc_state)); 2272 else 2273 return DP_TP_CTL(encoder->port); 2274 } 2275 2276 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2277 const struct intel_crtc_state *crtc_state) 2278 { 2279 struct intel_display *display = to_intel_display(encoder); 2280 2281 if (DISPLAY_VER(display) >= 12) 2282 return TGL_DP_TP_STATUS(display, 2283 tgl_dp_tp_transcoder(crtc_state)); 2284 else 2285 return DP_TP_STATUS(encoder->port); 2286 } 2287 2288 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2289 const struct intel_crtc_state *crtc_state) 2290 { 2291 struct intel_display *display = to_intel_display(encoder); 2292 2293 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2294 DP_TP_STATUS_ACT_SENT); 2295 } 2296 2297 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2298 const struct intel_crtc_state *crtc_state) 2299 { 2300 struct intel_display *display = to_intel_display(encoder); 2301 2302 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2303 DP_TP_STATUS_ACT_SENT, 1)) 2304 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2305 } 2306 2307 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2308 const struct intel_crtc_state *crtc_state, 2309 bool enable) 2310 { 2311 struct intel_display *display = to_intel_display(intel_dp); 2312 2313 if (!crtc_state->vrr.enable) 2314 return; 2315 2316 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2317 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2318 drm_dbg_kms(display->drm, 2319 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2320 str_enable_disable(enable)); 2321 } 2322 2323 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2324 const struct intel_crtc_state *crtc_state, 2325 bool enable) 2326 { 2327 struct intel_display *display = to_intel_display(intel_dp); 2328 2329 if (!crtc_state->fec_enable) 2330 return; 2331 2332 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2333 enable ? DP_FEC_READY : 0) <= 0) 2334 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2335 str_enabled_disabled(enable)); 2336 2337 if (enable && 2338 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2339 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2340 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2341 } 2342 2343 static int read_fec_detected_status(struct drm_dp_aux *aux) 2344 { 2345 int ret; 2346 u8 status; 2347 2348 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2349 if (ret < 0) 2350 return ret; 2351 2352 return status; 2353 } 2354 2355 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2356 { 2357 struct intel_display *display = to_intel_display(aux->drm_dev); 2358 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2359 int status; 2360 int err; 2361 2362 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2363 status & mask || status < 0, 2364 10000, 200000); 2365 2366 if (err || status < 0) { 2367 drm_dbg_kms(display->drm, 2368 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2369 str_enabled_disabled(enabled), err, status); 2370 return err ? err : status; 2371 } 2372 2373 return 0; 2374 } 2375 2376 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2377 const struct intel_crtc_state *crtc_state, 2378 bool enabled) 2379 { 2380 struct intel_display *display = to_intel_display(encoder); 2381 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2382 int ret; 2383 2384 if (!crtc_state->fec_enable) 2385 return 0; 2386 2387 if (enabled) 2388 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2389 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2390 else 2391 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2392 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2393 2394 if (ret) { 2395 drm_err(display->drm, 2396 "Timeout waiting for FEC live state to get %s\n", 2397 str_enabled_disabled(enabled)); 2398 return ret; 2399 } 2400 /* 2401 * At least the Synoptics MST hub doesn't set the detected flag for 2402 * FEC decoding disabling so skip waiting for that. 2403 */ 2404 if (enabled) { 2405 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2406 if (ret) 2407 return ret; 2408 } 2409 2410 return 0; 2411 } 2412 2413 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2414 const struct intel_crtc_state *crtc_state) 2415 { 2416 struct intel_display *display = to_intel_display(encoder); 2417 int i; 2418 int ret; 2419 2420 if (!crtc_state->fec_enable) 2421 return; 2422 2423 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2424 0, DP_TP_CTL_FEC_ENABLE); 2425 2426 if (DISPLAY_VER(display) < 30) 2427 return; 2428 2429 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2430 if (!ret) 2431 return; 2432 2433 for (i = 0; i < 3; i++) { 2434 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2435 2436 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2437 DP_TP_CTL_FEC_ENABLE, 0); 2438 2439 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2440 if (ret) 2441 continue; 2442 2443 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2444 0, DP_TP_CTL_FEC_ENABLE); 2445 2446 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2447 if (!ret) 2448 return; 2449 } 2450 2451 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2452 } 2453 2454 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2455 const struct intel_crtc_state *crtc_state) 2456 { 2457 struct intel_display *display = to_intel_display(encoder); 2458 2459 if (!crtc_state->fec_enable) 2460 return; 2461 2462 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2463 DP_TP_CTL_FEC_ENABLE, 0); 2464 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2465 } 2466 2467 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2468 const struct intel_crtc_state *crtc_state) 2469 { 2470 struct intel_display *display = to_intel_display(encoder); 2471 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2472 2473 if (intel_encoder_is_combo(encoder)) { 2474 enum phy phy = intel_encoder_to_phy(encoder); 2475 2476 intel_combo_phy_power_up_lanes(display, phy, false, 2477 crtc_state->lane_count, 2478 dig_port->lane_reversal); 2479 } 2480 } 2481 2482 /* 2483 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2484 * platforms. 2485 */ 2486 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2487 { 2488 if (DISPLAY_VER(display) > 20) 2489 return ~0; 2490 else if (display->platform.alderlake_p) 2491 return BIT(PIPE_A) | BIT(PIPE_B); 2492 else 2493 return BIT(PIPE_A); 2494 } 2495 2496 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2497 struct intel_crtc_state *pipe_config) 2498 { 2499 struct intel_display *display = to_intel_display(pipe_config); 2500 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2501 enum pipe pipe = crtc->pipe; 2502 u32 dss1; 2503 2504 if (!HAS_MSO(display)) 2505 return; 2506 2507 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2508 2509 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2510 if (!pipe_config->splitter.enable) 2511 return; 2512 2513 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2514 pipe_config->splitter.enable = false; 2515 return; 2516 } 2517 2518 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2519 default: 2520 drm_WARN(display->drm, true, 2521 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2522 fallthrough; 2523 case SPLITTER_CONFIGURATION_2_SEGMENT: 2524 pipe_config->splitter.link_count = 2; 2525 break; 2526 case SPLITTER_CONFIGURATION_4_SEGMENT: 2527 pipe_config->splitter.link_count = 4; 2528 break; 2529 } 2530 2531 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2532 } 2533 2534 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2535 { 2536 struct intel_display *display = to_intel_display(crtc_state); 2537 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2538 enum pipe pipe = crtc->pipe; 2539 u32 dss1 = 0; 2540 2541 if (!HAS_MSO(display)) 2542 return; 2543 2544 if (crtc_state->splitter.enable) { 2545 dss1 |= SPLITTER_ENABLE; 2546 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2547 if (crtc_state->splitter.link_count == 2) 2548 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2549 else 2550 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2551 } 2552 2553 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2554 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2555 OVERLAP_PIXELS_MASK, dss1); 2556 } 2557 2558 static void 2559 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2560 { 2561 struct intel_display *display = to_intel_display(encoder); 2562 enum port port = encoder->port; 2563 i915_reg_t reg; 2564 u32 set_bits, wait_bits; 2565 2566 if (DISPLAY_VER(display) < 14) 2567 return; 2568 2569 if (DISPLAY_VER(display) >= 20) { 2570 reg = DDI_BUF_CTL(port); 2571 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2572 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2573 } else { 2574 reg = XELPDP_PORT_BUF_CTL1(display, port); 2575 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2576 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2577 } 2578 2579 intel_de_rmw(display, reg, 0, set_bits); 2580 if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { 2581 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2582 port_name(port)); 2583 } 2584 } 2585 2586 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2587 const struct intel_crtc_state *crtc_state) 2588 { 2589 struct intel_display *display = to_intel_display(encoder); 2590 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2591 enum port port = encoder->port; 2592 u32 val = 0; 2593 2594 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2595 2596 if (intel_dp_is_uhbr(crtc_state)) 2597 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2598 else 2599 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2600 2601 if (dig_port->lane_reversal) 2602 val |= XELPDP_PORT_REVERSAL; 2603 2604 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2605 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2606 val); 2607 } 2608 2609 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2610 { 2611 struct intel_display *display = to_intel_display(encoder); 2612 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2613 u32 val; 2614 2615 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2616 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2617 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2618 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2619 } 2620 2621 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2622 struct intel_encoder *encoder, 2623 const struct intel_crtc_state *crtc_state, 2624 const struct drm_connector_state *conn_state) 2625 { 2626 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2627 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2628 bool transparent_mode; 2629 int ret; 2630 2631 intel_dp_set_link_params(intel_dp, 2632 crtc_state->port_clock, 2633 crtc_state->lane_count); 2634 2635 /* 2636 * We only configure what the register value will be here. Actual 2637 * enabling happens during link training farther down. 2638 */ 2639 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2640 2641 /* 2642 * 1. Enable Power Wells 2643 * 2644 * This was handled at the beginning of intel_atomic_commit_tail(), 2645 * before we called down into this function. 2646 */ 2647 2648 /* 2. PMdemand was already set */ 2649 2650 /* 3. Select Thunderbolt */ 2651 mtl_port_buf_ctl_io_selection(encoder); 2652 2653 /* 4. Enable Panel Power if PPS is required */ 2654 intel_pps_on(intel_dp); 2655 2656 /* 5. Enable the port PLL */ 2657 intel_ddi_enable_clock(encoder, crtc_state); 2658 2659 /* 2660 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2661 * Transcoder. 2662 */ 2663 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2664 2665 /* 2666 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2667 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2668 * Transport Select 2669 */ 2670 intel_ddi_config_transcoder_func(encoder, crtc_state); 2671 2672 /* 2673 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2674 */ 2675 intel_ddi_mso_configure(crtc_state); 2676 2677 if (!is_mst) 2678 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2679 2680 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2681 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2682 2683 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2684 if (!is_mst) 2685 intel_dp_sink_enable_decompression(state, 2686 to_intel_connector(conn_state->connector), 2687 crtc_state); 2688 2689 /* 2690 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2691 * in the FEC_CONFIGURATION register to 1 before initiating link 2692 * training 2693 */ 2694 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2695 2696 intel_dp_check_frl_training(intel_dp); 2697 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2698 2699 /* 2700 * 6. The rest of the below are substeps under the bspec's "Enable and 2701 * Train Display Port" step. Note that steps that are specific to 2702 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2703 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2704 * us when active_mst_links==0, so any steps designated for "single 2705 * stream or multi-stream master transcoder" can just be performed 2706 * unconditionally here. 2707 * 2708 * mtl_ddi_prepare_link_retrain() that is called by 2709 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2710 * 6.i and 6.j 2711 * 2712 * 6.k Follow DisplayPort specification training sequence (see notes for 2713 * failure handling) 2714 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2715 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2716 * (timeout after 800 us) 2717 */ 2718 intel_dp_start_link_train(state, intel_dp, crtc_state); 2719 2720 /* 6.n Set DP_TP_CTL link training to Normal */ 2721 if (!is_trans_port_sync_mode(crtc_state)) 2722 intel_dp_stop_link_train(intel_dp, crtc_state); 2723 2724 /* 6.o Configure and enable FEC if needed */ 2725 intel_ddi_enable_fec(encoder, crtc_state); 2726 2727 /* 7.a 128b/132b SST. */ 2728 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2729 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2730 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2731 if (ret < 0) 2732 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2733 } 2734 2735 if (!is_mst) 2736 intel_dsc_dp_pps_write(encoder, crtc_state); 2737 } 2738 2739 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2740 struct intel_encoder *encoder, 2741 const struct intel_crtc_state *crtc_state, 2742 const struct drm_connector_state *conn_state) 2743 { 2744 struct intel_display *display = to_intel_display(encoder); 2745 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2746 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2747 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2748 int ret; 2749 2750 intel_dp_set_link_params(intel_dp, 2751 crtc_state->port_clock, 2752 crtc_state->lane_count); 2753 2754 /* 2755 * We only configure what the register value will be here. Actual 2756 * enabling happens during link training farther down. 2757 */ 2758 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2759 2760 /* 2761 * 1. Enable Power Wells 2762 * 2763 * This was handled at the beginning of intel_atomic_commit_tail(), 2764 * before we called down into this function. 2765 */ 2766 2767 /* 2. Enable Panel Power if PPS is required */ 2768 intel_pps_on(intel_dp); 2769 2770 /* 2771 * 3. For non-TBT Type-C ports, set FIA lane count 2772 * (DFLEXDPSP.DPX4TXLATC) 2773 * 2774 * This was done before tgl_ddi_pre_enable_dp by 2775 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2776 */ 2777 2778 /* 2779 * 4. Enable the port PLL. 2780 * 2781 * The PLL enabling itself was already done before this function by 2782 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2783 * configure the PLL to port mapping here. 2784 */ 2785 intel_ddi_enable_clock(encoder, crtc_state); 2786 2787 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2788 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2789 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2790 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2791 dig_port->ddi_io_power_domain); 2792 } 2793 2794 /* 6. Program DP_MODE */ 2795 icl_program_mg_dp_mode(dig_port, crtc_state); 2796 2797 /* 2798 * 7. The rest of the below are substeps under the bspec's "Enable and 2799 * Train Display Port" step. Note that steps that are specific to 2800 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2801 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2802 * us when active_mst_links==0, so any steps designated for "single 2803 * stream or multi-stream master transcoder" can just be performed 2804 * unconditionally here. 2805 */ 2806 2807 /* 2808 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2809 * Transcoder. 2810 */ 2811 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2812 2813 /* 2814 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2815 * Transport Select 2816 */ 2817 intel_ddi_config_transcoder_func(encoder, crtc_state); 2818 2819 /* 2820 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2821 * selected 2822 * 2823 * This will be handled by the intel_dp_start_link_train() farther 2824 * down this function. 2825 */ 2826 2827 /* 7.e Configure voltage swing and related IO settings */ 2828 encoder->set_signal_levels(encoder, crtc_state); 2829 2830 /* 2831 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2832 * the used lanes of the DDI. 2833 */ 2834 intel_ddi_power_up_lanes(encoder, crtc_state); 2835 2836 /* 2837 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2838 */ 2839 intel_ddi_mso_configure(crtc_state); 2840 2841 if (!is_mst) 2842 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2843 2844 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2845 if (!is_mst) 2846 intel_dp_sink_enable_decompression(state, 2847 to_intel_connector(conn_state->connector), 2848 crtc_state); 2849 /* 2850 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2851 * in the FEC_CONFIGURATION register to 1 before initiating link 2852 * training 2853 */ 2854 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2855 2856 intel_dp_check_frl_training(intel_dp); 2857 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2858 2859 /* 2860 * 7.i Follow DisplayPort specification training sequence (see notes for 2861 * failure handling) 2862 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2863 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2864 * (timeout after 800 us) 2865 */ 2866 intel_dp_start_link_train(state, intel_dp, crtc_state); 2867 2868 /* 7.k Set DP_TP_CTL link training to Normal */ 2869 if (!is_trans_port_sync_mode(crtc_state)) 2870 intel_dp_stop_link_train(intel_dp, crtc_state); 2871 2872 /* 7.l Configure and enable FEC if needed */ 2873 intel_ddi_enable_fec(encoder, crtc_state); 2874 2875 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2876 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2877 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2878 if (ret < 0) 2879 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2880 } 2881 2882 if (!is_mst) 2883 intel_dsc_dp_pps_write(encoder, crtc_state); 2884 } 2885 2886 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2887 struct intel_encoder *encoder, 2888 const struct intel_crtc_state *crtc_state, 2889 const struct drm_connector_state *conn_state) 2890 { 2891 struct intel_display *display = to_intel_display(encoder); 2892 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2893 enum port port = encoder->port; 2894 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2895 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2896 2897 if (DISPLAY_VER(display) < 11) 2898 drm_WARN_ON(display->drm, 2899 is_mst && (port == PORT_A || port == PORT_E)); 2900 else 2901 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2902 2903 intel_dp_set_link_params(intel_dp, 2904 crtc_state->port_clock, 2905 crtc_state->lane_count); 2906 2907 /* 2908 * We only configure what the register value will be here. Actual 2909 * enabling happens during link training farther down. 2910 */ 2911 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2912 2913 intel_pps_on(intel_dp); 2914 2915 intel_ddi_enable_clock(encoder, crtc_state); 2916 2917 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2918 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2919 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2920 dig_port->ddi_io_power_domain); 2921 } 2922 2923 icl_program_mg_dp_mode(dig_port, crtc_state); 2924 2925 if (has_buf_trans_select(display)) 2926 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2927 2928 encoder->set_signal_levels(encoder, crtc_state); 2929 2930 intel_ddi_power_up_lanes(encoder, crtc_state); 2931 2932 if (!is_mst) 2933 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2934 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2935 if (!is_mst) 2936 intel_dp_sink_enable_decompression(state, 2937 to_intel_connector(conn_state->connector), 2938 crtc_state); 2939 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2940 intel_dp_start_link_train(state, intel_dp, crtc_state); 2941 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2942 !is_trans_port_sync_mode(crtc_state)) 2943 intel_dp_stop_link_train(intel_dp, crtc_state); 2944 2945 intel_ddi_enable_fec(encoder, crtc_state); 2946 2947 if (!is_mst) { 2948 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2949 intel_dsc_dp_pps_write(encoder, crtc_state); 2950 } 2951 } 2952 2953 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2954 struct intel_encoder *encoder, 2955 const struct intel_crtc_state *crtc_state, 2956 const struct drm_connector_state *conn_state) 2957 { 2958 struct intel_display *display = to_intel_display(encoder); 2959 2960 if (HAS_DP20(display)) 2961 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2962 crtc_state); 2963 2964 /* Panel replay has to be enabled in sink dpcd before link training. */ 2965 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2966 2967 if (DISPLAY_VER(display) >= 14) 2968 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2969 else if (DISPLAY_VER(display) >= 12) 2970 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2971 else 2972 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2973 2974 /* MST will call a setting of MSA after an allocating of Virtual Channel 2975 * from MST encoder pre_enable callback. 2976 */ 2977 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2978 intel_ddi_set_dp_msa(crtc_state, conn_state); 2979 } 2980 2981 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2982 struct intel_encoder *encoder, 2983 const struct intel_crtc_state *crtc_state, 2984 const struct drm_connector_state *conn_state) 2985 { 2986 struct intel_display *display = to_intel_display(encoder); 2987 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2988 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2989 2990 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2991 intel_ddi_enable_clock(encoder, crtc_state); 2992 2993 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2994 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2995 dig_port->ddi_io_power_domain); 2996 2997 icl_program_mg_dp_mode(dig_port, crtc_state); 2998 2999 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3000 3001 dig_port->set_infoframes(encoder, 3002 crtc_state->has_infoframe, 3003 crtc_state, conn_state); 3004 } 3005 3006 /* 3007 * Note: Also called from the ->pre_enable of the first active MST stream 3008 * encoder on its primary encoder. 3009 * 3010 * When called from DP MST code: 3011 * 3012 * - conn_state will be NULL 3013 * 3014 * - encoder will be the primary encoder (i.e. mst->primary) 3015 * 3016 * - the main connector associated with this port won't be active or linked to a 3017 * crtc 3018 * 3019 * - crtc_state will be the state of the first stream to be activated on this 3020 * port, and it may not be the same stream that will be deactivated last, but 3021 * each stream should have a state that is identical when it comes to the DP 3022 * link parameters. 3023 */ 3024 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3025 struct intel_encoder *encoder, 3026 const struct intel_crtc_state *crtc_state, 3027 const struct drm_connector_state *conn_state) 3028 { 3029 struct intel_display *display = to_intel_display(state); 3030 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3031 enum pipe pipe = crtc->pipe; 3032 3033 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3034 3035 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3036 3037 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3038 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3039 conn_state); 3040 } else { 3041 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3042 3043 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3044 conn_state); 3045 3046 /* FIXME precompute everything properly */ 3047 /* FIXME how do we turn infoframes off again? */ 3048 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3049 dig_port->set_infoframes(encoder, 3050 crtc_state->has_infoframe, 3051 crtc_state, conn_state); 3052 } 3053 } 3054 3055 static void 3056 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3057 { 3058 struct intel_display *display = to_intel_display(encoder); 3059 enum port port = encoder->port; 3060 i915_reg_t reg; 3061 u32 clr_bits, wait_bits; 3062 3063 if (DISPLAY_VER(display) < 14) 3064 return; 3065 3066 if (DISPLAY_VER(display) >= 20) { 3067 reg = DDI_BUF_CTL(port); 3068 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3069 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3070 } else { 3071 reg = XELPDP_PORT_BUF_CTL1(display, port); 3072 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3073 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3074 } 3075 3076 intel_de_rmw(display, reg, clr_bits, 0); 3077 if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) 3078 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3079 port_name(port)); 3080 } 3081 3082 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3083 { 3084 struct intel_display *display = to_intel_display(encoder); 3085 enum port port = encoder->port; 3086 3087 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3088 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3089 3090 intel_wait_ddi_buf_active(encoder); 3091 } 3092 3093 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3094 const struct intel_crtc_state *crtc_state) 3095 { 3096 struct intel_display *display = to_intel_display(encoder); 3097 enum port port = encoder->port; 3098 3099 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3100 3101 if (DISPLAY_VER(display) >= 14) 3102 intel_wait_ddi_buf_idle(display, port); 3103 3104 mtl_ddi_disable_d2d(encoder); 3105 3106 if (intel_crtc_has_dp_encoder(crtc_state)) { 3107 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3108 DP_TP_CTL_ENABLE, 0); 3109 } 3110 3111 intel_ddi_disable_fec(encoder, crtc_state); 3112 3113 if (DISPLAY_VER(display) < 14) 3114 intel_wait_ddi_buf_idle(display, port); 3115 3116 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3117 } 3118 3119 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3120 struct intel_encoder *encoder, 3121 const struct intel_crtc_state *old_crtc_state, 3122 const struct drm_connector_state *old_conn_state) 3123 { 3124 struct intel_display *display = to_intel_display(encoder); 3125 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3126 struct intel_dp *intel_dp = &dig_port->dp; 3127 intel_wakeref_t wakeref; 3128 bool is_mst = intel_crtc_has_type(old_crtc_state, 3129 INTEL_OUTPUT_DP_MST); 3130 3131 if (!is_mst) 3132 intel_dp_set_infoframes(encoder, false, 3133 old_crtc_state, old_conn_state); 3134 3135 /* 3136 * Power down sink before disabling the port, otherwise we end 3137 * up getting interrupts from the sink on detecting link loss. 3138 */ 3139 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3140 3141 if (DISPLAY_VER(display) >= 12) { 3142 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3143 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3144 3145 intel_de_rmw(display, 3146 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3147 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3148 0); 3149 } 3150 } else { 3151 if (!is_mst) 3152 intel_ddi_disable_transcoder_clock(old_crtc_state); 3153 } 3154 3155 intel_ddi_buf_disable(encoder, old_crtc_state); 3156 3157 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3158 3159 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3160 3161 /* 3162 * From TGL spec: "If single stream or multi-stream master transcoder: 3163 * Configure Transcoder Clock select to direct no clock to the 3164 * transcoder" 3165 */ 3166 if (DISPLAY_VER(display) >= 12) 3167 intel_ddi_disable_transcoder_clock(old_crtc_state); 3168 3169 intel_pps_vdd_on(intel_dp); 3170 intel_pps_off(intel_dp); 3171 3172 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3173 3174 if (wakeref) 3175 intel_display_power_put(display, 3176 dig_port->ddi_io_power_domain, 3177 wakeref); 3178 3179 intel_ddi_disable_clock(encoder); 3180 3181 /* De-select Thunderbolt */ 3182 if (DISPLAY_VER(display) >= 14) 3183 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3184 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3185 } 3186 3187 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3188 struct intel_encoder *encoder, 3189 const struct intel_crtc_state *old_crtc_state, 3190 const struct drm_connector_state *old_conn_state) 3191 { 3192 struct intel_display *display = to_intel_display(encoder); 3193 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3194 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3195 intel_wakeref_t wakeref; 3196 3197 dig_port->set_infoframes(encoder, false, 3198 old_crtc_state, old_conn_state); 3199 3200 if (DISPLAY_VER(display) < 12) 3201 intel_ddi_disable_transcoder_clock(old_crtc_state); 3202 3203 intel_ddi_buf_disable(encoder, old_crtc_state); 3204 3205 if (DISPLAY_VER(display) >= 12) 3206 intel_ddi_disable_transcoder_clock(old_crtc_state); 3207 3208 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3209 if (wakeref) 3210 intel_display_power_put(display, 3211 dig_port->ddi_io_power_domain, 3212 wakeref); 3213 3214 intel_ddi_disable_clock(encoder); 3215 3216 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3217 } 3218 3219 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3220 struct intel_encoder *encoder, 3221 const struct intel_crtc_state *old_crtc_state, 3222 const struct drm_connector_state *old_conn_state) 3223 { 3224 struct intel_display *display = to_intel_display(encoder); 3225 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3226 struct intel_crtc *pipe_crtc; 3227 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3228 int i; 3229 3230 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3231 const struct intel_crtc_state *old_pipe_crtc_state = 3232 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3233 3234 intel_crtc_vblank_off(old_pipe_crtc_state); 3235 } 3236 3237 intel_disable_transcoder(old_crtc_state); 3238 3239 /* 128b/132b SST */ 3240 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3241 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3242 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3243 3244 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3245 3246 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3247 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3248 3249 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3250 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3251 } 3252 3253 intel_vrr_transcoder_disable(old_crtc_state); 3254 3255 intel_ddi_disable_transcoder_func(old_crtc_state); 3256 3257 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3258 const struct intel_crtc_state *old_pipe_crtc_state = 3259 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3260 3261 intel_dsc_disable(old_pipe_crtc_state); 3262 3263 if (DISPLAY_VER(display) >= 9) 3264 skl_scaler_disable(old_pipe_crtc_state); 3265 else 3266 ilk_pfit_disable(old_pipe_crtc_state); 3267 } 3268 } 3269 3270 /* 3271 * Note: Also called from the ->post_disable of the last active MST stream 3272 * encoder on its primary encoder. See also the comment for 3273 * intel_ddi_pre_enable(). 3274 */ 3275 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3276 struct intel_encoder *encoder, 3277 const struct intel_crtc_state *old_crtc_state, 3278 const struct drm_connector_state *old_conn_state) 3279 { 3280 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3281 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3282 old_conn_state); 3283 3284 /* 3285 * When called from DP MST code: 3286 * - old_conn_state will be NULL 3287 * - encoder will be the main encoder (ie. mst->primary) 3288 * - the main connector associated with this port 3289 * won't be active or linked to a crtc 3290 * - old_crtc_state will be the state of the last stream to 3291 * be deactivated on this port, and it may not be the same 3292 * stream that was activated last, but each stream 3293 * should have a state that is identical when it comes to 3294 * the DP link parameters 3295 */ 3296 3297 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3298 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3299 old_conn_state); 3300 else 3301 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3302 old_conn_state); 3303 } 3304 3305 /* 3306 * Note: Also called from the ->post_pll_disable of the last active MST stream 3307 * encoder on its primary encoder. See also the comment for 3308 * intel_ddi_pre_enable(). 3309 */ 3310 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3311 struct intel_encoder *encoder, 3312 const struct intel_crtc_state *old_crtc_state, 3313 const struct drm_connector_state *old_conn_state) 3314 { 3315 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3316 3317 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3318 3319 if (intel_encoder_is_tc(encoder)) 3320 intel_tc_port_put_link(dig_port); 3321 } 3322 3323 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3324 struct intel_encoder *encoder, 3325 const struct intel_crtc_state *crtc_state) 3326 { 3327 const struct drm_connector_state *conn_state; 3328 struct drm_connector *conn; 3329 int i; 3330 3331 if (!crtc_state->sync_mode_slaves_mask) 3332 return; 3333 3334 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3335 struct intel_encoder *slave_encoder = 3336 to_intel_encoder(conn_state->best_encoder); 3337 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3338 const struct intel_crtc_state *slave_crtc_state; 3339 3340 if (!slave_crtc) 3341 continue; 3342 3343 slave_crtc_state = 3344 intel_atomic_get_new_crtc_state(state, slave_crtc); 3345 3346 if (slave_crtc_state->master_transcoder != 3347 crtc_state->cpu_transcoder) 3348 continue; 3349 3350 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3351 slave_crtc_state); 3352 } 3353 3354 usleep_range(200, 400); 3355 3356 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3357 crtc_state); 3358 } 3359 3360 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3361 struct intel_encoder *encoder, 3362 const struct intel_crtc_state *crtc_state, 3363 const struct drm_connector_state *conn_state) 3364 { 3365 struct intel_display *display = to_intel_display(encoder); 3366 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3367 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3368 enum port port = encoder->port; 3369 3370 if (port == PORT_A && DISPLAY_VER(display) < 9) 3371 intel_dp_stop_link_train(intel_dp, crtc_state); 3372 3373 drm_connector_update_privacy_screen(conn_state); 3374 intel_edp_backlight_on(crtc_state, conn_state); 3375 3376 intel_panel_prepare(crtc_state, conn_state); 3377 3378 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3379 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3380 3381 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3382 } 3383 3384 static i915_reg_t 3385 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3386 { 3387 static const enum transcoder trans[] = { 3388 [PORT_A] = TRANSCODER_EDP, 3389 [PORT_B] = TRANSCODER_A, 3390 [PORT_C] = TRANSCODER_B, 3391 [PORT_D] = TRANSCODER_C, 3392 [PORT_E] = TRANSCODER_A, 3393 }; 3394 3395 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3396 3397 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3398 port = PORT_A; 3399 3400 return CHICKEN_TRANS(display, trans[port]); 3401 } 3402 3403 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3404 struct intel_encoder *encoder, 3405 const struct intel_crtc_state *crtc_state, 3406 const struct drm_connector_state *conn_state) 3407 { 3408 struct intel_display *display = to_intel_display(encoder); 3409 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3410 struct drm_connector *connector = conn_state->connector; 3411 enum port port = encoder->port; 3412 u32 buf_ctl = 0; 3413 3414 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3415 crtc_state->hdmi_high_tmds_clock_ratio, 3416 crtc_state->hdmi_scrambling)) 3417 drm_dbg_kms(display->drm, 3418 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3419 connector->base.id, connector->name); 3420 3421 if (has_buf_trans_select(display)) 3422 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3423 3424 /* e. Enable D2D Link for C10/C20 Phy */ 3425 mtl_ddi_enable_d2d(encoder); 3426 3427 encoder->set_signal_levels(encoder, crtc_state); 3428 3429 /* Display WA #1143: skl,kbl,cfl */ 3430 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3431 /* 3432 * For some reason these chicken bits have been 3433 * stuffed into a transcoder register, event though 3434 * the bits affect a specific DDI port rather than 3435 * a specific transcoder. 3436 */ 3437 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3438 u32 val; 3439 3440 val = intel_de_read(display, reg); 3441 3442 if (port == PORT_E) 3443 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3444 DDIE_TRAINING_OVERRIDE_VALUE; 3445 else 3446 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3447 DDI_TRAINING_OVERRIDE_VALUE; 3448 3449 intel_de_write(display, reg, val); 3450 intel_de_posting_read(display, reg); 3451 3452 udelay(1); 3453 3454 if (port == PORT_E) 3455 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3456 DDIE_TRAINING_OVERRIDE_VALUE); 3457 else 3458 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3459 DDI_TRAINING_OVERRIDE_VALUE); 3460 3461 intel_de_write(display, reg, val); 3462 } 3463 3464 intel_ddi_power_up_lanes(encoder, crtc_state); 3465 3466 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3467 * are ignored so nothing special needs to be done besides 3468 * enabling the port. 3469 * 3470 * On ADL_P the PHY link rate and lane count must be programmed but 3471 * these are both 0 for HDMI. 3472 * 3473 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3474 * is filled with lane count, already set in the crtc_state. 3475 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3476 */ 3477 if (dig_port->lane_reversal) 3478 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3479 if (dig_port->ddi_a_4_lanes) 3480 buf_ctl |= DDI_A_4_LANES; 3481 3482 if (DISPLAY_VER(display) >= 14) { 3483 u32 port_buf = 0; 3484 3485 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3486 3487 if (dig_port->lane_reversal) 3488 port_buf |= XELPDP_PORT_REVERSAL; 3489 3490 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3491 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3492 3493 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3494 3495 if (DISPLAY_VER(display) >= 20) 3496 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3497 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3498 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3499 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3500 } 3501 3502 intel_ddi_buf_enable(encoder, buf_ctl); 3503 } 3504 3505 static void intel_ddi_enable(struct intel_atomic_state *state, 3506 struct intel_encoder *encoder, 3507 const struct intel_crtc_state *crtc_state, 3508 const struct drm_connector_state *conn_state) 3509 { 3510 struct intel_display *display = to_intel_display(encoder); 3511 struct intel_crtc *pipe_crtc; 3512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3513 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3514 int i; 3515 3516 /* 128b/132b SST */ 3517 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3518 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3519 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3520 3521 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3522 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3523 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3524 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3525 } 3526 3527 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3528 3529 intel_vrr_transcoder_enable(crtc_state); 3530 3531 /* 128b/132b SST */ 3532 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3533 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3534 3535 intel_ddi_clear_act_sent(encoder, crtc_state); 3536 3537 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3538 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3539 3540 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3541 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3542 } 3543 3544 intel_enable_transcoder(crtc_state); 3545 3546 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3547 3548 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3549 const struct intel_crtc_state *pipe_crtc_state = 3550 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3551 3552 intel_crtc_vblank_on(pipe_crtc_state); 3553 } 3554 3555 if (is_hdmi) 3556 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3557 else 3558 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3559 3560 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3561 3562 } 3563 3564 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3565 struct intel_encoder *encoder, 3566 const struct intel_crtc_state *old_crtc_state, 3567 const struct drm_connector_state *old_conn_state) 3568 { 3569 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3570 struct intel_connector *connector = 3571 to_intel_connector(old_conn_state->connector); 3572 3573 intel_dp->link.active = false; 3574 3575 intel_panel_unprepare(old_conn_state); 3576 intel_psr_disable(intel_dp, old_crtc_state); 3577 intel_alpm_disable(intel_dp); 3578 intel_edp_backlight_off(old_conn_state); 3579 /* Disable the decompression in DP Sink */ 3580 intel_dp_sink_disable_decompression(state, 3581 connector, old_crtc_state); 3582 /* Disable Ignore_MSA bit in DP Sink */ 3583 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3584 false); 3585 } 3586 3587 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3588 struct intel_encoder *encoder, 3589 const struct intel_crtc_state *old_crtc_state, 3590 const struct drm_connector_state *old_conn_state) 3591 { 3592 struct intel_display *display = to_intel_display(encoder); 3593 struct drm_connector *connector = old_conn_state->connector; 3594 3595 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3596 false, false)) 3597 drm_dbg_kms(display->drm, 3598 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3599 connector->base.id, connector->name); 3600 } 3601 3602 static void intel_ddi_disable(struct intel_atomic_state *state, 3603 struct intel_encoder *encoder, 3604 const struct intel_crtc_state *old_crtc_state, 3605 const struct drm_connector_state *old_conn_state) 3606 { 3607 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3608 3609 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3610 3611 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3612 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3613 old_conn_state); 3614 else 3615 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3616 old_conn_state); 3617 } 3618 3619 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3620 struct intel_encoder *encoder, 3621 const struct intel_crtc_state *crtc_state, 3622 const struct drm_connector_state *conn_state) 3623 { 3624 intel_ddi_set_dp_msa(crtc_state, conn_state); 3625 3626 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3627 3628 intel_backlight_update(state, encoder, crtc_state, conn_state); 3629 drm_connector_update_privacy_screen(conn_state); 3630 } 3631 3632 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3633 const struct intel_crtc_state *crtc_state, 3634 const struct drm_connector_state *conn_state) 3635 { 3636 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3637 } 3638 3639 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3640 struct intel_encoder *encoder, 3641 const struct intel_crtc_state *crtc_state, 3642 const struct drm_connector_state *conn_state) 3643 { 3644 3645 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3646 !intel_encoder_is_mst(encoder)) 3647 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3648 conn_state); 3649 3650 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3651 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3652 conn_state); 3653 3654 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3655 } 3656 3657 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3658 struct intel_encoder *encoder, 3659 struct intel_crtc *crtc) 3660 { 3661 struct intel_display *display = to_intel_display(encoder); 3662 const struct intel_crtc_state *crtc_state = 3663 intel_atomic_get_new_crtc_state(state, crtc); 3664 struct intel_crtc *pipe_crtc; 3665 3666 /* FIXME: Add MTL pll_mgr */ 3667 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3668 return; 3669 3670 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3671 intel_crtc_joined_pipe_mask(crtc_state)) 3672 intel_dpll_update_active(state, pipe_crtc, encoder); 3673 } 3674 3675 /* 3676 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3677 * encoder on its primary encoder. See also the comment for 3678 * intel_ddi_pre_enable(). 3679 */ 3680 static void 3681 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3682 struct intel_encoder *encoder, 3683 const struct intel_crtc_state *crtc_state, 3684 const struct drm_connector_state *conn_state) 3685 { 3686 struct intel_display *display = to_intel_display(encoder); 3687 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3688 bool is_tc_port = intel_encoder_is_tc(encoder); 3689 3690 if (is_tc_port) { 3691 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3692 3693 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3694 intel_ddi_update_active_dpll(state, encoder, crtc); 3695 } 3696 3697 main_link_aux_power_domain_get(dig_port, crtc_state); 3698 3699 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3700 /* 3701 * Program the lane count for static/dynamic connections on 3702 * Type-C ports. Skip this step for TBT. 3703 */ 3704 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3705 else if (display->platform.geminilake || display->platform.broxton) 3706 bxt_dpio_phy_set_lane_optim_mask(encoder, 3707 crtc_state->lane_lat_optim_mask); 3708 } 3709 3710 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3711 { 3712 struct intel_display *display = to_intel_display(encoder); 3713 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3714 int ln; 3715 3716 for (ln = 0; ln < 2; ln++) 3717 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3718 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3719 } 3720 3721 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3722 const struct intel_crtc_state *crtc_state) 3723 { 3724 struct intel_display *display = to_intel_display(crtc_state); 3725 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3726 struct intel_encoder *encoder = &dig_port->base; 3727 u32 dp_tp_ctl; 3728 3729 /* 3730 * TODO: To train with only a different voltage swing entry is not 3731 * necessary disable and enable port 3732 */ 3733 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3734 3735 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3736 3737 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3738 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3739 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3740 intel_dp_is_uhbr(crtc_state)) { 3741 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3742 } else { 3743 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3744 if (crtc_state->enhanced_framing) 3745 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3746 } 3747 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3748 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3749 3750 /* 6.f Enable D2D Link */ 3751 mtl_ddi_enable_d2d(encoder); 3752 3753 /* 6.g Configure voltage swing and related IO settings */ 3754 encoder->set_signal_levels(encoder, crtc_state); 3755 3756 /* 6.h Configure PORT_BUF_CTL1 */ 3757 mtl_port_buf_ctl_program(encoder, crtc_state); 3758 3759 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3760 if (DISPLAY_VER(display) >= 20) 3761 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3762 3763 intel_ddi_buf_enable(encoder, intel_dp->DP); 3764 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3765 3766 /* 3767 * 6.k If AUX-Less ALPM is going to be enabled: 3768 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3769 */ 3770 intel_alpm_port_configure(intel_dp, crtc_state); 3771 3772 /* 3773 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3774 * register 3775 */ 3776 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3777 } 3778 3779 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3780 const struct intel_crtc_state *crtc_state) 3781 { 3782 struct intel_display *display = to_intel_display(intel_dp); 3783 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3784 struct intel_encoder *encoder = &dig_port->base; 3785 u32 dp_tp_ctl; 3786 3787 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3788 3789 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3790 3791 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3792 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3793 intel_dp_is_uhbr(crtc_state)) { 3794 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3795 } else { 3796 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3797 if (crtc_state->enhanced_framing) 3798 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3799 } 3800 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3801 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3802 3803 if (display->platform.alderlake_p && 3804 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3805 adlp_tbt_to_dp_alt_switch_wa(encoder); 3806 3807 intel_ddi_buf_enable(encoder, intel_dp->DP); 3808 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3809 } 3810 3811 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3812 const struct intel_crtc_state *crtc_state, 3813 u8 dp_train_pat) 3814 { 3815 struct intel_display *display = to_intel_display(intel_dp); 3816 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3817 u32 temp; 3818 3819 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3820 3821 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3822 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3823 case DP_TRAINING_PATTERN_DISABLE: 3824 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3825 break; 3826 case DP_TRAINING_PATTERN_1: 3827 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3828 break; 3829 case DP_TRAINING_PATTERN_2: 3830 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3831 break; 3832 case DP_TRAINING_PATTERN_3: 3833 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3834 break; 3835 case DP_TRAINING_PATTERN_4: 3836 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3837 break; 3838 } 3839 3840 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3841 } 3842 3843 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3844 const struct intel_crtc_state *crtc_state) 3845 { 3846 struct intel_display *display = to_intel_display(intel_dp); 3847 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3848 enum port port = encoder->port; 3849 3850 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3851 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3852 3853 /* 3854 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3855 * reason we need to set idle transmission mode is to work around a HW 3856 * issue where we enable the pipe while not in idle link-training mode. 3857 * In this case there is requirement to wait for a minimum number of 3858 * idle patterns to be sent. 3859 */ 3860 if (port == PORT_A && DISPLAY_VER(display) < 12) 3861 return; 3862 3863 if (intel_de_wait_for_set(display, 3864 dp_tp_status_reg(encoder, crtc_state), 3865 DP_TP_STATUS_IDLE_DONE, 2)) 3866 drm_err(display->drm, 3867 "Timed out waiting for DP idle patterns\n"); 3868 } 3869 3870 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3871 enum transcoder cpu_transcoder) 3872 { 3873 if (cpu_transcoder == TRANSCODER_EDP) 3874 return false; 3875 3876 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3877 return false; 3878 3879 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3880 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3881 } 3882 3883 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3884 { 3885 if (crtc_state->port_clock > 594000) 3886 return 2; 3887 else 3888 return 0; 3889 } 3890 3891 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3892 { 3893 if (crtc_state->port_clock > 594000) 3894 return 3; 3895 else 3896 return 0; 3897 } 3898 3899 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3900 { 3901 if (crtc_state->port_clock > 594000) 3902 return 1; 3903 else 3904 return 0; 3905 } 3906 3907 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3908 { 3909 struct intel_display *display = to_intel_display(crtc_state); 3910 3911 if (DISPLAY_VER(display) >= 14) 3912 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3913 else if (DISPLAY_VER(display) >= 12) 3914 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3915 else if (display->platform.jasperlake || display->platform.elkhartlake) 3916 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3917 else if (DISPLAY_VER(display) >= 11) 3918 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3919 } 3920 3921 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3922 enum transcoder cpu_transcoder) 3923 { 3924 u32 master_select; 3925 3926 if (DISPLAY_VER(display) >= 11) { 3927 u32 ctl2 = intel_de_read(display, 3928 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3929 3930 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3931 return INVALID_TRANSCODER; 3932 3933 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3934 } else { 3935 u32 ctl = intel_de_read(display, 3936 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3937 3938 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3939 return INVALID_TRANSCODER; 3940 3941 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3942 } 3943 3944 if (master_select == 0) 3945 return TRANSCODER_EDP; 3946 else 3947 return master_select - 1; 3948 } 3949 3950 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3951 { 3952 struct intel_display *display = to_intel_display(crtc_state); 3953 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3954 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3955 enum transcoder cpu_transcoder; 3956 3957 crtc_state->master_transcoder = 3958 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3959 3960 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3961 enum intel_display_power_domain power_domain; 3962 intel_wakeref_t trans_wakeref; 3963 3964 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3965 trans_wakeref = intel_display_power_get_if_enabled(display, 3966 power_domain); 3967 3968 if (!trans_wakeref) 3969 continue; 3970 3971 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3972 crtc_state->cpu_transcoder) 3973 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3974 3975 intel_display_power_put(display, power_domain, trans_wakeref); 3976 } 3977 3978 drm_WARN_ON(display->drm, 3979 crtc_state->master_transcoder != INVALID_TRANSCODER && 3980 crtc_state->sync_mode_slaves_mask); 3981 } 3982 3983 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3984 struct intel_crtc_state *crtc_state, 3985 u32 ddi_func_ctl) 3986 { 3987 struct intel_display *display = to_intel_display(encoder); 3988 3989 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3990 if (DISPLAY_VER(display) >= 14) 3991 crtc_state->lane_count = 3992 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3993 else 3994 crtc_state->lane_count = 4; 3995 } 3996 3997 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3998 struct intel_crtc_state *crtc_state, 3999 u32 ddi_func_ctl) 4000 { 4001 crtc_state->has_hdmi_sink = true; 4002 4003 crtc_state->infoframes.enable |= 4004 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4005 4006 if (crtc_state->infoframes.enable) 4007 crtc_state->has_infoframe = true; 4008 4009 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4010 crtc_state->hdmi_scrambling = true; 4011 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4012 crtc_state->hdmi_high_tmds_clock_ratio = true; 4013 4014 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4015 } 4016 4017 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4018 struct intel_crtc_state *crtc_state, 4019 u32 ddi_func_ctl) 4020 { 4021 struct intel_display *display = to_intel_display(encoder); 4022 4023 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4024 crtc_state->enhanced_framing = 4025 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4026 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4027 } 4028 4029 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4030 struct intel_crtc_state *crtc_state, 4031 u32 ddi_func_ctl) 4032 { 4033 struct intel_display *display = to_intel_display(encoder); 4034 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4035 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4036 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4037 4038 if (encoder->type == INTEL_OUTPUT_EDP) 4039 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4040 else 4041 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4042 crtc_state->lane_count = 4043 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4044 4045 if (DISPLAY_VER(display) >= 12 && 4046 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4047 crtc_state->mst_master_transcoder = 4048 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4049 4050 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4051 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4052 4053 crtc_state->enhanced_framing = 4054 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4055 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4056 4057 if (DISPLAY_VER(display) >= 11) 4058 crtc_state->fec_enable = 4059 intel_de_read(display, 4060 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4061 4062 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4063 crtc_state->infoframes.enable |= 4064 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4065 else 4066 crtc_state->infoframes.enable |= 4067 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4068 } 4069 4070 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4071 struct intel_crtc_state *crtc_state, 4072 u32 ddi_func_ctl) 4073 { 4074 struct intel_display *display = to_intel_display(encoder); 4075 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4076 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4077 4078 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4079 crtc_state->lane_count = 4080 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4081 4082 if (DISPLAY_VER(display) >= 12) 4083 crtc_state->mst_master_transcoder = 4084 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4085 4086 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4087 4088 if (DISPLAY_VER(display) >= 11) 4089 crtc_state->fec_enable = 4090 intel_de_read(display, 4091 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4092 4093 crtc_state->infoframes.enable |= 4094 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4095 } 4096 4097 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4098 struct intel_crtc_state *pipe_config) 4099 { 4100 struct intel_display *display = to_intel_display(encoder); 4101 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4102 u32 ddi_func_ctl, ddi_mode, flags = 0; 4103 4104 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4105 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4106 flags |= DRM_MODE_FLAG_PHSYNC; 4107 else 4108 flags |= DRM_MODE_FLAG_NHSYNC; 4109 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4110 flags |= DRM_MODE_FLAG_PVSYNC; 4111 else 4112 flags |= DRM_MODE_FLAG_NVSYNC; 4113 4114 pipe_config->hw.adjusted_mode.flags |= flags; 4115 4116 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4117 case TRANS_DDI_BPC_6: 4118 pipe_config->pipe_bpp = 18; 4119 break; 4120 case TRANS_DDI_BPC_8: 4121 pipe_config->pipe_bpp = 24; 4122 break; 4123 case TRANS_DDI_BPC_10: 4124 pipe_config->pipe_bpp = 30; 4125 break; 4126 case TRANS_DDI_BPC_12: 4127 pipe_config->pipe_bpp = 36; 4128 break; 4129 default: 4130 break; 4131 } 4132 4133 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4134 4135 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4136 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4137 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4138 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4139 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4140 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4141 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4142 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4143 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4144 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4145 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4146 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4147 4148 /* 4149 * If this is true, we know we're being called from mst stream 4150 * encoder's ->get_config(). 4151 */ 4152 if (intel_dp_mst_active_streams(intel_dp)) 4153 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4154 else 4155 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4156 } 4157 } 4158 4159 /* 4160 * Note: Also called from the ->get_config of the MST stream encoders on their 4161 * primary encoder, via the platform specific hooks here. See also the comment 4162 * for intel_ddi_pre_enable(). 4163 */ 4164 static void intel_ddi_get_config(struct intel_encoder *encoder, 4165 struct intel_crtc_state *pipe_config) 4166 { 4167 struct intel_display *display = to_intel_display(encoder); 4168 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4169 4170 /* XXX: DSI transcoder paranoia */ 4171 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4172 return; 4173 4174 intel_ddi_read_func_ctl(encoder, pipe_config); 4175 4176 intel_ddi_mso_get_config(encoder, pipe_config); 4177 4178 pipe_config->has_audio = 4179 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4180 4181 if (encoder->type == INTEL_OUTPUT_EDP) 4182 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4183 4184 ddi_dotclock_get(pipe_config); 4185 4186 if (display->platform.geminilake || display->platform.broxton) 4187 pipe_config->lane_lat_optim_mask = 4188 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4189 4190 intel_ddi_compute_min_voltage_level(pipe_config); 4191 4192 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4193 4194 intel_read_infoframe(encoder, pipe_config, 4195 HDMI_INFOFRAME_TYPE_AVI, 4196 &pipe_config->infoframes.avi); 4197 intel_read_infoframe(encoder, pipe_config, 4198 HDMI_INFOFRAME_TYPE_SPD, 4199 &pipe_config->infoframes.spd); 4200 intel_read_infoframe(encoder, pipe_config, 4201 HDMI_INFOFRAME_TYPE_VENDOR, 4202 &pipe_config->infoframes.hdmi); 4203 intel_read_infoframe(encoder, pipe_config, 4204 HDMI_INFOFRAME_TYPE_DRM, 4205 &pipe_config->infoframes.drm); 4206 4207 if (DISPLAY_VER(display) >= 8) 4208 bdw_get_trans_port_sync_config(pipe_config); 4209 4210 intel_psr_get_config(encoder, pipe_config); 4211 4212 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4213 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4214 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4215 4216 intel_audio_codec_get_config(encoder, pipe_config); 4217 } 4218 4219 void intel_ddi_get_clock(struct intel_encoder *encoder, 4220 struct intel_crtc_state *crtc_state, 4221 struct intel_dpll *pll) 4222 { 4223 struct intel_display *display = to_intel_display(encoder); 4224 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4225 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4226 bool pll_active; 4227 4228 if (drm_WARN_ON(display->drm, !pll)) 4229 return; 4230 4231 port_dpll->pll = pll; 4232 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4233 drm_WARN_ON(display->drm, !pll_active); 4234 4235 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4236 4237 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4238 &crtc_state->dpll_hw_state); 4239 } 4240 4241 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4242 struct intel_crtc_state *crtc_state) 4243 { 4244 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4245 4246 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4247 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4248 else 4249 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4250 4251 intel_ddi_get_config(encoder, crtc_state); 4252 } 4253 4254 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4255 struct intel_crtc_state *crtc_state) 4256 { 4257 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4258 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4259 4260 intel_ddi_get_config(encoder, crtc_state); 4261 } 4262 4263 static void adls_ddi_get_config(struct intel_encoder *encoder, 4264 struct intel_crtc_state *crtc_state) 4265 { 4266 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4267 intel_ddi_get_config(encoder, crtc_state); 4268 } 4269 4270 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4271 struct intel_crtc_state *crtc_state) 4272 { 4273 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4274 intel_ddi_get_config(encoder, crtc_state); 4275 } 4276 4277 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4278 struct intel_crtc_state *crtc_state) 4279 { 4280 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4281 intel_ddi_get_config(encoder, crtc_state); 4282 } 4283 4284 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4285 struct intel_crtc_state *crtc_state) 4286 { 4287 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4288 intel_ddi_get_config(encoder, crtc_state); 4289 } 4290 4291 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4292 { 4293 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4294 } 4295 4296 static enum icl_port_dpll_id 4297 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4298 const struct intel_crtc_state *crtc_state) 4299 { 4300 struct intel_display *display = to_intel_display(encoder); 4301 const struct intel_dpll *pll = crtc_state->intel_dpll; 4302 4303 if (drm_WARN_ON(display->drm, !pll)) 4304 return ICL_PORT_DPLL_DEFAULT; 4305 4306 if (icl_ddi_tc_pll_is_tbt(pll)) 4307 return ICL_PORT_DPLL_DEFAULT; 4308 else 4309 return ICL_PORT_DPLL_MG_PHY; 4310 } 4311 4312 enum icl_port_dpll_id 4313 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4314 const struct intel_crtc_state *crtc_state) 4315 { 4316 if (!encoder->port_pll_type) 4317 return ICL_PORT_DPLL_DEFAULT; 4318 4319 return encoder->port_pll_type(encoder, crtc_state); 4320 } 4321 4322 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4323 struct intel_crtc_state *crtc_state, 4324 struct intel_dpll *pll) 4325 { 4326 struct intel_display *display = to_intel_display(encoder); 4327 enum icl_port_dpll_id port_dpll_id; 4328 struct icl_port_dpll *port_dpll; 4329 bool pll_active; 4330 4331 if (drm_WARN_ON(display->drm, !pll)) 4332 return; 4333 4334 if (icl_ddi_tc_pll_is_tbt(pll)) 4335 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4336 else 4337 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4338 4339 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4340 4341 port_dpll->pll = pll; 4342 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4343 drm_WARN_ON(display->drm, !pll_active); 4344 4345 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4346 4347 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4348 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4349 else 4350 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4351 &crtc_state->dpll_hw_state); 4352 } 4353 4354 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4355 struct intel_crtc_state *crtc_state) 4356 { 4357 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4358 intel_ddi_get_config(encoder, crtc_state); 4359 } 4360 4361 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4362 struct intel_crtc_state *crtc_state) 4363 { 4364 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4365 intel_ddi_get_config(encoder, crtc_state); 4366 } 4367 4368 static void skl_ddi_get_config(struct intel_encoder *encoder, 4369 struct intel_crtc_state *crtc_state) 4370 { 4371 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4372 intel_ddi_get_config(encoder, crtc_state); 4373 } 4374 4375 void hsw_ddi_get_config(struct intel_encoder *encoder, 4376 struct intel_crtc_state *crtc_state) 4377 { 4378 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4379 intel_ddi_get_config(encoder, crtc_state); 4380 } 4381 4382 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4383 const struct intel_crtc_state *crtc_state) 4384 { 4385 if (intel_encoder_is_tc(encoder)) 4386 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4387 crtc_state); 4388 4389 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4390 (!crtc_state && intel_encoder_is_dp(encoder))) 4391 intel_dp_sync_state(encoder, crtc_state); 4392 } 4393 4394 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4395 struct intel_crtc_state *crtc_state) 4396 { 4397 struct intel_display *display = to_intel_display(encoder); 4398 bool fastset = true; 4399 4400 if (intel_encoder_is_tc(encoder)) { 4401 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4402 encoder->base.base.id, encoder->base.name); 4403 crtc_state->uapi.mode_changed = true; 4404 fastset = false; 4405 } 4406 4407 if (intel_crtc_has_dp_encoder(crtc_state) && 4408 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4409 fastset = false; 4410 4411 return fastset; 4412 } 4413 4414 static enum intel_output_type 4415 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4416 struct intel_crtc_state *crtc_state, 4417 struct drm_connector_state *conn_state) 4418 { 4419 switch (conn_state->connector->connector_type) { 4420 case DRM_MODE_CONNECTOR_HDMIA: 4421 return INTEL_OUTPUT_HDMI; 4422 case DRM_MODE_CONNECTOR_eDP: 4423 return INTEL_OUTPUT_EDP; 4424 case DRM_MODE_CONNECTOR_DisplayPort: 4425 return INTEL_OUTPUT_DP; 4426 default: 4427 MISSING_CASE(conn_state->connector->connector_type); 4428 return INTEL_OUTPUT_UNUSED; 4429 } 4430 } 4431 4432 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4433 struct intel_crtc_state *pipe_config, 4434 struct drm_connector_state *conn_state) 4435 { 4436 struct intel_display *display = to_intel_display(encoder); 4437 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4438 enum port port = encoder->port; 4439 int ret; 4440 4441 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4442 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4443 4444 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4445 pipe_config->has_hdmi_sink = 4446 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4447 4448 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4449 } else { 4450 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4451 } 4452 4453 if (ret) 4454 return ret; 4455 4456 if (display->platform.haswell && crtc->pipe == PIPE_A && 4457 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4458 pipe_config->pch_pfit.force_thru = 4459 pipe_config->pch_pfit.enabled || 4460 pipe_config->crc_enabled; 4461 4462 if (display->platform.geminilake || display->platform.broxton) 4463 pipe_config->lane_lat_optim_mask = 4464 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4465 4466 intel_ddi_compute_min_voltage_level(pipe_config); 4467 4468 return 0; 4469 } 4470 4471 static bool mode_equal(const struct drm_display_mode *mode1, 4472 const struct drm_display_mode *mode2) 4473 { 4474 return drm_mode_match(mode1, mode2, 4475 DRM_MODE_MATCH_TIMINGS | 4476 DRM_MODE_MATCH_FLAGS | 4477 DRM_MODE_MATCH_3D_FLAGS) && 4478 mode1->clock == mode2->clock; /* we want an exact match */ 4479 } 4480 4481 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4482 const struct intel_link_m_n *m_n_2) 4483 { 4484 return m_n_1->tu == m_n_2->tu && 4485 m_n_1->data_m == m_n_2->data_m && 4486 m_n_1->data_n == m_n_2->data_n && 4487 m_n_1->link_m == m_n_2->link_m && 4488 m_n_1->link_n == m_n_2->link_n; 4489 } 4490 4491 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4492 const struct intel_crtc_state *crtc_state2) 4493 { 4494 /* 4495 * FIXME the modeset sequence is currently wrong and 4496 * can't deal with joiner + port sync at the same time. 4497 */ 4498 return crtc_state1->hw.active && crtc_state2->hw.active && 4499 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4500 crtc_state1->output_types == crtc_state2->output_types && 4501 crtc_state1->output_format == crtc_state2->output_format && 4502 crtc_state1->lane_count == crtc_state2->lane_count && 4503 crtc_state1->port_clock == crtc_state2->port_clock && 4504 mode_equal(&crtc_state1->hw.adjusted_mode, 4505 &crtc_state2->hw.adjusted_mode) && 4506 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4507 } 4508 4509 static u8 4510 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4511 int tile_group_id) 4512 { 4513 struct intel_display *display = to_intel_display(ref_crtc_state); 4514 struct drm_connector *connector; 4515 const struct drm_connector_state *conn_state; 4516 struct intel_atomic_state *state = 4517 to_intel_atomic_state(ref_crtc_state->uapi.state); 4518 u8 transcoders = 0; 4519 int i; 4520 4521 /* 4522 * We don't enable port sync on BDW due to missing w/as and 4523 * due to not having adjusted the modeset sequence appropriately. 4524 */ 4525 if (DISPLAY_VER(display) < 9) 4526 return 0; 4527 4528 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4529 return 0; 4530 4531 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4532 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4533 const struct intel_crtc_state *crtc_state; 4534 4535 if (!crtc) 4536 continue; 4537 4538 if (!connector->has_tile || 4539 connector->tile_group->id != 4540 tile_group_id) 4541 continue; 4542 crtc_state = intel_atomic_get_new_crtc_state(state, 4543 crtc); 4544 if (!crtcs_port_sync_compatible(ref_crtc_state, 4545 crtc_state)) 4546 continue; 4547 transcoders |= BIT(crtc_state->cpu_transcoder); 4548 } 4549 4550 return transcoders; 4551 } 4552 4553 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4554 struct intel_crtc_state *crtc_state, 4555 struct drm_connector_state *conn_state) 4556 { 4557 struct intel_display *display = to_intel_display(encoder); 4558 struct drm_connector *connector = conn_state->connector; 4559 u8 port_sync_transcoders = 0; 4560 4561 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4562 encoder->base.base.id, encoder->base.name, 4563 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4564 4565 if (connector->has_tile) 4566 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4567 connector->tile_group->id); 4568 4569 /* 4570 * EDP Transcoders cannot be ensalved 4571 * make them a master always when present 4572 */ 4573 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4574 crtc_state->master_transcoder = TRANSCODER_EDP; 4575 else 4576 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4577 4578 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4579 crtc_state->master_transcoder = INVALID_TRANSCODER; 4580 crtc_state->sync_mode_slaves_mask = 4581 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4582 } 4583 4584 return 0; 4585 } 4586 4587 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4588 { 4589 struct intel_display *display = to_intel_display(encoder->dev); 4590 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4591 4592 intel_dp_encoder_flush_work(encoder); 4593 if (intel_encoder_is_tc(&dig_port->base)) 4594 intel_tc_port_cleanup(dig_port); 4595 intel_display_power_flush_work(display); 4596 4597 drm_encoder_cleanup(encoder); 4598 kfree(dig_port->hdcp.port_data.streams); 4599 kfree(dig_port); 4600 } 4601 4602 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4603 { 4604 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4605 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4606 4607 intel_dp->reset_link_params = true; 4608 intel_dp_invalidate_source_oui(intel_dp); 4609 4610 intel_pps_encoder_reset(intel_dp); 4611 4612 if (intel_encoder_is_tc(&dig_port->base)) 4613 intel_tc_port_init_mode(dig_port); 4614 } 4615 4616 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4617 { 4618 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4619 4620 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4621 4622 return 0; 4623 } 4624 4625 static const struct drm_encoder_funcs intel_ddi_funcs = { 4626 .reset = intel_ddi_encoder_reset, 4627 .destroy = intel_ddi_encoder_destroy, 4628 .late_register = intel_ddi_encoder_late_register, 4629 }; 4630 4631 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4632 { 4633 struct intel_display *display = to_intel_display(dig_port); 4634 struct intel_connector *connector; 4635 enum port port = dig_port->base.port; 4636 4637 connector = intel_connector_alloc(); 4638 if (!connector) 4639 return -ENOMEM; 4640 4641 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4642 if (DISPLAY_VER(display) >= 14) 4643 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4644 else 4645 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4646 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4647 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4648 4649 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4650 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4651 4652 if (!intel_dp_init_connector(dig_port, connector)) { 4653 kfree(connector); 4654 return -EINVAL; 4655 } 4656 4657 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4658 struct drm_privacy_screen *privacy_screen; 4659 4660 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4661 if (!IS_ERR(privacy_screen)) { 4662 drm_connector_attach_privacy_screen_provider(&connector->base, 4663 privacy_screen); 4664 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4665 drm_warn(display->drm, "Error getting privacy-screen\n"); 4666 } 4667 } 4668 4669 return 0; 4670 } 4671 4672 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4673 struct drm_modeset_acquire_ctx *ctx) 4674 { 4675 struct intel_display *display = to_intel_display(encoder); 4676 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4677 struct intel_connector *connector = hdmi->attached_connector; 4678 struct i2c_adapter *ddc = connector->base.ddc; 4679 struct drm_connector_state *conn_state; 4680 struct intel_crtc_state *crtc_state; 4681 struct intel_crtc *crtc; 4682 u8 config; 4683 int ret; 4684 4685 if (connector->base.status != connector_status_connected) 4686 return 0; 4687 4688 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4689 ctx); 4690 if (ret) 4691 return ret; 4692 4693 conn_state = connector->base.state; 4694 4695 crtc = to_intel_crtc(conn_state->crtc); 4696 if (!crtc) 4697 return 0; 4698 4699 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4700 if (ret) 4701 return ret; 4702 4703 crtc_state = to_intel_crtc_state(crtc->base.state); 4704 4705 drm_WARN_ON(display->drm, 4706 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4707 4708 if (!crtc_state->hw.active) 4709 return 0; 4710 4711 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4712 !crtc_state->hdmi_scrambling) 4713 return 0; 4714 4715 if (conn_state->commit && 4716 !try_wait_for_completion(&conn_state->commit->hw_done)) 4717 return 0; 4718 4719 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4720 if (ret < 0) { 4721 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4722 connector->base.base.id, connector->base.name, ret); 4723 return 0; 4724 } 4725 4726 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4727 crtc_state->hdmi_high_tmds_clock_ratio && 4728 !!(config & SCDC_SCRAMBLING_ENABLE) == 4729 crtc_state->hdmi_scrambling) 4730 return 0; 4731 4732 /* 4733 * HDMI 2.0 says that one should not send scrambled data 4734 * prior to configuring the sink scrambling, and that 4735 * TMDS clock/data transmission should be suspended when 4736 * changing the TMDS clock rate in the sink. So let's 4737 * just do a full modeset here, even though some sinks 4738 * would be perfectly happy if were to just reconfigure 4739 * the SCDC settings on the fly. 4740 */ 4741 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4742 } 4743 4744 static void intel_ddi_link_check(struct intel_encoder *encoder) 4745 { 4746 struct intel_display *display = to_intel_display(encoder); 4747 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4748 4749 /* TODO: Move checking the HDMI link state here as well. */ 4750 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4751 4752 intel_dp_link_check(encoder); 4753 } 4754 4755 static enum intel_hotplug_state 4756 intel_ddi_hotplug(struct intel_encoder *encoder, 4757 struct intel_connector *connector) 4758 { 4759 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4760 struct intel_dp *intel_dp = &dig_port->dp; 4761 bool is_tc = intel_encoder_is_tc(encoder); 4762 struct drm_modeset_acquire_ctx ctx; 4763 enum intel_hotplug_state state; 4764 int ret; 4765 4766 if (intel_dp_test_phy(intel_dp)) 4767 return INTEL_HOTPLUG_UNCHANGED; 4768 4769 state = intel_encoder_hotplug(encoder, connector); 4770 4771 if (!intel_tc_port_link_reset(dig_port)) { 4772 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4773 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4774 ret = intel_hdmi_reset_link(encoder, &ctx); 4775 drm_WARN_ON(encoder->base.dev, ret); 4776 } else { 4777 intel_dp_check_link_state(intel_dp); 4778 } 4779 } 4780 4781 /* 4782 * Unpowered type-c dongles can take some time to boot and be 4783 * responsible, so here giving some time to those dongles to power up 4784 * and then retrying the probe. 4785 * 4786 * On many platforms the HDMI live state signal is known to be 4787 * unreliable, so we can't use it to detect if a sink is connected or 4788 * not. Instead we detect if it's connected based on whether we can 4789 * read the EDID or not. That in turn has a problem during disconnect, 4790 * since the HPD interrupt may be raised before the DDC lines get 4791 * disconnected (due to how the required length of DDC vs. HPD 4792 * connector pins are specified) and so we'll still be able to get a 4793 * valid EDID. To solve this schedule another detection cycle if this 4794 * time around we didn't detect any change in the sink's connection 4795 * status. 4796 * 4797 * Type-c connectors which get their HPD signal deasserted then 4798 * reasserted, without unplugging/replugging the sink from the 4799 * connector, introduce a delay until the AUX channel communication 4800 * becomes functional. Retry the detection for 5 seconds on type-c 4801 * connectors to account for this delay. 4802 */ 4803 if (state == INTEL_HOTPLUG_UNCHANGED && 4804 connector->hotplug_retries < (is_tc ? 5 : 1) && 4805 !dig_port->dp.is_mst) 4806 state = INTEL_HOTPLUG_RETRY; 4807 4808 return state; 4809 } 4810 4811 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4812 { 4813 struct intel_display *display = to_intel_display(encoder); 4814 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4815 4816 return intel_de_read(display, SDEISR) & bit; 4817 } 4818 4819 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4820 { 4821 struct intel_display *display = to_intel_display(encoder); 4822 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4823 4824 return intel_de_read(display, DEISR) & bit; 4825 } 4826 4827 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4828 { 4829 struct intel_display *display = to_intel_display(encoder); 4830 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4831 4832 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4833 } 4834 4835 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4836 { 4837 struct intel_connector *connector; 4838 enum port port = dig_port->base.port; 4839 4840 connector = intel_connector_alloc(); 4841 if (!connector) 4842 return -ENOMEM; 4843 4844 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4845 4846 if (!intel_hdmi_init_connector(dig_port, connector)) { 4847 /* 4848 * HDMI connector init failures may just mean conflicting DDC 4849 * pins or not having enough lanes. Handle them gracefully, but 4850 * don't fail the entire DDI init. 4851 */ 4852 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4853 kfree(connector); 4854 } 4855 4856 return 0; 4857 } 4858 4859 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4860 { 4861 struct intel_display *display = to_intel_display(dig_port); 4862 4863 if (dig_port->base.port != PORT_A) 4864 return false; 4865 4866 if (dig_port->ddi_a_4_lanes) 4867 return false; 4868 4869 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4870 * supported configuration 4871 */ 4872 if (display->platform.geminilake || display->platform.broxton) 4873 return true; 4874 4875 return false; 4876 } 4877 4878 static int 4879 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4880 { 4881 struct intel_display *display = to_intel_display(dig_port); 4882 enum port port = dig_port->base.port; 4883 int max_lanes = 4; 4884 4885 if (DISPLAY_VER(display) >= 11) 4886 return max_lanes; 4887 4888 if (port == PORT_A || port == PORT_E) { 4889 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4890 max_lanes = port == PORT_A ? 4 : 0; 4891 else 4892 /* Both A and E share 2 lanes */ 4893 max_lanes = 2; 4894 } 4895 4896 /* 4897 * Some BIOS might fail to set this bit on port A if eDP 4898 * wasn't lit up at boot. Force this bit set when needed 4899 * so we use the proper lane count for our calculations. 4900 */ 4901 if (intel_ddi_a_force_4_lanes(dig_port)) { 4902 drm_dbg_kms(display->drm, 4903 "Forcing DDI_A_4_LANES for port A\n"); 4904 dig_port->ddi_a_4_lanes = true; 4905 max_lanes = 4; 4906 } 4907 4908 return max_lanes; 4909 } 4910 4911 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4912 { 4913 if (port >= PORT_D_XELPD) 4914 return HPD_PORT_D + port - PORT_D_XELPD; 4915 else if (port >= PORT_TC1) 4916 return HPD_PORT_TC1 + port - PORT_TC1; 4917 else 4918 return HPD_PORT_A + port - PORT_A; 4919 } 4920 4921 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4922 { 4923 if (port >= PORT_TC1) 4924 return HPD_PORT_C + port - PORT_TC1; 4925 else 4926 return HPD_PORT_A + port - PORT_A; 4927 } 4928 4929 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4930 { 4931 if (port >= PORT_TC1) 4932 return HPD_PORT_TC1 + port - PORT_TC1; 4933 else 4934 return HPD_PORT_A + port - PORT_A; 4935 } 4936 4937 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4938 { 4939 if (HAS_PCH_TGP(display)) 4940 return tgl_hpd_pin(display, port); 4941 4942 if (port >= PORT_TC1) 4943 return HPD_PORT_C + port - PORT_TC1; 4944 else 4945 return HPD_PORT_A + port - PORT_A; 4946 } 4947 4948 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4949 { 4950 if (port >= PORT_C) 4951 return HPD_PORT_TC1 + port - PORT_C; 4952 else 4953 return HPD_PORT_A + port - PORT_A; 4954 } 4955 4956 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4957 { 4958 if (port == PORT_D) 4959 return HPD_PORT_A; 4960 4961 if (HAS_PCH_TGP(display)) 4962 return icl_hpd_pin(display, port); 4963 4964 return HPD_PORT_A + port - PORT_A; 4965 } 4966 4967 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4968 { 4969 if (HAS_PCH_TGP(display)) 4970 return icl_hpd_pin(display, port); 4971 4972 return HPD_PORT_A + port - PORT_A; 4973 } 4974 4975 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 4976 { 4977 if (DISPLAY_VER(display) >= 12) 4978 return port >= PORT_TC1; 4979 else if (DISPLAY_VER(display) >= 11) 4980 return port >= PORT_C; 4981 else 4982 return false; 4983 } 4984 4985 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4986 { 4987 intel_dp_encoder_suspend(encoder); 4988 } 4989 4990 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4991 { 4992 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4993 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4994 4995 /* 4996 * TODO: Move this to intel_dp_encoder_suspend(), 4997 * once modeset locking around that is removed. 4998 */ 4999 intel_encoder_link_check_flush_work(encoder); 5000 intel_tc_port_suspend(dig_port); 5001 } 5002 5003 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5004 { 5005 if (intel_encoder_is_dp(encoder)) 5006 intel_dp_encoder_shutdown(encoder); 5007 if (intel_encoder_is_hdmi(encoder)) 5008 intel_hdmi_encoder_shutdown(encoder); 5009 } 5010 5011 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5012 { 5013 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5014 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5015 5016 intel_tc_port_cleanup(dig_port); 5017 } 5018 5019 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5020 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5021 5022 static bool port_strap_detected(struct intel_display *display, enum port port) 5023 { 5024 /* straps not used on skl+ */ 5025 if (DISPLAY_VER(display) >= 9) 5026 return true; 5027 5028 switch (port) { 5029 case PORT_A: 5030 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5031 case PORT_B: 5032 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5033 case PORT_C: 5034 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5035 case PORT_D: 5036 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5037 case PORT_E: 5038 return true; /* no strap for DDI-E */ 5039 default: 5040 MISSING_CASE(port); 5041 return false; 5042 } 5043 } 5044 5045 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5046 { 5047 return init_dp || intel_encoder_is_tc(encoder); 5048 } 5049 5050 static bool assert_has_icl_dsi(struct intel_display *display) 5051 { 5052 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5053 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5054 "Platform does not support DSI\n"); 5055 } 5056 5057 static bool port_in_use(struct intel_display *display, enum port port) 5058 { 5059 struct intel_encoder *encoder; 5060 5061 for_each_intel_encoder(display->drm, encoder) { 5062 /* FIXME what about second port for dual link DSI? */ 5063 if (encoder->port == port) 5064 return true; 5065 } 5066 5067 return false; 5068 } 5069 5070 void intel_ddi_init(struct intel_display *display, 5071 const struct intel_bios_encoder_data *devdata) 5072 { 5073 struct intel_digital_port *dig_port; 5074 struct intel_encoder *encoder; 5075 bool init_hdmi, init_dp; 5076 enum port port; 5077 enum phy phy; 5078 u32 ddi_buf_ctl; 5079 5080 port = intel_bios_encoder_port(devdata); 5081 if (port == PORT_NONE) 5082 return; 5083 5084 if (!port_strap_detected(display, port)) { 5085 drm_dbg_kms(display->drm, 5086 "Port %c strap not detected\n", port_name(port)); 5087 return; 5088 } 5089 5090 if (!assert_port_valid(display, port)) 5091 return; 5092 5093 if (port_in_use(display, port)) { 5094 drm_dbg_kms(display->drm, 5095 "Port %c already claimed\n", port_name(port)); 5096 return; 5097 } 5098 5099 if (intel_bios_encoder_supports_dsi(devdata)) { 5100 /* BXT/GLK handled elsewhere, for now at least */ 5101 if (!assert_has_icl_dsi(display)) 5102 return; 5103 5104 icl_dsi_init(display, devdata); 5105 return; 5106 } 5107 5108 phy = intel_port_to_phy(display, port); 5109 5110 /* 5111 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5112 * have taken over some of the PHYs and made them unavailable to the 5113 * driver. In that case we should skip initializing the corresponding 5114 * outputs. 5115 */ 5116 if (intel_hti_uses_phy(display, phy)) { 5117 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5118 port_name(port), phy_name(phy)); 5119 return; 5120 } 5121 5122 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5123 intel_bios_encoder_supports_hdmi(devdata); 5124 init_dp = intel_bios_encoder_supports_dp(devdata); 5125 5126 if (intel_bios_encoder_is_lspcon(devdata)) { 5127 /* 5128 * Lspcon device needs to be driven with DP connector 5129 * with special detection sequence. So make sure DP 5130 * is initialized before lspcon. 5131 */ 5132 init_dp = true; 5133 init_hdmi = false; 5134 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5135 port_name(port)); 5136 } 5137 5138 if (!init_dp && !init_hdmi) { 5139 drm_dbg_kms(display->drm, 5140 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5141 port_name(port)); 5142 return; 5143 } 5144 5145 if (intel_phy_is_snps(display, phy) && 5146 display->snps.phy_failed_calibration & BIT(phy)) { 5147 drm_dbg_kms(display->drm, 5148 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5149 phy_name(phy)); 5150 } 5151 5152 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5153 if (!dig_port) 5154 return; 5155 5156 dig_port->aux_ch = AUX_CH_NONE; 5157 5158 encoder = &dig_port->base; 5159 encoder->devdata = devdata; 5160 5161 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5162 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5163 DRM_MODE_ENCODER_TMDS, 5164 "DDI %c/PHY %c", 5165 port_name(port - PORT_D_XELPD + PORT_D), 5166 phy_name(phy)); 5167 } else if (DISPLAY_VER(display) >= 12) { 5168 enum tc_port tc_port = intel_port_to_tc(display, port); 5169 5170 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5171 DRM_MODE_ENCODER_TMDS, 5172 "DDI %s%c/PHY %s%c", 5173 port >= PORT_TC1 ? "TC" : "", 5174 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5175 tc_port != TC_PORT_NONE ? "TC" : "", 5176 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5177 } else if (DISPLAY_VER(display) >= 11) { 5178 enum tc_port tc_port = intel_port_to_tc(display, port); 5179 5180 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5181 DRM_MODE_ENCODER_TMDS, 5182 "DDI %c%s/PHY %s%c", 5183 port_name(port), 5184 port >= PORT_C ? " (TC)" : "", 5185 tc_port != TC_PORT_NONE ? "TC" : "", 5186 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5187 } else { 5188 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5189 DRM_MODE_ENCODER_TMDS, 5190 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5191 } 5192 5193 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5194 5195 mutex_init(&dig_port->hdcp.mutex); 5196 dig_port->hdcp.num_streams = 0; 5197 5198 encoder->hotplug = intel_ddi_hotplug; 5199 encoder->compute_output_type = intel_ddi_compute_output_type; 5200 encoder->compute_config = intel_ddi_compute_config; 5201 encoder->compute_config_late = intel_ddi_compute_config_late; 5202 encoder->enable = intel_ddi_enable; 5203 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5204 encoder->pre_enable = intel_ddi_pre_enable; 5205 encoder->disable = intel_ddi_disable; 5206 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5207 encoder->post_disable = intel_ddi_post_disable; 5208 encoder->update_pipe = intel_ddi_update_pipe; 5209 encoder->audio_enable = intel_audio_codec_enable; 5210 encoder->audio_disable = intel_audio_codec_disable; 5211 encoder->get_hw_state = intel_ddi_get_hw_state; 5212 encoder->sync_state = intel_ddi_sync_state; 5213 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5214 encoder->suspend = intel_ddi_encoder_suspend; 5215 encoder->shutdown = intel_ddi_encoder_shutdown; 5216 encoder->get_power_domains = intel_ddi_get_power_domains; 5217 5218 encoder->type = INTEL_OUTPUT_DDI; 5219 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5220 encoder->port = port; 5221 encoder->cloneable = 0; 5222 encoder->pipe_mask = ~0; 5223 5224 if (DISPLAY_VER(display) >= 14) { 5225 encoder->enable_clock = intel_mtl_pll_enable; 5226 encoder->disable_clock = intel_mtl_pll_disable; 5227 encoder->port_pll_type = intel_mtl_port_pll_type; 5228 encoder->get_config = mtl_ddi_get_config; 5229 } else if (display->platform.dg2) { 5230 encoder->enable_clock = intel_mpllb_enable; 5231 encoder->disable_clock = intel_mpllb_disable; 5232 encoder->get_config = dg2_ddi_get_config; 5233 } else if (display->platform.alderlake_s) { 5234 encoder->enable_clock = adls_ddi_enable_clock; 5235 encoder->disable_clock = adls_ddi_disable_clock; 5236 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5237 encoder->get_config = adls_ddi_get_config; 5238 } else if (display->platform.rocketlake) { 5239 encoder->enable_clock = rkl_ddi_enable_clock; 5240 encoder->disable_clock = rkl_ddi_disable_clock; 5241 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5242 encoder->get_config = rkl_ddi_get_config; 5243 } else if (display->platform.dg1) { 5244 encoder->enable_clock = dg1_ddi_enable_clock; 5245 encoder->disable_clock = dg1_ddi_disable_clock; 5246 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5247 encoder->get_config = dg1_ddi_get_config; 5248 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5249 if (intel_ddi_is_tc(display, port)) { 5250 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5251 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5252 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5253 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5254 encoder->get_config = icl_ddi_combo_get_config; 5255 } else { 5256 encoder->enable_clock = icl_ddi_combo_enable_clock; 5257 encoder->disable_clock = icl_ddi_combo_disable_clock; 5258 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5259 encoder->get_config = icl_ddi_combo_get_config; 5260 } 5261 } else if (DISPLAY_VER(display) >= 11) { 5262 if (intel_ddi_is_tc(display, port)) { 5263 encoder->enable_clock = icl_ddi_tc_enable_clock; 5264 encoder->disable_clock = icl_ddi_tc_disable_clock; 5265 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5266 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5267 encoder->get_config = icl_ddi_tc_get_config; 5268 } else { 5269 encoder->enable_clock = icl_ddi_combo_enable_clock; 5270 encoder->disable_clock = icl_ddi_combo_disable_clock; 5271 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5272 encoder->get_config = icl_ddi_combo_get_config; 5273 } 5274 } else if (display->platform.geminilake || display->platform.broxton) { 5275 /* BXT/GLK have fixed PLL->port mapping */ 5276 encoder->get_config = bxt_ddi_get_config; 5277 } else if (DISPLAY_VER(display) == 9) { 5278 encoder->enable_clock = skl_ddi_enable_clock; 5279 encoder->disable_clock = skl_ddi_disable_clock; 5280 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5281 encoder->get_config = skl_ddi_get_config; 5282 } else if (display->platform.broadwell || display->platform.haswell) { 5283 encoder->enable_clock = hsw_ddi_enable_clock; 5284 encoder->disable_clock = hsw_ddi_disable_clock; 5285 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5286 encoder->get_config = hsw_ddi_get_config; 5287 } 5288 5289 if (DISPLAY_VER(display) >= 14) { 5290 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5291 } else if (display->platform.dg2) { 5292 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5293 } else if (DISPLAY_VER(display) >= 12) { 5294 if (intel_encoder_is_combo(encoder)) 5295 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5296 else 5297 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5298 } else if (DISPLAY_VER(display) >= 11) { 5299 if (intel_encoder_is_combo(encoder)) 5300 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5301 else 5302 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5303 } else if (display->platform.geminilake || display->platform.broxton) { 5304 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5305 } else { 5306 encoder->set_signal_levels = hsw_set_signal_levels; 5307 } 5308 5309 intel_ddi_buf_trans_init(encoder); 5310 5311 if (DISPLAY_VER(display) >= 13) 5312 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5313 else if (display->platform.dg1) 5314 encoder->hpd_pin = dg1_hpd_pin(display, port); 5315 else if (display->platform.rocketlake) 5316 encoder->hpd_pin = rkl_hpd_pin(display, port); 5317 else if (DISPLAY_VER(display) >= 12) 5318 encoder->hpd_pin = tgl_hpd_pin(display, port); 5319 else if (display->platform.jasperlake || display->platform.elkhartlake) 5320 encoder->hpd_pin = ehl_hpd_pin(display, port); 5321 else if (DISPLAY_VER(display) == 11) 5322 encoder->hpd_pin = icl_hpd_pin(display, port); 5323 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5324 encoder->hpd_pin = skl_hpd_pin(display, port); 5325 else 5326 encoder->hpd_pin = intel_hpd_pin_default(port); 5327 5328 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5329 5330 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5331 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5332 5333 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5334 5335 dig_port->dp.output_reg = INVALID_MMIO_REG; 5336 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5337 5338 if (need_aux_ch(encoder, init_dp)) { 5339 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5340 if (dig_port->aux_ch == AUX_CH_NONE) 5341 goto err; 5342 } 5343 5344 if (intel_encoder_is_tc(encoder)) { 5345 bool is_legacy = 5346 !intel_bios_encoder_supports_typec_usb(devdata) && 5347 !intel_bios_encoder_supports_tbt(devdata); 5348 5349 if (!is_legacy && init_hdmi) { 5350 is_legacy = !init_dp; 5351 5352 drm_dbg_kms(display->drm, 5353 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5354 port_name(port), 5355 str_yes_no(init_dp), 5356 is_legacy ? "legacy" : "non-legacy"); 5357 } 5358 5359 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5360 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5361 5362 dig_port->lock = intel_tc_port_lock; 5363 dig_port->unlock = intel_tc_port_unlock; 5364 5365 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5366 goto err; 5367 } 5368 5369 drm_WARN_ON(display->drm, port > PORT_I); 5370 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5371 5372 if (DISPLAY_VER(display) >= 11) { 5373 if (intel_encoder_is_tc(encoder)) 5374 dig_port->connected = intel_tc_port_connected; 5375 else 5376 dig_port->connected = lpt_digital_port_connected; 5377 } else if (display->platform.geminilake || display->platform.broxton) { 5378 dig_port->connected = bdw_digital_port_connected; 5379 } else if (DISPLAY_VER(display) == 9) { 5380 dig_port->connected = lpt_digital_port_connected; 5381 } else if (display->platform.broadwell) { 5382 if (port == PORT_A) 5383 dig_port->connected = bdw_digital_port_connected; 5384 else 5385 dig_port->connected = lpt_digital_port_connected; 5386 } else if (display->platform.haswell) { 5387 if (port == PORT_A) 5388 dig_port->connected = hsw_digital_port_connected; 5389 else 5390 dig_port->connected = lpt_digital_port_connected; 5391 } 5392 5393 intel_infoframe_init(dig_port); 5394 5395 if (init_dp) { 5396 if (intel_ddi_init_dp_connector(dig_port)) 5397 goto err; 5398 5399 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5400 5401 if (dig_port->dp.mso_link_count) 5402 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5403 } 5404 5405 /* 5406 * In theory we don't need the encoder->type check, 5407 * but leave it just in case we have some really bad VBTs... 5408 */ 5409 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5410 if (intel_ddi_init_hdmi_connector(dig_port)) 5411 goto err; 5412 } 5413 5414 return; 5415 5416 err: 5417 drm_encoder_cleanup(&encoder->base); 5418 kfree(dig_port); 5419 } 5420