1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dpio_phy.h" 58 #include "intel_dsi.h" 59 #include "intel_fdi.h" 60 #include "intel_fifo_underrun.h" 61 #include "intel_gmbus.h" 62 #include "intel_hdcp.h" 63 #include "intel_hdmi.h" 64 #include "intel_hotplug.h" 65 #include "intel_hti.h" 66 #include "intel_lspcon.h" 67 #include "intel_mg_phy_regs.h" 68 #include "intel_modeset_lock.h" 69 #include "intel_pps.h" 70 #include "intel_psr.h" 71 #include "intel_quirks.h" 72 #include "intel_snps_phy.h" 73 #include "intel_tc.h" 74 #include "intel_vdsc.h" 75 #include "intel_vdsc_regs.h" 76 #include "skl_scaler.h" 77 #include "skl_universal_plane.h" 78 79 static const u8 index_to_dp_signal_levels[] = { 80 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 81 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 82 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 83 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 84 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 88 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 89 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 90 }; 91 92 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 93 const struct intel_ddi_buf_trans *trans) 94 { 95 int level; 96 97 level = intel_bios_hdmi_level_shift(encoder->devdata); 98 if (level < 0) 99 level = trans->hdmi_default_entry; 100 101 return level; 102 } 103 104 static bool has_buf_trans_select(struct drm_i915_private *i915) 105 { 106 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 107 } 108 109 static bool has_iboost(struct drm_i915_private *i915) 110 { 111 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 112 } 113 114 /* 115 * Starting with Haswell, DDI port buffers must be programmed with correct 116 * values in advance. This function programs the correct values for 117 * DP/eDP/FDI use cases. 118 */ 119 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 120 const struct intel_crtc_state *crtc_state) 121 { 122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 123 u32 iboost_bit = 0; 124 int i, n_entries; 125 enum port port = encoder->port; 126 const struct intel_ddi_buf_trans *trans; 127 128 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 129 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 130 return; 131 132 /* If we're boosting the current, set bit 31 of trans1 */ 133 if (has_iboost(dev_priv) && 134 intel_bios_dp_boost_level(encoder->devdata)) 135 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 136 137 for (i = 0; i < n_entries; i++) { 138 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 139 trans->entries[i].hsw.trans1 | iboost_bit); 140 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 141 trans->entries[i].hsw.trans2); 142 } 143 } 144 145 /* 146 * Starting with Haswell, DDI port buffers must be programmed with correct 147 * values in advance. This function programs the correct values for 148 * HDMI/DVI use cases. 149 */ 150 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 151 const struct intel_crtc_state *crtc_state) 152 { 153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 154 int level = intel_ddi_level(encoder, crtc_state, 0); 155 u32 iboost_bit = 0; 156 int n_entries; 157 enum port port = encoder->port; 158 const struct intel_ddi_buf_trans *trans; 159 160 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 161 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 162 return; 163 164 /* If we're boosting the current, set bit 31 of trans1 */ 165 if (has_iboost(dev_priv) && 166 intel_bios_hdmi_boost_level(encoder->devdata)) 167 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 168 169 /* Entry 9 is for HDMI: */ 170 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 171 trans->entries[level].hsw.trans1 | iboost_bit); 172 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 173 trans->entries[level].hsw.trans2); 174 } 175 176 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 177 { 178 int ret; 179 180 /* FIXME: find out why Bspec's 100us timeout is too short */ 181 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & 182 XELPDP_PORT_BUF_PHY_IDLE), 10000); 183 if (ret) 184 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 185 port_name(port)); 186 } 187 188 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 189 enum port port) 190 { 191 if (IS_BROXTON(dev_priv)) { 192 udelay(16); 193 return; 194 } 195 196 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 197 DDI_BUF_IS_IDLE), 8)) 198 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 199 port_name(port)); 200 } 201 202 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 203 enum port port) 204 { 205 enum phy phy = intel_port_to_phy(dev_priv, port); 206 int timeout_us; 207 int ret; 208 209 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 210 if (DISPLAY_VER(dev_priv) < 10) { 211 usleep_range(518, 1000); 212 return; 213 } 214 215 if (DISPLAY_VER(dev_priv) >= 14) { 216 timeout_us = 10000; 217 } else if (IS_DG2(dev_priv)) { 218 timeout_us = 1200; 219 } else if (DISPLAY_VER(dev_priv) >= 12) { 220 if (intel_phy_is_tc(dev_priv, phy)) 221 timeout_us = 3000; 222 else 223 timeout_us = 1000; 224 } else { 225 timeout_us = 500; 226 } 227 228 if (DISPLAY_VER(dev_priv) >= 14) 229 ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE), 230 timeout_us, 10, 10); 231 else 232 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 233 timeout_us, 10, 10); 234 235 if (ret) 236 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 237 port_name(port)); 238 } 239 240 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 241 { 242 switch (pll->info->id) { 243 case DPLL_ID_WRPLL1: 244 return PORT_CLK_SEL_WRPLL1; 245 case DPLL_ID_WRPLL2: 246 return PORT_CLK_SEL_WRPLL2; 247 case DPLL_ID_SPLL: 248 return PORT_CLK_SEL_SPLL; 249 case DPLL_ID_LCPLL_810: 250 return PORT_CLK_SEL_LCPLL_810; 251 case DPLL_ID_LCPLL_1350: 252 return PORT_CLK_SEL_LCPLL_1350; 253 case DPLL_ID_LCPLL_2700: 254 return PORT_CLK_SEL_LCPLL_2700; 255 default: 256 MISSING_CASE(pll->info->id); 257 return PORT_CLK_SEL_NONE; 258 } 259 } 260 261 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 262 const struct intel_crtc_state *crtc_state) 263 { 264 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 265 int clock = crtc_state->port_clock; 266 const enum intel_dpll_id id = pll->info->id; 267 268 switch (id) { 269 default: 270 /* 271 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 272 * here, so do warn if this get passed in 273 */ 274 MISSING_CASE(id); 275 return DDI_CLK_SEL_NONE; 276 case DPLL_ID_ICL_TBTPLL: 277 switch (clock) { 278 case 162000: 279 return DDI_CLK_SEL_TBT_162; 280 case 270000: 281 return DDI_CLK_SEL_TBT_270; 282 case 540000: 283 return DDI_CLK_SEL_TBT_540; 284 case 810000: 285 return DDI_CLK_SEL_TBT_810; 286 default: 287 MISSING_CASE(clock); 288 return DDI_CLK_SEL_NONE; 289 } 290 case DPLL_ID_ICL_MGPLL1: 291 case DPLL_ID_ICL_MGPLL2: 292 case DPLL_ID_ICL_MGPLL3: 293 case DPLL_ID_ICL_MGPLL4: 294 case DPLL_ID_TGL_MGPLL5: 295 case DPLL_ID_TGL_MGPLL6: 296 return DDI_CLK_SEL_MG; 297 } 298 } 299 300 static u32 ddi_buf_phy_link_rate(int port_clock) 301 { 302 switch (port_clock) { 303 case 162000: 304 return DDI_BUF_PHY_LINK_RATE(0); 305 case 216000: 306 return DDI_BUF_PHY_LINK_RATE(4); 307 case 243000: 308 return DDI_BUF_PHY_LINK_RATE(5); 309 case 270000: 310 return DDI_BUF_PHY_LINK_RATE(1); 311 case 324000: 312 return DDI_BUF_PHY_LINK_RATE(6); 313 case 432000: 314 return DDI_BUF_PHY_LINK_RATE(7); 315 case 540000: 316 return DDI_BUF_PHY_LINK_RATE(2); 317 case 810000: 318 return DDI_BUF_PHY_LINK_RATE(3); 319 default: 320 MISSING_CASE(port_clock); 321 return DDI_BUF_PHY_LINK_RATE(0); 322 } 323 } 324 325 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 326 const struct intel_crtc_state *crtc_state) 327 { 328 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 329 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 330 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 331 enum phy phy = intel_port_to_phy(i915, encoder->port); 332 333 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 334 intel_dp->DP = dig_port->saved_port_bits | 335 DDI_PORT_WIDTH(crtc_state->lane_count) | 336 DDI_BUF_TRANS_SELECT(0); 337 338 if (DISPLAY_VER(i915) >= 14) { 339 if (intel_dp_is_uhbr(crtc_state)) 340 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 341 else 342 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 343 } 344 345 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 346 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 347 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 348 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 349 } 350 } 351 352 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 353 enum port port) 354 { 355 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 356 357 switch (val) { 358 case DDI_CLK_SEL_NONE: 359 return 0; 360 case DDI_CLK_SEL_TBT_162: 361 return 162000; 362 case DDI_CLK_SEL_TBT_270: 363 return 270000; 364 case DDI_CLK_SEL_TBT_540: 365 return 540000; 366 case DDI_CLK_SEL_TBT_810: 367 return 810000; 368 default: 369 MISSING_CASE(val); 370 return 0; 371 } 372 } 373 374 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 375 { 376 /* CRT dotclock is determined via other means */ 377 if (pipe_config->has_pch_encoder) 378 return; 379 380 pipe_config->hw.adjusted_mode.crtc_clock = 381 intel_crtc_dotclock(pipe_config); 382 } 383 384 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 385 const struct drm_connector_state *conn_state) 386 { 387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 388 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 389 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 390 u32 temp; 391 392 if (!intel_crtc_has_dp_encoder(crtc_state)) 393 return; 394 395 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 396 397 temp = DP_MSA_MISC_SYNC_CLOCK; 398 399 switch (crtc_state->pipe_bpp) { 400 case 18: 401 temp |= DP_MSA_MISC_6_BPC; 402 break; 403 case 24: 404 temp |= DP_MSA_MISC_8_BPC; 405 break; 406 case 30: 407 temp |= DP_MSA_MISC_10_BPC; 408 break; 409 case 36: 410 temp |= DP_MSA_MISC_12_BPC; 411 break; 412 default: 413 MISSING_CASE(crtc_state->pipe_bpp); 414 break; 415 } 416 417 /* nonsense combination */ 418 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 419 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 420 421 if (crtc_state->limited_color_range) 422 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 423 424 /* 425 * As per DP 1.2 spec section 2.3.4.3 while sending 426 * YCBCR 444 signals we should program MSA MISC1/0 fields with 427 * colorspace information. 428 */ 429 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 430 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 431 432 /* 433 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 434 * of Color Encoding Format and Content Color Gamut] while sending 435 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 436 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 437 */ 438 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 439 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 440 441 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 442 } 443 444 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 445 { 446 if (master_transcoder == TRANSCODER_EDP) 447 return 0; 448 else 449 return master_transcoder + 1; 450 } 451 452 static void 453 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 454 const struct intel_crtc_state *crtc_state) 455 { 456 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 457 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 458 u32 val = 0; 459 460 if (intel_dp_is_uhbr(crtc_state)) 461 val = TRANS_DP2_128B132B_CHANNEL_CODING; 462 463 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 464 } 465 466 /* 467 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 468 * 469 * Only intended to be used by intel_ddi_enable_transcoder_func() and 470 * intel_ddi_config_transcoder_func(). 471 */ 472 static u32 473 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 474 const struct intel_crtc_state *crtc_state) 475 { 476 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 478 enum pipe pipe = crtc->pipe; 479 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 480 enum port port = encoder->port; 481 u32 temp; 482 483 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 484 temp = TRANS_DDI_FUNC_ENABLE; 485 if (DISPLAY_VER(dev_priv) >= 12) 486 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 487 else 488 temp |= TRANS_DDI_SELECT_PORT(port); 489 490 switch (crtc_state->pipe_bpp) { 491 default: 492 MISSING_CASE(crtc_state->pipe_bpp); 493 fallthrough; 494 case 18: 495 temp |= TRANS_DDI_BPC_6; 496 break; 497 case 24: 498 temp |= TRANS_DDI_BPC_8; 499 break; 500 case 30: 501 temp |= TRANS_DDI_BPC_10; 502 break; 503 case 36: 504 temp |= TRANS_DDI_BPC_12; 505 break; 506 } 507 508 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 509 temp |= TRANS_DDI_PVSYNC; 510 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 511 temp |= TRANS_DDI_PHSYNC; 512 513 if (cpu_transcoder == TRANSCODER_EDP) { 514 switch (pipe) { 515 default: 516 MISSING_CASE(pipe); 517 fallthrough; 518 case PIPE_A: 519 /* On Haswell, can only use the always-on power well for 520 * eDP when not using the panel fitter, and when not 521 * using motion blur mitigation (which we don't 522 * support). */ 523 if (crtc_state->pch_pfit.force_thru) 524 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 525 else 526 temp |= TRANS_DDI_EDP_INPUT_A_ON; 527 break; 528 case PIPE_B: 529 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 530 break; 531 case PIPE_C: 532 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 533 break; 534 } 535 } 536 537 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 538 if (crtc_state->has_hdmi_sink) 539 temp |= TRANS_DDI_MODE_SELECT_HDMI; 540 else 541 temp |= TRANS_DDI_MODE_SELECT_DVI; 542 543 if (crtc_state->hdmi_scrambling) 544 temp |= TRANS_DDI_HDMI_SCRAMBLING; 545 if (crtc_state->hdmi_high_tmds_clock_ratio) 546 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 547 if (DISPLAY_VER(dev_priv) >= 14) 548 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 549 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 550 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 551 temp |= (crtc_state->fdi_lanes - 1) << 1; 552 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 553 if (intel_dp_is_uhbr(crtc_state)) 554 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 555 else 556 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 557 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 558 559 if (DISPLAY_VER(dev_priv) >= 12) { 560 enum transcoder master; 561 562 master = crtc_state->mst_master_transcoder; 563 drm_WARN_ON(&dev_priv->drm, 564 master == INVALID_TRANSCODER); 565 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 566 } 567 } else { 568 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 569 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 570 } 571 572 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 573 crtc_state->master_transcoder != INVALID_TRANSCODER) { 574 u8 master_select = 575 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 576 577 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 578 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 579 } 580 581 return temp; 582 } 583 584 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 585 const struct intel_crtc_state *crtc_state) 586 { 587 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 588 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 589 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 590 591 if (DISPLAY_VER(dev_priv) >= 11) { 592 enum transcoder master_transcoder = crtc_state->master_transcoder; 593 u32 ctl2 = 0; 594 595 if (master_transcoder != INVALID_TRANSCODER) { 596 u8 master_select = 597 bdw_trans_port_sync_master_select(master_transcoder); 598 599 ctl2 |= PORT_SYNC_MODE_ENABLE | 600 PORT_SYNC_MODE_MASTER_SELECT(master_select); 601 } 602 603 intel_de_write(dev_priv, 604 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 605 } 606 607 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 608 intel_ddi_transcoder_func_reg_val_get(encoder, 609 crtc_state)); 610 } 611 612 /* 613 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 614 * bit. 615 */ 616 static void 617 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 618 const struct intel_crtc_state *crtc_state) 619 { 620 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 621 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 622 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 623 u32 ctl; 624 625 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 626 ctl &= ~TRANS_DDI_FUNC_ENABLE; 627 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 628 } 629 630 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 631 { 632 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 634 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 635 u32 ctl; 636 637 if (DISPLAY_VER(dev_priv) >= 11) 638 intel_de_write(dev_priv, 639 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 640 641 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 642 643 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 644 645 ctl &= ~TRANS_DDI_FUNC_ENABLE; 646 647 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 648 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 649 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 650 651 if (DISPLAY_VER(dev_priv) >= 12) { 652 if (!intel_dp_mst_is_master_trans(crtc_state)) { 653 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 654 TRANS_DDI_MODE_SELECT_MASK); 655 } 656 } else { 657 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 658 } 659 660 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 661 662 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 663 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 664 drm_dbg_kms(&dev_priv->drm, 665 "Quirk Increase DDI disabled time\n"); 666 /* Quirk time at 100ms for reliable operation */ 667 msleep(100); 668 } 669 } 670 671 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 672 enum transcoder cpu_transcoder, 673 bool enable, u32 hdcp_mask) 674 { 675 struct drm_device *dev = intel_encoder->base.dev; 676 struct drm_i915_private *dev_priv = to_i915(dev); 677 intel_wakeref_t wakeref; 678 int ret = 0; 679 680 wakeref = intel_display_power_get_if_enabled(dev_priv, 681 intel_encoder->power_domain); 682 if (drm_WARN_ON(dev, !wakeref)) 683 return -ENXIO; 684 685 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 686 hdcp_mask, enable ? hdcp_mask : 0); 687 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 688 return ret; 689 } 690 691 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 692 { 693 struct drm_device *dev = intel_connector->base.dev; 694 struct drm_i915_private *dev_priv = to_i915(dev); 695 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 696 int type = intel_connector->base.connector_type; 697 enum port port = encoder->port; 698 enum transcoder cpu_transcoder; 699 intel_wakeref_t wakeref; 700 enum pipe pipe = 0; 701 u32 tmp; 702 bool ret; 703 704 wakeref = intel_display_power_get_if_enabled(dev_priv, 705 encoder->power_domain); 706 if (!wakeref) 707 return false; 708 709 if (!encoder->get_hw_state(encoder, &pipe)) { 710 ret = false; 711 goto out; 712 } 713 714 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 715 cpu_transcoder = TRANSCODER_EDP; 716 else 717 cpu_transcoder = (enum transcoder) pipe; 718 719 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 720 721 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 722 case TRANS_DDI_MODE_SELECT_HDMI: 723 case TRANS_DDI_MODE_SELECT_DVI: 724 ret = type == DRM_MODE_CONNECTOR_HDMIA; 725 break; 726 727 case TRANS_DDI_MODE_SELECT_DP_SST: 728 ret = type == DRM_MODE_CONNECTOR_eDP || 729 type == DRM_MODE_CONNECTOR_DisplayPort; 730 break; 731 732 case TRANS_DDI_MODE_SELECT_DP_MST: 733 /* if the transcoder is in MST state then 734 * connector isn't connected */ 735 ret = false; 736 break; 737 738 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 739 if (HAS_DP20(dev_priv)) 740 /* 128b/132b */ 741 ret = false; 742 else 743 /* FDI */ 744 ret = type == DRM_MODE_CONNECTOR_VGA; 745 break; 746 747 default: 748 ret = false; 749 break; 750 } 751 752 out: 753 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 754 755 return ret; 756 } 757 758 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 759 u8 *pipe_mask, bool *is_dp_mst) 760 { 761 struct drm_device *dev = encoder->base.dev; 762 struct drm_i915_private *dev_priv = to_i915(dev); 763 enum port port = encoder->port; 764 intel_wakeref_t wakeref; 765 enum pipe p; 766 u32 tmp; 767 u8 mst_pipe_mask; 768 769 *pipe_mask = 0; 770 *is_dp_mst = false; 771 772 wakeref = intel_display_power_get_if_enabled(dev_priv, 773 encoder->power_domain); 774 if (!wakeref) 775 return; 776 777 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 778 if (!(tmp & DDI_BUF_CTL_ENABLE)) 779 goto out; 780 781 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 782 tmp = intel_de_read(dev_priv, 783 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 784 785 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 786 default: 787 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 788 fallthrough; 789 case TRANS_DDI_EDP_INPUT_A_ON: 790 case TRANS_DDI_EDP_INPUT_A_ONOFF: 791 *pipe_mask = BIT(PIPE_A); 792 break; 793 case TRANS_DDI_EDP_INPUT_B_ONOFF: 794 *pipe_mask = BIT(PIPE_B); 795 break; 796 case TRANS_DDI_EDP_INPUT_C_ONOFF: 797 *pipe_mask = BIT(PIPE_C); 798 break; 799 } 800 801 goto out; 802 } 803 804 mst_pipe_mask = 0; 805 for_each_pipe(dev_priv, p) { 806 enum transcoder cpu_transcoder = (enum transcoder)p; 807 unsigned int port_mask, ddi_select; 808 intel_wakeref_t trans_wakeref; 809 810 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 811 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 812 if (!trans_wakeref) 813 continue; 814 815 if (DISPLAY_VER(dev_priv) >= 12) { 816 port_mask = TGL_TRANS_DDI_PORT_MASK; 817 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 818 } else { 819 port_mask = TRANS_DDI_PORT_MASK; 820 ddi_select = TRANS_DDI_SELECT_PORT(port); 821 } 822 823 tmp = intel_de_read(dev_priv, 824 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 825 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 826 trans_wakeref); 827 828 if ((tmp & port_mask) != ddi_select) 829 continue; 830 831 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 832 (HAS_DP20(dev_priv) && 833 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 834 mst_pipe_mask |= BIT(p); 835 836 *pipe_mask |= BIT(p); 837 } 838 839 if (!*pipe_mask) 840 drm_dbg_kms(&dev_priv->drm, 841 "No pipe for [ENCODER:%d:%s] found\n", 842 encoder->base.base.id, encoder->base.name); 843 844 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 845 drm_dbg_kms(&dev_priv->drm, 846 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 847 encoder->base.base.id, encoder->base.name, 848 *pipe_mask); 849 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 850 } 851 852 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 853 drm_dbg_kms(&dev_priv->drm, 854 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 855 encoder->base.base.id, encoder->base.name, 856 *pipe_mask, mst_pipe_mask); 857 else 858 *is_dp_mst = mst_pipe_mask; 859 860 out: 861 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 862 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 863 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 864 BXT_PHY_LANE_POWERDOWN_ACK | 865 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 866 drm_err(&dev_priv->drm, 867 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 868 encoder->base.base.id, encoder->base.name, tmp); 869 } 870 871 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 872 } 873 874 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 875 enum pipe *pipe) 876 { 877 u8 pipe_mask; 878 bool is_mst; 879 880 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 881 882 if (is_mst || !pipe_mask) 883 return false; 884 885 *pipe = ffs(pipe_mask) - 1; 886 887 return true; 888 } 889 890 static enum intel_display_power_domain 891 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 892 const struct intel_crtc_state *crtc_state) 893 { 894 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 895 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 896 897 /* 898 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 899 * DC states enabled at the same time, while for driver initiated AUX 900 * transfers we need the same AUX IOs to be powered but with DC states 901 * disabled. Accordingly use the AUX_IO_<port> power domain here which 902 * leaves DC states enabled. 903 * 904 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 905 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 906 * well, so we can acquire a wider AUX_<port> power domain reference 907 * instead of a specific AUX_IO_<port> reference without powering up any 908 * extra wells. 909 */ 910 if (intel_encoder_can_psr(&dig_port->base)) 911 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 912 else if (DISPLAY_VER(i915) < 14 && 913 (intel_crtc_has_dp_encoder(crtc_state) || 914 intel_phy_is_tc(i915, phy))) 915 return intel_aux_power_domain(dig_port); 916 else 917 return POWER_DOMAIN_INVALID; 918 } 919 920 static void 921 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 922 const struct intel_crtc_state *crtc_state) 923 { 924 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 925 enum intel_display_power_domain domain = 926 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 927 928 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 929 930 if (domain == POWER_DOMAIN_INVALID) 931 return; 932 933 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 934 } 935 936 static void 937 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 938 const struct intel_crtc_state *crtc_state) 939 { 940 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 941 enum intel_display_power_domain domain = 942 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 943 intel_wakeref_t wf; 944 945 wf = fetch_and_zero(&dig_port->aux_wakeref); 946 if (!wf) 947 return; 948 949 intel_display_power_put(i915, domain, wf); 950 } 951 952 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 953 struct intel_crtc_state *crtc_state) 954 { 955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 956 struct intel_digital_port *dig_port; 957 958 /* 959 * TODO: Add support for MST encoders. Atm, the following should never 960 * happen since fake-MST encoders don't set their get_power_domains() 961 * hook. 962 */ 963 if (drm_WARN_ON(&dev_priv->drm, 964 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 965 return; 966 967 dig_port = enc_to_dig_port(encoder); 968 969 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 970 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 971 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 972 dig_port->ddi_io_power_domain); 973 } 974 975 main_link_aux_power_domain_get(dig_port, crtc_state); 976 } 977 978 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 979 const struct intel_crtc_state *crtc_state) 980 { 981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 983 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 984 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 985 u32 val; 986 987 if (cpu_transcoder == TRANSCODER_EDP) 988 return; 989 990 if (DISPLAY_VER(dev_priv) >= 13) 991 val = TGL_TRANS_CLK_SEL_PORT(phy); 992 else if (DISPLAY_VER(dev_priv) >= 12) 993 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 994 else 995 val = TRANS_CLK_SEL_PORT(encoder->port); 996 997 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 998 } 999 1000 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1001 { 1002 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1003 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1004 u32 val; 1005 1006 if (cpu_transcoder == TRANSCODER_EDP) 1007 return; 1008 1009 if (DISPLAY_VER(dev_priv) >= 12) 1010 val = TGL_TRANS_CLK_SEL_DISABLED; 1011 else 1012 val = TRANS_CLK_SEL_DISABLED; 1013 1014 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1015 } 1016 1017 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1018 enum port port, u8 iboost) 1019 { 1020 u32 tmp; 1021 1022 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1023 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1024 if (iboost) 1025 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1026 else 1027 tmp |= BALANCE_LEG_DISABLE(port); 1028 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1029 } 1030 1031 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1032 const struct intel_crtc_state *crtc_state, 1033 int level) 1034 { 1035 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1037 u8 iboost; 1038 1039 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1040 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1041 else 1042 iboost = intel_bios_dp_boost_level(encoder->devdata); 1043 1044 if (iboost == 0) { 1045 const struct intel_ddi_buf_trans *trans; 1046 int n_entries; 1047 1048 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1049 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1050 return; 1051 1052 iboost = trans->entries[level].hsw.i_boost; 1053 } 1054 1055 /* Make sure that the requested I_boost is valid */ 1056 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1057 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1058 return; 1059 } 1060 1061 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1062 1063 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1064 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1065 } 1066 1067 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1068 const struct intel_crtc_state *crtc_state) 1069 { 1070 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1071 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1072 int n_entries; 1073 1074 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1075 1076 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1077 n_entries = 1; 1078 if (drm_WARN_ON(&dev_priv->drm, 1079 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1080 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1081 1082 return index_to_dp_signal_levels[n_entries - 1] & 1083 DP_TRAIN_VOLTAGE_SWING_MASK; 1084 } 1085 1086 /* 1087 * We assume that the full set of pre-emphasis values can be 1088 * used on all DDI platforms. Should that change we need to 1089 * rethink this code. 1090 */ 1091 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1092 { 1093 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1094 } 1095 1096 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1097 int lane) 1098 { 1099 if (crtc_state->port_clock > 600000) 1100 return 0; 1101 1102 if (crtc_state->lane_count == 4) 1103 return lane >= 1 ? LOADGEN_SELECT : 0; 1104 else 1105 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1106 } 1107 1108 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1109 const struct intel_crtc_state *crtc_state) 1110 { 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 const struct intel_ddi_buf_trans *trans; 1113 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1114 int n_entries, ln; 1115 u32 val; 1116 1117 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1118 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1119 return; 1120 1121 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1122 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1123 1124 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1125 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1126 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1127 intel_dp->hobl_active ? val : 0); 1128 } 1129 1130 /* Set PORT_TX_DW5 */ 1131 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1132 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1133 TAP2_DISABLE | TAP3_DISABLE); 1134 val |= SCALING_MODE_SEL(0x2); 1135 val |= RTERM_SELECT(0x6); 1136 val |= TAP3_DISABLE; 1137 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1138 1139 /* Program PORT_TX_DW2 */ 1140 for (ln = 0; ln < 4; ln++) { 1141 int level = intel_ddi_level(encoder, crtc_state, ln); 1142 1143 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1144 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1145 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1146 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1147 RCOMP_SCALAR(0x98)); 1148 } 1149 1150 /* Program PORT_TX_DW4 */ 1151 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1152 for (ln = 0; ln < 4; ln++) { 1153 int level = intel_ddi_level(encoder, crtc_state, ln); 1154 1155 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1156 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1157 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1158 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1159 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1160 } 1161 1162 /* Program PORT_TX_DW7 */ 1163 for (ln = 0; ln < 4; ln++) { 1164 int level = intel_ddi_level(encoder, crtc_state, ln); 1165 1166 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1167 N_SCALAR_MASK, 1168 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1169 } 1170 } 1171 1172 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1173 const struct intel_crtc_state *crtc_state) 1174 { 1175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1176 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1177 u32 val; 1178 int ln; 1179 1180 /* 1181 * 1. If port type is eDP or DP, 1182 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1183 * else clear to 0b. 1184 */ 1185 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1186 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1187 val &= ~COMMON_KEEPER_EN; 1188 else 1189 val |= COMMON_KEEPER_EN; 1190 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1191 1192 /* 2. Program loadgen select */ 1193 /* 1194 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1195 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1196 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1197 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1198 */ 1199 for (ln = 0; ln < 4; ln++) { 1200 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1201 LOADGEN_SELECT, 1202 icl_combo_phy_loadgen_select(crtc_state, ln)); 1203 } 1204 1205 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1206 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1207 0, SUS_CLOCK_CONFIG); 1208 1209 /* 4. Clear training enable to change swing values */ 1210 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1211 val &= ~TX_TRAINING_EN; 1212 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1213 1214 /* 5. Program swing and de-emphasis */ 1215 icl_ddi_combo_vswing_program(encoder, crtc_state); 1216 1217 /* 6. Set training enable to trigger update */ 1218 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1219 val |= TX_TRAINING_EN; 1220 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1221 } 1222 1223 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1224 const struct intel_crtc_state *crtc_state) 1225 { 1226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1227 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1228 const struct intel_ddi_buf_trans *trans; 1229 int n_entries, ln; 1230 1231 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1232 return; 1233 1234 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1235 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1236 return; 1237 1238 for (ln = 0; ln < 2; ln++) { 1239 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1240 CRI_USE_FS32, 0); 1241 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1242 CRI_USE_FS32, 0); 1243 } 1244 1245 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1246 for (ln = 0; ln < 2; ln++) { 1247 int level; 1248 1249 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1250 1251 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1252 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1253 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1254 1255 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1256 1257 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1258 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1259 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1260 } 1261 1262 /* Program MG_TX_DRVCTRL with values from vswing table */ 1263 for (ln = 0; ln < 2; ln++) { 1264 int level; 1265 1266 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1267 1268 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1269 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1270 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1271 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1272 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1273 CRI_TXDEEMPH_OVERRIDE_EN); 1274 1275 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1276 1277 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1278 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1279 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1280 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1281 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1282 CRI_TXDEEMPH_OVERRIDE_EN); 1283 1284 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1285 } 1286 1287 /* 1288 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1289 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1290 * values from table for which TX1 and TX2 enabled. 1291 */ 1292 for (ln = 0; ln < 2; ln++) { 1293 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1294 CFG_LOW_RATE_LKREN_EN, 1295 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1296 } 1297 1298 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1299 for (ln = 0; ln < 2; ln++) { 1300 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1301 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1302 CFG_AMI_CK_DIV_OVERRIDE_EN, 1303 crtc_state->port_clock > 500000 ? 1304 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1305 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1306 1307 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1308 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1309 CFG_AMI_CK_DIV_OVERRIDE_EN, 1310 crtc_state->port_clock > 500000 ? 1311 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1312 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1313 } 1314 1315 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1316 for (ln = 0; ln < 2; ln++) { 1317 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1318 0, CRI_CALCINIT); 1319 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1320 0, CRI_CALCINIT); 1321 } 1322 } 1323 1324 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1325 const struct intel_crtc_state *crtc_state) 1326 { 1327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1328 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1329 const struct intel_ddi_buf_trans *trans; 1330 int n_entries, ln; 1331 1332 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1333 return; 1334 1335 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1336 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1337 return; 1338 1339 for (ln = 0; ln < 2; ln++) { 1340 int level; 1341 1342 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1343 1344 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1345 1346 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1347 DKL_TX_PRESHOOT_COEFF_MASK | 1348 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1349 DKL_TX_VSWING_CONTROL_MASK, 1350 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1351 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1352 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1353 1354 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1355 1356 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1357 DKL_TX_PRESHOOT_COEFF_MASK | 1358 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1359 DKL_TX_VSWING_CONTROL_MASK, 1360 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1361 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1362 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1363 1364 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1365 DKL_TX_DP20BITMODE, 0); 1366 1367 if (IS_ALDERLAKE_P(dev_priv)) { 1368 u32 val; 1369 1370 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1371 if (ln == 0) { 1372 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1373 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1374 } else { 1375 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1376 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1377 } 1378 } else { 1379 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1380 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1381 } 1382 1383 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1384 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1385 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1386 val); 1387 } 1388 } 1389 } 1390 1391 static int translate_signal_level(struct intel_dp *intel_dp, 1392 u8 signal_levels) 1393 { 1394 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1395 int i; 1396 1397 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1398 if (index_to_dp_signal_levels[i] == signal_levels) 1399 return i; 1400 } 1401 1402 drm_WARN(&i915->drm, 1, 1403 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1404 signal_levels); 1405 1406 return 0; 1407 } 1408 1409 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1410 const struct intel_crtc_state *crtc_state, 1411 int lane) 1412 { 1413 u8 train_set = intel_dp->train_set[lane]; 1414 1415 if (intel_dp_is_uhbr(crtc_state)) { 1416 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1417 } else { 1418 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1419 DP_TRAIN_PRE_EMPHASIS_MASK); 1420 1421 return translate_signal_level(intel_dp, signal_levels); 1422 } 1423 } 1424 1425 int intel_ddi_level(struct intel_encoder *encoder, 1426 const struct intel_crtc_state *crtc_state, 1427 int lane) 1428 { 1429 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1430 const struct intel_ddi_buf_trans *trans; 1431 int level, n_entries; 1432 1433 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1434 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1435 return 0; 1436 1437 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1438 level = intel_ddi_hdmi_level(encoder, trans); 1439 else 1440 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1441 lane); 1442 1443 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1444 level = n_entries - 1; 1445 1446 return level; 1447 } 1448 1449 static void 1450 hsw_set_signal_levels(struct intel_encoder *encoder, 1451 const struct intel_crtc_state *crtc_state) 1452 { 1453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1454 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1455 int level = intel_ddi_level(encoder, crtc_state, 0); 1456 enum port port = encoder->port; 1457 u32 signal_levels; 1458 1459 if (has_iboost(dev_priv)) 1460 skl_ddi_set_iboost(encoder, crtc_state, level); 1461 1462 /* HDMI ignores the rest */ 1463 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1464 return; 1465 1466 signal_levels = DDI_BUF_TRANS_SELECT(level); 1467 1468 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1469 signal_levels); 1470 1471 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1472 intel_dp->DP |= signal_levels; 1473 1474 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1475 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1476 } 1477 1478 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1479 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1480 { 1481 mutex_lock(&i915->display.dpll.lock); 1482 1483 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1484 1485 /* 1486 * "This step and the step before must be 1487 * done with separate register writes." 1488 */ 1489 intel_de_rmw(i915, reg, clk_off, 0); 1490 1491 mutex_unlock(&i915->display.dpll.lock); 1492 } 1493 1494 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1495 u32 clk_off) 1496 { 1497 mutex_lock(&i915->display.dpll.lock); 1498 1499 intel_de_rmw(i915, reg, 0, clk_off); 1500 1501 mutex_unlock(&i915->display.dpll.lock); 1502 } 1503 1504 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1505 u32 clk_off) 1506 { 1507 return !(intel_de_read(i915, reg) & clk_off); 1508 } 1509 1510 static struct intel_shared_dpll * 1511 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1512 u32 clk_sel_mask, u32 clk_sel_shift) 1513 { 1514 enum intel_dpll_id id; 1515 1516 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1517 1518 return intel_get_shared_dpll_by_id(i915, id); 1519 } 1520 1521 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1522 const struct intel_crtc_state *crtc_state) 1523 { 1524 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1525 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1526 enum phy phy = intel_port_to_phy(i915, encoder->port); 1527 1528 if (drm_WARN_ON(&i915->drm, !pll)) 1529 return; 1530 1531 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1532 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1533 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1534 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1535 } 1536 1537 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1538 { 1539 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1540 enum phy phy = intel_port_to_phy(i915, encoder->port); 1541 1542 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1543 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1544 } 1545 1546 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1547 { 1548 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1549 enum phy phy = intel_port_to_phy(i915, encoder->port); 1550 1551 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1552 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1553 } 1554 1555 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1556 { 1557 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1558 enum phy phy = intel_port_to_phy(i915, encoder->port); 1559 1560 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1561 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1562 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1563 } 1564 1565 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1566 const struct intel_crtc_state *crtc_state) 1567 { 1568 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1569 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1570 enum phy phy = intel_port_to_phy(i915, encoder->port); 1571 1572 if (drm_WARN_ON(&i915->drm, !pll)) 1573 return; 1574 1575 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1576 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1578 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1579 } 1580 1581 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1582 { 1583 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1584 enum phy phy = intel_port_to_phy(i915, encoder->port); 1585 1586 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1587 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1588 } 1589 1590 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1591 { 1592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1593 enum phy phy = intel_port_to_phy(i915, encoder->port); 1594 1595 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1596 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1597 } 1598 1599 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1600 { 1601 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1602 enum phy phy = intel_port_to_phy(i915, encoder->port); 1603 1604 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1605 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1606 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1607 } 1608 1609 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1610 const struct intel_crtc_state *crtc_state) 1611 { 1612 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1613 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1614 enum phy phy = intel_port_to_phy(i915, encoder->port); 1615 1616 if (drm_WARN_ON(&i915->drm, !pll)) 1617 return; 1618 1619 /* 1620 * If we fail this, something went very wrong: first 2 PLLs should be 1621 * used by first 2 phys and last 2 PLLs by last phys 1622 */ 1623 if (drm_WARN_ON(&i915->drm, 1624 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1625 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1626 return; 1627 1628 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1629 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1630 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1631 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1632 } 1633 1634 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1635 { 1636 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1637 enum phy phy = intel_port_to_phy(i915, encoder->port); 1638 1639 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1640 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1641 } 1642 1643 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1644 { 1645 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1646 enum phy phy = intel_port_to_phy(i915, encoder->port); 1647 1648 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1649 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1650 } 1651 1652 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1653 { 1654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1655 enum phy phy = intel_port_to_phy(i915, encoder->port); 1656 enum intel_dpll_id id; 1657 u32 val; 1658 1659 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1660 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1661 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1662 id = val; 1663 1664 /* 1665 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1666 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1667 * bit for phy C and D. 1668 */ 1669 if (phy >= PHY_C) 1670 id += DPLL_ID_DG1_DPLL2; 1671 1672 return intel_get_shared_dpll_by_id(i915, id); 1673 } 1674 1675 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1676 const struct intel_crtc_state *crtc_state) 1677 { 1678 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1679 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1680 enum phy phy = intel_port_to_phy(i915, encoder->port); 1681 1682 if (drm_WARN_ON(&i915->drm, !pll)) 1683 return; 1684 1685 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1686 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1688 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1689 } 1690 1691 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1692 { 1693 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1694 enum phy phy = intel_port_to_phy(i915, encoder->port); 1695 1696 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1697 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1698 } 1699 1700 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1701 { 1702 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1703 enum phy phy = intel_port_to_phy(i915, encoder->port); 1704 1705 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1706 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1707 } 1708 1709 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1710 { 1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1712 enum phy phy = intel_port_to_phy(i915, encoder->port); 1713 1714 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1715 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1716 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1717 } 1718 1719 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1720 const struct intel_crtc_state *crtc_state) 1721 { 1722 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1723 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1724 enum port port = encoder->port; 1725 1726 if (drm_WARN_ON(&i915->drm, !pll)) 1727 return; 1728 1729 /* 1730 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1731 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1732 */ 1733 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1734 1735 icl_ddi_combo_enable_clock(encoder, crtc_state); 1736 } 1737 1738 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1739 { 1740 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1741 enum port port = encoder->port; 1742 1743 icl_ddi_combo_disable_clock(encoder); 1744 1745 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1746 } 1747 1748 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1749 { 1750 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1751 enum port port = encoder->port; 1752 u32 tmp; 1753 1754 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1755 1756 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1757 return false; 1758 1759 return icl_ddi_combo_is_clock_enabled(encoder); 1760 } 1761 1762 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1763 const struct intel_crtc_state *crtc_state) 1764 { 1765 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1766 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1767 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1768 enum port port = encoder->port; 1769 1770 if (drm_WARN_ON(&i915->drm, !pll)) 1771 return; 1772 1773 intel_de_write(i915, DDI_CLK_SEL(port), 1774 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1775 1776 mutex_lock(&i915->display.dpll.lock); 1777 1778 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1779 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1780 1781 mutex_unlock(&i915->display.dpll.lock); 1782 } 1783 1784 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1785 { 1786 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1787 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1788 enum port port = encoder->port; 1789 1790 mutex_lock(&i915->display.dpll.lock); 1791 1792 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1793 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1794 1795 mutex_unlock(&i915->display.dpll.lock); 1796 1797 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1798 } 1799 1800 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1801 { 1802 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1803 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1804 enum port port = encoder->port; 1805 u32 tmp; 1806 1807 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1808 1809 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1810 return false; 1811 1812 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1813 1814 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1815 } 1816 1817 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1818 { 1819 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1820 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1821 enum port port = encoder->port; 1822 enum intel_dpll_id id; 1823 u32 tmp; 1824 1825 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1826 1827 switch (tmp & DDI_CLK_SEL_MASK) { 1828 case DDI_CLK_SEL_TBT_162: 1829 case DDI_CLK_SEL_TBT_270: 1830 case DDI_CLK_SEL_TBT_540: 1831 case DDI_CLK_SEL_TBT_810: 1832 id = DPLL_ID_ICL_TBTPLL; 1833 break; 1834 case DDI_CLK_SEL_MG: 1835 id = icl_tc_port_to_pll_id(tc_port); 1836 break; 1837 default: 1838 MISSING_CASE(tmp); 1839 fallthrough; 1840 case DDI_CLK_SEL_NONE: 1841 return NULL; 1842 } 1843 1844 return intel_get_shared_dpll_by_id(i915, id); 1845 } 1846 1847 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1848 { 1849 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1850 enum intel_dpll_id id; 1851 1852 switch (encoder->port) { 1853 case PORT_A: 1854 id = DPLL_ID_SKL_DPLL0; 1855 break; 1856 case PORT_B: 1857 id = DPLL_ID_SKL_DPLL1; 1858 break; 1859 case PORT_C: 1860 id = DPLL_ID_SKL_DPLL2; 1861 break; 1862 default: 1863 MISSING_CASE(encoder->port); 1864 return NULL; 1865 } 1866 1867 return intel_get_shared_dpll_by_id(i915, id); 1868 } 1869 1870 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1871 const struct intel_crtc_state *crtc_state) 1872 { 1873 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1874 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1875 enum port port = encoder->port; 1876 1877 if (drm_WARN_ON(&i915->drm, !pll)) 1878 return; 1879 1880 mutex_lock(&i915->display.dpll.lock); 1881 1882 intel_de_rmw(i915, DPLL_CTRL2, 1883 DPLL_CTRL2_DDI_CLK_OFF(port) | 1884 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1885 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1886 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1887 1888 mutex_unlock(&i915->display.dpll.lock); 1889 } 1890 1891 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1892 { 1893 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1894 enum port port = encoder->port; 1895 1896 mutex_lock(&i915->display.dpll.lock); 1897 1898 intel_de_rmw(i915, DPLL_CTRL2, 1899 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1900 1901 mutex_unlock(&i915->display.dpll.lock); 1902 } 1903 1904 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1905 { 1906 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1907 enum port port = encoder->port; 1908 1909 /* 1910 * FIXME Not sure if the override affects both 1911 * the PLL selection and the CLK_OFF bit. 1912 */ 1913 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1914 } 1915 1916 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1917 { 1918 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1919 enum port port = encoder->port; 1920 enum intel_dpll_id id; 1921 u32 tmp; 1922 1923 tmp = intel_de_read(i915, DPLL_CTRL2); 1924 1925 /* 1926 * FIXME Not sure if the override affects both 1927 * the PLL selection and the CLK_OFF bit. 1928 */ 1929 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1930 return NULL; 1931 1932 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1933 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1934 1935 return intel_get_shared_dpll_by_id(i915, id); 1936 } 1937 1938 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1939 const struct intel_crtc_state *crtc_state) 1940 { 1941 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1942 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1943 enum port port = encoder->port; 1944 1945 if (drm_WARN_ON(&i915->drm, !pll)) 1946 return; 1947 1948 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1949 } 1950 1951 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1952 { 1953 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1954 enum port port = encoder->port; 1955 1956 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1957 } 1958 1959 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1960 { 1961 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1962 enum port port = encoder->port; 1963 1964 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1965 } 1966 1967 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1968 { 1969 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1970 enum port port = encoder->port; 1971 enum intel_dpll_id id; 1972 u32 tmp; 1973 1974 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1975 1976 switch (tmp & PORT_CLK_SEL_MASK) { 1977 case PORT_CLK_SEL_WRPLL1: 1978 id = DPLL_ID_WRPLL1; 1979 break; 1980 case PORT_CLK_SEL_WRPLL2: 1981 id = DPLL_ID_WRPLL2; 1982 break; 1983 case PORT_CLK_SEL_SPLL: 1984 id = DPLL_ID_SPLL; 1985 break; 1986 case PORT_CLK_SEL_LCPLL_810: 1987 id = DPLL_ID_LCPLL_810; 1988 break; 1989 case PORT_CLK_SEL_LCPLL_1350: 1990 id = DPLL_ID_LCPLL_1350; 1991 break; 1992 case PORT_CLK_SEL_LCPLL_2700: 1993 id = DPLL_ID_LCPLL_2700; 1994 break; 1995 default: 1996 MISSING_CASE(tmp); 1997 fallthrough; 1998 case PORT_CLK_SEL_NONE: 1999 return NULL; 2000 } 2001 2002 return intel_get_shared_dpll_by_id(i915, id); 2003 } 2004 2005 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2006 const struct intel_crtc_state *crtc_state) 2007 { 2008 if (encoder->enable_clock) 2009 encoder->enable_clock(encoder, crtc_state); 2010 } 2011 2012 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2013 { 2014 if (encoder->disable_clock) 2015 encoder->disable_clock(encoder); 2016 } 2017 2018 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2019 { 2020 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2021 u32 port_mask; 2022 bool ddi_clk_needed; 2023 2024 /* 2025 * In case of DP MST, we sanitize the primary encoder only, not the 2026 * virtual ones. 2027 */ 2028 if (encoder->type == INTEL_OUTPUT_DP_MST) 2029 return; 2030 2031 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2032 u8 pipe_mask; 2033 bool is_mst; 2034 2035 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2036 /* 2037 * In the unlikely case that BIOS enables DP in MST mode, just 2038 * warn since our MST HW readout is incomplete. 2039 */ 2040 if (drm_WARN_ON(&i915->drm, is_mst)) 2041 return; 2042 } 2043 2044 port_mask = BIT(encoder->port); 2045 ddi_clk_needed = encoder->base.crtc; 2046 2047 if (encoder->type == INTEL_OUTPUT_DSI) { 2048 struct intel_encoder *other_encoder; 2049 2050 port_mask = intel_dsi_encoder_ports(encoder); 2051 /* 2052 * Sanity check that we haven't incorrectly registered another 2053 * encoder using any of the ports of this DSI encoder. 2054 */ 2055 for_each_intel_encoder(&i915->drm, other_encoder) { 2056 if (other_encoder == encoder) 2057 continue; 2058 2059 if (drm_WARN_ON(&i915->drm, 2060 port_mask & BIT(other_encoder->port))) 2061 return; 2062 } 2063 /* 2064 * For DSI we keep the ddi clocks gated 2065 * except during enable/disable sequence. 2066 */ 2067 ddi_clk_needed = false; 2068 } 2069 2070 if (ddi_clk_needed || !encoder->is_clock_enabled || 2071 !encoder->is_clock_enabled(encoder)) 2072 return; 2073 2074 drm_notice(&i915->drm, 2075 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2076 encoder->base.base.id, encoder->base.name); 2077 2078 encoder->disable_clock(encoder); 2079 } 2080 2081 static void 2082 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2083 const struct intel_crtc_state *crtc_state) 2084 { 2085 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2086 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2087 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2088 u32 ln0, ln1, pin_assignment; 2089 u8 width; 2090 2091 if (!intel_phy_is_tc(dev_priv, phy) || 2092 intel_tc_port_in_tbt_alt_mode(dig_port)) 2093 return; 2094 2095 if (DISPLAY_VER(dev_priv) >= 12) { 2096 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2097 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2098 } else { 2099 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2100 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2101 } 2102 2103 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2104 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2105 2106 /* DPPATC */ 2107 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2108 width = crtc_state->lane_count; 2109 2110 switch (pin_assignment) { 2111 case 0x0: 2112 drm_WARN_ON(&dev_priv->drm, 2113 !intel_tc_port_in_legacy_mode(dig_port)); 2114 if (width == 1) { 2115 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2116 } else { 2117 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2118 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2119 } 2120 break; 2121 case 0x1: 2122 if (width == 4) { 2123 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2124 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2125 } 2126 break; 2127 case 0x2: 2128 if (width == 2) { 2129 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2130 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2131 } 2132 break; 2133 case 0x3: 2134 case 0x5: 2135 if (width == 1) { 2136 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2137 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2138 } else { 2139 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2140 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2141 } 2142 break; 2143 case 0x4: 2144 case 0x6: 2145 if (width == 1) { 2146 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2147 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2148 } else { 2149 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2150 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2151 } 2152 break; 2153 default: 2154 MISSING_CASE(pin_assignment); 2155 } 2156 2157 if (DISPLAY_VER(dev_priv) >= 12) { 2158 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2159 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2160 } else { 2161 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2162 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2163 } 2164 } 2165 2166 static enum transcoder 2167 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2168 { 2169 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2170 return crtc_state->mst_master_transcoder; 2171 else 2172 return crtc_state->cpu_transcoder; 2173 } 2174 2175 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2176 const struct intel_crtc_state *crtc_state) 2177 { 2178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2179 2180 if (DISPLAY_VER(dev_priv) >= 12) 2181 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2182 else 2183 return DP_TP_CTL(encoder->port); 2184 } 2185 2186 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2187 const struct intel_crtc_state *crtc_state) 2188 { 2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2190 2191 if (DISPLAY_VER(dev_priv) >= 12) 2192 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2193 else 2194 return DP_TP_STATUS(encoder->port); 2195 } 2196 2197 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2198 const struct intel_crtc_state *crtc_state, 2199 bool enable) 2200 { 2201 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2202 2203 if (!crtc_state->vrr.enable) 2204 return; 2205 2206 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2207 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2208 drm_dbg_kms(&i915->drm, 2209 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2210 str_enable_disable(enable)); 2211 } 2212 2213 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2214 const struct intel_crtc_state *crtc_state, 2215 bool enable) 2216 { 2217 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2218 2219 if (!crtc_state->fec_enable) 2220 return; 2221 2222 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2223 enable ? DP_FEC_READY : 0) <= 0) 2224 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2225 enable ? "enabled" : "disabled"); 2226 2227 if (enable && 2228 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2229 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2230 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2231 } 2232 2233 static int read_fec_detected_status(struct drm_dp_aux *aux) 2234 { 2235 int ret; 2236 u8 status; 2237 2238 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2239 if (ret < 0) 2240 return ret; 2241 2242 return status; 2243 } 2244 2245 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2246 { 2247 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2248 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2249 int status; 2250 int err; 2251 2252 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2253 status & mask || status < 0, 2254 10000, 200000); 2255 2256 if (!err && status >= 0) 2257 return; 2258 2259 if (err == -ETIMEDOUT) 2260 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2261 str_enabled_disabled(enabled)); 2262 else 2263 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2264 } 2265 2266 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2267 const struct intel_crtc_state *crtc_state, 2268 bool enabled) 2269 { 2270 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2271 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2272 int ret; 2273 2274 if (!crtc_state->fec_enable) 2275 return; 2276 2277 if (enabled) 2278 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2279 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2280 else 2281 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2282 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2283 2284 if (ret) 2285 drm_err(&i915->drm, 2286 "Timeout waiting for FEC live state to get %s\n", 2287 str_enabled_disabled(enabled)); 2288 2289 /* 2290 * At least the Synoptics MST hub doesn't set the detected flag for 2291 * FEC decoding disabling so skip waiting for that. 2292 */ 2293 if (enabled) 2294 wait_for_fec_detected(&intel_dp->aux, enabled); 2295 } 2296 2297 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2298 const struct intel_crtc_state *crtc_state) 2299 { 2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2301 2302 if (!crtc_state->fec_enable) 2303 return; 2304 2305 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2306 0, DP_TP_CTL_FEC_ENABLE); 2307 } 2308 2309 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2310 const struct intel_crtc_state *crtc_state) 2311 { 2312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2313 2314 if (!crtc_state->fec_enable) 2315 return; 2316 2317 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2318 DP_TP_CTL_FEC_ENABLE, 0); 2319 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2320 } 2321 2322 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2323 const struct intel_crtc_state *crtc_state) 2324 { 2325 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2326 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2327 enum phy phy = intel_port_to_phy(i915, encoder->port); 2328 2329 if (intel_phy_is_combo(i915, phy)) { 2330 bool lane_reversal = 2331 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2332 2333 intel_combo_phy_power_up_lanes(i915, phy, false, 2334 crtc_state->lane_count, 2335 lane_reversal); 2336 } 2337 } 2338 2339 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2340 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2341 { 2342 if (IS_ALDERLAKE_P(i915)) 2343 return BIT(PIPE_A) | BIT(PIPE_B); 2344 else 2345 return BIT(PIPE_A); 2346 } 2347 2348 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2349 struct intel_crtc_state *pipe_config) 2350 { 2351 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2352 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2353 enum pipe pipe = crtc->pipe; 2354 u32 dss1; 2355 2356 if (!HAS_MSO(i915)) 2357 return; 2358 2359 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2360 2361 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2362 if (!pipe_config->splitter.enable) 2363 return; 2364 2365 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2366 pipe_config->splitter.enable = false; 2367 return; 2368 } 2369 2370 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2371 default: 2372 drm_WARN(&i915->drm, true, 2373 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2374 fallthrough; 2375 case SPLITTER_CONFIGURATION_2_SEGMENT: 2376 pipe_config->splitter.link_count = 2; 2377 break; 2378 case SPLITTER_CONFIGURATION_4_SEGMENT: 2379 pipe_config->splitter.link_count = 4; 2380 break; 2381 } 2382 2383 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2384 } 2385 2386 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2387 { 2388 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2389 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2390 enum pipe pipe = crtc->pipe; 2391 u32 dss1 = 0; 2392 2393 if (!HAS_MSO(i915)) 2394 return; 2395 2396 if (crtc_state->splitter.enable) { 2397 dss1 |= SPLITTER_ENABLE; 2398 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2399 if (crtc_state->splitter.link_count == 2) 2400 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2401 else 2402 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2403 } 2404 2405 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2406 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2407 OVERLAP_PIXELS_MASK, dss1); 2408 } 2409 2410 static u8 mtl_get_port_width(u8 lane_count) 2411 { 2412 switch (lane_count) { 2413 case 1: 2414 return 0; 2415 case 2: 2416 return 1; 2417 case 3: 2418 return 4; 2419 case 4: 2420 return 3; 2421 default: 2422 MISSING_CASE(lane_count); 2423 return 4; 2424 } 2425 } 2426 2427 static void 2428 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2429 { 2430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2431 enum port port = encoder->port; 2432 2433 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0, 2434 XELPDP_PORT_BUF_D2D_LINK_ENABLE); 2435 2436 if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & 2437 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) { 2438 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n", 2439 port_name(port)); 2440 } 2441 } 2442 2443 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2444 const struct intel_crtc_state *crtc_state) 2445 { 2446 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2447 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2448 enum port port = encoder->port; 2449 u32 val; 2450 2451 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)); 2452 val &= ~XELPDP_PORT_WIDTH_MASK; 2453 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2454 2455 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2456 if (intel_dp_is_uhbr(crtc_state)) 2457 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2458 else 2459 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2460 2461 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2462 val |= XELPDP_PORT_REVERSAL; 2463 2464 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val); 2465 } 2466 2467 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2468 { 2469 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2470 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2471 u32 val; 2472 2473 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2474 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2475 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), 2476 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2477 } 2478 2479 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2480 struct intel_encoder *encoder, 2481 const struct intel_crtc_state *crtc_state, 2482 const struct drm_connector_state *conn_state) 2483 { 2484 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2485 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2486 2487 intel_dp_set_link_params(intel_dp, 2488 crtc_state->port_clock, 2489 crtc_state->lane_count); 2490 2491 /* 2492 * We only configure what the register value will be here. Actual 2493 * enabling happens during link training farther down. 2494 */ 2495 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2496 2497 /* 2498 * 1. Enable Power Wells 2499 * 2500 * This was handled at the beginning of intel_atomic_commit_tail(), 2501 * before we called down into this function. 2502 */ 2503 2504 /* 2. PMdemand was already set */ 2505 2506 /* 3. Select Thunderbolt */ 2507 mtl_port_buf_ctl_io_selection(encoder); 2508 2509 /* 4. Enable Panel Power if PPS is required */ 2510 intel_pps_on(intel_dp); 2511 2512 /* 5. Enable the port PLL */ 2513 intel_ddi_enable_clock(encoder, crtc_state); 2514 2515 /* 2516 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2517 * Transcoder. 2518 */ 2519 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2520 2521 /* 2522 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2523 */ 2524 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2525 2526 /* 2527 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2528 * Transport Select 2529 */ 2530 intel_ddi_config_transcoder_func(encoder, crtc_state); 2531 2532 /* 2533 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2534 */ 2535 intel_ddi_mso_configure(crtc_state); 2536 2537 if (!is_mst) 2538 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2539 2540 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2541 if (!is_mst) 2542 intel_dp_sink_enable_decompression(state, 2543 to_intel_connector(conn_state->connector), 2544 crtc_state); 2545 2546 /* 2547 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2548 * in the FEC_CONFIGURATION register to 1 before initiating link 2549 * training 2550 */ 2551 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2552 2553 intel_dp_check_frl_training(intel_dp); 2554 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2555 2556 /* 2557 * 6. The rest of the below are substeps under the bspec's "Enable and 2558 * Train Display Port" step. Note that steps that are specific to 2559 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2560 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2561 * us when active_mst_links==0, so any steps designated for "single 2562 * stream or multi-stream master transcoder" can just be performed 2563 * unconditionally here. 2564 * 2565 * mtl_ddi_prepare_link_retrain() that is called by 2566 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2567 * 6.i and 6.j 2568 * 2569 * 6.k Follow DisplayPort specification training sequence (see notes for 2570 * failure handling) 2571 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2572 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2573 * (timeout after 800 us) 2574 */ 2575 intel_dp_start_link_train(intel_dp, crtc_state); 2576 2577 /* 6.n Set DP_TP_CTL link training to Normal */ 2578 if (!is_trans_port_sync_mode(crtc_state)) 2579 intel_dp_stop_link_train(intel_dp, crtc_state); 2580 2581 /* 6.o Configure and enable FEC if needed */ 2582 intel_ddi_enable_fec(encoder, crtc_state); 2583 2584 if (!is_mst) 2585 intel_dsc_dp_pps_write(encoder, crtc_state); 2586 } 2587 2588 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2589 struct intel_encoder *encoder, 2590 const struct intel_crtc_state *crtc_state, 2591 const struct drm_connector_state *conn_state) 2592 { 2593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2595 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2596 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2597 2598 intel_dp_set_link_params(intel_dp, 2599 crtc_state->port_clock, 2600 crtc_state->lane_count); 2601 2602 /* 2603 * We only configure what the register value will be here. Actual 2604 * enabling happens during link training farther down. 2605 */ 2606 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2607 2608 /* 2609 * 1. Enable Power Wells 2610 * 2611 * This was handled at the beginning of intel_atomic_commit_tail(), 2612 * before we called down into this function. 2613 */ 2614 2615 /* 2. Enable Panel Power if PPS is required */ 2616 intel_pps_on(intel_dp); 2617 2618 /* 2619 * 3. For non-TBT Type-C ports, set FIA lane count 2620 * (DFLEXDPSP.DPX4TXLATC) 2621 * 2622 * This was done before tgl_ddi_pre_enable_dp by 2623 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2624 */ 2625 2626 /* 2627 * 4. Enable the port PLL. 2628 * 2629 * The PLL enabling itself was already done before this function by 2630 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2631 * configure the PLL to port mapping here. 2632 */ 2633 intel_ddi_enable_clock(encoder, crtc_state); 2634 2635 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2636 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2637 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2638 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2639 dig_port->ddi_io_power_domain); 2640 } 2641 2642 /* 6. Program DP_MODE */ 2643 icl_program_mg_dp_mode(dig_port, crtc_state); 2644 2645 /* 2646 * 7. The rest of the below are substeps under the bspec's "Enable and 2647 * Train Display Port" step. Note that steps that are specific to 2648 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2649 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2650 * us when active_mst_links==0, so any steps designated for "single 2651 * stream or multi-stream master transcoder" can just be performed 2652 * unconditionally here. 2653 */ 2654 2655 /* 2656 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2657 * Transcoder. 2658 */ 2659 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2660 2661 if (HAS_DP20(dev_priv)) 2662 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2663 2664 /* 2665 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2666 * Transport Select 2667 */ 2668 intel_ddi_config_transcoder_func(encoder, crtc_state); 2669 2670 /* 2671 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2672 * selected 2673 * 2674 * This will be handled by the intel_dp_start_link_train() farther 2675 * down this function. 2676 */ 2677 2678 /* 7.e Configure voltage swing and related IO settings */ 2679 encoder->set_signal_levels(encoder, crtc_state); 2680 2681 /* 2682 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2683 * the used lanes of the DDI. 2684 */ 2685 intel_ddi_power_up_lanes(encoder, crtc_state); 2686 2687 /* 2688 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2689 */ 2690 intel_ddi_mso_configure(crtc_state); 2691 2692 if (!is_mst) 2693 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2694 2695 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2696 if (!is_mst) 2697 intel_dp_sink_enable_decompression(state, 2698 to_intel_connector(conn_state->connector), 2699 crtc_state); 2700 /* 2701 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2702 * in the FEC_CONFIGURATION register to 1 before initiating link 2703 * training 2704 */ 2705 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2706 2707 intel_dp_check_frl_training(intel_dp); 2708 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2709 2710 /* 2711 * 7.i Follow DisplayPort specification training sequence (see notes for 2712 * failure handling) 2713 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2714 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2715 * (timeout after 800 us) 2716 */ 2717 intel_dp_start_link_train(intel_dp, crtc_state); 2718 2719 /* 7.k Set DP_TP_CTL link training to Normal */ 2720 if (!is_trans_port_sync_mode(crtc_state)) 2721 intel_dp_stop_link_train(intel_dp, crtc_state); 2722 2723 /* 7.l Configure and enable FEC if needed */ 2724 intel_ddi_enable_fec(encoder, crtc_state); 2725 2726 if (!is_mst) 2727 intel_dsc_dp_pps_write(encoder, crtc_state); 2728 } 2729 2730 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2731 struct intel_encoder *encoder, 2732 const struct intel_crtc_state *crtc_state, 2733 const struct drm_connector_state *conn_state) 2734 { 2735 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2736 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2737 enum port port = encoder->port; 2738 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2739 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2740 2741 if (DISPLAY_VER(dev_priv) < 11) 2742 drm_WARN_ON(&dev_priv->drm, 2743 is_mst && (port == PORT_A || port == PORT_E)); 2744 else 2745 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2746 2747 intel_dp_set_link_params(intel_dp, 2748 crtc_state->port_clock, 2749 crtc_state->lane_count); 2750 2751 /* 2752 * We only configure what the register value will be here. Actual 2753 * enabling happens during link training farther down. 2754 */ 2755 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2756 2757 intel_pps_on(intel_dp); 2758 2759 intel_ddi_enable_clock(encoder, crtc_state); 2760 2761 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2762 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2763 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2764 dig_port->ddi_io_power_domain); 2765 } 2766 2767 icl_program_mg_dp_mode(dig_port, crtc_state); 2768 2769 if (has_buf_trans_select(dev_priv)) 2770 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2771 2772 encoder->set_signal_levels(encoder, crtc_state); 2773 2774 intel_ddi_power_up_lanes(encoder, crtc_state); 2775 2776 if (!is_mst) 2777 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2778 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2779 if (!is_mst) 2780 intel_dp_sink_enable_decompression(state, 2781 to_intel_connector(conn_state->connector), 2782 crtc_state); 2783 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2784 intel_dp_start_link_train(intel_dp, crtc_state); 2785 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2786 !is_trans_port_sync_mode(crtc_state)) 2787 intel_dp_stop_link_train(intel_dp, crtc_state); 2788 2789 intel_ddi_enable_fec(encoder, crtc_state); 2790 2791 if (!is_mst) { 2792 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2793 intel_dsc_dp_pps_write(encoder, crtc_state); 2794 } 2795 } 2796 2797 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2798 struct intel_encoder *encoder, 2799 const struct intel_crtc_state *crtc_state, 2800 const struct drm_connector_state *conn_state) 2801 { 2802 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2803 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2804 2805 if (HAS_DP20(dev_priv)) { 2806 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2807 crtc_state); 2808 if (crtc_state->has_panel_replay) 2809 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 2810 DP_PANEL_REPLAY_ENABLE); 2811 } 2812 2813 if (DISPLAY_VER(dev_priv) >= 14) 2814 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2815 else if (DISPLAY_VER(dev_priv) >= 12) 2816 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2817 else 2818 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2819 2820 /* MST will call a setting of MSA after an allocating of Virtual Channel 2821 * from MST encoder pre_enable callback. 2822 */ 2823 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2824 intel_ddi_set_dp_msa(crtc_state, conn_state); 2825 } 2826 2827 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2828 struct intel_encoder *encoder, 2829 const struct intel_crtc_state *crtc_state, 2830 const struct drm_connector_state *conn_state) 2831 { 2832 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2833 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2835 2836 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2837 intel_ddi_enable_clock(encoder, crtc_state); 2838 2839 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2840 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2841 dig_port->ddi_io_power_domain); 2842 2843 icl_program_mg_dp_mode(dig_port, crtc_state); 2844 2845 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2846 2847 dig_port->set_infoframes(encoder, 2848 crtc_state->has_infoframe, 2849 crtc_state, conn_state); 2850 } 2851 2852 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2853 struct intel_encoder *encoder, 2854 const struct intel_crtc_state *crtc_state, 2855 const struct drm_connector_state *conn_state) 2856 { 2857 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2859 enum pipe pipe = crtc->pipe; 2860 2861 /* 2862 * When called from DP MST code: 2863 * - conn_state will be NULL 2864 * - encoder will be the main encoder (ie. mst->primary) 2865 * - the main connector associated with this port 2866 * won't be active or linked to a crtc 2867 * - crtc_state will be the state of the first stream to 2868 * be activated on this port, and it may not be the same 2869 * stream that will be deactivated last, but each stream 2870 * should have a state that is identical when it comes to 2871 * the DP link parameteres 2872 */ 2873 2874 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2875 2876 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2877 2878 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2879 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2880 conn_state); 2881 } else { 2882 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2883 2884 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2885 conn_state); 2886 2887 /* FIXME precompute everything properly */ 2888 /* FIXME how do we turn infoframes off again? */ 2889 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2890 dig_port->set_infoframes(encoder, 2891 crtc_state->has_infoframe, 2892 crtc_state, conn_state); 2893 } 2894 } 2895 2896 static void 2897 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2898 { 2899 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2900 enum port port = encoder->port; 2901 2902 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 2903 XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0); 2904 2905 if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & 2906 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) 2907 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n", 2908 port_name(port)); 2909 } 2910 2911 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2912 const struct intel_crtc_state *crtc_state) 2913 { 2914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2915 enum port port = encoder->port; 2916 u32 val; 2917 2918 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2919 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2920 if (val & DDI_BUF_CTL_ENABLE) { 2921 val &= ~DDI_BUF_CTL_ENABLE; 2922 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2923 2924 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2925 mtl_wait_ddi_buf_idle(dev_priv, port); 2926 } 2927 2928 /* 3.d Disable D2D Link */ 2929 mtl_ddi_disable_d2d_link(encoder); 2930 2931 /* 3.e Disable DP_TP_CTL */ 2932 if (intel_crtc_has_dp_encoder(crtc_state)) { 2933 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2934 DP_TP_CTL_ENABLE, 0); 2935 } 2936 } 2937 2938 static void disable_ddi_buf(struct intel_encoder *encoder, 2939 const struct intel_crtc_state *crtc_state) 2940 { 2941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2942 enum port port = encoder->port; 2943 bool wait = false; 2944 u32 val; 2945 2946 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2947 if (val & DDI_BUF_CTL_ENABLE) { 2948 val &= ~DDI_BUF_CTL_ENABLE; 2949 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2950 wait = true; 2951 } 2952 2953 if (intel_crtc_has_dp_encoder(crtc_state)) 2954 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2955 DP_TP_CTL_ENABLE, 0); 2956 2957 intel_ddi_disable_fec(encoder, crtc_state); 2958 2959 if (wait) 2960 intel_wait_ddi_buf_idle(dev_priv, port); 2961 } 2962 2963 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2964 const struct intel_crtc_state *crtc_state) 2965 { 2966 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2967 2968 if (DISPLAY_VER(dev_priv) >= 14) { 2969 mtl_disable_ddi_buf(encoder, crtc_state); 2970 2971 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2972 intel_ddi_disable_fec(encoder, crtc_state); 2973 } else { 2974 disable_ddi_buf(encoder, crtc_state); 2975 } 2976 2977 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2978 } 2979 2980 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2981 struct intel_encoder *encoder, 2982 const struct intel_crtc_state *old_crtc_state, 2983 const struct drm_connector_state *old_conn_state) 2984 { 2985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2986 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2987 struct intel_dp *intel_dp = &dig_port->dp; 2988 intel_wakeref_t wakeref; 2989 bool is_mst = intel_crtc_has_type(old_crtc_state, 2990 INTEL_OUTPUT_DP_MST); 2991 2992 if (!is_mst) 2993 intel_dp_set_infoframes(encoder, false, 2994 old_crtc_state, old_conn_state); 2995 2996 /* 2997 * Power down sink before disabling the port, otherwise we end 2998 * up getting interrupts from the sink on detecting link loss. 2999 */ 3000 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3001 3002 if (DISPLAY_VER(dev_priv) >= 12) { 3003 if (is_mst) { 3004 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3005 3006 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 3007 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3008 0); 3009 } 3010 } else { 3011 if (!is_mst) 3012 intel_ddi_disable_transcoder_clock(old_crtc_state); 3013 } 3014 3015 intel_disable_ddi_buf(encoder, old_crtc_state); 3016 3017 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3018 3019 /* 3020 * From TGL spec: "If single stream or multi-stream master transcoder: 3021 * Configure Transcoder Clock select to direct no clock to the 3022 * transcoder" 3023 */ 3024 if (DISPLAY_VER(dev_priv) >= 12) 3025 intel_ddi_disable_transcoder_clock(old_crtc_state); 3026 3027 intel_pps_vdd_on(intel_dp); 3028 intel_pps_off(intel_dp); 3029 3030 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3031 3032 if (wakeref) 3033 intel_display_power_put(dev_priv, 3034 dig_port->ddi_io_power_domain, 3035 wakeref); 3036 3037 intel_ddi_disable_clock(encoder); 3038 3039 /* De-select Thunderbolt */ 3040 if (DISPLAY_VER(dev_priv) >= 14) 3041 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port), 3042 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3043 } 3044 3045 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3046 struct intel_encoder *encoder, 3047 const struct intel_crtc_state *old_crtc_state, 3048 const struct drm_connector_state *old_conn_state) 3049 { 3050 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3051 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3052 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3053 intel_wakeref_t wakeref; 3054 3055 dig_port->set_infoframes(encoder, false, 3056 old_crtc_state, old_conn_state); 3057 3058 if (DISPLAY_VER(dev_priv) < 12) 3059 intel_ddi_disable_transcoder_clock(old_crtc_state); 3060 3061 intel_disable_ddi_buf(encoder, old_crtc_state); 3062 3063 if (DISPLAY_VER(dev_priv) >= 12) 3064 intel_ddi_disable_transcoder_clock(old_crtc_state); 3065 3066 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3067 if (wakeref) 3068 intel_display_power_put(dev_priv, 3069 dig_port->ddi_io_power_domain, 3070 wakeref); 3071 3072 intel_ddi_disable_clock(encoder); 3073 3074 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3075 } 3076 3077 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3078 struct intel_encoder *encoder, 3079 const struct intel_crtc_state *old_crtc_state, 3080 const struct drm_connector_state *old_conn_state) 3081 { 3082 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3083 struct intel_crtc *slave_crtc; 3084 3085 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3086 intel_crtc_vblank_off(old_crtc_state); 3087 3088 intel_disable_transcoder(old_crtc_state); 3089 3090 intel_ddi_disable_transcoder_func(old_crtc_state); 3091 3092 intel_dsc_disable(old_crtc_state); 3093 3094 if (DISPLAY_VER(dev_priv) >= 9) 3095 skl_scaler_disable(old_crtc_state); 3096 else 3097 ilk_pfit_disable(old_crtc_state); 3098 } 3099 3100 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 3101 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 3102 const struct intel_crtc_state *old_slave_crtc_state = 3103 intel_atomic_get_old_crtc_state(state, slave_crtc); 3104 3105 intel_crtc_vblank_off(old_slave_crtc_state); 3106 3107 intel_dsc_disable(old_slave_crtc_state); 3108 skl_scaler_disable(old_slave_crtc_state); 3109 } 3110 3111 /* 3112 * When called from DP MST code: 3113 * - old_conn_state will be NULL 3114 * - encoder will be the main encoder (ie. mst->primary) 3115 * - the main connector associated with this port 3116 * won't be active or linked to a crtc 3117 * - old_crtc_state will be the state of the last stream to 3118 * be deactivated on this port, and it may not be the same 3119 * stream that was activated last, but each stream 3120 * should have a state that is identical when it comes to 3121 * the DP link parameteres 3122 */ 3123 3124 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3125 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3126 old_conn_state); 3127 else 3128 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3129 old_conn_state); 3130 } 3131 3132 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3133 struct intel_encoder *encoder, 3134 const struct intel_crtc_state *old_crtc_state, 3135 const struct drm_connector_state *old_conn_state) 3136 { 3137 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3138 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3139 enum phy phy = intel_port_to_phy(i915, encoder->port); 3140 bool is_tc_port = intel_phy_is_tc(i915, phy); 3141 3142 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3143 3144 if (is_tc_port) 3145 intel_tc_port_put_link(dig_port); 3146 } 3147 3148 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3149 struct intel_encoder *encoder, 3150 const struct intel_crtc_state *crtc_state) 3151 { 3152 const struct drm_connector_state *conn_state; 3153 struct drm_connector *conn; 3154 int i; 3155 3156 if (!crtc_state->sync_mode_slaves_mask) 3157 return; 3158 3159 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3160 struct intel_encoder *slave_encoder = 3161 to_intel_encoder(conn_state->best_encoder); 3162 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3163 const struct intel_crtc_state *slave_crtc_state; 3164 3165 if (!slave_crtc) 3166 continue; 3167 3168 slave_crtc_state = 3169 intel_atomic_get_new_crtc_state(state, slave_crtc); 3170 3171 if (slave_crtc_state->master_transcoder != 3172 crtc_state->cpu_transcoder) 3173 continue; 3174 3175 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3176 slave_crtc_state); 3177 } 3178 3179 usleep_range(200, 400); 3180 3181 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3182 crtc_state); 3183 } 3184 3185 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3186 struct intel_encoder *encoder, 3187 const struct intel_crtc_state *crtc_state, 3188 const struct drm_connector_state *conn_state) 3189 { 3190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3191 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3192 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3193 enum port port = encoder->port; 3194 3195 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3196 intel_dp_stop_link_train(intel_dp, crtc_state); 3197 3198 drm_connector_update_privacy_screen(conn_state); 3199 intel_edp_backlight_on(crtc_state, conn_state); 3200 3201 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3202 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3203 3204 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3205 } 3206 3207 /* FIXME bad home for this function */ 3208 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3209 enum transcoder cpu_transcoder) 3210 { 3211 return DISPLAY_VER(i915) >= 14 ? 3212 MTL_CHICKEN_TRANS(cpu_transcoder) : 3213 CHICKEN_TRANS(cpu_transcoder); 3214 } 3215 3216 static i915_reg_t 3217 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3218 enum port port) 3219 { 3220 static const enum transcoder trans[] = { 3221 [PORT_A] = TRANSCODER_EDP, 3222 [PORT_B] = TRANSCODER_A, 3223 [PORT_C] = TRANSCODER_B, 3224 [PORT_D] = TRANSCODER_C, 3225 [PORT_E] = TRANSCODER_A, 3226 }; 3227 3228 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3229 3230 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3231 port = PORT_A; 3232 3233 return CHICKEN_TRANS(trans[port]); 3234 } 3235 3236 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3237 struct intel_encoder *encoder, 3238 const struct intel_crtc_state *crtc_state, 3239 const struct drm_connector_state *conn_state) 3240 { 3241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3242 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3243 struct drm_connector *connector = conn_state->connector; 3244 enum port port = encoder->port; 3245 enum phy phy = intel_port_to_phy(dev_priv, port); 3246 u32 buf_ctl; 3247 3248 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3249 crtc_state->hdmi_high_tmds_clock_ratio, 3250 crtc_state->hdmi_scrambling)) 3251 drm_dbg_kms(&dev_priv->drm, 3252 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3253 connector->base.id, connector->name); 3254 3255 if (has_buf_trans_select(dev_priv)) 3256 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3257 3258 /* e. Enable D2D Link for C10/C20 Phy */ 3259 if (DISPLAY_VER(dev_priv) >= 14) 3260 mtl_ddi_enable_d2d(encoder); 3261 3262 encoder->set_signal_levels(encoder, crtc_state); 3263 3264 /* Display WA #1143: skl,kbl,cfl */ 3265 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3266 /* 3267 * For some reason these chicken bits have been 3268 * stuffed into a transcoder register, event though 3269 * the bits affect a specific DDI port rather than 3270 * a specific transcoder. 3271 */ 3272 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3273 u32 val; 3274 3275 val = intel_de_read(dev_priv, reg); 3276 3277 if (port == PORT_E) 3278 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3279 DDIE_TRAINING_OVERRIDE_VALUE; 3280 else 3281 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3282 DDI_TRAINING_OVERRIDE_VALUE; 3283 3284 intel_de_write(dev_priv, reg, val); 3285 intel_de_posting_read(dev_priv, reg); 3286 3287 udelay(1); 3288 3289 if (port == PORT_E) 3290 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3291 DDIE_TRAINING_OVERRIDE_VALUE); 3292 else 3293 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3294 DDI_TRAINING_OVERRIDE_VALUE); 3295 3296 intel_de_write(dev_priv, reg, val); 3297 } 3298 3299 intel_ddi_power_up_lanes(encoder, crtc_state); 3300 3301 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3302 * are ignored so nothing special needs to be done besides 3303 * enabling the port. 3304 * 3305 * On ADL_P the PHY link rate and lane count must be programmed but 3306 * these are both 0 for HDMI. 3307 * 3308 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3309 * is filled with lane count, already set in the crtc_state. 3310 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3311 */ 3312 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3313 if (DISPLAY_VER(dev_priv) >= 14) { 3314 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3315 u32 port_buf = 0; 3316 3317 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3318 3319 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3320 port_buf |= XELPDP_PORT_REVERSAL; 3321 3322 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 3323 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3324 3325 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3326 } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 3327 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3328 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3329 } 3330 3331 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3332 3333 intel_wait_ddi_buf_active(dev_priv, port); 3334 } 3335 3336 static void intel_enable_ddi(struct intel_atomic_state *state, 3337 struct intel_encoder *encoder, 3338 const struct intel_crtc_state *crtc_state, 3339 const struct drm_connector_state *conn_state) 3340 { 3341 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3342 3343 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 3344 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3345 3346 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3347 intel_audio_sdp_split_update(crtc_state); 3348 3349 intel_enable_transcoder(crtc_state); 3350 3351 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3352 3353 intel_crtc_vblank_on(crtc_state); 3354 3355 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3356 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3357 else 3358 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3359 3360 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3361 3362 } 3363 3364 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3365 struct intel_encoder *encoder, 3366 const struct intel_crtc_state *old_crtc_state, 3367 const struct drm_connector_state *old_conn_state) 3368 { 3369 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3370 struct intel_connector *connector = 3371 to_intel_connector(old_conn_state->connector); 3372 3373 intel_dp->link_trained = false; 3374 3375 intel_psr_disable(intel_dp, old_crtc_state); 3376 intel_edp_backlight_off(old_conn_state); 3377 /* Disable the decompression in DP Sink */ 3378 intel_dp_sink_disable_decompression(state, 3379 connector, old_crtc_state); 3380 /* Disable Ignore_MSA bit in DP Sink */ 3381 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3382 false); 3383 } 3384 3385 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3386 struct intel_encoder *encoder, 3387 const struct intel_crtc_state *old_crtc_state, 3388 const struct drm_connector_state *old_conn_state) 3389 { 3390 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3391 struct drm_connector *connector = old_conn_state->connector; 3392 3393 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3394 false, false)) 3395 drm_dbg_kms(&i915->drm, 3396 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3397 connector->base.id, connector->name); 3398 } 3399 3400 static void intel_disable_ddi(struct intel_atomic_state *state, 3401 struct intel_encoder *encoder, 3402 const struct intel_crtc_state *old_crtc_state, 3403 const struct drm_connector_state *old_conn_state) 3404 { 3405 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3406 3407 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3408 3409 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3410 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3411 old_conn_state); 3412 else 3413 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3414 old_conn_state); 3415 } 3416 3417 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3418 struct intel_encoder *encoder, 3419 const struct intel_crtc_state *crtc_state, 3420 const struct drm_connector_state *conn_state) 3421 { 3422 intel_ddi_set_dp_msa(crtc_state, conn_state); 3423 3424 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3425 3426 intel_backlight_update(state, encoder, crtc_state, conn_state); 3427 drm_connector_update_privacy_screen(conn_state); 3428 } 3429 3430 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3431 struct intel_encoder *encoder, 3432 const struct intel_crtc_state *crtc_state, 3433 const struct drm_connector_state *conn_state) 3434 { 3435 3436 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3437 !intel_encoder_is_mst(encoder)) 3438 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3439 conn_state); 3440 3441 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3442 } 3443 3444 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3445 struct intel_encoder *encoder, 3446 struct intel_crtc *crtc) 3447 { 3448 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3449 struct intel_crtc_state *crtc_state = 3450 intel_atomic_get_new_crtc_state(state, crtc); 3451 struct intel_crtc *slave_crtc; 3452 enum phy phy = intel_port_to_phy(i915, encoder->port); 3453 3454 /* FIXME: Add MTL pll_mgr */ 3455 if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy)) 3456 return; 3457 3458 intel_update_active_dpll(state, crtc, encoder); 3459 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3460 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3461 intel_update_active_dpll(state, slave_crtc, encoder); 3462 } 3463 3464 static void 3465 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3466 struct intel_encoder *encoder, 3467 const struct intel_crtc_state *crtc_state, 3468 const struct drm_connector_state *conn_state) 3469 { 3470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3471 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3472 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3473 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3474 3475 if (is_tc_port) { 3476 struct intel_crtc *master_crtc = 3477 to_intel_crtc(crtc_state->uapi.crtc); 3478 3479 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3480 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3481 } 3482 3483 main_link_aux_power_domain_get(dig_port, crtc_state); 3484 3485 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3486 /* 3487 * Program the lane count for static/dynamic connections on 3488 * Type-C ports. Skip this step for TBT. 3489 */ 3490 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3491 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3492 bxt_ddi_phy_set_lane_optim_mask(encoder, 3493 crtc_state->lane_lat_optim_mask); 3494 } 3495 3496 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3497 { 3498 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3499 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3500 int ln; 3501 3502 for (ln = 0; ln < 2; ln++) 3503 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3504 } 3505 3506 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3507 const struct intel_crtc_state *crtc_state) 3508 { 3509 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3510 struct intel_encoder *encoder = &dig_port->base; 3511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3512 enum port port = encoder->port; 3513 u32 dp_tp_ctl; 3514 3515 /* 3516 * TODO: To train with only a different voltage swing entry is not 3517 * necessary disable and enable port 3518 */ 3519 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3520 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3521 mtl_disable_ddi_buf(encoder, crtc_state); 3522 3523 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3524 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3525 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3526 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3527 } else { 3528 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3529 if (crtc_state->enhanced_framing) 3530 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3531 } 3532 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3533 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3534 3535 /* 6.f Enable D2D Link */ 3536 mtl_ddi_enable_d2d(encoder); 3537 3538 /* 6.g Configure voltage swing and related IO settings */ 3539 encoder->set_signal_levels(encoder, crtc_state); 3540 3541 /* 6.h Configure PORT_BUF_CTL1 */ 3542 mtl_port_buf_ctl_program(encoder, crtc_state); 3543 3544 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3545 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3546 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3547 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3548 3549 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3550 intel_wait_ddi_buf_active(dev_priv, port); 3551 } 3552 3553 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3554 const struct intel_crtc_state *crtc_state) 3555 { 3556 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3557 struct intel_encoder *encoder = &dig_port->base; 3558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3559 enum port port = encoder->port; 3560 u32 dp_tp_ctl, ddi_buf_ctl; 3561 bool wait = false; 3562 3563 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3564 3565 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3566 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3567 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3568 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3569 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3570 wait = true; 3571 } 3572 3573 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3574 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3575 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3576 3577 if (wait) 3578 intel_wait_ddi_buf_idle(dev_priv, port); 3579 } 3580 3581 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3582 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3583 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3584 } else { 3585 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3586 if (crtc_state->enhanced_framing) 3587 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3588 } 3589 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3590 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3591 3592 if (IS_ALDERLAKE_P(dev_priv) && 3593 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3594 adlp_tbt_to_dp_alt_switch_wa(encoder); 3595 3596 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3597 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3598 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3599 3600 intel_wait_ddi_buf_active(dev_priv, port); 3601 } 3602 3603 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3604 const struct intel_crtc_state *crtc_state, 3605 u8 dp_train_pat) 3606 { 3607 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3609 u32 temp; 3610 3611 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3612 3613 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3614 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3615 case DP_TRAINING_PATTERN_DISABLE: 3616 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3617 break; 3618 case DP_TRAINING_PATTERN_1: 3619 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3620 break; 3621 case DP_TRAINING_PATTERN_2: 3622 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3623 break; 3624 case DP_TRAINING_PATTERN_3: 3625 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3626 break; 3627 case DP_TRAINING_PATTERN_4: 3628 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3629 break; 3630 } 3631 3632 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3633 } 3634 3635 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3636 const struct intel_crtc_state *crtc_state) 3637 { 3638 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3640 enum port port = encoder->port; 3641 3642 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3643 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3644 3645 /* 3646 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3647 * reason we need to set idle transmission mode is to work around a HW 3648 * issue where we enable the pipe while not in idle link-training mode. 3649 * In this case there is requirement to wait for a minimum number of 3650 * idle patterns to be sent. 3651 */ 3652 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3653 return; 3654 3655 if (intel_de_wait_for_set(dev_priv, 3656 dp_tp_status_reg(encoder, crtc_state), 3657 DP_TP_STATUS_IDLE_DONE, 1)) 3658 drm_err(&dev_priv->drm, 3659 "Timed out waiting for DP idle patterns\n"); 3660 } 3661 3662 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3663 enum transcoder cpu_transcoder) 3664 { 3665 if (cpu_transcoder == TRANSCODER_EDP) 3666 return false; 3667 3668 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3669 return false; 3670 3671 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3672 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3673 } 3674 3675 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3676 { 3677 if (crtc_state->port_clock > 594000) 3678 return 2; 3679 else 3680 return 0; 3681 } 3682 3683 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3684 { 3685 if (crtc_state->port_clock > 594000) 3686 return 3; 3687 else 3688 return 0; 3689 } 3690 3691 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3692 { 3693 if (crtc_state->port_clock > 594000) 3694 return 1; 3695 else 3696 return 0; 3697 } 3698 3699 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3700 { 3701 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3702 3703 if (DISPLAY_VER(dev_priv) >= 14) 3704 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3705 else if (DISPLAY_VER(dev_priv) >= 12) 3706 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3707 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3708 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3709 else if (DISPLAY_VER(dev_priv) >= 11) 3710 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3711 } 3712 3713 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3714 enum transcoder cpu_transcoder) 3715 { 3716 u32 master_select; 3717 3718 if (DISPLAY_VER(dev_priv) >= 11) { 3719 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3720 3721 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3722 return INVALID_TRANSCODER; 3723 3724 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3725 } else { 3726 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3727 3728 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3729 return INVALID_TRANSCODER; 3730 3731 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3732 } 3733 3734 if (master_select == 0) 3735 return TRANSCODER_EDP; 3736 else 3737 return master_select - 1; 3738 } 3739 3740 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3741 { 3742 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3743 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3744 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3745 enum transcoder cpu_transcoder; 3746 3747 crtc_state->master_transcoder = 3748 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3749 3750 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3751 enum intel_display_power_domain power_domain; 3752 intel_wakeref_t trans_wakeref; 3753 3754 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3755 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3756 power_domain); 3757 3758 if (!trans_wakeref) 3759 continue; 3760 3761 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3762 crtc_state->cpu_transcoder) 3763 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3764 3765 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3766 } 3767 3768 drm_WARN_ON(&dev_priv->drm, 3769 crtc_state->master_transcoder != INVALID_TRANSCODER && 3770 crtc_state->sync_mode_slaves_mask); 3771 } 3772 3773 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3774 struct intel_crtc_state *pipe_config) 3775 { 3776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3777 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3778 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3779 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3780 u32 temp, flags = 0; 3781 3782 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3783 if (temp & TRANS_DDI_PHSYNC) 3784 flags |= DRM_MODE_FLAG_PHSYNC; 3785 else 3786 flags |= DRM_MODE_FLAG_NHSYNC; 3787 if (temp & TRANS_DDI_PVSYNC) 3788 flags |= DRM_MODE_FLAG_PVSYNC; 3789 else 3790 flags |= DRM_MODE_FLAG_NVSYNC; 3791 3792 pipe_config->hw.adjusted_mode.flags |= flags; 3793 3794 switch (temp & TRANS_DDI_BPC_MASK) { 3795 case TRANS_DDI_BPC_6: 3796 pipe_config->pipe_bpp = 18; 3797 break; 3798 case TRANS_DDI_BPC_8: 3799 pipe_config->pipe_bpp = 24; 3800 break; 3801 case TRANS_DDI_BPC_10: 3802 pipe_config->pipe_bpp = 30; 3803 break; 3804 case TRANS_DDI_BPC_12: 3805 pipe_config->pipe_bpp = 36; 3806 break; 3807 default: 3808 break; 3809 } 3810 3811 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3812 case TRANS_DDI_MODE_SELECT_HDMI: 3813 pipe_config->has_hdmi_sink = true; 3814 3815 pipe_config->infoframes.enable |= 3816 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3817 3818 if (pipe_config->infoframes.enable) 3819 pipe_config->has_infoframe = true; 3820 3821 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3822 pipe_config->hdmi_scrambling = true; 3823 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3824 pipe_config->hdmi_high_tmds_clock_ratio = true; 3825 fallthrough; 3826 case TRANS_DDI_MODE_SELECT_DVI: 3827 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3828 if (DISPLAY_VER(dev_priv) >= 14) 3829 pipe_config->lane_count = 3830 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3831 else 3832 pipe_config->lane_count = 4; 3833 break; 3834 case TRANS_DDI_MODE_SELECT_DP_SST: 3835 if (encoder->type == INTEL_OUTPUT_EDP) 3836 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3837 else 3838 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3839 pipe_config->lane_count = 3840 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3841 3842 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3843 &pipe_config->dp_m_n); 3844 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3845 &pipe_config->dp_m2_n2); 3846 3847 pipe_config->enhanced_framing = 3848 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3849 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3850 3851 if (DISPLAY_VER(dev_priv) >= 11) 3852 pipe_config->fec_enable = 3853 intel_de_read(dev_priv, 3854 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3855 3856 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3857 pipe_config->infoframes.enable |= 3858 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3859 else 3860 pipe_config->infoframes.enable |= 3861 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3862 break; 3863 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3864 if (!HAS_DP20(dev_priv)) { 3865 /* FDI */ 3866 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3867 pipe_config->enhanced_framing = 3868 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3869 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3870 break; 3871 } 3872 fallthrough; /* 128b/132b */ 3873 case TRANS_DDI_MODE_SELECT_DP_MST: 3874 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3875 pipe_config->lane_count = 3876 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3877 3878 if (DISPLAY_VER(dev_priv) >= 12) 3879 pipe_config->mst_master_transcoder = 3880 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3881 3882 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3883 &pipe_config->dp_m_n); 3884 3885 if (DISPLAY_VER(dev_priv) >= 11) 3886 pipe_config->fec_enable = 3887 intel_de_read(dev_priv, 3888 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3889 3890 pipe_config->infoframes.enable |= 3891 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3892 break; 3893 default: 3894 break; 3895 } 3896 } 3897 3898 static void intel_ddi_get_config(struct intel_encoder *encoder, 3899 struct intel_crtc_state *pipe_config) 3900 { 3901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3902 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3903 3904 /* XXX: DSI transcoder paranoia */ 3905 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3906 return; 3907 3908 intel_ddi_read_func_ctl(encoder, pipe_config); 3909 3910 intel_ddi_mso_get_config(encoder, pipe_config); 3911 3912 pipe_config->has_audio = 3913 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3914 3915 if (encoder->type == INTEL_OUTPUT_EDP) 3916 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3917 3918 ddi_dotclock_get(pipe_config); 3919 3920 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3921 pipe_config->lane_lat_optim_mask = 3922 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3923 3924 intel_ddi_compute_min_voltage_level(pipe_config); 3925 3926 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3927 3928 intel_read_infoframe(encoder, pipe_config, 3929 HDMI_INFOFRAME_TYPE_AVI, 3930 &pipe_config->infoframes.avi); 3931 intel_read_infoframe(encoder, pipe_config, 3932 HDMI_INFOFRAME_TYPE_SPD, 3933 &pipe_config->infoframes.spd); 3934 intel_read_infoframe(encoder, pipe_config, 3935 HDMI_INFOFRAME_TYPE_VENDOR, 3936 &pipe_config->infoframes.hdmi); 3937 intel_read_infoframe(encoder, pipe_config, 3938 HDMI_INFOFRAME_TYPE_DRM, 3939 &pipe_config->infoframes.drm); 3940 3941 if (DISPLAY_VER(dev_priv) >= 8) 3942 bdw_get_trans_port_sync_config(pipe_config); 3943 3944 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3945 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3946 3947 intel_psr_get_config(encoder, pipe_config); 3948 3949 intel_audio_codec_get_config(encoder, pipe_config); 3950 } 3951 3952 void intel_ddi_get_clock(struct intel_encoder *encoder, 3953 struct intel_crtc_state *crtc_state, 3954 struct intel_shared_dpll *pll) 3955 { 3956 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3957 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3958 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3959 bool pll_active; 3960 3961 if (drm_WARN_ON(&i915->drm, !pll)) 3962 return; 3963 3964 port_dpll->pll = pll; 3965 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3966 drm_WARN_ON(&i915->drm, !pll_active); 3967 3968 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3969 3970 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3971 &crtc_state->dpll_hw_state); 3972 } 3973 3974 static void mtl_ddi_get_config(struct intel_encoder *encoder, 3975 struct intel_crtc_state *crtc_state) 3976 { 3977 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3978 3979 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 3980 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 3981 } else { 3982 intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state); 3983 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state); 3984 } 3985 3986 intel_ddi_get_config(encoder, crtc_state); 3987 } 3988 3989 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3990 struct intel_crtc_state *crtc_state) 3991 { 3992 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3993 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3994 3995 intel_ddi_get_config(encoder, crtc_state); 3996 } 3997 3998 static void adls_ddi_get_config(struct intel_encoder *encoder, 3999 struct intel_crtc_state *crtc_state) 4000 { 4001 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4002 intel_ddi_get_config(encoder, crtc_state); 4003 } 4004 4005 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4006 struct intel_crtc_state *crtc_state) 4007 { 4008 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4009 intel_ddi_get_config(encoder, crtc_state); 4010 } 4011 4012 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4013 struct intel_crtc_state *crtc_state) 4014 { 4015 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4016 intel_ddi_get_config(encoder, crtc_state); 4017 } 4018 4019 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4020 struct intel_crtc_state *crtc_state) 4021 { 4022 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4023 intel_ddi_get_config(encoder, crtc_state); 4024 } 4025 4026 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4027 { 4028 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4029 } 4030 4031 static enum icl_port_dpll_id 4032 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4033 const struct intel_crtc_state *crtc_state) 4034 { 4035 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4036 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4037 4038 if (drm_WARN_ON(&i915->drm, !pll)) 4039 return ICL_PORT_DPLL_DEFAULT; 4040 4041 if (icl_ddi_tc_pll_is_tbt(pll)) 4042 return ICL_PORT_DPLL_DEFAULT; 4043 else 4044 return ICL_PORT_DPLL_MG_PHY; 4045 } 4046 4047 enum icl_port_dpll_id 4048 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4049 const struct intel_crtc_state *crtc_state) 4050 { 4051 if (!encoder->port_pll_type) 4052 return ICL_PORT_DPLL_DEFAULT; 4053 4054 return encoder->port_pll_type(encoder, crtc_state); 4055 } 4056 4057 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4058 struct intel_crtc_state *crtc_state, 4059 struct intel_shared_dpll *pll) 4060 { 4061 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4062 enum icl_port_dpll_id port_dpll_id; 4063 struct icl_port_dpll *port_dpll; 4064 bool pll_active; 4065 4066 if (drm_WARN_ON(&i915->drm, !pll)) 4067 return; 4068 4069 if (icl_ddi_tc_pll_is_tbt(pll)) 4070 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4071 else 4072 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4073 4074 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4075 4076 port_dpll->pll = pll; 4077 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4078 drm_WARN_ON(&i915->drm, !pll_active); 4079 4080 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4081 4082 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4083 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4084 else 4085 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4086 &crtc_state->dpll_hw_state); 4087 } 4088 4089 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4090 struct intel_crtc_state *crtc_state) 4091 { 4092 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4093 intel_ddi_get_config(encoder, crtc_state); 4094 } 4095 4096 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4097 struct intel_crtc_state *crtc_state) 4098 { 4099 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4100 intel_ddi_get_config(encoder, crtc_state); 4101 } 4102 4103 static void skl_ddi_get_config(struct intel_encoder *encoder, 4104 struct intel_crtc_state *crtc_state) 4105 { 4106 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4107 intel_ddi_get_config(encoder, crtc_state); 4108 } 4109 4110 void hsw_ddi_get_config(struct intel_encoder *encoder, 4111 struct intel_crtc_state *crtc_state) 4112 { 4113 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4114 intel_ddi_get_config(encoder, crtc_state); 4115 } 4116 4117 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4118 const struct intel_crtc_state *crtc_state) 4119 { 4120 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4121 enum phy phy = intel_port_to_phy(i915, encoder->port); 4122 4123 if (intel_phy_is_tc(i915, phy)) 4124 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4125 crtc_state); 4126 4127 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 4128 intel_dp_sync_state(encoder, crtc_state); 4129 } 4130 4131 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4132 struct intel_crtc_state *crtc_state) 4133 { 4134 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4135 enum phy phy = intel_port_to_phy(i915, encoder->port); 4136 bool fastset = true; 4137 4138 if (intel_phy_is_tc(i915, phy)) { 4139 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4140 encoder->base.base.id, encoder->base.name); 4141 crtc_state->uapi.mode_changed = true; 4142 fastset = false; 4143 } 4144 4145 if (intel_crtc_has_dp_encoder(crtc_state) && 4146 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4147 fastset = false; 4148 4149 return fastset; 4150 } 4151 4152 static enum intel_output_type 4153 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4154 struct intel_crtc_state *crtc_state, 4155 struct drm_connector_state *conn_state) 4156 { 4157 switch (conn_state->connector->connector_type) { 4158 case DRM_MODE_CONNECTOR_HDMIA: 4159 return INTEL_OUTPUT_HDMI; 4160 case DRM_MODE_CONNECTOR_eDP: 4161 return INTEL_OUTPUT_EDP; 4162 case DRM_MODE_CONNECTOR_DisplayPort: 4163 return INTEL_OUTPUT_DP; 4164 default: 4165 MISSING_CASE(conn_state->connector->connector_type); 4166 return INTEL_OUTPUT_UNUSED; 4167 } 4168 } 4169 4170 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4171 struct intel_crtc_state *pipe_config, 4172 struct drm_connector_state *conn_state) 4173 { 4174 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4176 enum port port = encoder->port; 4177 int ret; 4178 4179 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4180 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4181 4182 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4183 pipe_config->has_hdmi_sink = 4184 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4185 4186 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4187 } else { 4188 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4189 } 4190 4191 if (ret) 4192 return ret; 4193 4194 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4195 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4196 pipe_config->pch_pfit.force_thru = 4197 pipe_config->pch_pfit.enabled || 4198 pipe_config->crc_enabled; 4199 4200 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4201 pipe_config->lane_lat_optim_mask = 4202 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4203 4204 intel_ddi_compute_min_voltage_level(pipe_config); 4205 4206 return 0; 4207 } 4208 4209 static bool mode_equal(const struct drm_display_mode *mode1, 4210 const struct drm_display_mode *mode2) 4211 { 4212 return drm_mode_match(mode1, mode2, 4213 DRM_MODE_MATCH_TIMINGS | 4214 DRM_MODE_MATCH_FLAGS | 4215 DRM_MODE_MATCH_3D_FLAGS) && 4216 mode1->clock == mode2->clock; /* we want an exact match */ 4217 } 4218 4219 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4220 const struct intel_link_m_n *m_n_2) 4221 { 4222 return m_n_1->tu == m_n_2->tu && 4223 m_n_1->data_m == m_n_2->data_m && 4224 m_n_1->data_n == m_n_2->data_n && 4225 m_n_1->link_m == m_n_2->link_m && 4226 m_n_1->link_n == m_n_2->link_n; 4227 } 4228 4229 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4230 const struct intel_crtc_state *crtc_state2) 4231 { 4232 return crtc_state1->hw.active && crtc_state2->hw.active && 4233 crtc_state1->output_types == crtc_state2->output_types && 4234 crtc_state1->output_format == crtc_state2->output_format && 4235 crtc_state1->lane_count == crtc_state2->lane_count && 4236 crtc_state1->port_clock == crtc_state2->port_clock && 4237 mode_equal(&crtc_state1->hw.adjusted_mode, 4238 &crtc_state2->hw.adjusted_mode) && 4239 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4240 } 4241 4242 static u8 4243 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4244 int tile_group_id) 4245 { 4246 struct drm_connector *connector; 4247 const struct drm_connector_state *conn_state; 4248 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4249 struct intel_atomic_state *state = 4250 to_intel_atomic_state(ref_crtc_state->uapi.state); 4251 u8 transcoders = 0; 4252 int i; 4253 4254 /* 4255 * We don't enable port sync on BDW due to missing w/as and 4256 * due to not having adjusted the modeset sequence appropriately. 4257 */ 4258 if (DISPLAY_VER(dev_priv) < 9) 4259 return 0; 4260 4261 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4262 return 0; 4263 4264 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4265 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4266 const struct intel_crtc_state *crtc_state; 4267 4268 if (!crtc) 4269 continue; 4270 4271 if (!connector->has_tile || 4272 connector->tile_group->id != 4273 tile_group_id) 4274 continue; 4275 crtc_state = intel_atomic_get_new_crtc_state(state, 4276 crtc); 4277 if (!crtcs_port_sync_compatible(ref_crtc_state, 4278 crtc_state)) 4279 continue; 4280 transcoders |= BIT(crtc_state->cpu_transcoder); 4281 } 4282 4283 return transcoders; 4284 } 4285 4286 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4287 struct intel_crtc_state *crtc_state, 4288 struct drm_connector_state *conn_state) 4289 { 4290 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4291 struct drm_connector *connector = conn_state->connector; 4292 u8 port_sync_transcoders = 0; 4293 4294 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4295 encoder->base.base.id, encoder->base.name, 4296 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4297 4298 if (connector->has_tile) 4299 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4300 connector->tile_group->id); 4301 4302 /* 4303 * EDP Transcoders cannot be ensalved 4304 * make them a master always when present 4305 */ 4306 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4307 crtc_state->master_transcoder = TRANSCODER_EDP; 4308 else 4309 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4310 4311 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4312 crtc_state->master_transcoder = INVALID_TRANSCODER; 4313 crtc_state->sync_mode_slaves_mask = 4314 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4315 } 4316 4317 return 0; 4318 } 4319 4320 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4321 { 4322 struct drm_i915_private *i915 = to_i915(encoder->dev); 4323 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4324 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4325 4326 intel_dp_encoder_flush_work(encoder); 4327 if (intel_phy_is_tc(i915, phy)) 4328 intel_tc_port_cleanup(dig_port); 4329 intel_display_power_flush_work(i915); 4330 4331 drm_encoder_cleanup(encoder); 4332 kfree(dig_port->hdcp_port_data.streams); 4333 kfree(dig_port); 4334 } 4335 4336 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4337 { 4338 struct drm_i915_private *i915 = to_i915(encoder->dev); 4339 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4340 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4341 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4342 4343 intel_dp->reset_link_params = true; 4344 4345 intel_pps_encoder_reset(intel_dp); 4346 4347 if (intel_phy_is_tc(i915, phy)) 4348 intel_tc_port_init_mode(dig_port); 4349 } 4350 4351 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4352 { 4353 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4354 4355 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4356 4357 return 0; 4358 } 4359 4360 static const struct drm_encoder_funcs intel_ddi_funcs = { 4361 .reset = intel_ddi_encoder_reset, 4362 .destroy = intel_ddi_encoder_destroy, 4363 .late_register = intel_ddi_encoder_late_register, 4364 }; 4365 4366 static struct intel_connector * 4367 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4368 { 4369 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4370 struct intel_connector *connector; 4371 enum port port = dig_port->base.port; 4372 4373 connector = intel_connector_alloc(); 4374 if (!connector) 4375 return NULL; 4376 4377 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4378 if (DISPLAY_VER(i915) >= 14) 4379 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4380 else 4381 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4382 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4383 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4384 4385 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4386 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4387 4388 if (!intel_dp_init_connector(dig_port, connector)) { 4389 kfree(connector); 4390 return NULL; 4391 } 4392 4393 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4394 struct drm_device *dev = dig_port->base.base.dev; 4395 struct drm_privacy_screen *privacy_screen; 4396 4397 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4398 if (!IS_ERR(privacy_screen)) { 4399 drm_connector_attach_privacy_screen_provider(&connector->base, 4400 privacy_screen); 4401 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4402 drm_warn(dev, "Error getting privacy-screen\n"); 4403 } 4404 } 4405 4406 return connector; 4407 } 4408 4409 static int modeset_pipe(struct drm_crtc *crtc, 4410 struct drm_modeset_acquire_ctx *ctx) 4411 { 4412 struct drm_atomic_state *state; 4413 struct drm_crtc_state *crtc_state; 4414 int ret; 4415 4416 state = drm_atomic_state_alloc(crtc->dev); 4417 if (!state) 4418 return -ENOMEM; 4419 4420 state->acquire_ctx = ctx; 4421 to_intel_atomic_state(state)->internal = true; 4422 4423 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4424 if (IS_ERR(crtc_state)) { 4425 ret = PTR_ERR(crtc_state); 4426 goto out; 4427 } 4428 4429 crtc_state->connectors_changed = true; 4430 4431 ret = drm_atomic_commit(state); 4432 out: 4433 drm_atomic_state_put(state); 4434 4435 return ret; 4436 } 4437 4438 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4439 struct drm_modeset_acquire_ctx *ctx) 4440 { 4441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4442 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4443 struct intel_connector *connector = hdmi->attached_connector; 4444 struct i2c_adapter *ddc = connector->base.ddc; 4445 struct drm_connector_state *conn_state; 4446 struct intel_crtc_state *crtc_state; 4447 struct intel_crtc *crtc; 4448 u8 config; 4449 int ret; 4450 4451 if (connector->base.status != connector_status_connected) 4452 return 0; 4453 4454 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4455 ctx); 4456 if (ret) 4457 return ret; 4458 4459 conn_state = connector->base.state; 4460 4461 crtc = to_intel_crtc(conn_state->crtc); 4462 if (!crtc) 4463 return 0; 4464 4465 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4466 if (ret) 4467 return ret; 4468 4469 crtc_state = to_intel_crtc_state(crtc->base.state); 4470 4471 drm_WARN_ON(&dev_priv->drm, 4472 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4473 4474 if (!crtc_state->hw.active) 4475 return 0; 4476 4477 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4478 !crtc_state->hdmi_scrambling) 4479 return 0; 4480 4481 if (conn_state->commit && 4482 !try_wait_for_completion(&conn_state->commit->hw_done)) 4483 return 0; 4484 4485 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4486 if (ret < 0) { 4487 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4488 connector->base.base.id, connector->base.name, ret); 4489 return 0; 4490 } 4491 4492 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4493 crtc_state->hdmi_high_tmds_clock_ratio && 4494 !!(config & SCDC_SCRAMBLING_ENABLE) == 4495 crtc_state->hdmi_scrambling) 4496 return 0; 4497 4498 /* 4499 * HDMI 2.0 says that one should not send scrambled data 4500 * prior to configuring the sink scrambling, and that 4501 * TMDS clock/data transmission should be suspended when 4502 * changing the TMDS clock rate in the sink. So let's 4503 * just do a full modeset here, even though some sinks 4504 * would be perfectly happy if were to just reconfigure 4505 * the SCDC settings on the fly. 4506 */ 4507 return modeset_pipe(&crtc->base, ctx); 4508 } 4509 4510 static enum intel_hotplug_state 4511 intel_ddi_hotplug(struct intel_encoder *encoder, 4512 struct intel_connector *connector) 4513 { 4514 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4515 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4516 struct intel_dp *intel_dp = &dig_port->dp; 4517 enum phy phy = intel_port_to_phy(i915, encoder->port); 4518 bool is_tc = intel_phy_is_tc(i915, phy); 4519 struct drm_modeset_acquire_ctx ctx; 4520 enum intel_hotplug_state state; 4521 int ret; 4522 4523 if (intel_dp->compliance.test_active && 4524 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4525 intel_dp_phy_test(encoder); 4526 /* just do the PHY test and nothing else */ 4527 return INTEL_HOTPLUG_UNCHANGED; 4528 } 4529 4530 state = intel_encoder_hotplug(encoder, connector); 4531 4532 if (!intel_tc_port_link_reset(dig_port)) { 4533 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4534 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4535 ret = intel_hdmi_reset_link(encoder, &ctx); 4536 else 4537 ret = intel_dp_retrain_link(encoder, &ctx); 4538 } 4539 4540 drm_WARN_ON(encoder->base.dev, ret); 4541 } 4542 4543 /* 4544 * Unpowered type-c dongles can take some time to boot and be 4545 * responsible, so here giving some time to those dongles to power up 4546 * and then retrying the probe. 4547 * 4548 * On many platforms the HDMI live state signal is known to be 4549 * unreliable, so we can't use it to detect if a sink is connected or 4550 * not. Instead we detect if it's connected based on whether we can 4551 * read the EDID or not. That in turn has a problem during disconnect, 4552 * since the HPD interrupt may be raised before the DDC lines get 4553 * disconnected (due to how the required length of DDC vs. HPD 4554 * connector pins are specified) and so we'll still be able to get a 4555 * valid EDID. To solve this schedule another detection cycle if this 4556 * time around we didn't detect any change in the sink's connection 4557 * status. 4558 * 4559 * Type-c connectors which get their HPD signal deasserted then 4560 * reasserted, without unplugging/replugging the sink from the 4561 * connector, introduce a delay until the AUX channel communication 4562 * becomes functional. Retry the detection for 5 seconds on type-c 4563 * connectors to account for this delay. 4564 */ 4565 if (state == INTEL_HOTPLUG_UNCHANGED && 4566 connector->hotplug_retries < (is_tc ? 5 : 1) && 4567 !dig_port->dp.is_mst) 4568 state = INTEL_HOTPLUG_RETRY; 4569 4570 return state; 4571 } 4572 4573 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4574 { 4575 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4576 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4577 4578 return intel_de_read(dev_priv, SDEISR) & bit; 4579 } 4580 4581 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4582 { 4583 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4584 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4585 4586 return intel_de_read(dev_priv, DEISR) & bit; 4587 } 4588 4589 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4590 { 4591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4592 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4593 4594 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4595 } 4596 4597 static struct intel_connector * 4598 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4599 { 4600 struct intel_connector *connector; 4601 enum port port = dig_port->base.port; 4602 4603 connector = intel_connector_alloc(); 4604 if (!connector) 4605 return NULL; 4606 4607 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4608 intel_hdmi_init_connector(dig_port, connector); 4609 4610 return connector; 4611 } 4612 4613 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4614 { 4615 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4616 4617 if (dig_port->base.port != PORT_A) 4618 return false; 4619 4620 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4621 return false; 4622 4623 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4624 * supported configuration 4625 */ 4626 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4627 return true; 4628 4629 return false; 4630 } 4631 4632 static int 4633 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4634 { 4635 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4636 enum port port = dig_port->base.port; 4637 int max_lanes = 4; 4638 4639 if (DISPLAY_VER(dev_priv) >= 11) 4640 return max_lanes; 4641 4642 if (port == PORT_A || port == PORT_E) { 4643 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4644 max_lanes = port == PORT_A ? 4 : 0; 4645 else 4646 /* Both A and E share 2 lanes */ 4647 max_lanes = 2; 4648 } 4649 4650 /* 4651 * Some BIOS might fail to set this bit on port A if eDP 4652 * wasn't lit up at boot. Force this bit set when needed 4653 * so we use the proper lane count for our calculations. 4654 */ 4655 if (intel_ddi_a_force_4_lanes(dig_port)) { 4656 drm_dbg_kms(&dev_priv->drm, 4657 "Forcing DDI_A_4_LANES for port A\n"); 4658 dig_port->saved_port_bits |= DDI_A_4_LANES; 4659 max_lanes = 4; 4660 } 4661 4662 return max_lanes; 4663 } 4664 4665 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4666 enum port port) 4667 { 4668 if (port >= PORT_D_XELPD) 4669 return HPD_PORT_D + port - PORT_D_XELPD; 4670 else if (port >= PORT_TC1) 4671 return HPD_PORT_TC1 + port - PORT_TC1; 4672 else 4673 return HPD_PORT_A + port - PORT_A; 4674 } 4675 4676 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4677 enum port port) 4678 { 4679 if (port >= PORT_TC1) 4680 return HPD_PORT_C + port - PORT_TC1; 4681 else 4682 return HPD_PORT_A + port - PORT_A; 4683 } 4684 4685 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4686 enum port port) 4687 { 4688 if (port >= PORT_TC1) 4689 return HPD_PORT_TC1 + port - PORT_TC1; 4690 else 4691 return HPD_PORT_A + port - PORT_A; 4692 } 4693 4694 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4695 enum port port) 4696 { 4697 if (HAS_PCH_TGP(dev_priv)) 4698 return tgl_hpd_pin(dev_priv, port); 4699 4700 if (port >= PORT_TC1) 4701 return HPD_PORT_C + port - PORT_TC1; 4702 else 4703 return HPD_PORT_A + port - PORT_A; 4704 } 4705 4706 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4707 enum port port) 4708 { 4709 if (port >= PORT_C) 4710 return HPD_PORT_TC1 + port - PORT_C; 4711 else 4712 return HPD_PORT_A + port - PORT_A; 4713 } 4714 4715 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4716 enum port port) 4717 { 4718 if (port == PORT_D) 4719 return HPD_PORT_A; 4720 4721 if (HAS_PCH_TGP(dev_priv)) 4722 return icl_hpd_pin(dev_priv, port); 4723 4724 return HPD_PORT_A + port - PORT_A; 4725 } 4726 4727 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4728 { 4729 if (HAS_PCH_TGP(dev_priv)) 4730 return icl_hpd_pin(dev_priv, port); 4731 4732 return HPD_PORT_A + port - PORT_A; 4733 } 4734 4735 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4736 { 4737 if (DISPLAY_VER(i915) >= 12) 4738 return port >= PORT_TC1; 4739 else if (DISPLAY_VER(i915) >= 11) 4740 return port >= PORT_C; 4741 else 4742 return false; 4743 } 4744 4745 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4746 { 4747 intel_dp_encoder_suspend(encoder); 4748 } 4749 4750 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4751 { 4752 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4753 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4754 4755 intel_tc_port_suspend(dig_port); 4756 } 4757 4758 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4759 { 4760 intel_dp_encoder_shutdown(encoder); 4761 intel_hdmi_encoder_shutdown(encoder); 4762 } 4763 4764 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4765 { 4766 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4767 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4768 4769 intel_tc_port_cleanup(dig_port); 4770 } 4771 4772 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4773 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4774 4775 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4776 { 4777 /* straps not used on skl+ */ 4778 if (DISPLAY_VER(i915) >= 9) 4779 return true; 4780 4781 switch (port) { 4782 case PORT_A: 4783 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4784 case PORT_B: 4785 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4786 case PORT_C: 4787 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4788 case PORT_D: 4789 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4790 case PORT_E: 4791 return true; /* no strap for DDI-E */ 4792 default: 4793 MISSING_CASE(port); 4794 return false; 4795 } 4796 } 4797 4798 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4799 { 4800 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4801 enum phy phy = intel_port_to_phy(i915, encoder->port); 4802 4803 return init_dp || intel_phy_is_tc(i915, phy); 4804 } 4805 4806 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4807 { 4808 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4809 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4810 "Platform does not support DSI\n"); 4811 } 4812 4813 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4814 { 4815 struct intel_encoder *encoder; 4816 4817 for_each_intel_encoder(&i915->drm, encoder) { 4818 /* FIXME what about second port for dual link DSI? */ 4819 if (encoder->port == port) 4820 return true; 4821 } 4822 4823 return false; 4824 } 4825 4826 void intel_ddi_init(struct drm_i915_private *dev_priv, 4827 const struct intel_bios_encoder_data *devdata) 4828 { 4829 struct intel_digital_port *dig_port; 4830 struct intel_encoder *encoder; 4831 bool init_hdmi, init_dp; 4832 enum port port; 4833 enum phy phy; 4834 4835 port = intel_bios_encoder_port(devdata); 4836 if (port == PORT_NONE) 4837 return; 4838 4839 if (!port_strap_detected(dev_priv, port)) { 4840 drm_dbg_kms(&dev_priv->drm, 4841 "Port %c strap not detected\n", port_name(port)); 4842 return; 4843 } 4844 4845 if (!assert_port_valid(dev_priv, port)) 4846 return; 4847 4848 if (port_in_use(dev_priv, port)) { 4849 drm_dbg_kms(&dev_priv->drm, 4850 "Port %c already claimed\n", port_name(port)); 4851 return; 4852 } 4853 4854 if (intel_bios_encoder_supports_dsi(devdata)) { 4855 /* BXT/GLK handled elsewhere, for now at least */ 4856 if (!assert_has_icl_dsi(dev_priv)) 4857 return; 4858 4859 icl_dsi_init(dev_priv, devdata); 4860 return; 4861 } 4862 4863 phy = intel_port_to_phy(dev_priv, port); 4864 4865 /* 4866 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4867 * have taken over some of the PHYs and made them unavailable to the 4868 * driver. In that case we should skip initializing the corresponding 4869 * outputs. 4870 */ 4871 if (intel_hti_uses_phy(dev_priv, phy)) { 4872 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4873 port_name(port), phy_name(phy)); 4874 return; 4875 } 4876 4877 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4878 intel_bios_encoder_supports_hdmi(devdata); 4879 init_dp = intel_bios_encoder_supports_dp(devdata); 4880 4881 if (intel_bios_encoder_is_lspcon(devdata)) { 4882 /* 4883 * Lspcon device needs to be driven with DP connector 4884 * with special detection sequence. So make sure DP 4885 * is initialized before lspcon. 4886 */ 4887 init_dp = true; 4888 init_hdmi = false; 4889 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4890 port_name(port)); 4891 } 4892 4893 if (!init_dp && !init_hdmi) { 4894 drm_dbg_kms(&dev_priv->drm, 4895 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4896 port_name(port)); 4897 return; 4898 } 4899 4900 if (intel_phy_is_snps(dev_priv, phy) && 4901 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4902 drm_dbg_kms(&dev_priv->drm, 4903 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4904 phy_name(phy)); 4905 } 4906 4907 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4908 if (!dig_port) 4909 return; 4910 4911 dig_port->aux_ch = AUX_CH_NONE; 4912 4913 encoder = &dig_port->base; 4914 encoder->devdata = devdata; 4915 4916 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4917 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4918 DRM_MODE_ENCODER_TMDS, 4919 "DDI %c/PHY %c", 4920 port_name(port - PORT_D_XELPD + PORT_D), 4921 phy_name(phy)); 4922 } else if (DISPLAY_VER(dev_priv) >= 12) { 4923 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4924 4925 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4926 DRM_MODE_ENCODER_TMDS, 4927 "DDI %s%c/PHY %s%c", 4928 port >= PORT_TC1 ? "TC" : "", 4929 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4930 tc_port != TC_PORT_NONE ? "TC" : "", 4931 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4932 } else if (DISPLAY_VER(dev_priv) >= 11) { 4933 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4934 4935 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4936 DRM_MODE_ENCODER_TMDS, 4937 "DDI %c%s/PHY %s%c", 4938 port_name(port), 4939 port >= PORT_C ? " (TC)" : "", 4940 tc_port != TC_PORT_NONE ? "TC" : "", 4941 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4942 } else { 4943 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4944 DRM_MODE_ENCODER_TMDS, 4945 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4946 } 4947 4948 mutex_init(&dig_port->hdcp_mutex); 4949 dig_port->num_hdcp_streams = 0; 4950 4951 encoder->hotplug = intel_ddi_hotplug; 4952 encoder->compute_output_type = intel_ddi_compute_output_type; 4953 encoder->compute_config = intel_ddi_compute_config; 4954 encoder->compute_config_late = intel_ddi_compute_config_late; 4955 encoder->enable = intel_enable_ddi; 4956 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4957 encoder->pre_enable = intel_ddi_pre_enable; 4958 encoder->disable = intel_disable_ddi; 4959 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4960 encoder->post_disable = intel_ddi_post_disable; 4961 encoder->update_pipe = intel_ddi_update_pipe; 4962 encoder->audio_enable = intel_audio_codec_enable; 4963 encoder->audio_disable = intel_audio_codec_disable; 4964 encoder->get_hw_state = intel_ddi_get_hw_state; 4965 encoder->sync_state = intel_ddi_sync_state; 4966 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4967 encoder->suspend = intel_ddi_encoder_suspend; 4968 encoder->shutdown = intel_ddi_encoder_shutdown; 4969 encoder->get_power_domains = intel_ddi_get_power_domains; 4970 4971 encoder->type = INTEL_OUTPUT_DDI; 4972 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4973 encoder->port = port; 4974 encoder->cloneable = 0; 4975 encoder->pipe_mask = ~0; 4976 4977 if (DISPLAY_VER(dev_priv) >= 14) { 4978 encoder->enable_clock = intel_mtl_pll_enable; 4979 encoder->disable_clock = intel_mtl_pll_disable; 4980 encoder->port_pll_type = intel_mtl_port_pll_type; 4981 encoder->get_config = mtl_ddi_get_config; 4982 } else if (IS_DG2(dev_priv)) { 4983 encoder->enable_clock = intel_mpllb_enable; 4984 encoder->disable_clock = intel_mpllb_disable; 4985 encoder->get_config = dg2_ddi_get_config; 4986 } else if (IS_ALDERLAKE_S(dev_priv)) { 4987 encoder->enable_clock = adls_ddi_enable_clock; 4988 encoder->disable_clock = adls_ddi_disable_clock; 4989 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4990 encoder->get_config = adls_ddi_get_config; 4991 } else if (IS_ROCKETLAKE(dev_priv)) { 4992 encoder->enable_clock = rkl_ddi_enable_clock; 4993 encoder->disable_clock = rkl_ddi_disable_clock; 4994 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4995 encoder->get_config = rkl_ddi_get_config; 4996 } else if (IS_DG1(dev_priv)) { 4997 encoder->enable_clock = dg1_ddi_enable_clock; 4998 encoder->disable_clock = dg1_ddi_disable_clock; 4999 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5000 encoder->get_config = dg1_ddi_get_config; 5001 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5002 if (intel_ddi_is_tc(dev_priv, port)) { 5003 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5004 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5005 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5006 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5007 encoder->get_config = icl_ddi_combo_get_config; 5008 } else { 5009 encoder->enable_clock = icl_ddi_combo_enable_clock; 5010 encoder->disable_clock = icl_ddi_combo_disable_clock; 5011 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5012 encoder->get_config = icl_ddi_combo_get_config; 5013 } 5014 } else if (DISPLAY_VER(dev_priv) >= 11) { 5015 if (intel_ddi_is_tc(dev_priv, port)) { 5016 encoder->enable_clock = icl_ddi_tc_enable_clock; 5017 encoder->disable_clock = icl_ddi_tc_disable_clock; 5018 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5019 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5020 encoder->get_config = icl_ddi_tc_get_config; 5021 } else { 5022 encoder->enable_clock = icl_ddi_combo_enable_clock; 5023 encoder->disable_clock = icl_ddi_combo_disable_clock; 5024 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5025 encoder->get_config = icl_ddi_combo_get_config; 5026 } 5027 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5028 /* BXT/GLK have fixed PLL->port mapping */ 5029 encoder->get_config = bxt_ddi_get_config; 5030 } else if (DISPLAY_VER(dev_priv) == 9) { 5031 encoder->enable_clock = skl_ddi_enable_clock; 5032 encoder->disable_clock = skl_ddi_disable_clock; 5033 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5034 encoder->get_config = skl_ddi_get_config; 5035 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5036 encoder->enable_clock = hsw_ddi_enable_clock; 5037 encoder->disable_clock = hsw_ddi_disable_clock; 5038 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5039 encoder->get_config = hsw_ddi_get_config; 5040 } 5041 5042 if (DISPLAY_VER(dev_priv) >= 14) { 5043 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5044 } else if (IS_DG2(dev_priv)) { 5045 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5046 } else if (DISPLAY_VER(dev_priv) >= 12) { 5047 if (intel_phy_is_combo(dev_priv, phy)) 5048 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5049 else 5050 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5051 } else if (DISPLAY_VER(dev_priv) >= 11) { 5052 if (intel_phy_is_combo(dev_priv, phy)) 5053 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5054 else 5055 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5056 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5057 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 5058 } else { 5059 encoder->set_signal_levels = hsw_set_signal_levels; 5060 } 5061 5062 intel_ddi_buf_trans_init(encoder); 5063 5064 if (DISPLAY_VER(dev_priv) >= 13) 5065 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5066 else if (IS_DG1(dev_priv)) 5067 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5068 else if (IS_ROCKETLAKE(dev_priv)) 5069 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5070 else if (DISPLAY_VER(dev_priv) >= 12) 5071 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5072 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5073 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5074 else if (DISPLAY_VER(dev_priv) == 11) 5075 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5076 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5077 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5078 else 5079 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5080 5081 if (DISPLAY_VER(dev_priv) >= 11) 5082 dig_port->saved_port_bits = 5083 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5084 & DDI_BUF_PORT_REVERSAL; 5085 else 5086 dig_port->saved_port_bits = 5087 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5088 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5089 5090 if (intel_bios_encoder_lane_reversal(devdata)) 5091 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5092 5093 dig_port->dp.output_reg = INVALID_MMIO_REG; 5094 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5095 5096 if (need_aux_ch(encoder, init_dp)) { 5097 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5098 if (dig_port->aux_ch == AUX_CH_NONE) 5099 goto err; 5100 } 5101 5102 if (intel_phy_is_tc(dev_priv, phy)) { 5103 bool is_legacy = 5104 !intel_bios_encoder_supports_typec_usb(devdata) && 5105 !intel_bios_encoder_supports_tbt(devdata); 5106 5107 if (!is_legacy && init_hdmi) { 5108 is_legacy = !init_dp; 5109 5110 drm_dbg_kms(&dev_priv->drm, 5111 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5112 port_name(port), 5113 str_yes_no(init_dp), 5114 is_legacy ? "legacy" : "non-legacy"); 5115 } 5116 5117 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5118 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5119 5120 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5121 goto err; 5122 } 5123 5124 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5125 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5126 5127 if (DISPLAY_VER(dev_priv) >= 11) { 5128 if (intel_phy_is_tc(dev_priv, phy)) 5129 dig_port->connected = intel_tc_port_connected; 5130 else 5131 dig_port->connected = lpt_digital_port_connected; 5132 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5133 dig_port->connected = bdw_digital_port_connected; 5134 } else if (DISPLAY_VER(dev_priv) == 9) { 5135 dig_port->connected = lpt_digital_port_connected; 5136 } else if (IS_BROADWELL(dev_priv)) { 5137 if (port == PORT_A) 5138 dig_port->connected = bdw_digital_port_connected; 5139 else 5140 dig_port->connected = lpt_digital_port_connected; 5141 } else if (IS_HASWELL(dev_priv)) { 5142 if (port == PORT_A) 5143 dig_port->connected = hsw_digital_port_connected; 5144 else 5145 dig_port->connected = lpt_digital_port_connected; 5146 } 5147 5148 intel_infoframe_init(dig_port); 5149 5150 if (init_dp) { 5151 if (!intel_ddi_init_dp_connector(dig_port)) 5152 goto err; 5153 5154 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5155 5156 if (dig_port->dp.mso_link_count) 5157 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5158 } 5159 5160 /* 5161 * In theory we don't need the encoder->type check, 5162 * but leave it just in case we have some really bad VBTs... 5163 */ 5164 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5165 if (!intel_ddi_init_hdmi_connector(dig_port)) 5166 goto err; 5167 } 5168 5169 return; 5170 5171 err: 5172 drm_encoder_cleanup(&encoder->base); 5173 kfree(dig_port); 5174 } 5175