1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dp_tunnel.h" 58 #include "intel_dpio_phy.h" 59 #include "intel_dsi.h" 60 #include "intel_encoder.h" 61 #include "intel_fdi.h" 62 #include "intel_fifo_underrun.h" 63 #include "intel_gmbus.h" 64 #include "intel_hdcp.h" 65 #include "intel_hdmi.h" 66 #include "intel_hotplug.h" 67 #include "intel_hti.h" 68 #include "intel_lspcon.h" 69 #include "intel_mg_phy_regs.h" 70 #include "intel_modeset_lock.h" 71 #include "intel_pps.h" 72 #include "intel_psr.h" 73 #include "intel_quirks.h" 74 #include "intel_snps_phy.h" 75 #include "intel_tc.h" 76 #include "intel_vdsc.h" 77 #include "intel_vdsc_regs.h" 78 #include "skl_scaler.h" 79 #include "skl_universal_plane.h" 80 81 static const u8 index_to_dp_signal_levels[] = { 82 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 83 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 84 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 85 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 86 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 87 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 88 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 89 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 90 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 91 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 }; 93 94 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 95 const struct intel_ddi_buf_trans *trans) 96 { 97 int level; 98 99 level = intel_bios_hdmi_level_shift(encoder->devdata); 100 if (level < 0) 101 level = trans->hdmi_default_entry; 102 103 return level; 104 } 105 106 static bool has_buf_trans_select(struct drm_i915_private *i915) 107 { 108 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 109 } 110 111 static bool has_iboost(struct drm_i915_private *i915) 112 { 113 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 114 } 115 116 /* 117 * Starting with Haswell, DDI port buffers must be programmed with correct 118 * values in advance. This function programs the correct values for 119 * DP/eDP/FDI use cases. 120 */ 121 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 122 const struct intel_crtc_state *crtc_state) 123 { 124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 125 u32 iboost_bit = 0; 126 int i, n_entries; 127 enum port port = encoder->port; 128 const struct intel_ddi_buf_trans *trans; 129 130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 132 return; 133 134 /* If we're boosting the current, set bit 31 of trans1 */ 135 if (has_iboost(dev_priv) && 136 intel_bios_dp_boost_level(encoder->devdata)) 137 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 138 139 for (i = 0; i < n_entries; i++) { 140 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 141 trans->entries[i].hsw.trans1 | iboost_bit); 142 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 143 trans->entries[i].hsw.trans2); 144 } 145 } 146 147 /* 148 * Starting with Haswell, DDI port buffers must be programmed with correct 149 * values in advance. This function programs the correct values for 150 * HDMI/DVI use cases. 151 */ 152 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 153 const struct intel_crtc_state *crtc_state) 154 { 155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 156 int level = intel_ddi_level(encoder, crtc_state, 0); 157 u32 iboost_bit = 0; 158 int n_entries; 159 enum port port = encoder->port; 160 const struct intel_ddi_buf_trans *trans; 161 162 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 163 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 164 return; 165 166 /* If we're boosting the current, set bit 31 of trans1 */ 167 if (has_iboost(dev_priv) && 168 intel_bios_hdmi_boost_level(encoder->devdata)) 169 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 170 171 /* Entry 9 is for HDMI: */ 172 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 173 trans->entries[level].hsw.trans1 | iboost_bit); 174 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 175 trans->entries[level].hsw.trans2); 176 } 177 178 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 179 { 180 int ret; 181 182 /* FIXME: find out why Bspec's 100us timeout is too short */ 183 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 184 XELPDP_PORT_BUF_PHY_IDLE), 10000); 185 if (ret) 186 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 187 port_name(port)); 188 } 189 190 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 191 enum port port) 192 { 193 if (IS_BROXTON(dev_priv)) { 194 udelay(16); 195 return; 196 } 197 198 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 199 DDI_BUF_IS_IDLE), 8)) 200 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 201 port_name(port)); 202 } 203 204 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 205 { 206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 207 enum port port = encoder->port; 208 int timeout_us; 209 int ret; 210 211 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 212 if (DISPLAY_VER(dev_priv) < 10) { 213 usleep_range(518, 1000); 214 return; 215 } 216 217 if (DISPLAY_VER(dev_priv) >= 14) { 218 timeout_us = 10000; 219 } else if (IS_DG2(dev_priv)) { 220 timeout_us = 1200; 221 } else if (DISPLAY_VER(dev_priv) >= 12) { 222 if (intel_encoder_is_tc(encoder)) 223 timeout_us = 3000; 224 else 225 timeout_us = 1000; 226 } else { 227 timeout_us = 500; 228 } 229 230 if (DISPLAY_VER(dev_priv) >= 14) 231 ret = _wait_for(!(intel_de_read(dev_priv, 232 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 233 XELPDP_PORT_BUF_PHY_IDLE), 234 timeout_us, 10, 10); 235 else 236 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 237 timeout_us, 10, 10); 238 239 if (ret) 240 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 241 port_name(port)); 242 } 243 244 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 245 { 246 switch (pll->info->id) { 247 case DPLL_ID_WRPLL1: 248 return PORT_CLK_SEL_WRPLL1; 249 case DPLL_ID_WRPLL2: 250 return PORT_CLK_SEL_WRPLL2; 251 case DPLL_ID_SPLL: 252 return PORT_CLK_SEL_SPLL; 253 case DPLL_ID_LCPLL_810: 254 return PORT_CLK_SEL_LCPLL_810; 255 case DPLL_ID_LCPLL_1350: 256 return PORT_CLK_SEL_LCPLL_1350; 257 case DPLL_ID_LCPLL_2700: 258 return PORT_CLK_SEL_LCPLL_2700; 259 default: 260 MISSING_CASE(pll->info->id); 261 return PORT_CLK_SEL_NONE; 262 } 263 } 264 265 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 266 const struct intel_crtc_state *crtc_state) 267 { 268 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 269 int clock = crtc_state->port_clock; 270 const enum intel_dpll_id id = pll->info->id; 271 272 switch (id) { 273 default: 274 /* 275 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 276 * here, so do warn if this get passed in 277 */ 278 MISSING_CASE(id); 279 return DDI_CLK_SEL_NONE; 280 case DPLL_ID_ICL_TBTPLL: 281 switch (clock) { 282 case 162000: 283 return DDI_CLK_SEL_TBT_162; 284 case 270000: 285 return DDI_CLK_SEL_TBT_270; 286 case 540000: 287 return DDI_CLK_SEL_TBT_540; 288 case 810000: 289 return DDI_CLK_SEL_TBT_810; 290 default: 291 MISSING_CASE(clock); 292 return DDI_CLK_SEL_NONE; 293 } 294 case DPLL_ID_ICL_MGPLL1: 295 case DPLL_ID_ICL_MGPLL2: 296 case DPLL_ID_ICL_MGPLL3: 297 case DPLL_ID_ICL_MGPLL4: 298 case DPLL_ID_TGL_MGPLL5: 299 case DPLL_ID_TGL_MGPLL6: 300 return DDI_CLK_SEL_MG; 301 } 302 } 303 304 static u32 ddi_buf_phy_link_rate(int port_clock) 305 { 306 switch (port_clock) { 307 case 162000: 308 return DDI_BUF_PHY_LINK_RATE(0); 309 case 216000: 310 return DDI_BUF_PHY_LINK_RATE(4); 311 case 243000: 312 return DDI_BUF_PHY_LINK_RATE(5); 313 case 270000: 314 return DDI_BUF_PHY_LINK_RATE(1); 315 case 324000: 316 return DDI_BUF_PHY_LINK_RATE(6); 317 case 432000: 318 return DDI_BUF_PHY_LINK_RATE(7); 319 case 540000: 320 return DDI_BUF_PHY_LINK_RATE(2); 321 case 810000: 322 return DDI_BUF_PHY_LINK_RATE(3); 323 default: 324 MISSING_CASE(port_clock); 325 return DDI_BUF_PHY_LINK_RATE(0); 326 } 327 } 328 329 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 330 const struct intel_crtc_state *crtc_state) 331 { 332 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 333 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 334 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 335 336 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 337 intel_dp->DP = dig_port->saved_port_bits | 338 DDI_PORT_WIDTH(crtc_state->lane_count) | 339 DDI_BUF_TRANS_SELECT(0); 340 341 if (DISPLAY_VER(i915) >= 14) { 342 if (intel_dp_is_uhbr(crtc_state)) 343 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 344 else 345 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 346 } 347 348 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 349 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 350 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 351 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 352 } 353 } 354 355 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 356 enum port port) 357 { 358 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 359 360 switch (val) { 361 case DDI_CLK_SEL_NONE: 362 return 0; 363 case DDI_CLK_SEL_TBT_162: 364 return 162000; 365 case DDI_CLK_SEL_TBT_270: 366 return 270000; 367 case DDI_CLK_SEL_TBT_540: 368 return 540000; 369 case DDI_CLK_SEL_TBT_810: 370 return 810000; 371 default: 372 MISSING_CASE(val); 373 return 0; 374 } 375 } 376 377 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 378 { 379 /* CRT dotclock is determined via other means */ 380 if (pipe_config->has_pch_encoder) 381 return; 382 383 pipe_config->hw.adjusted_mode.crtc_clock = 384 intel_crtc_dotclock(pipe_config); 385 } 386 387 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 388 const struct drm_connector_state *conn_state) 389 { 390 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 392 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 393 u32 temp; 394 395 if (!intel_crtc_has_dp_encoder(crtc_state)) 396 return; 397 398 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 399 400 temp = DP_MSA_MISC_SYNC_CLOCK; 401 402 switch (crtc_state->pipe_bpp) { 403 case 18: 404 temp |= DP_MSA_MISC_6_BPC; 405 break; 406 case 24: 407 temp |= DP_MSA_MISC_8_BPC; 408 break; 409 case 30: 410 temp |= DP_MSA_MISC_10_BPC; 411 break; 412 case 36: 413 temp |= DP_MSA_MISC_12_BPC; 414 break; 415 default: 416 MISSING_CASE(crtc_state->pipe_bpp); 417 break; 418 } 419 420 /* nonsense combination */ 421 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 422 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 423 424 if (crtc_state->limited_color_range) 425 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 426 427 /* 428 * As per DP 1.2 spec section 2.3.4.3 while sending 429 * YCBCR 444 signals we should program MSA MISC1/0 fields with 430 * colorspace information. 431 */ 432 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 433 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 434 435 /* 436 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 437 * of Color Encoding Format and Content Color Gamut] while sending 438 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 439 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 440 */ 441 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 442 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 443 444 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 445 temp); 446 } 447 448 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 449 { 450 if (master_transcoder == TRANSCODER_EDP) 451 return 0; 452 else 453 return master_transcoder + 1; 454 } 455 456 static void 457 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 458 const struct intel_crtc_state *crtc_state) 459 { 460 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 461 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 462 u32 val = 0; 463 464 if (intel_dp_is_uhbr(crtc_state)) 465 val = TRANS_DP2_128B132B_CHANNEL_CODING; 466 467 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 468 } 469 470 /* 471 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 472 * 473 * Only intended to be used by intel_ddi_enable_transcoder_func() and 474 * intel_ddi_config_transcoder_func(). 475 */ 476 static u32 477 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 478 const struct intel_crtc_state *crtc_state) 479 { 480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 482 enum pipe pipe = crtc->pipe; 483 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 484 enum port port = encoder->port; 485 u32 temp; 486 487 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 488 temp = TRANS_DDI_FUNC_ENABLE; 489 if (DISPLAY_VER(dev_priv) >= 12) 490 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 491 else 492 temp |= TRANS_DDI_SELECT_PORT(port); 493 494 switch (crtc_state->pipe_bpp) { 495 default: 496 MISSING_CASE(crtc_state->pipe_bpp); 497 fallthrough; 498 case 18: 499 temp |= TRANS_DDI_BPC_6; 500 break; 501 case 24: 502 temp |= TRANS_DDI_BPC_8; 503 break; 504 case 30: 505 temp |= TRANS_DDI_BPC_10; 506 break; 507 case 36: 508 temp |= TRANS_DDI_BPC_12; 509 break; 510 } 511 512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 513 temp |= TRANS_DDI_PVSYNC; 514 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 515 temp |= TRANS_DDI_PHSYNC; 516 517 if (cpu_transcoder == TRANSCODER_EDP) { 518 switch (pipe) { 519 default: 520 MISSING_CASE(pipe); 521 fallthrough; 522 case PIPE_A: 523 /* On Haswell, can only use the always-on power well for 524 * eDP when not using the panel fitter, and when not 525 * using motion blur mitigation (which we don't 526 * support). */ 527 if (crtc_state->pch_pfit.force_thru) 528 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 529 else 530 temp |= TRANS_DDI_EDP_INPUT_A_ON; 531 break; 532 case PIPE_B: 533 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 534 break; 535 case PIPE_C: 536 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 537 break; 538 } 539 } 540 541 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 542 if (crtc_state->has_hdmi_sink) 543 temp |= TRANS_DDI_MODE_SELECT_HDMI; 544 else 545 temp |= TRANS_DDI_MODE_SELECT_DVI; 546 547 if (crtc_state->hdmi_scrambling) 548 temp |= TRANS_DDI_HDMI_SCRAMBLING; 549 if (crtc_state->hdmi_high_tmds_clock_ratio) 550 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 551 if (DISPLAY_VER(dev_priv) >= 14) 552 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 553 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 554 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 555 temp |= (crtc_state->fdi_lanes - 1) << 1; 556 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 557 if (intel_dp_is_uhbr(crtc_state)) 558 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 559 else 560 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 561 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 562 563 if (DISPLAY_VER(dev_priv) >= 12) { 564 enum transcoder master; 565 566 master = crtc_state->mst_master_transcoder; 567 drm_WARN_ON(&dev_priv->drm, 568 master == INVALID_TRANSCODER); 569 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 570 } 571 } else { 572 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 573 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 574 } 575 576 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 577 crtc_state->master_transcoder != INVALID_TRANSCODER) { 578 u8 master_select = 579 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 580 581 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 582 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 583 } 584 585 return temp; 586 } 587 588 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 589 const struct intel_crtc_state *crtc_state) 590 { 591 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 592 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 593 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 594 595 if (DISPLAY_VER(dev_priv) >= 11) { 596 enum transcoder master_transcoder = crtc_state->master_transcoder; 597 u32 ctl2 = 0; 598 599 if (master_transcoder != INVALID_TRANSCODER) { 600 u8 master_select = 601 bdw_trans_port_sync_master_select(master_transcoder); 602 603 ctl2 |= PORT_SYNC_MODE_ENABLE | 604 PORT_SYNC_MODE_MASTER_SELECT(master_select); 605 } 606 607 intel_de_write(dev_priv, 608 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 609 ctl2); 610 } 611 612 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 613 intel_ddi_transcoder_func_reg_val_get(encoder, 614 crtc_state)); 615 } 616 617 /* 618 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 619 * bit. 620 */ 621 static void 622 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 623 const struct intel_crtc_state *crtc_state) 624 { 625 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 628 u32 ctl; 629 630 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 631 ctl &= ~TRANS_DDI_FUNC_ENABLE; 632 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 633 ctl); 634 } 635 636 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 637 { 638 struct intel_display *display = to_intel_display(crtc_state); 639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 641 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 642 u32 ctl; 643 644 if (DISPLAY_VER(dev_priv) >= 11) 645 intel_de_write(dev_priv, 646 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 647 0); 648 649 ctl = intel_de_read(dev_priv, 650 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 651 652 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 653 654 ctl &= ~TRANS_DDI_FUNC_ENABLE; 655 656 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 657 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 658 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 659 660 if (DISPLAY_VER(dev_priv) >= 12) { 661 if (!intel_dp_mst_is_master_trans(crtc_state)) { 662 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 663 TRANS_DDI_MODE_SELECT_MASK); 664 } 665 } else { 666 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 667 } 668 669 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 670 ctl); 671 672 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 673 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 674 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 675 /* Quirk time at 100ms for reliable operation */ 676 msleep(100); 677 } 678 } 679 680 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 681 enum transcoder cpu_transcoder, 682 bool enable, u32 hdcp_mask) 683 { 684 struct drm_device *dev = intel_encoder->base.dev; 685 struct drm_i915_private *dev_priv = to_i915(dev); 686 intel_wakeref_t wakeref; 687 int ret = 0; 688 689 wakeref = intel_display_power_get_if_enabled(dev_priv, 690 intel_encoder->power_domain); 691 if (drm_WARN_ON(dev, !wakeref)) 692 return -ENXIO; 693 694 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 695 hdcp_mask, enable ? hdcp_mask : 0); 696 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 697 return ret; 698 } 699 700 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 701 { 702 struct drm_device *dev = intel_connector->base.dev; 703 struct drm_i915_private *dev_priv = to_i915(dev); 704 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 705 int type = intel_connector->base.connector_type; 706 enum port port = encoder->port; 707 enum transcoder cpu_transcoder; 708 intel_wakeref_t wakeref; 709 enum pipe pipe = 0; 710 u32 tmp; 711 bool ret; 712 713 wakeref = intel_display_power_get_if_enabled(dev_priv, 714 encoder->power_domain); 715 if (!wakeref) 716 return false; 717 718 if (!encoder->get_hw_state(encoder, &pipe)) { 719 ret = false; 720 goto out; 721 } 722 723 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 724 cpu_transcoder = TRANSCODER_EDP; 725 else 726 cpu_transcoder = (enum transcoder) pipe; 727 728 tmp = intel_de_read(dev_priv, 729 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 730 731 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 732 case TRANS_DDI_MODE_SELECT_HDMI: 733 case TRANS_DDI_MODE_SELECT_DVI: 734 ret = type == DRM_MODE_CONNECTOR_HDMIA; 735 break; 736 737 case TRANS_DDI_MODE_SELECT_DP_SST: 738 ret = type == DRM_MODE_CONNECTOR_eDP || 739 type == DRM_MODE_CONNECTOR_DisplayPort; 740 break; 741 742 case TRANS_DDI_MODE_SELECT_DP_MST: 743 /* if the transcoder is in MST state then 744 * connector isn't connected */ 745 ret = false; 746 break; 747 748 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 749 if (HAS_DP20(dev_priv)) 750 /* 128b/132b */ 751 ret = false; 752 else 753 /* FDI */ 754 ret = type == DRM_MODE_CONNECTOR_VGA; 755 break; 756 757 default: 758 ret = false; 759 break; 760 } 761 762 out: 763 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 764 765 return ret; 766 } 767 768 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 769 u8 *pipe_mask, bool *is_dp_mst) 770 { 771 struct drm_device *dev = encoder->base.dev; 772 struct drm_i915_private *dev_priv = to_i915(dev); 773 enum port port = encoder->port; 774 intel_wakeref_t wakeref; 775 enum pipe p; 776 u32 tmp; 777 u8 mst_pipe_mask; 778 779 *pipe_mask = 0; 780 *is_dp_mst = false; 781 782 wakeref = intel_display_power_get_if_enabled(dev_priv, 783 encoder->power_domain); 784 if (!wakeref) 785 return; 786 787 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 788 if (!(tmp & DDI_BUF_CTL_ENABLE)) 789 goto out; 790 791 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 792 tmp = intel_de_read(dev_priv, 793 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 794 795 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 796 default: 797 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 798 fallthrough; 799 case TRANS_DDI_EDP_INPUT_A_ON: 800 case TRANS_DDI_EDP_INPUT_A_ONOFF: 801 *pipe_mask = BIT(PIPE_A); 802 break; 803 case TRANS_DDI_EDP_INPUT_B_ONOFF: 804 *pipe_mask = BIT(PIPE_B); 805 break; 806 case TRANS_DDI_EDP_INPUT_C_ONOFF: 807 *pipe_mask = BIT(PIPE_C); 808 break; 809 } 810 811 goto out; 812 } 813 814 mst_pipe_mask = 0; 815 for_each_pipe(dev_priv, p) { 816 enum transcoder cpu_transcoder = (enum transcoder)p; 817 unsigned int port_mask, ddi_select; 818 intel_wakeref_t trans_wakeref; 819 820 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 821 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 822 if (!trans_wakeref) 823 continue; 824 825 if (DISPLAY_VER(dev_priv) >= 12) { 826 port_mask = TGL_TRANS_DDI_PORT_MASK; 827 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 828 } else { 829 port_mask = TRANS_DDI_PORT_MASK; 830 ddi_select = TRANS_DDI_SELECT_PORT(port); 831 } 832 833 tmp = intel_de_read(dev_priv, 834 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 835 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 836 trans_wakeref); 837 838 if ((tmp & port_mask) != ddi_select) 839 continue; 840 841 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 842 (HAS_DP20(dev_priv) && 843 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 844 mst_pipe_mask |= BIT(p); 845 846 *pipe_mask |= BIT(p); 847 } 848 849 if (!*pipe_mask) 850 drm_dbg_kms(&dev_priv->drm, 851 "No pipe for [ENCODER:%d:%s] found\n", 852 encoder->base.base.id, encoder->base.name); 853 854 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 855 drm_dbg_kms(&dev_priv->drm, 856 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 857 encoder->base.base.id, encoder->base.name, 858 *pipe_mask); 859 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 860 } 861 862 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 863 drm_dbg_kms(&dev_priv->drm, 864 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 865 encoder->base.base.id, encoder->base.name, 866 *pipe_mask, mst_pipe_mask); 867 else 868 *is_dp_mst = mst_pipe_mask; 869 870 out: 871 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 872 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 873 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 874 BXT_PHY_LANE_POWERDOWN_ACK | 875 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 876 drm_err(&dev_priv->drm, 877 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 878 encoder->base.base.id, encoder->base.name, tmp); 879 } 880 881 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 882 } 883 884 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 885 enum pipe *pipe) 886 { 887 u8 pipe_mask; 888 bool is_mst; 889 890 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 891 892 if (is_mst || !pipe_mask) 893 return false; 894 895 *pipe = ffs(pipe_mask) - 1; 896 897 return true; 898 } 899 900 static enum intel_display_power_domain 901 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 902 const struct intel_crtc_state *crtc_state) 903 { 904 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 905 906 /* 907 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 908 * DC states enabled at the same time, while for driver initiated AUX 909 * transfers we need the same AUX IOs to be powered but with DC states 910 * disabled. Accordingly use the AUX_IO_<port> power domain here which 911 * leaves DC states enabled. 912 * 913 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 914 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 915 * well, so we can acquire a wider AUX_<port> power domain reference 916 * instead of a specific AUX_IO_<port> reference without powering up any 917 * extra wells. 918 */ 919 if (intel_encoder_can_psr(&dig_port->base)) 920 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 921 else if (DISPLAY_VER(i915) < 14 && 922 (intel_crtc_has_dp_encoder(crtc_state) || 923 intel_encoder_is_tc(&dig_port->base))) 924 return intel_aux_power_domain(dig_port); 925 else 926 return POWER_DOMAIN_INVALID; 927 } 928 929 static void 930 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 931 const struct intel_crtc_state *crtc_state) 932 { 933 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 934 enum intel_display_power_domain domain = 935 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 936 937 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 938 939 if (domain == POWER_DOMAIN_INVALID) 940 return; 941 942 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 943 } 944 945 static void 946 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 947 const struct intel_crtc_state *crtc_state) 948 { 949 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 950 enum intel_display_power_domain domain = 951 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 952 intel_wakeref_t wf; 953 954 wf = fetch_and_zero(&dig_port->aux_wakeref); 955 if (!wf) 956 return; 957 958 intel_display_power_put(i915, domain, wf); 959 } 960 961 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 962 struct intel_crtc_state *crtc_state) 963 { 964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 965 struct intel_digital_port *dig_port; 966 967 /* 968 * TODO: Add support for MST encoders. Atm, the following should never 969 * happen since fake-MST encoders don't set their get_power_domains() 970 * hook. 971 */ 972 if (drm_WARN_ON(&dev_priv->drm, 973 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 974 return; 975 976 dig_port = enc_to_dig_port(encoder); 977 978 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 979 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 980 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 981 dig_port->ddi_io_power_domain); 982 } 983 984 main_link_aux_power_domain_get(dig_port, crtc_state); 985 } 986 987 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 988 const struct intel_crtc_state *crtc_state) 989 { 990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 992 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 993 enum phy phy = intel_encoder_to_phy(encoder); 994 u32 val; 995 996 if (cpu_transcoder == TRANSCODER_EDP) 997 return; 998 999 if (DISPLAY_VER(dev_priv) >= 13) 1000 val = TGL_TRANS_CLK_SEL_PORT(phy); 1001 else if (DISPLAY_VER(dev_priv) >= 12) 1002 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1003 else 1004 val = TRANS_CLK_SEL_PORT(encoder->port); 1005 1006 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1007 } 1008 1009 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1010 { 1011 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1012 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1013 u32 val; 1014 1015 if (cpu_transcoder == TRANSCODER_EDP) 1016 return; 1017 1018 if (DISPLAY_VER(dev_priv) >= 12) 1019 val = TGL_TRANS_CLK_SEL_DISABLED; 1020 else 1021 val = TRANS_CLK_SEL_DISABLED; 1022 1023 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1024 } 1025 1026 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1027 enum port port, u8 iboost) 1028 { 1029 u32 tmp; 1030 1031 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1032 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1033 if (iboost) 1034 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1035 else 1036 tmp |= BALANCE_LEG_DISABLE(port); 1037 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1038 } 1039 1040 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state, 1042 int level) 1043 { 1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1046 u8 iboost; 1047 1048 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1049 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1050 else 1051 iboost = intel_bios_dp_boost_level(encoder->devdata); 1052 1053 if (iboost == 0) { 1054 const struct intel_ddi_buf_trans *trans; 1055 int n_entries; 1056 1057 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1058 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1059 return; 1060 1061 iboost = trans->entries[level].hsw.i_boost; 1062 } 1063 1064 /* Make sure that the requested I_boost is valid */ 1065 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1066 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1067 return; 1068 } 1069 1070 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1071 1072 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1073 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1074 } 1075 1076 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1077 const struct intel_crtc_state *crtc_state) 1078 { 1079 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1081 int n_entries; 1082 1083 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1084 1085 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1086 n_entries = 1; 1087 if (drm_WARN_ON(&dev_priv->drm, 1088 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1089 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1090 1091 return index_to_dp_signal_levels[n_entries - 1] & 1092 DP_TRAIN_VOLTAGE_SWING_MASK; 1093 } 1094 1095 /* 1096 * We assume that the full set of pre-emphasis values can be 1097 * used on all DDI platforms. Should that change we need to 1098 * rethink this code. 1099 */ 1100 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1101 { 1102 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1103 } 1104 1105 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1106 int lane) 1107 { 1108 if (crtc_state->port_clock > 600000) 1109 return 0; 1110 1111 if (crtc_state->lane_count == 4) 1112 return lane >= 1 ? LOADGEN_SELECT : 0; 1113 else 1114 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1115 } 1116 1117 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1118 const struct intel_crtc_state *crtc_state) 1119 { 1120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1121 const struct intel_ddi_buf_trans *trans; 1122 enum phy phy = intel_encoder_to_phy(encoder); 1123 int n_entries, ln; 1124 u32 val; 1125 1126 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1127 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1128 return; 1129 1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1131 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1132 1133 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1134 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1135 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1136 intel_dp->hobl_active ? val : 0); 1137 } 1138 1139 /* Set PORT_TX_DW5 */ 1140 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1141 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1142 TAP2_DISABLE | TAP3_DISABLE); 1143 val |= SCALING_MODE_SEL(0x2); 1144 val |= RTERM_SELECT(0x6); 1145 val |= TAP3_DISABLE; 1146 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1147 1148 /* Program PORT_TX_DW2 */ 1149 for (ln = 0; ln < 4; ln++) { 1150 int level = intel_ddi_level(encoder, crtc_state, ln); 1151 1152 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1153 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1154 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1155 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1156 RCOMP_SCALAR(0x98)); 1157 } 1158 1159 /* Program PORT_TX_DW4 */ 1160 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1161 for (ln = 0; ln < 4; ln++) { 1162 int level = intel_ddi_level(encoder, crtc_state, ln); 1163 1164 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1165 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1166 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1167 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1168 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1169 } 1170 1171 /* Program PORT_TX_DW7 */ 1172 for (ln = 0; ln < 4; ln++) { 1173 int level = intel_ddi_level(encoder, crtc_state, ln); 1174 1175 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1176 N_SCALAR_MASK, 1177 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1178 } 1179 } 1180 1181 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1182 const struct intel_crtc_state *crtc_state) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1185 enum phy phy = intel_encoder_to_phy(encoder); 1186 u32 val; 1187 int ln; 1188 1189 /* 1190 * 1. If port type is eDP or DP, 1191 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1192 * else clear to 0b. 1193 */ 1194 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1195 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1196 val &= ~COMMON_KEEPER_EN; 1197 else 1198 val |= COMMON_KEEPER_EN; 1199 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1200 1201 /* 2. Program loadgen select */ 1202 /* 1203 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1204 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1205 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1206 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1207 */ 1208 for (ln = 0; ln < 4; ln++) { 1209 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1210 LOADGEN_SELECT, 1211 icl_combo_phy_loadgen_select(crtc_state, ln)); 1212 } 1213 1214 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1215 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1216 0, SUS_CLOCK_CONFIG); 1217 1218 /* 4. Clear training enable to change swing values */ 1219 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1220 val &= ~TX_TRAINING_EN; 1221 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1222 1223 /* 5. Program swing and de-emphasis */ 1224 icl_ddi_combo_vswing_program(encoder, crtc_state); 1225 1226 /* 6. Set training enable to trigger update */ 1227 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1228 val |= TX_TRAINING_EN; 1229 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1230 } 1231 1232 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1233 const struct intel_crtc_state *crtc_state) 1234 { 1235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1236 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1237 const struct intel_ddi_buf_trans *trans; 1238 int n_entries, ln; 1239 1240 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1241 return; 1242 1243 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1244 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1245 return; 1246 1247 for (ln = 0; ln < 2; ln++) { 1248 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1249 CRI_USE_FS32, 0); 1250 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1251 CRI_USE_FS32, 0); 1252 } 1253 1254 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1255 for (ln = 0; ln < 2; ln++) { 1256 int level; 1257 1258 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1259 1260 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1261 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1262 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1263 1264 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1265 1266 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1267 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1268 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1269 } 1270 1271 /* Program MG_TX_DRVCTRL with values from vswing table */ 1272 for (ln = 0; ln < 2; ln++) { 1273 int level; 1274 1275 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1276 1277 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1278 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1279 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1280 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1281 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1282 CRI_TXDEEMPH_OVERRIDE_EN); 1283 1284 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1285 1286 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1287 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1288 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1289 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1290 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1291 CRI_TXDEEMPH_OVERRIDE_EN); 1292 1293 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1294 } 1295 1296 /* 1297 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1298 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1299 * values from table for which TX1 and TX2 enabled. 1300 */ 1301 for (ln = 0; ln < 2; ln++) { 1302 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1303 CFG_LOW_RATE_LKREN_EN, 1304 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1305 } 1306 1307 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1308 for (ln = 0; ln < 2; ln++) { 1309 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1310 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1311 CFG_AMI_CK_DIV_OVERRIDE_EN, 1312 crtc_state->port_clock > 500000 ? 1313 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1314 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1315 1316 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1317 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1318 CFG_AMI_CK_DIV_OVERRIDE_EN, 1319 crtc_state->port_clock > 500000 ? 1320 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1321 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1322 } 1323 1324 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1325 for (ln = 0; ln < 2; ln++) { 1326 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1327 0, CRI_CALCINIT); 1328 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1329 0, CRI_CALCINIT); 1330 } 1331 } 1332 1333 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1334 const struct intel_crtc_state *crtc_state) 1335 { 1336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1337 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1338 const struct intel_ddi_buf_trans *trans; 1339 int n_entries, ln; 1340 1341 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1342 return; 1343 1344 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1345 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1346 return; 1347 1348 for (ln = 0; ln < 2; ln++) { 1349 int level; 1350 1351 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1352 1353 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1354 1355 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1356 DKL_TX_PRESHOOT_COEFF_MASK | 1357 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1358 DKL_TX_VSWING_CONTROL_MASK, 1359 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1360 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1361 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1362 1363 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1364 1365 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1366 DKL_TX_PRESHOOT_COEFF_MASK | 1367 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1368 DKL_TX_VSWING_CONTROL_MASK, 1369 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1370 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1371 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1372 1373 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1374 DKL_TX_DP20BITMODE, 0); 1375 1376 if (IS_ALDERLAKE_P(dev_priv)) { 1377 u32 val; 1378 1379 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1380 if (ln == 0) { 1381 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1382 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1383 } else { 1384 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1385 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1386 } 1387 } else { 1388 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1389 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1390 } 1391 1392 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1393 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1394 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1395 val); 1396 } 1397 } 1398 } 1399 1400 static int translate_signal_level(struct intel_dp *intel_dp, 1401 u8 signal_levels) 1402 { 1403 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1404 int i; 1405 1406 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1407 if (index_to_dp_signal_levels[i] == signal_levels) 1408 return i; 1409 } 1410 1411 drm_WARN(&i915->drm, 1, 1412 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1413 signal_levels); 1414 1415 return 0; 1416 } 1417 1418 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1419 const struct intel_crtc_state *crtc_state, 1420 int lane) 1421 { 1422 u8 train_set = intel_dp->train_set[lane]; 1423 1424 if (intel_dp_is_uhbr(crtc_state)) { 1425 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1426 } else { 1427 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1428 DP_TRAIN_PRE_EMPHASIS_MASK); 1429 1430 return translate_signal_level(intel_dp, signal_levels); 1431 } 1432 } 1433 1434 int intel_ddi_level(struct intel_encoder *encoder, 1435 const struct intel_crtc_state *crtc_state, 1436 int lane) 1437 { 1438 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1439 const struct intel_ddi_buf_trans *trans; 1440 int level, n_entries; 1441 1442 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1443 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1444 return 0; 1445 1446 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1447 level = intel_ddi_hdmi_level(encoder, trans); 1448 else 1449 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1450 lane); 1451 1452 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1453 level = n_entries - 1; 1454 1455 return level; 1456 } 1457 1458 static void 1459 hsw_set_signal_levels(struct intel_encoder *encoder, 1460 const struct intel_crtc_state *crtc_state) 1461 { 1462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1463 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1464 int level = intel_ddi_level(encoder, crtc_state, 0); 1465 enum port port = encoder->port; 1466 u32 signal_levels; 1467 1468 if (has_iboost(dev_priv)) 1469 skl_ddi_set_iboost(encoder, crtc_state, level); 1470 1471 /* HDMI ignores the rest */ 1472 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1473 return; 1474 1475 signal_levels = DDI_BUF_TRANS_SELECT(level); 1476 1477 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1478 signal_levels); 1479 1480 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1481 intel_dp->DP |= signal_levels; 1482 1483 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1484 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1485 } 1486 1487 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1488 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1489 { 1490 mutex_lock(&i915->display.dpll.lock); 1491 1492 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1493 1494 /* 1495 * "This step and the step before must be 1496 * done with separate register writes." 1497 */ 1498 intel_de_rmw(i915, reg, clk_off, 0); 1499 1500 mutex_unlock(&i915->display.dpll.lock); 1501 } 1502 1503 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1504 u32 clk_off) 1505 { 1506 mutex_lock(&i915->display.dpll.lock); 1507 1508 intel_de_rmw(i915, reg, 0, clk_off); 1509 1510 mutex_unlock(&i915->display.dpll.lock); 1511 } 1512 1513 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1514 u32 clk_off) 1515 { 1516 return !(intel_de_read(i915, reg) & clk_off); 1517 } 1518 1519 static struct intel_shared_dpll * 1520 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1521 u32 clk_sel_mask, u32 clk_sel_shift) 1522 { 1523 enum intel_dpll_id id; 1524 1525 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1526 1527 return intel_get_shared_dpll_by_id(i915, id); 1528 } 1529 1530 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1531 const struct intel_crtc_state *crtc_state) 1532 { 1533 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1534 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1535 enum phy phy = intel_encoder_to_phy(encoder); 1536 1537 if (drm_WARN_ON(&i915->drm, !pll)) 1538 return; 1539 1540 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1541 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1542 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1543 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1544 } 1545 1546 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1547 { 1548 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1549 enum phy phy = intel_encoder_to_phy(encoder); 1550 1551 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1552 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1553 } 1554 1555 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1556 { 1557 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1558 enum phy phy = intel_encoder_to_phy(encoder); 1559 1560 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1561 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1562 } 1563 1564 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1565 { 1566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1567 enum phy phy = intel_encoder_to_phy(encoder); 1568 1569 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1570 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1571 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1572 } 1573 1574 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1575 const struct intel_crtc_state *crtc_state) 1576 { 1577 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1578 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1579 enum phy phy = intel_encoder_to_phy(encoder); 1580 1581 if (drm_WARN_ON(&i915->drm, !pll)) 1582 return; 1583 1584 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1585 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1586 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1587 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1588 } 1589 1590 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1591 { 1592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1593 enum phy phy = intel_encoder_to_phy(encoder); 1594 1595 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1596 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1597 } 1598 1599 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1600 { 1601 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1602 enum phy phy = intel_encoder_to_phy(encoder); 1603 1604 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1605 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1606 } 1607 1608 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1609 { 1610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1611 enum phy phy = intel_encoder_to_phy(encoder); 1612 1613 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1614 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1615 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1616 } 1617 1618 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1619 const struct intel_crtc_state *crtc_state) 1620 { 1621 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1622 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1623 enum phy phy = intel_encoder_to_phy(encoder); 1624 1625 if (drm_WARN_ON(&i915->drm, !pll)) 1626 return; 1627 1628 /* 1629 * If we fail this, something went very wrong: first 2 PLLs should be 1630 * used by first 2 phys and last 2 PLLs by last phys 1631 */ 1632 if (drm_WARN_ON(&i915->drm, 1633 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1634 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1635 return; 1636 1637 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1638 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1639 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1640 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1641 } 1642 1643 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1644 { 1645 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1646 enum phy phy = intel_encoder_to_phy(encoder); 1647 1648 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1649 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1650 } 1651 1652 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1653 { 1654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1655 enum phy phy = intel_encoder_to_phy(encoder); 1656 1657 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1658 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1659 } 1660 1661 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1662 { 1663 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1664 enum phy phy = intel_encoder_to_phy(encoder); 1665 enum intel_dpll_id id; 1666 u32 val; 1667 1668 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1669 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1670 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1671 id = val; 1672 1673 /* 1674 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1675 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1676 * bit for phy C and D. 1677 */ 1678 if (phy >= PHY_C) 1679 id += DPLL_ID_DG1_DPLL2; 1680 1681 return intel_get_shared_dpll_by_id(i915, id); 1682 } 1683 1684 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1685 const struct intel_crtc_state *crtc_state) 1686 { 1687 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1688 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1689 enum phy phy = intel_encoder_to_phy(encoder); 1690 1691 if (drm_WARN_ON(&i915->drm, !pll)) 1692 return; 1693 1694 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1695 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1696 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1697 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1698 } 1699 1700 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1701 { 1702 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1703 enum phy phy = intel_encoder_to_phy(encoder); 1704 1705 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1706 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1707 } 1708 1709 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1710 { 1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1712 enum phy phy = intel_encoder_to_phy(encoder); 1713 1714 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1715 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1716 } 1717 1718 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1719 { 1720 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1721 enum phy phy = intel_encoder_to_phy(encoder); 1722 1723 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1724 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1725 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1726 } 1727 1728 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1729 const struct intel_crtc_state *crtc_state) 1730 { 1731 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1732 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1733 enum port port = encoder->port; 1734 1735 if (drm_WARN_ON(&i915->drm, !pll)) 1736 return; 1737 1738 /* 1739 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1740 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1741 */ 1742 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1743 1744 icl_ddi_combo_enable_clock(encoder, crtc_state); 1745 } 1746 1747 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1748 { 1749 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1750 enum port port = encoder->port; 1751 1752 icl_ddi_combo_disable_clock(encoder); 1753 1754 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1755 } 1756 1757 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1758 { 1759 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1760 enum port port = encoder->port; 1761 u32 tmp; 1762 1763 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1764 1765 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1766 return false; 1767 1768 return icl_ddi_combo_is_clock_enabled(encoder); 1769 } 1770 1771 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1772 const struct intel_crtc_state *crtc_state) 1773 { 1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1775 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1776 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1777 enum port port = encoder->port; 1778 1779 if (drm_WARN_ON(&i915->drm, !pll)) 1780 return; 1781 1782 intel_de_write(i915, DDI_CLK_SEL(port), 1783 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1784 1785 mutex_lock(&i915->display.dpll.lock); 1786 1787 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1788 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1789 1790 mutex_unlock(&i915->display.dpll.lock); 1791 } 1792 1793 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1794 { 1795 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1796 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1797 enum port port = encoder->port; 1798 1799 mutex_lock(&i915->display.dpll.lock); 1800 1801 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1802 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1803 1804 mutex_unlock(&i915->display.dpll.lock); 1805 1806 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1807 } 1808 1809 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1810 { 1811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1812 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1813 enum port port = encoder->port; 1814 u32 tmp; 1815 1816 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1817 1818 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1819 return false; 1820 1821 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1822 1823 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1824 } 1825 1826 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1827 { 1828 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1829 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1830 enum port port = encoder->port; 1831 enum intel_dpll_id id; 1832 u32 tmp; 1833 1834 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1835 1836 switch (tmp & DDI_CLK_SEL_MASK) { 1837 case DDI_CLK_SEL_TBT_162: 1838 case DDI_CLK_SEL_TBT_270: 1839 case DDI_CLK_SEL_TBT_540: 1840 case DDI_CLK_SEL_TBT_810: 1841 id = DPLL_ID_ICL_TBTPLL; 1842 break; 1843 case DDI_CLK_SEL_MG: 1844 id = icl_tc_port_to_pll_id(tc_port); 1845 break; 1846 default: 1847 MISSING_CASE(tmp); 1848 fallthrough; 1849 case DDI_CLK_SEL_NONE: 1850 return NULL; 1851 } 1852 1853 return intel_get_shared_dpll_by_id(i915, id); 1854 } 1855 1856 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1857 { 1858 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1859 enum intel_dpll_id id; 1860 1861 switch (encoder->port) { 1862 case PORT_A: 1863 id = DPLL_ID_SKL_DPLL0; 1864 break; 1865 case PORT_B: 1866 id = DPLL_ID_SKL_DPLL1; 1867 break; 1868 case PORT_C: 1869 id = DPLL_ID_SKL_DPLL2; 1870 break; 1871 default: 1872 MISSING_CASE(encoder->port); 1873 return NULL; 1874 } 1875 1876 return intel_get_shared_dpll_by_id(i915, id); 1877 } 1878 1879 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1880 const struct intel_crtc_state *crtc_state) 1881 { 1882 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1883 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1884 enum port port = encoder->port; 1885 1886 if (drm_WARN_ON(&i915->drm, !pll)) 1887 return; 1888 1889 mutex_lock(&i915->display.dpll.lock); 1890 1891 intel_de_rmw(i915, DPLL_CTRL2, 1892 DPLL_CTRL2_DDI_CLK_OFF(port) | 1893 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1894 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1895 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1896 1897 mutex_unlock(&i915->display.dpll.lock); 1898 } 1899 1900 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1901 { 1902 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1903 enum port port = encoder->port; 1904 1905 mutex_lock(&i915->display.dpll.lock); 1906 1907 intel_de_rmw(i915, DPLL_CTRL2, 1908 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1909 1910 mutex_unlock(&i915->display.dpll.lock); 1911 } 1912 1913 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1914 { 1915 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1916 enum port port = encoder->port; 1917 1918 /* 1919 * FIXME Not sure if the override affects both 1920 * the PLL selection and the CLK_OFF bit. 1921 */ 1922 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1923 } 1924 1925 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1926 { 1927 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1928 enum port port = encoder->port; 1929 enum intel_dpll_id id; 1930 u32 tmp; 1931 1932 tmp = intel_de_read(i915, DPLL_CTRL2); 1933 1934 /* 1935 * FIXME Not sure if the override affects both 1936 * the PLL selection and the CLK_OFF bit. 1937 */ 1938 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1939 return NULL; 1940 1941 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1942 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1943 1944 return intel_get_shared_dpll_by_id(i915, id); 1945 } 1946 1947 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1948 const struct intel_crtc_state *crtc_state) 1949 { 1950 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1951 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1952 enum port port = encoder->port; 1953 1954 if (drm_WARN_ON(&i915->drm, !pll)) 1955 return; 1956 1957 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1958 } 1959 1960 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1961 { 1962 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1963 enum port port = encoder->port; 1964 1965 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1966 } 1967 1968 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 enum port port = encoder->port; 1972 1973 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1974 } 1975 1976 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1977 { 1978 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1979 enum port port = encoder->port; 1980 enum intel_dpll_id id; 1981 u32 tmp; 1982 1983 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1984 1985 switch (tmp & PORT_CLK_SEL_MASK) { 1986 case PORT_CLK_SEL_WRPLL1: 1987 id = DPLL_ID_WRPLL1; 1988 break; 1989 case PORT_CLK_SEL_WRPLL2: 1990 id = DPLL_ID_WRPLL2; 1991 break; 1992 case PORT_CLK_SEL_SPLL: 1993 id = DPLL_ID_SPLL; 1994 break; 1995 case PORT_CLK_SEL_LCPLL_810: 1996 id = DPLL_ID_LCPLL_810; 1997 break; 1998 case PORT_CLK_SEL_LCPLL_1350: 1999 id = DPLL_ID_LCPLL_1350; 2000 break; 2001 case PORT_CLK_SEL_LCPLL_2700: 2002 id = DPLL_ID_LCPLL_2700; 2003 break; 2004 default: 2005 MISSING_CASE(tmp); 2006 fallthrough; 2007 case PORT_CLK_SEL_NONE: 2008 return NULL; 2009 } 2010 2011 return intel_get_shared_dpll_by_id(i915, id); 2012 } 2013 2014 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2015 const struct intel_crtc_state *crtc_state) 2016 { 2017 if (encoder->enable_clock) 2018 encoder->enable_clock(encoder, crtc_state); 2019 } 2020 2021 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2022 { 2023 if (encoder->disable_clock) 2024 encoder->disable_clock(encoder); 2025 } 2026 2027 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2028 { 2029 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2030 u32 port_mask; 2031 bool ddi_clk_needed; 2032 2033 /* 2034 * In case of DP MST, we sanitize the primary encoder only, not the 2035 * virtual ones. 2036 */ 2037 if (encoder->type == INTEL_OUTPUT_DP_MST) 2038 return; 2039 2040 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2041 u8 pipe_mask; 2042 bool is_mst; 2043 2044 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2045 /* 2046 * In the unlikely case that BIOS enables DP in MST mode, just 2047 * warn since our MST HW readout is incomplete. 2048 */ 2049 if (drm_WARN_ON(&i915->drm, is_mst)) 2050 return; 2051 } 2052 2053 port_mask = BIT(encoder->port); 2054 ddi_clk_needed = encoder->base.crtc; 2055 2056 if (encoder->type == INTEL_OUTPUT_DSI) { 2057 struct intel_encoder *other_encoder; 2058 2059 port_mask = intel_dsi_encoder_ports(encoder); 2060 /* 2061 * Sanity check that we haven't incorrectly registered another 2062 * encoder using any of the ports of this DSI encoder. 2063 */ 2064 for_each_intel_encoder(&i915->drm, other_encoder) { 2065 if (other_encoder == encoder) 2066 continue; 2067 2068 if (drm_WARN_ON(&i915->drm, 2069 port_mask & BIT(other_encoder->port))) 2070 return; 2071 } 2072 /* 2073 * For DSI we keep the ddi clocks gated 2074 * except during enable/disable sequence. 2075 */ 2076 ddi_clk_needed = false; 2077 } 2078 2079 if (ddi_clk_needed || !encoder->is_clock_enabled || 2080 !encoder->is_clock_enabled(encoder)) 2081 return; 2082 2083 drm_dbg_kms(&i915->drm, 2084 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2085 encoder->base.base.id, encoder->base.name); 2086 2087 encoder->disable_clock(encoder); 2088 } 2089 2090 static void 2091 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2092 const struct intel_crtc_state *crtc_state) 2093 { 2094 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2095 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2096 u32 ln0, ln1, pin_assignment; 2097 u8 width; 2098 2099 if (!intel_encoder_is_tc(&dig_port->base) || 2100 intel_tc_port_in_tbt_alt_mode(dig_port)) 2101 return; 2102 2103 if (DISPLAY_VER(dev_priv) >= 12) { 2104 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2105 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2106 } else { 2107 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2108 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2109 } 2110 2111 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2112 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2113 2114 /* DPPATC */ 2115 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2116 width = crtc_state->lane_count; 2117 2118 switch (pin_assignment) { 2119 case 0x0: 2120 drm_WARN_ON(&dev_priv->drm, 2121 !intel_tc_port_in_legacy_mode(dig_port)); 2122 if (width == 1) { 2123 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2124 } else { 2125 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2126 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2127 } 2128 break; 2129 case 0x1: 2130 if (width == 4) { 2131 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2132 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2133 } 2134 break; 2135 case 0x2: 2136 if (width == 2) { 2137 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2138 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2139 } 2140 break; 2141 case 0x3: 2142 case 0x5: 2143 if (width == 1) { 2144 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2145 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2146 } else { 2147 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2148 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2149 } 2150 break; 2151 case 0x4: 2152 case 0x6: 2153 if (width == 1) { 2154 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2155 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2156 } else { 2157 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2158 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2159 } 2160 break; 2161 default: 2162 MISSING_CASE(pin_assignment); 2163 } 2164 2165 if (DISPLAY_VER(dev_priv) >= 12) { 2166 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2167 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2168 } else { 2169 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2170 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2171 } 2172 } 2173 2174 static enum transcoder 2175 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2176 { 2177 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2178 return crtc_state->mst_master_transcoder; 2179 else 2180 return crtc_state->cpu_transcoder; 2181 } 2182 2183 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2184 const struct intel_crtc_state *crtc_state) 2185 { 2186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2187 2188 if (DISPLAY_VER(dev_priv) >= 12) 2189 return TGL_DP_TP_CTL(dev_priv, 2190 tgl_dp_tp_transcoder(crtc_state)); 2191 else 2192 return DP_TP_CTL(encoder->port); 2193 } 2194 2195 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2196 const struct intel_crtc_state *crtc_state) 2197 { 2198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2199 2200 if (DISPLAY_VER(dev_priv) >= 12) 2201 return TGL_DP_TP_STATUS(dev_priv, 2202 tgl_dp_tp_transcoder(crtc_state)); 2203 else 2204 return DP_TP_STATUS(encoder->port); 2205 } 2206 2207 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2208 const struct intel_crtc_state *crtc_state, 2209 bool enable) 2210 { 2211 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2212 2213 if (!crtc_state->vrr.enable) 2214 return; 2215 2216 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2217 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2218 drm_dbg_kms(&i915->drm, 2219 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2220 str_enable_disable(enable)); 2221 } 2222 2223 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2224 const struct intel_crtc_state *crtc_state, 2225 bool enable) 2226 { 2227 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2228 2229 if (!crtc_state->fec_enable) 2230 return; 2231 2232 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2233 enable ? DP_FEC_READY : 0) <= 0) 2234 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2235 enable ? "enabled" : "disabled"); 2236 2237 if (enable && 2238 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2239 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2240 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2241 } 2242 2243 static int read_fec_detected_status(struct drm_dp_aux *aux) 2244 { 2245 int ret; 2246 u8 status; 2247 2248 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2249 if (ret < 0) 2250 return ret; 2251 2252 return status; 2253 } 2254 2255 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2256 { 2257 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2258 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2259 int status; 2260 int err; 2261 2262 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2263 status & mask || status < 0, 2264 10000, 200000); 2265 2266 if (!err && status >= 0) 2267 return; 2268 2269 if (err == -ETIMEDOUT) 2270 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2271 str_enabled_disabled(enabled)); 2272 else 2273 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2274 } 2275 2276 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2277 const struct intel_crtc_state *crtc_state, 2278 bool enabled) 2279 { 2280 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2282 int ret; 2283 2284 if (!crtc_state->fec_enable) 2285 return; 2286 2287 if (enabled) 2288 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2289 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2290 else 2291 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2292 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2293 2294 if (ret) 2295 drm_err(&i915->drm, 2296 "Timeout waiting for FEC live state to get %s\n", 2297 str_enabled_disabled(enabled)); 2298 2299 /* 2300 * At least the Synoptics MST hub doesn't set the detected flag for 2301 * FEC decoding disabling so skip waiting for that. 2302 */ 2303 if (enabled) 2304 wait_for_fec_detected(&intel_dp->aux, enabled); 2305 } 2306 2307 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2308 const struct intel_crtc_state *crtc_state) 2309 { 2310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2311 2312 if (!crtc_state->fec_enable) 2313 return; 2314 2315 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2316 0, DP_TP_CTL_FEC_ENABLE); 2317 } 2318 2319 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2320 const struct intel_crtc_state *crtc_state) 2321 { 2322 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2323 2324 if (!crtc_state->fec_enable) 2325 return; 2326 2327 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2328 DP_TP_CTL_FEC_ENABLE, 0); 2329 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2330 } 2331 2332 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2333 const struct intel_crtc_state *crtc_state) 2334 { 2335 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2336 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2337 2338 if (intel_encoder_is_combo(encoder)) { 2339 enum phy phy = intel_encoder_to_phy(encoder); 2340 bool lane_reversal = 2341 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2342 2343 intel_combo_phy_power_up_lanes(i915, phy, false, 2344 crtc_state->lane_count, 2345 lane_reversal); 2346 } 2347 } 2348 2349 /* 2350 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2351 * platforms. 2352 */ 2353 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2354 { 2355 if (DISPLAY_VER(i915) > 20) 2356 return ~0; 2357 else if (IS_ALDERLAKE_P(i915)) 2358 return BIT(PIPE_A) | BIT(PIPE_B); 2359 else 2360 return BIT(PIPE_A); 2361 } 2362 2363 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2364 struct intel_crtc_state *pipe_config) 2365 { 2366 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2367 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2368 enum pipe pipe = crtc->pipe; 2369 u32 dss1; 2370 2371 if (!HAS_MSO(i915)) 2372 return; 2373 2374 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2375 2376 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2377 if (!pipe_config->splitter.enable) 2378 return; 2379 2380 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2381 pipe_config->splitter.enable = false; 2382 return; 2383 } 2384 2385 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2386 default: 2387 drm_WARN(&i915->drm, true, 2388 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2389 fallthrough; 2390 case SPLITTER_CONFIGURATION_2_SEGMENT: 2391 pipe_config->splitter.link_count = 2; 2392 break; 2393 case SPLITTER_CONFIGURATION_4_SEGMENT: 2394 pipe_config->splitter.link_count = 4; 2395 break; 2396 } 2397 2398 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2399 } 2400 2401 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2402 { 2403 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2404 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2405 enum pipe pipe = crtc->pipe; 2406 u32 dss1 = 0; 2407 2408 if (!HAS_MSO(i915)) 2409 return; 2410 2411 if (crtc_state->splitter.enable) { 2412 dss1 |= SPLITTER_ENABLE; 2413 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2414 if (crtc_state->splitter.link_count == 2) 2415 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2416 else 2417 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2418 } 2419 2420 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2421 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2422 OVERLAP_PIXELS_MASK, dss1); 2423 } 2424 2425 static u8 mtl_get_port_width(u8 lane_count) 2426 { 2427 switch (lane_count) { 2428 case 1: 2429 return 0; 2430 case 2: 2431 return 1; 2432 case 3: 2433 return 4; 2434 case 4: 2435 return 3; 2436 default: 2437 MISSING_CASE(lane_count); 2438 return 4; 2439 } 2440 } 2441 2442 static void 2443 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2444 { 2445 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2446 enum port port = encoder->port; 2447 i915_reg_t reg; 2448 u32 set_bits, wait_bits; 2449 2450 if (DISPLAY_VER(dev_priv) >= 20) { 2451 reg = DDI_BUF_CTL(port); 2452 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2453 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2454 } else { 2455 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2456 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2457 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2458 } 2459 2460 intel_de_rmw(dev_priv, reg, 0, set_bits); 2461 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2462 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2463 port_name(port)); 2464 } 2465 } 2466 2467 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2468 const struct intel_crtc_state *crtc_state) 2469 { 2470 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2471 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2472 enum port port = encoder->port; 2473 u32 val; 2474 2475 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2476 val &= ~XELPDP_PORT_WIDTH_MASK; 2477 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2478 2479 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2480 if (intel_dp_is_uhbr(crtc_state)) 2481 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2482 else 2483 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2484 2485 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2486 val |= XELPDP_PORT_REVERSAL; 2487 2488 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2489 } 2490 2491 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2492 { 2493 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2494 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2495 u32 val; 2496 2497 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2498 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2499 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2500 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2501 } 2502 2503 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2504 struct intel_encoder *encoder, 2505 const struct intel_crtc_state *crtc_state, 2506 const struct drm_connector_state *conn_state) 2507 { 2508 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2509 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2510 2511 intel_dp_set_link_params(intel_dp, 2512 crtc_state->port_clock, 2513 crtc_state->lane_count); 2514 2515 /* 2516 * We only configure what the register value will be here. Actual 2517 * enabling happens during link training farther down. 2518 */ 2519 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2520 2521 /* 2522 * 1. Enable Power Wells 2523 * 2524 * This was handled at the beginning of intel_atomic_commit_tail(), 2525 * before we called down into this function. 2526 */ 2527 2528 /* 2. PMdemand was already set */ 2529 2530 /* 3. Select Thunderbolt */ 2531 mtl_port_buf_ctl_io_selection(encoder); 2532 2533 /* 4. Enable Panel Power if PPS is required */ 2534 intel_pps_on(intel_dp); 2535 2536 /* 5. Enable the port PLL */ 2537 intel_ddi_enable_clock(encoder, crtc_state); 2538 2539 /* 2540 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2541 * Transcoder. 2542 */ 2543 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2544 2545 /* 2546 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2547 */ 2548 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2549 2550 /* 2551 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2552 * Transport Select 2553 */ 2554 intel_ddi_config_transcoder_func(encoder, crtc_state); 2555 2556 /* 2557 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2558 */ 2559 intel_ddi_mso_configure(crtc_state); 2560 2561 if (!is_mst) 2562 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2563 2564 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2565 if (!is_mst) 2566 intel_dp_sink_enable_decompression(state, 2567 to_intel_connector(conn_state->connector), 2568 crtc_state); 2569 2570 /* 2571 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2572 * in the FEC_CONFIGURATION register to 1 before initiating link 2573 * training 2574 */ 2575 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2576 2577 intel_dp_check_frl_training(intel_dp); 2578 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2579 2580 /* 2581 * 6. The rest of the below are substeps under the bspec's "Enable and 2582 * Train Display Port" step. Note that steps that are specific to 2583 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2584 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2585 * us when active_mst_links==0, so any steps designated for "single 2586 * stream or multi-stream master transcoder" can just be performed 2587 * unconditionally here. 2588 * 2589 * mtl_ddi_prepare_link_retrain() that is called by 2590 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2591 * 6.i and 6.j 2592 * 2593 * 6.k Follow DisplayPort specification training sequence (see notes for 2594 * failure handling) 2595 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2596 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2597 * (timeout after 800 us) 2598 */ 2599 intel_dp_start_link_train(state, intel_dp, crtc_state); 2600 2601 /* 6.n Set DP_TP_CTL link training to Normal */ 2602 if (!is_trans_port_sync_mode(crtc_state)) 2603 intel_dp_stop_link_train(intel_dp, crtc_state); 2604 2605 /* 6.o Configure and enable FEC if needed */ 2606 intel_ddi_enable_fec(encoder, crtc_state); 2607 2608 if (!is_mst) 2609 intel_dsc_dp_pps_write(encoder, crtc_state); 2610 } 2611 2612 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2613 struct intel_encoder *encoder, 2614 const struct intel_crtc_state *crtc_state, 2615 const struct drm_connector_state *conn_state) 2616 { 2617 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2619 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2620 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2621 2622 intel_dp_set_link_params(intel_dp, 2623 crtc_state->port_clock, 2624 crtc_state->lane_count); 2625 2626 /* 2627 * We only configure what the register value will be here. Actual 2628 * enabling happens during link training farther down. 2629 */ 2630 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2631 2632 /* 2633 * 1. Enable Power Wells 2634 * 2635 * This was handled at the beginning of intel_atomic_commit_tail(), 2636 * before we called down into this function. 2637 */ 2638 2639 /* 2. Enable Panel Power if PPS is required */ 2640 intel_pps_on(intel_dp); 2641 2642 /* 2643 * 3. For non-TBT Type-C ports, set FIA lane count 2644 * (DFLEXDPSP.DPX4TXLATC) 2645 * 2646 * This was done before tgl_ddi_pre_enable_dp by 2647 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2648 */ 2649 2650 /* 2651 * 4. Enable the port PLL. 2652 * 2653 * The PLL enabling itself was already done before this function by 2654 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2655 * configure the PLL to port mapping here. 2656 */ 2657 intel_ddi_enable_clock(encoder, crtc_state); 2658 2659 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2660 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2661 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2662 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2663 dig_port->ddi_io_power_domain); 2664 } 2665 2666 /* 6. Program DP_MODE */ 2667 icl_program_mg_dp_mode(dig_port, crtc_state); 2668 2669 /* 2670 * 7. The rest of the below are substeps under the bspec's "Enable and 2671 * Train Display Port" step. Note that steps that are specific to 2672 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2673 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2674 * us when active_mst_links==0, so any steps designated for "single 2675 * stream or multi-stream master transcoder" can just be performed 2676 * unconditionally here. 2677 */ 2678 2679 /* 2680 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2681 * Transcoder. 2682 */ 2683 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2684 2685 if (HAS_DP20(dev_priv)) 2686 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2687 2688 /* 2689 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2690 * Transport Select 2691 */ 2692 intel_ddi_config_transcoder_func(encoder, crtc_state); 2693 2694 /* 2695 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2696 * selected 2697 * 2698 * This will be handled by the intel_dp_start_link_train() farther 2699 * down this function. 2700 */ 2701 2702 /* 7.e Configure voltage swing and related IO settings */ 2703 encoder->set_signal_levels(encoder, crtc_state); 2704 2705 /* 2706 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2707 * the used lanes of the DDI. 2708 */ 2709 intel_ddi_power_up_lanes(encoder, crtc_state); 2710 2711 /* 2712 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2713 */ 2714 intel_ddi_mso_configure(crtc_state); 2715 2716 if (!is_mst) 2717 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2718 2719 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2720 if (!is_mst) 2721 intel_dp_sink_enable_decompression(state, 2722 to_intel_connector(conn_state->connector), 2723 crtc_state); 2724 /* 2725 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2726 * in the FEC_CONFIGURATION register to 1 before initiating link 2727 * training 2728 */ 2729 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2730 2731 intel_dp_check_frl_training(intel_dp); 2732 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2733 2734 /* 2735 * 7.i Follow DisplayPort specification training sequence (see notes for 2736 * failure handling) 2737 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2738 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2739 * (timeout after 800 us) 2740 */ 2741 intel_dp_start_link_train(state, intel_dp, crtc_state); 2742 2743 /* 7.k Set DP_TP_CTL link training to Normal */ 2744 if (!is_trans_port_sync_mode(crtc_state)) 2745 intel_dp_stop_link_train(intel_dp, crtc_state); 2746 2747 /* 7.l Configure and enable FEC if needed */ 2748 intel_ddi_enable_fec(encoder, crtc_state); 2749 2750 if (!is_mst) 2751 intel_dsc_dp_pps_write(encoder, crtc_state); 2752 } 2753 2754 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2755 struct intel_encoder *encoder, 2756 const struct intel_crtc_state *crtc_state, 2757 const struct drm_connector_state *conn_state) 2758 { 2759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2760 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2761 enum port port = encoder->port; 2762 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2763 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2764 2765 if (DISPLAY_VER(dev_priv) < 11) 2766 drm_WARN_ON(&dev_priv->drm, 2767 is_mst && (port == PORT_A || port == PORT_E)); 2768 else 2769 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2770 2771 intel_dp_set_link_params(intel_dp, 2772 crtc_state->port_clock, 2773 crtc_state->lane_count); 2774 2775 /* 2776 * We only configure what the register value will be here. Actual 2777 * enabling happens during link training farther down. 2778 */ 2779 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2780 2781 intel_pps_on(intel_dp); 2782 2783 intel_ddi_enable_clock(encoder, crtc_state); 2784 2785 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2786 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2787 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2788 dig_port->ddi_io_power_domain); 2789 } 2790 2791 icl_program_mg_dp_mode(dig_port, crtc_state); 2792 2793 if (has_buf_trans_select(dev_priv)) 2794 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2795 2796 encoder->set_signal_levels(encoder, crtc_state); 2797 2798 intel_ddi_power_up_lanes(encoder, crtc_state); 2799 2800 if (!is_mst) 2801 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2802 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2803 if (!is_mst) 2804 intel_dp_sink_enable_decompression(state, 2805 to_intel_connector(conn_state->connector), 2806 crtc_state); 2807 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2808 intel_dp_start_link_train(state, intel_dp, crtc_state); 2809 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2810 !is_trans_port_sync_mode(crtc_state)) 2811 intel_dp_stop_link_train(intel_dp, crtc_state); 2812 2813 intel_ddi_enable_fec(encoder, crtc_state); 2814 2815 if (!is_mst) { 2816 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2817 intel_dsc_dp_pps_write(encoder, crtc_state); 2818 } 2819 } 2820 2821 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2822 struct intel_encoder *encoder, 2823 const struct intel_crtc_state *crtc_state, 2824 const struct drm_connector_state *conn_state) 2825 { 2826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2827 2828 if (HAS_DP20(dev_priv)) 2829 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2830 crtc_state); 2831 2832 /* Panel replay has to be enabled in sink dpcd before link training. */ 2833 if (crtc_state->has_panel_replay) 2834 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2835 2836 if (DISPLAY_VER(dev_priv) >= 14) 2837 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2838 else if (DISPLAY_VER(dev_priv) >= 12) 2839 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2840 else 2841 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2842 2843 /* MST will call a setting of MSA after an allocating of Virtual Channel 2844 * from MST encoder pre_enable callback. 2845 */ 2846 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2847 intel_ddi_set_dp_msa(crtc_state, conn_state); 2848 } 2849 2850 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2851 struct intel_encoder *encoder, 2852 const struct intel_crtc_state *crtc_state, 2853 const struct drm_connector_state *conn_state) 2854 { 2855 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2856 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2857 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2858 2859 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2860 intel_ddi_enable_clock(encoder, crtc_state); 2861 2862 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2863 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2864 dig_port->ddi_io_power_domain); 2865 2866 icl_program_mg_dp_mode(dig_port, crtc_state); 2867 2868 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2869 2870 dig_port->set_infoframes(encoder, 2871 crtc_state->has_infoframe, 2872 crtc_state, conn_state); 2873 } 2874 2875 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2876 struct intel_encoder *encoder, 2877 const struct intel_crtc_state *crtc_state, 2878 const struct drm_connector_state *conn_state) 2879 { 2880 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2881 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2882 enum pipe pipe = crtc->pipe; 2883 2884 /* 2885 * When called from DP MST code: 2886 * - conn_state will be NULL 2887 * - encoder will be the main encoder (ie. mst->primary) 2888 * - the main connector associated with this port 2889 * won't be active or linked to a crtc 2890 * - crtc_state will be the state of the first stream to 2891 * be activated on this port, and it may not be the same 2892 * stream that will be deactivated last, but each stream 2893 * should have a state that is identical when it comes to 2894 * the DP link parameteres 2895 */ 2896 2897 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2898 2899 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2900 2901 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2902 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2903 conn_state); 2904 } else { 2905 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2906 2907 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2908 conn_state); 2909 2910 /* FIXME precompute everything properly */ 2911 /* FIXME how do we turn infoframes off again? */ 2912 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2913 dig_port->set_infoframes(encoder, 2914 crtc_state->has_infoframe, 2915 crtc_state, conn_state); 2916 } 2917 } 2918 2919 static void 2920 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2921 { 2922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2923 enum port port = encoder->port; 2924 i915_reg_t reg; 2925 u32 clr_bits, wait_bits; 2926 2927 if (DISPLAY_VER(dev_priv) >= 20) { 2928 reg = DDI_BUF_CTL(port); 2929 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2930 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2931 } else { 2932 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2933 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2934 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2935 } 2936 2937 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2938 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2939 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2940 port_name(port)); 2941 } 2942 2943 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2944 const struct intel_crtc_state *crtc_state) 2945 { 2946 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2947 enum port port = encoder->port; 2948 u32 val; 2949 2950 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2951 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2952 if (val & DDI_BUF_CTL_ENABLE) { 2953 val &= ~DDI_BUF_CTL_ENABLE; 2954 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2955 2956 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2957 mtl_wait_ddi_buf_idle(dev_priv, port); 2958 } 2959 2960 /* 3.d Disable D2D Link */ 2961 mtl_ddi_disable_d2d_link(encoder); 2962 2963 /* 3.e Disable DP_TP_CTL */ 2964 if (intel_crtc_has_dp_encoder(crtc_state)) { 2965 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2966 DP_TP_CTL_ENABLE, 0); 2967 } 2968 } 2969 2970 static void disable_ddi_buf(struct intel_encoder *encoder, 2971 const struct intel_crtc_state *crtc_state) 2972 { 2973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2974 enum port port = encoder->port; 2975 bool wait = false; 2976 u32 val; 2977 2978 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2979 if (val & DDI_BUF_CTL_ENABLE) { 2980 val &= ~DDI_BUF_CTL_ENABLE; 2981 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2982 wait = true; 2983 } 2984 2985 if (intel_crtc_has_dp_encoder(crtc_state)) 2986 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2987 DP_TP_CTL_ENABLE, 0); 2988 2989 intel_ddi_disable_fec(encoder, crtc_state); 2990 2991 if (wait) 2992 intel_wait_ddi_buf_idle(dev_priv, port); 2993 } 2994 2995 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2996 const struct intel_crtc_state *crtc_state) 2997 { 2998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2999 3000 if (DISPLAY_VER(dev_priv) >= 14) { 3001 mtl_disable_ddi_buf(encoder, crtc_state); 3002 3003 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3004 intel_ddi_disable_fec(encoder, crtc_state); 3005 } else { 3006 disable_ddi_buf(encoder, crtc_state); 3007 } 3008 3009 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3010 } 3011 3012 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3013 struct intel_encoder *encoder, 3014 const struct intel_crtc_state *old_crtc_state, 3015 const struct drm_connector_state *old_conn_state) 3016 { 3017 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3018 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3019 struct intel_dp *intel_dp = &dig_port->dp; 3020 intel_wakeref_t wakeref; 3021 bool is_mst = intel_crtc_has_type(old_crtc_state, 3022 INTEL_OUTPUT_DP_MST); 3023 3024 if (!is_mst) 3025 intel_dp_set_infoframes(encoder, false, 3026 old_crtc_state, old_conn_state); 3027 3028 /* 3029 * Power down sink before disabling the port, otherwise we end 3030 * up getting interrupts from the sink on detecting link loss. 3031 */ 3032 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3033 3034 if (DISPLAY_VER(dev_priv) >= 12) { 3035 if (is_mst) { 3036 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3037 3038 intel_de_rmw(dev_priv, 3039 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3040 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3041 0); 3042 } 3043 } else { 3044 if (!is_mst) 3045 intel_ddi_disable_transcoder_clock(old_crtc_state); 3046 } 3047 3048 intel_disable_ddi_buf(encoder, old_crtc_state); 3049 3050 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3051 3052 /* 3053 * From TGL spec: "If single stream or multi-stream master transcoder: 3054 * Configure Transcoder Clock select to direct no clock to the 3055 * transcoder" 3056 */ 3057 if (DISPLAY_VER(dev_priv) >= 12) 3058 intel_ddi_disable_transcoder_clock(old_crtc_state); 3059 3060 intel_pps_vdd_on(intel_dp); 3061 intel_pps_off(intel_dp); 3062 3063 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3064 3065 if (wakeref) 3066 intel_display_power_put(dev_priv, 3067 dig_port->ddi_io_power_domain, 3068 wakeref); 3069 3070 intel_ddi_disable_clock(encoder); 3071 3072 /* De-select Thunderbolt */ 3073 if (DISPLAY_VER(dev_priv) >= 14) 3074 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3075 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3076 } 3077 3078 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3079 struct intel_encoder *encoder, 3080 const struct intel_crtc_state *old_crtc_state, 3081 const struct drm_connector_state *old_conn_state) 3082 { 3083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3084 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3085 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3086 intel_wakeref_t wakeref; 3087 3088 dig_port->set_infoframes(encoder, false, 3089 old_crtc_state, old_conn_state); 3090 3091 if (DISPLAY_VER(dev_priv) < 12) 3092 intel_ddi_disable_transcoder_clock(old_crtc_state); 3093 3094 intel_disable_ddi_buf(encoder, old_crtc_state); 3095 3096 if (DISPLAY_VER(dev_priv) >= 12) 3097 intel_ddi_disable_transcoder_clock(old_crtc_state); 3098 3099 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3100 if (wakeref) 3101 intel_display_power_put(dev_priv, 3102 dig_port->ddi_io_power_domain, 3103 wakeref); 3104 3105 intel_ddi_disable_clock(encoder); 3106 3107 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3108 } 3109 3110 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3111 struct intel_encoder *encoder, 3112 const struct intel_crtc_state *old_crtc_state, 3113 const struct drm_connector_state *old_conn_state) 3114 { 3115 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3116 struct intel_crtc *pipe_crtc; 3117 3118 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3119 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3120 const struct intel_crtc_state *old_pipe_crtc_state = 3121 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3122 3123 intel_crtc_vblank_off(old_pipe_crtc_state); 3124 } 3125 3126 intel_disable_transcoder(old_crtc_state); 3127 3128 intel_ddi_disable_transcoder_func(old_crtc_state); 3129 3130 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3131 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3132 const struct intel_crtc_state *old_pipe_crtc_state = 3133 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3134 3135 intel_dsc_disable(old_pipe_crtc_state); 3136 3137 if (DISPLAY_VER(dev_priv) >= 9) 3138 skl_scaler_disable(old_pipe_crtc_state); 3139 else 3140 ilk_pfit_disable(old_pipe_crtc_state); 3141 } 3142 } 3143 3144 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3145 struct intel_encoder *encoder, 3146 const struct intel_crtc_state *old_crtc_state, 3147 const struct drm_connector_state *old_conn_state) 3148 { 3149 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3150 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3151 old_conn_state); 3152 3153 /* 3154 * When called from DP MST code: 3155 * - old_conn_state will be NULL 3156 * - encoder will be the main encoder (ie. mst->primary) 3157 * - the main connector associated with this port 3158 * won't be active or linked to a crtc 3159 * - old_crtc_state will be the state of the last stream to 3160 * be deactivated on this port, and it may not be the same 3161 * stream that was activated last, but each stream 3162 * should have a state that is identical when it comes to 3163 * the DP link parameteres 3164 */ 3165 3166 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3167 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3168 old_conn_state); 3169 else 3170 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3171 old_conn_state); 3172 } 3173 3174 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3175 struct intel_encoder *encoder, 3176 const struct intel_crtc_state *old_crtc_state, 3177 const struct drm_connector_state *old_conn_state) 3178 { 3179 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3180 3181 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3182 3183 if (intel_encoder_is_tc(encoder)) 3184 intel_tc_port_put_link(dig_port); 3185 } 3186 3187 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3188 struct intel_encoder *encoder, 3189 const struct intel_crtc_state *crtc_state) 3190 { 3191 const struct drm_connector_state *conn_state; 3192 struct drm_connector *conn; 3193 int i; 3194 3195 if (!crtc_state->sync_mode_slaves_mask) 3196 return; 3197 3198 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3199 struct intel_encoder *slave_encoder = 3200 to_intel_encoder(conn_state->best_encoder); 3201 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3202 const struct intel_crtc_state *slave_crtc_state; 3203 3204 if (!slave_crtc) 3205 continue; 3206 3207 slave_crtc_state = 3208 intel_atomic_get_new_crtc_state(state, slave_crtc); 3209 3210 if (slave_crtc_state->master_transcoder != 3211 crtc_state->cpu_transcoder) 3212 continue; 3213 3214 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3215 slave_crtc_state); 3216 } 3217 3218 usleep_range(200, 400); 3219 3220 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3221 crtc_state); 3222 } 3223 3224 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3225 struct intel_encoder *encoder, 3226 const struct intel_crtc_state *crtc_state, 3227 const struct drm_connector_state *conn_state) 3228 { 3229 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3230 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3231 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3232 enum port port = encoder->port; 3233 3234 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3235 intel_dp_stop_link_train(intel_dp, crtc_state); 3236 3237 drm_connector_update_privacy_screen(conn_state); 3238 intel_edp_backlight_on(crtc_state, conn_state); 3239 3240 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3241 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3242 3243 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3244 } 3245 3246 /* FIXME bad home for this function */ 3247 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3248 enum transcoder cpu_transcoder) 3249 { 3250 return DISPLAY_VER(i915) >= 14 ? 3251 MTL_CHICKEN_TRANS(cpu_transcoder) : 3252 CHICKEN_TRANS(cpu_transcoder); 3253 } 3254 3255 static i915_reg_t 3256 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3257 enum port port) 3258 { 3259 static const enum transcoder trans[] = { 3260 [PORT_A] = TRANSCODER_EDP, 3261 [PORT_B] = TRANSCODER_A, 3262 [PORT_C] = TRANSCODER_B, 3263 [PORT_D] = TRANSCODER_C, 3264 [PORT_E] = TRANSCODER_A, 3265 }; 3266 3267 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3268 3269 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3270 port = PORT_A; 3271 3272 return CHICKEN_TRANS(trans[port]); 3273 } 3274 3275 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3276 struct intel_encoder *encoder, 3277 const struct intel_crtc_state *crtc_state, 3278 const struct drm_connector_state *conn_state) 3279 { 3280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3281 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3282 struct drm_connector *connector = conn_state->connector; 3283 enum port port = encoder->port; 3284 u32 buf_ctl; 3285 3286 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3287 crtc_state->hdmi_high_tmds_clock_ratio, 3288 crtc_state->hdmi_scrambling)) 3289 drm_dbg_kms(&dev_priv->drm, 3290 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3291 connector->base.id, connector->name); 3292 3293 if (has_buf_trans_select(dev_priv)) 3294 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3295 3296 /* e. Enable D2D Link for C10/C20 Phy */ 3297 if (DISPLAY_VER(dev_priv) >= 14) 3298 mtl_ddi_enable_d2d(encoder); 3299 3300 encoder->set_signal_levels(encoder, crtc_state); 3301 3302 /* Display WA #1143: skl,kbl,cfl */ 3303 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3304 /* 3305 * For some reason these chicken bits have been 3306 * stuffed into a transcoder register, event though 3307 * the bits affect a specific DDI port rather than 3308 * a specific transcoder. 3309 */ 3310 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3311 u32 val; 3312 3313 val = intel_de_read(dev_priv, reg); 3314 3315 if (port == PORT_E) 3316 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3317 DDIE_TRAINING_OVERRIDE_VALUE; 3318 else 3319 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3320 DDI_TRAINING_OVERRIDE_VALUE; 3321 3322 intel_de_write(dev_priv, reg, val); 3323 intel_de_posting_read(dev_priv, reg); 3324 3325 udelay(1); 3326 3327 if (port == PORT_E) 3328 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3329 DDIE_TRAINING_OVERRIDE_VALUE); 3330 else 3331 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3332 DDI_TRAINING_OVERRIDE_VALUE); 3333 3334 intel_de_write(dev_priv, reg, val); 3335 } 3336 3337 intel_ddi_power_up_lanes(encoder, crtc_state); 3338 3339 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3340 * are ignored so nothing special needs to be done besides 3341 * enabling the port. 3342 * 3343 * On ADL_P the PHY link rate and lane count must be programmed but 3344 * these are both 0 for HDMI. 3345 * 3346 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3347 * is filled with lane count, already set in the crtc_state. 3348 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3349 */ 3350 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3351 if (DISPLAY_VER(dev_priv) >= 14) { 3352 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3353 u32 port_buf = 0; 3354 3355 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3356 3357 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3358 port_buf |= XELPDP_PORT_REVERSAL; 3359 3360 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3361 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3362 3363 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3364 3365 if (DISPLAY_VER(dev_priv) >= 20) 3366 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3367 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3368 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3369 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3370 } 3371 3372 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3373 3374 intel_wait_ddi_buf_active(encoder); 3375 } 3376 3377 static void intel_enable_ddi(struct intel_atomic_state *state, 3378 struct intel_encoder *encoder, 3379 const struct intel_crtc_state *crtc_state, 3380 const struct drm_connector_state *conn_state) 3381 { 3382 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3383 struct intel_crtc *pipe_crtc; 3384 3385 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3386 3387 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3388 intel_audio_sdp_split_update(crtc_state); 3389 3390 intel_enable_transcoder(crtc_state); 3391 3392 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3393 3394 for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, 3395 intel_crtc_joined_pipe_mask(crtc_state)) { 3396 const struct intel_crtc_state *pipe_crtc_state = 3397 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3398 3399 intel_crtc_vblank_on(pipe_crtc_state); 3400 } 3401 3402 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3403 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3404 else 3405 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3406 3407 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3408 3409 } 3410 3411 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3412 struct intel_encoder *encoder, 3413 const struct intel_crtc_state *old_crtc_state, 3414 const struct drm_connector_state *old_conn_state) 3415 { 3416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3417 struct intel_connector *connector = 3418 to_intel_connector(old_conn_state->connector); 3419 3420 intel_dp->link_trained = false; 3421 3422 intel_psr_disable(intel_dp, old_crtc_state); 3423 intel_edp_backlight_off(old_conn_state); 3424 /* Disable the decompression in DP Sink */ 3425 intel_dp_sink_disable_decompression(state, 3426 connector, old_crtc_state); 3427 /* Disable Ignore_MSA bit in DP Sink */ 3428 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3429 false); 3430 } 3431 3432 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3433 struct intel_encoder *encoder, 3434 const struct intel_crtc_state *old_crtc_state, 3435 const struct drm_connector_state *old_conn_state) 3436 { 3437 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3438 struct drm_connector *connector = old_conn_state->connector; 3439 3440 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3441 false, false)) 3442 drm_dbg_kms(&i915->drm, 3443 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3444 connector->base.id, connector->name); 3445 } 3446 3447 static void intel_disable_ddi(struct intel_atomic_state *state, 3448 struct intel_encoder *encoder, 3449 const struct intel_crtc_state *old_crtc_state, 3450 const struct drm_connector_state *old_conn_state) 3451 { 3452 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3453 3454 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3455 3456 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3457 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3458 old_conn_state); 3459 else 3460 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3461 old_conn_state); 3462 } 3463 3464 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3465 struct intel_encoder *encoder, 3466 const struct intel_crtc_state *crtc_state, 3467 const struct drm_connector_state *conn_state) 3468 { 3469 intel_ddi_set_dp_msa(crtc_state, conn_state); 3470 3471 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3472 3473 intel_backlight_update(state, encoder, crtc_state, conn_state); 3474 drm_connector_update_privacy_screen(conn_state); 3475 } 3476 3477 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3478 struct intel_encoder *encoder, 3479 const struct intel_crtc_state *crtc_state, 3480 const struct drm_connector_state *conn_state) 3481 { 3482 3483 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3484 !intel_encoder_is_mst(encoder)) 3485 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3486 conn_state); 3487 3488 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3489 } 3490 3491 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3492 struct intel_encoder *encoder, 3493 struct intel_crtc *crtc) 3494 { 3495 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3496 const struct intel_crtc_state *crtc_state = 3497 intel_atomic_get_new_crtc_state(state, crtc); 3498 struct intel_crtc *pipe_crtc; 3499 3500 /* FIXME: Add MTL pll_mgr */ 3501 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3502 return; 3503 3504 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3505 intel_crtc_joined_pipe_mask(crtc_state)) 3506 intel_update_active_dpll(state, pipe_crtc, encoder); 3507 } 3508 3509 static void 3510 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3511 struct intel_encoder *encoder, 3512 const struct intel_crtc_state *crtc_state, 3513 const struct drm_connector_state *conn_state) 3514 { 3515 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3516 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3517 bool is_tc_port = intel_encoder_is_tc(encoder); 3518 3519 if (is_tc_port) { 3520 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3521 3522 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3523 intel_ddi_update_active_dpll(state, encoder, crtc); 3524 } 3525 3526 main_link_aux_power_domain_get(dig_port, crtc_state); 3527 3528 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3529 /* 3530 * Program the lane count for static/dynamic connections on 3531 * Type-C ports. Skip this step for TBT. 3532 */ 3533 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3534 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3535 bxt_dpio_phy_set_lane_optim_mask(encoder, 3536 crtc_state->lane_lat_optim_mask); 3537 } 3538 3539 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3540 { 3541 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3542 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3543 int ln; 3544 3545 for (ln = 0; ln < 2; ln++) 3546 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3547 } 3548 3549 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3550 const struct intel_crtc_state *crtc_state) 3551 { 3552 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3553 struct intel_encoder *encoder = &dig_port->base; 3554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3555 enum port port = encoder->port; 3556 u32 dp_tp_ctl; 3557 3558 /* 3559 * TODO: To train with only a different voltage swing entry is not 3560 * necessary disable and enable port 3561 */ 3562 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3563 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3564 mtl_disable_ddi_buf(encoder, crtc_state); 3565 3566 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3567 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3568 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3569 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3570 } else { 3571 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3572 if (crtc_state->enhanced_framing) 3573 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3574 } 3575 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3576 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3577 3578 /* 6.f Enable D2D Link */ 3579 mtl_ddi_enable_d2d(encoder); 3580 3581 /* 6.g Configure voltage swing and related IO settings */ 3582 encoder->set_signal_levels(encoder, crtc_state); 3583 3584 /* 6.h Configure PORT_BUF_CTL1 */ 3585 mtl_port_buf_ctl_program(encoder, crtc_state); 3586 3587 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3588 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3589 if (DISPLAY_VER(dev_priv) >= 20) 3590 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3591 3592 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3593 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3594 3595 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3596 intel_wait_ddi_buf_active(encoder); 3597 } 3598 3599 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3600 const struct intel_crtc_state *crtc_state) 3601 { 3602 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3603 struct intel_encoder *encoder = &dig_port->base; 3604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3605 enum port port = encoder->port; 3606 u32 dp_tp_ctl, ddi_buf_ctl; 3607 bool wait = false; 3608 3609 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3610 3611 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3612 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3613 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3614 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3615 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3616 wait = true; 3617 } 3618 3619 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3620 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3621 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3622 3623 if (wait) 3624 intel_wait_ddi_buf_idle(dev_priv, port); 3625 } 3626 3627 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3628 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3629 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3630 } else { 3631 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3632 if (crtc_state->enhanced_framing) 3633 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3634 } 3635 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3636 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3637 3638 if (IS_ALDERLAKE_P(dev_priv) && 3639 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3640 adlp_tbt_to_dp_alt_switch_wa(encoder); 3641 3642 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3643 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3644 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3645 3646 intel_wait_ddi_buf_active(encoder); 3647 } 3648 3649 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3650 const struct intel_crtc_state *crtc_state, 3651 u8 dp_train_pat) 3652 { 3653 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3655 u32 temp; 3656 3657 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3658 3659 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3660 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3661 case DP_TRAINING_PATTERN_DISABLE: 3662 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3663 break; 3664 case DP_TRAINING_PATTERN_1: 3665 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3666 break; 3667 case DP_TRAINING_PATTERN_2: 3668 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3669 break; 3670 case DP_TRAINING_PATTERN_3: 3671 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3672 break; 3673 case DP_TRAINING_PATTERN_4: 3674 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3675 break; 3676 } 3677 3678 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3679 } 3680 3681 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3682 const struct intel_crtc_state *crtc_state) 3683 { 3684 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3686 enum port port = encoder->port; 3687 3688 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3689 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3690 3691 /* 3692 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3693 * reason we need to set idle transmission mode is to work around a HW 3694 * issue where we enable the pipe while not in idle link-training mode. 3695 * In this case there is requirement to wait for a minimum number of 3696 * idle patterns to be sent. 3697 */ 3698 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3699 return; 3700 3701 if (intel_de_wait_for_set(dev_priv, 3702 dp_tp_status_reg(encoder, crtc_state), 3703 DP_TP_STATUS_IDLE_DONE, 2)) 3704 drm_err(&dev_priv->drm, 3705 "Timed out waiting for DP idle patterns\n"); 3706 } 3707 3708 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3709 enum transcoder cpu_transcoder) 3710 { 3711 if (cpu_transcoder == TRANSCODER_EDP) 3712 return false; 3713 3714 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3715 return false; 3716 3717 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3718 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3719 } 3720 3721 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3722 { 3723 if (crtc_state->port_clock > 594000) 3724 return 2; 3725 else 3726 return 0; 3727 } 3728 3729 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3730 { 3731 if (crtc_state->port_clock > 594000) 3732 return 3; 3733 else 3734 return 0; 3735 } 3736 3737 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3738 { 3739 if (crtc_state->port_clock > 594000) 3740 return 1; 3741 else 3742 return 0; 3743 } 3744 3745 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3746 { 3747 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3748 3749 if (DISPLAY_VER(dev_priv) >= 14) 3750 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3751 else if (DISPLAY_VER(dev_priv) >= 12) 3752 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3753 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3754 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3755 else if (DISPLAY_VER(dev_priv) >= 11) 3756 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3757 } 3758 3759 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3760 enum transcoder cpu_transcoder) 3761 { 3762 u32 master_select; 3763 3764 if (DISPLAY_VER(dev_priv) >= 11) { 3765 u32 ctl2 = intel_de_read(dev_priv, 3766 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3767 3768 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3769 return INVALID_TRANSCODER; 3770 3771 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3772 } else { 3773 u32 ctl = intel_de_read(dev_priv, 3774 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3775 3776 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3777 return INVALID_TRANSCODER; 3778 3779 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3780 } 3781 3782 if (master_select == 0) 3783 return TRANSCODER_EDP; 3784 else 3785 return master_select - 1; 3786 } 3787 3788 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3789 { 3790 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3791 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3792 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3793 enum transcoder cpu_transcoder; 3794 3795 crtc_state->master_transcoder = 3796 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3797 3798 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3799 enum intel_display_power_domain power_domain; 3800 intel_wakeref_t trans_wakeref; 3801 3802 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3803 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3804 power_domain); 3805 3806 if (!trans_wakeref) 3807 continue; 3808 3809 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3810 crtc_state->cpu_transcoder) 3811 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3812 3813 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3814 } 3815 3816 drm_WARN_ON(&dev_priv->drm, 3817 crtc_state->master_transcoder != INVALID_TRANSCODER && 3818 crtc_state->sync_mode_slaves_mask); 3819 } 3820 3821 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3822 struct intel_crtc_state *pipe_config) 3823 { 3824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3825 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3826 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3827 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3828 u32 temp, flags = 0; 3829 3830 temp = intel_de_read(dev_priv, 3831 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3832 if (temp & TRANS_DDI_PHSYNC) 3833 flags |= DRM_MODE_FLAG_PHSYNC; 3834 else 3835 flags |= DRM_MODE_FLAG_NHSYNC; 3836 if (temp & TRANS_DDI_PVSYNC) 3837 flags |= DRM_MODE_FLAG_PVSYNC; 3838 else 3839 flags |= DRM_MODE_FLAG_NVSYNC; 3840 3841 pipe_config->hw.adjusted_mode.flags |= flags; 3842 3843 switch (temp & TRANS_DDI_BPC_MASK) { 3844 case TRANS_DDI_BPC_6: 3845 pipe_config->pipe_bpp = 18; 3846 break; 3847 case TRANS_DDI_BPC_8: 3848 pipe_config->pipe_bpp = 24; 3849 break; 3850 case TRANS_DDI_BPC_10: 3851 pipe_config->pipe_bpp = 30; 3852 break; 3853 case TRANS_DDI_BPC_12: 3854 pipe_config->pipe_bpp = 36; 3855 break; 3856 default: 3857 break; 3858 } 3859 3860 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3861 case TRANS_DDI_MODE_SELECT_HDMI: 3862 pipe_config->has_hdmi_sink = true; 3863 3864 pipe_config->infoframes.enable |= 3865 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3866 3867 if (pipe_config->infoframes.enable) 3868 pipe_config->has_infoframe = true; 3869 3870 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3871 pipe_config->hdmi_scrambling = true; 3872 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3873 pipe_config->hdmi_high_tmds_clock_ratio = true; 3874 fallthrough; 3875 case TRANS_DDI_MODE_SELECT_DVI: 3876 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3877 if (DISPLAY_VER(dev_priv) >= 14) 3878 pipe_config->lane_count = 3879 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3880 else 3881 pipe_config->lane_count = 4; 3882 break; 3883 case TRANS_DDI_MODE_SELECT_DP_SST: 3884 if (encoder->type == INTEL_OUTPUT_EDP) 3885 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3886 else 3887 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3888 pipe_config->lane_count = 3889 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3890 3891 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3892 &pipe_config->dp_m_n); 3893 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3894 &pipe_config->dp_m2_n2); 3895 3896 pipe_config->enhanced_framing = 3897 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3898 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3899 3900 if (DISPLAY_VER(dev_priv) >= 11) 3901 pipe_config->fec_enable = 3902 intel_de_read(dev_priv, 3903 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3904 3905 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3906 pipe_config->infoframes.enable |= 3907 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3908 else 3909 pipe_config->infoframes.enable |= 3910 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3911 break; 3912 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3913 if (!HAS_DP20(dev_priv)) { 3914 /* FDI */ 3915 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3916 pipe_config->enhanced_framing = 3917 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3918 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3919 break; 3920 } 3921 fallthrough; /* 128b/132b */ 3922 case TRANS_DDI_MODE_SELECT_DP_MST: 3923 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3924 pipe_config->lane_count = 3925 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3926 3927 if (DISPLAY_VER(dev_priv) >= 12) 3928 pipe_config->mst_master_transcoder = 3929 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3930 3931 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3932 &pipe_config->dp_m_n); 3933 3934 if (DISPLAY_VER(dev_priv) >= 11) 3935 pipe_config->fec_enable = 3936 intel_de_read(dev_priv, 3937 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3938 3939 pipe_config->infoframes.enable |= 3940 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3941 break; 3942 default: 3943 break; 3944 } 3945 } 3946 3947 static void intel_ddi_get_config(struct intel_encoder *encoder, 3948 struct intel_crtc_state *pipe_config) 3949 { 3950 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3951 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3952 3953 /* XXX: DSI transcoder paranoia */ 3954 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3955 return; 3956 3957 intel_ddi_read_func_ctl(encoder, pipe_config); 3958 3959 intel_ddi_mso_get_config(encoder, pipe_config); 3960 3961 pipe_config->has_audio = 3962 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3963 3964 if (encoder->type == INTEL_OUTPUT_EDP) 3965 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3966 3967 ddi_dotclock_get(pipe_config); 3968 3969 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3970 pipe_config->lane_lat_optim_mask = 3971 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 3972 3973 intel_ddi_compute_min_voltage_level(pipe_config); 3974 3975 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3976 3977 intel_read_infoframe(encoder, pipe_config, 3978 HDMI_INFOFRAME_TYPE_AVI, 3979 &pipe_config->infoframes.avi); 3980 intel_read_infoframe(encoder, pipe_config, 3981 HDMI_INFOFRAME_TYPE_SPD, 3982 &pipe_config->infoframes.spd); 3983 intel_read_infoframe(encoder, pipe_config, 3984 HDMI_INFOFRAME_TYPE_VENDOR, 3985 &pipe_config->infoframes.hdmi); 3986 intel_read_infoframe(encoder, pipe_config, 3987 HDMI_INFOFRAME_TYPE_DRM, 3988 &pipe_config->infoframes.drm); 3989 3990 if (DISPLAY_VER(dev_priv) >= 8) 3991 bdw_get_trans_port_sync_config(pipe_config); 3992 3993 intel_psr_get_config(encoder, pipe_config); 3994 3995 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3996 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3997 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 3998 3999 intel_audio_codec_get_config(encoder, pipe_config); 4000 } 4001 4002 void intel_ddi_get_clock(struct intel_encoder *encoder, 4003 struct intel_crtc_state *crtc_state, 4004 struct intel_shared_dpll *pll) 4005 { 4006 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4007 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4008 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4009 bool pll_active; 4010 4011 if (drm_WARN_ON(&i915->drm, !pll)) 4012 return; 4013 4014 port_dpll->pll = pll; 4015 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4016 drm_WARN_ON(&i915->drm, !pll_active); 4017 4018 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4019 4020 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4021 &crtc_state->dpll_hw_state); 4022 } 4023 4024 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4025 struct intel_crtc_state *crtc_state) 4026 { 4027 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4028 4029 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 4030 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4031 } else { 4032 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4033 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4034 } 4035 4036 intel_ddi_get_config(encoder, crtc_state); 4037 } 4038 4039 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4040 struct intel_crtc_state *crtc_state) 4041 { 4042 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4043 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4044 4045 intel_ddi_get_config(encoder, crtc_state); 4046 } 4047 4048 static void adls_ddi_get_config(struct intel_encoder *encoder, 4049 struct intel_crtc_state *crtc_state) 4050 { 4051 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4052 intel_ddi_get_config(encoder, crtc_state); 4053 } 4054 4055 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4056 struct intel_crtc_state *crtc_state) 4057 { 4058 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4059 intel_ddi_get_config(encoder, crtc_state); 4060 } 4061 4062 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4063 struct intel_crtc_state *crtc_state) 4064 { 4065 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4066 intel_ddi_get_config(encoder, crtc_state); 4067 } 4068 4069 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4070 struct intel_crtc_state *crtc_state) 4071 { 4072 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4073 intel_ddi_get_config(encoder, crtc_state); 4074 } 4075 4076 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4077 { 4078 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4079 } 4080 4081 static enum icl_port_dpll_id 4082 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4083 const struct intel_crtc_state *crtc_state) 4084 { 4085 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4086 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4087 4088 if (drm_WARN_ON(&i915->drm, !pll)) 4089 return ICL_PORT_DPLL_DEFAULT; 4090 4091 if (icl_ddi_tc_pll_is_tbt(pll)) 4092 return ICL_PORT_DPLL_DEFAULT; 4093 else 4094 return ICL_PORT_DPLL_MG_PHY; 4095 } 4096 4097 enum icl_port_dpll_id 4098 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4099 const struct intel_crtc_state *crtc_state) 4100 { 4101 if (!encoder->port_pll_type) 4102 return ICL_PORT_DPLL_DEFAULT; 4103 4104 return encoder->port_pll_type(encoder, crtc_state); 4105 } 4106 4107 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4108 struct intel_crtc_state *crtc_state, 4109 struct intel_shared_dpll *pll) 4110 { 4111 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4112 enum icl_port_dpll_id port_dpll_id; 4113 struct icl_port_dpll *port_dpll; 4114 bool pll_active; 4115 4116 if (drm_WARN_ON(&i915->drm, !pll)) 4117 return; 4118 4119 if (icl_ddi_tc_pll_is_tbt(pll)) 4120 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4121 else 4122 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4123 4124 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4125 4126 port_dpll->pll = pll; 4127 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4128 drm_WARN_ON(&i915->drm, !pll_active); 4129 4130 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4131 4132 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4133 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4134 else 4135 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4136 &crtc_state->dpll_hw_state); 4137 } 4138 4139 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4140 struct intel_crtc_state *crtc_state) 4141 { 4142 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4143 intel_ddi_get_config(encoder, crtc_state); 4144 } 4145 4146 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4147 struct intel_crtc_state *crtc_state) 4148 { 4149 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4150 intel_ddi_get_config(encoder, crtc_state); 4151 } 4152 4153 static void skl_ddi_get_config(struct intel_encoder *encoder, 4154 struct intel_crtc_state *crtc_state) 4155 { 4156 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4157 intel_ddi_get_config(encoder, crtc_state); 4158 } 4159 4160 void hsw_ddi_get_config(struct intel_encoder *encoder, 4161 struct intel_crtc_state *crtc_state) 4162 { 4163 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4164 intel_ddi_get_config(encoder, crtc_state); 4165 } 4166 4167 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4168 const struct intel_crtc_state *crtc_state) 4169 { 4170 if (intel_encoder_is_tc(encoder)) 4171 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4172 crtc_state); 4173 4174 if (intel_encoder_is_dp(encoder)) 4175 intel_dp_sync_state(encoder, crtc_state); 4176 } 4177 4178 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4179 struct intel_crtc_state *crtc_state) 4180 { 4181 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4182 bool fastset = true; 4183 4184 if (intel_encoder_is_tc(encoder)) { 4185 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4186 encoder->base.base.id, encoder->base.name); 4187 crtc_state->uapi.mode_changed = true; 4188 fastset = false; 4189 } 4190 4191 if (intel_crtc_has_dp_encoder(crtc_state) && 4192 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4193 fastset = false; 4194 4195 return fastset; 4196 } 4197 4198 static enum intel_output_type 4199 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4200 struct intel_crtc_state *crtc_state, 4201 struct drm_connector_state *conn_state) 4202 { 4203 switch (conn_state->connector->connector_type) { 4204 case DRM_MODE_CONNECTOR_HDMIA: 4205 return INTEL_OUTPUT_HDMI; 4206 case DRM_MODE_CONNECTOR_eDP: 4207 return INTEL_OUTPUT_EDP; 4208 case DRM_MODE_CONNECTOR_DisplayPort: 4209 return INTEL_OUTPUT_DP; 4210 default: 4211 MISSING_CASE(conn_state->connector->connector_type); 4212 return INTEL_OUTPUT_UNUSED; 4213 } 4214 } 4215 4216 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4217 struct intel_crtc_state *pipe_config, 4218 struct drm_connector_state *conn_state) 4219 { 4220 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4222 enum port port = encoder->port; 4223 int ret; 4224 4225 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4226 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4227 4228 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4229 pipe_config->has_hdmi_sink = 4230 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4231 4232 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4233 } else { 4234 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4235 } 4236 4237 if (ret) 4238 return ret; 4239 4240 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4241 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4242 pipe_config->pch_pfit.force_thru = 4243 pipe_config->pch_pfit.enabled || 4244 pipe_config->crc_enabled; 4245 4246 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4247 pipe_config->lane_lat_optim_mask = 4248 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4249 4250 intel_ddi_compute_min_voltage_level(pipe_config); 4251 4252 return 0; 4253 } 4254 4255 static bool mode_equal(const struct drm_display_mode *mode1, 4256 const struct drm_display_mode *mode2) 4257 { 4258 return drm_mode_match(mode1, mode2, 4259 DRM_MODE_MATCH_TIMINGS | 4260 DRM_MODE_MATCH_FLAGS | 4261 DRM_MODE_MATCH_3D_FLAGS) && 4262 mode1->clock == mode2->clock; /* we want an exact match */ 4263 } 4264 4265 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4266 const struct intel_link_m_n *m_n_2) 4267 { 4268 return m_n_1->tu == m_n_2->tu && 4269 m_n_1->data_m == m_n_2->data_m && 4270 m_n_1->data_n == m_n_2->data_n && 4271 m_n_1->link_m == m_n_2->link_m && 4272 m_n_1->link_n == m_n_2->link_n; 4273 } 4274 4275 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4276 const struct intel_crtc_state *crtc_state2) 4277 { 4278 /* 4279 * FIXME the modeset sequence is currently wrong and 4280 * can't deal with joiner + port sync at the same time. 4281 */ 4282 return crtc_state1->hw.active && crtc_state2->hw.active && 4283 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4284 crtc_state1->output_types == crtc_state2->output_types && 4285 crtc_state1->output_format == crtc_state2->output_format && 4286 crtc_state1->lane_count == crtc_state2->lane_count && 4287 crtc_state1->port_clock == crtc_state2->port_clock && 4288 mode_equal(&crtc_state1->hw.adjusted_mode, 4289 &crtc_state2->hw.adjusted_mode) && 4290 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4291 } 4292 4293 static u8 4294 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4295 int tile_group_id) 4296 { 4297 struct drm_connector *connector; 4298 const struct drm_connector_state *conn_state; 4299 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4300 struct intel_atomic_state *state = 4301 to_intel_atomic_state(ref_crtc_state->uapi.state); 4302 u8 transcoders = 0; 4303 int i; 4304 4305 /* 4306 * We don't enable port sync on BDW due to missing w/as and 4307 * due to not having adjusted the modeset sequence appropriately. 4308 */ 4309 if (DISPLAY_VER(dev_priv) < 9) 4310 return 0; 4311 4312 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4313 return 0; 4314 4315 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4316 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4317 const struct intel_crtc_state *crtc_state; 4318 4319 if (!crtc) 4320 continue; 4321 4322 if (!connector->has_tile || 4323 connector->tile_group->id != 4324 tile_group_id) 4325 continue; 4326 crtc_state = intel_atomic_get_new_crtc_state(state, 4327 crtc); 4328 if (!crtcs_port_sync_compatible(ref_crtc_state, 4329 crtc_state)) 4330 continue; 4331 transcoders |= BIT(crtc_state->cpu_transcoder); 4332 } 4333 4334 return transcoders; 4335 } 4336 4337 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4338 struct intel_crtc_state *crtc_state, 4339 struct drm_connector_state *conn_state) 4340 { 4341 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4342 struct drm_connector *connector = conn_state->connector; 4343 u8 port_sync_transcoders = 0; 4344 4345 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4346 encoder->base.base.id, encoder->base.name, 4347 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4348 4349 if (connector->has_tile) 4350 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4351 connector->tile_group->id); 4352 4353 /* 4354 * EDP Transcoders cannot be ensalved 4355 * make them a master always when present 4356 */ 4357 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4358 crtc_state->master_transcoder = TRANSCODER_EDP; 4359 else 4360 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4361 4362 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4363 crtc_state->master_transcoder = INVALID_TRANSCODER; 4364 crtc_state->sync_mode_slaves_mask = 4365 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4366 } 4367 4368 return 0; 4369 } 4370 4371 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4372 { 4373 struct drm_i915_private *i915 = to_i915(encoder->dev); 4374 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4375 4376 intel_dp_encoder_flush_work(encoder); 4377 if (intel_encoder_is_tc(&dig_port->base)) 4378 intel_tc_port_cleanup(dig_port); 4379 intel_display_power_flush_work(i915); 4380 4381 drm_encoder_cleanup(encoder); 4382 kfree(dig_port->hdcp_port_data.streams); 4383 kfree(dig_port); 4384 } 4385 4386 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4387 { 4388 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4389 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4390 4391 intel_dp->reset_link_params = true; 4392 4393 intel_pps_encoder_reset(intel_dp); 4394 4395 if (intel_encoder_is_tc(&dig_port->base)) 4396 intel_tc_port_init_mode(dig_port); 4397 } 4398 4399 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4400 { 4401 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4402 4403 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4404 4405 return 0; 4406 } 4407 4408 static const struct drm_encoder_funcs intel_ddi_funcs = { 4409 .reset = intel_ddi_encoder_reset, 4410 .destroy = intel_ddi_encoder_destroy, 4411 .late_register = intel_ddi_encoder_late_register, 4412 }; 4413 4414 static struct intel_connector * 4415 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4416 { 4417 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4418 struct intel_connector *connector; 4419 enum port port = dig_port->base.port; 4420 4421 connector = intel_connector_alloc(); 4422 if (!connector) 4423 return NULL; 4424 4425 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4426 if (DISPLAY_VER(i915) >= 14) 4427 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4428 else 4429 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4430 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4431 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4432 4433 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4434 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4435 4436 if (!intel_dp_init_connector(dig_port, connector)) { 4437 kfree(connector); 4438 return NULL; 4439 } 4440 4441 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4442 struct drm_device *dev = dig_port->base.base.dev; 4443 struct drm_privacy_screen *privacy_screen; 4444 4445 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4446 if (!IS_ERR(privacy_screen)) { 4447 drm_connector_attach_privacy_screen_provider(&connector->base, 4448 privacy_screen); 4449 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4450 drm_warn(dev, "Error getting privacy-screen\n"); 4451 } 4452 } 4453 4454 return connector; 4455 } 4456 4457 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4458 struct drm_modeset_acquire_ctx *ctx) 4459 { 4460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4461 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4462 struct intel_connector *connector = hdmi->attached_connector; 4463 struct i2c_adapter *ddc = connector->base.ddc; 4464 struct drm_connector_state *conn_state; 4465 struct intel_crtc_state *crtc_state; 4466 struct intel_crtc *crtc; 4467 u8 config; 4468 int ret; 4469 4470 if (connector->base.status != connector_status_connected) 4471 return 0; 4472 4473 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4474 ctx); 4475 if (ret) 4476 return ret; 4477 4478 conn_state = connector->base.state; 4479 4480 crtc = to_intel_crtc(conn_state->crtc); 4481 if (!crtc) 4482 return 0; 4483 4484 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4485 if (ret) 4486 return ret; 4487 4488 crtc_state = to_intel_crtc_state(crtc->base.state); 4489 4490 drm_WARN_ON(&dev_priv->drm, 4491 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4492 4493 if (!crtc_state->hw.active) 4494 return 0; 4495 4496 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4497 !crtc_state->hdmi_scrambling) 4498 return 0; 4499 4500 if (conn_state->commit && 4501 !try_wait_for_completion(&conn_state->commit->hw_done)) 4502 return 0; 4503 4504 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4505 if (ret < 0) { 4506 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4507 connector->base.base.id, connector->base.name, ret); 4508 return 0; 4509 } 4510 4511 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4512 crtc_state->hdmi_high_tmds_clock_ratio && 4513 !!(config & SCDC_SCRAMBLING_ENABLE) == 4514 crtc_state->hdmi_scrambling) 4515 return 0; 4516 4517 /* 4518 * HDMI 2.0 says that one should not send scrambled data 4519 * prior to configuring the sink scrambling, and that 4520 * TMDS clock/data transmission should be suspended when 4521 * changing the TMDS clock rate in the sink. So let's 4522 * just do a full modeset here, even though some sinks 4523 * would be perfectly happy if were to just reconfigure 4524 * the SCDC settings on the fly. 4525 */ 4526 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4527 } 4528 4529 static void intel_ddi_link_check(struct intel_encoder *encoder) 4530 { 4531 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4532 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4533 4534 /* TODO: Move checking the HDMI link state here as well. */ 4535 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4536 4537 intel_dp_link_check(encoder); 4538 } 4539 4540 static enum intel_hotplug_state 4541 intel_ddi_hotplug(struct intel_encoder *encoder, 4542 struct intel_connector *connector) 4543 { 4544 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4545 struct intel_dp *intel_dp = &dig_port->dp; 4546 bool is_tc = intel_encoder_is_tc(encoder); 4547 struct drm_modeset_acquire_ctx ctx; 4548 enum intel_hotplug_state state; 4549 int ret; 4550 4551 if (intel_dp->compliance.test_active && 4552 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4553 intel_dp_phy_test(encoder); 4554 /* just do the PHY test and nothing else */ 4555 return INTEL_HOTPLUG_UNCHANGED; 4556 } 4557 4558 state = intel_encoder_hotplug(encoder, connector); 4559 4560 if (!intel_tc_port_link_reset(dig_port)) { 4561 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4562 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4563 ret = intel_hdmi_reset_link(encoder, &ctx); 4564 drm_WARN_ON(encoder->base.dev, ret); 4565 } else { 4566 intel_dp_check_link_state(intel_dp); 4567 } 4568 } 4569 4570 /* 4571 * Unpowered type-c dongles can take some time to boot and be 4572 * responsible, so here giving some time to those dongles to power up 4573 * and then retrying the probe. 4574 * 4575 * On many platforms the HDMI live state signal is known to be 4576 * unreliable, so we can't use it to detect if a sink is connected or 4577 * not. Instead we detect if it's connected based on whether we can 4578 * read the EDID or not. That in turn has a problem during disconnect, 4579 * since the HPD interrupt may be raised before the DDC lines get 4580 * disconnected (due to how the required length of DDC vs. HPD 4581 * connector pins are specified) and so we'll still be able to get a 4582 * valid EDID. To solve this schedule another detection cycle if this 4583 * time around we didn't detect any change in the sink's connection 4584 * status. 4585 * 4586 * Type-c connectors which get their HPD signal deasserted then 4587 * reasserted, without unplugging/replugging the sink from the 4588 * connector, introduce a delay until the AUX channel communication 4589 * becomes functional. Retry the detection for 5 seconds on type-c 4590 * connectors to account for this delay. 4591 */ 4592 if (state == INTEL_HOTPLUG_UNCHANGED && 4593 connector->hotplug_retries < (is_tc ? 5 : 1) && 4594 !dig_port->dp.is_mst) 4595 state = INTEL_HOTPLUG_RETRY; 4596 4597 return state; 4598 } 4599 4600 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4601 { 4602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4603 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4604 4605 return intel_de_read(dev_priv, SDEISR) & bit; 4606 } 4607 4608 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4609 { 4610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4611 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4612 4613 return intel_de_read(dev_priv, DEISR) & bit; 4614 } 4615 4616 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4617 { 4618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4619 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4620 4621 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4622 } 4623 4624 static struct intel_connector * 4625 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4626 { 4627 struct intel_connector *connector; 4628 enum port port = dig_port->base.port; 4629 4630 connector = intel_connector_alloc(); 4631 if (!connector) 4632 return NULL; 4633 4634 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4635 intel_hdmi_init_connector(dig_port, connector); 4636 4637 return connector; 4638 } 4639 4640 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4641 { 4642 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4643 4644 if (dig_port->base.port != PORT_A) 4645 return false; 4646 4647 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4648 return false; 4649 4650 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4651 * supported configuration 4652 */ 4653 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4654 return true; 4655 4656 return false; 4657 } 4658 4659 static int 4660 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4661 { 4662 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4663 enum port port = dig_port->base.port; 4664 int max_lanes = 4; 4665 4666 if (DISPLAY_VER(dev_priv) >= 11) 4667 return max_lanes; 4668 4669 if (port == PORT_A || port == PORT_E) { 4670 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4671 max_lanes = port == PORT_A ? 4 : 0; 4672 else 4673 /* Both A and E share 2 lanes */ 4674 max_lanes = 2; 4675 } 4676 4677 /* 4678 * Some BIOS might fail to set this bit on port A if eDP 4679 * wasn't lit up at boot. Force this bit set when needed 4680 * so we use the proper lane count for our calculations. 4681 */ 4682 if (intel_ddi_a_force_4_lanes(dig_port)) { 4683 drm_dbg_kms(&dev_priv->drm, 4684 "Forcing DDI_A_4_LANES for port A\n"); 4685 dig_port->saved_port_bits |= DDI_A_4_LANES; 4686 max_lanes = 4; 4687 } 4688 4689 return max_lanes; 4690 } 4691 4692 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4693 enum port port) 4694 { 4695 if (port >= PORT_D_XELPD) 4696 return HPD_PORT_D + port - PORT_D_XELPD; 4697 else if (port >= PORT_TC1) 4698 return HPD_PORT_TC1 + port - PORT_TC1; 4699 else 4700 return HPD_PORT_A + port - PORT_A; 4701 } 4702 4703 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4704 enum port port) 4705 { 4706 if (port >= PORT_TC1) 4707 return HPD_PORT_C + port - PORT_TC1; 4708 else 4709 return HPD_PORT_A + port - PORT_A; 4710 } 4711 4712 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4713 enum port port) 4714 { 4715 if (port >= PORT_TC1) 4716 return HPD_PORT_TC1 + port - PORT_TC1; 4717 else 4718 return HPD_PORT_A + port - PORT_A; 4719 } 4720 4721 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4722 enum port port) 4723 { 4724 if (HAS_PCH_TGP(dev_priv)) 4725 return tgl_hpd_pin(dev_priv, port); 4726 4727 if (port >= PORT_TC1) 4728 return HPD_PORT_C + port - PORT_TC1; 4729 else 4730 return HPD_PORT_A + port - PORT_A; 4731 } 4732 4733 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4734 enum port port) 4735 { 4736 if (port >= PORT_C) 4737 return HPD_PORT_TC1 + port - PORT_C; 4738 else 4739 return HPD_PORT_A + port - PORT_A; 4740 } 4741 4742 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4743 enum port port) 4744 { 4745 if (port == PORT_D) 4746 return HPD_PORT_A; 4747 4748 if (HAS_PCH_TGP(dev_priv)) 4749 return icl_hpd_pin(dev_priv, port); 4750 4751 return HPD_PORT_A + port - PORT_A; 4752 } 4753 4754 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4755 { 4756 if (HAS_PCH_TGP(dev_priv)) 4757 return icl_hpd_pin(dev_priv, port); 4758 4759 return HPD_PORT_A + port - PORT_A; 4760 } 4761 4762 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4763 { 4764 if (DISPLAY_VER(i915) >= 12) 4765 return port >= PORT_TC1; 4766 else if (DISPLAY_VER(i915) >= 11) 4767 return port >= PORT_C; 4768 else 4769 return false; 4770 } 4771 4772 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4773 { 4774 intel_dp_encoder_suspend(encoder); 4775 } 4776 4777 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4778 { 4779 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4780 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4781 4782 /* 4783 * TODO: Move this to intel_dp_encoder_suspend(), 4784 * once modeset locking around that is removed. 4785 */ 4786 intel_encoder_link_check_flush_work(encoder); 4787 intel_tc_port_suspend(dig_port); 4788 } 4789 4790 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4791 { 4792 intel_dp_encoder_shutdown(encoder); 4793 intel_hdmi_encoder_shutdown(encoder); 4794 } 4795 4796 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4797 { 4798 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4799 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4800 4801 intel_tc_port_cleanup(dig_port); 4802 } 4803 4804 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4805 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4806 4807 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4808 { 4809 /* straps not used on skl+ */ 4810 if (DISPLAY_VER(i915) >= 9) 4811 return true; 4812 4813 switch (port) { 4814 case PORT_A: 4815 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4816 case PORT_B: 4817 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4818 case PORT_C: 4819 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4820 case PORT_D: 4821 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4822 case PORT_E: 4823 return true; /* no strap for DDI-E */ 4824 default: 4825 MISSING_CASE(port); 4826 return false; 4827 } 4828 } 4829 4830 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4831 { 4832 return init_dp || intel_encoder_is_tc(encoder); 4833 } 4834 4835 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4836 { 4837 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4838 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4839 "Platform does not support DSI\n"); 4840 } 4841 4842 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4843 { 4844 struct intel_encoder *encoder; 4845 4846 for_each_intel_encoder(&i915->drm, encoder) { 4847 /* FIXME what about second port for dual link DSI? */ 4848 if (encoder->port == port) 4849 return true; 4850 } 4851 4852 return false; 4853 } 4854 4855 void intel_ddi_init(struct drm_i915_private *dev_priv, 4856 const struct intel_bios_encoder_data *devdata) 4857 { 4858 struct intel_digital_port *dig_port; 4859 struct intel_encoder *encoder; 4860 bool init_hdmi, init_dp; 4861 enum port port; 4862 enum phy phy; 4863 4864 port = intel_bios_encoder_port(devdata); 4865 if (port == PORT_NONE) 4866 return; 4867 4868 if (!port_strap_detected(dev_priv, port)) { 4869 drm_dbg_kms(&dev_priv->drm, 4870 "Port %c strap not detected\n", port_name(port)); 4871 return; 4872 } 4873 4874 if (!assert_port_valid(dev_priv, port)) 4875 return; 4876 4877 if (port_in_use(dev_priv, port)) { 4878 drm_dbg_kms(&dev_priv->drm, 4879 "Port %c already claimed\n", port_name(port)); 4880 return; 4881 } 4882 4883 if (intel_bios_encoder_supports_dsi(devdata)) { 4884 /* BXT/GLK handled elsewhere, for now at least */ 4885 if (!assert_has_icl_dsi(dev_priv)) 4886 return; 4887 4888 icl_dsi_init(dev_priv, devdata); 4889 return; 4890 } 4891 4892 phy = intel_port_to_phy(dev_priv, port); 4893 4894 /* 4895 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4896 * have taken over some of the PHYs and made them unavailable to the 4897 * driver. In that case we should skip initializing the corresponding 4898 * outputs. 4899 */ 4900 if (intel_hti_uses_phy(dev_priv, phy)) { 4901 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4902 port_name(port), phy_name(phy)); 4903 return; 4904 } 4905 4906 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4907 intel_bios_encoder_supports_hdmi(devdata); 4908 init_dp = intel_bios_encoder_supports_dp(devdata); 4909 4910 if (intel_bios_encoder_is_lspcon(devdata)) { 4911 /* 4912 * Lspcon device needs to be driven with DP connector 4913 * with special detection sequence. So make sure DP 4914 * is initialized before lspcon. 4915 */ 4916 init_dp = true; 4917 init_hdmi = false; 4918 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4919 port_name(port)); 4920 } 4921 4922 if (!init_dp && !init_hdmi) { 4923 drm_dbg_kms(&dev_priv->drm, 4924 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4925 port_name(port)); 4926 return; 4927 } 4928 4929 if (intel_phy_is_snps(dev_priv, phy) && 4930 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4931 drm_dbg_kms(&dev_priv->drm, 4932 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4933 phy_name(phy)); 4934 } 4935 4936 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4937 if (!dig_port) 4938 return; 4939 4940 dig_port->aux_ch = AUX_CH_NONE; 4941 4942 encoder = &dig_port->base; 4943 encoder->devdata = devdata; 4944 4945 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4946 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4947 DRM_MODE_ENCODER_TMDS, 4948 "DDI %c/PHY %c", 4949 port_name(port - PORT_D_XELPD + PORT_D), 4950 phy_name(phy)); 4951 } else if (DISPLAY_VER(dev_priv) >= 12) { 4952 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4953 4954 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4955 DRM_MODE_ENCODER_TMDS, 4956 "DDI %s%c/PHY %s%c", 4957 port >= PORT_TC1 ? "TC" : "", 4958 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4959 tc_port != TC_PORT_NONE ? "TC" : "", 4960 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4961 } else if (DISPLAY_VER(dev_priv) >= 11) { 4962 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4963 4964 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4965 DRM_MODE_ENCODER_TMDS, 4966 "DDI %c%s/PHY %s%c", 4967 port_name(port), 4968 port >= PORT_C ? " (TC)" : "", 4969 tc_port != TC_PORT_NONE ? "TC" : "", 4970 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4971 } else { 4972 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4973 DRM_MODE_ENCODER_TMDS, 4974 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4975 } 4976 4977 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 4978 4979 mutex_init(&dig_port->hdcp_mutex); 4980 dig_port->num_hdcp_streams = 0; 4981 4982 encoder->hotplug = intel_ddi_hotplug; 4983 encoder->compute_output_type = intel_ddi_compute_output_type; 4984 encoder->compute_config = intel_ddi_compute_config; 4985 encoder->compute_config_late = intel_ddi_compute_config_late; 4986 encoder->enable = intel_enable_ddi; 4987 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4988 encoder->pre_enable = intel_ddi_pre_enable; 4989 encoder->disable = intel_disable_ddi; 4990 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4991 encoder->post_disable = intel_ddi_post_disable; 4992 encoder->update_pipe = intel_ddi_update_pipe; 4993 encoder->audio_enable = intel_audio_codec_enable; 4994 encoder->audio_disable = intel_audio_codec_disable; 4995 encoder->get_hw_state = intel_ddi_get_hw_state; 4996 encoder->sync_state = intel_ddi_sync_state; 4997 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4998 encoder->suspend = intel_ddi_encoder_suspend; 4999 encoder->shutdown = intel_ddi_encoder_shutdown; 5000 encoder->get_power_domains = intel_ddi_get_power_domains; 5001 5002 encoder->type = INTEL_OUTPUT_DDI; 5003 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5004 encoder->port = port; 5005 encoder->cloneable = 0; 5006 encoder->pipe_mask = ~0; 5007 5008 if (DISPLAY_VER(dev_priv) >= 14) { 5009 encoder->enable_clock = intel_mtl_pll_enable; 5010 encoder->disable_clock = intel_mtl_pll_disable; 5011 encoder->port_pll_type = intel_mtl_port_pll_type; 5012 encoder->get_config = mtl_ddi_get_config; 5013 } else if (IS_DG2(dev_priv)) { 5014 encoder->enable_clock = intel_mpllb_enable; 5015 encoder->disable_clock = intel_mpllb_disable; 5016 encoder->get_config = dg2_ddi_get_config; 5017 } else if (IS_ALDERLAKE_S(dev_priv)) { 5018 encoder->enable_clock = adls_ddi_enable_clock; 5019 encoder->disable_clock = adls_ddi_disable_clock; 5020 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5021 encoder->get_config = adls_ddi_get_config; 5022 } else if (IS_ROCKETLAKE(dev_priv)) { 5023 encoder->enable_clock = rkl_ddi_enable_clock; 5024 encoder->disable_clock = rkl_ddi_disable_clock; 5025 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5026 encoder->get_config = rkl_ddi_get_config; 5027 } else if (IS_DG1(dev_priv)) { 5028 encoder->enable_clock = dg1_ddi_enable_clock; 5029 encoder->disable_clock = dg1_ddi_disable_clock; 5030 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5031 encoder->get_config = dg1_ddi_get_config; 5032 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5033 if (intel_ddi_is_tc(dev_priv, port)) { 5034 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5035 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5036 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5037 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5038 encoder->get_config = icl_ddi_combo_get_config; 5039 } else { 5040 encoder->enable_clock = icl_ddi_combo_enable_clock; 5041 encoder->disable_clock = icl_ddi_combo_disable_clock; 5042 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5043 encoder->get_config = icl_ddi_combo_get_config; 5044 } 5045 } else if (DISPLAY_VER(dev_priv) >= 11) { 5046 if (intel_ddi_is_tc(dev_priv, port)) { 5047 encoder->enable_clock = icl_ddi_tc_enable_clock; 5048 encoder->disable_clock = icl_ddi_tc_disable_clock; 5049 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5050 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5051 encoder->get_config = icl_ddi_tc_get_config; 5052 } else { 5053 encoder->enable_clock = icl_ddi_combo_enable_clock; 5054 encoder->disable_clock = icl_ddi_combo_disable_clock; 5055 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5056 encoder->get_config = icl_ddi_combo_get_config; 5057 } 5058 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5059 /* BXT/GLK have fixed PLL->port mapping */ 5060 encoder->get_config = bxt_ddi_get_config; 5061 } else if (DISPLAY_VER(dev_priv) == 9) { 5062 encoder->enable_clock = skl_ddi_enable_clock; 5063 encoder->disable_clock = skl_ddi_disable_clock; 5064 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5065 encoder->get_config = skl_ddi_get_config; 5066 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5067 encoder->enable_clock = hsw_ddi_enable_clock; 5068 encoder->disable_clock = hsw_ddi_disable_clock; 5069 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5070 encoder->get_config = hsw_ddi_get_config; 5071 } 5072 5073 if (DISPLAY_VER(dev_priv) >= 14) { 5074 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5075 } else if (IS_DG2(dev_priv)) { 5076 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5077 } else if (DISPLAY_VER(dev_priv) >= 12) { 5078 if (intel_encoder_is_combo(encoder)) 5079 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5080 else 5081 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5082 } else if (DISPLAY_VER(dev_priv) >= 11) { 5083 if (intel_encoder_is_combo(encoder)) 5084 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5085 else 5086 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5087 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5088 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5089 } else { 5090 encoder->set_signal_levels = hsw_set_signal_levels; 5091 } 5092 5093 intel_ddi_buf_trans_init(encoder); 5094 5095 if (DISPLAY_VER(dev_priv) >= 13) 5096 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5097 else if (IS_DG1(dev_priv)) 5098 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5099 else if (IS_ROCKETLAKE(dev_priv)) 5100 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5101 else if (DISPLAY_VER(dev_priv) >= 12) 5102 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5103 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5104 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5105 else if (DISPLAY_VER(dev_priv) == 11) 5106 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5107 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5108 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5109 else 5110 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5111 5112 if (DISPLAY_VER(dev_priv) >= 11) 5113 dig_port->saved_port_bits = 5114 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5115 & DDI_BUF_PORT_REVERSAL; 5116 else 5117 dig_port->saved_port_bits = 5118 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5119 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5120 5121 if (intel_bios_encoder_lane_reversal(devdata)) 5122 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5123 5124 dig_port->dp.output_reg = INVALID_MMIO_REG; 5125 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5126 5127 if (need_aux_ch(encoder, init_dp)) { 5128 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5129 if (dig_port->aux_ch == AUX_CH_NONE) 5130 goto err; 5131 } 5132 5133 if (intel_encoder_is_tc(encoder)) { 5134 bool is_legacy = 5135 !intel_bios_encoder_supports_typec_usb(devdata) && 5136 !intel_bios_encoder_supports_tbt(devdata); 5137 5138 if (!is_legacy && init_hdmi) { 5139 is_legacy = !init_dp; 5140 5141 drm_dbg_kms(&dev_priv->drm, 5142 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5143 port_name(port), 5144 str_yes_no(init_dp), 5145 is_legacy ? "legacy" : "non-legacy"); 5146 } 5147 5148 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5149 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5150 5151 dig_port->lock = intel_tc_port_lock; 5152 dig_port->unlock = intel_tc_port_unlock; 5153 5154 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5155 goto err; 5156 } 5157 5158 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5159 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5160 5161 if (DISPLAY_VER(dev_priv) >= 11) { 5162 if (intel_encoder_is_tc(encoder)) 5163 dig_port->connected = intel_tc_port_connected; 5164 else 5165 dig_port->connected = lpt_digital_port_connected; 5166 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5167 dig_port->connected = bdw_digital_port_connected; 5168 } else if (DISPLAY_VER(dev_priv) == 9) { 5169 dig_port->connected = lpt_digital_port_connected; 5170 } else if (IS_BROADWELL(dev_priv)) { 5171 if (port == PORT_A) 5172 dig_port->connected = bdw_digital_port_connected; 5173 else 5174 dig_port->connected = lpt_digital_port_connected; 5175 } else if (IS_HASWELL(dev_priv)) { 5176 if (port == PORT_A) 5177 dig_port->connected = hsw_digital_port_connected; 5178 else 5179 dig_port->connected = lpt_digital_port_connected; 5180 } 5181 5182 intel_infoframe_init(dig_port); 5183 5184 if (init_dp) { 5185 if (!intel_ddi_init_dp_connector(dig_port)) 5186 goto err; 5187 5188 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5189 5190 if (dig_port->dp.mso_link_count) 5191 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5192 } 5193 5194 /* 5195 * In theory we don't need the encoder->type check, 5196 * but leave it just in case we have some really bad VBTs... 5197 */ 5198 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5199 if (!intel_ddi_init_hdmi_connector(dig_port)) 5200 goto err; 5201 } 5202 5203 return; 5204 5205 err: 5206 drm_encoder_cleanup(&encoder->base); 5207 kfree(dig_port); 5208 } 5209