1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_privacy_screen_consumer.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "icl_dsi.h" 38 #include "intel_audio.h" 39 #include "intel_audio_regs.h" 40 #include "intel_backlight.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_cx0_phy.h" 46 #include "intel_cx0_phy_regs.h" 47 #include "intel_ddi.h" 48 #include "intel_ddi_buf_trans.h" 49 #include "intel_de.h" 50 #include "intel_display_power.h" 51 #include "intel_display_types.h" 52 #include "intel_dkl_phy.h" 53 #include "intel_dkl_phy_regs.h" 54 #include "intel_dp.h" 55 #include "intel_dp_aux.h" 56 #include "intel_dp_link_training.h" 57 #include "intel_dp_mst.h" 58 #include "intel_dp_test.h" 59 #include "intel_dp_tunnel.h" 60 #include "intel_dpio_phy.h" 61 #include "intel_dsi.h" 62 #include "intel_encoder.h" 63 #include "intel_fdi.h" 64 #include "intel_fifo_underrun.h" 65 #include "intel_gmbus.h" 66 #include "intel_hdcp.h" 67 #include "intel_hdmi.h" 68 #include "intel_hotplug.h" 69 #include "intel_hti.h" 70 #include "intel_lspcon.h" 71 #include "intel_mg_phy_regs.h" 72 #include "intel_modeset_lock.h" 73 #include "intel_pps.h" 74 #include "intel_psr.h" 75 #include "intel_quirks.h" 76 #include "intel_snps_phy.h" 77 #include "intel_tc.h" 78 #include "intel_vdsc.h" 79 #include "intel_vdsc_regs.h" 80 #include "skl_scaler.h" 81 #include "skl_universal_plane.h" 82 83 static const u8 index_to_dp_signal_levels[] = { 84 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 88 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 91 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 }; 95 96 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 97 const struct intel_ddi_buf_trans *trans) 98 { 99 int level; 100 101 level = intel_bios_hdmi_level_shift(encoder->devdata); 102 if (level < 0) 103 level = trans->hdmi_default_entry; 104 105 return level; 106 } 107 108 static bool has_buf_trans_select(struct drm_i915_private *i915) 109 { 110 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 111 } 112 113 static bool has_iboost(struct drm_i915_private *i915) 114 { 115 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 116 } 117 118 /* 119 * Starting with Haswell, DDI port buffers must be programmed with correct 120 * values in advance. This function programs the correct values for 121 * DP/eDP/FDI use cases. 122 */ 123 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 124 const struct intel_crtc_state *crtc_state) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 u32 iboost_bit = 0; 128 int i, n_entries; 129 enum port port = encoder->port; 130 const struct intel_ddi_buf_trans *trans; 131 132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 134 return; 135 136 /* If we're boosting the current, set bit 31 of trans1 */ 137 if (has_iboost(dev_priv) && 138 intel_bios_dp_boost_level(encoder->devdata)) 139 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 140 141 for (i = 0; i < n_entries; i++) { 142 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 143 trans->entries[i].hsw.trans1 | iboost_bit); 144 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 145 trans->entries[i].hsw.trans2); 146 } 147 } 148 149 /* 150 * Starting with Haswell, DDI port buffers must be programmed with correct 151 * values in advance. This function programs the correct values for 152 * HDMI/DVI use cases. 153 */ 154 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 155 const struct intel_crtc_state *crtc_state) 156 { 157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 158 int level = intel_ddi_level(encoder, crtc_state, 0); 159 u32 iboost_bit = 0; 160 int n_entries; 161 enum port port = encoder->port; 162 const struct intel_ddi_buf_trans *trans; 163 164 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 165 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 166 return; 167 168 /* If we're boosting the current, set bit 31 of trans1 */ 169 if (has_iboost(dev_priv) && 170 intel_bios_hdmi_boost_level(encoder->devdata)) 171 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 172 173 /* Entry 9 is for HDMI: */ 174 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 175 trans->entries[level].hsw.trans1 | iboost_bit); 176 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 177 trans->entries[level].hsw.trans2); 178 } 179 180 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 181 { 182 int ret; 183 184 /* FIXME: find out why Bspec's 100us timeout is too short */ 185 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 186 XELPDP_PORT_BUF_PHY_IDLE), 10000); 187 if (ret) 188 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 189 port_name(port)); 190 } 191 192 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 193 enum port port) 194 { 195 if (IS_BROXTON(dev_priv)) { 196 udelay(16); 197 return; 198 } 199 200 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 201 DDI_BUF_IS_IDLE), 8)) 202 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 203 port_name(port)); 204 } 205 206 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 207 { 208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 209 enum port port = encoder->port; 210 int timeout_us; 211 int ret; 212 213 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 214 if (DISPLAY_VER(dev_priv) < 10) { 215 usleep_range(518, 1000); 216 return; 217 } 218 219 if (DISPLAY_VER(dev_priv) >= 14) { 220 timeout_us = 10000; 221 } else if (IS_DG2(dev_priv)) { 222 timeout_us = 1200; 223 } else if (DISPLAY_VER(dev_priv) >= 12) { 224 if (intel_encoder_is_tc(encoder)) 225 timeout_us = 3000; 226 else 227 timeout_us = 1000; 228 } else { 229 timeout_us = 500; 230 } 231 232 if (DISPLAY_VER(dev_priv) >= 14) 233 ret = _wait_for(!(intel_de_read(dev_priv, 234 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 235 XELPDP_PORT_BUF_PHY_IDLE), 236 timeout_us, 10, 10); 237 else 238 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 239 timeout_us, 10, 10); 240 241 if (ret) 242 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state) 333 { 334 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 336 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 337 338 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 339 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 340 DDI_BUF_TRANS_SELECT(0); 341 342 if (dig_port->lane_reversal) 343 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 344 if (dig_port->ddi_a_4_lanes) 345 intel_dp->DP |= DDI_A_4_LANES; 346 347 if (DISPLAY_VER(i915) >= 14) { 348 if (intel_dp_is_uhbr(crtc_state)) 349 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 350 else 351 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 352 } 353 354 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 355 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 356 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 357 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 358 } 359 } 360 361 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 362 enum port port) 363 { 364 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 365 366 switch (val) { 367 case DDI_CLK_SEL_NONE: 368 return 0; 369 case DDI_CLK_SEL_TBT_162: 370 return 162000; 371 case DDI_CLK_SEL_TBT_270: 372 return 270000; 373 case DDI_CLK_SEL_TBT_540: 374 return 540000; 375 case DDI_CLK_SEL_TBT_810: 376 return 810000; 377 default: 378 MISSING_CASE(val); 379 return 0; 380 } 381 } 382 383 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 384 { 385 /* CRT dotclock is determined via other means */ 386 if (pipe_config->has_pch_encoder) 387 return; 388 389 pipe_config->hw.adjusted_mode.crtc_clock = 390 intel_crtc_dotclock(pipe_config); 391 } 392 393 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 394 const struct drm_connector_state *conn_state) 395 { 396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 398 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 399 u32 temp; 400 401 if (!intel_crtc_has_dp_encoder(crtc_state)) 402 return; 403 404 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 405 406 temp = DP_MSA_MISC_SYNC_CLOCK; 407 408 switch (crtc_state->pipe_bpp) { 409 case 18: 410 temp |= DP_MSA_MISC_6_BPC; 411 break; 412 case 24: 413 temp |= DP_MSA_MISC_8_BPC; 414 break; 415 case 30: 416 temp |= DP_MSA_MISC_10_BPC; 417 break; 418 case 36: 419 temp |= DP_MSA_MISC_12_BPC; 420 break; 421 default: 422 MISSING_CASE(crtc_state->pipe_bpp); 423 break; 424 } 425 426 /* nonsense combination */ 427 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 428 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 429 430 if (crtc_state->limited_color_range) 431 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 432 433 /* 434 * As per DP 1.2 spec section 2.3.4.3 while sending 435 * YCBCR 444 signals we should program MSA MISC1/0 fields with 436 * colorspace information. 437 */ 438 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 439 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 440 441 /* 442 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 443 * of Color Encoding Format and Content Color Gamut] while sending 444 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 445 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 446 */ 447 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 448 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 449 450 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 451 temp); 452 } 453 454 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 455 { 456 if (master_transcoder == TRANSCODER_EDP) 457 return 0; 458 else 459 return master_transcoder + 1; 460 } 461 462 static void 463 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 464 bool enable) 465 { 466 struct intel_display *display = to_intel_display(crtc_state); 467 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 468 u32 val = 0; 469 470 if (!HAS_DP20(display)) 471 return; 472 473 if (enable && intel_dp_is_uhbr(crtc_state)) 474 val = TRANS_DP2_128B132B_CHANNEL_CODING; 475 476 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 477 } 478 479 /* 480 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 481 * 482 * Only intended to be used by intel_ddi_enable_transcoder_func() and 483 * intel_ddi_config_transcoder_func(). 484 */ 485 static u32 486 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 487 const struct intel_crtc_state *crtc_state) 488 { 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 enum pipe pipe = crtc->pipe; 492 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 493 enum port port = encoder->port; 494 u32 temp; 495 496 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 497 temp = TRANS_DDI_FUNC_ENABLE; 498 if (DISPLAY_VER(dev_priv) >= 12) 499 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 500 else 501 temp |= TRANS_DDI_SELECT_PORT(port); 502 503 switch (crtc_state->pipe_bpp) { 504 default: 505 MISSING_CASE(crtc_state->pipe_bpp); 506 fallthrough; 507 case 18: 508 temp |= TRANS_DDI_BPC_6; 509 break; 510 case 24: 511 temp |= TRANS_DDI_BPC_8; 512 break; 513 case 30: 514 temp |= TRANS_DDI_BPC_10; 515 break; 516 case 36: 517 temp |= TRANS_DDI_BPC_12; 518 break; 519 } 520 521 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 522 temp |= TRANS_DDI_PVSYNC; 523 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 524 temp |= TRANS_DDI_PHSYNC; 525 526 if (cpu_transcoder == TRANSCODER_EDP) { 527 switch (pipe) { 528 default: 529 MISSING_CASE(pipe); 530 fallthrough; 531 case PIPE_A: 532 /* On Haswell, can only use the always-on power well for 533 * eDP when not using the panel fitter, and when not 534 * using motion blur mitigation (which we don't 535 * support). */ 536 if (crtc_state->pch_pfit.force_thru) 537 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 538 else 539 temp |= TRANS_DDI_EDP_INPUT_A_ON; 540 break; 541 case PIPE_B: 542 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 543 break; 544 case PIPE_C: 545 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 546 break; 547 } 548 } 549 550 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 551 if (crtc_state->has_hdmi_sink) 552 temp |= TRANS_DDI_MODE_SELECT_HDMI; 553 else 554 temp |= TRANS_DDI_MODE_SELECT_DVI; 555 556 if (crtc_state->hdmi_scrambling) 557 temp |= TRANS_DDI_HDMI_SCRAMBLING; 558 if (crtc_state->hdmi_high_tmds_clock_ratio) 559 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 560 if (DISPLAY_VER(dev_priv) >= 14) 561 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 562 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 563 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 564 temp |= (crtc_state->fdi_lanes - 1) << 1; 565 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 566 intel_dp_is_uhbr(crtc_state)) { 567 if (intel_dp_is_uhbr(crtc_state)) 568 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 569 else 570 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 573 if (DISPLAY_VER(dev_priv) >= 12) { 574 enum transcoder master; 575 576 master = crtc_state->mst_master_transcoder; 577 drm_WARN_ON(&dev_priv->drm, 578 master == INVALID_TRANSCODER); 579 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 580 } 581 } else { 582 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 583 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 584 } 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 587 crtc_state->master_transcoder != INVALID_TRANSCODER) { 588 u8 master_select = 589 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 590 591 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 592 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 593 } 594 595 return temp; 596 } 597 598 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 599 const struct intel_crtc_state *crtc_state) 600 { 601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 603 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 604 605 if (DISPLAY_VER(dev_priv) >= 11) { 606 enum transcoder master_transcoder = crtc_state->master_transcoder; 607 u32 ctl2 = 0; 608 609 if (master_transcoder != INVALID_TRANSCODER) { 610 u8 master_select = 611 bdw_trans_port_sync_master_select(master_transcoder); 612 613 ctl2 |= PORT_SYNC_MODE_ENABLE | 614 PORT_SYNC_MODE_MASTER_SELECT(master_select); 615 } 616 617 intel_de_write(dev_priv, 618 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 619 ctl2); 620 } 621 622 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 623 intel_ddi_transcoder_func_reg_val_get(encoder, 624 crtc_state)); 625 } 626 627 /* 628 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 629 * bit for the DDI function and enables the DP2 configuration. Called for all 630 * transcoder types. 631 */ 632 void 633 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 634 const struct intel_crtc_state *crtc_state) 635 { 636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 638 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 639 u32 ctl; 640 641 intel_ddi_config_transcoder_dp2(crtc_state, true); 642 643 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 644 ctl &= ~TRANS_DDI_FUNC_ENABLE; 645 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 646 ctl); 647 } 648 649 /* 650 * Disable the DDI function and port syncing. 651 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 652 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 653 * transcoders these are done later in intel_ddi_post_disable_dp(). 654 */ 655 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 656 { 657 struct intel_display *display = to_intel_display(crtc_state); 658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 660 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 661 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 662 u32 ctl; 663 664 if (DISPLAY_VER(dev_priv) >= 11) 665 intel_de_write(dev_priv, 666 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 667 0); 668 669 ctl = intel_de_read(dev_priv, 670 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 671 672 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 673 674 ctl &= ~TRANS_DDI_FUNC_ENABLE; 675 676 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 677 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 678 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 679 680 if (DISPLAY_VER(dev_priv) >= 12) { 681 if (!intel_dp_mst_is_master_trans(crtc_state) || 682 (!is_mst && intel_dp_is_uhbr(crtc_state))) { 683 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 684 TRANS_DDI_MODE_SELECT_MASK); 685 } 686 } else { 687 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 688 } 689 690 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 691 ctl); 692 693 if (intel_dp_mst_is_slave_trans(crtc_state)) 694 intel_ddi_config_transcoder_dp2(crtc_state, false); 695 696 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 697 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 698 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 699 /* Quirk time at 100ms for reliable operation */ 700 msleep(100); 701 } 702 } 703 704 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 705 enum transcoder cpu_transcoder, 706 bool enable, u32 hdcp_mask) 707 { 708 struct drm_device *dev = intel_encoder->base.dev; 709 struct drm_i915_private *dev_priv = to_i915(dev); 710 intel_wakeref_t wakeref; 711 int ret = 0; 712 713 wakeref = intel_display_power_get_if_enabled(dev_priv, 714 intel_encoder->power_domain); 715 if (drm_WARN_ON(dev, !wakeref)) 716 return -ENXIO; 717 718 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 719 hdcp_mask, enable ? hdcp_mask : 0); 720 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 721 return ret; 722 } 723 724 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 725 { 726 struct intel_display *display = to_intel_display(intel_connector); 727 struct drm_i915_private *dev_priv = to_i915(display->drm); 728 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 729 int type = intel_connector->base.connector_type; 730 enum port port = encoder->port; 731 enum transcoder cpu_transcoder; 732 intel_wakeref_t wakeref; 733 enum pipe pipe = 0; 734 u32 ddi_mode; 735 bool ret; 736 737 wakeref = intel_display_power_get_if_enabled(dev_priv, 738 encoder->power_domain); 739 if (!wakeref) 740 return false; 741 742 /* Note: This returns false for DP MST primary encoders. */ 743 if (!encoder->get_hw_state(encoder, &pipe)) { 744 ret = false; 745 goto out; 746 } 747 748 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 749 cpu_transcoder = TRANSCODER_EDP; 750 else 751 cpu_transcoder = (enum transcoder) pipe; 752 753 ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 754 TRANS_DDI_MODE_SELECT_MASK; 755 756 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 757 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 758 ret = type == DRM_MODE_CONNECTOR_HDMIA; 759 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 760 ret = type == DRM_MODE_CONNECTOR_VGA; 761 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 762 ret = type == DRM_MODE_CONNECTOR_eDP || 763 type == DRM_MODE_CONNECTOR_DisplayPort; 764 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 765 /* 766 * encoder->get_hw_state() should have bailed out on MST. This 767 * must be SST and non-eDP. 768 */ 769 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 770 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 771 /* encoder->get_hw_state() should have bailed out on MST. */ 772 ret = false; 773 } else { 774 ret = false; 775 } 776 777 out: 778 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 779 780 return ret; 781 } 782 783 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 784 u8 *pipe_mask, bool *is_dp_mst) 785 { 786 struct intel_display *display = to_intel_display(encoder); 787 struct drm_i915_private *dev_priv = to_i915(display->drm); 788 enum port port = encoder->port; 789 intel_wakeref_t wakeref; 790 enum pipe p; 791 u32 tmp; 792 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 793 794 *pipe_mask = 0; 795 *is_dp_mst = false; 796 797 wakeref = intel_display_power_get_if_enabled(dev_priv, 798 encoder->power_domain); 799 if (!wakeref) 800 return; 801 802 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 803 if (!(tmp & DDI_BUF_CTL_ENABLE)) 804 goto out; 805 806 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 807 tmp = intel_de_read(dev_priv, 808 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 809 810 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 811 default: 812 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 813 fallthrough; 814 case TRANS_DDI_EDP_INPUT_A_ON: 815 case TRANS_DDI_EDP_INPUT_A_ONOFF: 816 *pipe_mask = BIT(PIPE_A); 817 break; 818 case TRANS_DDI_EDP_INPUT_B_ONOFF: 819 *pipe_mask = BIT(PIPE_B); 820 break; 821 case TRANS_DDI_EDP_INPUT_C_ONOFF: 822 *pipe_mask = BIT(PIPE_C); 823 break; 824 } 825 826 goto out; 827 } 828 829 for_each_pipe(dev_priv, p) { 830 enum transcoder cpu_transcoder = (enum transcoder)p; 831 u32 port_mask, ddi_select, ddi_mode; 832 intel_wakeref_t trans_wakeref; 833 834 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 835 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 836 if (!trans_wakeref) 837 continue; 838 839 if (DISPLAY_VER(dev_priv) >= 12) { 840 port_mask = TGL_TRANS_DDI_PORT_MASK; 841 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 842 } else { 843 port_mask = TRANS_DDI_PORT_MASK; 844 ddi_select = TRANS_DDI_SELECT_PORT(port); 845 } 846 847 tmp = intel_de_read(dev_priv, 848 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 849 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 850 trans_wakeref); 851 852 if ((tmp & port_mask) != ddi_select) 853 continue; 854 855 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 856 857 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 858 mst_pipe_mask |= BIT(p); 859 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 860 dp128b132b_pipe_mask |= BIT(p); 861 862 *pipe_mask |= BIT(p); 863 } 864 865 if (!*pipe_mask) 866 drm_dbg_kms(&dev_priv->drm, 867 "No pipe for [ENCODER:%d:%s] found\n", 868 encoder->base.base.id, encoder->base.name); 869 870 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 871 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 872 873 /* 874 * If we don't have 8b/10b MST, but have more than one 875 * transcoder in 128b/132b mode, we know it must be 128b/132b 876 * MST. 877 * 878 * Otherwise, we fall back to checking the current MST 879 * state. It's not accurate for hardware takeover at probe, but 880 * we don't expect MST to have been enabled at that point, and 881 * can assume it's SST. 882 */ 883 if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst) 884 mst_pipe_mask = dp128b132b_pipe_mask; 885 } 886 887 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 888 drm_dbg_kms(&dev_priv->drm, 889 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 890 encoder->base.base.id, encoder->base.name, 891 *pipe_mask); 892 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 893 } 894 895 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 896 drm_dbg_kms(&dev_priv->drm, 897 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 898 encoder->base.base.id, encoder->base.name, 899 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 900 else 901 *is_dp_mst = mst_pipe_mask; 902 903 out: 904 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 905 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 906 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 907 BXT_PHY_LANE_POWERDOWN_ACK | 908 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 909 drm_err(&dev_priv->drm, 910 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 911 encoder->base.base.id, encoder->base.name, tmp); 912 } 913 914 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 915 } 916 917 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 918 enum pipe *pipe) 919 { 920 u8 pipe_mask; 921 bool is_mst; 922 923 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 924 925 if (is_mst || !pipe_mask) 926 return false; 927 928 *pipe = ffs(pipe_mask) - 1; 929 930 return true; 931 } 932 933 static enum intel_display_power_domain 934 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 935 const struct intel_crtc_state *crtc_state) 936 { 937 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 938 939 /* 940 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 941 * DC states enabled at the same time, while for driver initiated AUX 942 * transfers we need the same AUX IOs to be powered but with DC states 943 * disabled. Accordingly use the AUX_IO_<port> power domain here which 944 * leaves DC states enabled. 945 * 946 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 947 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 948 * well, so we can acquire a wider AUX_<port> power domain reference 949 * instead of a specific AUX_IO_<port> reference without powering up any 950 * extra wells. 951 */ 952 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 953 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 954 else if (DISPLAY_VER(i915) < 14 && 955 (intel_crtc_has_dp_encoder(crtc_state) || 956 intel_encoder_is_tc(&dig_port->base))) 957 return intel_aux_power_domain(dig_port); 958 else 959 return POWER_DOMAIN_INVALID; 960 } 961 962 static void 963 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 964 const struct intel_crtc_state *crtc_state) 965 { 966 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 967 enum intel_display_power_domain domain = 968 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 969 970 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 971 972 if (domain == POWER_DOMAIN_INVALID) 973 return; 974 975 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 976 } 977 978 static void 979 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 980 const struct intel_crtc_state *crtc_state) 981 { 982 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 983 enum intel_display_power_domain domain = 984 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 985 intel_wakeref_t wf; 986 987 wf = fetch_and_zero(&dig_port->aux_wakeref); 988 if (!wf) 989 return; 990 991 intel_display_power_put(i915, domain, wf); 992 } 993 994 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 995 struct intel_crtc_state *crtc_state) 996 { 997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 998 struct intel_digital_port *dig_port; 999 1000 /* 1001 * TODO: Add support for MST encoders. Atm, the following should never 1002 * happen since fake-MST encoders don't set their get_power_domains() 1003 * hook. 1004 */ 1005 if (drm_WARN_ON(&dev_priv->drm, 1006 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1007 return; 1008 1009 dig_port = enc_to_dig_port(encoder); 1010 1011 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1012 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 1013 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 1014 dig_port->ddi_io_power_domain); 1015 } 1016 1017 main_link_aux_power_domain_get(dig_port, crtc_state); 1018 } 1019 1020 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1021 const struct intel_crtc_state *crtc_state) 1022 { 1023 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1025 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1026 enum phy phy = intel_encoder_to_phy(encoder); 1027 u32 val; 1028 1029 if (cpu_transcoder == TRANSCODER_EDP) 1030 return; 1031 1032 if (DISPLAY_VER(dev_priv) >= 13) 1033 val = TGL_TRANS_CLK_SEL_PORT(phy); 1034 else if (DISPLAY_VER(dev_priv) >= 12) 1035 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1036 else 1037 val = TRANS_CLK_SEL_PORT(encoder->port); 1038 1039 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1040 } 1041 1042 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1043 { 1044 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1045 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1046 u32 val; 1047 1048 if (cpu_transcoder == TRANSCODER_EDP) 1049 return; 1050 1051 if (DISPLAY_VER(dev_priv) >= 12) 1052 val = TGL_TRANS_CLK_SEL_DISABLED; 1053 else 1054 val = TRANS_CLK_SEL_DISABLED; 1055 1056 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1057 } 1058 1059 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1060 enum port port, u8 iboost) 1061 { 1062 u32 tmp; 1063 1064 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1065 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1066 if (iboost) 1067 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1068 else 1069 tmp |= BALANCE_LEG_DISABLE(port); 1070 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1071 } 1072 1073 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1074 const struct intel_crtc_state *crtc_state, 1075 int level) 1076 { 1077 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1078 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1079 u8 iboost; 1080 1081 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1082 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1083 else 1084 iboost = intel_bios_dp_boost_level(encoder->devdata); 1085 1086 if (iboost == 0) { 1087 const struct intel_ddi_buf_trans *trans; 1088 int n_entries; 1089 1090 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1091 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1092 return; 1093 1094 iboost = trans->entries[level].hsw.i_boost; 1095 } 1096 1097 /* Make sure that the requested I_boost is valid */ 1098 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1099 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1100 return; 1101 } 1102 1103 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1104 1105 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1106 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1107 } 1108 1109 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1110 const struct intel_crtc_state *crtc_state) 1111 { 1112 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1113 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1114 int n_entries; 1115 1116 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1117 1118 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1119 n_entries = 1; 1120 if (drm_WARN_ON(&dev_priv->drm, 1121 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1122 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1123 1124 return index_to_dp_signal_levels[n_entries - 1] & 1125 DP_TRAIN_VOLTAGE_SWING_MASK; 1126 } 1127 1128 /* 1129 * We assume that the full set of pre-emphasis values can be 1130 * used on all DDI platforms. Should that change we need to 1131 * rethink this code. 1132 */ 1133 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1134 { 1135 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1136 } 1137 1138 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1139 int lane) 1140 { 1141 if (crtc_state->port_clock > 600000) 1142 return 0; 1143 1144 if (crtc_state->lane_count == 4) 1145 return lane >= 1 ? LOADGEN_SELECT : 0; 1146 else 1147 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1148 } 1149 1150 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1151 const struct intel_crtc_state *crtc_state) 1152 { 1153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1154 const struct intel_ddi_buf_trans *trans; 1155 enum phy phy = intel_encoder_to_phy(encoder); 1156 int n_entries, ln; 1157 u32 val; 1158 1159 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1160 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1161 return; 1162 1163 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1164 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1165 1166 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1167 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1168 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1169 intel_dp->hobl_active ? val : 0); 1170 } 1171 1172 /* Set PORT_TX_DW5 */ 1173 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1174 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1175 TAP2_DISABLE | TAP3_DISABLE); 1176 val |= SCALING_MODE_SEL(0x2); 1177 val |= RTERM_SELECT(0x6); 1178 val |= TAP3_DISABLE; 1179 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1180 1181 /* Program PORT_TX_DW2 */ 1182 for (ln = 0; ln < 4; ln++) { 1183 int level = intel_ddi_level(encoder, crtc_state, ln); 1184 1185 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1186 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1187 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1188 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1189 RCOMP_SCALAR(0x98)); 1190 } 1191 1192 /* Program PORT_TX_DW4 */ 1193 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1194 for (ln = 0; ln < 4; ln++) { 1195 int level = intel_ddi_level(encoder, crtc_state, ln); 1196 1197 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1198 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1199 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1200 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1201 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1202 } 1203 1204 /* Program PORT_TX_DW7 */ 1205 for (ln = 0; ln < 4; ln++) { 1206 int level = intel_ddi_level(encoder, crtc_state, ln); 1207 1208 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1209 N_SCALAR_MASK, 1210 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1211 } 1212 } 1213 1214 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1215 const struct intel_crtc_state *crtc_state) 1216 { 1217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1218 enum phy phy = intel_encoder_to_phy(encoder); 1219 u32 val; 1220 int ln; 1221 1222 /* 1223 * 1. If port type is eDP or DP, 1224 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1225 * else clear to 0b. 1226 */ 1227 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1228 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1229 val &= ~COMMON_KEEPER_EN; 1230 else 1231 val |= COMMON_KEEPER_EN; 1232 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1233 1234 /* 2. Program loadgen select */ 1235 /* 1236 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1237 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1238 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1239 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1240 */ 1241 for (ln = 0; ln < 4; ln++) { 1242 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1243 LOADGEN_SELECT, 1244 icl_combo_phy_loadgen_select(crtc_state, ln)); 1245 } 1246 1247 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1248 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1249 0, SUS_CLOCK_CONFIG); 1250 1251 /* 4. Clear training enable to change swing values */ 1252 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1253 val &= ~TX_TRAINING_EN; 1254 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1255 1256 /* 5. Program swing and de-emphasis */ 1257 icl_ddi_combo_vswing_program(encoder, crtc_state); 1258 1259 /* 6. Set training enable to trigger update */ 1260 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1261 val |= TX_TRAINING_EN; 1262 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1263 } 1264 1265 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1266 const struct intel_crtc_state *crtc_state) 1267 { 1268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1269 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1270 const struct intel_ddi_buf_trans *trans; 1271 int n_entries, ln; 1272 1273 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1274 return; 1275 1276 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1277 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1278 return; 1279 1280 for (ln = 0; ln < 2; ln++) { 1281 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1282 CRI_USE_FS32, 0); 1283 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1284 CRI_USE_FS32, 0); 1285 } 1286 1287 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1288 for (ln = 0; ln < 2; ln++) { 1289 int level; 1290 1291 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1292 1293 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1294 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1295 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1296 1297 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1298 1299 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1300 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1301 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1302 } 1303 1304 /* Program MG_TX_DRVCTRL with values from vswing table */ 1305 for (ln = 0; ln < 2; ln++) { 1306 int level; 1307 1308 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1309 1310 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1311 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1312 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1313 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1314 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1315 CRI_TXDEEMPH_OVERRIDE_EN); 1316 1317 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1318 1319 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1320 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1321 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1322 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1323 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1324 CRI_TXDEEMPH_OVERRIDE_EN); 1325 1326 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1327 } 1328 1329 /* 1330 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1331 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1332 * values from table for which TX1 and TX2 enabled. 1333 */ 1334 for (ln = 0; ln < 2; ln++) { 1335 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1336 CFG_LOW_RATE_LKREN_EN, 1337 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1338 } 1339 1340 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1341 for (ln = 0; ln < 2; ln++) { 1342 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1343 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1344 CFG_AMI_CK_DIV_OVERRIDE_EN, 1345 crtc_state->port_clock > 500000 ? 1346 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1347 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1348 1349 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1350 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1351 CFG_AMI_CK_DIV_OVERRIDE_EN, 1352 crtc_state->port_clock > 500000 ? 1353 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1354 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1355 } 1356 1357 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1358 for (ln = 0; ln < 2; ln++) { 1359 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1360 0, CRI_CALCINIT); 1361 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1362 0, CRI_CALCINIT); 1363 } 1364 } 1365 1366 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1367 const struct intel_crtc_state *crtc_state) 1368 { 1369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1370 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1371 const struct intel_ddi_buf_trans *trans; 1372 int n_entries, ln; 1373 1374 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1375 return; 1376 1377 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1378 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1379 return; 1380 1381 for (ln = 0; ln < 2; ln++) { 1382 int level; 1383 1384 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1385 1386 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1387 1388 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1389 DKL_TX_PRESHOOT_COEFF_MASK | 1390 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1391 DKL_TX_VSWING_CONTROL_MASK, 1392 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1393 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1394 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1395 1396 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1397 1398 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1399 DKL_TX_PRESHOOT_COEFF_MASK | 1400 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1401 DKL_TX_VSWING_CONTROL_MASK, 1402 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1403 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1404 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1405 1406 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1407 DKL_TX_DP20BITMODE, 0); 1408 1409 if (IS_ALDERLAKE_P(dev_priv)) { 1410 u32 val; 1411 1412 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1413 if (ln == 0) { 1414 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1415 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1416 } else { 1417 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1418 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1419 } 1420 } else { 1421 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1422 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1423 } 1424 1425 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1426 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1427 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1428 val); 1429 } 1430 } 1431 } 1432 1433 static int translate_signal_level(struct intel_dp *intel_dp, 1434 u8 signal_levels) 1435 { 1436 struct intel_display *display = to_intel_display(intel_dp); 1437 int i; 1438 1439 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1440 if (index_to_dp_signal_levels[i] == signal_levels) 1441 return i; 1442 } 1443 1444 drm_WARN(display->drm, 1, 1445 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1446 signal_levels); 1447 1448 return 0; 1449 } 1450 1451 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1452 const struct intel_crtc_state *crtc_state, 1453 int lane) 1454 { 1455 u8 train_set = intel_dp->train_set[lane]; 1456 1457 if (intel_dp_is_uhbr(crtc_state)) { 1458 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1459 } else { 1460 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1461 DP_TRAIN_PRE_EMPHASIS_MASK); 1462 1463 return translate_signal_level(intel_dp, signal_levels); 1464 } 1465 } 1466 1467 int intel_ddi_level(struct intel_encoder *encoder, 1468 const struct intel_crtc_state *crtc_state, 1469 int lane) 1470 { 1471 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1472 const struct intel_ddi_buf_trans *trans; 1473 int level, n_entries; 1474 1475 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1476 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1477 return 0; 1478 1479 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1480 level = intel_ddi_hdmi_level(encoder, trans); 1481 else 1482 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1483 lane); 1484 1485 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1486 level = n_entries - 1; 1487 1488 return level; 1489 } 1490 1491 static void 1492 hsw_set_signal_levels(struct intel_encoder *encoder, 1493 const struct intel_crtc_state *crtc_state) 1494 { 1495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1496 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1497 int level = intel_ddi_level(encoder, crtc_state, 0); 1498 enum port port = encoder->port; 1499 u32 signal_levels; 1500 1501 if (has_iboost(dev_priv)) 1502 skl_ddi_set_iboost(encoder, crtc_state, level); 1503 1504 /* HDMI ignores the rest */ 1505 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1506 return; 1507 1508 signal_levels = DDI_BUF_TRANS_SELECT(level); 1509 1510 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1511 signal_levels); 1512 1513 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1514 intel_dp->DP |= signal_levels; 1515 1516 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1517 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1518 } 1519 1520 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1521 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1522 { 1523 mutex_lock(&i915->display.dpll.lock); 1524 1525 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1526 1527 /* 1528 * "This step and the step before must be 1529 * done with separate register writes." 1530 */ 1531 intel_de_rmw(i915, reg, clk_off, 0); 1532 1533 mutex_unlock(&i915->display.dpll.lock); 1534 } 1535 1536 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1537 u32 clk_off) 1538 { 1539 mutex_lock(&i915->display.dpll.lock); 1540 1541 intel_de_rmw(i915, reg, 0, clk_off); 1542 1543 mutex_unlock(&i915->display.dpll.lock); 1544 } 1545 1546 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1547 u32 clk_off) 1548 { 1549 return !(intel_de_read(i915, reg) & clk_off); 1550 } 1551 1552 static struct intel_shared_dpll * 1553 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1554 u32 clk_sel_mask, u32 clk_sel_shift) 1555 { 1556 enum intel_dpll_id id; 1557 1558 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1559 1560 return intel_get_shared_dpll_by_id(i915, id); 1561 } 1562 1563 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1564 const struct intel_crtc_state *crtc_state) 1565 { 1566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1567 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1568 enum phy phy = intel_encoder_to_phy(encoder); 1569 1570 if (drm_WARN_ON(&i915->drm, !pll)) 1571 return; 1572 1573 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1574 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1575 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1576 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1577 } 1578 1579 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1580 { 1581 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1582 enum phy phy = intel_encoder_to_phy(encoder); 1583 1584 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1585 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1586 } 1587 1588 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1589 { 1590 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1591 enum phy phy = intel_encoder_to_phy(encoder); 1592 1593 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1594 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1595 } 1596 1597 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1598 { 1599 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1600 enum phy phy = intel_encoder_to_phy(encoder); 1601 1602 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1603 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1604 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1605 } 1606 1607 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1608 const struct intel_crtc_state *crtc_state) 1609 { 1610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1611 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1612 enum phy phy = intel_encoder_to_phy(encoder); 1613 1614 if (drm_WARN_ON(&i915->drm, !pll)) 1615 return; 1616 1617 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1618 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1619 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1620 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1621 } 1622 1623 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1624 { 1625 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1626 enum phy phy = intel_encoder_to_phy(encoder); 1627 1628 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1629 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1630 } 1631 1632 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1633 { 1634 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1635 enum phy phy = intel_encoder_to_phy(encoder); 1636 1637 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1638 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1639 } 1640 1641 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1642 { 1643 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1644 enum phy phy = intel_encoder_to_phy(encoder); 1645 1646 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1647 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1648 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1649 } 1650 1651 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1652 const struct intel_crtc_state *crtc_state) 1653 { 1654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1655 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 1658 if (drm_WARN_ON(&i915->drm, !pll)) 1659 return; 1660 1661 /* 1662 * If we fail this, something went very wrong: first 2 PLLs should be 1663 * used by first 2 phys and last 2 PLLs by last phys 1664 */ 1665 if (drm_WARN_ON(&i915->drm, 1666 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1667 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1668 return; 1669 1670 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1671 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1672 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1673 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1674 } 1675 1676 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1677 { 1678 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1679 enum phy phy = intel_encoder_to_phy(encoder); 1680 1681 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1682 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1683 } 1684 1685 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1686 { 1687 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1688 enum phy phy = intel_encoder_to_phy(encoder); 1689 1690 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1691 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1692 } 1693 1694 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1695 { 1696 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1697 enum phy phy = intel_encoder_to_phy(encoder); 1698 enum intel_dpll_id id; 1699 u32 val; 1700 1701 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1702 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1703 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1704 id = val; 1705 1706 /* 1707 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1708 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1709 * bit for phy C and D. 1710 */ 1711 if (phy >= PHY_C) 1712 id += DPLL_ID_DG1_DPLL2; 1713 1714 return intel_get_shared_dpll_by_id(i915, id); 1715 } 1716 1717 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1718 const struct intel_crtc_state *crtc_state) 1719 { 1720 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1721 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1722 enum phy phy = intel_encoder_to_phy(encoder); 1723 1724 if (drm_WARN_ON(&i915->drm, !pll)) 1725 return; 1726 1727 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1728 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1729 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1730 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1731 } 1732 1733 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1734 { 1735 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1736 enum phy phy = intel_encoder_to_phy(encoder); 1737 1738 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1739 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1740 } 1741 1742 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1743 { 1744 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1745 enum phy phy = intel_encoder_to_phy(encoder); 1746 1747 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1748 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1749 } 1750 1751 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1752 { 1753 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1754 enum phy phy = intel_encoder_to_phy(encoder); 1755 1756 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1757 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1758 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1759 } 1760 1761 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1762 const struct intel_crtc_state *crtc_state) 1763 { 1764 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1765 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1766 enum port port = encoder->port; 1767 1768 if (drm_WARN_ON(&i915->drm, !pll)) 1769 return; 1770 1771 /* 1772 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1773 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1774 */ 1775 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1776 1777 icl_ddi_combo_enable_clock(encoder, crtc_state); 1778 } 1779 1780 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1781 { 1782 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1783 enum port port = encoder->port; 1784 1785 icl_ddi_combo_disable_clock(encoder); 1786 1787 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1788 } 1789 1790 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1791 { 1792 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1793 enum port port = encoder->port; 1794 u32 tmp; 1795 1796 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1797 1798 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1799 return false; 1800 1801 return icl_ddi_combo_is_clock_enabled(encoder); 1802 } 1803 1804 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1805 const struct intel_crtc_state *crtc_state) 1806 { 1807 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1808 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1809 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1810 enum port port = encoder->port; 1811 1812 if (drm_WARN_ON(&i915->drm, !pll)) 1813 return; 1814 1815 intel_de_write(i915, DDI_CLK_SEL(port), 1816 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1817 1818 mutex_lock(&i915->display.dpll.lock); 1819 1820 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1821 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1822 1823 mutex_unlock(&i915->display.dpll.lock); 1824 } 1825 1826 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1827 { 1828 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1829 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1830 enum port port = encoder->port; 1831 1832 mutex_lock(&i915->display.dpll.lock); 1833 1834 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1835 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1836 1837 mutex_unlock(&i915->display.dpll.lock); 1838 1839 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1840 } 1841 1842 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1843 { 1844 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1845 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1846 enum port port = encoder->port; 1847 u32 tmp; 1848 1849 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1850 1851 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1852 return false; 1853 1854 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1855 1856 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1857 } 1858 1859 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1860 { 1861 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1862 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1863 enum port port = encoder->port; 1864 enum intel_dpll_id id; 1865 u32 tmp; 1866 1867 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1868 1869 switch (tmp & DDI_CLK_SEL_MASK) { 1870 case DDI_CLK_SEL_TBT_162: 1871 case DDI_CLK_SEL_TBT_270: 1872 case DDI_CLK_SEL_TBT_540: 1873 case DDI_CLK_SEL_TBT_810: 1874 id = DPLL_ID_ICL_TBTPLL; 1875 break; 1876 case DDI_CLK_SEL_MG: 1877 id = icl_tc_port_to_pll_id(tc_port); 1878 break; 1879 default: 1880 MISSING_CASE(tmp); 1881 fallthrough; 1882 case DDI_CLK_SEL_NONE: 1883 return NULL; 1884 } 1885 1886 return intel_get_shared_dpll_by_id(i915, id); 1887 } 1888 1889 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1890 { 1891 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1892 enum intel_dpll_id id; 1893 1894 switch (encoder->port) { 1895 case PORT_A: 1896 id = DPLL_ID_SKL_DPLL0; 1897 break; 1898 case PORT_B: 1899 id = DPLL_ID_SKL_DPLL1; 1900 break; 1901 case PORT_C: 1902 id = DPLL_ID_SKL_DPLL2; 1903 break; 1904 default: 1905 MISSING_CASE(encoder->port); 1906 return NULL; 1907 } 1908 1909 return intel_get_shared_dpll_by_id(i915, id); 1910 } 1911 1912 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1913 const struct intel_crtc_state *crtc_state) 1914 { 1915 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1916 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1917 enum port port = encoder->port; 1918 1919 if (drm_WARN_ON(&i915->drm, !pll)) 1920 return; 1921 1922 mutex_lock(&i915->display.dpll.lock); 1923 1924 intel_de_rmw(i915, DPLL_CTRL2, 1925 DPLL_CTRL2_DDI_CLK_OFF(port) | 1926 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1927 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1928 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1929 1930 mutex_unlock(&i915->display.dpll.lock); 1931 } 1932 1933 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1934 { 1935 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1936 enum port port = encoder->port; 1937 1938 mutex_lock(&i915->display.dpll.lock); 1939 1940 intel_de_rmw(i915, DPLL_CTRL2, 1941 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1942 1943 mutex_unlock(&i915->display.dpll.lock); 1944 } 1945 1946 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1947 { 1948 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1949 enum port port = encoder->port; 1950 1951 /* 1952 * FIXME Not sure if the override affects both 1953 * the PLL selection and the CLK_OFF bit. 1954 */ 1955 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1956 } 1957 1958 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1959 { 1960 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1961 enum port port = encoder->port; 1962 enum intel_dpll_id id; 1963 u32 tmp; 1964 1965 tmp = intel_de_read(i915, DPLL_CTRL2); 1966 1967 /* 1968 * FIXME Not sure if the override affects both 1969 * the PLL selection and the CLK_OFF bit. 1970 */ 1971 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1972 return NULL; 1973 1974 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1975 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1976 1977 return intel_get_shared_dpll_by_id(i915, id); 1978 } 1979 1980 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1981 const struct intel_crtc_state *crtc_state) 1982 { 1983 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1984 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1985 enum port port = encoder->port; 1986 1987 if (drm_WARN_ON(&i915->drm, !pll)) 1988 return; 1989 1990 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1991 } 1992 1993 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1994 { 1995 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1996 enum port port = encoder->port; 1997 1998 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1999 } 2000 2001 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2002 { 2003 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2004 enum port port = encoder->port; 2005 2006 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2007 } 2008 2009 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2010 { 2011 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2012 enum port port = encoder->port; 2013 enum intel_dpll_id id; 2014 u32 tmp; 2015 2016 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2017 2018 switch (tmp & PORT_CLK_SEL_MASK) { 2019 case PORT_CLK_SEL_WRPLL1: 2020 id = DPLL_ID_WRPLL1; 2021 break; 2022 case PORT_CLK_SEL_WRPLL2: 2023 id = DPLL_ID_WRPLL2; 2024 break; 2025 case PORT_CLK_SEL_SPLL: 2026 id = DPLL_ID_SPLL; 2027 break; 2028 case PORT_CLK_SEL_LCPLL_810: 2029 id = DPLL_ID_LCPLL_810; 2030 break; 2031 case PORT_CLK_SEL_LCPLL_1350: 2032 id = DPLL_ID_LCPLL_1350; 2033 break; 2034 case PORT_CLK_SEL_LCPLL_2700: 2035 id = DPLL_ID_LCPLL_2700; 2036 break; 2037 default: 2038 MISSING_CASE(tmp); 2039 fallthrough; 2040 case PORT_CLK_SEL_NONE: 2041 return NULL; 2042 } 2043 2044 return intel_get_shared_dpll_by_id(i915, id); 2045 } 2046 2047 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2048 const struct intel_crtc_state *crtc_state) 2049 { 2050 if (encoder->enable_clock) 2051 encoder->enable_clock(encoder, crtc_state); 2052 } 2053 2054 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2055 { 2056 if (encoder->disable_clock) 2057 encoder->disable_clock(encoder); 2058 } 2059 2060 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2061 { 2062 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2063 u32 port_mask; 2064 bool ddi_clk_needed; 2065 2066 /* 2067 * In case of DP MST, we sanitize the primary encoder only, not the 2068 * virtual ones. 2069 */ 2070 if (encoder->type == INTEL_OUTPUT_DP_MST) 2071 return; 2072 2073 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2074 u8 pipe_mask; 2075 bool is_mst; 2076 2077 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2078 /* 2079 * In the unlikely case that BIOS enables DP in MST mode, just 2080 * warn since our MST HW readout is incomplete. 2081 */ 2082 if (drm_WARN_ON(&i915->drm, is_mst)) 2083 return; 2084 } 2085 2086 port_mask = BIT(encoder->port); 2087 ddi_clk_needed = encoder->base.crtc; 2088 2089 if (encoder->type == INTEL_OUTPUT_DSI) { 2090 struct intel_encoder *other_encoder; 2091 2092 port_mask = intel_dsi_encoder_ports(encoder); 2093 /* 2094 * Sanity check that we haven't incorrectly registered another 2095 * encoder using any of the ports of this DSI encoder. 2096 */ 2097 for_each_intel_encoder(&i915->drm, other_encoder) { 2098 if (other_encoder == encoder) 2099 continue; 2100 2101 if (drm_WARN_ON(&i915->drm, 2102 port_mask & BIT(other_encoder->port))) 2103 return; 2104 } 2105 /* 2106 * For DSI we keep the ddi clocks gated 2107 * except during enable/disable sequence. 2108 */ 2109 ddi_clk_needed = false; 2110 } 2111 2112 if (ddi_clk_needed || !encoder->is_clock_enabled || 2113 !encoder->is_clock_enabled(encoder)) 2114 return; 2115 2116 drm_dbg_kms(&i915->drm, 2117 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2118 encoder->base.base.id, encoder->base.name); 2119 2120 encoder->disable_clock(encoder); 2121 } 2122 2123 static void 2124 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2125 const struct intel_crtc_state *crtc_state) 2126 { 2127 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2128 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2129 u32 ln0, ln1, pin_assignment; 2130 u8 width; 2131 2132 if (DISPLAY_VER(dev_priv) >= 14) 2133 return; 2134 2135 if (!intel_encoder_is_tc(&dig_port->base) || 2136 intel_tc_port_in_tbt_alt_mode(dig_port)) 2137 return; 2138 2139 if (DISPLAY_VER(dev_priv) >= 12) { 2140 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2141 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2142 } else { 2143 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2144 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2145 } 2146 2147 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2148 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2149 2150 /* DPPATC */ 2151 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2152 width = crtc_state->lane_count; 2153 2154 switch (pin_assignment) { 2155 case 0x0: 2156 drm_WARN_ON(&dev_priv->drm, 2157 !intel_tc_port_in_legacy_mode(dig_port)); 2158 if (width == 1) { 2159 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2160 } else { 2161 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2162 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2163 } 2164 break; 2165 case 0x1: 2166 if (width == 4) { 2167 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2168 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2169 } 2170 break; 2171 case 0x2: 2172 if (width == 2) { 2173 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2174 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2175 } 2176 break; 2177 case 0x3: 2178 case 0x5: 2179 if (width == 1) { 2180 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2181 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2182 } else { 2183 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2184 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2185 } 2186 break; 2187 case 0x4: 2188 case 0x6: 2189 if (width == 1) { 2190 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2191 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2192 } else { 2193 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2194 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2195 } 2196 break; 2197 default: 2198 MISSING_CASE(pin_assignment); 2199 } 2200 2201 if (DISPLAY_VER(dev_priv) >= 12) { 2202 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2203 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2204 } else { 2205 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2206 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2207 } 2208 } 2209 2210 static enum transcoder 2211 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2212 { 2213 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2214 return crtc_state->mst_master_transcoder; 2215 else 2216 return crtc_state->cpu_transcoder; 2217 } 2218 2219 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2220 const struct intel_crtc_state *crtc_state) 2221 { 2222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2223 2224 if (DISPLAY_VER(dev_priv) >= 12) 2225 return TGL_DP_TP_CTL(dev_priv, 2226 tgl_dp_tp_transcoder(crtc_state)); 2227 else 2228 return DP_TP_CTL(encoder->port); 2229 } 2230 2231 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2232 const struct intel_crtc_state *crtc_state) 2233 { 2234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2235 2236 if (DISPLAY_VER(dev_priv) >= 12) 2237 return TGL_DP_TP_STATUS(dev_priv, 2238 tgl_dp_tp_transcoder(crtc_state)); 2239 else 2240 return DP_TP_STATUS(encoder->port); 2241 } 2242 2243 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2244 const struct intel_crtc_state *crtc_state) 2245 { 2246 struct intel_display *display = to_intel_display(encoder); 2247 2248 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2249 DP_TP_STATUS_ACT_SENT); 2250 } 2251 2252 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2253 const struct intel_crtc_state *crtc_state) 2254 { 2255 struct intel_display *display = to_intel_display(encoder); 2256 2257 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2258 DP_TP_STATUS_ACT_SENT, 1)) 2259 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2260 } 2261 2262 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2263 const struct intel_crtc_state *crtc_state, 2264 bool enable) 2265 { 2266 struct intel_display *display = to_intel_display(intel_dp); 2267 2268 if (!crtc_state->vrr.enable) 2269 return; 2270 2271 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2272 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2273 drm_dbg_kms(display->drm, 2274 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2275 str_enable_disable(enable)); 2276 } 2277 2278 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2279 const struct intel_crtc_state *crtc_state, 2280 bool enable) 2281 { 2282 struct intel_display *display = to_intel_display(intel_dp); 2283 2284 if (!crtc_state->fec_enable) 2285 return; 2286 2287 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2288 enable ? DP_FEC_READY : 0) <= 0) 2289 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2290 str_enabled_disabled(enable)); 2291 2292 if (enable && 2293 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2294 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2295 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2296 } 2297 2298 static int read_fec_detected_status(struct drm_dp_aux *aux) 2299 { 2300 int ret; 2301 u8 status; 2302 2303 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2304 if (ret < 0) 2305 return ret; 2306 2307 return status; 2308 } 2309 2310 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2311 { 2312 struct intel_display *display = to_intel_display(aux->drm_dev); 2313 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2314 int status; 2315 int err; 2316 2317 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2318 status & mask || status < 0, 2319 10000, 200000); 2320 2321 if (err || status < 0) { 2322 drm_dbg_kms(display->drm, 2323 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2324 str_enabled_disabled(enabled), err, status); 2325 return err ? err : status; 2326 } 2327 2328 return 0; 2329 } 2330 2331 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2332 const struct intel_crtc_state *crtc_state, 2333 bool enabled) 2334 { 2335 struct intel_display *display = to_intel_display(encoder); 2336 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2337 int ret; 2338 2339 if (!crtc_state->fec_enable) 2340 return 0; 2341 2342 if (enabled) 2343 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2344 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2345 else 2346 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2347 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2348 2349 if (ret) { 2350 drm_err(display->drm, 2351 "Timeout waiting for FEC live state to get %s\n", 2352 str_enabled_disabled(enabled)); 2353 return ret; 2354 } 2355 /* 2356 * At least the Synoptics MST hub doesn't set the detected flag for 2357 * FEC decoding disabling so skip waiting for that. 2358 */ 2359 if (enabled) { 2360 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2361 if (ret) 2362 return ret; 2363 } 2364 2365 return 0; 2366 } 2367 2368 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2369 const struct intel_crtc_state *crtc_state) 2370 { 2371 struct intel_display *display = to_intel_display(encoder); 2372 int i; 2373 int ret; 2374 2375 if (!crtc_state->fec_enable) 2376 return; 2377 2378 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2379 0, DP_TP_CTL_FEC_ENABLE); 2380 2381 if (DISPLAY_VER(display) < 30) 2382 return; 2383 2384 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2385 if (!ret) 2386 return; 2387 2388 for (i = 0; i < 3; i++) { 2389 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2390 2391 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2392 DP_TP_CTL_FEC_ENABLE, 0); 2393 2394 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2395 if (ret) 2396 continue; 2397 2398 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2399 0, DP_TP_CTL_FEC_ENABLE); 2400 2401 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2402 if (!ret) 2403 return; 2404 } 2405 2406 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2407 } 2408 2409 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2410 const struct intel_crtc_state *crtc_state) 2411 { 2412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2413 2414 if (!crtc_state->fec_enable) 2415 return; 2416 2417 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2418 DP_TP_CTL_FEC_ENABLE, 0); 2419 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2420 } 2421 2422 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2423 const struct intel_crtc_state *crtc_state) 2424 { 2425 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2426 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2427 2428 if (intel_encoder_is_combo(encoder)) { 2429 enum phy phy = intel_encoder_to_phy(encoder); 2430 2431 intel_combo_phy_power_up_lanes(i915, phy, false, 2432 crtc_state->lane_count, 2433 dig_port->lane_reversal); 2434 } 2435 } 2436 2437 /* 2438 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2439 * platforms. 2440 */ 2441 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2442 { 2443 if (DISPLAY_VER(i915) > 20) 2444 return ~0; 2445 else if (IS_ALDERLAKE_P(i915)) 2446 return BIT(PIPE_A) | BIT(PIPE_B); 2447 else 2448 return BIT(PIPE_A); 2449 } 2450 2451 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2452 struct intel_crtc_state *pipe_config) 2453 { 2454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2455 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2456 enum pipe pipe = crtc->pipe; 2457 u32 dss1; 2458 2459 if (!HAS_MSO(i915)) 2460 return; 2461 2462 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2463 2464 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2465 if (!pipe_config->splitter.enable) 2466 return; 2467 2468 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2469 pipe_config->splitter.enable = false; 2470 return; 2471 } 2472 2473 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2474 default: 2475 drm_WARN(&i915->drm, true, 2476 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2477 fallthrough; 2478 case SPLITTER_CONFIGURATION_2_SEGMENT: 2479 pipe_config->splitter.link_count = 2; 2480 break; 2481 case SPLITTER_CONFIGURATION_4_SEGMENT: 2482 pipe_config->splitter.link_count = 4; 2483 break; 2484 } 2485 2486 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2487 } 2488 2489 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2490 { 2491 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2492 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2493 enum pipe pipe = crtc->pipe; 2494 u32 dss1 = 0; 2495 2496 if (!HAS_MSO(i915)) 2497 return; 2498 2499 if (crtc_state->splitter.enable) { 2500 dss1 |= SPLITTER_ENABLE; 2501 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2502 if (crtc_state->splitter.link_count == 2) 2503 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2504 else 2505 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2506 } 2507 2508 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2509 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2510 OVERLAP_PIXELS_MASK, dss1); 2511 } 2512 2513 static u8 mtl_get_port_width(u8 lane_count) 2514 { 2515 switch (lane_count) { 2516 case 1: 2517 return 0; 2518 case 2: 2519 return 1; 2520 case 3: 2521 return 4; 2522 case 4: 2523 return 3; 2524 default: 2525 MISSING_CASE(lane_count); 2526 return 4; 2527 } 2528 } 2529 2530 static void 2531 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2532 { 2533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2534 enum port port = encoder->port; 2535 i915_reg_t reg; 2536 u32 set_bits, wait_bits; 2537 2538 if (DISPLAY_VER(dev_priv) >= 20) { 2539 reg = DDI_BUF_CTL(port); 2540 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2541 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2542 } else { 2543 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2544 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2545 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2546 } 2547 2548 intel_de_rmw(dev_priv, reg, 0, set_bits); 2549 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2550 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2551 port_name(port)); 2552 } 2553 } 2554 2555 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2556 const struct intel_crtc_state *crtc_state) 2557 { 2558 struct intel_display *display = to_intel_display(encoder); 2559 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2560 enum port port = encoder->port; 2561 u32 val = 0; 2562 2563 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2564 2565 if (intel_dp_is_uhbr(crtc_state)) 2566 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2567 else 2568 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2569 2570 if (dig_port->lane_reversal) 2571 val |= XELPDP_PORT_REVERSAL; 2572 2573 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2574 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2575 val); 2576 } 2577 2578 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2579 { 2580 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2581 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2582 u32 val; 2583 2584 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2585 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2586 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2587 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2588 } 2589 2590 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2591 struct intel_encoder *encoder, 2592 const struct intel_crtc_state *crtc_state, 2593 const struct drm_connector_state *conn_state) 2594 { 2595 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2596 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2597 int ret; 2598 2599 intel_dp_set_link_params(intel_dp, 2600 crtc_state->port_clock, 2601 crtc_state->lane_count); 2602 2603 /* 2604 * We only configure what the register value will be here. Actual 2605 * enabling happens during link training farther down. 2606 */ 2607 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2608 2609 /* 2610 * 1. Enable Power Wells 2611 * 2612 * This was handled at the beginning of intel_atomic_commit_tail(), 2613 * before we called down into this function. 2614 */ 2615 2616 /* 2. PMdemand was already set */ 2617 2618 /* 3. Select Thunderbolt */ 2619 mtl_port_buf_ctl_io_selection(encoder); 2620 2621 /* 4. Enable Panel Power if PPS is required */ 2622 intel_pps_on(intel_dp); 2623 2624 /* 5. Enable the port PLL */ 2625 intel_ddi_enable_clock(encoder, crtc_state); 2626 2627 /* 2628 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2629 * Transcoder. 2630 */ 2631 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2632 2633 /* 2634 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2635 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2636 * Transport Select 2637 */ 2638 intel_ddi_config_transcoder_func(encoder, crtc_state); 2639 2640 /* 2641 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2642 */ 2643 intel_ddi_mso_configure(crtc_state); 2644 2645 if (!is_mst) 2646 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2647 2648 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2649 if (!is_mst) 2650 intel_dp_sink_enable_decompression(state, 2651 to_intel_connector(conn_state->connector), 2652 crtc_state); 2653 2654 /* 2655 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2656 * in the FEC_CONFIGURATION register to 1 before initiating link 2657 * training 2658 */ 2659 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2660 2661 intel_dp_check_frl_training(intel_dp); 2662 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2663 2664 /* 2665 * 6. The rest of the below are substeps under the bspec's "Enable and 2666 * Train Display Port" step. Note that steps that are specific to 2667 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2668 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2669 * us when active_mst_links==0, so any steps designated for "single 2670 * stream or multi-stream master transcoder" can just be performed 2671 * unconditionally here. 2672 * 2673 * mtl_ddi_prepare_link_retrain() that is called by 2674 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2675 * 6.i and 6.j 2676 * 2677 * 6.k Follow DisplayPort specification training sequence (see notes for 2678 * failure handling) 2679 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2680 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2681 * (timeout after 800 us) 2682 */ 2683 intel_dp_start_link_train(state, intel_dp, crtc_state); 2684 2685 /* 6.n Set DP_TP_CTL link training to Normal */ 2686 if (!is_trans_port_sync_mode(crtc_state)) 2687 intel_dp_stop_link_train(intel_dp, crtc_state); 2688 2689 /* 6.o Configure and enable FEC if needed */ 2690 intel_ddi_enable_fec(encoder, crtc_state); 2691 2692 /* 7.a 128b/132b SST. */ 2693 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2694 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2695 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2696 if (ret < 0) 2697 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2698 } 2699 2700 if (!is_mst) 2701 intel_dsc_dp_pps_write(encoder, crtc_state); 2702 } 2703 2704 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2705 struct intel_encoder *encoder, 2706 const struct intel_crtc_state *crtc_state, 2707 const struct drm_connector_state *conn_state) 2708 { 2709 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2710 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2711 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2712 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2713 int ret; 2714 2715 intel_dp_set_link_params(intel_dp, 2716 crtc_state->port_clock, 2717 crtc_state->lane_count); 2718 2719 /* 2720 * We only configure what the register value will be here. Actual 2721 * enabling happens during link training farther down. 2722 */ 2723 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2724 2725 /* 2726 * 1. Enable Power Wells 2727 * 2728 * This was handled at the beginning of intel_atomic_commit_tail(), 2729 * before we called down into this function. 2730 */ 2731 2732 /* 2. Enable Panel Power if PPS is required */ 2733 intel_pps_on(intel_dp); 2734 2735 /* 2736 * 3. For non-TBT Type-C ports, set FIA lane count 2737 * (DFLEXDPSP.DPX4TXLATC) 2738 * 2739 * This was done before tgl_ddi_pre_enable_dp by 2740 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2741 */ 2742 2743 /* 2744 * 4. Enable the port PLL. 2745 * 2746 * The PLL enabling itself was already done before this function by 2747 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2748 * configure the PLL to port mapping here. 2749 */ 2750 intel_ddi_enable_clock(encoder, crtc_state); 2751 2752 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2753 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2754 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2755 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2756 dig_port->ddi_io_power_domain); 2757 } 2758 2759 /* 6. Program DP_MODE */ 2760 icl_program_mg_dp_mode(dig_port, crtc_state); 2761 2762 /* 2763 * 7. The rest of the below are substeps under the bspec's "Enable and 2764 * Train Display Port" step. Note that steps that are specific to 2765 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2766 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2767 * us when active_mst_links==0, so any steps designated for "single 2768 * stream or multi-stream master transcoder" can just be performed 2769 * unconditionally here. 2770 */ 2771 2772 /* 2773 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2774 * Transcoder. 2775 */ 2776 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2777 2778 /* 2779 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2780 * Transport Select 2781 */ 2782 intel_ddi_config_transcoder_func(encoder, crtc_state); 2783 2784 /* 2785 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2786 * selected 2787 * 2788 * This will be handled by the intel_dp_start_link_train() farther 2789 * down this function. 2790 */ 2791 2792 /* 7.e Configure voltage swing and related IO settings */ 2793 encoder->set_signal_levels(encoder, crtc_state); 2794 2795 /* 2796 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2797 * the used lanes of the DDI. 2798 */ 2799 intel_ddi_power_up_lanes(encoder, crtc_state); 2800 2801 /* 2802 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2803 */ 2804 intel_ddi_mso_configure(crtc_state); 2805 2806 if (!is_mst) 2807 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2808 2809 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2810 if (!is_mst) 2811 intel_dp_sink_enable_decompression(state, 2812 to_intel_connector(conn_state->connector), 2813 crtc_state); 2814 /* 2815 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2816 * in the FEC_CONFIGURATION register to 1 before initiating link 2817 * training 2818 */ 2819 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2820 2821 intel_dp_check_frl_training(intel_dp); 2822 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2823 2824 /* 2825 * 7.i Follow DisplayPort specification training sequence (see notes for 2826 * failure handling) 2827 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2828 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2829 * (timeout after 800 us) 2830 */ 2831 intel_dp_start_link_train(state, intel_dp, crtc_state); 2832 2833 /* 7.k Set DP_TP_CTL link training to Normal */ 2834 if (!is_trans_port_sync_mode(crtc_state)) 2835 intel_dp_stop_link_train(intel_dp, crtc_state); 2836 2837 /* 7.l Configure and enable FEC if needed */ 2838 intel_ddi_enable_fec(encoder, crtc_state); 2839 2840 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2841 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2842 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2843 if (ret < 0) 2844 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2845 } 2846 2847 if (!is_mst) 2848 intel_dsc_dp_pps_write(encoder, crtc_state); 2849 } 2850 2851 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2852 struct intel_encoder *encoder, 2853 const struct intel_crtc_state *crtc_state, 2854 const struct drm_connector_state *conn_state) 2855 { 2856 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2857 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2858 enum port port = encoder->port; 2859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2860 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2861 2862 if (DISPLAY_VER(dev_priv) < 11) 2863 drm_WARN_ON(&dev_priv->drm, 2864 is_mst && (port == PORT_A || port == PORT_E)); 2865 else 2866 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2867 2868 intel_dp_set_link_params(intel_dp, 2869 crtc_state->port_clock, 2870 crtc_state->lane_count); 2871 2872 /* 2873 * We only configure what the register value will be here. Actual 2874 * enabling happens during link training farther down. 2875 */ 2876 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2877 2878 intel_pps_on(intel_dp); 2879 2880 intel_ddi_enable_clock(encoder, crtc_state); 2881 2882 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2883 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2884 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2885 dig_port->ddi_io_power_domain); 2886 } 2887 2888 icl_program_mg_dp_mode(dig_port, crtc_state); 2889 2890 if (has_buf_trans_select(dev_priv)) 2891 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2892 2893 encoder->set_signal_levels(encoder, crtc_state); 2894 2895 intel_ddi_power_up_lanes(encoder, crtc_state); 2896 2897 if (!is_mst) 2898 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2899 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2900 if (!is_mst) 2901 intel_dp_sink_enable_decompression(state, 2902 to_intel_connector(conn_state->connector), 2903 crtc_state); 2904 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2905 intel_dp_start_link_train(state, intel_dp, crtc_state); 2906 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2907 !is_trans_port_sync_mode(crtc_state)) 2908 intel_dp_stop_link_train(intel_dp, crtc_state); 2909 2910 intel_ddi_enable_fec(encoder, crtc_state); 2911 2912 if (!is_mst) { 2913 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2914 intel_dsc_dp_pps_write(encoder, crtc_state); 2915 } 2916 } 2917 2918 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2919 struct intel_encoder *encoder, 2920 const struct intel_crtc_state *crtc_state, 2921 const struct drm_connector_state *conn_state) 2922 { 2923 struct intel_display *display = to_intel_display(encoder); 2924 2925 if (HAS_DP20(display)) 2926 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2927 crtc_state); 2928 2929 /* Panel replay has to be enabled in sink dpcd before link training. */ 2930 if (crtc_state->has_panel_replay) 2931 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2932 2933 if (DISPLAY_VER(display) >= 14) 2934 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2935 else if (DISPLAY_VER(display) >= 12) 2936 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2937 else 2938 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2939 2940 /* MST will call a setting of MSA after an allocating of Virtual Channel 2941 * from MST encoder pre_enable callback. 2942 */ 2943 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2944 intel_ddi_set_dp_msa(crtc_state, conn_state); 2945 } 2946 2947 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2948 struct intel_encoder *encoder, 2949 const struct intel_crtc_state *crtc_state, 2950 const struct drm_connector_state *conn_state) 2951 { 2952 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2953 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2955 2956 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2957 intel_ddi_enable_clock(encoder, crtc_state); 2958 2959 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2960 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2961 dig_port->ddi_io_power_domain); 2962 2963 icl_program_mg_dp_mode(dig_port, crtc_state); 2964 2965 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2966 2967 dig_port->set_infoframes(encoder, 2968 crtc_state->has_infoframe, 2969 crtc_state, conn_state); 2970 } 2971 2972 /* 2973 * Note: Also called from the ->pre_enable of the first active MST stream 2974 * encoder on its primary encoder. 2975 * 2976 * When called from DP MST code: 2977 * 2978 * - conn_state will be NULL 2979 * 2980 * - encoder will be the primary encoder (i.e. mst->primary) 2981 * 2982 * - the main connector associated with this port won't be active or linked to a 2983 * crtc 2984 * 2985 * - crtc_state will be the state of the first stream to be activated on this 2986 * port, and it may not be the same stream that will be deactivated last, but 2987 * each stream should have a state that is identical when it comes to the DP 2988 * link parameteres 2989 */ 2990 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2991 struct intel_encoder *encoder, 2992 const struct intel_crtc_state *crtc_state, 2993 const struct drm_connector_state *conn_state) 2994 { 2995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2996 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2997 enum pipe pipe = crtc->pipe; 2998 2999 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3000 3001 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3002 3003 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3004 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3005 conn_state); 3006 } else { 3007 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3008 3009 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3010 conn_state); 3011 3012 /* FIXME precompute everything properly */ 3013 /* FIXME how do we turn infoframes off again? */ 3014 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3015 dig_port->set_infoframes(encoder, 3016 crtc_state->has_infoframe, 3017 crtc_state, conn_state); 3018 } 3019 } 3020 3021 static void 3022 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 3023 { 3024 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3025 enum port port = encoder->port; 3026 i915_reg_t reg; 3027 u32 clr_bits, wait_bits; 3028 3029 if (DISPLAY_VER(dev_priv) >= 20) { 3030 reg = DDI_BUF_CTL(port); 3031 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3032 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3033 } else { 3034 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 3035 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3036 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3037 } 3038 3039 intel_de_rmw(dev_priv, reg, clr_bits, 0); 3040 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 3041 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3042 port_name(port)); 3043 } 3044 3045 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 3046 const struct intel_crtc_state *crtc_state) 3047 { 3048 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3049 enum port port = encoder->port; 3050 u32 val; 3051 3052 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 3053 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3054 if (val & DDI_BUF_CTL_ENABLE) { 3055 val &= ~DDI_BUF_CTL_ENABLE; 3056 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3057 3058 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 3059 mtl_wait_ddi_buf_idle(dev_priv, port); 3060 } 3061 3062 /* 3.d Disable D2D Link */ 3063 mtl_ddi_disable_d2d_link(encoder); 3064 3065 /* 3.e Disable DP_TP_CTL */ 3066 if (intel_crtc_has_dp_encoder(crtc_state)) { 3067 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3068 DP_TP_CTL_ENABLE, 0); 3069 } 3070 } 3071 3072 static void disable_ddi_buf(struct intel_encoder *encoder, 3073 const struct intel_crtc_state *crtc_state) 3074 { 3075 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3076 enum port port = encoder->port; 3077 bool wait = false; 3078 u32 val; 3079 3080 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3081 if (val & DDI_BUF_CTL_ENABLE) { 3082 val &= ~DDI_BUF_CTL_ENABLE; 3083 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3084 wait = true; 3085 } 3086 3087 if (intel_crtc_has_dp_encoder(crtc_state)) 3088 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3089 DP_TP_CTL_ENABLE, 0); 3090 3091 intel_ddi_disable_fec(encoder, crtc_state); 3092 3093 if (wait) 3094 intel_wait_ddi_buf_idle(dev_priv, port); 3095 } 3096 3097 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3098 const struct intel_crtc_state *crtc_state) 3099 { 3100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3101 3102 if (DISPLAY_VER(dev_priv) >= 14) { 3103 mtl_disable_ddi_buf(encoder, crtc_state); 3104 3105 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3106 intel_ddi_disable_fec(encoder, crtc_state); 3107 } else { 3108 disable_ddi_buf(encoder, crtc_state); 3109 } 3110 3111 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3112 } 3113 3114 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3115 struct intel_encoder *encoder, 3116 const struct intel_crtc_state *old_crtc_state, 3117 const struct drm_connector_state *old_conn_state) 3118 { 3119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3120 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3121 struct intel_dp *intel_dp = &dig_port->dp; 3122 intel_wakeref_t wakeref; 3123 bool is_mst = intel_crtc_has_type(old_crtc_state, 3124 INTEL_OUTPUT_DP_MST); 3125 3126 if (!is_mst) 3127 intel_dp_set_infoframes(encoder, false, 3128 old_crtc_state, old_conn_state); 3129 3130 /* 3131 * Power down sink before disabling the port, otherwise we end 3132 * up getting interrupts from the sink on detecting link loss. 3133 */ 3134 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3135 3136 if (DISPLAY_VER(dev_priv) >= 12) { 3137 if (is_mst) { 3138 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3139 3140 intel_de_rmw(dev_priv, 3141 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3142 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3143 0); 3144 } 3145 } else { 3146 if (!is_mst) 3147 intel_ddi_disable_transcoder_clock(old_crtc_state); 3148 } 3149 3150 intel_disable_ddi_buf(encoder, old_crtc_state); 3151 3152 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3153 3154 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3155 3156 /* 3157 * From TGL spec: "If single stream or multi-stream master transcoder: 3158 * Configure Transcoder Clock select to direct no clock to the 3159 * transcoder" 3160 */ 3161 if (DISPLAY_VER(dev_priv) >= 12) 3162 intel_ddi_disable_transcoder_clock(old_crtc_state); 3163 3164 intel_pps_vdd_on(intel_dp); 3165 intel_pps_off(intel_dp); 3166 3167 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3168 3169 if (wakeref) 3170 intel_display_power_put(dev_priv, 3171 dig_port->ddi_io_power_domain, 3172 wakeref); 3173 3174 intel_ddi_disable_clock(encoder); 3175 3176 /* De-select Thunderbolt */ 3177 if (DISPLAY_VER(dev_priv) >= 14) 3178 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3179 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3180 } 3181 3182 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3183 struct intel_encoder *encoder, 3184 const struct intel_crtc_state *old_crtc_state, 3185 const struct drm_connector_state *old_conn_state) 3186 { 3187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3188 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3189 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3190 intel_wakeref_t wakeref; 3191 3192 dig_port->set_infoframes(encoder, false, 3193 old_crtc_state, old_conn_state); 3194 3195 if (DISPLAY_VER(dev_priv) < 12) 3196 intel_ddi_disable_transcoder_clock(old_crtc_state); 3197 3198 intel_disable_ddi_buf(encoder, old_crtc_state); 3199 3200 if (DISPLAY_VER(dev_priv) >= 12) 3201 intel_ddi_disable_transcoder_clock(old_crtc_state); 3202 3203 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3204 if (wakeref) 3205 intel_display_power_put(dev_priv, 3206 dig_port->ddi_io_power_domain, 3207 wakeref); 3208 3209 intel_ddi_disable_clock(encoder); 3210 3211 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3212 } 3213 3214 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3215 struct intel_encoder *encoder, 3216 const struct intel_crtc_state *old_crtc_state, 3217 const struct drm_connector_state *old_conn_state) 3218 { 3219 struct intel_display *display = to_intel_display(encoder); 3220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3221 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3222 struct intel_crtc *pipe_crtc; 3223 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3224 int i; 3225 3226 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3227 const struct intel_crtc_state *old_pipe_crtc_state = 3228 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3229 3230 intel_crtc_vblank_off(old_pipe_crtc_state); 3231 } 3232 3233 intel_disable_transcoder(old_crtc_state); 3234 3235 /* 128b/132b SST */ 3236 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3237 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3238 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3239 3240 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3241 3242 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3243 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3244 3245 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3246 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3247 } 3248 3249 intel_ddi_disable_transcoder_func(old_crtc_state); 3250 3251 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3252 const struct intel_crtc_state *old_pipe_crtc_state = 3253 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3254 3255 intel_dsc_disable(old_pipe_crtc_state); 3256 3257 if (DISPLAY_VER(dev_priv) >= 9) 3258 skl_scaler_disable(old_pipe_crtc_state); 3259 else 3260 ilk_pfit_disable(old_pipe_crtc_state); 3261 } 3262 } 3263 3264 /* 3265 * Note: Also called from the ->post_disable of the last active MST stream 3266 * encoder on its primary encoder. See also the comment for 3267 * intel_ddi_pre_enable(). 3268 */ 3269 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3270 struct intel_encoder *encoder, 3271 const struct intel_crtc_state *old_crtc_state, 3272 const struct drm_connector_state *old_conn_state) 3273 { 3274 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3275 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3276 old_conn_state); 3277 3278 /* 3279 * When called from DP MST code: 3280 * - old_conn_state will be NULL 3281 * - encoder will be the main encoder (ie. mst->primary) 3282 * - the main connector associated with this port 3283 * won't be active or linked to a crtc 3284 * - old_crtc_state will be the state of the last stream to 3285 * be deactivated on this port, and it may not be the same 3286 * stream that was activated last, but each stream 3287 * should have a state that is identical when it comes to 3288 * the DP link parameteres 3289 */ 3290 3291 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3292 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3293 old_conn_state); 3294 else 3295 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3296 old_conn_state); 3297 } 3298 3299 /* 3300 * Note: Also called from the ->post_pll_disable of the last active MST stream 3301 * encoder on its primary encoder. See also the comment for 3302 * intel_ddi_pre_enable(). 3303 */ 3304 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3305 struct intel_encoder *encoder, 3306 const struct intel_crtc_state *old_crtc_state, 3307 const struct drm_connector_state *old_conn_state) 3308 { 3309 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3310 3311 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3312 3313 if (intel_encoder_is_tc(encoder)) 3314 intel_tc_port_put_link(dig_port); 3315 } 3316 3317 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3318 struct intel_encoder *encoder, 3319 const struct intel_crtc_state *crtc_state) 3320 { 3321 const struct drm_connector_state *conn_state; 3322 struct drm_connector *conn; 3323 int i; 3324 3325 if (!crtc_state->sync_mode_slaves_mask) 3326 return; 3327 3328 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3329 struct intel_encoder *slave_encoder = 3330 to_intel_encoder(conn_state->best_encoder); 3331 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3332 const struct intel_crtc_state *slave_crtc_state; 3333 3334 if (!slave_crtc) 3335 continue; 3336 3337 slave_crtc_state = 3338 intel_atomic_get_new_crtc_state(state, slave_crtc); 3339 3340 if (slave_crtc_state->master_transcoder != 3341 crtc_state->cpu_transcoder) 3342 continue; 3343 3344 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3345 slave_crtc_state); 3346 } 3347 3348 usleep_range(200, 400); 3349 3350 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3351 crtc_state); 3352 } 3353 3354 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3355 struct intel_encoder *encoder, 3356 const struct intel_crtc_state *crtc_state, 3357 const struct drm_connector_state *conn_state) 3358 { 3359 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3360 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3361 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3362 enum port port = encoder->port; 3363 3364 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3365 intel_dp_stop_link_train(intel_dp, crtc_state); 3366 3367 drm_connector_update_privacy_screen(conn_state); 3368 intel_edp_backlight_on(crtc_state, conn_state); 3369 3370 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3371 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3372 3373 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3374 } 3375 3376 static i915_reg_t 3377 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3378 { 3379 static const enum transcoder trans[] = { 3380 [PORT_A] = TRANSCODER_EDP, 3381 [PORT_B] = TRANSCODER_A, 3382 [PORT_C] = TRANSCODER_B, 3383 [PORT_D] = TRANSCODER_C, 3384 [PORT_E] = TRANSCODER_A, 3385 }; 3386 3387 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3388 3389 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3390 port = PORT_A; 3391 3392 return CHICKEN_TRANS(display, trans[port]); 3393 } 3394 3395 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3396 struct intel_encoder *encoder, 3397 const struct intel_crtc_state *crtc_state, 3398 const struct drm_connector_state *conn_state) 3399 { 3400 struct intel_display *display = to_intel_display(encoder); 3401 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3402 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3403 struct drm_connector *connector = conn_state->connector; 3404 enum port port = encoder->port; 3405 u32 buf_ctl; 3406 3407 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3408 crtc_state->hdmi_high_tmds_clock_ratio, 3409 crtc_state->hdmi_scrambling)) 3410 drm_dbg_kms(&dev_priv->drm, 3411 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3412 connector->base.id, connector->name); 3413 3414 if (has_buf_trans_select(dev_priv)) 3415 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3416 3417 /* e. Enable D2D Link for C10/C20 Phy */ 3418 if (DISPLAY_VER(dev_priv) >= 14) 3419 mtl_ddi_enable_d2d(encoder); 3420 3421 encoder->set_signal_levels(encoder, crtc_state); 3422 3423 /* Display WA #1143: skl,kbl,cfl */ 3424 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3425 /* 3426 * For some reason these chicken bits have been 3427 * stuffed into a transcoder register, event though 3428 * the bits affect a specific DDI port rather than 3429 * a specific transcoder. 3430 */ 3431 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3432 u32 val; 3433 3434 val = intel_de_read(dev_priv, reg); 3435 3436 if (port == PORT_E) 3437 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3438 DDIE_TRAINING_OVERRIDE_VALUE; 3439 else 3440 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3441 DDI_TRAINING_OVERRIDE_VALUE; 3442 3443 intel_de_write(dev_priv, reg, val); 3444 intel_de_posting_read(dev_priv, reg); 3445 3446 udelay(1); 3447 3448 if (port == PORT_E) 3449 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3450 DDIE_TRAINING_OVERRIDE_VALUE); 3451 else 3452 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3453 DDI_TRAINING_OVERRIDE_VALUE); 3454 3455 intel_de_write(dev_priv, reg, val); 3456 } 3457 3458 intel_ddi_power_up_lanes(encoder, crtc_state); 3459 3460 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3461 * are ignored so nothing special needs to be done besides 3462 * enabling the port. 3463 * 3464 * On ADL_P the PHY link rate and lane count must be programmed but 3465 * these are both 0 for HDMI. 3466 * 3467 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3468 * is filled with lane count, already set in the crtc_state. 3469 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3470 */ 3471 buf_ctl = DDI_BUF_CTL_ENABLE; 3472 3473 if (dig_port->lane_reversal) 3474 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3475 if (dig_port->ddi_a_4_lanes) 3476 buf_ctl |= DDI_A_4_LANES; 3477 3478 if (DISPLAY_VER(dev_priv) >= 14) { 3479 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3480 u32 port_buf = 0; 3481 3482 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3483 3484 if (dig_port->lane_reversal) 3485 port_buf |= XELPDP_PORT_REVERSAL; 3486 3487 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3488 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3489 3490 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3491 3492 if (DISPLAY_VER(dev_priv) >= 20) 3493 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3494 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3495 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3496 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3497 } 3498 3499 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3500 3501 intel_wait_ddi_buf_active(encoder); 3502 } 3503 3504 static void intel_ddi_enable(struct intel_atomic_state *state, 3505 struct intel_encoder *encoder, 3506 const struct intel_crtc_state *crtc_state, 3507 const struct drm_connector_state *conn_state) 3508 { 3509 struct intel_display *display = to_intel_display(encoder); 3510 struct intel_crtc *pipe_crtc; 3511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3512 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3513 int i; 3514 3515 /* 128b/132b SST */ 3516 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3517 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3518 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3519 3520 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3521 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3522 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3523 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3524 } 3525 3526 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3527 3528 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3529 intel_audio_sdp_split_update(crtc_state); 3530 3531 /* 128b/132b SST */ 3532 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3533 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3534 3535 intel_ddi_clear_act_sent(encoder, crtc_state); 3536 3537 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3538 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3539 3540 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3541 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3542 } 3543 3544 intel_enable_transcoder(crtc_state); 3545 3546 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3547 3548 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3549 const struct intel_crtc_state *pipe_crtc_state = 3550 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3551 3552 intel_crtc_vblank_on(pipe_crtc_state); 3553 } 3554 3555 if (is_hdmi) 3556 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3557 else 3558 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3559 3560 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3561 3562 } 3563 3564 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3565 struct intel_encoder *encoder, 3566 const struct intel_crtc_state *old_crtc_state, 3567 const struct drm_connector_state *old_conn_state) 3568 { 3569 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3570 struct intel_connector *connector = 3571 to_intel_connector(old_conn_state->connector); 3572 3573 intel_dp->link_trained = false; 3574 3575 intel_psr_disable(intel_dp, old_crtc_state); 3576 intel_edp_backlight_off(old_conn_state); 3577 /* Disable the decompression in DP Sink */ 3578 intel_dp_sink_disable_decompression(state, 3579 connector, old_crtc_state); 3580 /* Disable Ignore_MSA bit in DP Sink */ 3581 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3582 false); 3583 } 3584 3585 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3586 struct intel_encoder *encoder, 3587 const struct intel_crtc_state *old_crtc_state, 3588 const struct drm_connector_state *old_conn_state) 3589 { 3590 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3591 struct drm_connector *connector = old_conn_state->connector; 3592 3593 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3594 false, false)) 3595 drm_dbg_kms(&i915->drm, 3596 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3597 connector->base.id, connector->name); 3598 } 3599 3600 static void intel_ddi_disable(struct intel_atomic_state *state, 3601 struct intel_encoder *encoder, 3602 const struct intel_crtc_state *old_crtc_state, 3603 const struct drm_connector_state *old_conn_state) 3604 { 3605 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3606 3607 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3608 3609 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3610 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3611 old_conn_state); 3612 else 3613 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3614 old_conn_state); 3615 } 3616 3617 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3618 struct intel_encoder *encoder, 3619 const struct intel_crtc_state *crtc_state, 3620 const struct drm_connector_state *conn_state) 3621 { 3622 intel_ddi_set_dp_msa(crtc_state, conn_state); 3623 3624 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3625 3626 intel_backlight_update(state, encoder, crtc_state, conn_state); 3627 drm_connector_update_privacy_screen(conn_state); 3628 } 3629 3630 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3631 const struct intel_crtc_state *crtc_state, 3632 const struct drm_connector_state *conn_state) 3633 { 3634 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3635 } 3636 3637 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3638 struct intel_encoder *encoder, 3639 const struct intel_crtc_state *crtc_state, 3640 const struct drm_connector_state *conn_state) 3641 { 3642 3643 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3644 !intel_encoder_is_mst(encoder)) 3645 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3646 conn_state); 3647 3648 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3649 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3650 conn_state); 3651 3652 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3653 } 3654 3655 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3656 struct intel_encoder *encoder, 3657 struct intel_crtc *crtc) 3658 { 3659 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3660 const struct intel_crtc_state *crtc_state = 3661 intel_atomic_get_new_crtc_state(state, crtc); 3662 struct intel_crtc *pipe_crtc; 3663 3664 /* FIXME: Add MTL pll_mgr */ 3665 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3666 return; 3667 3668 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3669 intel_crtc_joined_pipe_mask(crtc_state)) 3670 intel_update_active_dpll(state, pipe_crtc, encoder); 3671 } 3672 3673 /* 3674 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3675 * encoder on its primary encoder. See also the comment for 3676 * intel_ddi_pre_enable(). 3677 */ 3678 static void 3679 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3680 struct intel_encoder *encoder, 3681 const struct intel_crtc_state *crtc_state, 3682 const struct drm_connector_state *conn_state) 3683 { 3684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3685 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3686 bool is_tc_port = intel_encoder_is_tc(encoder); 3687 3688 if (is_tc_port) { 3689 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3690 3691 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3692 intel_ddi_update_active_dpll(state, encoder, crtc); 3693 } 3694 3695 main_link_aux_power_domain_get(dig_port, crtc_state); 3696 3697 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3698 /* 3699 * Program the lane count for static/dynamic connections on 3700 * Type-C ports. Skip this step for TBT. 3701 */ 3702 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3703 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3704 bxt_dpio_phy_set_lane_optim_mask(encoder, 3705 crtc_state->lane_lat_optim_mask); 3706 } 3707 3708 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3709 { 3710 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3711 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3712 int ln; 3713 3714 for (ln = 0; ln < 2; ln++) 3715 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3716 } 3717 3718 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3719 const struct intel_crtc_state *crtc_state) 3720 { 3721 struct intel_display *display = to_intel_display(crtc_state); 3722 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3723 struct intel_encoder *encoder = &dig_port->base; 3724 enum port port = encoder->port; 3725 u32 dp_tp_ctl; 3726 3727 /* 3728 * TODO: To train with only a different voltage swing entry is not 3729 * necessary disable and enable port 3730 */ 3731 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3732 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3733 mtl_disable_ddi_buf(encoder, crtc_state); 3734 3735 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3736 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3737 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3738 intel_dp_is_uhbr(crtc_state)) { 3739 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3740 } else { 3741 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3742 if (crtc_state->enhanced_framing) 3743 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3744 } 3745 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3746 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3747 3748 /* 6.f Enable D2D Link */ 3749 mtl_ddi_enable_d2d(encoder); 3750 3751 /* 6.g Configure voltage swing and related IO settings */ 3752 encoder->set_signal_levels(encoder, crtc_state); 3753 3754 /* 6.h Configure PORT_BUF_CTL1 */ 3755 mtl_port_buf_ctl_program(encoder, crtc_state); 3756 3757 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3758 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3759 if (DISPLAY_VER(display) >= 20) 3760 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3761 3762 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 3763 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3764 3765 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3766 intel_wait_ddi_buf_active(encoder); 3767 } 3768 3769 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3770 const struct intel_crtc_state *crtc_state) 3771 { 3772 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3773 struct intel_encoder *encoder = &dig_port->base; 3774 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3775 enum port port = encoder->port; 3776 u32 dp_tp_ctl, ddi_buf_ctl; 3777 bool wait = false; 3778 3779 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3780 3781 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3782 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3783 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3784 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3785 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3786 wait = true; 3787 } 3788 3789 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3790 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3791 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3792 3793 if (wait) 3794 intel_wait_ddi_buf_idle(dev_priv, port); 3795 } 3796 3797 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3798 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3799 intel_dp_is_uhbr(crtc_state)) { 3800 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3801 } else { 3802 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3803 if (crtc_state->enhanced_framing) 3804 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3805 } 3806 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3807 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3808 3809 if (IS_ALDERLAKE_P(dev_priv) && 3810 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3811 adlp_tbt_to_dp_alt_switch_wa(encoder); 3812 3813 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3814 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3815 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3816 3817 intel_wait_ddi_buf_active(encoder); 3818 } 3819 3820 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3821 const struct intel_crtc_state *crtc_state, 3822 u8 dp_train_pat) 3823 { 3824 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3825 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3826 u32 temp; 3827 3828 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3829 3830 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3831 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3832 case DP_TRAINING_PATTERN_DISABLE: 3833 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3834 break; 3835 case DP_TRAINING_PATTERN_1: 3836 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3837 break; 3838 case DP_TRAINING_PATTERN_2: 3839 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3840 break; 3841 case DP_TRAINING_PATTERN_3: 3842 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3843 break; 3844 case DP_TRAINING_PATTERN_4: 3845 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3846 break; 3847 } 3848 3849 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3850 } 3851 3852 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3853 const struct intel_crtc_state *crtc_state) 3854 { 3855 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3857 enum port port = encoder->port; 3858 3859 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3860 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3861 3862 /* 3863 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3864 * reason we need to set idle transmission mode is to work around a HW 3865 * issue where we enable the pipe while not in idle link-training mode. 3866 * In this case there is requirement to wait for a minimum number of 3867 * idle patterns to be sent. 3868 */ 3869 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3870 return; 3871 3872 if (intel_de_wait_for_set(dev_priv, 3873 dp_tp_status_reg(encoder, crtc_state), 3874 DP_TP_STATUS_IDLE_DONE, 2)) 3875 drm_err(&dev_priv->drm, 3876 "Timed out waiting for DP idle patterns\n"); 3877 } 3878 3879 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3880 enum transcoder cpu_transcoder) 3881 { 3882 if (cpu_transcoder == TRANSCODER_EDP) 3883 return false; 3884 3885 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3886 return false; 3887 3888 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3889 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3890 } 3891 3892 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3893 { 3894 if (crtc_state->port_clock > 594000) 3895 return 2; 3896 else 3897 return 0; 3898 } 3899 3900 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3901 { 3902 if (crtc_state->port_clock > 594000) 3903 return 3; 3904 else 3905 return 0; 3906 } 3907 3908 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3909 { 3910 if (crtc_state->port_clock > 594000) 3911 return 1; 3912 else 3913 return 0; 3914 } 3915 3916 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3917 { 3918 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3919 3920 if (DISPLAY_VER(dev_priv) >= 14) 3921 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3922 else if (DISPLAY_VER(dev_priv) >= 12) 3923 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3924 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3925 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3926 else if (DISPLAY_VER(dev_priv) >= 11) 3927 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3928 } 3929 3930 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3931 enum transcoder cpu_transcoder) 3932 { 3933 u32 master_select; 3934 3935 if (DISPLAY_VER(dev_priv) >= 11) { 3936 u32 ctl2 = intel_de_read(dev_priv, 3937 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3938 3939 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3940 return INVALID_TRANSCODER; 3941 3942 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3943 } else { 3944 u32 ctl = intel_de_read(dev_priv, 3945 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3946 3947 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3948 return INVALID_TRANSCODER; 3949 3950 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3951 } 3952 3953 if (master_select == 0) 3954 return TRANSCODER_EDP; 3955 else 3956 return master_select - 1; 3957 } 3958 3959 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3960 { 3961 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3962 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3963 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3964 enum transcoder cpu_transcoder; 3965 3966 crtc_state->master_transcoder = 3967 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3968 3969 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3970 enum intel_display_power_domain power_domain; 3971 intel_wakeref_t trans_wakeref; 3972 3973 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3974 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3975 power_domain); 3976 3977 if (!trans_wakeref) 3978 continue; 3979 3980 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3981 crtc_state->cpu_transcoder) 3982 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3983 3984 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3985 } 3986 3987 drm_WARN_ON(&dev_priv->drm, 3988 crtc_state->master_transcoder != INVALID_TRANSCODER && 3989 crtc_state->sync_mode_slaves_mask); 3990 } 3991 3992 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3993 struct intel_crtc_state *crtc_state, 3994 u32 ddi_func_ctl) 3995 { 3996 struct intel_display *display = to_intel_display(encoder); 3997 3998 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3999 if (DISPLAY_VER(display) >= 14) 4000 crtc_state->lane_count = 4001 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4002 else 4003 crtc_state->lane_count = 4; 4004 } 4005 4006 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4007 struct intel_crtc_state *crtc_state, 4008 u32 ddi_func_ctl) 4009 { 4010 crtc_state->has_hdmi_sink = true; 4011 4012 crtc_state->infoframes.enable |= 4013 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4014 4015 if (crtc_state->infoframes.enable) 4016 crtc_state->has_infoframe = true; 4017 4018 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4019 crtc_state->hdmi_scrambling = true; 4020 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4021 crtc_state->hdmi_high_tmds_clock_ratio = true; 4022 4023 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4024 } 4025 4026 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4027 struct intel_crtc_state *crtc_state, 4028 u32 ddi_func_ctl) 4029 { 4030 struct intel_display *display = to_intel_display(encoder); 4031 4032 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4033 crtc_state->enhanced_framing = 4034 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4035 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4036 } 4037 4038 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4039 struct intel_crtc_state *crtc_state, 4040 u32 ddi_func_ctl) 4041 { 4042 struct intel_display *display = to_intel_display(encoder); 4043 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4045 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4046 4047 if (encoder->type == INTEL_OUTPUT_EDP) 4048 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4049 else 4050 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4051 crtc_state->lane_count = 4052 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4053 4054 if (DISPLAY_VER(display) >= 12 && 4055 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4056 crtc_state->mst_master_transcoder = 4057 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4058 4059 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4060 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4061 4062 crtc_state->enhanced_framing = 4063 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4064 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4065 4066 if (DISPLAY_VER(display) >= 11) 4067 crtc_state->fec_enable = 4068 intel_de_read(display, 4069 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4070 4071 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 4072 crtc_state->infoframes.enable |= 4073 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4074 else 4075 crtc_state->infoframes.enable |= 4076 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4077 } 4078 4079 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4080 struct intel_crtc_state *crtc_state, 4081 u32 ddi_func_ctl) 4082 { 4083 struct intel_display *display = to_intel_display(encoder); 4084 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4085 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4086 4087 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4088 crtc_state->lane_count = 4089 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4090 4091 if (DISPLAY_VER(display) >= 12) 4092 crtc_state->mst_master_transcoder = 4093 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4094 4095 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4096 4097 if (DISPLAY_VER(display) >= 11) 4098 crtc_state->fec_enable = 4099 intel_de_read(display, 4100 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4101 4102 crtc_state->infoframes.enable |= 4103 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4104 } 4105 4106 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4107 struct intel_crtc_state *pipe_config) 4108 { 4109 struct intel_display *display = to_intel_display(encoder); 4110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4111 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4112 u32 ddi_func_ctl, ddi_mode, flags = 0; 4113 4114 ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 4115 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4116 flags |= DRM_MODE_FLAG_PHSYNC; 4117 else 4118 flags |= DRM_MODE_FLAG_NHSYNC; 4119 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4120 flags |= DRM_MODE_FLAG_PVSYNC; 4121 else 4122 flags |= DRM_MODE_FLAG_NVSYNC; 4123 4124 pipe_config->hw.adjusted_mode.flags |= flags; 4125 4126 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4127 case TRANS_DDI_BPC_6: 4128 pipe_config->pipe_bpp = 18; 4129 break; 4130 case TRANS_DDI_BPC_8: 4131 pipe_config->pipe_bpp = 24; 4132 break; 4133 case TRANS_DDI_BPC_10: 4134 pipe_config->pipe_bpp = 30; 4135 break; 4136 case TRANS_DDI_BPC_12: 4137 pipe_config->pipe_bpp = 36; 4138 break; 4139 default: 4140 break; 4141 } 4142 4143 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4144 4145 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4146 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4147 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4148 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4150 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4152 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4153 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4154 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4155 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4156 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4157 4158 /* 4159 * If this is true, we know we're being called from mst stream 4160 * encoder's ->get_config(). 4161 */ 4162 if (intel_dp->is_mst) 4163 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4164 else 4165 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4166 } 4167 } 4168 4169 /* 4170 * Note: Also called from the ->get_config of the MST stream encoders on their 4171 * primary encoder, via the platform specific hooks here. See also the comment 4172 * for intel_ddi_pre_enable(). 4173 */ 4174 static void intel_ddi_get_config(struct intel_encoder *encoder, 4175 struct intel_crtc_state *pipe_config) 4176 { 4177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4178 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4179 4180 /* XXX: DSI transcoder paranoia */ 4181 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4182 return; 4183 4184 intel_ddi_read_func_ctl(encoder, pipe_config); 4185 4186 intel_ddi_mso_get_config(encoder, pipe_config); 4187 4188 pipe_config->has_audio = 4189 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4190 4191 if (encoder->type == INTEL_OUTPUT_EDP) 4192 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4193 4194 ddi_dotclock_get(pipe_config); 4195 4196 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4197 pipe_config->lane_lat_optim_mask = 4198 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4199 4200 intel_ddi_compute_min_voltage_level(pipe_config); 4201 4202 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4203 4204 intel_read_infoframe(encoder, pipe_config, 4205 HDMI_INFOFRAME_TYPE_AVI, 4206 &pipe_config->infoframes.avi); 4207 intel_read_infoframe(encoder, pipe_config, 4208 HDMI_INFOFRAME_TYPE_SPD, 4209 &pipe_config->infoframes.spd); 4210 intel_read_infoframe(encoder, pipe_config, 4211 HDMI_INFOFRAME_TYPE_VENDOR, 4212 &pipe_config->infoframes.hdmi); 4213 intel_read_infoframe(encoder, pipe_config, 4214 HDMI_INFOFRAME_TYPE_DRM, 4215 &pipe_config->infoframes.drm); 4216 4217 if (DISPLAY_VER(dev_priv) >= 8) 4218 bdw_get_trans_port_sync_config(pipe_config); 4219 4220 intel_psr_get_config(encoder, pipe_config); 4221 4222 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4223 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4224 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4225 4226 intel_audio_codec_get_config(encoder, pipe_config); 4227 } 4228 4229 void intel_ddi_get_clock(struct intel_encoder *encoder, 4230 struct intel_crtc_state *crtc_state, 4231 struct intel_shared_dpll *pll) 4232 { 4233 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4234 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4235 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4236 bool pll_active; 4237 4238 if (drm_WARN_ON(&i915->drm, !pll)) 4239 return; 4240 4241 port_dpll->pll = pll; 4242 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4243 drm_WARN_ON(&i915->drm, !pll_active); 4244 4245 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4246 4247 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4248 &crtc_state->dpll_hw_state); 4249 } 4250 4251 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4252 struct intel_crtc_state *crtc_state) 4253 { 4254 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4255 4256 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4257 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4258 else 4259 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4260 4261 intel_ddi_get_config(encoder, crtc_state); 4262 } 4263 4264 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4265 struct intel_crtc_state *crtc_state) 4266 { 4267 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4268 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4269 4270 intel_ddi_get_config(encoder, crtc_state); 4271 } 4272 4273 static void adls_ddi_get_config(struct intel_encoder *encoder, 4274 struct intel_crtc_state *crtc_state) 4275 { 4276 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4277 intel_ddi_get_config(encoder, crtc_state); 4278 } 4279 4280 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4281 struct intel_crtc_state *crtc_state) 4282 { 4283 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4284 intel_ddi_get_config(encoder, crtc_state); 4285 } 4286 4287 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4288 struct intel_crtc_state *crtc_state) 4289 { 4290 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4291 intel_ddi_get_config(encoder, crtc_state); 4292 } 4293 4294 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4295 struct intel_crtc_state *crtc_state) 4296 { 4297 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4298 intel_ddi_get_config(encoder, crtc_state); 4299 } 4300 4301 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4302 { 4303 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4304 } 4305 4306 static enum icl_port_dpll_id 4307 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4308 const struct intel_crtc_state *crtc_state) 4309 { 4310 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4311 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4312 4313 if (drm_WARN_ON(&i915->drm, !pll)) 4314 return ICL_PORT_DPLL_DEFAULT; 4315 4316 if (icl_ddi_tc_pll_is_tbt(pll)) 4317 return ICL_PORT_DPLL_DEFAULT; 4318 else 4319 return ICL_PORT_DPLL_MG_PHY; 4320 } 4321 4322 enum icl_port_dpll_id 4323 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4324 const struct intel_crtc_state *crtc_state) 4325 { 4326 if (!encoder->port_pll_type) 4327 return ICL_PORT_DPLL_DEFAULT; 4328 4329 return encoder->port_pll_type(encoder, crtc_state); 4330 } 4331 4332 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4333 struct intel_crtc_state *crtc_state, 4334 struct intel_shared_dpll *pll) 4335 { 4336 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4337 enum icl_port_dpll_id port_dpll_id; 4338 struct icl_port_dpll *port_dpll; 4339 bool pll_active; 4340 4341 if (drm_WARN_ON(&i915->drm, !pll)) 4342 return; 4343 4344 if (icl_ddi_tc_pll_is_tbt(pll)) 4345 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4346 else 4347 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4348 4349 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4350 4351 port_dpll->pll = pll; 4352 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4353 drm_WARN_ON(&i915->drm, !pll_active); 4354 4355 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4356 4357 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4358 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4359 else 4360 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4361 &crtc_state->dpll_hw_state); 4362 } 4363 4364 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4365 struct intel_crtc_state *crtc_state) 4366 { 4367 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4368 intel_ddi_get_config(encoder, crtc_state); 4369 } 4370 4371 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4372 struct intel_crtc_state *crtc_state) 4373 { 4374 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4375 intel_ddi_get_config(encoder, crtc_state); 4376 } 4377 4378 static void skl_ddi_get_config(struct intel_encoder *encoder, 4379 struct intel_crtc_state *crtc_state) 4380 { 4381 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4382 intel_ddi_get_config(encoder, crtc_state); 4383 } 4384 4385 void hsw_ddi_get_config(struct intel_encoder *encoder, 4386 struct intel_crtc_state *crtc_state) 4387 { 4388 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4389 intel_ddi_get_config(encoder, crtc_state); 4390 } 4391 4392 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4393 const struct intel_crtc_state *crtc_state) 4394 { 4395 if (intel_encoder_is_tc(encoder)) 4396 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4397 crtc_state); 4398 4399 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4400 (!crtc_state && intel_encoder_is_dp(encoder))) 4401 intel_dp_sync_state(encoder, crtc_state); 4402 } 4403 4404 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4405 struct intel_crtc_state *crtc_state) 4406 { 4407 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4408 bool fastset = true; 4409 4410 if (intel_encoder_is_tc(encoder)) { 4411 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4412 encoder->base.base.id, encoder->base.name); 4413 crtc_state->uapi.mode_changed = true; 4414 fastset = false; 4415 } 4416 4417 if (intel_crtc_has_dp_encoder(crtc_state) && 4418 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4419 fastset = false; 4420 4421 return fastset; 4422 } 4423 4424 static enum intel_output_type 4425 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4426 struct intel_crtc_state *crtc_state, 4427 struct drm_connector_state *conn_state) 4428 { 4429 switch (conn_state->connector->connector_type) { 4430 case DRM_MODE_CONNECTOR_HDMIA: 4431 return INTEL_OUTPUT_HDMI; 4432 case DRM_MODE_CONNECTOR_eDP: 4433 return INTEL_OUTPUT_EDP; 4434 case DRM_MODE_CONNECTOR_DisplayPort: 4435 return INTEL_OUTPUT_DP; 4436 default: 4437 MISSING_CASE(conn_state->connector->connector_type); 4438 return INTEL_OUTPUT_UNUSED; 4439 } 4440 } 4441 4442 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4443 struct intel_crtc_state *pipe_config, 4444 struct drm_connector_state *conn_state) 4445 { 4446 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4448 enum port port = encoder->port; 4449 int ret; 4450 4451 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4452 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4453 4454 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4455 pipe_config->has_hdmi_sink = 4456 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4457 4458 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4459 } else { 4460 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4461 } 4462 4463 if (ret) 4464 return ret; 4465 4466 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4467 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4468 pipe_config->pch_pfit.force_thru = 4469 pipe_config->pch_pfit.enabled || 4470 pipe_config->crc_enabled; 4471 4472 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4473 pipe_config->lane_lat_optim_mask = 4474 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4475 4476 intel_ddi_compute_min_voltage_level(pipe_config); 4477 4478 return 0; 4479 } 4480 4481 static bool mode_equal(const struct drm_display_mode *mode1, 4482 const struct drm_display_mode *mode2) 4483 { 4484 return drm_mode_match(mode1, mode2, 4485 DRM_MODE_MATCH_TIMINGS | 4486 DRM_MODE_MATCH_FLAGS | 4487 DRM_MODE_MATCH_3D_FLAGS) && 4488 mode1->clock == mode2->clock; /* we want an exact match */ 4489 } 4490 4491 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4492 const struct intel_link_m_n *m_n_2) 4493 { 4494 return m_n_1->tu == m_n_2->tu && 4495 m_n_1->data_m == m_n_2->data_m && 4496 m_n_1->data_n == m_n_2->data_n && 4497 m_n_1->link_m == m_n_2->link_m && 4498 m_n_1->link_n == m_n_2->link_n; 4499 } 4500 4501 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4502 const struct intel_crtc_state *crtc_state2) 4503 { 4504 /* 4505 * FIXME the modeset sequence is currently wrong and 4506 * can't deal with joiner + port sync at the same time. 4507 */ 4508 return crtc_state1->hw.active && crtc_state2->hw.active && 4509 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4510 crtc_state1->output_types == crtc_state2->output_types && 4511 crtc_state1->output_format == crtc_state2->output_format && 4512 crtc_state1->lane_count == crtc_state2->lane_count && 4513 crtc_state1->port_clock == crtc_state2->port_clock && 4514 mode_equal(&crtc_state1->hw.adjusted_mode, 4515 &crtc_state2->hw.adjusted_mode) && 4516 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4517 } 4518 4519 static u8 4520 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4521 int tile_group_id) 4522 { 4523 struct drm_connector *connector; 4524 const struct drm_connector_state *conn_state; 4525 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4526 struct intel_atomic_state *state = 4527 to_intel_atomic_state(ref_crtc_state->uapi.state); 4528 u8 transcoders = 0; 4529 int i; 4530 4531 /* 4532 * We don't enable port sync on BDW due to missing w/as and 4533 * due to not having adjusted the modeset sequence appropriately. 4534 */ 4535 if (DISPLAY_VER(dev_priv) < 9) 4536 return 0; 4537 4538 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4539 return 0; 4540 4541 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4542 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4543 const struct intel_crtc_state *crtc_state; 4544 4545 if (!crtc) 4546 continue; 4547 4548 if (!connector->has_tile || 4549 connector->tile_group->id != 4550 tile_group_id) 4551 continue; 4552 crtc_state = intel_atomic_get_new_crtc_state(state, 4553 crtc); 4554 if (!crtcs_port_sync_compatible(ref_crtc_state, 4555 crtc_state)) 4556 continue; 4557 transcoders |= BIT(crtc_state->cpu_transcoder); 4558 } 4559 4560 return transcoders; 4561 } 4562 4563 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4564 struct intel_crtc_state *crtc_state, 4565 struct drm_connector_state *conn_state) 4566 { 4567 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4568 struct drm_connector *connector = conn_state->connector; 4569 u8 port_sync_transcoders = 0; 4570 4571 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4572 encoder->base.base.id, encoder->base.name, 4573 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4574 4575 if (connector->has_tile) 4576 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4577 connector->tile_group->id); 4578 4579 /* 4580 * EDP Transcoders cannot be ensalved 4581 * make them a master always when present 4582 */ 4583 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4584 crtc_state->master_transcoder = TRANSCODER_EDP; 4585 else 4586 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4587 4588 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4589 crtc_state->master_transcoder = INVALID_TRANSCODER; 4590 crtc_state->sync_mode_slaves_mask = 4591 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4592 } 4593 4594 return 0; 4595 } 4596 4597 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4598 { 4599 struct drm_i915_private *i915 = to_i915(encoder->dev); 4600 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4601 4602 intel_dp_encoder_flush_work(encoder); 4603 if (intel_encoder_is_tc(&dig_port->base)) 4604 intel_tc_port_cleanup(dig_port); 4605 intel_display_power_flush_work(i915); 4606 4607 drm_encoder_cleanup(encoder); 4608 kfree(dig_port->hdcp_port_data.streams); 4609 kfree(dig_port); 4610 } 4611 4612 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4613 { 4614 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4615 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4616 4617 intel_dp->reset_link_params = true; 4618 intel_dp_invalidate_source_oui(intel_dp); 4619 4620 intel_pps_encoder_reset(intel_dp); 4621 4622 if (intel_encoder_is_tc(&dig_port->base)) 4623 intel_tc_port_init_mode(dig_port); 4624 } 4625 4626 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4627 { 4628 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4629 4630 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4631 4632 return 0; 4633 } 4634 4635 static const struct drm_encoder_funcs intel_ddi_funcs = { 4636 .reset = intel_ddi_encoder_reset, 4637 .destroy = intel_ddi_encoder_destroy, 4638 .late_register = intel_ddi_encoder_late_register, 4639 }; 4640 4641 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4642 { 4643 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4644 struct intel_connector *connector; 4645 enum port port = dig_port->base.port; 4646 4647 connector = intel_connector_alloc(); 4648 if (!connector) 4649 return -ENOMEM; 4650 4651 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4652 if (DISPLAY_VER(i915) >= 14) 4653 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4654 else 4655 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4656 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4657 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4658 4659 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4660 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4661 4662 if (!intel_dp_init_connector(dig_port, connector)) { 4663 kfree(connector); 4664 return -EINVAL; 4665 } 4666 4667 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4668 struct drm_device *dev = dig_port->base.base.dev; 4669 struct drm_privacy_screen *privacy_screen; 4670 4671 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4672 if (!IS_ERR(privacy_screen)) { 4673 drm_connector_attach_privacy_screen_provider(&connector->base, 4674 privacy_screen); 4675 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4676 drm_warn(dev, "Error getting privacy-screen\n"); 4677 } 4678 } 4679 4680 return 0; 4681 } 4682 4683 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4684 struct drm_modeset_acquire_ctx *ctx) 4685 { 4686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4687 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4688 struct intel_connector *connector = hdmi->attached_connector; 4689 struct i2c_adapter *ddc = connector->base.ddc; 4690 struct drm_connector_state *conn_state; 4691 struct intel_crtc_state *crtc_state; 4692 struct intel_crtc *crtc; 4693 u8 config; 4694 int ret; 4695 4696 if (connector->base.status != connector_status_connected) 4697 return 0; 4698 4699 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4700 ctx); 4701 if (ret) 4702 return ret; 4703 4704 conn_state = connector->base.state; 4705 4706 crtc = to_intel_crtc(conn_state->crtc); 4707 if (!crtc) 4708 return 0; 4709 4710 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4711 if (ret) 4712 return ret; 4713 4714 crtc_state = to_intel_crtc_state(crtc->base.state); 4715 4716 drm_WARN_ON(&dev_priv->drm, 4717 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4718 4719 if (!crtc_state->hw.active) 4720 return 0; 4721 4722 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4723 !crtc_state->hdmi_scrambling) 4724 return 0; 4725 4726 if (conn_state->commit && 4727 !try_wait_for_completion(&conn_state->commit->hw_done)) 4728 return 0; 4729 4730 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4731 if (ret < 0) { 4732 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4733 connector->base.base.id, connector->base.name, ret); 4734 return 0; 4735 } 4736 4737 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4738 crtc_state->hdmi_high_tmds_clock_ratio && 4739 !!(config & SCDC_SCRAMBLING_ENABLE) == 4740 crtc_state->hdmi_scrambling) 4741 return 0; 4742 4743 /* 4744 * HDMI 2.0 says that one should not send scrambled data 4745 * prior to configuring the sink scrambling, and that 4746 * TMDS clock/data transmission should be suspended when 4747 * changing the TMDS clock rate in the sink. So let's 4748 * just do a full modeset here, even though some sinks 4749 * would be perfectly happy if were to just reconfigure 4750 * the SCDC settings on the fly. 4751 */ 4752 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4753 } 4754 4755 static void intel_ddi_link_check(struct intel_encoder *encoder) 4756 { 4757 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4758 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4759 4760 /* TODO: Move checking the HDMI link state here as well. */ 4761 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4762 4763 intel_dp_link_check(encoder); 4764 } 4765 4766 static enum intel_hotplug_state 4767 intel_ddi_hotplug(struct intel_encoder *encoder, 4768 struct intel_connector *connector) 4769 { 4770 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4771 struct intel_dp *intel_dp = &dig_port->dp; 4772 bool is_tc = intel_encoder_is_tc(encoder); 4773 struct drm_modeset_acquire_ctx ctx; 4774 enum intel_hotplug_state state; 4775 int ret; 4776 4777 if (intel_dp_test_phy(intel_dp)) 4778 return INTEL_HOTPLUG_UNCHANGED; 4779 4780 state = intel_encoder_hotplug(encoder, connector); 4781 4782 if (!intel_tc_port_link_reset(dig_port)) { 4783 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4784 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4785 ret = intel_hdmi_reset_link(encoder, &ctx); 4786 drm_WARN_ON(encoder->base.dev, ret); 4787 } else { 4788 intel_dp_check_link_state(intel_dp); 4789 } 4790 } 4791 4792 /* 4793 * Unpowered type-c dongles can take some time to boot and be 4794 * responsible, so here giving some time to those dongles to power up 4795 * and then retrying the probe. 4796 * 4797 * On many platforms the HDMI live state signal is known to be 4798 * unreliable, so we can't use it to detect if a sink is connected or 4799 * not. Instead we detect if it's connected based on whether we can 4800 * read the EDID or not. That in turn has a problem during disconnect, 4801 * since the HPD interrupt may be raised before the DDC lines get 4802 * disconnected (due to how the required length of DDC vs. HPD 4803 * connector pins are specified) and so we'll still be able to get a 4804 * valid EDID. To solve this schedule another detection cycle if this 4805 * time around we didn't detect any change in the sink's connection 4806 * status. 4807 * 4808 * Type-c connectors which get their HPD signal deasserted then 4809 * reasserted, without unplugging/replugging the sink from the 4810 * connector, introduce a delay until the AUX channel communication 4811 * becomes functional. Retry the detection for 5 seconds on type-c 4812 * connectors to account for this delay. 4813 */ 4814 if (state == INTEL_HOTPLUG_UNCHANGED && 4815 connector->hotplug_retries < (is_tc ? 5 : 1) && 4816 !dig_port->dp.is_mst) 4817 state = INTEL_HOTPLUG_RETRY; 4818 4819 return state; 4820 } 4821 4822 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4823 { 4824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4825 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4826 4827 return intel_de_read(dev_priv, SDEISR) & bit; 4828 } 4829 4830 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4831 { 4832 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4833 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4834 4835 return intel_de_read(dev_priv, DEISR) & bit; 4836 } 4837 4838 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4839 { 4840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4841 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4842 4843 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4844 } 4845 4846 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4847 { 4848 struct intel_connector *connector; 4849 enum port port = dig_port->base.port; 4850 4851 connector = intel_connector_alloc(); 4852 if (!connector) 4853 return -ENOMEM; 4854 4855 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4856 4857 if (!intel_hdmi_init_connector(dig_port, connector)) { 4858 /* 4859 * HDMI connector init failures may just mean conflicting DDC 4860 * pins or not having enough lanes. Handle them gracefully, but 4861 * don't fail the entire DDI init. 4862 */ 4863 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4864 kfree(connector); 4865 } 4866 4867 return 0; 4868 } 4869 4870 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4871 { 4872 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4873 4874 if (dig_port->base.port != PORT_A) 4875 return false; 4876 4877 if (dig_port->ddi_a_4_lanes) 4878 return false; 4879 4880 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4881 * supported configuration 4882 */ 4883 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4884 return true; 4885 4886 return false; 4887 } 4888 4889 static int 4890 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4891 { 4892 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4893 enum port port = dig_port->base.port; 4894 int max_lanes = 4; 4895 4896 if (DISPLAY_VER(dev_priv) >= 11) 4897 return max_lanes; 4898 4899 if (port == PORT_A || port == PORT_E) { 4900 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4901 max_lanes = port == PORT_A ? 4 : 0; 4902 else 4903 /* Both A and E share 2 lanes */ 4904 max_lanes = 2; 4905 } 4906 4907 /* 4908 * Some BIOS might fail to set this bit on port A if eDP 4909 * wasn't lit up at boot. Force this bit set when needed 4910 * so we use the proper lane count for our calculations. 4911 */ 4912 if (intel_ddi_a_force_4_lanes(dig_port)) { 4913 drm_dbg_kms(&dev_priv->drm, 4914 "Forcing DDI_A_4_LANES for port A\n"); 4915 dig_port->ddi_a_4_lanes = true; 4916 max_lanes = 4; 4917 } 4918 4919 return max_lanes; 4920 } 4921 4922 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4923 enum port port) 4924 { 4925 if (port >= PORT_D_XELPD) 4926 return HPD_PORT_D + port - PORT_D_XELPD; 4927 else if (port >= PORT_TC1) 4928 return HPD_PORT_TC1 + port - PORT_TC1; 4929 else 4930 return HPD_PORT_A + port - PORT_A; 4931 } 4932 4933 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4934 enum port port) 4935 { 4936 if (port >= PORT_TC1) 4937 return HPD_PORT_C + port - PORT_TC1; 4938 else 4939 return HPD_PORT_A + port - PORT_A; 4940 } 4941 4942 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4943 enum port port) 4944 { 4945 if (port >= PORT_TC1) 4946 return HPD_PORT_TC1 + port - PORT_TC1; 4947 else 4948 return HPD_PORT_A + port - PORT_A; 4949 } 4950 4951 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4952 enum port port) 4953 { 4954 if (HAS_PCH_TGP(dev_priv)) 4955 return tgl_hpd_pin(dev_priv, port); 4956 4957 if (port >= PORT_TC1) 4958 return HPD_PORT_C + port - PORT_TC1; 4959 else 4960 return HPD_PORT_A + port - PORT_A; 4961 } 4962 4963 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4964 enum port port) 4965 { 4966 if (port >= PORT_C) 4967 return HPD_PORT_TC1 + port - PORT_C; 4968 else 4969 return HPD_PORT_A + port - PORT_A; 4970 } 4971 4972 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4973 enum port port) 4974 { 4975 if (port == PORT_D) 4976 return HPD_PORT_A; 4977 4978 if (HAS_PCH_TGP(dev_priv)) 4979 return icl_hpd_pin(dev_priv, port); 4980 4981 return HPD_PORT_A + port - PORT_A; 4982 } 4983 4984 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4985 { 4986 if (HAS_PCH_TGP(dev_priv)) 4987 return icl_hpd_pin(dev_priv, port); 4988 4989 return HPD_PORT_A + port - PORT_A; 4990 } 4991 4992 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4993 { 4994 if (DISPLAY_VER(i915) >= 12) 4995 return port >= PORT_TC1; 4996 else if (DISPLAY_VER(i915) >= 11) 4997 return port >= PORT_C; 4998 else 4999 return false; 5000 } 5001 5002 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5003 { 5004 intel_dp_encoder_suspend(encoder); 5005 } 5006 5007 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5008 { 5009 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5010 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5011 5012 /* 5013 * TODO: Move this to intel_dp_encoder_suspend(), 5014 * once modeset locking around that is removed. 5015 */ 5016 intel_encoder_link_check_flush_work(encoder); 5017 intel_tc_port_suspend(dig_port); 5018 } 5019 5020 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5021 { 5022 if (intel_encoder_is_dp(encoder)) 5023 intel_dp_encoder_shutdown(encoder); 5024 if (intel_encoder_is_hdmi(encoder)) 5025 intel_hdmi_encoder_shutdown(encoder); 5026 } 5027 5028 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5029 { 5030 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5031 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5032 5033 intel_tc_port_cleanup(dig_port); 5034 } 5035 5036 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5037 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5038 5039 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 5040 { 5041 /* straps not used on skl+ */ 5042 if (DISPLAY_VER(i915) >= 9) 5043 return true; 5044 5045 switch (port) { 5046 case PORT_A: 5047 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5048 case PORT_B: 5049 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5050 case PORT_C: 5051 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5052 case PORT_D: 5053 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5054 case PORT_E: 5055 return true; /* no strap for DDI-E */ 5056 default: 5057 MISSING_CASE(port); 5058 return false; 5059 } 5060 } 5061 5062 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5063 { 5064 return init_dp || intel_encoder_is_tc(encoder); 5065 } 5066 5067 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 5068 { 5069 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 5070 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 5071 "Platform does not support DSI\n"); 5072 } 5073 5074 static bool port_in_use(struct drm_i915_private *i915, enum port port) 5075 { 5076 struct intel_encoder *encoder; 5077 5078 for_each_intel_encoder(&i915->drm, encoder) { 5079 /* FIXME what about second port for dual link DSI? */ 5080 if (encoder->port == port) 5081 return true; 5082 } 5083 5084 return false; 5085 } 5086 5087 void intel_ddi_init(struct intel_display *display, 5088 const struct intel_bios_encoder_data *devdata) 5089 { 5090 struct drm_i915_private *dev_priv = to_i915(display->drm); 5091 struct intel_digital_port *dig_port; 5092 struct intel_encoder *encoder; 5093 bool init_hdmi, init_dp; 5094 enum port port; 5095 enum phy phy; 5096 u32 ddi_buf_ctl; 5097 5098 port = intel_bios_encoder_port(devdata); 5099 if (port == PORT_NONE) 5100 return; 5101 5102 if (!port_strap_detected(dev_priv, port)) { 5103 drm_dbg_kms(&dev_priv->drm, 5104 "Port %c strap not detected\n", port_name(port)); 5105 return; 5106 } 5107 5108 if (!assert_port_valid(dev_priv, port)) 5109 return; 5110 5111 if (port_in_use(dev_priv, port)) { 5112 drm_dbg_kms(&dev_priv->drm, 5113 "Port %c already claimed\n", port_name(port)); 5114 return; 5115 } 5116 5117 if (intel_bios_encoder_supports_dsi(devdata)) { 5118 /* BXT/GLK handled elsewhere, for now at least */ 5119 if (!assert_has_icl_dsi(dev_priv)) 5120 return; 5121 5122 icl_dsi_init(display, devdata); 5123 return; 5124 } 5125 5126 phy = intel_port_to_phy(dev_priv, port); 5127 5128 /* 5129 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5130 * have taken over some of the PHYs and made them unavailable to the 5131 * driver. In that case we should skip initializing the corresponding 5132 * outputs. 5133 */ 5134 if (intel_hti_uses_phy(display, phy)) { 5135 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5136 port_name(port), phy_name(phy)); 5137 return; 5138 } 5139 5140 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5141 intel_bios_encoder_supports_hdmi(devdata); 5142 init_dp = intel_bios_encoder_supports_dp(devdata); 5143 5144 if (intel_bios_encoder_is_lspcon(devdata)) { 5145 /* 5146 * Lspcon device needs to be driven with DP connector 5147 * with special detection sequence. So make sure DP 5148 * is initialized before lspcon. 5149 */ 5150 init_dp = true; 5151 init_hdmi = false; 5152 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5153 port_name(port)); 5154 } 5155 5156 if (!init_dp && !init_hdmi) { 5157 drm_dbg_kms(&dev_priv->drm, 5158 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5159 port_name(port)); 5160 return; 5161 } 5162 5163 if (intel_phy_is_snps(dev_priv, phy) && 5164 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 5165 drm_dbg_kms(&dev_priv->drm, 5166 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5167 phy_name(phy)); 5168 } 5169 5170 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5171 if (!dig_port) 5172 return; 5173 5174 dig_port->aux_ch = AUX_CH_NONE; 5175 5176 encoder = &dig_port->base; 5177 encoder->devdata = devdata; 5178 5179 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 5180 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5181 DRM_MODE_ENCODER_TMDS, 5182 "DDI %c/PHY %c", 5183 port_name(port - PORT_D_XELPD + PORT_D), 5184 phy_name(phy)); 5185 } else if (DISPLAY_VER(dev_priv) >= 12) { 5186 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5187 5188 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5189 DRM_MODE_ENCODER_TMDS, 5190 "DDI %s%c/PHY %s%c", 5191 port >= PORT_TC1 ? "TC" : "", 5192 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5193 tc_port != TC_PORT_NONE ? "TC" : "", 5194 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5195 } else if (DISPLAY_VER(dev_priv) >= 11) { 5196 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5197 5198 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5199 DRM_MODE_ENCODER_TMDS, 5200 "DDI %c%s/PHY %s%c", 5201 port_name(port), 5202 port >= PORT_C ? " (TC)" : "", 5203 tc_port != TC_PORT_NONE ? "TC" : "", 5204 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5205 } else { 5206 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5207 DRM_MODE_ENCODER_TMDS, 5208 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5209 } 5210 5211 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5212 5213 mutex_init(&dig_port->hdcp_mutex); 5214 dig_port->num_hdcp_streams = 0; 5215 5216 encoder->hotplug = intel_ddi_hotplug; 5217 encoder->compute_output_type = intel_ddi_compute_output_type; 5218 encoder->compute_config = intel_ddi_compute_config; 5219 encoder->compute_config_late = intel_ddi_compute_config_late; 5220 encoder->enable = intel_ddi_enable; 5221 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5222 encoder->pre_enable = intel_ddi_pre_enable; 5223 encoder->disable = intel_ddi_disable; 5224 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5225 encoder->post_disable = intel_ddi_post_disable; 5226 encoder->update_pipe = intel_ddi_update_pipe; 5227 encoder->audio_enable = intel_audio_codec_enable; 5228 encoder->audio_disable = intel_audio_codec_disable; 5229 encoder->get_hw_state = intel_ddi_get_hw_state; 5230 encoder->sync_state = intel_ddi_sync_state; 5231 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5232 encoder->suspend = intel_ddi_encoder_suspend; 5233 encoder->shutdown = intel_ddi_encoder_shutdown; 5234 encoder->get_power_domains = intel_ddi_get_power_domains; 5235 5236 encoder->type = INTEL_OUTPUT_DDI; 5237 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5238 encoder->port = port; 5239 encoder->cloneable = 0; 5240 encoder->pipe_mask = ~0; 5241 5242 if (DISPLAY_VER(dev_priv) >= 14) { 5243 encoder->enable_clock = intel_mtl_pll_enable; 5244 encoder->disable_clock = intel_mtl_pll_disable; 5245 encoder->port_pll_type = intel_mtl_port_pll_type; 5246 encoder->get_config = mtl_ddi_get_config; 5247 } else if (IS_DG2(dev_priv)) { 5248 encoder->enable_clock = intel_mpllb_enable; 5249 encoder->disable_clock = intel_mpllb_disable; 5250 encoder->get_config = dg2_ddi_get_config; 5251 } else if (IS_ALDERLAKE_S(dev_priv)) { 5252 encoder->enable_clock = adls_ddi_enable_clock; 5253 encoder->disable_clock = adls_ddi_disable_clock; 5254 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5255 encoder->get_config = adls_ddi_get_config; 5256 } else if (IS_ROCKETLAKE(dev_priv)) { 5257 encoder->enable_clock = rkl_ddi_enable_clock; 5258 encoder->disable_clock = rkl_ddi_disable_clock; 5259 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5260 encoder->get_config = rkl_ddi_get_config; 5261 } else if (IS_DG1(dev_priv)) { 5262 encoder->enable_clock = dg1_ddi_enable_clock; 5263 encoder->disable_clock = dg1_ddi_disable_clock; 5264 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5265 encoder->get_config = dg1_ddi_get_config; 5266 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5267 if (intel_ddi_is_tc(dev_priv, port)) { 5268 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5269 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5270 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5271 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5272 encoder->get_config = icl_ddi_combo_get_config; 5273 } else { 5274 encoder->enable_clock = icl_ddi_combo_enable_clock; 5275 encoder->disable_clock = icl_ddi_combo_disable_clock; 5276 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5277 encoder->get_config = icl_ddi_combo_get_config; 5278 } 5279 } else if (DISPLAY_VER(dev_priv) >= 11) { 5280 if (intel_ddi_is_tc(dev_priv, port)) { 5281 encoder->enable_clock = icl_ddi_tc_enable_clock; 5282 encoder->disable_clock = icl_ddi_tc_disable_clock; 5283 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5284 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5285 encoder->get_config = icl_ddi_tc_get_config; 5286 } else { 5287 encoder->enable_clock = icl_ddi_combo_enable_clock; 5288 encoder->disable_clock = icl_ddi_combo_disable_clock; 5289 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5290 encoder->get_config = icl_ddi_combo_get_config; 5291 } 5292 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5293 /* BXT/GLK have fixed PLL->port mapping */ 5294 encoder->get_config = bxt_ddi_get_config; 5295 } else if (DISPLAY_VER(dev_priv) == 9) { 5296 encoder->enable_clock = skl_ddi_enable_clock; 5297 encoder->disable_clock = skl_ddi_disable_clock; 5298 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5299 encoder->get_config = skl_ddi_get_config; 5300 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5301 encoder->enable_clock = hsw_ddi_enable_clock; 5302 encoder->disable_clock = hsw_ddi_disable_clock; 5303 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5304 encoder->get_config = hsw_ddi_get_config; 5305 } 5306 5307 if (DISPLAY_VER(dev_priv) >= 14) { 5308 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5309 } else if (IS_DG2(dev_priv)) { 5310 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5311 } else if (DISPLAY_VER(dev_priv) >= 12) { 5312 if (intel_encoder_is_combo(encoder)) 5313 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5314 else 5315 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5316 } else if (DISPLAY_VER(dev_priv) >= 11) { 5317 if (intel_encoder_is_combo(encoder)) 5318 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5319 else 5320 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5321 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5322 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5323 } else { 5324 encoder->set_signal_levels = hsw_set_signal_levels; 5325 } 5326 5327 intel_ddi_buf_trans_init(encoder); 5328 5329 if (DISPLAY_VER(dev_priv) >= 13) 5330 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5331 else if (IS_DG1(dev_priv)) 5332 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5333 else if (IS_ROCKETLAKE(dev_priv)) 5334 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5335 else if (DISPLAY_VER(dev_priv) >= 12) 5336 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5337 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5338 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5339 else if (DISPLAY_VER(dev_priv) == 11) 5340 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5341 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5342 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5343 else 5344 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5345 5346 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 5347 5348 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5349 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5350 5351 dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5352 5353 dig_port->dp.output_reg = INVALID_MMIO_REG; 5354 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5355 5356 if (need_aux_ch(encoder, init_dp)) { 5357 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5358 if (dig_port->aux_ch == AUX_CH_NONE) 5359 goto err; 5360 } 5361 5362 if (intel_encoder_is_tc(encoder)) { 5363 bool is_legacy = 5364 !intel_bios_encoder_supports_typec_usb(devdata) && 5365 !intel_bios_encoder_supports_tbt(devdata); 5366 5367 if (!is_legacy && init_hdmi) { 5368 is_legacy = !init_dp; 5369 5370 drm_dbg_kms(&dev_priv->drm, 5371 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5372 port_name(port), 5373 str_yes_no(init_dp), 5374 is_legacy ? "legacy" : "non-legacy"); 5375 } 5376 5377 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5378 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5379 5380 dig_port->lock = intel_tc_port_lock; 5381 dig_port->unlock = intel_tc_port_unlock; 5382 5383 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5384 goto err; 5385 } 5386 5387 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5388 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5389 5390 if (DISPLAY_VER(dev_priv) >= 11) { 5391 if (intel_encoder_is_tc(encoder)) 5392 dig_port->connected = intel_tc_port_connected; 5393 else 5394 dig_port->connected = lpt_digital_port_connected; 5395 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5396 dig_port->connected = bdw_digital_port_connected; 5397 } else if (DISPLAY_VER(dev_priv) == 9) { 5398 dig_port->connected = lpt_digital_port_connected; 5399 } else if (IS_BROADWELL(dev_priv)) { 5400 if (port == PORT_A) 5401 dig_port->connected = bdw_digital_port_connected; 5402 else 5403 dig_port->connected = lpt_digital_port_connected; 5404 } else if (IS_HASWELL(dev_priv)) { 5405 if (port == PORT_A) 5406 dig_port->connected = hsw_digital_port_connected; 5407 else 5408 dig_port->connected = lpt_digital_port_connected; 5409 } 5410 5411 intel_infoframe_init(dig_port); 5412 5413 if (init_dp) { 5414 if (intel_ddi_init_dp_connector(dig_port)) 5415 goto err; 5416 5417 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5418 5419 if (dig_port->dp.mso_link_count) 5420 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5421 } 5422 5423 /* 5424 * In theory we don't need the encoder->type check, 5425 * but leave it just in case we have some really bad VBTs... 5426 */ 5427 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5428 if (intel_ddi_init_hdmi_connector(dig_port)) 5429 goto err; 5430 } 5431 5432 return; 5433 5434 err: 5435 drm_encoder_cleanup(&encoder->base); 5436 kfree(dig_port); 5437 } 5438