1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_privacy_screen_consumer.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "icl_dsi.h" 38 #include "intel_audio.h" 39 #include "intel_audio_regs.h" 40 #include "intel_backlight.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_cx0_phy.h" 46 #include "intel_cx0_phy_regs.h" 47 #include "intel_ddi.h" 48 #include "intel_ddi_buf_trans.h" 49 #include "intel_de.h" 50 #include "intel_display_power.h" 51 #include "intel_display_types.h" 52 #include "intel_dkl_phy.h" 53 #include "intel_dkl_phy_regs.h" 54 #include "intel_dp.h" 55 #include "intel_dp_aux.h" 56 #include "intel_dp_link_training.h" 57 #include "intel_dp_mst.h" 58 #include "intel_dp_test.h" 59 #include "intel_dp_tunnel.h" 60 #include "intel_dpio_phy.h" 61 #include "intel_dsi.h" 62 #include "intel_encoder.h" 63 #include "intel_fdi.h" 64 #include "intel_fifo_underrun.h" 65 #include "intel_gmbus.h" 66 #include "intel_hdcp.h" 67 #include "intel_hdmi.h" 68 #include "intel_hotplug.h" 69 #include "intel_hti.h" 70 #include "intel_lspcon.h" 71 #include "intel_mg_phy_regs.h" 72 #include "intel_modeset_lock.h" 73 #include "intel_pps.h" 74 #include "intel_psr.h" 75 #include "intel_quirks.h" 76 #include "intel_snps_phy.h" 77 #include "intel_tc.h" 78 #include "intel_vdsc.h" 79 #include "intel_vdsc_regs.h" 80 #include "skl_scaler.h" 81 #include "skl_universal_plane.h" 82 83 static const u8 index_to_dp_signal_levels[] = { 84 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 88 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 91 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 }; 95 96 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 97 const struct intel_ddi_buf_trans *trans) 98 { 99 int level; 100 101 level = intel_bios_hdmi_level_shift(encoder->devdata); 102 if (level < 0) 103 level = trans->hdmi_default_entry; 104 105 return level; 106 } 107 108 static bool has_buf_trans_select(struct drm_i915_private *i915) 109 { 110 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 111 } 112 113 static bool has_iboost(struct drm_i915_private *i915) 114 { 115 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 116 } 117 118 /* 119 * Starting with Haswell, DDI port buffers must be programmed with correct 120 * values in advance. This function programs the correct values for 121 * DP/eDP/FDI use cases. 122 */ 123 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 124 const struct intel_crtc_state *crtc_state) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 u32 iboost_bit = 0; 128 int i, n_entries; 129 enum port port = encoder->port; 130 const struct intel_ddi_buf_trans *trans; 131 132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 134 return; 135 136 /* If we're boosting the current, set bit 31 of trans1 */ 137 if (has_iboost(dev_priv) && 138 intel_bios_dp_boost_level(encoder->devdata)) 139 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 140 141 for (i = 0; i < n_entries; i++) { 142 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 143 trans->entries[i].hsw.trans1 | iboost_bit); 144 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 145 trans->entries[i].hsw.trans2); 146 } 147 } 148 149 /* 150 * Starting with Haswell, DDI port buffers must be programmed with correct 151 * values in advance. This function programs the correct values for 152 * HDMI/DVI use cases. 153 */ 154 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 155 const struct intel_crtc_state *crtc_state) 156 { 157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 158 int level = intel_ddi_level(encoder, crtc_state, 0); 159 u32 iboost_bit = 0; 160 int n_entries; 161 enum port port = encoder->port; 162 const struct intel_ddi_buf_trans *trans; 163 164 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 165 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 166 return; 167 168 /* If we're boosting the current, set bit 31 of trans1 */ 169 if (has_iboost(dev_priv) && 170 intel_bios_hdmi_boost_level(encoder->devdata)) 171 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 172 173 /* Entry 9 is for HDMI: */ 174 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 175 trans->entries[level].hsw.trans1 | iboost_bit); 176 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 177 trans->entries[level].hsw.trans2); 178 } 179 180 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 181 { 182 int ret; 183 184 /* FIXME: find out why Bspec's 100us timeout is too short */ 185 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 186 XELPDP_PORT_BUF_PHY_IDLE), 10000); 187 if (ret) 188 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 189 port_name(port)); 190 } 191 192 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 193 enum port port) 194 { 195 if (IS_BROXTON(dev_priv)) { 196 udelay(16); 197 return; 198 } 199 200 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 201 DDI_BUF_IS_IDLE), 8)) 202 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 203 port_name(port)); 204 } 205 206 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 207 { 208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 209 enum port port = encoder->port; 210 int timeout_us; 211 int ret; 212 213 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 214 if (DISPLAY_VER(dev_priv) < 10) { 215 usleep_range(518, 1000); 216 return; 217 } 218 219 if (DISPLAY_VER(dev_priv) >= 14) { 220 timeout_us = 10000; 221 } else if (IS_DG2(dev_priv)) { 222 timeout_us = 1200; 223 } else if (DISPLAY_VER(dev_priv) >= 12) { 224 if (intel_encoder_is_tc(encoder)) 225 timeout_us = 3000; 226 else 227 timeout_us = 1000; 228 } else { 229 timeout_us = 500; 230 } 231 232 if (DISPLAY_VER(dev_priv) >= 14) 233 ret = _wait_for(!(intel_de_read(dev_priv, 234 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 235 XELPDP_PORT_BUF_PHY_IDLE), 236 timeout_us, 10, 10); 237 else 238 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 239 timeout_us, 10, 10); 240 241 if (ret) 242 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state) 333 { 334 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 336 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 337 338 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 339 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 340 DDI_BUF_TRANS_SELECT(0); 341 342 if (dig_port->lane_reversal) 343 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 344 if (dig_port->ddi_a_4_lanes) 345 intel_dp->DP |= DDI_A_4_LANES; 346 347 if (DISPLAY_VER(i915) >= 14) { 348 if (intel_dp_is_uhbr(crtc_state)) 349 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 350 else 351 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 352 } 353 354 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 355 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 356 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 357 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 358 } 359 } 360 361 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 362 enum port port) 363 { 364 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 365 366 switch (val) { 367 case DDI_CLK_SEL_NONE: 368 return 0; 369 case DDI_CLK_SEL_TBT_162: 370 return 162000; 371 case DDI_CLK_SEL_TBT_270: 372 return 270000; 373 case DDI_CLK_SEL_TBT_540: 374 return 540000; 375 case DDI_CLK_SEL_TBT_810: 376 return 810000; 377 default: 378 MISSING_CASE(val); 379 return 0; 380 } 381 } 382 383 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 384 { 385 /* CRT dotclock is determined via other means */ 386 if (pipe_config->has_pch_encoder) 387 return; 388 389 pipe_config->hw.adjusted_mode.crtc_clock = 390 intel_crtc_dotclock(pipe_config); 391 } 392 393 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 394 const struct drm_connector_state *conn_state) 395 { 396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 398 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 399 u32 temp; 400 401 if (!intel_crtc_has_dp_encoder(crtc_state)) 402 return; 403 404 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 405 406 temp = DP_MSA_MISC_SYNC_CLOCK; 407 408 switch (crtc_state->pipe_bpp) { 409 case 18: 410 temp |= DP_MSA_MISC_6_BPC; 411 break; 412 case 24: 413 temp |= DP_MSA_MISC_8_BPC; 414 break; 415 case 30: 416 temp |= DP_MSA_MISC_10_BPC; 417 break; 418 case 36: 419 temp |= DP_MSA_MISC_12_BPC; 420 break; 421 default: 422 MISSING_CASE(crtc_state->pipe_bpp); 423 break; 424 } 425 426 /* nonsense combination */ 427 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 428 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 429 430 if (crtc_state->limited_color_range) 431 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 432 433 /* 434 * As per DP 1.2 spec section 2.3.4.3 while sending 435 * YCBCR 444 signals we should program MSA MISC1/0 fields with 436 * colorspace information. 437 */ 438 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 439 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 440 441 /* 442 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 443 * of Color Encoding Format and Content Color Gamut] while sending 444 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 445 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 446 */ 447 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 448 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 449 450 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 451 temp); 452 } 453 454 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 455 { 456 if (master_transcoder == TRANSCODER_EDP) 457 return 0; 458 else 459 return master_transcoder + 1; 460 } 461 462 static void 463 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 464 bool enable) 465 { 466 struct intel_display *display = to_intel_display(crtc_state); 467 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 468 u32 val = 0; 469 470 if (!HAS_DP20(display)) 471 return; 472 473 if (enable && intel_dp_is_uhbr(crtc_state)) 474 val = TRANS_DP2_128B132B_CHANNEL_CODING; 475 476 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 477 } 478 479 /* 480 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 481 * 482 * Only intended to be used by intel_ddi_enable_transcoder_func() and 483 * intel_ddi_config_transcoder_func(). 484 */ 485 static u32 486 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 487 const struct intel_crtc_state *crtc_state) 488 { 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 enum pipe pipe = crtc->pipe; 492 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 493 enum port port = encoder->port; 494 u32 temp; 495 496 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 497 temp = TRANS_DDI_FUNC_ENABLE; 498 if (DISPLAY_VER(dev_priv) >= 12) 499 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 500 else 501 temp |= TRANS_DDI_SELECT_PORT(port); 502 503 switch (crtc_state->pipe_bpp) { 504 default: 505 MISSING_CASE(crtc_state->pipe_bpp); 506 fallthrough; 507 case 18: 508 temp |= TRANS_DDI_BPC_6; 509 break; 510 case 24: 511 temp |= TRANS_DDI_BPC_8; 512 break; 513 case 30: 514 temp |= TRANS_DDI_BPC_10; 515 break; 516 case 36: 517 temp |= TRANS_DDI_BPC_12; 518 break; 519 } 520 521 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 522 temp |= TRANS_DDI_PVSYNC; 523 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 524 temp |= TRANS_DDI_PHSYNC; 525 526 if (cpu_transcoder == TRANSCODER_EDP) { 527 switch (pipe) { 528 default: 529 MISSING_CASE(pipe); 530 fallthrough; 531 case PIPE_A: 532 /* On Haswell, can only use the always-on power well for 533 * eDP when not using the panel fitter, and when not 534 * using motion blur mitigation (which we don't 535 * support). */ 536 if (crtc_state->pch_pfit.force_thru) 537 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 538 else 539 temp |= TRANS_DDI_EDP_INPUT_A_ON; 540 break; 541 case PIPE_B: 542 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 543 break; 544 case PIPE_C: 545 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 546 break; 547 } 548 } 549 550 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 551 if (crtc_state->has_hdmi_sink) 552 temp |= TRANS_DDI_MODE_SELECT_HDMI; 553 else 554 temp |= TRANS_DDI_MODE_SELECT_DVI; 555 556 if (crtc_state->hdmi_scrambling) 557 temp |= TRANS_DDI_HDMI_SCRAMBLING; 558 if (crtc_state->hdmi_high_tmds_clock_ratio) 559 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 560 if (DISPLAY_VER(dev_priv) >= 14) 561 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 562 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 563 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 564 temp |= (crtc_state->fdi_lanes - 1) << 1; 565 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 566 intel_dp_is_uhbr(crtc_state)) { 567 if (intel_dp_is_uhbr(crtc_state)) 568 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 569 else 570 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 573 if (DISPLAY_VER(dev_priv) >= 12) { 574 enum transcoder master; 575 576 master = crtc_state->mst_master_transcoder; 577 drm_WARN_ON(&dev_priv->drm, 578 master == INVALID_TRANSCODER); 579 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 580 } 581 } else { 582 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 583 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 584 } 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 587 crtc_state->master_transcoder != INVALID_TRANSCODER) { 588 u8 master_select = 589 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 590 591 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 592 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 593 } 594 595 return temp; 596 } 597 598 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 599 const struct intel_crtc_state *crtc_state) 600 { 601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 603 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 604 605 if (DISPLAY_VER(dev_priv) >= 11) { 606 enum transcoder master_transcoder = crtc_state->master_transcoder; 607 u32 ctl2 = 0; 608 609 if (master_transcoder != INVALID_TRANSCODER) { 610 u8 master_select = 611 bdw_trans_port_sync_master_select(master_transcoder); 612 613 ctl2 |= PORT_SYNC_MODE_ENABLE | 614 PORT_SYNC_MODE_MASTER_SELECT(master_select); 615 } 616 617 intel_de_write(dev_priv, 618 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 619 ctl2); 620 } 621 622 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 623 intel_ddi_transcoder_func_reg_val_get(encoder, 624 crtc_state)); 625 } 626 627 /* 628 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 629 * bit for the DDI function and enables the DP2 configuration. Called for all 630 * transcoder types. 631 */ 632 void 633 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 634 const struct intel_crtc_state *crtc_state) 635 { 636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 638 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 639 u32 ctl; 640 641 intel_ddi_config_transcoder_dp2(crtc_state, true); 642 643 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 644 ctl &= ~TRANS_DDI_FUNC_ENABLE; 645 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 646 ctl); 647 } 648 649 /* 650 * Disable the DDI function and port syncing. 651 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 652 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 653 * transcoders these are done later in intel_ddi_post_disable_dp(). 654 */ 655 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 656 { 657 struct intel_display *display = to_intel_display(crtc_state); 658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 660 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 661 u32 ctl; 662 663 if (DISPLAY_VER(dev_priv) >= 11) 664 intel_de_write(dev_priv, 665 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 666 0); 667 668 ctl = intel_de_read(dev_priv, 669 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 670 671 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 672 673 ctl &= ~TRANS_DDI_FUNC_ENABLE; 674 675 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 676 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 677 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 678 679 if (DISPLAY_VER(dev_priv) >= 12) { 680 if (!intel_dp_mst_is_master_trans(crtc_state)) { 681 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 682 TRANS_DDI_MODE_SELECT_MASK); 683 } 684 } else { 685 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 686 } 687 688 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 689 ctl); 690 691 if (intel_dp_mst_is_slave_trans(crtc_state)) 692 intel_ddi_config_transcoder_dp2(crtc_state, false); 693 694 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 695 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 696 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 697 /* Quirk time at 100ms for reliable operation */ 698 msleep(100); 699 } 700 } 701 702 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 703 enum transcoder cpu_transcoder, 704 bool enable, u32 hdcp_mask) 705 { 706 struct drm_device *dev = intel_encoder->base.dev; 707 struct drm_i915_private *dev_priv = to_i915(dev); 708 intel_wakeref_t wakeref; 709 int ret = 0; 710 711 wakeref = intel_display_power_get_if_enabled(dev_priv, 712 intel_encoder->power_domain); 713 if (drm_WARN_ON(dev, !wakeref)) 714 return -ENXIO; 715 716 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 717 hdcp_mask, enable ? hdcp_mask : 0); 718 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 719 return ret; 720 } 721 722 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 723 { 724 struct intel_display *display = to_intel_display(intel_connector); 725 struct drm_i915_private *dev_priv = to_i915(display->drm); 726 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 727 int type = intel_connector->base.connector_type; 728 enum port port = encoder->port; 729 enum transcoder cpu_transcoder; 730 intel_wakeref_t wakeref; 731 enum pipe pipe = 0; 732 u32 ddi_mode; 733 bool ret; 734 735 wakeref = intel_display_power_get_if_enabled(dev_priv, 736 encoder->power_domain); 737 if (!wakeref) 738 return false; 739 740 /* Note: This returns false for DP MST primary encoders. */ 741 if (!encoder->get_hw_state(encoder, &pipe)) { 742 ret = false; 743 goto out; 744 } 745 746 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 747 cpu_transcoder = TRANSCODER_EDP; 748 else 749 cpu_transcoder = (enum transcoder) pipe; 750 751 ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 752 TRANS_DDI_MODE_SELECT_MASK; 753 754 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 755 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 756 ret = type == DRM_MODE_CONNECTOR_HDMIA; 757 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 758 ret = type == DRM_MODE_CONNECTOR_VGA; 759 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 760 ret = type == DRM_MODE_CONNECTOR_eDP || 761 type == DRM_MODE_CONNECTOR_DisplayPort; 762 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 763 /* 764 * encoder->get_hw_state() should have bailed out on MST. This 765 * must be SST and non-eDP. 766 */ 767 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 768 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 769 /* encoder->get_hw_state() should have bailed out on MST. */ 770 ret = false; 771 } else { 772 ret = false; 773 } 774 775 out: 776 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 777 778 return ret; 779 } 780 781 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 782 u8 *pipe_mask, bool *is_dp_mst) 783 { 784 struct intel_display *display = to_intel_display(encoder); 785 struct drm_i915_private *dev_priv = to_i915(display->drm); 786 enum port port = encoder->port; 787 intel_wakeref_t wakeref; 788 enum pipe p; 789 u32 tmp; 790 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 791 792 *pipe_mask = 0; 793 *is_dp_mst = false; 794 795 wakeref = intel_display_power_get_if_enabled(dev_priv, 796 encoder->power_domain); 797 if (!wakeref) 798 return; 799 800 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 801 if (!(tmp & DDI_BUF_CTL_ENABLE)) 802 goto out; 803 804 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 805 tmp = intel_de_read(dev_priv, 806 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 807 808 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 809 default: 810 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 811 fallthrough; 812 case TRANS_DDI_EDP_INPUT_A_ON: 813 case TRANS_DDI_EDP_INPUT_A_ONOFF: 814 *pipe_mask = BIT(PIPE_A); 815 break; 816 case TRANS_DDI_EDP_INPUT_B_ONOFF: 817 *pipe_mask = BIT(PIPE_B); 818 break; 819 case TRANS_DDI_EDP_INPUT_C_ONOFF: 820 *pipe_mask = BIT(PIPE_C); 821 break; 822 } 823 824 goto out; 825 } 826 827 for_each_pipe(dev_priv, p) { 828 enum transcoder cpu_transcoder = (enum transcoder)p; 829 u32 port_mask, ddi_select, ddi_mode; 830 intel_wakeref_t trans_wakeref; 831 832 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 833 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 834 if (!trans_wakeref) 835 continue; 836 837 if (DISPLAY_VER(dev_priv) >= 12) { 838 port_mask = TGL_TRANS_DDI_PORT_MASK; 839 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 840 } else { 841 port_mask = TRANS_DDI_PORT_MASK; 842 ddi_select = TRANS_DDI_SELECT_PORT(port); 843 } 844 845 tmp = intel_de_read(dev_priv, 846 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 847 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 848 trans_wakeref); 849 850 if ((tmp & port_mask) != ddi_select) 851 continue; 852 853 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 854 855 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 856 mst_pipe_mask |= BIT(p); 857 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 858 dp128b132b_pipe_mask |= BIT(p); 859 860 *pipe_mask |= BIT(p); 861 } 862 863 if (!*pipe_mask) 864 drm_dbg_kms(&dev_priv->drm, 865 "No pipe for [ENCODER:%d:%s] found\n", 866 encoder->base.base.id, encoder->base.name); 867 868 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 870 871 /* 872 * If we don't have 8b/10b MST, but have more than one 873 * transcoder in 128b/132b mode, we know it must be 128b/132b 874 * MST. 875 * 876 * Otherwise, we fall back to checking the current MST 877 * state. It's not accurate for hardware takeover at probe, but 878 * we don't expect MST to have been enabled at that point, and 879 * can assume it's SST. 880 */ 881 if (hweight8(dp128b132b_pipe_mask) > 1 || 882 intel_dp_mst_encoder_active_links(dig_port)) 883 mst_pipe_mask = dp128b132b_pipe_mask; 884 } 885 886 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 887 drm_dbg_kms(&dev_priv->drm, 888 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 889 encoder->base.base.id, encoder->base.name, 890 *pipe_mask); 891 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 892 } 893 894 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 895 drm_dbg_kms(&dev_priv->drm, 896 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 897 encoder->base.base.id, encoder->base.name, 898 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 899 else 900 *is_dp_mst = mst_pipe_mask; 901 902 out: 903 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 904 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 905 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 906 BXT_PHY_LANE_POWERDOWN_ACK | 907 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 908 drm_err(&dev_priv->drm, 909 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 910 encoder->base.base.id, encoder->base.name, tmp); 911 } 912 913 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 914 } 915 916 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 917 enum pipe *pipe) 918 { 919 u8 pipe_mask; 920 bool is_mst; 921 922 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 923 924 if (is_mst || !pipe_mask) 925 return false; 926 927 *pipe = ffs(pipe_mask) - 1; 928 929 return true; 930 } 931 932 static enum intel_display_power_domain 933 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 934 const struct intel_crtc_state *crtc_state) 935 { 936 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 937 938 /* 939 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 940 * DC states enabled at the same time, while for driver initiated AUX 941 * transfers we need the same AUX IOs to be powered but with DC states 942 * disabled. Accordingly use the AUX_IO_<port> power domain here which 943 * leaves DC states enabled. 944 * 945 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 946 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 947 * well, so we can acquire a wider AUX_<port> power domain reference 948 * instead of a specific AUX_IO_<port> reference without powering up any 949 * extra wells. 950 */ 951 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 952 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 953 else if (DISPLAY_VER(i915) < 14 && 954 (intel_crtc_has_dp_encoder(crtc_state) || 955 intel_encoder_is_tc(&dig_port->base))) 956 return intel_aux_power_domain(dig_port); 957 else 958 return POWER_DOMAIN_INVALID; 959 } 960 961 static void 962 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 963 const struct intel_crtc_state *crtc_state) 964 { 965 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 966 enum intel_display_power_domain domain = 967 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 968 969 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 970 971 if (domain == POWER_DOMAIN_INVALID) 972 return; 973 974 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 975 } 976 977 static void 978 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 979 const struct intel_crtc_state *crtc_state) 980 { 981 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 982 enum intel_display_power_domain domain = 983 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 984 intel_wakeref_t wf; 985 986 wf = fetch_and_zero(&dig_port->aux_wakeref); 987 if (!wf) 988 return; 989 990 intel_display_power_put(i915, domain, wf); 991 } 992 993 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 994 struct intel_crtc_state *crtc_state) 995 { 996 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 997 struct intel_digital_port *dig_port; 998 999 /* 1000 * TODO: Add support for MST encoders. Atm, the following should never 1001 * happen since fake-MST encoders don't set their get_power_domains() 1002 * hook. 1003 */ 1004 if (drm_WARN_ON(&dev_priv->drm, 1005 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1006 return; 1007 1008 dig_port = enc_to_dig_port(encoder); 1009 1010 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1011 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 1012 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 1013 dig_port->ddi_io_power_domain); 1014 } 1015 1016 main_link_aux_power_domain_get(dig_port, crtc_state); 1017 } 1018 1019 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1020 const struct intel_crtc_state *crtc_state) 1021 { 1022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1024 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1025 enum phy phy = intel_encoder_to_phy(encoder); 1026 u32 val; 1027 1028 if (cpu_transcoder == TRANSCODER_EDP) 1029 return; 1030 1031 if (DISPLAY_VER(dev_priv) >= 13) 1032 val = TGL_TRANS_CLK_SEL_PORT(phy); 1033 else if (DISPLAY_VER(dev_priv) >= 12) 1034 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1035 else 1036 val = TRANS_CLK_SEL_PORT(encoder->port); 1037 1038 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1039 } 1040 1041 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1042 { 1043 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1045 u32 val; 1046 1047 if (cpu_transcoder == TRANSCODER_EDP) 1048 return; 1049 1050 if (DISPLAY_VER(dev_priv) >= 12) 1051 val = TGL_TRANS_CLK_SEL_DISABLED; 1052 else 1053 val = TRANS_CLK_SEL_DISABLED; 1054 1055 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1056 } 1057 1058 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1059 enum port port, u8 iboost) 1060 { 1061 u32 tmp; 1062 1063 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1064 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1065 if (iboost) 1066 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1067 else 1068 tmp |= BALANCE_LEG_DISABLE(port); 1069 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1070 } 1071 1072 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1073 const struct intel_crtc_state *crtc_state, 1074 int level) 1075 { 1076 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1078 u8 iboost; 1079 1080 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1081 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1082 else 1083 iboost = intel_bios_dp_boost_level(encoder->devdata); 1084 1085 if (iboost == 0) { 1086 const struct intel_ddi_buf_trans *trans; 1087 int n_entries; 1088 1089 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1090 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1091 return; 1092 1093 iboost = trans->entries[level].hsw.i_boost; 1094 } 1095 1096 /* Make sure that the requested I_boost is valid */ 1097 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1098 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1099 return; 1100 } 1101 1102 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1103 1104 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1105 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1106 } 1107 1108 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1109 const struct intel_crtc_state *crtc_state) 1110 { 1111 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1113 int n_entries; 1114 1115 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1116 1117 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1118 n_entries = 1; 1119 if (drm_WARN_ON(&dev_priv->drm, 1120 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1121 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1122 1123 return index_to_dp_signal_levels[n_entries - 1] & 1124 DP_TRAIN_VOLTAGE_SWING_MASK; 1125 } 1126 1127 /* 1128 * We assume that the full set of pre-emphasis values can be 1129 * used on all DDI platforms. Should that change we need to 1130 * rethink this code. 1131 */ 1132 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1133 { 1134 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1135 } 1136 1137 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1138 int lane) 1139 { 1140 if (crtc_state->port_clock > 600000) 1141 return 0; 1142 1143 if (crtc_state->lane_count == 4) 1144 return lane >= 1 ? LOADGEN_SELECT : 0; 1145 else 1146 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1147 } 1148 1149 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1150 const struct intel_crtc_state *crtc_state) 1151 { 1152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1153 const struct intel_ddi_buf_trans *trans; 1154 enum phy phy = intel_encoder_to_phy(encoder); 1155 int n_entries, ln; 1156 u32 val; 1157 1158 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1159 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1160 return; 1161 1162 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1163 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1164 1165 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1166 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1167 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1168 intel_dp->hobl_active ? val : 0); 1169 } 1170 1171 /* Set PORT_TX_DW5 */ 1172 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1173 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1174 TAP2_DISABLE | TAP3_DISABLE); 1175 val |= SCALING_MODE_SEL(0x2); 1176 val |= RTERM_SELECT(0x6); 1177 val |= TAP3_DISABLE; 1178 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1179 1180 /* Program PORT_TX_DW2 */ 1181 for (ln = 0; ln < 4; ln++) { 1182 int level = intel_ddi_level(encoder, crtc_state, ln); 1183 1184 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1185 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1186 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1187 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1188 RCOMP_SCALAR(0x98)); 1189 } 1190 1191 /* Program PORT_TX_DW4 */ 1192 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1193 for (ln = 0; ln < 4; ln++) { 1194 int level = intel_ddi_level(encoder, crtc_state, ln); 1195 1196 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1197 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1198 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1199 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1200 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1201 } 1202 1203 /* Program PORT_TX_DW7 */ 1204 for (ln = 0; ln < 4; ln++) { 1205 int level = intel_ddi_level(encoder, crtc_state, ln); 1206 1207 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1208 N_SCALAR_MASK, 1209 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1210 } 1211 } 1212 1213 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1214 const struct intel_crtc_state *crtc_state) 1215 { 1216 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1217 enum phy phy = intel_encoder_to_phy(encoder); 1218 u32 val; 1219 int ln; 1220 1221 /* 1222 * 1. If port type is eDP or DP, 1223 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1224 * else clear to 0b. 1225 */ 1226 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1227 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1228 val &= ~COMMON_KEEPER_EN; 1229 else 1230 val |= COMMON_KEEPER_EN; 1231 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1232 1233 /* 2. Program loadgen select */ 1234 /* 1235 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1236 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1237 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1238 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1239 */ 1240 for (ln = 0; ln < 4; ln++) { 1241 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1242 LOADGEN_SELECT, 1243 icl_combo_phy_loadgen_select(crtc_state, ln)); 1244 } 1245 1246 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1247 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1248 0, SUS_CLOCK_CONFIG); 1249 1250 /* 4. Clear training enable to change swing values */ 1251 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1252 val &= ~TX_TRAINING_EN; 1253 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1254 1255 /* 5. Program swing and de-emphasis */ 1256 icl_ddi_combo_vswing_program(encoder, crtc_state); 1257 1258 /* 6. Set training enable to trigger update */ 1259 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1260 val |= TX_TRAINING_EN; 1261 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1262 } 1263 1264 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1265 const struct intel_crtc_state *crtc_state) 1266 { 1267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1268 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1269 const struct intel_ddi_buf_trans *trans; 1270 int n_entries, ln; 1271 1272 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1273 return; 1274 1275 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1276 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1277 return; 1278 1279 for (ln = 0; ln < 2; ln++) { 1280 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1281 CRI_USE_FS32, 0); 1282 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1283 CRI_USE_FS32, 0); 1284 } 1285 1286 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1287 for (ln = 0; ln < 2; ln++) { 1288 int level; 1289 1290 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1291 1292 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1293 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1294 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1295 1296 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1297 1298 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1299 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1300 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1301 } 1302 1303 /* Program MG_TX_DRVCTRL with values from vswing table */ 1304 for (ln = 0; ln < 2; ln++) { 1305 int level; 1306 1307 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1308 1309 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1310 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1311 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1312 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1313 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1314 CRI_TXDEEMPH_OVERRIDE_EN); 1315 1316 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1317 1318 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1319 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1320 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1321 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1322 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1323 CRI_TXDEEMPH_OVERRIDE_EN); 1324 1325 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1326 } 1327 1328 /* 1329 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1330 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1331 * values from table for which TX1 and TX2 enabled. 1332 */ 1333 for (ln = 0; ln < 2; ln++) { 1334 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1335 CFG_LOW_RATE_LKREN_EN, 1336 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1337 } 1338 1339 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1340 for (ln = 0; ln < 2; ln++) { 1341 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1342 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1343 CFG_AMI_CK_DIV_OVERRIDE_EN, 1344 crtc_state->port_clock > 500000 ? 1345 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1346 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1347 1348 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1349 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1350 CFG_AMI_CK_DIV_OVERRIDE_EN, 1351 crtc_state->port_clock > 500000 ? 1352 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1353 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1354 } 1355 1356 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1357 for (ln = 0; ln < 2; ln++) { 1358 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1359 0, CRI_CALCINIT); 1360 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1361 0, CRI_CALCINIT); 1362 } 1363 } 1364 1365 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1366 const struct intel_crtc_state *crtc_state) 1367 { 1368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1369 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1370 const struct intel_ddi_buf_trans *trans; 1371 int n_entries, ln; 1372 1373 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1374 return; 1375 1376 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1377 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1378 return; 1379 1380 for (ln = 0; ln < 2; ln++) { 1381 int level; 1382 1383 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1384 1385 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1386 1387 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1388 DKL_TX_PRESHOOT_COEFF_MASK | 1389 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1390 DKL_TX_VSWING_CONTROL_MASK, 1391 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1392 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1393 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1394 1395 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1396 1397 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1398 DKL_TX_PRESHOOT_COEFF_MASK | 1399 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1400 DKL_TX_VSWING_CONTROL_MASK, 1401 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1402 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1403 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1404 1405 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1406 DKL_TX_DP20BITMODE, 0); 1407 1408 if (IS_ALDERLAKE_P(dev_priv)) { 1409 u32 val; 1410 1411 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1412 if (ln == 0) { 1413 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1414 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1415 } else { 1416 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1417 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1418 } 1419 } else { 1420 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1421 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1422 } 1423 1424 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1425 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1426 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1427 val); 1428 } 1429 } 1430 } 1431 1432 static int translate_signal_level(struct intel_dp *intel_dp, 1433 u8 signal_levels) 1434 { 1435 struct intel_display *display = to_intel_display(intel_dp); 1436 int i; 1437 1438 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1439 if (index_to_dp_signal_levels[i] == signal_levels) 1440 return i; 1441 } 1442 1443 drm_WARN(display->drm, 1, 1444 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1445 signal_levels); 1446 1447 return 0; 1448 } 1449 1450 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1451 const struct intel_crtc_state *crtc_state, 1452 int lane) 1453 { 1454 u8 train_set = intel_dp->train_set[lane]; 1455 1456 if (intel_dp_is_uhbr(crtc_state)) { 1457 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1458 } else { 1459 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1460 DP_TRAIN_PRE_EMPHASIS_MASK); 1461 1462 return translate_signal_level(intel_dp, signal_levels); 1463 } 1464 } 1465 1466 int intel_ddi_level(struct intel_encoder *encoder, 1467 const struct intel_crtc_state *crtc_state, 1468 int lane) 1469 { 1470 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1471 const struct intel_ddi_buf_trans *trans; 1472 int level, n_entries; 1473 1474 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1475 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1476 return 0; 1477 1478 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1479 level = intel_ddi_hdmi_level(encoder, trans); 1480 else 1481 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1482 lane); 1483 1484 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1485 level = n_entries - 1; 1486 1487 return level; 1488 } 1489 1490 static void 1491 hsw_set_signal_levels(struct intel_encoder *encoder, 1492 const struct intel_crtc_state *crtc_state) 1493 { 1494 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1495 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1496 int level = intel_ddi_level(encoder, crtc_state, 0); 1497 enum port port = encoder->port; 1498 u32 signal_levels; 1499 1500 if (has_iboost(dev_priv)) 1501 skl_ddi_set_iboost(encoder, crtc_state, level); 1502 1503 /* HDMI ignores the rest */ 1504 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1505 return; 1506 1507 signal_levels = DDI_BUF_TRANS_SELECT(level); 1508 1509 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1510 signal_levels); 1511 1512 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1513 intel_dp->DP |= signal_levels; 1514 1515 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1516 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1517 } 1518 1519 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1520 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1521 { 1522 mutex_lock(&i915->display.dpll.lock); 1523 1524 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1525 1526 /* 1527 * "This step and the step before must be 1528 * done with separate register writes." 1529 */ 1530 intel_de_rmw(i915, reg, clk_off, 0); 1531 1532 mutex_unlock(&i915->display.dpll.lock); 1533 } 1534 1535 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1536 u32 clk_off) 1537 { 1538 mutex_lock(&i915->display.dpll.lock); 1539 1540 intel_de_rmw(i915, reg, 0, clk_off); 1541 1542 mutex_unlock(&i915->display.dpll.lock); 1543 } 1544 1545 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1546 u32 clk_off) 1547 { 1548 return !(intel_de_read(i915, reg) & clk_off); 1549 } 1550 1551 static struct intel_shared_dpll * 1552 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1553 u32 clk_sel_mask, u32 clk_sel_shift) 1554 { 1555 enum intel_dpll_id id; 1556 1557 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1558 1559 return intel_get_shared_dpll_by_id(i915, id); 1560 } 1561 1562 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1563 const struct intel_crtc_state *crtc_state) 1564 { 1565 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1566 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1567 enum phy phy = intel_encoder_to_phy(encoder); 1568 1569 if (drm_WARN_ON(&i915->drm, !pll)) 1570 return; 1571 1572 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1573 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1574 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1575 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1576 } 1577 1578 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1579 { 1580 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1581 enum phy phy = intel_encoder_to_phy(encoder); 1582 1583 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1584 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1585 } 1586 1587 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1588 { 1589 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1590 enum phy phy = intel_encoder_to_phy(encoder); 1591 1592 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1593 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1594 } 1595 1596 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1597 { 1598 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1599 enum phy phy = intel_encoder_to_phy(encoder); 1600 1601 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1602 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1603 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1604 } 1605 1606 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1607 const struct intel_crtc_state *crtc_state) 1608 { 1609 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1610 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1611 enum phy phy = intel_encoder_to_phy(encoder); 1612 1613 if (drm_WARN_ON(&i915->drm, !pll)) 1614 return; 1615 1616 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1617 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1618 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1619 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1620 } 1621 1622 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1623 { 1624 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1625 enum phy phy = intel_encoder_to_phy(encoder); 1626 1627 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1628 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1629 } 1630 1631 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1632 { 1633 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1634 enum phy phy = intel_encoder_to_phy(encoder); 1635 1636 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1637 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1638 } 1639 1640 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1641 { 1642 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1643 enum phy phy = intel_encoder_to_phy(encoder); 1644 1645 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1646 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1647 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1648 } 1649 1650 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1651 const struct intel_crtc_state *crtc_state) 1652 { 1653 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1654 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1655 enum phy phy = intel_encoder_to_phy(encoder); 1656 1657 if (drm_WARN_ON(&i915->drm, !pll)) 1658 return; 1659 1660 /* 1661 * If we fail this, something went very wrong: first 2 PLLs should be 1662 * used by first 2 phys and last 2 PLLs by last phys 1663 */ 1664 if (drm_WARN_ON(&i915->drm, 1665 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1666 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1667 return; 1668 1669 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1670 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1671 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1672 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1673 } 1674 1675 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1676 { 1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1678 enum phy phy = intel_encoder_to_phy(encoder); 1679 1680 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1681 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1682 } 1683 1684 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1685 { 1686 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1687 enum phy phy = intel_encoder_to_phy(encoder); 1688 1689 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1690 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1691 } 1692 1693 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1694 { 1695 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1696 enum phy phy = intel_encoder_to_phy(encoder); 1697 enum intel_dpll_id id; 1698 u32 val; 1699 1700 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1701 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1702 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1703 id = val; 1704 1705 /* 1706 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1707 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1708 * bit for phy C and D. 1709 */ 1710 if (phy >= PHY_C) 1711 id += DPLL_ID_DG1_DPLL2; 1712 1713 return intel_get_shared_dpll_by_id(i915, id); 1714 } 1715 1716 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1717 const struct intel_crtc_state *crtc_state) 1718 { 1719 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1720 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1721 enum phy phy = intel_encoder_to_phy(encoder); 1722 1723 if (drm_WARN_ON(&i915->drm, !pll)) 1724 return; 1725 1726 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1727 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1728 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1729 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1730 } 1731 1732 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1733 { 1734 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1735 enum phy phy = intel_encoder_to_phy(encoder); 1736 1737 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1738 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1739 } 1740 1741 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1742 { 1743 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1744 enum phy phy = intel_encoder_to_phy(encoder); 1745 1746 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1747 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1748 } 1749 1750 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1751 { 1752 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1753 enum phy phy = intel_encoder_to_phy(encoder); 1754 1755 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1756 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1757 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1758 } 1759 1760 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1761 const struct intel_crtc_state *crtc_state) 1762 { 1763 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1764 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1765 enum port port = encoder->port; 1766 1767 if (drm_WARN_ON(&i915->drm, !pll)) 1768 return; 1769 1770 /* 1771 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1772 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1773 */ 1774 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1775 1776 icl_ddi_combo_enable_clock(encoder, crtc_state); 1777 } 1778 1779 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1780 { 1781 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1782 enum port port = encoder->port; 1783 1784 icl_ddi_combo_disable_clock(encoder); 1785 1786 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1787 } 1788 1789 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1790 { 1791 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1792 enum port port = encoder->port; 1793 u32 tmp; 1794 1795 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1796 1797 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1798 return false; 1799 1800 return icl_ddi_combo_is_clock_enabled(encoder); 1801 } 1802 1803 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1804 const struct intel_crtc_state *crtc_state) 1805 { 1806 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1807 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1808 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1809 enum port port = encoder->port; 1810 1811 if (drm_WARN_ON(&i915->drm, !pll)) 1812 return; 1813 1814 intel_de_write(i915, DDI_CLK_SEL(port), 1815 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1816 1817 mutex_lock(&i915->display.dpll.lock); 1818 1819 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1820 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1821 1822 mutex_unlock(&i915->display.dpll.lock); 1823 } 1824 1825 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1826 { 1827 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1828 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1829 enum port port = encoder->port; 1830 1831 mutex_lock(&i915->display.dpll.lock); 1832 1833 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1834 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1835 1836 mutex_unlock(&i915->display.dpll.lock); 1837 1838 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1839 } 1840 1841 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1842 { 1843 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1844 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1845 enum port port = encoder->port; 1846 u32 tmp; 1847 1848 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1849 1850 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1851 return false; 1852 1853 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1854 1855 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1856 } 1857 1858 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1859 { 1860 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1861 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1862 enum port port = encoder->port; 1863 enum intel_dpll_id id; 1864 u32 tmp; 1865 1866 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1867 1868 switch (tmp & DDI_CLK_SEL_MASK) { 1869 case DDI_CLK_SEL_TBT_162: 1870 case DDI_CLK_SEL_TBT_270: 1871 case DDI_CLK_SEL_TBT_540: 1872 case DDI_CLK_SEL_TBT_810: 1873 id = DPLL_ID_ICL_TBTPLL; 1874 break; 1875 case DDI_CLK_SEL_MG: 1876 id = icl_tc_port_to_pll_id(tc_port); 1877 break; 1878 default: 1879 MISSING_CASE(tmp); 1880 fallthrough; 1881 case DDI_CLK_SEL_NONE: 1882 return NULL; 1883 } 1884 1885 return intel_get_shared_dpll_by_id(i915, id); 1886 } 1887 1888 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1889 { 1890 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1891 enum intel_dpll_id id; 1892 1893 switch (encoder->port) { 1894 case PORT_A: 1895 id = DPLL_ID_SKL_DPLL0; 1896 break; 1897 case PORT_B: 1898 id = DPLL_ID_SKL_DPLL1; 1899 break; 1900 case PORT_C: 1901 id = DPLL_ID_SKL_DPLL2; 1902 break; 1903 default: 1904 MISSING_CASE(encoder->port); 1905 return NULL; 1906 } 1907 1908 return intel_get_shared_dpll_by_id(i915, id); 1909 } 1910 1911 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1912 const struct intel_crtc_state *crtc_state) 1913 { 1914 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1915 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1916 enum port port = encoder->port; 1917 1918 if (drm_WARN_ON(&i915->drm, !pll)) 1919 return; 1920 1921 mutex_lock(&i915->display.dpll.lock); 1922 1923 intel_de_rmw(i915, DPLL_CTRL2, 1924 DPLL_CTRL2_DDI_CLK_OFF(port) | 1925 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1926 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1927 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1928 1929 mutex_unlock(&i915->display.dpll.lock); 1930 } 1931 1932 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1933 { 1934 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1935 enum port port = encoder->port; 1936 1937 mutex_lock(&i915->display.dpll.lock); 1938 1939 intel_de_rmw(i915, DPLL_CTRL2, 1940 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1941 1942 mutex_unlock(&i915->display.dpll.lock); 1943 } 1944 1945 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1946 { 1947 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1948 enum port port = encoder->port; 1949 1950 /* 1951 * FIXME Not sure if the override affects both 1952 * the PLL selection and the CLK_OFF bit. 1953 */ 1954 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1955 } 1956 1957 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1958 { 1959 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1960 enum port port = encoder->port; 1961 enum intel_dpll_id id; 1962 u32 tmp; 1963 1964 tmp = intel_de_read(i915, DPLL_CTRL2); 1965 1966 /* 1967 * FIXME Not sure if the override affects both 1968 * the PLL selection and the CLK_OFF bit. 1969 */ 1970 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1971 return NULL; 1972 1973 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1974 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1975 1976 return intel_get_shared_dpll_by_id(i915, id); 1977 } 1978 1979 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1980 const struct intel_crtc_state *crtc_state) 1981 { 1982 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1983 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1984 enum port port = encoder->port; 1985 1986 if (drm_WARN_ON(&i915->drm, !pll)) 1987 return; 1988 1989 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1990 } 1991 1992 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1993 { 1994 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1995 enum port port = encoder->port; 1996 1997 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1998 } 1999 2000 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2001 { 2002 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2003 enum port port = encoder->port; 2004 2005 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2006 } 2007 2008 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2009 { 2010 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2011 enum port port = encoder->port; 2012 enum intel_dpll_id id; 2013 u32 tmp; 2014 2015 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2016 2017 switch (tmp & PORT_CLK_SEL_MASK) { 2018 case PORT_CLK_SEL_WRPLL1: 2019 id = DPLL_ID_WRPLL1; 2020 break; 2021 case PORT_CLK_SEL_WRPLL2: 2022 id = DPLL_ID_WRPLL2; 2023 break; 2024 case PORT_CLK_SEL_SPLL: 2025 id = DPLL_ID_SPLL; 2026 break; 2027 case PORT_CLK_SEL_LCPLL_810: 2028 id = DPLL_ID_LCPLL_810; 2029 break; 2030 case PORT_CLK_SEL_LCPLL_1350: 2031 id = DPLL_ID_LCPLL_1350; 2032 break; 2033 case PORT_CLK_SEL_LCPLL_2700: 2034 id = DPLL_ID_LCPLL_2700; 2035 break; 2036 default: 2037 MISSING_CASE(tmp); 2038 fallthrough; 2039 case PORT_CLK_SEL_NONE: 2040 return NULL; 2041 } 2042 2043 return intel_get_shared_dpll_by_id(i915, id); 2044 } 2045 2046 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2047 const struct intel_crtc_state *crtc_state) 2048 { 2049 if (encoder->enable_clock) 2050 encoder->enable_clock(encoder, crtc_state); 2051 } 2052 2053 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2054 { 2055 if (encoder->disable_clock) 2056 encoder->disable_clock(encoder); 2057 } 2058 2059 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2060 { 2061 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2062 u32 port_mask; 2063 bool ddi_clk_needed; 2064 2065 /* 2066 * In case of DP MST, we sanitize the primary encoder only, not the 2067 * virtual ones. 2068 */ 2069 if (encoder->type == INTEL_OUTPUT_DP_MST) 2070 return; 2071 2072 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2073 u8 pipe_mask; 2074 bool is_mst; 2075 2076 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2077 /* 2078 * In the unlikely case that BIOS enables DP in MST mode, just 2079 * warn since our MST HW readout is incomplete. 2080 */ 2081 if (drm_WARN_ON(&i915->drm, is_mst)) 2082 return; 2083 } 2084 2085 port_mask = BIT(encoder->port); 2086 ddi_clk_needed = encoder->base.crtc; 2087 2088 if (encoder->type == INTEL_OUTPUT_DSI) { 2089 struct intel_encoder *other_encoder; 2090 2091 port_mask = intel_dsi_encoder_ports(encoder); 2092 /* 2093 * Sanity check that we haven't incorrectly registered another 2094 * encoder using any of the ports of this DSI encoder. 2095 */ 2096 for_each_intel_encoder(&i915->drm, other_encoder) { 2097 if (other_encoder == encoder) 2098 continue; 2099 2100 if (drm_WARN_ON(&i915->drm, 2101 port_mask & BIT(other_encoder->port))) 2102 return; 2103 } 2104 /* 2105 * For DSI we keep the ddi clocks gated 2106 * except during enable/disable sequence. 2107 */ 2108 ddi_clk_needed = false; 2109 } 2110 2111 if (ddi_clk_needed || !encoder->is_clock_enabled || 2112 !encoder->is_clock_enabled(encoder)) 2113 return; 2114 2115 drm_dbg_kms(&i915->drm, 2116 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2117 encoder->base.base.id, encoder->base.name); 2118 2119 encoder->disable_clock(encoder); 2120 } 2121 2122 static void 2123 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2124 const struct intel_crtc_state *crtc_state) 2125 { 2126 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2127 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2128 u32 ln0, ln1, pin_assignment; 2129 u8 width; 2130 2131 if (DISPLAY_VER(dev_priv) >= 14) 2132 return; 2133 2134 if (!intel_encoder_is_tc(&dig_port->base) || 2135 intel_tc_port_in_tbt_alt_mode(dig_port)) 2136 return; 2137 2138 if (DISPLAY_VER(dev_priv) >= 12) { 2139 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2140 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2141 } else { 2142 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2143 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2144 } 2145 2146 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2147 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2148 2149 /* DPPATC */ 2150 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2151 width = crtc_state->lane_count; 2152 2153 switch (pin_assignment) { 2154 case 0x0: 2155 drm_WARN_ON(&dev_priv->drm, 2156 !intel_tc_port_in_legacy_mode(dig_port)); 2157 if (width == 1) { 2158 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2159 } else { 2160 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2161 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2162 } 2163 break; 2164 case 0x1: 2165 if (width == 4) { 2166 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2167 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2168 } 2169 break; 2170 case 0x2: 2171 if (width == 2) { 2172 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2173 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2174 } 2175 break; 2176 case 0x3: 2177 case 0x5: 2178 if (width == 1) { 2179 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2180 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2181 } else { 2182 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2183 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2184 } 2185 break; 2186 case 0x4: 2187 case 0x6: 2188 if (width == 1) { 2189 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2190 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2191 } else { 2192 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2193 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2194 } 2195 break; 2196 default: 2197 MISSING_CASE(pin_assignment); 2198 } 2199 2200 if (DISPLAY_VER(dev_priv) >= 12) { 2201 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2202 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2203 } else { 2204 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2205 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2206 } 2207 } 2208 2209 static enum transcoder 2210 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2211 { 2212 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2213 return crtc_state->mst_master_transcoder; 2214 else 2215 return crtc_state->cpu_transcoder; 2216 } 2217 2218 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2219 const struct intel_crtc_state *crtc_state) 2220 { 2221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2222 2223 if (DISPLAY_VER(dev_priv) >= 12) 2224 return TGL_DP_TP_CTL(dev_priv, 2225 tgl_dp_tp_transcoder(crtc_state)); 2226 else 2227 return DP_TP_CTL(encoder->port); 2228 } 2229 2230 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2231 const struct intel_crtc_state *crtc_state) 2232 { 2233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2234 2235 if (DISPLAY_VER(dev_priv) >= 12) 2236 return TGL_DP_TP_STATUS(dev_priv, 2237 tgl_dp_tp_transcoder(crtc_state)); 2238 else 2239 return DP_TP_STATUS(encoder->port); 2240 } 2241 2242 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2243 const struct intel_crtc_state *crtc_state) 2244 { 2245 struct intel_display *display = to_intel_display(encoder); 2246 2247 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2248 DP_TP_STATUS_ACT_SENT); 2249 } 2250 2251 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2252 const struct intel_crtc_state *crtc_state) 2253 { 2254 struct intel_display *display = to_intel_display(encoder); 2255 2256 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2257 DP_TP_STATUS_ACT_SENT, 1)) 2258 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2259 } 2260 2261 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2262 const struct intel_crtc_state *crtc_state, 2263 bool enable) 2264 { 2265 struct intel_display *display = to_intel_display(intel_dp); 2266 2267 if (!crtc_state->vrr.enable) 2268 return; 2269 2270 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2271 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2272 drm_dbg_kms(display->drm, 2273 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2274 str_enable_disable(enable)); 2275 } 2276 2277 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2278 const struct intel_crtc_state *crtc_state, 2279 bool enable) 2280 { 2281 struct intel_display *display = to_intel_display(intel_dp); 2282 2283 if (!crtc_state->fec_enable) 2284 return; 2285 2286 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2287 enable ? DP_FEC_READY : 0) <= 0) 2288 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2289 str_enabled_disabled(enable)); 2290 2291 if (enable && 2292 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2293 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2294 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2295 } 2296 2297 static int read_fec_detected_status(struct drm_dp_aux *aux) 2298 { 2299 int ret; 2300 u8 status; 2301 2302 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2303 if (ret < 0) 2304 return ret; 2305 2306 return status; 2307 } 2308 2309 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2310 { 2311 struct intel_display *display = to_intel_display(aux->drm_dev); 2312 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2313 int status; 2314 int err; 2315 2316 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2317 status & mask || status < 0, 2318 10000, 200000); 2319 2320 if (err || status < 0) { 2321 drm_dbg_kms(display->drm, 2322 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2323 str_enabled_disabled(enabled), err, status); 2324 return err ? err : status; 2325 } 2326 2327 return 0; 2328 } 2329 2330 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2331 const struct intel_crtc_state *crtc_state, 2332 bool enabled) 2333 { 2334 struct intel_display *display = to_intel_display(encoder); 2335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2336 int ret; 2337 2338 if (!crtc_state->fec_enable) 2339 return 0; 2340 2341 if (enabled) 2342 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2343 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2344 else 2345 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2346 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2347 2348 if (ret) { 2349 drm_err(display->drm, 2350 "Timeout waiting for FEC live state to get %s\n", 2351 str_enabled_disabled(enabled)); 2352 return ret; 2353 } 2354 /* 2355 * At least the Synoptics MST hub doesn't set the detected flag for 2356 * FEC decoding disabling so skip waiting for that. 2357 */ 2358 if (enabled) { 2359 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2360 if (ret) 2361 return ret; 2362 } 2363 2364 return 0; 2365 } 2366 2367 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2368 const struct intel_crtc_state *crtc_state) 2369 { 2370 struct intel_display *display = to_intel_display(encoder); 2371 int i; 2372 int ret; 2373 2374 if (!crtc_state->fec_enable) 2375 return; 2376 2377 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2378 0, DP_TP_CTL_FEC_ENABLE); 2379 2380 if (DISPLAY_VER(display) < 30) 2381 return; 2382 2383 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2384 if (!ret) 2385 return; 2386 2387 for (i = 0; i < 3; i++) { 2388 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2389 2390 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2391 DP_TP_CTL_FEC_ENABLE, 0); 2392 2393 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2394 if (ret) 2395 continue; 2396 2397 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2398 0, DP_TP_CTL_FEC_ENABLE); 2399 2400 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2401 if (!ret) 2402 return; 2403 } 2404 2405 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2406 } 2407 2408 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2409 const struct intel_crtc_state *crtc_state) 2410 { 2411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2412 2413 if (!crtc_state->fec_enable) 2414 return; 2415 2416 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2417 DP_TP_CTL_FEC_ENABLE, 0); 2418 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2419 } 2420 2421 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2422 const struct intel_crtc_state *crtc_state) 2423 { 2424 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2425 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2426 2427 if (intel_encoder_is_combo(encoder)) { 2428 enum phy phy = intel_encoder_to_phy(encoder); 2429 2430 intel_combo_phy_power_up_lanes(i915, phy, false, 2431 crtc_state->lane_count, 2432 dig_port->lane_reversal); 2433 } 2434 } 2435 2436 /* 2437 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2438 * platforms. 2439 */ 2440 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2441 { 2442 if (DISPLAY_VER(i915) > 20) 2443 return ~0; 2444 else if (IS_ALDERLAKE_P(i915)) 2445 return BIT(PIPE_A) | BIT(PIPE_B); 2446 else 2447 return BIT(PIPE_A); 2448 } 2449 2450 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2451 struct intel_crtc_state *pipe_config) 2452 { 2453 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2454 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2455 enum pipe pipe = crtc->pipe; 2456 u32 dss1; 2457 2458 if (!HAS_MSO(i915)) 2459 return; 2460 2461 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2462 2463 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2464 if (!pipe_config->splitter.enable) 2465 return; 2466 2467 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2468 pipe_config->splitter.enable = false; 2469 return; 2470 } 2471 2472 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2473 default: 2474 drm_WARN(&i915->drm, true, 2475 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2476 fallthrough; 2477 case SPLITTER_CONFIGURATION_2_SEGMENT: 2478 pipe_config->splitter.link_count = 2; 2479 break; 2480 case SPLITTER_CONFIGURATION_4_SEGMENT: 2481 pipe_config->splitter.link_count = 4; 2482 break; 2483 } 2484 2485 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2486 } 2487 2488 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2489 { 2490 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2491 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2492 enum pipe pipe = crtc->pipe; 2493 u32 dss1 = 0; 2494 2495 if (!HAS_MSO(i915)) 2496 return; 2497 2498 if (crtc_state->splitter.enable) { 2499 dss1 |= SPLITTER_ENABLE; 2500 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2501 if (crtc_state->splitter.link_count == 2) 2502 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2503 else 2504 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2505 } 2506 2507 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2508 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2509 OVERLAP_PIXELS_MASK, dss1); 2510 } 2511 2512 static u8 mtl_get_port_width(u8 lane_count) 2513 { 2514 switch (lane_count) { 2515 case 1: 2516 return 0; 2517 case 2: 2518 return 1; 2519 case 3: 2520 return 4; 2521 case 4: 2522 return 3; 2523 default: 2524 MISSING_CASE(lane_count); 2525 return 4; 2526 } 2527 } 2528 2529 static void 2530 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2531 { 2532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2533 enum port port = encoder->port; 2534 i915_reg_t reg; 2535 u32 set_bits, wait_bits; 2536 2537 if (DISPLAY_VER(dev_priv) >= 20) { 2538 reg = DDI_BUF_CTL(port); 2539 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2540 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2541 } else { 2542 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2543 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2544 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2545 } 2546 2547 intel_de_rmw(dev_priv, reg, 0, set_bits); 2548 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2549 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2550 port_name(port)); 2551 } 2552 } 2553 2554 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2555 const struct intel_crtc_state *crtc_state) 2556 { 2557 struct intel_display *display = to_intel_display(encoder); 2558 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2559 enum port port = encoder->port; 2560 u32 val = 0; 2561 2562 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2563 2564 if (intel_dp_is_uhbr(crtc_state)) 2565 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2566 else 2567 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2568 2569 if (dig_port->lane_reversal) 2570 val |= XELPDP_PORT_REVERSAL; 2571 2572 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2573 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2574 val); 2575 } 2576 2577 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2578 { 2579 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2580 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2581 u32 val; 2582 2583 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2584 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2585 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2586 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2587 } 2588 2589 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2590 struct intel_encoder *encoder, 2591 const struct intel_crtc_state *crtc_state, 2592 const struct drm_connector_state *conn_state) 2593 { 2594 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2595 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2596 int ret; 2597 2598 intel_dp_set_link_params(intel_dp, 2599 crtc_state->port_clock, 2600 crtc_state->lane_count); 2601 2602 /* 2603 * We only configure what the register value will be here. Actual 2604 * enabling happens during link training farther down. 2605 */ 2606 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2607 2608 /* 2609 * 1. Enable Power Wells 2610 * 2611 * This was handled at the beginning of intel_atomic_commit_tail(), 2612 * before we called down into this function. 2613 */ 2614 2615 /* 2. PMdemand was already set */ 2616 2617 /* 3. Select Thunderbolt */ 2618 mtl_port_buf_ctl_io_selection(encoder); 2619 2620 /* 4. Enable Panel Power if PPS is required */ 2621 intel_pps_on(intel_dp); 2622 2623 /* 5. Enable the port PLL */ 2624 intel_ddi_enable_clock(encoder, crtc_state); 2625 2626 /* 2627 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2628 * Transcoder. 2629 */ 2630 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2631 2632 /* 2633 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2634 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2635 * Transport Select 2636 */ 2637 intel_ddi_config_transcoder_func(encoder, crtc_state); 2638 2639 /* 2640 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2641 */ 2642 intel_ddi_mso_configure(crtc_state); 2643 2644 if (!is_mst) 2645 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2646 2647 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2648 if (!is_mst) 2649 intel_dp_sink_enable_decompression(state, 2650 to_intel_connector(conn_state->connector), 2651 crtc_state); 2652 2653 /* 2654 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2655 * in the FEC_CONFIGURATION register to 1 before initiating link 2656 * training 2657 */ 2658 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2659 2660 intel_dp_check_frl_training(intel_dp); 2661 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2662 2663 /* 2664 * 6. The rest of the below are substeps under the bspec's "Enable and 2665 * Train Display Port" step. Note that steps that are specific to 2666 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2667 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2668 * us when active_mst_links==0, so any steps designated for "single 2669 * stream or multi-stream master transcoder" can just be performed 2670 * unconditionally here. 2671 * 2672 * mtl_ddi_prepare_link_retrain() that is called by 2673 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2674 * 6.i and 6.j 2675 * 2676 * 6.k Follow DisplayPort specification training sequence (see notes for 2677 * failure handling) 2678 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2679 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2680 * (timeout after 800 us) 2681 */ 2682 intel_dp_start_link_train(state, intel_dp, crtc_state); 2683 2684 /* 6.n Set DP_TP_CTL link training to Normal */ 2685 if (!is_trans_port_sync_mode(crtc_state)) 2686 intel_dp_stop_link_train(intel_dp, crtc_state); 2687 2688 /* 6.o Configure and enable FEC if needed */ 2689 intel_ddi_enable_fec(encoder, crtc_state); 2690 2691 /* 7.a 128b/132b SST. */ 2692 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2693 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2694 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2695 if (ret < 0) 2696 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2697 } 2698 2699 if (!is_mst) 2700 intel_dsc_dp_pps_write(encoder, crtc_state); 2701 } 2702 2703 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2704 struct intel_encoder *encoder, 2705 const struct intel_crtc_state *crtc_state, 2706 const struct drm_connector_state *conn_state) 2707 { 2708 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2710 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2711 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2712 int ret; 2713 2714 intel_dp_set_link_params(intel_dp, 2715 crtc_state->port_clock, 2716 crtc_state->lane_count); 2717 2718 /* 2719 * We only configure what the register value will be here. Actual 2720 * enabling happens during link training farther down. 2721 */ 2722 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2723 2724 /* 2725 * 1. Enable Power Wells 2726 * 2727 * This was handled at the beginning of intel_atomic_commit_tail(), 2728 * before we called down into this function. 2729 */ 2730 2731 /* 2. Enable Panel Power if PPS is required */ 2732 intel_pps_on(intel_dp); 2733 2734 /* 2735 * 3. For non-TBT Type-C ports, set FIA lane count 2736 * (DFLEXDPSP.DPX4TXLATC) 2737 * 2738 * This was done before tgl_ddi_pre_enable_dp by 2739 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2740 */ 2741 2742 /* 2743 * 4. Enable the port PLL. 2744 * 2745 * The PLL enabling itself was already done before this function by 2746 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2747 * configure the PLL to port mapping here. 2748 */ 2749 intel_ddi_enable_clock(encoder, crtc_state); 2750 2751 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2752 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2753 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2754 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2755 dig_port->ddi_io_power_domain); 2756 } 2757 2758 /* 6. Program DP_MODE */ 2759 icl_program_mg_dp_mode(dig_port, crtc_state); 2760 2761 /* 2762 * 7. The rest of the below are substeps under the bspec's "Enable and 2763 * Train Display Port" step. Note that steps that are specific to 2764 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2765 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2766 * us when active_mst_links==0, so any steps designated for "single 2767 * stream or multi-stream master transcoder" can just be performed 2768 * unconditionally here. 2769 */ 2770 2771 /* 2772 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2773 * Transcoder. 2774 */ 2775 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2776 2777 /* 2778 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2779 * Transport Select 2780 */ 2781 intel_ddi_config_transcoder_func(encoder, crtc_state); 2782 2783 /* 2784 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2785 * selected 2786 * 2787 * This will be handled by the intel_dp_start_link_train() farther 2788 * down this function. 2789 */ 2790 2791 /* 7.e Configure voltage swing and related IO settings */ 2792 encoder->set_signal_levels(encoder, crtc_state); 2793 2794 /* 2795 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2796 * the used lanes of the DDI. 2797 */ 2798 intel_ddi_power_up_lanes(encoder, crtc_state); 2799 2800 /* 2801 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2802 */ 2803 intel_ddi_mso_configure(crtc_state); 2804 2805 if (!is_mst) 2806 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2807 2808 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2809 if (!is_mst) 2810 intel_dp_sink_enable_decompression(state, 2811 to_intel_connector(conn_state->connector), 2812 crtc_state); 2813 /* 2814 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2815 * in the FEC_CONFIGURATION register to 1 before initiating link 2816 * training 2817 */ 2818 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2819 2820 intel_dp_check_frl_training(intel_dp); 2821 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2822 2823 /* 2824 * 7.i Follow DisplayPort specification training sequence (see notes for 2825 * failure handling) 2826 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2827 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2828 * (timeout after 800 us) 2829 */ 2830 intel_dp_start_link_train(state, intel_dp, crtc_state); 2831 2832 /* 7.k Set DP_TP_CTL link training to Normal */ 2833 if (!is_trans_port_sync_mode(crtc_state)) 2834 intel_dp_stop_link_train(intel_dp, crtc_state); 2835 2836 /* 7.l Configure and enable FEC if needed */ 2837 intel_ddi_enable_fec(encoder, crtc_state); 2838 2839 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2840 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2841 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2842 if (ret < 0) 2843 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2844 } 2845 2846 if (!is_mst) 2847 intel_dsc_dp_pps_write(encoder, crtc_state); 2848 } 2849 2850 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2851 struct intel_encoder *encoder, 2852 const struct intel_crtc_state *crtc_state, 2853 const struct drm_connector_state *conn_state) 2854 { 2855 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2857 enum port port = encoder->port; 2858 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2859 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2860 2861 if (DISPLAY_VER(dev_priv) < 11) 2862 drm_WARN_ON(&dev_priv->drm, 2863 is_mst && (port == PORT_A || port == PORT_E)); 2864 else 2865 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2866 2867 intel_dp_set_link_params(intel_dp, 2868 crtc_state->port_clock, 2869 crtc_state->lane_count); 2870 2871 /* 2872 * We only configure what the register value will be here. Actual 2873 * enabling happens during link training farther down. 2874 */ 2875 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2876 2877 intel_pps_on(intel_dp); 2878 2879 intel_ddi_enable_clock(encoder, crtc_state); 2880 2881 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2882 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2883 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2884 dig_port->ddi_io_power_domain); 2885 } 2886 2887 icl_program_mg_dp_mode(dig_port, crtc_state); 2888 2889 if (has_buf_trans_select(dev_priv)) 2890 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2891 2892 encoder->set_signal_levels(encoder, crtc_state); 2893 2894 intel_ddi_power_up_lanes(encoder, crtc_state); 2895 2896 if (!is_mst) 2897 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2898 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2899 if (!is_mst) 2900 intel_dp_sink_enable_decompression(state, 2901 to_intel_connector(conn_state->connector), 2902 crtc_state); 2903 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2904 intel_dp_start_link_train(state, intel_dp, crtc_state); 2905 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2906 !is_trans_port_sync_mode(crtc_state)) 2907 intel_dp_stop_link_train(intel_dp, crtc_state); 2908 2909 intel_ddi_enable_fec(encoder, crtc_state); 2910 2911 if (!is_mst) { 2912 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2913 intel_dsc_dp_pps_write(encoder, crtc_state); 2914 } 2915 } 2916 2917 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2918 struct intel_encoder *encoder, 2919 const struct intel_crtc_state *crtc_state, 2920 const struct drm_connector_state *conn_state) 2921 { 2922 struct intel_display *display = to_intel_display(encoder); 2923 2924 if (HAS_DP20(display)) 2925 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2926 crtc_state); 2927 2928 /* Panel replay has to be enabled in sink dpcd before link training. */ 2929 if (crtc_state->has_panel_replay) 2930 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2931 2932 if (DISPLAY_VER(display) >= 14) 2933 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2934 else if (DISPLAY_VER(display) >= 12) 2935 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2936 else 2937 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2938 2939 /* MST will call a setting of MSA after an allocating of Virtual Channel 2940 * from MST encoder pre_enable callback. 2941 */ 2942 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2943 intel_ddi_set_dp_msa(crtc_state, conn_state); 2944 } 2945 2946 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2947 struct intel_encoder *encoder, 2948 const struct intel_crtc_state *crtc_state, 2949 const struct drm_connector_state *conn_state) 2950 { 2951 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2952 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2954 2955 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2956 intel_ddi_enable_clock(encoder, crtc_state); 2957 2958 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2959 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2960 dig_port->ddi_io_power_domain); 2961 2962 icl_program_mg_dp_mode(dig_port, crtc_state); 2963 2964 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2965 2966 dig_port->set_infoframes(encoder, 2967 crtc_state->has_infoframe, 2968 crtc_state, conn_state); 2969 } 2970 2971 /* 2972 * Note: Also called from the ->pre_enable of the first active MST stream 2973 * encoder on its primary encoder. 2974 * 2975 * When called from DP MST code: 2976 * 2977 * - conn_state will be NULL 2978 * 2979 * - encoder will be the primary encoder (i.e. mst->primary) 2980 * 2981 * - the main connector associated with this port won't be active or linked to a 2982 * crtc 2983 * 2984 * - crtc_state will be the state of the first stream to be activated on this 2985 * port, and it may not be the same stream that will be deactivated last, but 2986 * each stream should have a state that is identical when it comes to the DP 2987 * link parameteres 2988 */ 2989 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2990 struct intel_encoder *encoder, 2991 const struct intel_crtc_state *crtc_state, 2992 const struct drm_connector_state *conn_state) 2993 { 2994 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2995 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2996 enum pipe pipe = crtc->pipe; 2997 2998 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2999 3000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3001 3002 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3003 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3004 conn_state); 3005 } else { 3006 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3007 3008 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3009 conn_state); 3010 3011 /* FIXME precompute everything properly */ 3012 /* FIXME how do we turn infoframes off again? */ 3013 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3014 dig_port->set_infoframes(encoder, 3015 crtc_state->has_infoframe, 3016 crtc_state, conn_state); 3017 } 3018 } 3019 3020 static void 3021 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 3022 { 3023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3024 enum port port = encoder->port; 3025 i915_reg_t reg; 3026 u32 clr_bits, wait_bits; 3027 3028 if (DISPLAY_VER(dev_priv) >= 20) { 3029 reg = DDI_BUF_CTL(port); 3030 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3031 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3032 } else { 3033 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 3034 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3035 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3036 } 3037 3038 intel_de_rmw(dev_priv, reg, clr_bits, 0); 3039 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 3040 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3041 port_name(port)); 3042 } 3043 3044 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 3045 const struct intel_crtc_state *crtc_state) 3046 { 3047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3048 enum port port = encoder->port; 3049 u32 val; 3050 3051 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 3052 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3053 if (val & DDI_BUF_CTL_ENABLE) { 3054 val &= ~DDI_BUF_CTL_ENABLE; 3055 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3056 3057 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 3058 mtl_wait_ddi_buf_idle(dev_priv, port); 3059 } 3060 3061 /* 3.d Disable D2D Link */ 3062 mtl_ddi_disable_d2d_link(encoder); 3063 3064 /* 3.e Disable DP_TP_CTL */ 3065 if (intel_crtc_has_dp_encoder(crtc_state)) { 3066 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3067 DP_TP_CTL_ENABLE, 0); 3068 } 3069 } 3070 3071 static void disable_ddi_buf(struct intel_encoder *encoder, 3072 const struct intel_crtc_state *crtc_state) 3073 { 3074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3075 enum port port = encoder->port; 3076 bool wait = false; 3077 u32 val; 3078 3079 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3080 if (val & DDI_BUF_CTL_ENABLE) { 3081 val &= ~DDI_BUF_CTL_ENABLE; 3082 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3083 wait = true; 3084 } 3085 3086 if (intel_crtc_has_dp_encoder(crtc_state)) 3087 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3088 DP_TP_CTL_ENABLE, 0); 3089 3090 intel_ddi_disable_fec(encoder, crtc_state); 3091 3092 if (wait) 3093 intel_wait_ddi_buf_idle(dev_priv, port); 3094 } 3095 3096 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3097 const struct intel_crtc_state *crtc_state) 3098 { 3099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3100 3101 if (DISPLAY_VER(dev_priv) >= 14) { 3102 mtl_disable_ddi_buf(encoder, crtc_state); 3103 3104 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3105 intel_ddi_disable_fec(encoder, crtc_state); 3106 } else { 3107 disable_ddi_buf(encoder, crtc_state); 3108 } 3109 3110 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3111 } 3112 3113 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3114 struct intel_encoder *encoder, 3115 const struct intel_crtc_state *old_crtc_state, 3116 const struct drm_connector_state *old_conn_state) 3117 { 3118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3119 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3120 struct intel_dp *intel_dp = &dig_port->dp; 3121 intel_wakeref_t wakeref; 3122 bool is_mst = intel_crtc_has_type(old_crtc_state, 3123 INTEL_OUTPUT_DP_MST); 3124 3125 if (!is_mst) 3126 intel_dp_set_infoframes(encoder, false, 3127 old_crtc_state, old_conn_state); 3128 3129 /* 3130 * Power down sink before disabling the port, otherwise we end 3131 * up getting interrupts from the sink on detecting link loss. 3132 */ 3133 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3134 3135 if (DISPLAY_VER(dev_priv) >= 12) { 3136 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3137 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3138 3139 intel_de_rmw(dev_priv, 3140 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3141 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3142 0); 3143 } 3144 } else { 3145 if (!is_mst) 3146 intel_ddi_disable_transcoder_clock(old_crtc_state); 3147 } 3148 3149 intel_disable_ddi_buf(encoder, old_crtc_state); 3150 3151 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3152 3153 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3154 3155 /* 3156 * From TGL spec: "If single stream or multi-stream master transcoder: 3157 * Configure Transcoder Clock select to direct no clock to the 3158 * transcoder" 3159 */ 3160 if (DISPLAY_VER(dev_priv) >= 12) 3161 intel_ddi_disable_transcoder_clock(old_crtc_state); 3162 3163 intel_pps_vdd_on(intel_dp); 3164 intel_pps_off(intel_dp); 3165 3166 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3167 3168 if (wakeref) 3169 intel_display_power_put(dev_priv, 3170 dig_port->ddi_io_power_domain, 3171 wakeref); 3172 3173 intel_ddi_disable_clock(encoder); 3174 3175 /* De-select Thunderbolt */ 3176 if (DISPLAY_VER(dev_priv) >= 14) 3177 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3178 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3179 } 3180 3181 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3182 struct intel_encoder *encoder, 3183 const struct intel_crtc_state *old_crtc_state, 3184 const struct drm_connector_state *old_conn_state) 3185 { 3186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3187 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3188 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3189 intel_wakeref_t wakeref; 3190 3191 dig_port->set_infoframes(encoder, false, 3192 old_crtc_state, old_conn_state); 3193 3194 if (DISPLAY_VER(dev_priv) < 12) 3195 intel_ddi_disable_transcoder_clock(old_crtc_state); 3196 3197 intel_disable_ddi_buf(encoder, old_crtc_state); 3198 3199 if (DISPLAY_VER(dev_priv) >= 12) 3200 intel_ddi_disable_transcoder_clock(old_crtc_state); 3201 3202 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3203 if (wakeref) 3204 intel_display_power_put(dev_priv, 3205 dig_port->ddi_io_power_domain, 3206 wakeref); 3207 3208 intel_ddi_disable_clock(encoder); 3209 3210 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3211 } 3212 3213 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3214 struct intel_encoder *encoder, 3215 const struct intel_crtc_state *old_crtc_state, 3216 const struct drm_connector_state *old_conn_state) 3217 { 3218 struct intel_display *display = to_intel_display(encoder); 3219 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3220 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3221 struct intel_crtc *pipe_crtc; 3222 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3223 int i; 3224 3225 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3226 const struct intel_crtc_state *old_pipe_crtc_state = 3227 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3228 3229 intel_crtc_vblank_off(old_pipe_crtc_state); 3230 } 3231 3232 intel_disable_transcoder(old_crtc_state); 3233 3234 /* 128b/132b SST */ 3235 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3236 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3237 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3238 3239 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3240 3241 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3242 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3243 3244 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3245 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3246 } 3247 3248 intel_ddi_disable_transcoder_func(old_crtc_state); 3249 3250 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3251 const struct intel_crtc_state *old_pipe_crtc_state = 3252 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3253 3254 intel_dsc_disable(old_pipe_crtc_state); 3255 3256 if (DISPLAY_VER(dev_priv) >= 9) 3257 skl_scaler_disable(old_pipe_crtc_state); 3258 else 3259 ilk_pfit_disable(old_pipe_crtc_state); 3260 } 3261 } 3262 3263 /* 3264 * Note: Also called from the ->post_disable of the last active MST stream 3265 * encoder on its primary encoder. See also the comment for 3266 * intel_ddi_pre_enable(). 3267 */ 3268 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3269 struct intel_encoder *encoder, 3270 const struct intel_crtc_state *old_crtc_state, 3271 const struct drm_connector_state *old_conn_state) 3272 { 3273 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3274 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3275 old_conn_state); 3276 3277 /* 3278 * When called from DP MST code: 3279 * - old_conn_state will be NULL 3280 * - encoder will be the main encoder (ie. mst->primary) 3281 * - the main connector associated with this port 3282 * won't be active or linked to a crtc 3283 * - old_crtc_state will be the state of the last stream to 3284 * be deactivated on this port, and it may not be the same 3285 * stream that was activated last, but each stream 3286 * should have a state that is identical when it comes to 3287 * the DP link parameteres 3288 */ 3289 3290 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3291 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3292 old_conn_state); 3293 else 3294 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3295 old_conn_state); 3296 } 3297 3298 /* 3299 * Note: Also called from the ->post_pll_disable of the last active MST stream 3300 * encoder on its primary encoder. See also the comment for 3301 * intel_ddi_pre_enable(). 3302 */ 3303 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3304 struct intel_encoder *encoder, 3305 const struct intel_crtc_state *old_crtc_state, 3306 const struct drm_connector_state *old_conn_state) 3307 { 3308 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3309 3310 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3311 3312 if (intel_encoder_is_tc(encoder)) 3313 intel_tc_port_put_link(dig_port); 3314 } 3315 3316 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3317 struct intel_encoder *encoder, 3318 const struct intel_crtc_state *crtc_state) 3319 { 3320 const struct drm_connector_state *conn_state; 3321 struct drm_connector *conn; 3322 int i; 3323 3324 if (!crtc_state->sync_mode_slaves_mask) 3325 return; 3326 3327 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3328 struct intel_encoder *slave_encoder = 3329 to_intel_encoder(conn_state->best_encoder); 3330 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3331 const struct intel_crtc_state *slave_crtc_state; 3332 3333 if (!slave_crtc) 3334 continue; 3335 3336 slave_crtc_state = 3337 intel_atomic_get_new_crtc_state(state, slave_crtc); 3338 3339 if (slave_crtc_state->master_transcoder != 3340 crtc_state->cpu_transcoder) 3341 continue; 3342 3343 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3344 slave_crtc_state); 3345 } 3346 3347 usleep_range(200, 400); 3348 3349 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3350 crtc_state); 3351 } 3352 3353 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3354 struct intel_encoder *encoder, 3355 const struct intel_crtc_state *crtc_state, 3356 const struct drm_connector_state *conn_state) 3357 { 3358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3359 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3360 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3361 enum port port = encoder->port; 3362 3363 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3364 intel_dp_stop_link_train(intel_dp, crtc_state); 3365 3366 drm_connector_update_privacy_screen(conn_state); 3367 intel_edp_backlight_on(crtc_state, conn_state); 3368 3369 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3370 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3371 3372 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3373 } 3374 3375 static i915_reg_t 3376 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3377 { 3378 static const enum transcoder trans[] = { 3379 [PORT_A] = TRANSCODER_EDP, 3380 [PORT_B] = TRANSCODER_A, 3381 [PORT_C] = TRANSCODER_B, 3382 [PORT_D] = TRANSCODER_C, 3383 [PORT_E] = TRANSCODER_A, 3384 }; 3385 3386 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3387 3388 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3389 port = PORT_A; 3390 3391 return CHICKEN_TRANS(display, trans[port]); 3392 } 3393 3394 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3395 struct intel_encoder *encoder, 3396 const struct intel_crtc_state *crtc_state, 3397 const struct drm_connector_state *conn_state) 3398 { 3399 struct intel_display *display = to_intel_display(encoder); 3400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3401 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3402 struct drm_connector *connector = conn_state->connector; 3403 enum port port = encoder->port; 3404 u32 buf_ctl; 3405 3406 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3407 crtc_state->hdmi_high_tmds_clock_ratio, 3408 crtc_state->hdmi_scrambling)) 3409 drm_dbg_kms(&dev_priv->drm, 3410 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3411 connector->base.id, connector->name); 3412 3413 if (has_buf_trans_select(dev_priv)) 3414 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3415 3416 /* e. Enable D2D Link for C10/C20 Phy */ 3417 if (DISPLAY_VER(dev_priv) >= 14) 3418 mtl_ddi_enable_d2d(encoder); 3419 3420 encoder->set_signal_levels(encoder, crtc_state); 3421 3422 /* Display WA #1143: skl,kbl,cfl */ 3423 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3424 /* 3425 * For some reason these chicken bits have been 3426 * stuffed into a transcoder register, event though 3427 * the bits affect a specific DDI port rather than 3428 * a specific transcoder. 3429 */ 3430 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3431 u32 val; 3432 3433 val = intel_de_read(dev_priv, reg); 3434 3435 if (port == PORT_E) 3436 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3437 DDIE_TRAINING_OVERRIDE_VALUE; 3438 else 3439 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3440 DDI_TRAINING_OVERRIDE_VALUE; 3441 3442 intel_de_write(dev_priv, reg, val); 3443 intel_de_posting_read(dev_priv, reg); 3444 3445 udelay(1); 3446 3447 if (port == PORT_E) 3448 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3449 DDIE_TRAINING_OVERRIDE_VALUE); 3450 else 3451 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3452 DDI_TRAINING_OVERRIDE_VALUE); 3453 3454 intel_de_write(dev_priv, reg, val); 3455 } 3456 3457 intel_ddi_power_up_lanes(encoder, crtc_state); 3458 3459 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3460 * are ignored so nothing special needs to be done besides 3461 * enabling the port. 3462 * 3463 * On ADL_P the PHY link rate and lane count must be programmed but 3464 * these are both 0 for HDMI. 3465 * 3466 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3467 * is filled with lane count, already set in the crtc_state. 3468 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3469 */ 3470 buf_ctl = DDI_BUF_CTL_ENABLE; 3471 3472 if (dig_port->lane_reversal) 3473 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3474 if (dig_port->ddi_a_4_lanes) 3475 buf_ctl |= DDI_A_4_LANES; 3476 3477 if (DISPLAY_VER(dev_priv) >= 14) { 3478 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3479 u32 port_buf = 0; 3480 3481 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3482 3483 if (dig_port->lane_reversal) 3484 port_buf |= XELPDP_PORT_REVERSAL; 3485 3486 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3487 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3488 3489 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3490 3491 if (DISPLAY_VER(dev_priv) >= 20) 3492 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3493 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3494 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3495 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3496 } 3497 3498 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3499 3500 intel_wait_ddi_buf_active(encoder); 3501 } 3502 3503 static void intel_ddi_enable(struct intel_atomic_state *state, 3504 struct intel_encoder *encoder, 3505 const struct intel_crtc_state *crtc_state, 3506 const struct drm_connector_state *conn_state) 3507 { 3508 struct intel_display *display = to_intel_display(encoder); 3509 struct intel_crtc *pipe_crtc; 3510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3511 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3512 int i; 3513 3514 /* 128b/132b SST */ 3515 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3516 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3517 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3518 3519 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3520 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3521 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3522 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3523 } 3524 3525 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3526 3527 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3528 intel_audio_sdp_split_update(crtc_state); 3529 3530 /* 128b/132b SST */ 3531 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3532 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3533 3534 intel_ddi_clear_act_sent(encoder, crtc_state); 3535 3536 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3537 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3538 3539 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3540 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3541 } 3542 3543 intel_enable_transcoder(crtc_state); 3544 3545 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3546 3547 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3548 const struct intel_crtc_state *pipe_crtc_state = 3549 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3550 3551 intel_crtc_vblank_on(pipe_crtc_state); 3552 } 3553 3554 if (is_hdmi) 3555 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3556 else 3557 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3558 3559 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3560 3561 } 3562 3563 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3564 struct intel_encoder *encoder, 3565 const struct intel_crtc_state *old_crtc_state, 3566 const struct drm_connector_state *old_conn_state) 3567 { 3568 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3569 struct intel_connector *connector = 3570 to_intel_connector(old_conn_state->connector); 3571 3572 intel_dp->link_trained = false; 3573 3574 intel_psr_disable(intel_dp, old_crtc_state); 3575 intel_edp_backlight_off(old_conn_state); 3576 /* Disable the decompression in DP Sink */ 3577 intel_dp_sink_disable_decompression(state, 3578 connector, old_crtc_state); 3579 /* Disable Ignore_MSA bit in DP Sink */ 3580 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3581 false); 3582 } 3583 3584 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3585 struct intel_encoder *encoder, 3586 const struct intel_crtc_state *old_crtc_state, 3587 const struct drm_connector_state *old_conn_state) 3588 { 3589 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3590 struct drm_connector *connector = old_conn_state->connector; 3591 3592 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3593 false, false)) 3594 drm_dbg_kms(&i915->drm, 3595 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3596 connector->base.id, connector->name); 3597 } 3598 3599 static void intel_ddi_disable(struct intel_atomic_state *state, 3600 struct intel_encoder *encoder, 3601 const struct intel_crtc_state *old_crtc_state, 3602 const struct drm_connector_state *old_conn_state) 3603 { 3604 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3605 3606 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3607 3608 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3609 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3610 old_conn_state); 3611 else 3612 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3613 old_conn_state); 3614 } 3615 3616 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3617 struct intel_encoder *encoder, 3618 const struct intel_crtc_state *crtc_state, 3619 const struct drm_connector_state *conn_state) 3620 { 3621 intel_ddi_set_dp_msa(crtc_state, conn_state); 3622 3623 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3624 3625 intel_backlight_update(state, encoder, crtc_state, conn_state); 3626 drm_connector_update_privacy_screen(conn_state); 3627 } 3628 3629 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3630 const struct intel_crtc_state *crtc_state, 3631 const struct drm_connector_state *conn_state) 3632 { 3633 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3634 } 3635 3636 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3637 struct intel_encoder *encoder, 3638 const struct intel_crtc_state *crtc_state, 3639 const struct drm_connector_state *conn_state) 3640 { 3641 3642 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3643 !intel_encoder_is_mst(encoder)) 3644 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3645 conn_state); 3646 3647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3648 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3649 conn_state); 3650 3651 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3652 } 3653 3654 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3655 struct intel_encoder *encoder, 3656 struct intel_crtc *crtc) 3657 { 3658 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3659 const struct intel_crtc_state *crtc_state = 3660 intel_atomic_get_new_crtc_state(state, crtc); 3661 struct intel_crtc *pipe_crtc; 3662 3663 /* FIXME: Add MTL pll_mgr */ 3664 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3665 return; 3666 3667 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3668 intel_crtc_joined_pipe_mask(crtc_state)) 3669 intel_update_active_dpll(state, pipe_crtc, encoder); 3670 } 3671 3672 /* 3673 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3674 * encoder on its primary encoder. See also the comment for 3675 * intel_ddi_pre_enable(). 3676 */ 3677 static void 3678 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3679 struct intel_encoder *encoder, 3680 const struct intel_crtc_state *crtc_state, 3681 const struct drm_connector_state *conn_state) 3682 { 3683 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3684 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3685 bool is_tc_port = intel_encoder_is_tc(encoder); 3686 3687 if (is_tc_port) { 3688 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3689 3690 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3691 intel_ddi_update_active_dpll(state, encoder, crtc); 3692 } 3693 3694 main_link_aux_power_domain_get(dig_port, crtc_state); 3695 3696 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3697 /* 3698 * Program the lane count for static/dynamic connections on 3699 * Type-C ports. Skip this step for TBT. 3700 */ 3701 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3702 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3703 bxt_dpio_phy_set_lane_optim_mask(encoder, 3704 crtc_state->lane_lat_optim_mask); 3705 } 3706 3707 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3708 { 3709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3710 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3711 int ln; 3712 3713 for (ln = 0; ln < 2; ln++) 3714 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3715 } 3716 3717 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3718 const struct intel_crtc_state *crtc_state) 3719 { 3720 struct intel_display *display = to_intel_display(crtc_state); 3721 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3722 struct intel_encoder *encoder = &dig_port->base; 3723 enum port port = encoder->port; 3724 u32 dp_tp_ctl; 3725 3726 /* 3727 * TODO: To train with only a different voltage swing entry is not 3728 * necessary disable and enable port 3729 */ 3730 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3731 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3732 mtl_disable_ddi_buf(encoder, crtc_state); 3733 3734 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3735 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3736 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3737 intel_dp_is_uhbr(crtc_state)) { 3738 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3739 } else { 3740 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3741 if (crtc_state->enhanced_framing) 3742 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3743 } 3744 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3745 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3746 3747 /* 6.f Enable D2D Link */ 3748 mtl_ddi_enable_d2d(encoder); 3749 3750 /* 6.g Configure voltage swing and related IO settings */ 3751 encoder->set_signal_levels(encoder, crtc_state); 3752 3753 /* 6.h Configure PORT_BUF_CTL1 */ 3754 mtl_port_buf_ctl_program(encoder, crtc_state); 3755 3756 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3757 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3758 if (DISPLAY_VER(display) >= 20) 3759 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3760 3761 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 3762 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3763 3764 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3765 intel_wait_ddi_buf_active(encoder); 3766 } 3767 3768 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3769 const struct intel_crtc_state *crtc_state) 3770 { 3771 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3772 struct intel_encoder *encoder = &dig_port->base; 3773 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3774 enum port port = encoder->port; 3775 u32 dp_tp_ctl, ddi_buf_ctl; 3776 bool wait = false; 3777 3778 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3779 3780 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3781 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3782 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3783 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3784 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3785 wait = true; 3786 } 3787 3788 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3789 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3790 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3791 3792 if (wait) 3793 intel_wait_ddi_buf_idle(dev_priv, port); 3794 } 3795 3796 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3797 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3798 intel_dp_is_uhbr(crtc_state)) { 3799 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3800 } else { 3801 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3802 if (crtc_state->enhanced_framing) 3803 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3804 } 3805 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3806 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3807 3808 if (IS_ALDERLAKE_P(dev_priv) && 3809 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3810 adlp_tbt_to_dp_alt_switch_wa(encoder); 3811 3812 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3813 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3814 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3815 3816 intel_wait_ddi_buf_active(encoder); 3817 } 3818 3819 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3820 const struct intel_crtc_state *crtc_state, 3821 u8 dp_train_pat) 3822 { 3823 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3825 u32 temp; 3826 3827 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3828 3829 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3830 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3831 case DP_TRAINING_PATTERN_DISABLE: 3832 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3833 break; 3834 case DP_TRAINING_PATTERN_1: 3835 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3836 break; 3837 case DP_TRAINING_PATTERN_2: 3838 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3839 break; 3840 case DP_TRAINING_PATTERN_3: 3841 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3842 break; 3843 case DP_TRAINING_PATTERN_4: 3844 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3845 break; 3846 } 3847 3848 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3849 } 3850 3851 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3852 const struct intel_crtc_state *crtc_state) 3853 { 3854 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3855 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3856 enum port port = encoder->port; 3857 3858 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3859 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3860 3861 /* 3862 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3863 * reason we need to set idle transmission mode is to work around a HW 3864 * issue where we enable the pipe while not in idle link-training mode. 3865 * In this case there is requirement to wait for a minimum number of 3866 * idle patterns to be sent. 3867 */ 3868 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3869 return; 3870 3871 if (intel_de_wait_for_set(dev_priv, 3872 dp_tp_status_reg(encoder, crtc_state), 3873 DP_TP_STATUS_IDLE_DONE, 2)) 3874 drm_err(&dev_priv->drm, 3875 "Timed out waiting for DP idle patterns\n"); 3876 } 3877 3878 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3879 enum transcoder cpu_transcoder) 3880 { 3881 if (cpu_transcoder == TRANSCODER_EDP) 3882 return false; 3883 3884 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3885 return false; 3886 3887 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3888 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3889 } 3890 3891 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3892 { 3893 if (crtc_state->port_clock > 594000) 3894 return 2; 3895 else 3896 return 0; 3897 } 3898 3899 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3900 { 3901 if (crtc_state->port_clock > 594000) 3902 return 3; 3903 else 3904 return 0; 3905 } 3906 3907 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3908 { 3909 if (crtc_state->port_clock > 594000) 3910 return 1; 3911 else 3912 return 0; 3913 } 3914 3915 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3916 { 3917 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3918 3919 if (DISPLAY_VER(dev_priv) >= 14) 3920 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3921 else if (DISPLAY_VER(dev_priv) >= 12) 3922 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3923 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3924 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3925 else if (DISPLAY_VER(dev_priv) >= 11) 3926 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3927 } 3928 3929 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3930 enum transcoder cpu_transcoder) 3931 { 3932 u32 master_select; 3933 3934 if (DISPLAY_VER(dev_priv) >= 11) { 3935 u32 ctl2 = intel_de_read(dev_priv, 3936 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3937 3938 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3939 return INVALID_TRANSCODER; 3940 3941 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3942 } else { 3943 u32 ctl = intel_de_read(dev_priv, 3944 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3945 3946 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3947 return INVALID_TRANSCODER; 3948 3949 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3950 } 3951 3952 if (master_select == 0) 3953 return TRANSCODER_EDP; 3954 else 3955 return master_select - 1; 3956 } 3957 3958 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3959 { 3960 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3961 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3962 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3963 enum transcoder cpu_transcoder; 3964 3965 crtc_state->master_transcoder = 3966 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3967 3968 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3969 enum intel_display_power_domain power_domain; 3970 intel_wakeref_t trans_wakeref; 3971 3972 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3973 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3974 power_domain); 3975 3976 if (!trans_wakeref) 3977 continue; 3978 3979 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3980 crtc_state->cpu_transcoder) 3981 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3982 3983 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3984 } 3985 3986 drm_WARN_ON(&dev_priv->drm, 3987 crtc_state->master_transcoder != INVALID_TRANSCODER && 3988 crtc_state->sync_mode_slaves_mask); 3989 } 3990 3991 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3992 struct intel_crtc_state *crtc_state, 3993 u32 ddi_func_ctl) 3994 { 3995 struct intel_display *display = to_intel_display(encoder); 3996 3997 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3998 if (DISPLAY_VER(display) >= 14) 3999 crtc_state->lane_count = 4000 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4001 else 4002 crtc_state->lane_count = 4; 4003 } 4004 4005 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4006 struct intel_crtc_state *crtc_state, 4007 u32 ddi_func_ctl) 4008 { 4009 crtc_state->has_hdmi_sink = true; 4010 4011 crtc_state->infoframes.enable |= 4012 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4013 4014 if (crtc_state->infoframes.enable) 4015 crtc_state->has_infoframe = true; 4016 4017 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4018 crtc_state->hdmi_scrambling = true; 4019 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4020 crtc_state->hdmi_high_tmds_clock_ratio = true; 4021 4022 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4023 } 4024 4025 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4026 struct intel_crtc_state *crtc_state, 4027 u32 ddi_func_ctl) 4028 { 4029 struct intel_display *display = to_intel_display(encoder); 4030 4031 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4032 crtc_state->enhanced_framing = 4033 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4034 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4035 } 4036 4037 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4038 struct intel_crtc_state *crtc_state, 4039 u32 ddi_func_ctl) 4040 { 4041 struct intel_display *display = to_intel_display(encoder); 4042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4043 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4045 4046 if (encoder->type == INTEL_OUTPUT_EDP) 4047 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4048 else 4049 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4050 crtc_state->lane_count = 4051 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4052 4053 if (DISPLAY_VER(display) >= 12 && 4054 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4055 crtc_state->mst_master_transcoder = 4056 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4057 4058 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4059 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4060 4061 crtc_state->enhanced_framing = 4062 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4063 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4064 4065 if (DISPLAY_VER(display) >= 11) 4066 crtc_state->fec_enable = 4067 intel_de_read(display, 4068 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4069 4070 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 4071 crtc_state->infoframes.enable |= 4072 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4073 else 4074 crtc_state->infoframes.enable |= 4075 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4076 } 4077 4078 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4079 struct intel_crtc_state *crtc_state, 4080 u32 ddi_func_ctl) 4081 { 4082 struct intel_display *display = to_intel_display(encoder); 4083 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4084 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4085 4086 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4087 crtc_state->lane_count = 4088 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4089 4090 if (DISPLAY_VER(display) >= 12) 4091 crtc_state->mst_master_transcoder = 4092 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4093 4094 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4095 4096 if (DISPLAY_VER(display) >= 11) 4097 crtc_state->fec_enable = 4098 intel_de_read(display, 4099 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4100 4101 crtc_state->infoframes.enable |= 4102 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4103 } 4104 4105 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4106 struct intel_crtc_state *pipe_config) 4107 { 4108 struct intel_display *display = to_intel_display(encoder); 4109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4110 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4111 u32 ddi_func_ctl, ddi_mode, flags = 0; 4112 4113 ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 4114 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4115 flags |= DRM_MODE_FLAG_PHSYNC; 4116 else 4117 flags |= DRM_MODE_FLAG_NHSYNC; 4118 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4119 flags |= DRM_MODE_FLAG_PVSYNC; 4120 else 4121 flags |= DRM_MODE_FLAG_NVSYNC; 4122 4123 pipe_config->hw.adjusted_mode.flags |= flags; 4124 4125 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4126 case TRANS_DDI_BPC_6: 4127 pipe_config->pipe_bpp = 18; 4128 break; 4129 case TRANS_DDI_BPC_8: 4130 pipe_config->pipe_bpp = 24; 4131 break; 4132 case TRANS_DDI_BPC_10: 4133 pipe_config->pipe_bpp = 30; 4134 break; 4135 case TRANS_DDI_BPC_12: 4136 pipe_config->pipe_bpp = 36; 4137 break; 4138 default: 4139 break; 4140 } 4141 4142 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4143 4144 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4145 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4146 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4147 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4148 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4149 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4150 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4151 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4152 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4153 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4154 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4155 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4156 4157 /* 4158 * If this is true, we know we're being called from mst stream 4159 * encoder's ->get_config(). 4160 */ 4161 if (intel_dp_mst_encoder_active_links(dig_port)) 4162 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4163 else 4164 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4165 } 4166 } 4167 4168 /* 4169 * Note: Also called from the ->get_config of the MST stream encoders on their 4170 * primary encoder, via the platform specific hooks here. See also the comment 4171 * for intel_ddi_pre_enable(). 4172 */ 4173 static void intel_ddi_get_config(struct intel_encoder *encoder, 4174 struct intel_crtc_state *pipe_config) 4175 { 4176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4177 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4178 4179 /* XXX: DSI transcoder paranoia */ 4180 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4181 return; 4182 4183 intel_ddi_read_func_ctl(encoder, pipe_config); 4184 4185 intel_ddi_mso_get_config(encoder, pipe_config); 4186 4187 pipe_config->has_audio = 4188 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4189 4190 if (encoder->type == INTEL_OUTPUT_EDP) 4191 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4192 4193 ddi_dotclock_get(pipe_config); 4194 4195 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4196 pipe_config->lane_lat_optim_mask = 4197 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4198 4199 intel_ddi_compute_min_voltage_level(pipe_config); 4200 4201 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4202 4203 intel_read_infoframe(encoder, pipe_config, 4204 HDMI_INFOFRAME_TYPE_AVI, 4205 &pipe_config->infoframes.avi); 4206 intel_read_infoframe(encoder, pipe_config, 4207 HDMI_INFOFRAME_TYPE_SPD, 4208 &pipe_config->infoframes.spd); 4209 intel_read_infoframe(encoder, pipe_config, 4210 HDMI_INFOFRAME_TYPE_VENDOR, 4211 &pipe_config->infoframes.hdmi); 4212 intel_read_infoframe(encoder, pipe_config, 4213 HDMI_INFOFRAME_TYPE_DRM, 4214 &pipe_config->infoframes.drm); 4215 4216 if (DISPLAY_VER(dev_priv) >= 8) 4217 bdw_get_trans_port_sync_config(pipe_config); 4218 4219 intel_psr_get_config(encoder, pipe_config); 4220 4221 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4222 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4223 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4224 4225 intel_audio_codec_get_config(encoder, pipe_config); 4226 } 4227 4228 void intel_ddi_get_clock(struct intel_encoder *encoder, 4229 struct intel_crtc_state *crtc_state, 4230 struct intel_shared_dpll *pll) 4231 { 4232 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4233 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4234 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4235 bool pll_active; 4236 4237 if (drm_WARN_ON(&i915->drm, !pll)) 4238 return; 4239 4240 port_dpll->pll = pll; 4241 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4242 drm_WARN_ON(&i915->drm, !pll_active); 4243 4244 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4245 4246 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4247 &crtc_state->dpll_hw_state); 4248 } 4249 4250 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4251 struct intel_crtc_state *crtc_state) 4252 { 4253 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4254 4255 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4256 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4257 else 4258 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4259 4260 intel_ddi_get_config(encoder, crtc_state); 4261 } 4262 4263 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4264 struct intel_crtc_state *crtc_state) 4265 { 4266 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4267 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4268 4269 intel_ddi_get_config(encoder, crtc_state); 4270 } 4271 4272 static void adls_ddi_get_config(struct intel_encoder *encoder, 4273 struct intel_crtc_state *crtc_state) 4274 { 4275 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4276 intel_ddi_get_config(encoder, crtc_state); 4277 } 4278 4279 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4280 struct intel_crtc_state *crtc_state) 4281 { 4282 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4283 intel_ddi_get_config(encoder, crtc_state); 4284 } 4285 4286 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4287 struct intel_crtc_state *crtc_state) 4288 { 4289 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4290 intel_ddi_get_config(encoder, crtc_state); 4291 } 4292 4293 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4294 struct intel_crtc_state *crtc_state) 4295 { 4296 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4297 intel_ddi_get_config(encoder, crtc_state); 4298 } 4299 4300 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4301 { 4302 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4303 } 4304 4305 static enum icl_port_dpll_id 4306 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4307 const struct intel_crtc_state *crtc_state) 4308 { 4309 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4310 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4311 4312 if (drm_WARN_ON(&i915->drm, !pll)) 4313 return ICL_PORT_DPLL_DEFAULT; 4314 4315 if (icl_ddi_tc_pll_is_tbt(pll)) 4316 return ICL_PORT_DPLL_DEFAULT; 4317 else 4318 return ICL_PORT_DPLL_MG_PHY; 4319 } 4320 4321 enum icl_port_dpll_id 4322 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4323 const struct intel_crtc_state *crtc_state) 4324 { 4325 if (!encoder->port_pll_type) 4326 return ICL_PORT_DPLL_DEFAULT; 4327 4328 return encoder->port_pll_type(encoder, crtc_state); 4329 } 4330 4331 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4332 struct intel_crtc_state *crtc_state, 4333 struct intel_shared_dpll *pll) 4334 { 4335 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4336 enum icl_port_dpll_id port_dpll_id; 4337 struct icl_port_dpll *port_dpll; 4338 bool pll_active; 4339 4340 if (drm_WARN_ON(&i915->drm, !pll)) 4341 return; 4342 4343 if (icl_ddi_tc_pll_is_tbt(pll)) 4344 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4345 else 4346 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4347 4348 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4349 4350 port_dpll->pll = pll; 4351 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4352 drm_WARN_ON(&i915->drm, !pll_active); 4353 4354 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4355 4356 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4357 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4358 else 4359 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4360 &crtc_state->dpll_hw_state); 4361 } 4362 4363 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4364 struct intel_crtc_state *crtc_state) 4365 { 4366 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4367 intel_ddi_get_config(encoder, crtc_state); 4368 } 4369 4370 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4371 struct intel_crtc_state *crtc_state) 4372 { 4373 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4374 intel_ddi_get_config(encoder, crtc_state); 4375 } 4376 4377 static void skl_ddi_get_config(struct intel_encoder *encoder, 4378 struct intel_crtc_state *crtc_state) 4379 { 4380 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4381 intel_ddi_get_config(encoder, crtc_state); 4382 } 4383 4384 void hsw_ddi_get_config(struct intel_encoder *encoder, 4385 struct intel_crtc_state *crtc_state) 4386 { 4387 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4388 intel_ddi_get_config(encoder, crtc_state); 4389 } 4390 4391 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4392 const struct intel_crtc_state *crtc_state) 4393 { 4394 if (intel_encoder_is_tc(encoder)) 4395 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4396 crtc_state); 4397 4398 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4399 (!crtc_state && intel_encoder_is_dp(encoder))) 4400 intel_dp_sync_state(encoder, crtc_state); 4401 } 4402 4403 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4404 struct intel_crtc_state *crtc_state) 4405 { 4406 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4407 bool fastset = true; 4408 4409 if (intel_encoder_is_tc(encoder)) { 4410 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4411 encoder->base.base.id, encoder->base.name); 4412 crtc_state->uapi.mode_changed = true; 4413 fastset = false; 4414 } 4415 4416 if (intel_crtc_has_dp_encoder(crtc_state) && 4417 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4418 fastset = false; 4419 4420 return fastset; 4421 } 4422 4423 static enum intel_output_type 4424 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4425 struct intel_crtc_state *crtc_state, 4426 struct drm_connector_state *conn_state) 4427 { 4428 switch (conn_state->connector->connector_type) { 4429 case DRM_MODE_CONNECTOR_HDMIA: 4430 return INTEL_OUTPUT_HDMI; 4431 case DRM_MODE_CONNECTOR_eDP: 4432 return INTEL_OUTPUT_EDP; 4433 case DRM_MODE_CONNECTOR_DisplayPort: 4434 return INTEL_OUTPUT_DP; 4435 default: 4436 MISSING_CASE(conn_state->connector->connector_type); 4437 return INTEL_OUTPUT_UNUSED; 4438 } 4439 } 4440 4441 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4442 struct intel_crtc_state *pipe_config, 4443 struct drm_connector_state *conn_state) 4444 { 4445 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4446 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4447 enum port port = encoder->port; 4448 int ret; 4449 4450 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4451 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4452 4453 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4454 pipe_config->has_hdmi_sink = 4455 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4456 4457 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4458 } else { 4459 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4460 } 4461 4462 if (ret) 4463 return ret; 4464 4465 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4466 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4467 pipe_config->pch_pfit.force_thru = 4468 pipe_config->pch_pfit.enabled || 4469 pipe_config->crc_enabled; 4470 4471 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4472 pipe_config->lane_lat_optim_mask = 4473 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4474 4475 intel_ddi_compute_min_voltage_level(pipe_config); 4476 4477 return 0; 4478 } 4479 4480 static bool mode_equal(const struct drm_display_mode *mode1, 4481 const struct drm_display_mode *mode2) 4482 { 4483 return drm_mode_match(mode1, mode2, 4484 DRM_MODE_MATCH_TIMINGS | 4485 DRM_MODE_MATCH_FLAGS | 4486 DRM_MODE_MATCH_3D_FLAGS) && 4487 mode1->clock == mode2->clock; /* we want an exact match */ 4488 } 4489 4490 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4491 const struct intel_link_m_n *m_n_2) 4492 { 4493 return m_n_1->tu == m_n_2->tu && 4494 m_n_1->data_m == m_n_2->data_m && 4495 m_n_1->data_n == m_n_2->data_n && 4496 m_n_1->link_m == m_n_2->link_m && 4497 m_n_1->link_n == m_n_2->link_n; 4498 } 4499 4500 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4501 const struct intel_crtc_state *crtc_state2) 4502 { 4503 /* 4504 * FIXME the modeset sequence is currently wrong and 4505 * can't deal with joiner + port sync at the same time. 4506 */ 4507 return crtc_state1->hw.active && crtc_state2->hw.active && 4508 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4509 crtc_state1->output_types == crtc_state2->output_types && 4510 crtc_state1->output_format == crtc_state2->output_format && 4511 crtc_state1->lane_count == crtc_state2->lane_count && 4512 crtc_state1->port_clock == crtc_state2->port_clock && 4513 mode_equal(&crtc_state1->hw.adjusted_mode, 4514 &crtc_state2->hw.adjusted_mode) && 4515 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4516 } 4517 4518 static u8 4519 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4520 int tile_group_id) 4521 { 4522 struct drm_connector *connector; 4523 const struct drm_connector_state *conn_state; 4524 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4525 struct intel_atomic_state *state = 4526 to_intel_atomic_state(ref_crtc_state->uapi.state); 4527 u8 transcoders = 0; 4528 int i; 4529 4530 /* 4531 * We don't enable port sync on BDW due to missing w/as and 4532 * due to not having adjusted the modeset sequence appropriately. 4533 */ 4534 if (DISPLAY_VER(dev_priv) < 9) 4535 return 0; 4536 4537 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4538 return 0; 4539 4540 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4541 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4542 const struct intel_crtc_state *crtc_state; 4543 4544 if (!crtc) 4545 continue; 4546 4547 if (!connector->has_tile || 4548 connector->tile_group->id != 4549 tile_group_id) 4550 continue; 4551 crtc_state = intel_atomic_get_new_crtc_state(state, 4552 crtc); 4553 if (!crtcs_port_sync_compatible(ref_crtc_state, 4554 crtc_state)) 4555 continue; 4556 transcoders |= BIT(crtc_state->cpu_transcoder); 4557 } 4558 4559 return transcoders; 4560 } 4561 4562 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4563 struct intel_crtc_state *crtc_state, 4564 struct drm_connector_state *conn_state) 4565 { 4566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4567 struct drm_connector *connector = conn_state->connector; 4568 u8 port_sync_transcoders = 0; 4569 4570 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4571 encoder->base.base.id, encoder->base.name, 4572 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4573 4574 if (connector->has_tile) 4575 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4576 connector->tile_group->id); 4577 4578 /* 4579 * EDP Transcoders cannot be ensalved 4580 * make them a master always when present 4581 */ 4582 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4583 crtc_state->master_transcoder = TRANSCODER_EDP; 4584 else 4585 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4586 4587 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4588 crtc_state->master_transcoder = INVALID_TRANSCODER; 4589 crtc_state->sync_mode_slaves_mask = 4590 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4591 } 4592 4593 return 0; 4594 } 4595 4596 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4597 { 4598 struct drm_i915_private *i915 = to_i915(encoder->dev); 4599 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4600 4601 intel_dp_encoder_flush_work(encoder); 4602 if (intel_encoder_is_tc(&dig_port->base)) 4603 intel_tc_port_cleanup(dig_port); 4604 intel_display_power_flush_work(i915); 4605 4606 drm_encoder_cleanup(encoder); 4607 kfree(dig_port->hdcp_port_data.streams); 4608 kfree(dig_port); 4609 } 4610 4611 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4612 { 4613 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4614 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4615 4616 intel_dp->reset_link_params = true; 4617 intel_dp_invalidate_source_oui(intel_dp); 4618 4619 intel_pps_encoder_reset(intel_dp); 4620 4621 if (intel_encoder_is_tc(&dig_port->base)) 4622 intel_tc_port_init_mode(dig_port); 4623 } 4624 4625 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4626 { 4627 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4628 4629 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4630 4631 return 0; 4632 } 4633 4634 static const struct drm_encoder_funcs intel_ddi_funcs = { 4635 .reset = intel_ddi_encoder_reset, 4636 .destroy = intel_ddi_encoder_destroy, 4637 .late_register = intel_ddi_encoder_late_register, 4638 }; 4639 4640 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4641 { 4642 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4643 struct intel_connector *connector; 4644 enum port port = dig_port->base.port; 4645 4646 connector = intel_connector_alloc(); 4647 if (!connector) 4648 return -ENOMEM; 4649 4650 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4651 if (DISPLAY_VER(i915) >= 14) 4652 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4653 else 4654 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4655 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4656 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4657 4658 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4659 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4660 4661 if (!intel_dp_init_connector(dig_port, connector)) { 4662 kfree(connector); 4663 return -EINVAL; 4664 } 4665 4666 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4667 struct drm_device *dev = dig_port->base.base.dev; 4668 struct drm_privacy_screen *privacy_screen; 4669 4670 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4671 if (!IS_ERR(privacy_screen)) { 4672 drm_connector_attach_privacy_screen_provider(&connector->base, 4673 privacy_screen); 4674 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4675 drm_warn(dev, "Error getting privacy-screen\n"); 4676 } 4677 } 4678 4679 return 0; 4680 } 4681 4682 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4683 struct drm_modeset_acquire_ctx *ctx) 4684 { 4685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4686 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4687 struct intel_connector *connector = hdmi->attached_connector; 4688 struct i2c_adapter *ddc = connector->base.ddc; 4689 struct drm_connector_state *conn_state; 4690 struct intel_crtc_state *crtc_state; 4691 struct intel_crtc *crtc; 4692 u8 config; 4693 int ret; 4694 4695 if (connector->base.status != connector_status_connected) 4696 return 0; 4697 4698 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4699 ctx); 4700 if (ret) 4701 return ret; 4702 4703 conn_state = connector->base.state; 4704 4705 crtc = to_intel_crtc(conn_state->crtc); 4706 if (!crtc) 4707 return 0; 4708 4709 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4710 if (ret) 4711 return ret; 4712 4713 crtc_state = to_intel_crtc_state(crtc->base.state); 4714 4715 drm_WARN_ON(&dev_priv->drm, 4716 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4717 4718 if (!crtc_state->hw.active) 4719 return 0; 4720 4721 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4722 !crtc_state->hdmi_scrambling) 4723 return 0; 4724 4725 if (conn_state->commit && 4726 !try_wait_for_completion(&conn_state->commit->hw_done)) 4727 return 0; 4728 4729 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4730 if (ret < 0) { 4731 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4732 connector->base.base.id, connector->base.name, ret); 4733 return 0; 4734 } 4735 4736 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4737 crtc_state->hdmi_high_tmds_clock_ratio && 4738 !!(config & SCDC_SCRAMBLING_ENABLE) == 4739 crtc_state->hdmi_scrambling) 4740 return 0; 4741 4742 /* 4743 * HDMI 2.0 says that one should not send scrambled data 4744 * prior to configuring the sink scrambling, and that 4745 * TMDS clock/data transmission should be suspended when 4746 * changing the TMDS clock rate in the sink. So let's 4747 * just do a full modeset here, even though some sinks 4748 * would be perfectly happy if were to just reconfigure 4749 * the SCDC settings on the fly. 4750 */ 4751 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4752 } 4753 4754 static void intel_ddi_link_check(struct intel_encoder *encoder) 4755 { 4756 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4757 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4758 4759 /* TODO: Move checking the HDMI link state here as well. */ 4760 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4761 4762 intel_dp_link_check(encoder); 4763 } 4764 4765 static enum intel_hotplug_state 4766 intel_ddi_hotplug(struct intel_encoder *encoder, 4767 struct intel_connector *connector) 4768 { 4769 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4770 struct intel_dp *intel_dp = &dig_port->dp; 4771 bool is_tc = intel_encoder_is_tc(encoder); 4772 struct drm_modeset_acquire_ctx ctx; 4773 enum intel_hotplug_state state; 4774 int ret; 4775 4776 if (intel_dp_test_phy(intel_dp)) 4777 return INTEL_HOTPLUG_UNCHANGED; 4778 4779 state = intel_encoder_hotplug(encoder, connector); 4780 4781 if (!intel_tc_port_link_reset(dig_port)) { 4782 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4783 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4784 ret = intel_hdmi_reset_link(encoder, &ctx); 4785 drm_WARN_ON(encoder->base.dev, ret); 4786 } else { 4787 intel_dp_check_link_state(intel_dp); 4788 } 4789 } 4790 4791 /* 4792 * Unpowered type-c dongles can take some time to boot and be 4793 * responsible, so here giving some time to those dongles to power up 4794 * and then retrying the probe. 4795 * 4796 * On many platforms the HDMI live state signal is known to be 4797 * unreliable, so we can't use it to detect if a sink is connected or 4798 * not. Instead we detect if it's connected based on whether we can 4799 * read the EDID or not. That in turn has a problem during disconnect, 4800 * since the HPD interrupt may be raised before the DDC lines get 4801 * disconnected (due to how the required length of DDC vs. HPD 4802 * connector pins are specified) and so we'll still be able to get a 4803 * valid EDID. To solve this schedule another detection cycle if this 4804 * time around we didn't detect any change in the sink's connection 4805 * status. 4806 * 4807 * Type-c connectors which get their HPD signal deasserted then 4808 * reasserted, without unplugging/replugging the sink from the 4809 * connector, introduce a delay until the AUX channel communication 4810 * becomes functional. Retry the detection for 5 seconds on type-c 4811 * connectors to account for this delay. 4812 */ 4813 if (state == INTEL_HOTPLUG_UNCHANGED && 4814 connector->hotplug_retries < (is_tc ? 5 : 1) && 4815 !dig_port->dp.is_mst) 4816 state = INTEL_HOTPLUG_RETRY; 4817 4818 return state; 4819 } 4820 4821 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4822 { 4823 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4824 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4825 4826 return intel_de_read(dev_priv, SDEISR) & bit; 4827 } 4828 4829 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4830 { 4831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4832 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4833 4834 return intel_de_read(dev_priv, DEISR) & bit; 4835 } 4836 4837 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4838 { 4839 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4840 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4841 4842 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4843 } 4844 4845 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4846 { 4847 struct intel_connector *connector; 4848 enum port port = dig_port->base.port; 4849 4850 connector = intel_connector_alloc(); 4851 if (!connector) 4852 return -ENOMEM; 4853 4854 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4855 4856 if (!intel_hdmi_init_connector(dig_port, connector)) { 4857 /* 4858 * HDMI connector init failures may just mean conflicting DDC 4859 * pins or not having enough lanes. Handle them gracefully, but 4860 * don't fail the entire DDI init. 4861 */ 4862 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4863 kfree(connector); 4864 } 4865 4866 return 0; 4867 } 4868 4869 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4870 { 4871 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4872 4873 if (dig_port->base.port != PORT_A) 4874 return false; 4875 4876 if (dig_port->ddi_a_4_lanes) 4877 return false; 4878 4879 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4880 * supported configuration 4881 */ 4882 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4883 return true; 4884 4885 return false; 4886 } 4887 4888 static int 4889 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4890 { 4891 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4892 enum port port = dig_port->base.port; 4893 int max_lanes = 4; 4894 4895 if (DISPLAY_VER(dev_priv) >= 11) 4896 return max_lanes; 4897 4898 if (port == PORT_A || port == PORT_E) { 4899 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4900 max_lanes = port == PORT_A ? 4 : 0; 4901 else 4902 /* Both A and E share 2 lanes */ 4903 max_lanes = 2; 4904 } 4905 4906 /* 4907 * Some BIOS might fail to set this bit on port A if eDP 4908 * wasn't lit up at boot. Force this bit set when needed 4909 * so we use the proper lane count for our calculations. 4910 */ 4911 if (intel_ddi_a_force_4_lanes(dig_port)) { 4912 drm_dbg_kms(&dev_priv->drm, 4913 "Forcing DDI_A_4_LANES for port A\n"); 4914 dig_port->ddi_a_4_lanes = true; 4915 max_lanes = 4; 4916 } 4917 4918 return max_lanes; 4919 } 4920 4921 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4922 enum port port) 4923 { 4924 if (port >= PORT_D_XELPD) 4925 return HPD_PORT_D + port - PORT_D_XELPD; 4926 else if (port >= PORT_TC1) 4927 return HPD_PORT_TC1 + port - PORT_TC1; 4928 else 4929 return HPD_PORT_A + port - PORT_A; 4930 } 4931 4932 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4933 enum port port) 4934 { 4935 if (port >= PORT_TC1) 4936 return HPD_PORT_C + port - PORT_TC1; 4937 else 4938 return HPD_PORT_A + port - PORT_A; 4939 } 4940 4941 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4942 enum port port) 4943 { 4944 if (port >= PORT_TC1) 4945 return HPD_PORT_TC1 + port - PORT_TC1; 4946 else 4947 return HPD_PORT_A + port - PORT_A; 4948 } 4949 4950 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4951 enum port port) 4952 { 4953 if (HAS_PCH_TGP(dev_priv)) 4954 return tgl_hpd_pin(dev_priv, port); 4955 4956 if (port >= PORT_TC1) 4957 return HPD_PORT_C + port - PORT_TC1; 4958 else 4959 return HPD_PORT_A + port - PORT_A; 4960 } 4961 4962 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4963 enum port port) 4964 { 4965 if (port >= PORT_C) 4966 return HPD_PORT_TC1 + port - PORT_C; 4967 else 4968 return HPD_PORT_A + port - PORT_A; 4969 } 4970 4971 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4972 enum port port) 4973 { 4974 if (port == PORT_D) 4975 return HPD_PORT_A; 4976 4977 if (HAS_PCH_TGP(dev_priv)) 4978 return icl_hpd_pin(dev_priv, port); 4979 4980 return HPD_PORT_A + port - PORT_A; 4981 } 4982 4983 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4984 { 4985 if (HAS_PCH_TGP(dev_priv)) 4986 return icl_hpd_pin(dev_priv, port); 4987 4988 return HPD_PORT_A + port - PORT_A; 4989 } 4990 4991 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4992 { 4993 if (DISPLAY_VER(i915) >= 12) 4994 return port >= PORT_TC1; 4995 else if (DISPLAY_VER(i915) >= 11) 4996 return port >= PORT_C; 4997 else 4998 return false; 4999 } 5000 5001 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5002 { 5003 intel_dp_encoder_suspend(encoder); 5004 } 5005 5006 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5007 { 5008 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5009 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5010 5011 /* 5012 * TODO: Move this to intel_dp_encoder_suspend(), 5013 * once modeset locking around that is removed. 5014 */ 5015 intel_encoder_link_check_flush_work(encoder); 5016 intel_tc_port_suspend(dig_port); 5017 } 5018 5019 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5020 { 5021 if (intel_encoder_is_dp(encoder)) 5022 intel_dp_encoder_shutdown(encoder); 5023 if (intel_encoder_is_hdmi(encoder)) 5024 intel_hdmi_encoder_shutdown(encoder); 5025 } 5026 5027 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5028 { 5029 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5030 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5031 5032 intel_tc_port_cleanup(dig_port); 5033 } 5034 5035 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5036 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5037 5038 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 5039 { 5040 /* straps not used on skl+ */ 5041 if (DISPLAY_VER(i915) >= 9) 5042 return true; 5043 5044 switch (port) { 5045 case PORT_A: 5046 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5047 case PORT_B: 5048 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5049 case PORT_C: 5050 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5051 case PORT_D: 5052 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5053 case PORT_E: 5054 return true; /* no strap for DDI-E */ 5055 default: 5056 MISSING_CASE(port); 5057 return false; 5058 } 5059 } 5060 5061 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5062 { 5063 return init_dp || intel_encoder_is_tc(encoder); 5064 } 5065 5066 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 5067 { 5068 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 5069 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 5070 "Platform does not support DSI\n"); 5071 } 5072 5073 static bool port_in_use(struct drm_i915_private *i915, enum port port) 5074 { 5075 struct intel_encoder *encoder; 5076 5077 for_each_intel_encoder(&i915->drm, encoder) { 5078 /* FIXME what about second port for dual link DSI? */ 5079 if (encoder->port == port) 5080 return true; 5081 } 5082 5083 return false; 5084 } 5085 5086 void intel_ddi_init(struct intel_display *display, 5087 const struct intel_bios_encoder_data *devdata) 5088 { 5089 struct drm_i915_private *dev_priv = to_i915(display->drm); 5090 struct intel_digital_port *dig_port; 5091 struct intel_encoder *encoder; 5092 bool init_hdmi, init_dp; 5093 enum port port; 5094 enum phy phy; 5095 u32 ddi_buf_ctl; 5096 5097 port = intel_bios_encoder_port(devdata); 5098 if (port == PORT_NONE) 5099 return; 5100 5101 if (!port_strap_detected(dev_priv, port)) { 5102 drm_dbg_kms(&dev_priv->drm, 5103 "Port %c strap not detected\n", port_name(port)); 5104 return; 5105 } 5106 5107 if (!assert_port_valid(dev_priv, port)) 5108 return; 5109 5110 if (port_in_use(dev_priv, port)) { 5111 drm_dbg_kms(&dev_priv->drm, 5112 "Port %c already claimed\n", port_name(port)); 5113 return; 5114 } 5115 5116 if (intel_bios_encoder_supports_dsi(devdata)) { 5117 /* BXT/GLK handled elsewhere, for now at least */ 5118 if (!assert_has_icl_dsi(dev_priv)) 5119 return; 5120 5121 icl_dsi_init(display, devdata); 5122 return; 5123 } 5124 5125 phy = intel_port_to_phy(dev_priv, port); 5126 5127 /* 5128 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5129 * have taken over some of the PHYs and made them unavailable to the 5130 * driver. In that case we should skip initializing the corresponding 5131 * outputs. 5132 */ 5133 if (intel_hti_uses_phy(display, phy)) { 5134 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5135 port_name(port), phy_name(phy)); 5136 return; 5137 } 5138 5139 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5140 intel_bios_encoder_supports_hdmi(devdata); 5141 init_dp = intel_bios_encoder_supports_dp(devdata); 5142 5143 if (intel_bios_encoder_is_lspcon(devdata)) { 5144 /* 5145 * Lspcon device needs to be driven with DP connector 5146 * with special detection sequence. So make sure DP 5147 * is initialized before lspcon. 5148 */ 5149 init_dp = true; 5150 init_hdmi = false; 5151 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5152 port_name(port)); 5153 } 5154 5155 if (!init_dp && !init_hdmi) { 5156 drm_dbg_kms(&dev_priv->drm, 5157 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5158 port_name(port)); 5159 return; 5160 } 5161 5162 if (intel_phy_is_snps(dev_priv, phy) && 5163 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 5164 drm_dbg_kms(&dev_priv->drm, 5165 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5166 phy_name(phy)); 5167 } 5168 5169 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5170 if (!dig_port) 5171 return; 5172 5173 dig_port->aux_ch = AUX_CH_NONE; 5174 5175 encoder = &dig_port->base; 5176 encoder->devdata = devdata; 5177 5178 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 5179 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5180 DRM_MODE_ENCODER_TMDS, 5181 "DDI %c/PHY %c", 5182 port_name(port - PORT_D_XELPD + PORT_D), 5183 phy_name(phy)); 5184 } else if (DISPLAY_VER(dev_priv) >= 12) { 5185 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5186 5187 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5188 DRM_MODE_ENCODER_TMDS, 5189 "DDI %s%c/PHY %s%c", 5190 port >= PORT_TC1 ? "TC" : "", 5191 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5192 tc_port != TC_PORT_NONE ? "TC" : "", 5193 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5194 } else if (DISPLAY_VER(dev_priv) >= 11) { 5195 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5196 5197 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5198 DRM_MODE_ENCODER_TMDS, 5199 "DDI %c%s/PHY %s%c", 5200 port_name(port), 5201 port >= PORT_C ? " (TC)" : "", 5202 tc_port != TC_PORT_NONE ? "TC" : "", 5203 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5204 } else { 5205 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5206 DRM_MODE_ENCODER_TMDS, 5207 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5208 } 5209 5210 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5211 5212 mutex_init(&dig_port->hdcp_mutex); 5213 dig_port->num_hdcp_streams = 0; 5214 5215 encoder->hotplug = intel_ddi_hotplug; 5216 encoder->compute_output_type = intel_ddi_compute_output_type; 5217 encoder->compute_config = intel_ddi_compute_config; 5218 encoder->compute_config_late = intel_ddi_compute_config_late; 5219 encoder->enable = intel_ddi_enable; 5220 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5221 encoder->pre_enable = intel_ddi_pre_enable; 5222 encoder->disable = intel_ddi_disable; 5223 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5224 encoder->post_disable = intel_ddi_post_disable; 5225 encoder->update_pipe = intel_ddi_update_pipe; 5226 encoder->audio_enable = intel_audio_codec_enable; 5227 encoder->audio_disable = intel_audio_codec_disable; 5228 encoder->get_hw_state = intel_ddi_get_hw_state; 5229 encoder->sync_state = intel_ddi_sync_state; 5230 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5231 encoder->suspend = intel_ddi_encoder_suspend; 5232 encoder->shutdown = intel_ddi_encoder_shutdown; 5233 encoder->get_power_domains = intel_ddi_get_power_domains; 5234 5235 encoder->type = INTEL_OUTPUT_DDI; 5236 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5237 encoder->port = port; 5238 encoder->cloneable = 0; 5239 encoder->pipe_mask = ~0; 5240 5241 if (DISPLAY_VER(dev_priv) >= 14) { 5242 encoder->enable_clock = intel_mtl_pll_enable; 5243 encoder->disable_clock = intel_mtl_pll_disable; 5244 encoder->port_pll_type = intel_mtl_port_pll_type; 5245 encoder->get_config = mtl_ddi_get_config; 5246 } else if (IS_DG2(dev_priv)) { 5247 encoder->enable_clock = intel_mpllb_enable; 5248 encoder->disable_clock = intel_mpllb_disable; 5249 encoder->get_config = dg2_ddi_get_config; 5250 } else if (IS_ALDERLAKE_S(dev_priv)) { 5251 encoder->enable_clock = adls_ddi_enable_clock; 5252 encoder->disable_clock = adls_ddi_disable_clock; 5253 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5254 encoder->get_config = adls_ddi_get_config; 5255 } else if (IS_ROCKETLAKE(dev_priv)) { 5256 encoder->enable_clock = rkl_ddi_enable_clock; 5257 encoder->disable_clock = rkl_ddi_disable_clock; 5258 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5259 encoder->get_config = rkl_ddi_get_config; 5260 } else if (IS_DG1(dev_priv)) { 5261 encoder->enable_clock = dg1_ddi_enable_clock; 5262 encoder->disable_clock = dg1_ddi_disable_clock; 5263 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5264 encoder->get_config = dg1_ddi_get_config; 5265 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5266 if (intel_ddi_is_tc(dev_priv, port)) { 5267 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5268 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5269 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5270 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5271 encoder->get_config = icl_ddi_combo_get_config; 5272 } else { 5273 encoder->enable_clock = icl_ddi_combo_enable_clock; 5274 encoder->disable_clock = icl_ddi_combo_disable_clock; 5275 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5276 encoder->get_config = icl_ddi_combo_get_config; 5277 } 5278 } else if (DISPLAY_VER(dev_priv) >= 11) { 5279 if (intel_ddi_is_tc(dev_priv, port)) { 5280 encoder->enable_clock = icl_ddi_tc_enable_clock; 5281 encoder->disable_clock = icl_ddi_tc_disable_clock; 5282 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5283 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5284 encoder->get_config = icl_ddi_tc_get_config; 5285 } else { 5286 encoder->enable_clock = icl_ddi_combo_enable_clock; 5287 encoder->disable_clock = icl_ddi_combo_disable_clock; 5288 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5289 encoder->get_config = icl_ddi_combo_get_config; 5290 } 5291 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5292 /* BXT/GLK have fixed PLL->port mapping */ 5293 encoder->get_config = bxt_ddi_get_config; 5294 } else if (DISPLAY_VER(dev_priv) == 9) { 5295 encoder->enable_clock = skl_ddi_enable_clock; 5296 encoder->disable_clock = skl_ddi_disable_clock; 5297 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5298 encoder->get_config = skl_ddi_get_config; 5299 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5300 encoder->enable_clock = hsw_ddi_enable_clock; 5301 encoder->disable_clock = hsw_ddi_disable_clock; 5302 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5303 encoder->get_config = hsw_ddi_get_config; 5304 } 5305 5306 if (DISPLAY_VER(dev_priv) >= 14) { 5307 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5308 } else if (IS_DG2(dev_priv)) { 5309 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5310 } else if (DISPLAY_VER(dev_priv) >= 12) { 5311 if (intel_encoder_is_combo(encoder)) 5312 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5313 else 5314 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5315 } else if (DISPLAY_VER(dev_priv) >= 11) { 5316 if (intel_encoder_is_combo(encoder)) 5317 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5318 else 5319 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5320 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5321 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5322 } else { 5323 encoder->set_signal_levels = hsw_set_signal_levels; 5324 } 5325 5326 intel_ddi_buf_trans_init(encoder); 5327 5328 if (DISPLAY_VER(dev_priv) >= 13) 5329 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5330 else if (IS_DG1(dev_priv)) 5331 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5332 else if (IS_ROCKETLAKE(dev_priv)) 5333 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5334 else if (DISPLAY_VER(dev_priv) >= 12) 5335 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5336 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5337 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5338 else if (DISPLAY_VER(dev_priv) == 11) 5339 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5340 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5341 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5342 else 5343 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5344 5345 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 5346 5347 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5348 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5349 5350 dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5351 5352 dig_port->dp.output_reg = INVALID_MMIO_REG; 5353 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5354 5355 if (need_aux_ch(encoder, init_dp)) { 5356 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5357 if (dig_port->aux_ch == AUX_CH_NONE) 5358 goto err; 5359 } 5360 5361 if (intel_encoder_is_tc(encoder)) { 5362 bool is_legacy = 5363 !intel_bios_encoder_supports_typec_usb(devdata) && 5364 !intel_bios_encoder_supports_tbt(devdata); 5365 5366 if (!is_legacy && init_hdmi) { 5367 is_legacy = !init_dp; 5368 5369 drm_dbg_kms(&dev_priv->drm, 5370 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5371 port_name(port), 5372 str_yes_no(init_dp), 5373 is_legacy ? "legacy" : "non-legacy"); 5374 } 5375 5376 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5377 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5378 5379 dig_port->lock = intel_tc_port_lock; 5380 dig_port->unlock = intel_tc_port_unlock; 5381 5382 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5383 goto err; 5384 } 5385 5386 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5387 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5388 5389 if (DISPLAY_VER(dev_priv) >= 11) { 5390 if (intel_encoder_is_tc(encoder)) 5391 dig_port->connected = intel_tc_port_connected; 5392 else 5393 dig_port->connected = lpt_digital_port_connected; 5394 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5395 dig_port->connected = bdw_digital_port_connected; 5396 } else if (DISPLAY_VER(dev_priv) == 9) { 5397 dig_port->connected = lpt_digital_port_connected; 5398 } else if (IS_BROADWELL(dev_priv)) { 5399 if (port == PORT_A) 5400 dig_port->connected = bdw_digital_port_connected; 5401 else 5402 dig_port->connected = lpt_digital_port_connected; 5403 } else if (IS_HASWELL(dev_priv)) { 5404 if (port == PORT_A) 5405 dig_port->connected = hsw_digital_port_connected; 5406 else 5407 dig_port->connected = lpt_digital_port_connected; 5408 } 5409 5410 intel_infoframe_init(dig_port); 5411 5412 if (init_dp) { 5413 if (intel_ddi_init_dp_connector(dig_port)) 5414 goto err; 5415 5416 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5417 5418 if (dig_port->dp.mso_link_count) 5419 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5420 } 5421 5422 /* 5423 * In theory we don't need the encoder->type check, 5424 * but leave it just in case we have some really bad VBTs... 5425 */ 5426 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5427 if (intel_ddi_init_hdmi_connector(dig_port)) 5428 goto err; 5429 } 5430 5431 return; 5432 5433 err: 5434 drm_encoder_cleanup(&encoder->base); 5435 kfree(dig_port); 5436 } 5437