1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 37 #include "i915_reg.h" 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_display_utils.h" 56 #include "intel_dkl_phy.h" 57 #include "intel_dkl_phy_regs.h" 58 #include "intel_dp.h" 59 #include "intel_dp_aux.h" 60 #include "intel_dp_link_training.h" 61 #include "intel_dp_mst.h" 62 #include "intel_dp_test.h" 63 #include "intel_dp_tunnel.h" 64 #include "intel_dpio_phy.h" 65 #include "intel_dsi.h" 66 #include "intel_encoder.h" 67 #include "intel_fdi.h" 68 #include "intel_fifo_underrun.h" 69 #include "intel_gmbus.h" 70 #include "intel_hdcp.h" 71 #include "intel_hdmi.h" 72 #include "intel_hotplug.h" 73 #include "intel_hti.h" 74 #include "intel_lspcon.h" 75 #include "intel_lt_phy.h" 76 #include "intel_mg_phy_regs.h" 77 #include "intel_modeset_lock.h" 78 #include "intel_panel.h" 79 #include "intel_pfit.h" 80 #include "intel_pps.h" 81 #include "intel_psr.h" 82 #include "intel_quirks.h" 83 #include "intel_snps_phy.h" 84 #include "intel_step.h" 85 #include "intel_tc.h" 86 #include "intel_vdsc.h" 87 #include "intel_vdsc_regs.h" 88 #include "intel_vrr.h" 89 #include "skl_scaler.h" 90 #include "skl_universal_plane.h" 91 92 struct intel_dpll; 93 94 static const u8 index_to_dp_signal_levels[] = { 95 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 98 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 99 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 100 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 101 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 102 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 103 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 104 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 105 }; 106 107 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 108 const struct intel_ddi_buf_trans *trans) 109 { 110 int level; 111 112 level = intel_bios_hdmi_level_shift(encoder->devdata); 113 if (level < 0) 114 level = trans->hdmi_default_entry; 115 116 return level; 117 } 118 119 static bool has_buf_trans_select(struct intel_display *display) 120 { 121 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 122 } 123 124 static bool has_iboost(struct intel_display *display) 125 { 126 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 127 } 128 129 /* 130 * Starting with Haswell, DDI port buffers must be programmed with correct 131 * values in advance. This function programs the correct values for 132 * DP/eDP/FDI use cases. 133 */ 134 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 135 const struct intel_crtc_state *crtc_state) 136 { 137 struct intel_display *display = to_intel_display(encoder); 138 u32 iboost_bit = 0; 139 int i, n_entries; 140 enum port port = encoder->port; 141 const struct intel_ddi_buf_trans *trans; 142 143 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 144 if (drm_WARN_ON_ONCE(display->drm, !trans)) 145 return; 146 147 /* If we're boosting the current, set bit 31 of trans1 */ 148 if (has_iboost(display) && 149 intel_bios_dp_boost_level(encoder->devdata)) 150 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 151 152 for (i = 0; i < n_entries; i++) { 153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 154 trans->entries[i].hsw.trans1 | iboost_bit); 155 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 156 trans->entries[i].hsw.trans2); 157 } 158 } 159 160 /* 161 * Starting with Haswell, DDI port buffers must be programmed with correct 162 * values in advance. This function programs the correct values for 163 * HDMI/DVI use cases. 164 */ 165 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 166 const struct intel_crtc_state *crtc_state) 167 { 168 struct intel_display *display = to_intel_display(encoder); 169 int level = intel_ddi_level(encoder, crtc_state, 0); 170 u32 iboost_bit = 0; 171 int n_entries; 172 enum port port = encoder->port; 173 const struct intel_ddi_buf_trans *trans; 174 175 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 176 if (drm_WARN_ON_ONCE(display->drm, !trans)) 177 return; 178 179 /* If we're boosting the current, set bit 31 of trans1 */ 180 if (has_iboost(display) && 181 intel_bios_hdmi_boost_level(encoder->devdata)) 182 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 183 184 /* Entry 9 is for HDMI: */ 185 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 186 trans->entries[level].hsw.trans1 | iboost_bit); 187 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 188 trans->entries[level].hsw.trans2); 189 } 190 191 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 192 { 193 if (DISPLAY_VER(display) >= 14) 194 return XELPDP_PORT_BUF_CTL1(display, port); 195 else 196 return DDI_BUF_CTL(port); 197 } 198 199 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 200 { 201 /* 202 * Bspec's platform specific timeouts: 203 * MTL+ : 100 us 204 * BXT : fixed 16 us 205 * HSW-ADL: 8 us 206 * 207 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 208 */ 209 if (display->platform.broxton) { 210 udelay(16); 211 return; 212 } 213 214 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 215 if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port), 216 DDI_BUF_IS_IDLE, 10)) 217 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 218 port_name(port)); 219 } 220 221 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 222 { 223 struct intel_display *display = to_intel_display(encoder); 224 enum port port = encoder->port; 225 226 /* 227 * Bspec's platform specific timeouts: 228 * MTL+ : 10000 us 229 * DG2 : 1200 us 230 * TGL-ADL combo PHY: 1000 us 231 * TGL-ADL TypeC PHY: 3000 us 232 * HSW-ICL : fixed 518 us 233 */ 234 if (DISPLAY_VER(display) < 10) { 235 usleep_range(518, 1000); 236 return; 237 } 238 239 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 240 if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port), 241 DDI_BUF_IS_IDLE, 10)) 242 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_dpll *pll = crtc_state->intel_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static int dp_phy_lane_stagger_delay(int port_clock) 332 { 333 /* 334 * Return the number of symbol clocks delay used to stagger the 335 * assertion/desassertion of the port lane enables. The target delay 336 * time is 100 ns or greater, return the number of symbols specific to 337 * the provided port_clock (aka link clock) corresponding to this delay 338 * time, i.e. so that 339 * 340 * number_of_symbols * duration_of_one_symbol >= 100 ns 341 * 342 * The delay must be applied only on TypeC DP outputs, for everything else 343 * the delay must be set to 0. 344 * 345 * Return the number of link symbols per 100 ns: 346 * port_clock (10 kHz) -> bits / 100 us 347 * / symbol_size -> symbols / 100 us 348 * / 1000 -> symbols / 100 ns 349 */ 350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 351 } 352 353 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state) 355 { 356 struct intel_display *display = to_intel_display(encoder); 357 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 358 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 359 360 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 362 DDI_BUF_TRANS_SELECT(0); 363 364 if (dig_port->lane_reversal) 365 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 366 if (dig_port->ddi_a_4_lanes) 367 intel_dp->DP |= DDI_A_4_LANES; 368 369 if (DISPLAY_VER(display) >= 14) { 370 if (intel_dp_is_uhbr(crtc_state)) 371 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 372 else 373 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 374 } 375 376 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 378 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 379 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 380 } 381 382 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 384 385 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 386 } 387 } 388 389 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 390 { 391 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 392 393 switch (val) { 394 case DDI_CLK_SEL_NONE: 395 return 0; 396 case DDI_CLK_SEL_TBT_162: 397 return 162000; 398 case DDI_CLK_SEL_TBT_270: 399 return 270000; 400 case DDI_CLK_SEL_TBT_540: 401 return 540000; 402 case DDI_CLK_SEL_TBT_810: 403 return 810000; 404 default: 405 MISSING_CASE(val); 406 return 0; 407 } 408 } 409 410 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 411 { 412 /* CRT dotclock is determined via other means */ 413 if (pipe_config->has_pch_encoder) 414 return; 415 416 pipe_config->hw.adjusted_mode.crtc_clock = 417 intel_crtc_dotclock(pipe_config); 418 } 419 420 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 421 const struct drm_connector_state *conn_state) 422 { 423 struct intel_display *display = to_intel_display(crtc_state); 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 u32 temp; 426 427 if (!intel_crtc_has_dp_encoder(crtc_state)) 428 return; 429 430 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 431 432 temp = DP_MSA_MISC_SYNC_CLOCK; 433 434 switch (crtc_state->pipe_bpp) { 435 case 18: 436 temp |= DP_MSA_MISC_6_BPC; 437 break; 438 case 24: 439 temp |= DP_MSA_MISC_8_BPC; 440 break; 441 case 30: 442 temp |= DP_MSA_MISC_10_BPC; 443 break; 444 case 36: 445 temp |= DP_MSA_MISC_12_BPC; 446 break; 447 default: 448 MISSING_CASE(crtc_state->pipe_bpp); 449 break; 450 } 451 452 /* nonsense combination */ 453 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 454 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 455 456 if (crtc_state->limited_color_range) 457 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 458 459 /* 460 * As per DP 1.2 spec section 2.3.4.3 while sending 461 * YCBCR 444 signals we should program MSA MISC1/0 fields with 462 * colorspace information. 463 */ 464 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 465 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 466 467 /* 468 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 469 * of Color Encoding Format and Content Color Gamut] while sending 470 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 471 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 472 */ 473 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 474 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 475 476 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 477 temp); 478 } 479 480 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 481 { 482 if (master_transcoder == TRANSCODER_EDP) 483 return 0; 484 else 485 return master_transcoder + 1; 486 } 487 488 static void 489 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 490 bool enable) 491 { 492 struct intel_display *display = to_intel_display(crtc_state); 493 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 494 u32 val = 0; 495 496 if (!HAS_DP20(display)) 497 return; 498 499 if (enable && intel_dp_is_uhbr(crtc_state)) 500 val = TRANS_DP2_128B132B_CHANNEL_CODING; 501 502 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 503 } 504 505 /* 506 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 507 * 508 * Only intended to be used by intel_ddi_enable_transcoder_func() and 509 * intel_ddi_config_transcoder_func(). 510 */ 511 static u32 512 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 513 const struct intel_crtc_state *crtc_state) 514 { 515 struct intel_display *display = to_intel_display(crtc_state); 516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 517 enum pipe pipe = crtc->pipe; 518 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 519 enum port port = encoder->port; 520 u32 temp; 521 522 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 523 temp = TRANS_DDI_FUNC_ENABLE; 524 if (DISPLAY_VER(display) >= 12) 525 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 526 else 527 temp |= TRANS_DDI_SELECT_PORT(port); 528 529 switch (crtc_state->pipe_bpp) { 530 default: 531 MISSING_CASE(crtc_state->pipe_bpp); 532 fallthrough; 533 case 18: 534 temp |= TRANS_DDI_BPC_6; 535 break; 536 case 24: 537 temp |= TRANS_DDI_BPC_8; 538 break; 539 case 30: 540 temp |= TRANS_DDI_BPC_10; 541 break; 542 case 36: 543 temp |= TRANS_DDI_BPC_12; 544 break; 545 } 546 547 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 548 temp |= TRANS_DDI_PVSYNC; 549 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 550 temp |= TRANS_DDI_PHSYNC; 551 552 if (cpu_transcoder == TRANSCODER_EDP) { 553 switch (pipe) { 554 default: 555 MISSING_CASE(pipe); 556 fallthrough; 557 case PIPE_A: 558 /* On Haswell, can only use the always-on power well for 559 * eDP when not using the panel fitter, and when not 560 * using motion blur mitigation (which we don't 561 * support). */ 562 if (crtc_state->pch_pfit.force_thru) 563 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 564 else 565 temp |= TRANS_DDI_EDP_INPUT_A_ON; 566 break; 567 case PIPE_B: 568 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 569 break; 570 case PIPE_C: 571 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 572 break; 573 } 574 } 575 576 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 577 if (crtc_state->has_hdmi_sink) 578 temp |= TRANS_DDI_MODE_SELECT_HDMI; 579 else 580 temp |= TRANS_DDI_MODE_SELECT_DVI; 581 582 if (crtc_state->hdmi_scrambling) 583 temp |= TRANS_DDI_HDMI_SCRAMBLING; 584 if (crtc_state->hdmi_high_tmds_clock_ratio) 585 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 586 if (DISPLAY_VER(display) >= 14) 587 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 588 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 589 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 590 temp |= (crtc_state->fdi_lanes - 1) << 1; 591 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 592 intel_dp_is_uhbr(crtc_state)) { 593 if (intel_dp_is_uhbr(crtc_state)) 594 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 595 else 596 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 597 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 598 599 if (DISPLAY_VER(display) >= 12) { 600 enum transcoder master; 601 602 master = crtc_state->mst_master_transcoder; 603 if (drm_WARN_ON(display->drm, 604 master == INVALID_TRANSCODER)) 605 master = TRANSCODER_A; 606 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 607 } 608 } else { 609 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 610 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 611 } 612 613 if (IS_DISPLAY_VER(display, 8, 10) && 614 crtc_state->master_transcoder != INVALID_TRANSCODER) { 615 u8 master_select = 616 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 617 618 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 619 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 620 } 621 622 return temp; 623 } 624 625 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 626 const struct intel_crtc_state *crtc_state) 627 { 628 struct intel_display *display = to_intel_display(crtc_state); 629 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 630 631 if (DISPLAY_VER(display) >= 11) { 632 enum transcoder master_transcoder = crtc_state->master_transcoder; 633 u32 ctl2 = 0; 634 635 if (master_transcoder != INVALID_TRANSCODER) { 636 u8 master_select = 637 bdw_trans_port_sync_master_select(master_transcoder); 638 639 ctl2 |= PORT_SYNC_MODE_ENABLE | 640 PORT_SYNC_MODE_MASTER_SELECT(master_select); 641 } 642 643 intel_de_write(display, 644 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 645 ctl2); 646 } 647 648 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 649 intel_ddi_transcoder_func_reg_val_get(encoder, 650 crtc_state)); 651 } 652 653 /* 654 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 655 * bit for the DDI function and enables the DP2 configuration. Called for all 656 * transcoder types. 657 */ 658 void 659 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 660 const struct intel_crtc_state *crtc_state) 661 { 662 struct intel_display *display = to_intel_display(crtc_state); 663 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 664 u32 ctl; 665 666 intel_ddi_config_transcoder_dp2(crtc_state, true); 667 668 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 669 ctl &= ~TRANS_DDI_FUNC_ENABLE; 670 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 671 ctl); 672 } 673 674 /* 675 * Disable the DDI function and port syncing. 676 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 677 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 678 * transcoders these are done later in intel_ddi_post_disable_dp(). 679 */ 680 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 681 { 682 struct intel_display *display = to_intel_display(crtc_state); 683 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 684 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 685 u32 ctl; 686 687 if (DISPLAY_VER(display) >= 11) 688 intel_de_write(display, 689 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 690 0); 691 692 ctl = intel_de_read(display, 693 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 694 695 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 696 697 ctl &= ~TRANS_DDI_FUNC_ENABLE; 698 699 if (IS_DISPLAY_VER(display, 8, 10)) 700 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 701 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 702 703 if (DISPLAY_VER(display) >= 12) { 704 if (!intel_dp_mst_is_master_trans(crtc_state)) { 705 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 706 TRANS_DDI_MODE_SELECT_MASK); 707 } 708 } else { 709 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 710 } 711 712 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 713 ctl); 714 715 if (intel_dp_mst_is_slave_trans(crtc_state)) 716 intel_ddi_config_transcoder_dp2(crtc_state, false); 717 718 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 719 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 720 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 721 /* Quirk time at 100ms for reliable operation */ 722 msleep(100); 723 } 724 } 725 726 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 727 enum transcoder cpu_transcoder, 728 bool enable, u32 hdcp_mask) 729 { 730 struct intel_display *display = to_intel_display(intel_encoder); 731 struct ref_tracker *wakeref; 732 int ret = 0; 733 734 wakeref = intel_display_power_get_if_enabled(display, 735 intel_encoder->power_domain); 736 if (drm_WARN_ON(display->drm, !wakeref)) 737 return -ENXIO; 738 739 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 740 hdcp_mask, enable ? hdcp_mask : 0); 741 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 742 return ret; 743 } 744 745 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 746 { 747 struct intel_display *display = to_intel_display(intel_connector); 748 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 749 int type = intel_connector->base.connector_type; 750 enum port port = encoder->port; 751 enum transcoder cpu_transcoder; 752 struct ref_tracker *wakeref; 753 enum pipe pipe = 0; 754 u32 ddi_mode; 755 bool ret; 756 757 wakeref = intel_display_power_get_if_enabled(display, 758 encoder->power_domain); 759 if (!wakeref) 760 return false; 761 762 /* Note: This returns false for DP MST primary encoders. */ 763 if (!encoder->get_hw_state(encoder, &pipe)) { 764 ret = false; 765 goto out; 766 } 767 768 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 769 cpu_transcoder = TRANSCODER_EDP; 770 else 771 cpu_transcoder = (enum transcoder) pipe; 772 773 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 774 TRANS_DDI_MODE_SELECT_MASK; 775 776 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 777 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 778 ret = type == DRM_MODE_CONNECTOR_HDMIA; 779 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 780 ret = type == DRM_MODE_CONNECTOR_VGA; 781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 782 ret = type == DRM_MODE_CONNECTOR_eDP || 783 type == DRM_MODE_CONNECTOR_DisplayPort; 784 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 785 /* 786 * encoder->get_hw_state() should have bailed out on MST. This 787 * must be SST and non-eDP. 788 */ 789 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 790 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 791 /* encoder->get_hw_state() should have bailed out on MST. */ 792 ret = false; 793 } else { 794 ret = false; 795 } 796 797 out: 798 intel_display_power_put(display, encoder->power_domain, wakeref); 799 800 return ret; 801 } 802 803 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 804 u8 *pipe_mask, bool *is_dp_mst) 805 { 806 struct intel_display *display = to_intel_display(encoder); 807 enum port port = encoder->port; 808 struct ref_tracker *wakeref; 809 enum pipe p; 810 u32 tmp; 811 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 812 813 *pipe_mask = 0; 814 *is_dp_mst = false; 815 816 wakeref = intel_display_power_get_if_enabled(display, 817 encoder->power_domain); 818 if (!wakeref) 819 return; 820 821 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 822 if (!(tmp & DDI_BUF_CTL_ENABLE)) 823 goto out; 824 825 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 826 tmp = intel_de_read(display, 827 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 828 829 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 830 default: 831 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 832 fallthrough; 833 case TRANS_DDI_EDP_INPUT_A_ON: 834 case TRANS_DDI_EDP_INPUT_A_ONOFF: 835 *pipe_mask = BIT(PIPE_A); 836 break; 837 case TRANS_DDI_EDP_INPUT_B_ONOFF: 838 *pipe_mask = BIT(PIPE_B); 839 break; 840 case TRANS_DDI_EDP_INPUT_C_ONOFF: 841 *pipe_mask = BIT(PIPE_C); 842 break; 843 } 844 845 goto out; 846 } 847 848 for_each_pipe(display, p) { 849 enum transcoder cpu_transcoder = (enum transcoder)p; 850 u32 port_mask, ddi_select, ddi_mode; 851 struct ref_tracker *trans_wakeref; 852 853 trans_wakeref = intel_display_power_get_if_enabled(display, 854 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 855 if (!trans_wakeref) 856 continue; 857 858 if (DISPLAY_VER(display) >= 12) { 859 port_mask = TGL_TRANS_DDI_PORT_MASK; 860 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 861 } else { 862 port_mask = TRANS_DDI_PORT_MASK; 863 ddi_select = TRANS_DDI_SELECT_PORT(port); 864 } 865 866 tmp = intel_de_read(display, 867 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 868 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 869 trans_wakeref); 870 871 if ((tmp & port_mask) != ddi_select) 872 continue; 873 874 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 875 876 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 877 mst_pipe_mask |= BIT(p); 878 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 879 dp128b132b_pipe_mask |= BIT(p); 880 881 *pipe_mask |= BIT(p); 882 } 883 884 if (!*pipe_mask) 885 drm_dbg_kms(display->drm, 886 "No pipe for [ENCODER:%d:%s] found\n", 887 encoder->base.base.id, encoder->base.name); 888 889 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 890 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 891 892 /* 893 * If we don't have 8b/10b MST, but have more than one 894 * transcoder in 128b/132b mode, we know it must be 128b/132b 895 * MST. 896 * 897 * Otherwise, we fall back to checking the current MST 898 * state. It's not accurate for hardware takeover at probe, but 899 * we don't expect MST to have been enabled at that point, and 900 * can assume it's SST. 901 */ 902 if (hweight8(dp128b132b_pipe_mask) > 1 || 903 intel_dp_mst_active_streams(intel_dp)) 904 mst_pipe_mask = dp128b132b_pipe_mask; 905 } 906 907 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 908 drm_dbg_kms(display->drm, 909 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 910 encoder->base.base.id, encoder->base.name, 911 *pipe_mask); 912 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 913 } 914 915 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 916 drm_dbg_kms(display->drm, 917 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 918 encoder->base.base.id, encoder->base.name, 919 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 920 else 921 *is_dp_mst = mst_pipe_mask; 922 923 out: 924 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 925 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 926 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 927 BXT_PHY_LANE_POWERDOWN_ACK | 928 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 929 drm_err(display->drm, 930 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 931 encoder->base.base.id, encoder->base.name, tmp); 932 } 933 934 intel_display_power_put(display, encoder->power_domain, wakeref); 935 } 936 937 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 938 enum pipe *pipe) 939 { 940 u8 pipe_mask; 941 bool is_mst; 942 943 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 944 945 if (is_mst || !pipe_mask) 946 return false; 947 948 *pipe = ffs(pipe_mask) - 1; 949 950 return true; 951 } 952 953 static enum intel_display_power_domain 954 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 955 const struct intel_crtc_state *crtc_state) 956 { 957 struct intel_display *display = to_intel_display(dig_port); 958 959 /* 960 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 961 * DC states enabled at the same time, while for driver initiated AUX 962 * transfers we need the same AUX IOs to be powered but with DC states 963 * disabled. Accordingly use the AUX_IO_<port> power domain here which 964 * leaves DC states enabled. 965 * 966 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 967 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 968 * well, so we can acquire a wider AUX_<port> power domain reference 969 * instead of a specific AUX_IO_<port> reference without powering up any 970 * extra wells. 971 */ 972 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 973 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 974 else if (DISPLAY_VER(display) < 14 && 975 (intel_crtc_has_dp_encoder(crtc_state) || 976 intel_encoder_is_tc(&dig_port->base))) 977 return intel_aux_power_domain(dig_port); 978 else 979 return POWER_DOMAIN_INVALID; 980 } 981 982 static void 983 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 984 const struct intel_crtc_state *crtc_state) 985 { 986 struct intel_display *display = to_intel_display(dig_port); 987 enum intel_display_power_domain domain = 988 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 989 990 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 991 992 if (domain == POWER_DOMAIN_INVALID) 993 return; 994 995 dig_port->aux_wakeref = intel_display_power_get(display, domain); 996 } 997 998 static void 999 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 1000 const struct intel_crtc_state *crtc_state) 1001 { 1002 struct intel_display *display = to_intel_display(dig_port); 1003 enum intel_display_power_domain domain = 1004 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1005 struct ref_tracker *wf; 1006 1007 wf = fetch_and_zero(&dig_port->aux_wakeref); 1008 if (!wf) 1009 return; 1010 1011 intel_display_power_put(display, domain, wf); 1012 } 1013 1014 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1015 struct intel_crtc_state *crtc_state) 1016 { 1017 struct intel_display *display = to_intel_display(encoder); 1018 struct intel_digital_port *dig_port; 1019 1020 /* 1021 * TODO: Add support for MST encoders. Atm, the following should never 1022 * happen since fake-MST encoders don't set their get_power_domains() 1023 * hook. 1024 */ 1025 if (drm_WARN_ON(display->drm, 1026 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1027 return; 1028 1029 dig_port = enc_to_dig_port(encoder); 1030 1031 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1032 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1033 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1034 dig_port->ddi_io_power_domain); 1035 } 1036 1037 main_link_aux_power_domain_get(dig_port, crtc_state); 1038 } 1039 1040 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state) 1042 { 1043 struct intel_display *display = to_intel_display(crtc_state); 1044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1045 enum phy phy = intel_encoder_to_phy(encoder); 1046 u32 val; 1047 1048 if (cpu_transcoder == TRANSCODER_EDP) 1049 return; 1050 1051 if (DISPLAY_VER(display) >= 13) 1052 val = TGL_TRANS_CLK_SEL_PORT(phy); 1053 else if (DISPLAY_VER(display) >= 12) 1054 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1055 else 1056 val = TRANS_CLK_SEL_PORT(encoder->port); 1057 1058 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1059 } 1060 1061 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1062 { 1063 struct intel_display *display = to_intel_display(crtc_state); 1064 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1065 u32 val; 1066 1067 if (cpu_transcoder == TRANSCODER_EDP) 1068 return; 1069 1070 if (DISPLAY_VER(display) >= 12) 1071 val = TGL_TRANS_CLK_SEL_DISABLED; 1072 else 1073 val = TRANS_CLK_SEL_DISABLED; 1074 1075 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1076 } 1077 1078 static void _skl_ddi_set_iboost(struct intel_display *display, 1079 enum port port, u8 iboost) 1080 { 1081 u32 tmp; 1082 1083 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1084 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1085 if (iboost) 1086 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1087 else 1088 tmp |= BALANCE_LEG_DISABLE(port); 1089 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1090 } 1091 1092 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1093 const struct intel_crtc_state *crtc_state, 1094 int level) 1095 { 1096 struct intel_display *display = to_intel_display(encoder); 1097 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1098 u8 iboost; 1099 1100 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1101 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1102 else 1103 iboost = intel_bios_dp_boost_level(encoder->devdata); 1104 1105 if (iboost == 0) { 1106 const struct intel_ddi_buf_trans *trans; 1107 int n_entries; 1108 1109 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1110 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1111 return; 1112 1113 iboost = trans->entries[level].hsw.i_boost; 1114 } 1115 1116 /* Make sure that the requested I_boost is valid */ 1117 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1118 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1119 return; 1120 } 1121 1122 _skl_ddi_set_iboost(display, encoder->port, iboost); 1123 1124 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1125 _skl_ddi_set_iboost(display, PORT_E, iboost); 1126 } 1127 1128 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1129 const struct intel_crtc_state *crtc_state) 1130 { 1131 struct intel_display *display = to_intel_display(intel_dp); 1132 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1133 int n_entries; 1134 1135 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1136 1137 if (drm_WARN_ON(display->drm, n_entries < 1)) 1138 n_entries = 1; 1139 if (drm_WARN_ON(display->drm, 1140 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1141 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1142 1143 return index_to_dp_signal_levels[n_entries - 1] & 1144 DP_TRAIN_VOLTAGE_SWING_MASK; 1145 } 1146 1147 /* 1148 * We assume that the full set of pre-emphasis values can be 1149 * used on all DDI platforms. Should that change we need to 1150 * rethink this code. 1151 */ 1152 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1153 { 1154 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1155 } 1156 1157 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1158 int lane) 1159 { 1160 if (crtc_state->port_clock > 600000) 1161 return 0; 1162 1163 if (crtc_state->lane_count == 4) 1164 return lane >= 1 ? LOADGEN_SELECT : 0; 1165 else 1166 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1167 } 1168 1169 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1170 const struct intel_crtc_state *crtc_state) 1171 { 1172 struct intel_display *display = to_intel_display(encoder); 1173 const struct intel_ddi_buf_trans *trans; 1174 enum phy phy = intel_encoder_to_phy(encoder); 1175 int n_entries, ln; 1176 u32 val; 1177 1178 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1179 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1180 return; 1181 1182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1183 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1184 1185 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1186 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1187 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1188 intel_dp->hobl_active ? val : 0); 1189 } 1190 1191 /* Set PORT_TX_DW5 */ 1192 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1193 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1194 COEFF_POLARITY | CURSOR_PROGRAM | 1195 TAP2_DISABLE | TAP3_DISABLE); 1196 val |= SCALING_MODE_SEL(0x2); 1197 val |= RTERM_SELECT(0x6); 1198 val |= TAP3_DISABLE; 1199 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1200 1201 /* Program PORT_TX_DW2 */ 1202 for (ln = 0; ln < 4; ln++) { 1203 int level = intel_ddi_level(encoder, crtc_state, ln); 1204 1205 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1206 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1207 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1208 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1209 RCOMP_SCALAR(0x98)); 1210 } 1211 1212 /* Program PORT_TX_DW4 */ 1213 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1214 for (ln = 0; ln < 4; ln++) { 1215 int level = intel_ddi_level(encoder, crtc_state, ln); 1216 1217 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1218 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1219 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1220 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1221 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1222 } 1223 1224 /* Program PORT_TX_DW7 */ 1225 for (ln = 0; ln < 4; ln++) { 1226 int level = intel_ddi_level(encoder, crtc_state, ln); 1227 1228 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1229 N_SCALAR_MASK, 1230 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1231 } 1232 } 1233 1234 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1235 const struct intel_crtc_state *crtc_state) 1236 { 1237 struct intel_display *display = to_intel_display(encoder); 1238 enum phy phy = intel_encoder_to_phy(encoder); 1239 u32 val; 1240 int ln; 1241 1242 /* 1243 * 1. If port type is eDP or DP, 1244 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1245 * else clear to 0b. 1246 */ 1247 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1248 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1249 val &= ~COMMON_KEEPER_EN; 1250 else 1251 val |= COMMON_KEEPER_EN; 1252 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1253 1254 /* 2. Program loadgen select */ 1255 /* 1256 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1257 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1258 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1259 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1260 */ 1261 for (ln = 0; ln < 4; ln++) { 1262 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1263 LOADGEN_SELECT, 1264 icl_combo_phy_loadgen_select(crtc_state, ln)); 1265 } 1266 1267 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1268 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1269 0, SUS_CLOCK_CONFIG); 1270 1271 /* 4. Clear training enable to change swing values */ 1272 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1273 val &= ~TX_TRAINING_EN; 1274 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1275 1276 /* 5. Program swing and de-emphasis */ 1277 icl_ddi_combo_vswing_program(encoder, crtc_state); 1278 1279 /* 6. Set training enable to trigger update */ 1280 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1281 val |= TX_TRAINING_EN; 1282 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1283 } 1284 1285 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1286 const struct intel_crtc_state *crtc_state) 1287 { 1288 struct intel_display *display = to_intel_display(encoder); 1289 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1290 const struct intel_ddi_buf_trans *trans; 1291 int n_entries, ln; 1292 1293 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1294 return; 1295 1296 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1297 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1298 return; 1299 1300 for (ln = 0; ln < 2; ln++) { 1301 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1302 CRI_USE_FS32, 0); 1303 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1304 CRI_USE_FS32, 0); 1305 } 1306 1307 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1308 for (ln = 0; ln < 2; ln++) { 1309 int level; 1310 1311 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1312 1313 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1314 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1315 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1316 1317 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1318 1319 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1320 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1321 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1322 } 1323 1324 /* Program MG_TX_DRVCTRL with values from vswing table */ 1325 for (ln = 0; ln < 2; ln++) { 1326 int level; 1327 1328 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1329 1330 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1331 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1332 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1333 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1334 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1335 CRI_TXDEEMPH_OVERRIDE_EN); 1336 1337 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1338 1339 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1340 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1341 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1342 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1343 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1344 CRI_TXDEEMPH_OVERRIDE_EN); 1345 1346 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1347 } 1348 1349 /* 1350 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1351 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1352 * values from table for which TX1 and TX2 enabled. 1353 */ 1354 for (ln = 0; ln < 2; ln++) { 1355 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1356 CFG_LOW_RATE_LKREN_EN, 1357 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1358 } 1359 1360 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1361 for (ln = 0; ln < 2; ln++) { 1362 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1363 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1364 CFG_AMI_CK_DIV_OVERRIDE_EN, 1365 crtc_state->port_clock > 500000 ? 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1367 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1368 1369 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1370 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1371 CFG_AMI_CK_DIV_OVERRIDE_EN, 1372 crtc_state->port_clock > 500000 ? 1373 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1374 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1375 } 1376 1377 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1378 for (ln = 0; ln < 2; ln++) { 1379 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1380 0, CRI_CALCINIT); 1381 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1382 0, CRI_CALCINIT); 1383 } 1384 } 1385 1386 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1387 const struct intel_crtc_state *crtc_state) 1388 { 1389 struct intel_display *display = to_intel_display(encoder); 1390 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1391 const struct intel_ddi_buf_trans *trans; 1392 int n_entries, ln; 1393 1394 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1395 return; 1396 1397 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1398 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1399 return; 1400 1401 for (ln = 0; ln < 2; ln++) { 1402 int level; 1403 1404 /* Wa_16011342517:adl-p */ 1405 if (display->platform.alderlake_p && 1406 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) { 1407 if ((intel_encoder_is_hdmi(encoder) && 1408 crtc_state->port_clock == 594000) || 1409 (intel_encoder_is_dp(encoder) && 1410 crtc_state->port_clock == 162000)) { 1411 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1412 LOADGEN_SHARING_PMD_DISABLE, 1); 1413 } else { 1414 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1415 LOADGEN_SHARING_PMD_DISABLE, 0); 1416 } 1417 } 1418 1419 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1420 1421 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1422 1423 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1424 DKL_TX_PRESHOOT_COEFF_MASK | 1425 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1426 DKL_TX_VSWING_CONTROL_MASK, 1427 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1428 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1429 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1430 1431 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1432 1433 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1434 DKL_TX_PRESHOOT_COEFF_MASK | 1435 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1436 DKL_TX_VSWING_CONTROL_MASK, 1437 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1438 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1439 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1440 1441 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1442 DKL_TX_DP20BITMODE, 0); 1443 1444 if (display->platform.alderlake_p) { 1445 u32 val; 1446 1447 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1448 if (ln == 0) { 1449 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1450 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1451 } else { 1452 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1453 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1454 } 1455 } else { 1456 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1457 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1458 } 1459 1460 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1461 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1462 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1463 val); 1464 } 1465 } 1466 } 1467 1468 static int translate_signal_level(struct intel_dp *intel_dp, 1469 u8 signal_levels) 1470 { 1471 struct intel_display *display = to_intel_display(intel_dp); 1472 const u8 *signal_array; 1473 size_t array_size; 1474 int i; 1475 1476 signal_array = index_to_dp_signal_levels; 1477 array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1478 1479 for (i = 0; i < array_size; i++) { 1480 if (signal_array[i] == signal_levels) 1481 return i; 1482 } 1483 1484 drm_WARN(display->drm, 1, 1485 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1486 signal_levels); 1487 1488 return 0; 1489 } 1490 1491 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1492 const struct intel_crtc_state *crtc_state, 1493 int lane) 1494 { 1495 u8 train_set = intel_dp->train_set[lane]; 1496 1497 if (intel_dp_is_uhbr(crtc_state)) { 1498 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1499 } else { 1500 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1501 DP_TRAIN_PRE_EMPHASIS_MASK); 1502 1503 return translate_signal_level(intel_dp, signal_levels); 1504 } 1505 } 1506 1507 int intel_ddi_level(struct intel_encoder *encoder, 1508 const struct intel_crtc_state *crtc_state, 1509 int lane) 1510 { 1511 struct intel_display *display = to_intel_display(encoder); 1512 const struct intel_ddi_buf_trans *trans; 1513 int level, n_entries; 1514 1515 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1516 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1517 return 0; 1518 1519 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1520 level = intel_ddi_hdmi_level(encoder, trans); 1521 else 1522 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1523 lane); 1524 1525 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1526 level = n_entries - 1; 1527 1528 return level; 1529 } 1530 1531 static void 1532 hsw_set_signal_levels(struct intel_encoder *encoder, 1533 const struct intel_crtc_state *crtc_state) 1534 { 1535 struct intel_display *display = to_intel_display(encoder); 1536 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1537 int level = intel_ddi_level(encoder, crtc_state, 0); 1538 enum port port = encoder->port; 1539 u32 signal_levels; 1540 1541 if (has_iboost(display)) 1542 skl_ddi_set_iboost(encoder, crtc_state, level); 1543 1544 /* HDMI ignores the rest */ 1545 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1546 return; 1547 1548 signal_levels = DDI_BUF_TRANS_SELECT(level); 1549 1550 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1551 signal_levels); 1552 1553 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1554 intel_dp->DP |= signal_levels; 1555 1556 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1557 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1558 } 1559 1560 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1561 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1562 { 1563 mutex_lock(&display->dpll.lock); 1564 1565 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1566 1567 /* 1568 * "This step and the step before must be 1569 * done with separate register writes." 1570 */ 1571 intel_de_rmw(display, reg, clk_off, 0); 1572 1573 mutex_unlock(&display->dpll.lock); 1574 } 1575 1576 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1577 u32 clk_off) 1578 { 1579 mutex_lock(&display->dpll.lock); 1580 1581 intel_de_rmw(display, reg, 0, clk_off); 1582 1583 mutex_unlock(&display->dpll.lock); 1584 } 1585 1586 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1587 u32 clk_off) 1588 { 1589 return !(intel_de_read(display, reg) & clk_off); 1590 } 1591 1592 static struct intel_dpll * 1593 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1594 u32 clk_sel_mask, u32 clk_sel_shift) 1595 { 1596 enum intel_dpll_id id; 1597 1598 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1599 1600 return intel_get_dpll_by_id(display, id); 1601 } 1602 1603 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1604 const struct intel_crtc_state *crtc_state) 1605 { 1606 struct intel_display *display = to_intel_display(encoder); 1607 const struct intel_dpll *pll = crtc_state->intel_dpll; 1608 enum phy phy = intel_encoder_to_phy(encoder); 1609 1610 if (drm_WARN_ON(display->drm, !pll)) 1611 return; 1612 1613 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1614 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1615 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1616 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1617 } 1618 1619 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1620 { 1621 struct intel_display *display = to_intel_display(encoder); 1622 enum phy phy = intel_encoder_to_phy(encoder); 1623 1624 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1625 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1626 } 1627 1628 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1629 { 1630 struct intel_display *display = to_intel_display(encoder); 1631 enum phy phy = intel_encoder_to_phy(encoder); 1632 1633 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1634 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1635 } 1636 1637 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1638 { 1639 struct intel_display *display = to_intel_display(encoder); 1640 enum phy phy = intel_encoder_to_phy(encoder); 1641 1642 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1643 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1644 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1645 } 1646 1647 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1648 const struct intel_crtc_state *crtc_state) 1649 { 1650 struct intel_display *display = to_intel_display(encoder); 1651 const struct intel_dpll *pll = crtc_state->intel_dpll; 1652 enum phy phy = intel_encoder_to_phy(encoder); 1653 1654 if (drm_WARN_ON(display->drm, !pll)) 1655 return; 1656 1657 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1658 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1659 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1661 } 1662 1663 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1664 { 1665 struct intel_display *display = to_intel_display(encoder); 1666 enum phy phy = intel_encoder_to_phy(encoder); 1667 1668 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1669 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1670 } 1671 1672 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1673 { 1674 struct intel_display *display = to_intel_display(encoder); 1675 enum phy phy = intel_encoder_to_phy(encoder); 1676 1677 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1678 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1679 } 1680 1681 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1682 { 1683 struct intel_display *display = to_intel_display(encoder); 1684 enum phy phy = intel_encoder_to_phy(encoder); 1685 1686 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1687 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1688 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1689 } 1690 1691 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1692 const struct intel_crtc_state *crtc_state) 1693 { 1694 struct intel_display *display = to_intel_display(encoder); 1695 const struct intel_dpll *pll = crtc_state->intel_dpll; 1696 enum phy phy = intel_encoder_to_phy(encoder); 1697 1698 if (drm_WARN_ON(display->drm, !pll)) 1699 return; 1700 1701 /* 1702 * If we fail this, something went very wrong: first 2 PLLs should be 1703 * used by first 2 phys and last 2 PLLs by last phys 1704 */ 1705 if (drm_WARN_ON(display->drm, 1706 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1707 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1708 return; 1709 1710 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1711 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1712 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1713 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1714 } 1715 1716 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1717 { 1718 struct intel_display *display = to_intel_display(encoder); 1719 enum phy phy = intel_encoder_to_phy(encoder); 1720 1721 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1722 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1723 } 1724 1725 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1726 { 1727 struct intel_display *display = to_intel_display(encoder); 1728 enum phy phy = intel_encoder_to_phy(encoder); 1729 1730 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1731 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1732 } 1733 1734 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1735 { 1736 struct intel_display *display = to_intel_display(encoder); 1737 enum phy phy = intel_encoder_to_phy(encoder); 1738 enum intel_dpll_id id; 1739 u32 val; 1740 1741 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1742 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1743 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1744 id = val; 1745 1746 /* 1747 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1748 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1749 * bit for phy C and D. 1750 */ 1751 if (phy >= PHY_C) 1752 id += DPLL_ID_DG1_DPLL2; 1753 1754 return intel_get_dpll_by_id(display, id); 1755 } 1756 1757 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1758 const struct intel_crtc_state *crtc_state) 1759 { 1760 struct intel_display *display = to_intel_display(encoder); 1761 const struct intel_dpll *pll = crtc_state->intel_dpll; 1762 enum phy phy = intel_encoder_to_phy(encoder); 1763 1764 if (drm_WARN_ON(display->drm, !pll)) 1765 return; 1766 1767 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1768 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1769 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1771 } 1772 1773 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1774 { 1775 struct intel_display *display = to_intel_display(encoder); 1776 enum phy phy = intel_encoder_to_phy(encoder); 1777 1778 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1779 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1780 } 1781 1782 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1783 { 1784 struct intel_display *display = to_intel_display(encoder); 1785 enum phy phy = intel_encoder_to_phy(encoder); 1786 1787 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1788 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1789 } 1790 1791 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1792 { 1793 struct intel_display *display = to_intel_display(encoder); 1794 enum phy phy = intel_encoder_to_phy(encoder); 1795 1796 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1797 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1798 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1799 } 1800 1801 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1802 const struct intel_crtc_state *crtc_state) 1803 { 1804 struct intel_display *display = to_intel_display(encoder); 1805 const struct intel_dpll *pll = crtc_state->intel_dpll; 1806 enum port port = encoder->port; 1807 1808 if (drm_WARN_ON(display->drm, !pll)) 1809 return; 1810 1811 /* 1812 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1813 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1814 */ 1815 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1816 1817 icl_ddi_combo_enable_clock(encoder, crtc_state); 1818 } 1819 1820 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1821 { 1822 struct intel_display *display = to_intel_display(encoder); 1823 enum port port = encoder->port; 1824 1825 icl_ddi_combo_disable_clock(encoder); 1826 1827 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1828 } 1829 1830 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1831 { 1832 struct intel_display *display = to_intel_display(encoder); 1833 enum port port = encoder->port; 1834 u32 tmp; 1835 1836 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1837 1838 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1839 return false; 1840 1841 return icl_ddi_combo_is_clock_enabled(encoder); 1842 } 1843 1844 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1845 const struct intel_crtc_state *crtc_state) 1846 { 1847 struct intel_display *display = to_intel_display(encoder); 1848 const struct intel_dpll *pll = crtc_state->intel_dpll; 1849 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1850 enum port port = encoder->port; 1851 1852 if (drm_WARN_ON(display->drm, !pll)) 1853 return; 1854 1855 intel_de_write(display, DDI_CLK_SEL(port), 1856 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1857 1858 mutex_lock(&display->dpll.lock); 1859 1860 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1861 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1862 1863 mutex_unlock(&display->dpll.lock); 1864 } 1865 1866 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1867 { 1868 struct intel_display *display = to_intel_display(encoder); 1869 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1870 enum port port = encoder->port; 1871 1872 mutex_lock(&display->dpll.lock); 1873 1874 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1875 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1876 1877 mutex_unlock(&display->dpll.lock); 1878 1879 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1880 } 1881 1882 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1883 { 1884 struct intel_display *display = to_intel_display(encoder); 1885 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1886 enum port port = encoder->port; 1887 u32 tmp; 1888 1889 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1890 1891 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1892 return false; 1893 1894 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1895 1896 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1897 } 1898 1899 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1900 { 1901 struct intel_display *display = to_intel_display(encoder); 1902 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1903 enum port port = encoder->port; 1904 enum intel_dpll_id id; 1905 u32 tmp; 1906 1907 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1908 1909 switch (tmp & DDI_CLK_SEL_MASK) { 1910 case DDI_CLK_SEL_TBT_162: 1911 case DDI_CLK_SEL_TBT_270: 1912 case DDI_CLK_SEL_TBT_540: 1913 case DDI_CLK_SEL_TBT_810: 1914 id = DPLL_ID_ICL_TBTPLL; 1915 break; 1916 case DDI_CLK_SEL_MG: 1917 id = icl_tc_port_to_pll_id(tc_port); 1918 break; 1919 default: 1920 MISSING_CASE(tmp); 1921 fallthrough; 1922 case DDI_CLK_SEL_NONE: 1923 return NULL; 1924 } 1925 1926 return intel_get_dpll_by_id(display, id); 1927 } 1928 1929 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1930 { 1931 struct intel_display *display = to_intel_display(encoder->base.dev); 1932 enum intel_dpll_id id; 1933 1934 switch (encoder->port) { 1935 case PORT_A: 1936 id = DPLL_ID_SKL_DPLL0; 1937 break; 1938 case PORT_B: 1939 id = DPLL_ID_SKL_DPLL1; 1940 break; 1941 case PORT_C: 1942 id = DPLL_ID_SKL_DPLL2; 1943 break; 1944 default: 1945 MISSING_CASE(encoder->port); 1946 return NULL; 1947 } 1948 1949 return intel_get_dpll_by_id(display, id); 1950 } 1951 1952 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1953 const struct intel_crtc_state *crtc_state) 1954 { 1955 struct intel_display *display = to_intel_display(encoder); 1956 const struct intel_dpll *pll = crtc_state->intel_dpll; 1957 enum port port = encoder->port; 1958 1959 if (drm_WARN_ON(display->drm, !pll)) 1960 return; 1961 1962 mutex_lock(&display->dpll.lock); 1963 1964 intel_de_rmw(display, DPLL_CTRL2, 1965 DPLL_CTRL2_DDI_CLK_OFF(port) | 1966 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1967 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1968 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1969 1970 mutex_unlock(&display->dpll.lock); 1971 } 1972 1973 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1974 { 1975 struct intel_display *display = to_intel_display(encoder); 1976 enum port port = encoder->port; 1977 1978 mutex_lock(&display->dpll.lock); 1979 1980 intel_de_rmw(display, DPLL_CTRL2, 1981 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1982 1983 mutex_unlock(&display->dpll.lock); 1984 } 1985 1986 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1987 { 1988 struct intel_display *display = to_intel_display(encoder); 1989 enum port port = encoder->port; 1990 1991 /* 1992 * FIXME Not sure if the override affects both 1993 * the PLL selection and the CLK_OFF bit. 1994 */ 1995 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1996 } 1997 1998 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1999 { 2000 struct intel_display *display = to_intel_display(encoder); 2001 enum port port = encoder->port; 2002 enum intel_dpll_id id; 2003 u32 tmp; 2004 2005 tmp = intel_de_read(display, DPLL_CTRL2); 2006 2007 /* 2008 * FIXME Not sure if the override affects both 2009 * the PLL selection and the CLK_OFF bit. 2010 */ 2011 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2012 return NULL; 2013 2014 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2015 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2016 2017 return intel_get_dpll_by_id(display, id); 2018 } 2019 2020 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2021 const struct intel_crtc_state *crtc_state) 2022 { 2023 struct intel_display *display = to_intel_display(encoder); 2024 const struct intel_dpll *pll = crtc_state->intel_dpll; 2025 enum port port = encoder->port; 2026 2027 if (drm_WARN_ON(display->drm, !pll)) 2028 return; 2029 2030 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2031 } 2032 2033 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2034 { 2035 struct intel_display *display = to_intel_display(encoder); 2036 enum port port = encoder->port; 2037 2038 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2039 } 2040 2041 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2042 { 2043 struct intel_display *display = to_intel_display(encoder); 2044 enum port port = encoder->port; 2045 2046 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2047 } 2048 2049 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2050 { 2051 struct intel_display *display = to_intel_display(encoder); 2052 enum port port = encoder->port; 2053 enum intel_dpll_id id; 2054 u32 tmp; 2055 2056 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2057 2058 switch (tmp & PORT_CLK_SEL_MASK) { 2059 case PORT_CLK_SEL_WRPLL1: 2060 id = DPLL_ID_WRPLL1; 2061 break; 2062 case PORT_CLK_SEL_WRPLL2: 2063 id = DPLL_ID_WRPLL2; 2064 break; 2065 case PORT_CLK_SEL_SPLL: 2066 id = DPLL_ID_SPLL; 2067 break; 2068 case PORT_CLK_SEL_LCPLL_810: 2069 id = DPLL_ID_LCPLL_810; 2070 break; 2071 case PORT_CLK_SEL_LCPLL_1350: 2072 id = DPLL_ID_LCPLL_1350; 2073 break; 2074 case PORT_CLK_SEL_LCPLL_2700: 2075 id = DPLL_ID_LCPLL_2700; 2076 break; 2077 default: 2078 MISSING_CASE(tmp); 2079 fallthrough; 2080 case PORT_CLK_SEL_NONE: 2081 return NULL; 2082 } 2083 2084 return intel_get_dpll_by_id(display, id); 2085 } 2086 2087 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2088 const struct intel_crtc_state *crtc_state) 2089 { 2090 if (encoder->enable_clock) 2091 encoder->enable_clock(encoder, crtc_state); 2092 } 2093 2094 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2095 { 2096 if (encoder->disable_clock) 2097 encoder->disable_clock(encoder); 2098 } 2099 2100 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2101 { 2102 struct intel_display *display = to_intel_display(encoder); 2103 u32 port_mask; 2104 bool ddi_clk_needed; 2105 2106 /* 2107 * In case of DP MST, we sanitize the primary encoder only, not the 2108 * virtual ones. 2109 */ 2110 if (encoder->type == INTEL_OUTPUT_DP_MST) 2111 return; 2112 2113 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2114 u8 pipe_mask; 2115 bool is_mst; 2116 2117 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2118 /* 2119 * In the unlikely case that BIOS enables DP in MST mode, just 2120 * warn since our MST HW readout is incomplete. 2121 */ 2122 if (drm_WARN_ON(display->drm, is_mst)) 2123 return; 2124 } 2125 2126 port_mask = BIT(encoder->port); 2127 ddi_clk_needed = encoder->base.crtc; 2128 2129 if (encoder->type == INTEL_OUTPUT_DSI) { 2130 struct intel_encoder *other_encoder; 2131 2132 port_mask = intel_dsi_encoder_ports(encoder); 2133 /* 2134 * Sanity check that we haven't incorrectly registered another 2135 * encoder using any of the ports of this DSI encoder. 2136 */ 2137 for_each_intel_encoder(display->drm, other_encoder) { 2138 if (other_encoder == encoder) 2139 continue; 2140 2141 if (drm_WARN_ON(display->drm, 2142 port_mask & BIT(other_encoder->port))) 2143 return; 2144 } 2145 /* 2146 * For DSI we keep the ddi clocks gated 2147 * except during enable/disable sequence. 2148 */ 2149 ddi_clk_needed = false; 2150 } 2151 2152 if (ddi_clk_needed || !encoder->is_clock_enabled || 2153 !encoder->is_clock_enabled(encoder)) 2154 return; 2155 2156 drm_dbg_kms(display->drm, 2157 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2158 encoder->base.base.id, encoder->base.name); 2159 2160 encoder->disable_clock(encoder); 2161 } 2162 2163 static void 2164 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2165 enum tc_port tc_port, u32 ln0, u32 ln1) 2166 { 2167 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2168 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2169 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2170 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2171 } 2172 2173 static void 2174 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2175 const struct intel_crtc_state *crtc_state) 2176 { 2177 struct intel_display *display = to_intel_display(crtc_state); 2178 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2179 enum intel_tc_pin_assignment pin_assignment; 2180 u32 ln0, ln1; 2181 u8 width; 2182 2183 if (DISPLAY_VER(display) >= 14) 2184 return; 2185 2186 if (!intel_encoder_is_tc(&dig_port->base) || 2187 intel_tc_port_in_tbt_alt_mode(dig_port)) 2188 return; 2189 2190 if (DISPLAY_VER(display) >= 12) { 2191 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2192 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2193 } else { 2194 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2195 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2196 } 2197 2198 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2199 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2200 2201 /* DPPATC */ 2202 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2203 width = crtc_state->lane_count; 2204 2205 switch (pin_assignment) { 2206 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2207 drm_WARN_ON(display->drm, 2208 !intel_tc_port_in_legacy_mode(dig_port)); 2209 if (width == 1) { 2210 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2211 } else { 2212 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2213 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2214 } 2215 break; 2216 case INTEL_TC_PIN_ASSIGNMENT_A: 2217 if (width == 4) { 2218 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2219 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2220 } 2221 break; 2222 case INTEL_TC_PIN_ASSIGNMENT_B: 2223 if (width == 2) { 2224 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2225 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 } 2227 break; 2228 case INTEL_TC_PIN_ASSIGNMENT_C: 2229 case INTEL_TC_PIN_ASSIGNMENT_E: 2230 if (width == 1) { 2231 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2232 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2233 } else { 2234 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2235 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2236 } 2237 break; 2238 case INTEL_TC_PIN_ASSIGNMENT_D: 2239 case INTEL_TC_PIN_ASSIGNMENT_F: 2240 if (width == 1) { 2241 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2242 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2243 } else { 2244 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2245 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2246 } 2247 break; 2248 default: 2249 MISSING_CASE(pin_assignment); 2250 } 2251 2252 if (DISPLAY_VER(display) >= 12) { 2253 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2254 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2255 /* WA_14018221282 */ 2256 if (IS_DISPLAY_VER(display, 12, 13)) 2257 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2258 2259 } else { 2260 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2261 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2262 } 2263 } 2264 2265 static enum transcoder 2266 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2267 { 2268 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2269 return crtc_state->mst_master_transcoder; 2270 else 2271 return crtc_state->cpu_transcoder; 2272 } 2273 2274 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2275 const struct intel_crtc_state *crtc_state) 2276 { 2277 struct intel_display *display = to_intel_display(encoder); 2278 2279 if (DISPLAY_VER(display) >= 12) 2280 return TGL_DP_TP_CTL(display, 2281 tgl_dp_tp_transcoder(crtc_state)); 2282 else 2283 return DP_TP_CTL(encoder->port); 2284 } 2285 2286 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2287 const struct intel_crtc_state *crtc_state) 2288 { 2289 struct intel_display *display = to_intel_display(encoder); 2290 2291 if (DISPLAY_VER(display) >= 12) 2292 return TGL_DP_TP_STATUS(display, 2293 tgl_dp_tp_transcoder(crtc_state)); 2294 else 2295 return DP_TP_STATUS(encoder->port); 2296 } 2297 2298 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2299 const struct intel_crtc_state *crtc_state) 2300 { 2301 struct intel_display *display = to_intel_display(encoder); 2302 2303 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2304 DP_TP_STATUS_ACT_SENT); 2305 } 2306 2307 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2308 const struct intel_crtc_state *crtc_state) 2309 { 2310 struct intel_display *display = to_intel_display(encoder); 2311 2312 if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2313 DP_TP_STATUS_ACT_SENT, 1)) 2314 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2315 } 2316 2317 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2318 const struct intel_crtc_state *crtc_state, 2319 bool enable) 2320 { 2321 struct intel_display *display = to_intel_display(intel_dp); 2322 2323 if (!crtc_state->vrr.enable) 2324 return; 2325 2326 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2327 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2328 drm_dbg_kms(display->drm, 2329 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2330 str_enable_disable(enable)); 2331 } 2332 2333 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2334 const struct intel_crtc_state *crtc_state, 2335 bool enable) 2336 { 2337 struct intel_display *display = to_intel_display(intel_dp); 2338 2339 if (!crtc_state->fec_enable) 2340 return; 2341 2342 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2343 enable ? DP_FEC_READY : 0) <= 0) 2344 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2345 str_enabled_disabled(enable)); 2346 2347 if (enable && 2348 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2349 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2350 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2351 } 2352 2353 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2354 { 2355 struct intel_display *display = to_intel_display(aux->drm_dev); 2356 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2357 u8 status = 0; 2358 int ret, err; 2359 2360 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2361 err || (status & mask), 2362 10 * 1000, 200 * 1000, false); 2363 2364 /* Either can be non-zero, but not both */ 2365 ret = ret ?: err; 2366 if (ret) { 2367 drm_dbg_kms(display->drm, 2368 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2369 str_enabled_disabled(enabled), ret, status); 2370 return ret; 2371 } 2372 2373 return 0; 2374 } 2375 2376 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2377 const struct intel_crtc_state *crtc_state, 2378 bool enabled) 2379 { 2380 struct intel_display *display = to_intel_display(encoder); 2381 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2382 int ret; 2383 2384 if (!crtc_state->fec_enable) 2385 return 0; 2386 2387 if (enabled) 2388 ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2389 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2390 else 2391 ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state), 2392 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2393 2394 if (ret) { 2395 drm_err(display->drm, 2396 "Timeout waiting for FEC live state to get %s\n", 2397 str_enabled_disabled(enabled)); 2398 return ret; 2399 } 2400 /* 2401 * At least the Synoptics MST hub doesn't set the detected flag for 2402 * FEC decoding disabling so skip waiting for that. 2403 */ 2404 if (enabled) { 2405 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2406 if (ret) 2407 return ret; 2408 } 2409 2410 return 0; 2411 } 2412 2413 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2414 const struct intel_crtc_state *crtc_state) 2415 { 2416 struct intel_display *display = to_intel_display(encoder); 2417 int i; 2418 int ret; 2419 2420 if (!crtc_state->fec_enable) 2421 return; 2422 2423 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2424 0, DP_TP_CTL_FEC_ENABLE); 2425 2426 if (DISPLAY_VER(display) < 30) 2427 return; 2428 2429 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2430 if (!ret) 2431 return; 2432 2433 for (i = 0; i < 3; i++) { 2434 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2435 2436 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2437 DP_TP_CTL_FEC_ENABLE, 0); 2438 2439 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2440 if (ret) 2441 continue; 2442 2443 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2444 0, DP_TP_CTL_FEC_ENABLE); 2445 2446 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2447 if (!ret) 2448 return; 2449 } 2450 2451 drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); 2452 } 2453 2454 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2455 const struct intel_crtc_state *crtc_state) 2456 { 2457 struct intel_display *display = to_intel_display(encoder); 2458 2459 if (!crtc_state->fec_enable) 2460 return; 2461 2462 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2463 DP_TP_CTL_FEC_ENABLE, 0); 2464 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2465 } 2466 2467 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2468 const struct intel_crtc_state *crtc_state) 2469 { 2470 struct intel_display *display = to_intel_display(encoder); 2471 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2472 2473 if (intel_encoder_is_combo(encoder)) { 2474 enum phy phy = intel_encoder_to_phy(encoder); 2475 2476 intel_combo_phy_power_up_lanes(display, phy, false, 2477 crtc_state->lane_count, 2478 dig_port->lane_reversal); 2479 } 2480 } 2481 2482 /* 2483 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2484 * platforms. 2485 */ 2486 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2487 { 2488 if (DISPLAY_VER(display) > 20) 2489 return ~0; 2490 else if (display->platform.alderlake_p) 2491 return BIT(PIPE_A) | BIT(PIPE_B); 2492 else 2493 return BIT(PIPE_A); 2494 } 2495 2496 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2497 struct intel_crtc_state *pipe_config) 2498 { 2499 struct intel_display *display = to_intel_display(pipe_config); 2500 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2501 enum pipe pipe = crtc->pipe; 2502 u32 dss1; 2503 2504 if (!HAS_MSO(display)) 2505 return; 2506 2507 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2508 2509 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2510 if (!pipe_config->splitter.enable) 2511 return; 2512 2513 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2514 pipe_config->splitter.enable = false; 2515 return; 2516 } 2517 2518 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2519 default: 2520 drm_WARN(display->drm, true, 2521 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2522 fallthrough; 2523 case SPLITTER_CONFIGURATION_2_SEGMENT: 2524 pipe_config->splitter.link_count = 2; 2525 break; 2526 case SPLITTER_CONFIGURATION_4_SEGMENT: 2527 pipe_config->splitter.link_count = 4; 2528 break; 2529 } 2530 2531 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2532 } 2533 2534 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2535 { 2536 struct intel_display *display = to_intel_display(crtc_state); 2537 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2538 enum pipe pipe = crtc->pipe; 2539 u32 dss1 = 0; 2540 2541 if (!HAS_MSO(display)) 2542 return; 2543 2544 if (crtc_state->splitter.enable) { 2545 dss1 |= SPLITTER_ENABLE; 2546 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2547 if (crtc_state->splitter.link_count == 2) 2548 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2549 else 2550 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2551 } 2552 2553 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2554 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2555 OVERLAP_PIXELS_MASK, dss1); 2556 } 2557 2558 static void 2559 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2560 { 2561 struct intel_display *display = to_intel_display(encoder); 2562 enum port port = encoder->port; 2563 i915_reg_t reg; 2564 u32 set_bits, wait_bits; 2565 int ret; 2566 2567 if (DISPLAY_VER(display) < 14) 2568 return; 2569 2570 if (DISPLAY_VER(display) >= 20) { 2571 reg = DDI_BUF_CTL(port); 2572 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2573 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2574 } else { 2575 reg = XELPDP_PORT_BUF_CTL1(display, port); 2576 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2577 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2578 } 2579 2580 intel_de_rmw(display, reg, 0, set_bits); 2581 2582 ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100); 2583 if (ret) { 2584 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2585 port_name(port)); 2586 } 2587 } 2588 2589 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2590 const struct intel_crtc_state *crtc_state) 2591 { 2592 struct intel_display *display = to_intel_display(encoder); 2593 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2594 enum port port = encoder->port; 2595 u32 val = 0; 2596 2597 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2598 2599 if (intel_dp_is_uhbr(crtc_state)) 2600 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2601 else 2602 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2603 2604 if (dig_port->lane_reversal) 2605 val |= XELPDP_PORT_REVERSAL; 2606 2607 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2608 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2609 val); 2610 } 2611 2612 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2613 { 2614 struct intel_display *display = to_intel_display(encoder); 2615 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2616 u32 val; 2617 2618 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2619 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2620 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2621 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2622 } 2623 2624 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2625 struct intel_encoder *encoder, 2626 const struct intel_crtc_state *crtc_state, 2627 const struct drm_connector_state *conn_state) 2628 { 2629 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2630 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2631 bool transparent_mode; 2632 int ret; 2633 2634 intel_dp_set_link_params(intel_dp, 2635 crtc_state->port_clock, 2636 crtc_state->lane_count); 2637 2638 /* 2639 * We only configure what the register value will be here. Actual 2640 * enabling happens during link training farther down. 2641 */ 2642 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2643 2644 /* 2645 * 1. Enable Power Wells 2646 * 2647 * This was handled at the beginning of intel_atomic_commit_tail(), 2648 * before we called down into this function. 2649 */ 2650 2651 /* 2. PMdemand was already set */ 2652 2653 /* 3. Select Thunderbolt */ 2654 mtl_port_buf_ctl_io_selection(encoder); 2655 2656 /* 4. Enable Panel Power if PPS is required */ 2657 intel_pps_on(intel_dp); 2658 2659 /* 5. Enable the port PLL */ 2660 intel_ddi_enable_clock(encoder, crtc_state); 2661 2662 /* 2663 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2664 * Transcoder. 2665 */ 2666 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2667 2668 /* 2669 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2670 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2671 * Transport Select 2672 */ 2673 intel_ddi_config_transcoder_func(encoder, crtc_state); 2674 2675 /* 2676 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2677 */ 2678 intel_ddi_mso_configure(crtc_state); 2679 2680 if (!is_mst) 2681 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2682 2683 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2684 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2685 2686 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2687 if (!is_mst) 2688 intel_dp_sink_enable_decompression(state, 2689 to_intel_connector(conn_state->connector), 2690 crtc_state); 2691 2692 /* 2693 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2694 * in the FEC_CONFIGURATION register to 1 before initiating link 2695 * training 2696 */ 2697 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2698 2699 intel_dp_check_frl_training(intel_dp); 2700 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2701 2702 /* 2703 * 6. The rest of the below are substeps under the bspec's "Enable and 2704 * Train Display Port" step. Note that steps that are specific to 2705 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2706 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2707 * us when active_mst_links==0, so any steps designated for "single 2708 * stream or multi-stream master transcoder" can just be performed 2709 * unconditionally here. 2710 * 2711 * mtl_ddi_prepare_link_retrain() that is called by 2712 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2713 * 6.i and 6.j 2714 * 2715 * 6.k Follow DisplayPort specification training sequence (see notes for 2716 * failure handling) 2717 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2718 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2719 * (timeout after 800 us) 2720 */ 2721 intel_dp_start_link_train(state, intel_dp, crtc_state); 2722 2723 /* 6.n Set DP_TP_CTL link training to Normal */ 2724 if (!is_trans_port_sync_mode(crtc_state)) 2725 intel_dp_stop_link_train(intel_dp, crtc_state); 2726 2727 /* 6.o Configure and enable FEC if needed */ 2728 intel_ddi_enable_fec(encoder, crtc_state); 2729 2730 /* 7.a 128b/132b SST. */ 2731 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2732 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2733 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2734 if (ret < 0) 2735 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2736 } 2737 2738 if (!is_mst) 2739 intel_dsc_dp_pps_write(encoder, crtc_state); 2740 } 2741 2742 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2743 struct intel_encoder *encoder, 2744 const struct intel_crtc_state *crtc_state, 2745 const struct drm_connector_state *conn_state) 2746 { 2747 struct intel_display *display = to_intel_display(encoder); 2748 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2749 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2750 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2751 int ret; 2752 2753 intel_dp_set_link_params(intel_dp, 2754 crtc_state->port_clock, 2755 crtc_state->lane_count); 2756 2757 /* 2758 * We only configure what the register value will be here. Actual 2759 * enabling happens during link training farther down. 2760 */ 2761 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2762 2763 /* 2764 * 1. Enable Power Wells 2765 * 2766 * This was handled at the beginning of intel_atomic_commit_tail(), 2767 * before we called down into this function. 2768 */ 2769 2770 /* 2. Enable Panel Power if PPS is required */ 2771 intel_pps_on(intel_dp); 2772 2773 /* 2774 * 3. For non-TBT Type-C ports, set FIA lane count 2775 * (DFLEXDPSP.DPX4TXLATC) 2776 * 2777 * This was done before tgl_ddi_pre_enable_dp by 2778 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2779 */ 2780 2781 /* 2782 * 4. Enable the port PLL. 2783 * 2784 * The PLL enabling itself was already done before this function by 2785 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2786 * configure the PLL to port mapping here. 2787 */ 2788 intel_ddi_enable_clock(encoder, crtc_state); 2789 2790 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2791 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2792 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2793 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2794 dig_port->ddi_io_power_domain); 2795 } 2796 2797 /* 6. Program DP_MODE */ 2798 icl_program_mg_dp_mode(dig_port, crtc_state); 2799 2800 /* 2801 * 7. The rest of the below are substeps under the bspec's "Enable and 2802 * Train Display Port" step. Note that steps that are specific to 2803 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2804 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2805 * us when active_mst_links==0, so any steps designated for "single 2806 * stream or multi-stream master transcoder" can just be performed 2807 * unconditionally here. 2808 */ 2809 2810 /* 2811 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2812 * Transcoder. 2813 */ 2814 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2815 2816 /* 2817 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2818 * Transport Select 2819 */ 2820 intel_ddi_config_transcoder_func(encoder, crtc_state); 2821 2822 /* 2823 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2824 * selected 2825 * 2826 * This will be handled by the intel_dp_start_link_train() farther 2827 * down this function. 2828 */ 2829 2830 /* 7.e Configure voltage swing and related IO settings */ 2831 encoder->set_signal_levels(encoder, crtc_state); 2832 2833 /* 2834 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2835 * the used lanes of the DDI. 2836 */ 2837 intel_ddi_power_up_lanes(encoder, crtc_state); 2838 2839 /* 2840 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2841 */ 2842 intel_ddi_mso_configure(crtc_state); 2843 2844 if (!is_mst) 2845 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2846 2847 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2848 if (!is_mst) 2849 intel_dp_sink_enable_decompression(state, 2850 to_intel_connector(conn_state->connector), 2851 crtc_state); 2852 /* 2853 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2854 * in the FEC_CONFIGURATION register to 1 before initiating link 2855 * training 2856 */ 2857 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2858 2859 intel_dp_check_frl_training(intel_dp); 2860 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2861 2862 /* 2863 * 7.i Follow DisplayPort specification training sequence (see notes for 2864 * failure handling) 2865 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2866 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2867 * (timeout after 800 us) 2868 */ 2869 intel_dp_start_link_train(state, intel_dp, crtc_state); 2870 2871 /* 7.k Set DP_TP_CTL link training to Normal */ 2872 if (!is_trans_port_sync_mode(crtc_state)) 2873 intel_dp_stop_link_train(intel_dp, crtc_state); 2874 2875 /* 7.l Configure and enable FEC if needed */ 2876 intel_ddi_enable_fec(encoder, crtc_state); 2877 2878 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2879 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2880 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2881 if (ret < 0) 2882 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2883 } 2884 2885 if (!is_mst) 2886 intel_dsc_dp_pps_write(encoder, crtc_state); 2887 } 2888 2889 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2890 struct intel_encoder *encoder, 2891 const struct intel_crtc_state *crtc_state, 2892 const struct drm_connector_state *conn_state) 2893 { 2894 struct intel_display *display = to_intel_display(encoder); 2895 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2896 enum port port = encoder->port; 2897 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2898 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2899 2900 if (DISPLAY_VER(display) < 11) 2901 drm_WARN_ON(display->drm, 2902 is_mst && (port == PORT_A || port == PORT_E)); 2903 else 2904 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2905 2906 intel_dp_set_link_params(intel_dp, 2907 crtc_state->port_clock, 2908 crtc_state->lane_count); 2909 2910 /* 2911 * We only configure what the register value will be here. Actual 2912 * enabling happens during link training farther down. 2913 */ 2914 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2915 2916 intel_pps_on(intel_dp); 2917 2918 intel_ddi_enable_clock(encoder, crtc_state); 2919 2920 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2921 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2922 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2923 dig_port->ddi_io_power_domain); 2924 } 2925 2926 icl_program_mg_dp_mode(dig_port, crtc_state); 2927 2928 if (has_buf_trans_select(display)) 2929 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2930 2931 encoder->set_signal_levels(encoder, crtc_state); 2932 2933 intel_ddi_power_up_lanes(encoder, crtc_state); 2934 2935 if (!is_mst) 2936 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2937 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2938 if (!is_mst) 2939 intel_dp_sink_enable_decompression(state, 2940 to_intel_connector(conn_state->connector), 2941 crtc_state); 2942 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2943 intel_dp_start_link_train(state, intel_dp, crtc_state); 2944 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2945 !is_trans_port_sync_mode(crtc_state)) 2946 intel_dp_stop_link_train(intel_dp, crtc_state); 2947 2948 intel_ddi_enable_fec(encoder, crtc_state); 2949 2950 if (!is_mst) { 2951 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2952 intel_dsc_dp_pps_write(encoder, crtc_state); 2953 } 2954 } 2955 2956 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2957 struct intel_encoder *encoder, 2958 const struct intel_crtc_state *crtc_state, 2959 const struct drm_connector_state *conn_state) 2960 { 2961 struct intel_display *display = to_intel_display(encoder); 2962 2963 if (HAS_DP20(display)) 2964 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2965 crtc_state); 2966 2967 /* Panel replay has to be enabled in sink dpcd before link training. */ 2968 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2969 2970 if (DISPLAY_VER(display) >= 14) 2971 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2972 else if (DISPLAY_VER(display) >= 12) 2973 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2974 else 2975 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2976 2977 /* MST will call a setting of MSA after an allocating of Virtual Channel 2978 * from MST encoder pre_enable callback. 2979 */ 2980 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2981 intel_ddi_set_dp_msa(crtc_state, conn_state); 2982 } 2983 2984 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2985 struct intel_encoder *encoder, 2986 const struct intel_crtc_state *crtc_state, 2987 const struct drm_connector_state *conn_state) 2988 { 2989 struct intel_display *display = to_intel_display(encoder); 2990 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2991 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2992 2993 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2994 intel_ddi_enable_clock(encoder, crtc_state); 2995 2996 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2997 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2998 dig_port->ddi_io_power_domain); 2999 3000 icl_program_mg_dp_mode(dig_port, crtc_state); 3001 3002 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3003 3004 dig_port->set_infoframes(encoder, 3005 crtc_state->has_infoframe, 3006 crtc_state, conn_state); 3007 } 3008 3009 /* 3010 * Note: Also called from the ->pre_enable of the first active MST stream 3011 * encoder on its primary encoder. 3012 * 3013 * When called from DP MST code: 3014 * 3015 * - conn_state will be NULL 3016 * 3017 * - encoder will be the primary encoder (i.e. mst->primary) 3018 * 3019 * - the main connector associated with this port won't be active or linked to a 3020 * crtc 3021 * 3022 * - crtc_state will be the state of the first stream to be activated on this 3023 * port, and it may not be the same stream that will be deactivated last, but 3024 * each stream should have a state that is identical when it comes to the DP 3025 * link parameters. 3026 */ 3027 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3028 struct intel_encoder *encoder, 3029 const struct intel_crtc_state *crtc_state, 3030 const struct drm_connector_state *conn_state) 3031 { 3032 struct intel_display *display = to_intel_display(state); 3033 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3034 enum pipe pipe = crtc->pipe; 3035 3036 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3037 3038 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3039 3040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3041 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3042 conn_state); 3043 } else { 3044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3045 3046 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3047 conn_state); 3048 3049 /* FIXME precompute everything properly */ 3050 /* FIXME how do we turn infoframes off again? */ 3051 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3052 dig_port->set_infoframes(encoder, 3053 crtc_state->has_infoframe, 3054 crtc_state, conn_state); 3055 } 3056 } 3057 3058 static void 3059 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3060 { 3061 struct intel_display *display = to_intel_display(encoder); 3062 enum port port = encoder->port; 3063 i915_reg_t reg; 3064 u32 clr_bits, wait_bits; 3065 int ret; 3066 3067 if (DISPLAY_VER(display) < 14) 3068 return; 3069 3070 if (DISPLAY_VER(display) >= 20) { 3071 reg = DDI_BUF_CTL(port); 3072 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3073 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3074 } else { 3075 reg = XELPDP_PORT_BUF_CTL1(display, port); 3076 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3077 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3078 } 3079 3080 intel_de_rmw(display, reg, clr_bits, 0); 3081 3082 ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100); 3083 if (ret) 3084 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3085 port_name(port)); 3086 } 3087 3088 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3089 { 3090 struct intel_display *display = to_intel_display(encoder); 3091 enum port port = encoder->port; 3092 3093 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3094 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3095 3096 intel_wait_ddi_buf_active(encoder); 3097 } 3098 3099 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3100 const struct intel_crtc_state *crtc_state) 3101 { 3102 struct intel_display *display = to_intel_display(encoder); 3103 enum port port = encoder->port; 3104 3105 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3106 3107 if (DISPLAY_VER(display) >= 14) 3108 intel_wait_ddi_buf_idle(display, port); 3109 3110 mtl_ddi_disable_d2d(encoder); 3111 3112 if (intel_crtc_has_dp_encoder(crtc_state)) { 3113 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3114 DP_TP_CTL_ENABLE, 0); 3115 } 3116 3117 intel_ddi_disable_fec(encoder, crtc_state); 3118 3119 if (DISPLAY_VER(display) < 14) 3120 intel_wait_ddi_buf_idle(display, port); 3121 3122 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3123 } 3124 3125 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3126 struct intel_encoder *encoder, 3127 const struct intel_crtc_state *old_crtc_state, 3128 const struct drm_connector_state *old_conn_state) 3129 { 3130 struct intel_display *display = to_intel_display(encoder); 3131 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3132 struct intel_dp *intel_dp = &dig_port->dp; 3133 struct ref_tracker *wakeref; 3134 bool is_mst = intel_crtc_has_type(old_crtc_state, 3135 INTEL_OUTPUT_DP_MST); 3136 3137 if (!is_mst) 3138 intel_dp_set_infoframes(encoder, false, 3139 old_crtc_state, old_conn_state); 3140 3141 /* 3142 * Power down sink before disabling the port, otherwise we end 3143 * up getting interrupts from the sink on detecting link loss. 3144 */ 3145 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3146 3147 if (DISPLAY_VER(display) >= 12) { 3148 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3149 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3150 3151 intel_de_rmw(display, 3152 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3153 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3154 0); 3155 } 3156 } else { 3157 if (!is_mst) 3158 intel_ddi_disable_transcoder_clock(old_crtc_state); 3159 } 3160 3161 intel_ddi_buf_disable(encoder, old_crtc_state); 3162 3163 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3164 3165 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3166 3167 /* 3168 * From TGL spec: "If single stream or multi-stream master transcoder: 3169 * Configure Transcoder Clock select to direct no clock to the 3170 * transcoder" 3171 */ 3172 if (DISPLAY_VER(display) >= 12) 3173 intel_ddi_disable_transcoder_clock(old_crtc_state); 3174 3175 intel_pps_vdd_on(intel_dp); 3176 intel_pps_off(intel_dp); 3177 3178 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3179 3180 if (wakeref) 3181 intel_display_power_put(display, 3182 dig_port->ddi_io_power_domain, 3183 wakeref); 3184 3185 intel_ddi_disable_clock(encoder); 3186 3187 /* De-select Thunderbolt */ 3188 if (DISPLAY_VER(display) >= 14) 3189 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3190 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3191 } 3192 3193 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3194 struct intel_encoder *encoder, 3195 const struct intel_crtc_state *old_crtc_state, 3196 const struct drm_connector_state *old_conn_state) 3197 { 3198 struct intel_display *display = to_intel_display(encoder); 3199 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3200 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3201 struct ref_tracker *wakeref; 3202 3203 dig_port->set_infoframes(encoder, false, 3204 old_crtc_state, old_conn_state); 3205 3206 if (DISPLAY_VER(display) < 12) 3207 intel_ddi_disable_transcoder_clock(old_crtc_state); 3208 3209 intel_ddi_buf_disable(encoder, old_crtc_state); 3210 3211 if (DISPLAY_VER(display) >= 12) 3212 intel_ddi_disable_transcoder_clock(old_crtc_state); 3213 3214 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3215 if (wakeref) 3216 intel_display_power_put(display, 3217 dig_port->ddi_io_power_domain, 3218 wakeref); 3219 3220 intel_ddi_disable_clock(encoder); 3221 3222 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3223 } 3224 3225 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3226 struct intel_encoder *encoder, 3227 const struct intel_crtc_state *old_crtc_state, 3228 const struct drm_connector_state *old_conn_state) 3229 { 3230 struct intel_display *display = to_intel_display(encoder); 3231 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3232 struct intel_crtc *pipe_crtc; 3233 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3234 int i; 3235 3236 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3237 const struct intel_crtc_state *old_pipe_crtc_state = 3238 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3239 3240 intel_crtc_vblank_off(old_pipe_crtc_state); 3241 } 3242 3243 intel_disable_transcoder(old_crtc_state); 3244 3245 /* 128b/132b SST */ 3246 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3247 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3248 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3249 3250 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3251 3252 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3253 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3254 3255 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3256 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3257 } 3258 3259 intel_vrr_transcoder_disable(old_crtc_state); 3260 3261 intel_ddi_disable_transcoder_func(old_crtc_state); 3262 3263 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3264 const struct intel_crtc_state *old_pipe_crtc_state = 3265 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3266 3267 intel_dsc_disable(old_pipe_crtc_state); 3268 3269 if (DISPLAY_VER(display) >= 9) 3270 skl_scaler_disable(old_pipe_crtc_state); 3271 else 3272 ilk_pfit_disable(old_pipe_crtc_state); 3273 } 3274 } 3275 3276 /* 3277 * Note: Also called from the ->post_disable of the last active MST stream 3278 * encoder on its primary encoder. See also the comment for 3279 * intel_ddi_pre_enable(). 3280 */ 3281 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3282 struct intel_encoder *encoder, 3283 const struct intel_crtc_state *old_crtc_state, 3284 const struct drm_connector_state *old_conn_state) 3285 { 3286 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3287 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3288 old_conn_state); 3289 3290 /* 3291 * When called from DP MST code: 3292 * - old_conn_state will be NULL 3293 * - encoder will be the main encoder (ie. mst->primary) 3294 * - the main connector associated with this port 3295 * won't be active or linked to a crtc 3296 * - old_crtc_state will be the state of the last stream to 3297 * be deactivated on this port, and it may not be the same 3298 * stream that was activated last, but each stream 3299 * should have a state that is identical when it comes to 3300 * the DP link parameters 3301 */ 3302 3303 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3304 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3305 old_conn_state); 3306 else 3307 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3308 old_conn_state); 3309 } 3310 3311 /* 3312 * Note: Also called from the ->post_pll_disable of the last active MST stream 3313 * encoder on its primary encoder. See also the comment for 3314 * intel_ddi_pre_enable(). 3315 */ 3316 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3317 struct intel_encoder *encoder, 3318 const struct intel_crtc_state *old_crtc_state, 3319 const struct drm_connector_state *old_conn_state) 3320 { 3321 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3322 3323 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3324 3325 if (intel_encoder_is_tc(encoder)) 3326 intel_tc_port_put_link(dig_port); 3327 } 3328 3329 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3330 struct intel_encoder *encoder, 3331 const struct intel_crtc_state *crtc_state) 3332 { 3333 const struct drm_connector_state *conn_state; 3334 struct drm_connector *conn; 3335 int i; 3336 3337 if (!crtc_state->sync_mode_slaves_mask) 3338 return; 3339 3340 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3341 struct intel_encoder *slave_encoder = 3342 to_intel_encoder(conn_state->best_encoder); 3343 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3344 const struct intel_crtc_state *slave_crtc_state; 3345 3346 if (!slave_crtc) 3347 continue; 3348 3349 slave_crtc_state = 3350 intel_atomic_get_new_crtc_state(state, slave_crtc); 3351 3352 if (slave_crtc_state->master_transcoder != 3353 crtc_state->cpu_transcoder) 3354 continue; 3355 3356 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3357 slave_crtc_state); 3358 } 3359 3360 usleep_range(200, 400); 3361 3362 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3363 crtc_state); 3364 } 3365 3366 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3367 struct intel_encoder *encoder, 3368 const struct intel_crtc_state *crtc_state, 3369 const struct drm_connector_state *conn_state) 3370 { 3371 struct intel_display *display = to_intel_display(encoder); 3372 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3373 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3374 enum port port = encoder->port; 3375 3376 if (port == PORT_A && DISPLAY_VER(display) < 9) 3377 intel_dp_stop_link_train(intel_dp, crtc_state); 3378 3379 drm_connector_update_privacy_screen(conn_state); 3380 intel_edp_backlight_on(crtc_state, conn_state); 3381 3382 intel_panel_prepare(crtc_state, conn_state); 3383 3384 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3385 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3386 3387 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3388 } 3389 3390 static i915_reg_t 3391 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3392 { 3393 static const enum transcoder trans[] = { 3394 [PORT_A] = TRANSCODER_EDP, 3395 [PORT_B] = TRANSCODER_A, 3396 [PORT_C] = TRANSCODER_B, 3397 [PORT_D] = TRANSCODER_C, 3398 [PORT_E] = TRANSCODER_A, 3399 }; 3400 3401 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3402 3403 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3404 port = PORT_A; 3405 3406 return CHICKEN_TRANS(display, trans[port]); 3407 } 3408 3409 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3410 struct intel_encoder *encoder, 3411 const struct intel_crtc_state *crtc_state, 3412 const struct drm_connector_state *conn_state) 3413 { 3414 struct intel_display *display = to_intel_display(encoder); 3415 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3416 struct drm_connector *connector = conn_state->connector; 3417 enum port port = encoder->port; 3418 u32 buf_ctl = 0; 3419 3420 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3421 crtc_state->hdmi_high_tmds_clock_ratio, 3422 crtc_state->hdmi_scrambling)) 3423 drm_dbg_kms(display->drm, 3424 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3425 connector->base.id, connector->name); 3426 3427 if (has_buf_trans_select(display)) 3428 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3429 3430 /* e. Enable D2D Link for C10/C20 Phy */ 3431 mtl_ddi_enable_d2d(encoder); 3432 3433 encoder->set_signal_levels(encoder, crtc_state); 3434 3435 /* Display WA #1143: skl,kbl,cfl */ 3436 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3437 /* 3438 * For some reason these chicken bits have been 3439 * stuffed into a transcoder register, event though 3440 * the bits affect a specific DDI port rather than 3441 * a specific transcoder. 3442 */ 3443 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3444 u32 val; 3445 3446 val = intel_de_read(display, reg); 3447 3448 if (port == PORT_E) 3449 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3450 DDIE_TRAINING_OVERRIDE_VALUE; 3451 else 3452 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3453 DDI_TRAINING_OVERRIDE_VALUE; 3454 3455 intel_de_write(display, reg, val); 3456 intel_de_posting_read(display, reg); 3457 3458 udelay(1); 3459 3460 if (port == PORT_E) 3461 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3462 DDIE_TRAINING_OVERRIDE_VALUE); 3463 else 3464 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3465 DDI_TRAINING_OVERRIDE_VALUE); 3466 3467 intel_de_write(display, reg, val); 3468 } 3469 3470 intel_ddi_power_up_lanes(encoder, crtc_state); 3471 3472 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3473 * are ignored so nothing special needs to be done besides 3474 * enabling the port. 3475 * 3476 * On ADL_P the PHY link rate and lane count must be programmed but 3477 * these are both 0 for HDMI. 3478 * 3479 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3480 * is filled with lane count, already set in the crtc_state. 3481 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3482 */ 3483 if (dig_port->lane_reversal) 3484 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3485 if (dig_port->ddi_a_4_lanes) 3486 buf_ctl |= DDI_A_4_LANES; 3487 3488 if (DISPLAY_VER(display) >= 14) { 3489 u32 port_buf = 0; 3490 3491 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3492 3493 if (dig_port->lane_reversal) 3494 port_buf |= XELPDP_PORT_REVERSAL; 3495 3496 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3497 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3498 3499 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3500 3501 if (DISPLAY_VER(display) >= 20) 3502 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3503 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3504 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3505 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3506 } 3507 3508 intel_ddi_buf_enable(encoder, buf_ctl); 3509 } 3510 3511 static void intel_ddi_enable(struct intel_atomic_state *state, 3512 struct intel_encoder *encoder, 3513 const struct intel_crtc_state *crtc_state, 3514 const struct drm_connector_state *conn_state) 3515 { 3516 struct intel_display *display = to_intel_display(encoder); 3517 struct intel_crtc *pipe_crtc; 3518 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3519 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3520 int i; 3521 3522 /* 128b/132b SST */ 3523 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3524 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3525 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3526 3527 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3528 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3529 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3530 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3531 } 3532 3533 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3534 3535 intel_vrr_transcoder_enable(crtc_state); 3536 3537 /* 128b/132b SST */ 3538 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3539 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3540 3541 intel_ddi_clear_act_sent(encoder, crtc_state); 3542 3543 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3544 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3545 3546 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3547 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3548 } 3549 3550 intel_enable_transcoder(crtc_state); 3551 3552 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3553 3554 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3555 const struct intel_crtc_state *pipe_crtc_state = 3556 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3557 3558 intel_crtc_vblank_on(pipe_crtc_state); 3559 } 3560 3561 if (is_hdmi) 3562 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3563 else 3564 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3565 3566 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3567 3568 } 3569 3570 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3571 struct intel_encoder *encoder, 3572 const struct intel_crtc_state *old_crtc_state, 3573 const struct drm_connector_state *old_conn_state) 3574 { 3575 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3576 struct intel_connector *connector = 3577 to_intel_connector(old_conn_state->connector); 3578 3579 intel_dp->link.active = false; 3580 3581 intel_panel_unprepare(old_conn_state); 3582 intel_psr_disable(intel_dp, old_crtc_state); 3583 intel_alpm_disable(intel_dp); 3584 intel_edp_backlight_off(old_conn_state); 3585 /* Disable the decompression in DP Sink */ 3586 intel_dp_sink_disable_decompression(state, 3587 connector, old_crtc_state); 3588 /* Disable Ignore_MSA bit in DP Sink */ 3589 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3590 false); 3591 } 3592 3593 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3594 struct intel_encoder *encoder, 3595 const struct intel_crtc_state *old_crtc_state, 3596 const struct drm_connector_state *old_conn_state) 3597 { 3598 struct intel_display *display = to_intel_display(encoder); 3599 struct drm_connector *connector = old_conn_state->connector; 3600 3601 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3602 false, false)) 3603 drm_dbg_kms(display->drm, 3604 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3605 connector->base.id, connector->name); 3606 } 3607 3608 static void intel_ddi_disable(struct intel_atomic_state *state, 3609 struct intel_encoder *encoder, 3610 const struct intel_crtc_state *old_crtc_state, 3611 const struct drm_connector_state *old_conn_state) 3612 { 3613 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3614 3615 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3616 3617 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3618 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3619 old_conn_state); 3620 else 3621 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3622 old_conn_state); 3623 } 3624 3625 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3626 struct intel_encoder *encoder, 3627 const struct intel_crtc_state *crtc_state, 3628 const struct drm_connector_state *conn_state) 3629 { 3630 intel_ddi_set_dp_msa(crtc_state, conn_state); 3631 3632 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3633 3634 intel_backlight_update(state, encoder, crtc_state, conn_state); 3635 drm_connector_update_privacy_screen(conn_state); 3636 } 3637 3638 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3639 const struct intel_crtc_state *crtc_state, 3640 const struct drm_connector_state *conn_state) 3641 { 3642 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3643 } 3644 3645 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3646 struct intel_encoder *encoder, 3647 const struct intel_crtc_state *crtc_state, 3648 const struct drm_connector_state *conn_state) 3649 { 3650 3651 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3652 !intel_encoder_is_mst(encoder)) 3653 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3654 conn_state); 3655 3656 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3657 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3658 conn_state); 3659 3660 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3661 } 3662 3663 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3664 struct intel_encoder *encoder, 3665 struct intel_crtc *crtc) 3666 { 3667 struct intel_display *display = to_intel_display(encoder); 3668 const struct intel_crtc_state *crtc_state = 3669 intel_atomic_get_new_crtc_state(state, crtc); 3670 struct intel_crtc *pipe_crtc; 3671 3672 /* FIXME: Add NVL+ and DG2 pll_mgr */ 3673 if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) 3674 return; 3675 3676 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3677 intel_crtc_joined_pipe_mask(crtc_state)) 3678 intel_dpll_update_active(state, pipe_crtc, encoder); 3679 } 3680 3681 /* 3682 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3683 * encoder on its primary encoder. See also the comment for 3684 * intel_ddi_pre_enable(). 3685 */ 3686 static void 3687 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3688 struct intel_encoder *encoder, 3689 const struct intel_crtc_state *crtc_state, 3690 const struct drm_connector_state *conn_state) 3691 { 3692 struct intel_display *display = to_intel_display(encoder); 3693 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3694 bool is_tc_port = intel_encoder_is_tc(encoder); 3695 3696 if (is_tc_port) { 3697 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3698 3699 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3700 intel_ddi_update_active_dpll(state, encoder, crtc); 3701 } 3702 3703 main_link_aux_power_domain_get(dig_port, crtc_state); 3704 3705 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3706 /* 3707 * Program the lane count for static/dynamic connections on 3708 * Type-C ports. Skip this step for TBT. 3709 */ 3710 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3711 else if (display->platform.geminilake || display->platform.broxton) 3712 bxt_dpio_phy_set_lane_optim_mask(encoder, 3713 crtc_state->lane_lat_optim_mask); 3714 } 3715 3716 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3717 { 3718 struct intel_display *display = to_intel_display(encoder); 3719 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3720 int ln; 3721 3722 for (ln = 0; ln < 2; ln++) 3723 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3724 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3725 } 3726 3727 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3728 const struct intel_crtc_state *crtc_state) 3729 { 3730 struct intel_display *display = to_intel_display(crtc_state); 3731 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3732 struct intel_encoder *encoder = &dig_port->base; 3733 u32 dp_tp_ctl; 3734 3735 /* 3736 * TODO: To train with only a different voltage swing entry is not 3737 * necessary disable and enable port 3738 */ 3739 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3740 3741 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3742 3743 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3744 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3745 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3746 intel_dp_is_uhbr(crtc_state)) { 3747 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3748 } else { 3749 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3750 if (crtc_state->enhanced_framing) 3751 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3752 } 3753 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3754 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3755 3756 /* 6.f Enable D2D Link */ 3757 mtl_ddi_enable_d2d(encoder); 3758 3759 /* 6.g Configure voltage swing and related IO settings */ 3760 encoder->set_signal_levels(encoder, crtc_state); 3761 3762 /* 6.h Configure PORT_BUF_CTL1 */ 3763 mtl_port_buf_ctl_program(encoder, crtc_state); 3764 3765 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3766 if (DISPLAY_VER(display) >= 20) 3767 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3768 3769 intel_ddi_buf_enable(encoder, intel_dp->DP); 3770 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3771 3772 /* 3773 * 6.k If AUX-Less ALPM is going to be enabled: 3774 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3775 */ 3776 intel_alpm_port_configure(intel_dp, crtc_state); 3777 3778 /* 3779 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3780 * register 3781 */ 3782 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3783 } 3784 3785 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3786 const struct intel_crtc_state *crtc_state) 3787 { 3788 struct intel_display *display = to_intel_display(intel_dp); 3789 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3790 struct intel_encoder *encoder = &dig_port->base; 3791 u32 dp_tp_ctl; 3792 3793 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3794 3795 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3796 3797 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3798 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3799 intel_dp_is_uhbr(crtc_state)) { 3800 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3801 } else { 3802 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3803 if (crtc_state->enhanced_framing) 3804 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3805 } 3806 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3807 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3808 3809 if (display->platform.alderlake_p && 3810 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3811 adlp_tbt_to_dp_alt_switch_wa(encoder); 3812 3813 intel_ddi_buf_enable(encoder, intel_dp->DP); 3814 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3815 } 3816 3817 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3818 const struct intel_crtc_state *crtc_state, 3819 u8 dp_train_pat) 3820 { 3821 struct intel_display *display = to_intel_display(intel_dp); 3822 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3823 u32 temp; 3824 3825 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3826 3827 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3828 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3829 case DP_TRAINING_PATTERN_DISABLE: 3830 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3831 break; 3832 case DP_TRAINING_PATTERN_1: 3833 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3834 break; 3835 case DP_TRAINING_PATTERN_2: 3836 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3837 break; 3838 case DP_TRAINING_PATTERN_3: 3839 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3840 break; 3841 case DP_TRAINING_PATTERN_4: 3842 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3843 break; 3844 } 3845 3846 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3847 } 3848 3849 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3850 const struct intel_crtc_state *crtc_state) 3851 { 3852 struct intel_display *display = to_intel_display(intel_dp); 3853 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3854 enum port port = encoder->port; 3855 3856 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3857 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3858 3859 /* 3860 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3861 * reason we need to set idle transmission mode is to work around a HW 3862 * issue where we enable the pipe while not in idle link-training mode. 3863 * In this case there is requirement to wait for a minimum number of 3864 * idle patterns to be sent. 3865 */ 3866 if (port == PORT_A && DISPLAY_VER(display) < 12) 3867 return; 3868 3869 if (intel_de_wait_for_set_ms(display, 3870 dp_tp_status_reg(encoder, crtc_state), 3871 DP_TP_STATUS_IDLE_DONE, 2)) 3872 drm_err(display->drm, 3873 "Timed out waiting for DP idle patterns\n"); 3874 } 3875 3876 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3877 enum transcoder cpu_transcoder) 3878 { 3879 if (cpu_transcoder == TRANSCODER_EDP) 3880 return false; 3881 3882 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3883 return false; 3884 3885 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3886 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3887 } 3888 3889 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3890 { 3891 if (crtc_state->port_clock > 594000) 3892 return 2; 3893 else 3894 return 0; 3895 } 3896 3897 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3898 { 3899 if (crtc_state->port_clock > 594000) 3900 return 3; 3901 else 3902 return 0; 3903 } 3904 3905 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3906 { 3907 if (crtc_state->port_clock > 594000) 3908 return 1; 3909 else 3910 return 0; 3911 } 3912 3913 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3914 { 3915 struct intel_display *display = to_intel_display(crtc_state); 3916 3917 if (DISPLAY_VER(display) >= 14) 3918 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3919 else if (DISPLAY_VER(display) >= 12) 3920 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3921 else if (display->platform.jasperlake || display->platform.elkhartlake) 3922 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3923 else if (DISPLAY_VER(display) >= 11) 3924 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3925 } 3926 3927 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3928 enum transcoder cpu_transcoder) 3929 { 3930 u32 master_select; 3931 3932 if (DISPLAY_VER(display) >= 11) { 3933 u32 ctl2 = intel_de_read(display, 3934 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3935 3936 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3937 return INVALID_TRANSCODER; 3938 3939 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3940 } else { 3941 u32 ctl = intel_de_read(display, 3942 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3943 3944 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3945 return INVALID_TRANSCODER; 3946 3947 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3948 } 3949 3950 if (master_select == 0) 3951 return TRANSCODER_EDP; 3952 else 3953 return master_select - 1; 3954 } 3955 3956 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3957 { 3958 struct intel_display *display = to_intel_display(crtc_state); 3959 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3960 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3961 enum transcoder cpu_transcoder; 3962 3963 crtc_state->master_transcoder = 3964 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3965 3966 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3967 enum intel_display_power_domain power_domain; 3968 struct ref_tracker *trans_wakeref; 3969 3970 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3971 trans_wakeref = intel_display_power_get_if_enabled(display, 3972 power_domain); 3973 3974 if (!trans_wakeref) 3975 continue; 3976 3977 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3978 crtc_state->cpu_transcoder) 3979 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3980 3981 intel_display_power_put(display, power_domain, trans_wakeref); 3982 } 3983 3984 drm_WARN_ON(display->drm, 3985 crtc_state->master_transcoder != INVALID_TRANSCODER && 3986 crtc_state->sync_mode_slaves_mask); 3987 } 3988 3989 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3990 struct intel_crtc_state *crtc_state, 3991 u32 ddi_func_ctl) 3992 { 3993 struct intel_display *display = to_intel_display(encoder); 3994 3995 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3996 if (DISPLAY_VER(display) >= 14) 3997 crtc_state->lane_count = 3998 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3999 else 4000 crtc_state->lane_count = 4; 4001 } 4002 4003 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4004 struct intel_crtc_state *crtc_state, 4005 u32 ddi_func_ctl) 4006 { 4007 crtc_state->has_hdmi_sink = true; 4008 4009 crtc_state->infoframes.enable |= 4010 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4011 4012 if (crtc_state->infoframes.enable) 4013 crtc_state->has_infoframe = true; 4014 4015 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4016 crtc_state->hdmi_scrambling = true; 4017 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4018 crtc_state->hdmi_high_tmds_clock_ratio = true; 4019 4020 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4021 } 4022 4023 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4024 struct intel_crtc_state *crtc_state, 4025 u32 ddi_func_ctl) 4026 { 4027 struct intel_display *display = to_intel_display(encoder); 4028 4029 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4030 crtc_state->enhanced_framing = 4031 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4032 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4033 } 4034 4035 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4036 struct intel_crtc_state *crtc_state, 4037 u32 ddi_func_ctl) 4038 { 4039 struct intel_display *display = to_intel_display(encoder); 4040 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4041 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4042 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4043 4044 if (encoder->type == INTEL_OUTPUT_EDP) 4045 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4046 else 4047 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4048 crtc_state->lane_count = 4049 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4050 4051 if (DISPLAY_VER(display) >= 12 && 4052 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4053 crtc_state->mst_master_transcoder = 4054 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4055 4056 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4057 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4058 4059 crtc_state->enhanced_framing = 4060 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4061 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4062 4063 if (DISPLAY_VER(display) >= 11) 4064 crtc_state->fec_enable = 4065 intel_de_read(display, 4066 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4067 4068 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4069 crtc_state->infoframes.enable |= 4070 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4071 else 4072 crtc_state->infoframes.enable |= 4073 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4074 } 4075 4076 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4077 struct intel_crtc_state *crtc_state, 4078 u32 ddi_func_ctl) 4079 { 4080 struct intel_display *display = to_intel_display(encoder); 4081 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4082 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4083 4084 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4085 crtc_state->lane_count = 4086 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4087 4088 if (DISPLAY_VER(display) >= 12) 4089 crtc_state->mst_master_transcoder = 4090 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4091 4092 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4093 4094 if (DISPLAY_VER(display) >= 11) 4095 crtc_state->fec_enable = 4096 intel_de_read(display, 4097 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4098 4099 crtc_state->infoframes.enable |= 4100 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4101 } 4102 4103 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4104 struct intel_crtc_state *pipe_config) 4105 { 4106 struct intel_display *display = to_intel_display(encoder); 4107 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4108 u32 ddi_func_ctl, ddi_mode, flags = 0; 4109 4110 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4111 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4112 flags |= DRM_MODE_FLAG_PHSYNC; 4113 else 4114 flags |= DRM_MODE_FLAG_NHSYNC; 4115 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4116 flags |= DRM_MODE_FLAG_PVSYNC; 4117 else 4118 flags |= DRM_MODE_FLAG_NVSYNC; 4119 4120 pipe_config->hw.adjusted_mode.flags |= flags; 4121 4122 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4123 case TRANS_DDI_BPC_6: 4124 pipe_config->pipe_bpp = 18; 4125 break; 4126 case TRANS_DDI_BPC_8: 4127 pipe_config->pipe_bpp = 24; 4128 break; 4129 case TRANS_DDI_BPC_10: 4130 pipe_config->pipe_bpp = 30; 4131 break; 4132 case TRANS_DDI_BPC_12: 4133 pipe_config->pipe_bpp = 36; 4134 break; 4135 default: 4136 break; 4137 } 4138 4139 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4140 4141 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4142 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4143 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4144 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4145 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4146 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4147 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4148 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4150 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4152 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4153 4154 /* 4155 * If this is true, we know we're being called from mst stream 4156 * encoder's ->get_config(). 4157 */ 4158 if (intel_dp_mst_active_streams(intel_dp)) 4159 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4160 else 4161 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4162 } 4163 } 4164 4165 /* 4166 * Note: Also called from the ->get_config of the MST stream encoders on their 4167 * primary encoder, via the platform specific hooks here. See also the comment 4168 * for intel_ddi_pre_enable(). 4169 */ 4170 static void intel_ddi_get_config(struct intel_encoder *encoder, 4171 struct intel_crtc_state *pipe_config) 4172 { 4173 struct intel_display *display = to_intel_display(encoder); 4174 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4175 4176 /* XXX: DSI transcoder paranoia */ 4177 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4178 return; 4179 4180 intel_ddi_read_func_ctl(encoder, pipe_config); 4181 4182 intel_ddi_mso_get_config(encoder, pipe_config); 4183 4184 pipe_config->has_audio = 4185 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4186 4187 if (encoder->type == INTEL_OUTPUT_EDP) 4188 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4189 4190 ddi_dotclock_get(pipe_config); 4191 4192 if (display->platform.geminilake || display->platform.broxton) 4193 pipe_config->lane_lat_optim_mask = 4194 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4195 4196 intel_ddi_compute_min_voltage_level(pipe_config); 4197 4198 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4199 4200 intel_read_infoframe(encoder, pipe_config, 4201 HDMI_INFOFRAME_TYPE_AVI, 4202 &pipe_config->infoframes.avi); 4203 intel_read_infoframe(encoder, pipe_config, 4204 HDMI_INFOFRAME_TYPE_SPD, 4205 &pipe_config->infoframes.spd); 4206 intel_read_infoframe(encoder, pipe_config, 4207 HDMI_INFOFRAME_TYPE_VENDOR, 4208 &pipe_config->infoframes.hdmi); 4209 intel_read_infoframe(encoder, pipe_config, 4210 HDMI_INFOFRAME_TYPE_DRM, 4211 &pipe_config->infoframes.drm); 4212 4213 if (DISPLAY_VER(display) >= 8) 4214 bdw_get_trans_port_sync_config(pipe_config); 4215 4216 intel_psr_get_config(encoder, pipe_config); 4217 4218 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4219 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4220 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4221 4222 intel_audio_codec_get_config(encoder, pipe_config); 4223 } 4224 4225 void intel_ddi_get_clock(struct intel_encoder *encoder, 4226 struct intel_crtc_state *crtc_state, 4227 struct intel_dpll *pll) 4228 { 4229 struct intel_display *display = to_intel_display(encoder); 4230 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4231 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4232 bool pll_active; 4233 4234 if (drm_WARN_ON(display->drm, !pll)) 4235 return; 4236 4237 port_dpll->pll = pll; 4238 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4239 drm_WARN_ON(display->drm, !pll_active); 4240 4241 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4242 4243 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4244 &crtc_state->dpll_hw_state); 4245 } 4246 4247 static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, 4248 struct intel_crtc_state *crtc_state) 4249 { 4250 intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll); 4251 4252 if (crtc_state->dpll_hw_state.ltpll.tbt_mode) 4253 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4254 else 4255 crtc_state->port_clock = 4256 intel_lt_phy_calc_port_clock(encoder, crtc_state); 4257 intel_ddi_get_config(encoder, crtc_state); 4258 } 4259 4260 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4261 { 4262 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4263 } 4264 4265 static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, 4266 struct intel_crtc_state *crtc_state, 4267 enum icl_port_dpll_id port_dpll_id, 4268 enum intel_dpll_id pll_id) 4269 { 4270 struct intel_display *display = to_intel_display(encoder); 4271 struct icl_port_dpll *port_dpll; 4272 struct intel_dpll *pll; 4273 bool pll_active; 4274 4275 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4276 pll = intel_get_dpll_by_id(display, pll_id); 4277 4278 if (drm_WARN_ON(display->drm, !pll)) 4279 return; 4280 4281 port_dpll->pll = pll; 4282 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4283 drm_WARN_ON(display->drm, !pll_active); 4284 4285 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4286 4287 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4288 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4289 else 4290 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4291 &crtc_state->dpll_hw_state); 4292 4293 intel_ddi_get_config(encoder, crtc_state); 4294 } 4295 4296 /* 4297 * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4298 * C20 PHY PLL in the cases of: 4299 * - BMG port A/B 4300 * - PTL port B eDP over TypeC PHY 4301 */ 4302 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4303 struct intel_crtc_state *crtc_state) 4304 { 4305 struct intel_display *display = to_intel_display(encoder); 4306 4307 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4308 mtl_port_to_pll_id(display, encoder->port)); 4309 } 4310 4311 static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, 4312 struct intel_crtc_state *crtc_state) 4313 { 4314 struct intel_display *display = to_intel_display(encoder); 4315 4316 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4317 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4318 DPLL_ID_ICL_TBTPLL); 4319 else 4320 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, 4321 mtl_port_to_pll_id(display, encoder->port)); 4322 } 4323 4324 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4325 struct intel_crtc_state *crtc_state) 4326 { 4327 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4328 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4329 4330 intel_ddi_get_config(encoder, crtc_state); 4331 } 4332 4333 static void adls_ddi_get_config(struct intel_encoder *encoder, 4334 struct intel_crtc_state *crtc_state) 4335 { 4336 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4337 intel_ddi_get_config(encoder, crtc_state); 4338 } 4339 4340 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4341 struct intel_crtc_state *crtc_state) 4342 { 4343 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4344 intel_ddi_get_config(encoder, crtc_state); 4345 } 4346 4347 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4348 struct intel_crtc_state *crtc_state) 4349 { 4350 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4351 intel_ddi_get_config(encoder, crtc_state); 4352 } 4353 4354 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4355 struct intel_crtc_state *crtc_state) 4356 { 4357 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4358 intel_ddi_get_config(encoder, crtc_state); 4359 } 4360 4361 static enum icl_port_dpll_id 4362 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4363 const struct intel_crtc_state *crtc_state) 4364 { 4365 struct intel_display *display = to_intel_display(encoder); 4366 const struct intel_dpll *pll = crtc_state->intel_dpll; 4367 4368 if (drm_WARN_ON(display->drm, !pll)) 4369 return ICL_PORT_DPLL_DEFAULT; 4370 4371 if (icl_ddi_tc_pll_is_tbt(pll)) 4372 return ICL_PORT_DPLL_DEFAULT; 4373 else 4374 return ICL_PORT_DPLL_MG_PHY; 4375 } 4376 4377 enum icl_port_dpll_id 4378 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4379 const struct intel_crtc_state *crtc_state) 4380 { 4381 if (!encoder->port_pll_type) 4382 return ICL_PORT_DPLL_DEFAULT; 4383 4384 return encoder->port_pll_type(encoder, crtc_state); 4385 } 4386 4387 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4388 struct intel_crtc_state *crtc_state, 4389 struct intel_dpll *pll) 4390 { 4391 struct intel_display *display = to_intel_display(encoder); 4392 enum icl_port_dpll_id port_dpll_id; 4393 struct icl_port_dpll *port_dpll; 4394 bool pll_active; 4395 4396 if (drm_WARN_ON(display->drm, !pll)) 4397 return; 4398 4399 if (icl_ddi_tc_pll_is_tbt(pll)) 4400 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4401 else 4402 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4403 4404 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4405 4406 port_dpll->pll = pll; 4407 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4408 drm_WARN_ON(display->drm, !pll_active); 4409 4410 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4411 4412 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4413 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4414 else 4415 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4416 &crtc_state->dpll_hw_state); 4417 } 4418 4419 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4420 struct intel_crtc_state *crtc_state) 4421 { 4422 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4423 intel_ddi_get_config(encoder, crtc_state); 4424 } 4425 4426 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4427 struct intel_crtc_state *crtc_state) 4428 { 4429 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4430 intel_ddi_get_config(encoder, crtc_state); 4431 } 4432 4433 static void skl_ddi_get_config(struct intel_encoder *encoder, 4434 struct intel_crtc_state *crtc_state) 4435 { 4436 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4437 intel_ddi_get_config(encoder, crtc_state); 4438 } 4439 4440 void hsw_ddi_get_config(struct intel_encoder *encoder, 4441 struct intel_crtc_state *crtc_state) 4442 { 4443 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4444 intel_ddi_get_config(encoder, crtc_state); 4445 } 4446 4447 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4448 const struct intel_crtc_state *crtc_state) 4449 { 4450 if (intel_encoder_is_tc(encoder)) 4451 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4452 crtc_state); 4453 4454 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4455 (!crtc_state && intel_encoder_is_dp(encoder))) 4456 intel_dp_sync_state(encoder, crtc_state); 4457 } 4458 4459 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4460 struct intel_crtc_state *crtc_state) 4461 { 4462 struct intel_display *display = to_intel_display(encoder); 4463 bool fastset = true; 4464 4465 if (intel_encoder_is_tc(encoder)) { 4466 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4467 encoder->base.base.id, encoder->base.name); 4468 crtc_state->uapi.mode_changed = true; 4469 fastset = false; 4470 } 4471 4472 if (intel_crtc_has_dp_encoder(crtc_state) && 4473 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4474 fastset = false; 4475 4476 return fastset; 4477 } 4478 4479 static enum intel_output_type 4480 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4481 struct intel_crtc_state *crtc_state, 4482 struct drm_connector_state *conn_state) 4483 { 4484 switch (conn_state->connector->connector_type) { 4485 case DRM_MODE_CONNECTOR_HDMIA: 4486 return INTEL_OUTPUT_HDMI; 4487 case DRM_MODE_CONNECTOR_eDP: 4488 return INTEL_OUTPUT_EDP; 4489 case DRM_MODE_CONNECTOR_DisplayPort: 4490 return INTEL_OUTPUT_DP; 4491 default: 4492 MISSING_CASE(conn_state->connector->connector_type); 4493 return INTEL_OUTPUT_UNUSED; 4494 } 4495 } 4496 4497 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4498 struct intel_crtc_state *pipe_config, 4499 struct drm_connector_state *conn_state) 4500 { 4501 struct intel_display *display = to_intel_display(encoder); 4502 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4503 enum port port = encoder->port; 4504 int ret; 4505 4506 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4507 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4508 4509 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4510 pipe_config->has_hdmi_sink = 4511 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4512 4513 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4514 } else { 4515 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4516 } 4517 4518 if (ret) 4519 return ret; 4520 4521 if (display->platform.haswell && crtc->pipe == PIPE_A && 4522 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4523 pipe_config->pch_pfit.force_thru = 4524 pipe_config->pch_pfit.enabled || 4525 pipe_config->crc_enabled; 4526 4527 if (display->platform.geminilake || display->platform.broxton) 4528 pipe_config->lane_lat_optim_mask = 4529 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4530 4531 intel_ddi_compute_min_voltage_level(pipe_config); 4532 4533 return 0; 4534 } 4535 4536 static bool mode_equal(const struct drm_display_mode *mode1, 4537 const struct drm_display_mode *mode2) 4538 { 4539 return drm_mode_match(mode1, mode2, 4540 DRM_MODE_MATCH_TIMINGS | 4541 DRM_MODE_MATCH_FLAGS | 4542 DRM_MODE_MATCH_3D_FLAGS) && 4543 mode1->clock == mode2->clock; /* we want an exact match */ 4544 } 4545 4546 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4547 const struct intel_link_m_n *m_n_2) 4548 { 4549 return m_n_1->tu == m_n_2->tu && 4550 m_n_1->data_m == m_n_2->data_m && 4551 m_n_1->data_n == m_n_2->data_n && 4552 m_n_1->link_m == m_n_2->link_m && 4553 m_n_1->link_n == m_n_2->link_n; 4554 } 4555 4556 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4557 const struct intel_crtc_state *crtc_state2) 4558 { 4559 /* 4560 * FIXME the modeset sequence is currently wrong and 4561 * can't deal with joiner + port sync at the same time. 4562 */ 4563 return crtc_state1->hw.active && crtc_state2->hw.active && 4564 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4565 crtc_state1->output_types == crtc_state2->output_types && 4566 crtc_state1->output_format == crtc_state2->output_format && 4567 crtc_state1->lane_count == crtc_state2->lane_count && 4568 crtc_state1->port_clock == crtc_state2->port_clock && 4569 mode_equal(&crtc_state1->hw.adjusted_mode, 4570 &crtc_state2->hw.adjusted_mode) && 4571 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4572 } 4573 4574 static u8 4575 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4576 int tile_group_id) 4577 { 4578 struct intel_display *display = to_intel_display(ref_crtc_state); 4579 struct drm_connector *connector; 4580 const struct drm_connector_state *conn_state; 4581 struct intel_atomic_state *state = 4582 to_intel_atomic_state(ref_crtc_state->uapi.state); 4583 u8 transcoders = 0; 4584 int i; 4585 4586 /* 4587 * We don't enable port sync on BDW due to missing w/as and 4588 * due to not having adjusted the modeset sequence appropriately. 4589 */ 4590 if (DISPLAY_VER(display) < 9) 4591 return 0; 4592 4593 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4594 return 0; 4595 4596 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4597 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4598 const struct intel_crtc_state *crtc_state; 4599 4600 if (!crtc) 4601 continue; 4602 4603 if (!connector->has_tile || 4604 connector->tile_group->id != 4605 tile_group_id) 4606 continue; 4607 crtc_state = intel_atomic_get_new_crtc_state(state, 4608 crtc); 4609 if (!crtcs_port_sync_compatible(ref_crtc_state, 4610 crtc_state)) 4611 continue; 4612 transcoders |= BIT(crtc_state->cpu_transcoder); 4613 } 4614 4615 return transcoders; 4616 } 4617 4618 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4619 struct intel_crtc_state *crtc_state, 4620 struct drm_connector_state *conn_state) 4621 { 4622 struct intel_display *display = to_intel_display(encoder); 4623 struct drm_connector *connector = conn_state->connector; 4624 u8 port_sync_transcoders = 0; 4625 int ret = 0; 4626 4627 if (intel_crtc_has_dp_encoder(crtc_state)) 4628 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); 4629 4630 if (ret) 4631 return ret; 4632 4633 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4634 encoder->base.base.id, encoder->base.name, 4635 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4636 4637 if (connector->has_tile) 4638 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4639 connector->tile_group->id); 4640 4641 /* 4642 * EDP Transcoders cannot be ensalved 4643 * make them a master always when present 4644 */ 4645 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4646 crtc_state->master_transcoder = TRANSCODER_EDP; 4647 else 4648 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4649 4650 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4651 crtc_state->master_transcoder = INVALID_TRANSCODER; 4652 crtc_state->sync_mode_slaves_mask = 4653 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4654 } 4655 4656 return 0; 4657 } 4658 4659 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4660 { 4661 struct intel_display *display = to_intel_display(encoder->dev); 4662 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4663 4664 intel_dp_encoder_flush_work(encoder); 4665 if (intel_encoder_is_tc(&dig_port->base)) 4666 intel_tc_port_cleanup(dig_port); 4667 intel_display_power_flush_work(display); 4668 4669 drm_encoder_cleanup(encoder); 4670 kfree(dig_port->hdcp.port_data.streams); 4671 kfree(dig_port); 4672 } 4673 4674 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4675 { 4676 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4677 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4678 4679 intel_dp->reset_link_params = true; 4680 intel_dp_invalidate_source_oui(intel_dp); 4681 4682 intel_pps_encoder_reset(intel_dp); 4683 4684 if (intel_encoder_is_tc(&dig_port->base)) 4685 intel_tc_port_init_mode(dig_port); 4686 } 4687 4688 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4689 { 4690 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4691 4692 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4693 4694 return 0; 4695 } 4696 4697 static const struct drm_encoder_funcs intel_ddi_funcs = { 4698 .reset = intel_ddi_encoder_reset, 4699 .destroy = intel_ddi_encoder_destroy, 4700 .late_register = intel_ddi_encoder_late_register, 4701 }; 4702 4703 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4704 { 4705 struct intel_display *display = to_intel_display(dig_port); 4706 struct intel_connector *connector; 4707 enum port port = dig_port->base.port; 4708 4709 connector = intel_connector_alloc(); 4710 if (!connector) 4711 return -ENOMEM; 4712 4713 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4714 if (DISPLAY_VER(display) >= 14) 4715 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4716 else 4717 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4718 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4719 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4720 4721 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4722 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4723 4724 if (!intel_dp_init_connector(dig_port, connector)) { 4725 kfree(connector); 4726 return -EINVAL; 4727 } 4728 4729 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4730 struct drm_privacy_screen *privacy_screen; 4731 4732 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4733 if (!IS_ERR(privacy_screen)) { 4734 drm_connector_attach_privacy_screen_provider(&connector->base, 4735 privacy_screen); 4736 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4737 drm_warn(display->drm, "Error getting privacy-screen\n"); 4738 } 4739 } 4740 4741 return 0; 4742 } 4743 4744 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4745 struct drm_modeset_acquire_ctx *ctx) 4746 { 4747 struct intel_display *display = to_intel_display(encoder); 4748 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4749 struct intel_connector *connector = hdmi->attached_connector; 4750 struct i2c_adapter *ddc = connector->base.ddc; 4751 struct drm_connector_state *conn_state; 4752 struct intel_crtc_state *crtc_state; 4753 struct intel_crtc *crtc; 4754 u8 config; 4755 int ret; 4756 4757 if (connector->base.status != connector_status_connected) 4758 return 0; 4759 4760 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4761 ctx); 4762 if (ret) 4763 return ret; 4764 4765 conn_state = connector->base.state; 4766 4767 crtc = to_intel_crtc(conn_state->crtc); 4768 if (!crtc) 4769 return 0; 4770 4771 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4772 if (ret) 4773 return ret; 4774 4775 crtc_state = to_intel_crtc_state(crtc->base.state); 4776 4777 drm_WARN_ON(display->drm, 4778 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4779 4780 if (!crtc_state->hw.active) 4781 return 0; 4782 4783 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4784 !crtc_state->hdmi_scrambling) 4785 return 0; 4786 4787 if (conn_state->commit && 4788 !try_wait_for_completion(&conn_state->commit->hw_done)) 4789 return 0; 4790 4791 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4792 if (ret < 0) { 4793 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4794 connector->base.base.id, connector->base.name, ret); 4795 return 0; 4796 } 4797 4798 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4799 crtc_state->hdmi_high_tmds_clock_ratio && 4800 !!(config & SCDC_SCRAMBLING_ENABLE) == 4801 crtc_state->hdmi_scrambling) 4802 return 0; 4803 4804 /* 4805 * HDMI 2.0 says that one should not send scrambled data 4806 * prior to configuring the sink scrambling, and that 4807 * TMDS clock/data transmission should be suspended when 4808 * changing the TMDS clock rate in the sink. So let's 4809 * just do a full modeset here, even though some sinks 4810 * would be perfectly happy if were to just reconfigure 4811 * the SCDC settings on the fly. 4812 */ 4813 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4814 } 4815 4816 static void intel_ddi_link_check(struct intel_encoder *encoder) 4817 { 4818 struct intel_display *display = to_intel_display(encoder); 4819 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4820 4821 /* TODO: Move checking the HDMI link state here as well. */ 4822 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4823 4824 intel_dp_link_check(encoder); 4825 } 4826 4827 static enum intel_hotplug_state 4828 intel_ddi_hotplug(struct intel_encoder *encoder, 4829 struct intel_connector *connector) 4830 { 4831 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4832 struct intel_dp *intel_dp = &dig_port->dp; 4833 bool is_tc = intel_encoder_is_tc(encoder); 4834 struct drm_modeset_acquire_ctx ctx; 4835 enum intel_hotplug_state state; 4836 int ret; 4837 4838 if (intel_dp_test_phy(intel_dp)) 4839 return INTEL_HOTPLUG_UNCHANGED; 4840 4841 state = intel_encoder_hotplug(encoder, connector); 4842 4843 if (!intel_tc_port_link_reset(dig_port)) { 4844 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4845 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4846 ret = intel_hdmi_reset_link(encoder, &ctx); 4847 drm_WARN_ON(encoder->base.dev, ret); 4848 } else { 4849 intel_dp_check_link_state(intel_dp); 4850 } 4851 } 4852 4853 /* 4854 * Unpowered type-c dongles can take some time to boot and be 4855 * responsible, so here giving some time to those dongles to power up 4856 * and then retrying the probe. 4857 * 4858 * On many platforms the HDMI live state signal is known to be 4859 * unreliable, so we can't use it to detect if a sink is connected or 4860 * not. Instead we detect if it's connected based on whether we can 4861 * read the EDID or not. That in turn has a problem during disconnect, 4862 * since the HPD interrupt may be raised before the DDC lines get 4863 * disconnected (due to how the required length of DDC vs. HPD 4864 * connector pins are specified) and so we'll still be able to get a 4865 * valid EDID. To solve this schedule another detection cycle if this 4866 * time around we didn't detect any change in the sink's connection 4867 * status. 4868 * 4869 * Type-c connectors which get their HPD signal deasserted then 4870 * reasserted, without unplugging/replugging the sink from the 4871 * connector, introduce a delay until the AUX channel communication 4872 * becomes functional. Retry the detection for 5 seconds on type-c 4873 * connectors to account for this delay. 4874 */ 4875 if (state == INTEL_HOTPLUG_UNCHANGED && 4876 connector->hotplug_retries < (is_tc ? 5 : 1) && 4877 !dig_port->dp.is_mst) 4878 state = INTEL_HOTPLUG_RETRY; 4879 4880 return state; 4881 } 4882 4883 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4884 { 4885 struct intel_display *display = to_intel_display(encoder); 4886 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4887 4888 return intel_de_read(display, SDEISR) & bit; 4889 } 4890 4891 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4892 { 4893 struct intel_display *display = to_intel_display(encoder); 4894 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4895 4896 return intel_de_read(display, DEISR) & bit; 4897 } 4898 4899 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4900 { 4901 struct intel_display *display = to_intel_display(encoder); 4902 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4903 4904 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4905 } 4906 4907 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4908 { 4909 struct intel_connector *connector; 4910 enum port port = dig_port->base.port; 4911 4912 connector = intel_connector_alloc(); 4913 if (!connector) 4914 return -ENOMEM; 4915 4916 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4917 4918 if (!intel_hdmi_init_connector(dig_port, connector)) { 4919 /* 4920 * HDMI connector init failures may just mean conflicting DDC 4921 * pins or not having enough lanes. Handle them gracefully, but 4922 * don't fail the entire DDI init. 4923 */ 4924 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4925 kfree(connector); 4926 } 4927 4928 return 0; 4929 } 4930 4931 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4932 { 4933 struct intel_display *display = to_intel_display(dig_port); 4934 4935 if (dig_port->base.port != PORT_A) 4936 return false; 4937 4938 if (dig_port->ddi_a_4_lanes) 4939 return false; 4940 4941 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4942 * supported configuration 4943 */ 4944 if (display->platform.geminilake || display->platform.broxton) 4945 return true; 4946 4947 return false; 4948 } 4949 4950 static int 4951 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4952 { 4953 struct intel_display *display = to_intel_display(dig_port); 4954 enum port port = dig_port->base.port; 4955 int max_lanes = 4; 4956 4957 if (DISPLAY_VER(display) >= 11) 4958 return max_lanes; 4959 4960 if (port == PORT_A || port == PORT_E) { 4961 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4962 max_lanes = port == PORT_A ? 4 : 0; 4963 else 4964 /* Both A and E share 2 lanes */ 4965 max_lanes = 2; 4966 } 4967 4968 /* 4969 * Some BIOS might fail to set this bit on port A if eDP 4970 * wasn't lit up at boot. Force this bit set when needed 4971 * so we use the proper lane count for our calculations. 4972 */ 4973 if (intel_ddi_a_force_4_lanes(dig_port)) { 4974 drm_dbg_kms(display->drm, 4975 "Forcing DDI_A_4_LANES for port A\n"); 4976 dig_port->ddi_a_4_lanes = true; 4977 max_lanes = 4; 4978 } 4979 4980 return max_lanes; 4981 } 4982 4983 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4984 { 4985 if (port >= PORT_D_XELPD) 4986 return HPD_PORT_D + port - PORT_D_XELPD; 4987 else if (port >= PORT_TC1) 4988 return HPD_PORT_TC1 + port - PORT_TC1; 4989 else 4990 return HPD_PORT_A + port - PORT_A; 4991 } 4992 4993 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4994 { 4995 if (port >= PORT_TC1) 4996 return HPD_PORT_C + port - PORT_TC1; 4997 else 4998 return HPD_PORT_A + port - PORT_A; 4999 } 5000 5001 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 5002 { 5003 if (port >= PORT_TC1) 5004 return HPD_PORT_TC1 + port - PORT_TC1; 5005 else 5006 return HPD_PORT_A + port - PORT_A; 5007 } 5008 5009 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 5010 { 5011 if (HAS_PCH_TGP(display)) 5012 return tgl_hpd_pin(display, port); 5013 5014 if (port >= PORT_TC1) 5015 return HPD_PORT_C + port - PORT_TC1; 5016 else 5017 return HPD_PORT_A + port - PORT_A; 5018 } 5019 5020 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 5021 { 5022 if (port >= PORT_C) 5023 return HPD_PORT_TC1 + port - PORT_C; 5024 else 5025 return HPD_PORT_A + port - PORT_A; 5026 } 5027 5028 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 5029 { 5030 if (port == PORT_D) 5031 return HPD_PORT_A; 5032 5033 if (HAS_PCH_TGP(display)) 5034 return icl_hpd_pin(display, port); 5035 5036 return HPD_PORT_A + port - PORT_A; 5037 } 5038 5039 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 5040 { 5041 if (HAS_PCH_TGP(display)) 5042 return icl_hpd_pin(display, port); 5043 5044 return HPD_PORT_A + port - PORT_A; 5045 } 5046 5047 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 5048 { 5049 if (DISPLAY_VER(display) >= 12) 5050 return port >= PORT_TC1; 5051 else if (DISPLAY_VER(display) >= 11) 5052 return port >= PORT_C; 5053 else 5054 return false; 5055 } 5056 5057 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5058 { 5059 intel_dp_encoder_suspend(encoder); 5060 } 5061 5062 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5063 { 5064 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5065 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5066 5067 /* 5068 * TODO: Move this to intel_dp_encoder_suspend(), 5069 * once modeset locking around that is removed. 5070 */ 5071 intel_encoder_link_check_flush_work(encoder); 5072 intel_tc_port_suspend(dig_port); 5073 } 5074 5075 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5076 { 5077 if (intel_encoder_is_dp(encoder)) 5078 intel_dp_encoder_shutdown(encoder); 5079 if (intel_encoder_is_hdmi(encoder)) 5080 intel_hdmi_encoder_shutdown(encoder); 5081 } 5082 5083 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5084 { 5085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5086 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5087 5088 intel_tc_port_cleanup(dig_port); 5089 } 5090 5091 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5092 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5093 5094 static bool port_strap_detected(struct intel_display *display, enum port port) 5095 { 5096 /* straps not used on skl+ */ 5097 if (DISPLAY_VER(display) >= 9) 5098 return true; 5099 5100 switch (port) { 5101 case PORT_A: 5102 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5103 case PORT_B: 5104 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5105 case PORT_C: 5106 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5107 case PORT_D: 5108 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5109 case PORT_E: 5110 return true; /* no strap for DDI-E */ 5111 default: 5112 MISSING_CASE(port); 5113 return false; 5114 } 5115 } 5116 5117 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5118 { 5119 return init_dp || intel_encoder_is_tc(encoder); 5120 } 5121 5122 static bool assert_has_icl_dsi(struct intel_display *display) 5123 { 5124 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5125 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5126 "Platform does not support DSI\n"); 5127 } 5128 5129 static bool port_in_use(struct intel_display *display, enum port port) 5130 { 5131 struct intel_encoder *encoder; 5132 5133 for_each_intel_encoder(display->drm, encoder) { 5134 /* FIXME what about second port for dual link DSI? */ 5135 if (encoder->port == port) 5136 return true; 5137 } 5138 5139 return false; 5140 } 5141 5142 static const char *intel_ddi_encoder_name(struct intel_display *display, 5143 enum port port, enum phy phy, 5144 struct seq_buf *s) 5145 { 5146 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5147 seq_buf_printf(s, "DDI %c/PHY %c", 5148 port_name(port - PORT_D_XELPD + PORT_D), 5149 phy_name(phy)); 5150 } else if (DISPLAY_VER(display) >= 12) { 5151 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5152 5153 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5154 port >= PORT_TC1 ? "TC" : "", 5155 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5156 tc_port != TC_PORT_NONE ? "TC" : "", 5157 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5158 } else if (DISPLAY_VER(display) >= 11) { 5159 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5160 5161 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5162 port_name(port), 5163 port >= PORT_C ? " (TC)" : "", 5164 tc_port != TC_PORT_NONE ? "TC" : "", 5165 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5166 } else { 5167 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5168 } 5169 5170 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5171 5172 return seq_buf_str(s); 5173 } 5174 5175 void intel_ddi_init(struct intel_display *display, 5176 const struct intel_bios_encoder_data *devdata) 5177 { 5178 struct intel_digital_port *dig_port; 5179 struct intel_encoder *encoder; 5180 DECLARE_SEQ_BUF(encoder_name, 20); 5181 bool init_hdmi, init_dp; 5182 enum port port; 5183 enum phy phy; 5184 u32 ddi_buf_ctl; 5185 5186 port = intel_bios_encoder_port(devdata); 5187 if (port == PORT_NONE) 5188 return; 5189 5190 if (!port_strap_detected(display, port)) { 5191 drm_dbg_kms(display->drm, 5192 "Port %c strap not detected\n", port_name(port)); 5193 return; 5194 } 5195 5196 if (!assert_port_valid(display, port)) 5197 return; 5198 5199 if (port_in_use(display, port)) { 5200 drm_dbg_kms(display->drm, 5201 "Port %c already claimed\n", port_name(port)); 5202 return; 5203 } 5204 5205 if (intel_bios_encoder_supports_dsi(devdata)) { 5206 /* BXT/GLK handled elsewhere, for now at least */ 5207 if (!assert_has_icl_dsi(display)) 5208 return; 5209 5210 icl_dsi_init(display, devdata); 5211 return; 5212 } 5213 5214 phy = intel_port_to_phy(display, port); 5215 5216 /* 5217 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5218 * have taken over some of the PHYs and made them unavailable to the 5219 * driver. In that case we should skip initializing the corresponding 5220 * outputs. 5221 */ 5222 if (intel_hti_uses_phy(display, phy)) { 5223 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5224 port_name(port), phy_name(phy)); 5225 return; 5226 } 5227 5228 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5229 intel_bios_encoder_supports_hdmi(devdata); 5230 init_dp = intel_bios_encoder_supports_dp(devdata); 5231 5232 if (intel_bios_encoder_is_lspcon(devdata)) { 5233 /* 5234 * Lspcon device needs to be driven with DP connector 5235 * with special detection sequence. So make sure DP 5236 * is initialized before lspcon. 5237 */ 5238 init_dp = true; 5239 init_hdmi = false; 5240 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5241 port_name(port)); 5242 } 5243 5244 if (!init_dp && !init_hdmi) { 5245 drm_dbg_kms(display->drm, 5246 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5247 port_name(port)); 5248 return; 5249 } 5250 5251 if (intel_phy_is_snps(display, phy) && 5252 display->snps.phy_failed_calibration & BIT(phy)) { 5253 drm_dbg_kms(display->drm, 5254 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5255 phy_name(phy)); 5256 } 5257 5258 dig_port = intel_dig_port_alloc(); 5259 if (!dig_port) 5260 return; 5261 5262 encoder = &dig_port->base; 5263 encoder->devdata = devdata; 5264 5265 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5266 DRM_MODE_ENCODER_TMDS, "%s", 5267 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5268 5269 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5270 5271 encoder->hotplug = intel_ddi_hotplug; 5272 encoder->compute_output_type = intel_ddi_compute_output_type; 5273 encoder->compute_config = intel_ddi_compute_config; 5274 encoder->compute_config_late = intel_ddi_compute_config_late; 5275 encoder->enable = intel_ddi_enable; 5276 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5277 encoder->pre_enable = intel_ddi_pre_enable; 5278 encoder->disable = intel_ddi_disable; 5279 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5280 encoder->post_disable = intel_ddi_post_disable; 5281 encoder->update_pipe = intel_ddi_update_pipe; 5282 encoder->audio_enable = intel_audio_codec_enable; 5283 encoder->audio_disable = intel_audio_codec_disable; 5284 encoder->get_hw_state = intel_ddi_get_hw_state; 5285 encoder->sync_state = intel_ddi_sync_state; 5286 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5287 encoder->suspend = intel_ddi_encoder_suspend; 5288 encoder->shutdown = intel_ddi_encoder_shutdown; 5289 encoder->get_power_domains = intel_ddi_get_power_domains; 5290 5291 encoder->type = INTEL_OUTPUT_DDI; 5292 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5293 encoder->port = port; 5294 encoder->cloneable = 0; 5295 encoder->pipe_mask = ~0; 5296 5297 if (HAS_LT_PHY(display)) { 5298 encoder->enable_clock = intel_xe3plpd_pll_enable; 5299 encoder->disable_clock = intel_xe3plpd_pll_disable; 5300 encoder->port_pll_type = intel_mtl_port_pll_type; 5301 encoder->get_config = xe3plpd_ddi_get_config; 5302 } else if (DISPLAY_VER(display) >= 14) { 5303 encoder->enable_clock = intel_mtl_pll_enable_clock; 5304 encoder->disable_clock = intel_mtl_pll_disable_clock; 5305 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5306 if (intel_encoder_is_tc(encoder)) 5307 encoder->get_config = mtl_ddi_tc_phy_get_config; 5308 else 5309 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5310 } else if (display->platform.dg2) { 5311 encoder->enable_clock = intel_mpllb_enable; 5312 encoder->disable_clock = intel_mpllb_disable; 5313 encoder->get_config = dg2_ddi_get_config; 5314 } else if (display->platform.alderlake_s) { 5315 encoder->enable_clock = adls_ddi_enable_clock; 5316 encoder->disable_clock = adls_ddi_disable_clock; 5317 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5318 encoder->get_config = adls_ddi_get_config; 5319 } else if (display->platform.rocketlake) { 5320 encoder->enable_clock = rkl_ddi_enable_clock; 5321 encoder->disable_clock = rkl_ddi_disable_clock; 5322 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5323 encoder->get_config = rkl_ddi_get_config; 5324 } else if (display->platform.dg1) { 5325 encoder->enable_clock = dg1_ddi_enable_clock; 5326 encoder->disable_clock = dg1_ddi_disable_clock; 5327 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5328 encoder->get_config = dg1_ddi_get_config; 5329 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5330 if (intel_ddi_is_tc(display, port)) { 5331 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5332 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5333 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5334 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5335 encoder->get_config = icl_ddi_combo_get_config; 5336 } else { 5337 encoder->enable_clock = icl_ddi_combo_enable_clock; 5338 encoder->disable_clock = icl_ddi_combo_disable_clock; 5339 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5340 encoder->get_config = icl_ddi_combo_get_config; 5341 } 5342 } else if (DISPLAY_VER(display) >= 11) { 5343 if (intel_ddi_is_tc(display, port)) { 5344 encoder->enable_clock = icl_ddi_tc_enable_clock; 5345 encoder->disable_clock = icl_ddi_tc_disable_clock; 5346 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5347 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5348 encoder->get_config = icl_ddi_tc_get_config; 5349 } else { 5350 encoder->enable_clock = icl_ddi_combo_enable_clock; 5351 encoder->disable_clock = icl_ddi_combo_disable_clock; 5352 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5353 encoder->get_config = icl_ddi_combo_get_config; 5354 } 5355 } else if (display->platform.geminilake || display->platform.broxton) { 5356 /* BXT/GLK have fixed PLL->port mapping */ 5357 encoder->get_config = bxt_ddi_get_config; 5358 } else if (DISPLAY_VER(display) == 9) { 5359 encoder->enable_clock = skl_ddi_enable_clock; 5360 encoder->disable_clock = skl_ddi_disable_clock; 5361 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5362 encoder->get_config = skl_ddi_get_config; 5363 } else if (display->platform.broadwell || display->platform.haswell) { 5364 encoder->enable_clock = hsw_ddi_enable_clock; 5365 encoder->disable_clock = hsw_ddi_disable_clock; 5366 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5367 encoder->get_config = hsw_ddi_get_config; 5368 } 5369 5370 if (HAS_LT_PHY(display)) { 5371 encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5372 } else if (DISPLAY_VER(display) >= 14) { 5373 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5374 } else if (display->platform.dg2) { 5375 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5376 } else if (DISPLAY_VER(display) >= 12) { 5377 if (intel_encoder_is_combo(encoder)) 5378 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5379 else 5380 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5381 } else if (DISPLAY_VER(display) >= 11) { 5382 if (intel_encoder_is_combo(encoder)) 5383 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5384 else 5385 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5386 } else if (display->platform.geminilake || display->platform.broxton) { 5387 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5388 } else { 5389 encoder->set_signal_levels = hsw_set_signal_levels; 5390 } 5391 5392 intel_ddi_buf_trans_init(encoder); 5393 5394 if (DISPLAY_VER(display) >= 13) 5395 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5396 else if (display->platform.dg1) 5397 encoder->hpd_pin = dg1_hpd_pin(display, port); 5398 else if (display->platform.rocketlake) 5399 encoder->hpd_pin = rkl_hpd_pin(display, port); 5400 else if (DISPLAY_VER(display) >= 12) 5401 encoder->hpd_pin = tgl_hpd_pin(display, port); 5402 else if (display->platform.jasperlake || display->platform.elkhartlake) 5403 encoder->hpd_pin = ehl_hpd_pin(display, port); 5404 else if (DISPLAY_VER(display) == 11) 5405 encoder->hpd_pin = icl_hpd_pin(display, port); 5406 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5407 encoder->hpd_pin = skl_hpd_pin(display, port); 5408 else 5409 encoder->hpd_pin = intel_hpd_pin_default(port); 5410 5411 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5412 5413 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5414 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5415 5416 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5417 5418 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5419 5420 if (need_aux_ch(encoder, init_dp)) { 5421 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5422 if (dig_port->aux_ch == AUX_CH_NONE) 5423 goto err; 5424 } 5425 5426 /* 5427 * FIXME: We currently need to store dedicated_external because devdata 5428 * does not live long enough for when intel_encoder_is_tc() is called on 5429 * the unbind path. This needs to be fixed by making sure that the VBT 5430 * data is kept long enough, so that 5431 * intel_bios_encoder_is_dedicated_external() can be called directly 5432 * from intel_encoder_is_tc(). 5433 */ 5434 if (intel_bios_encoder_is_dedicated_external(devdata)) 5435 dig_port->dedicated_external = true; 5436 5437 if (intel_encoder_is_tc(encoder)) { 5438 bool is_legacy = 5439 !intel_bios_encoder_supports_typec_usb(devdata) && 5440 !intel_bios_encoder_supports_tbt(devdata); 5441 5442 if (!is_legacy && init_hdmi) { 5443 is_legacy = !init_dp; 5444 5445 drm_dbg_kms(display->drm, 5446 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5447 port_name(port), 5448 str_yes_no(init_dp), 5449 is_legacy ? "legacy" : "non-legacy"); 5450 } 5451 5452 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5453 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5454 5455 dig_port->lock = intel_tc_port_lock; 5456 dig_port->unlock = intel_tc_port_unlock; 5457 5458 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5459 goto err; 5460 } 5461 5462 drm_WARN_ON(display->drm, port > PORT_I); 5463 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5464 5465 if (DISPLAY_VER(display) >= 11) { 5466 if (intel_encoder_is_tc(encoder)) 5467 dig_port->connected = intel_tc_port_connected; 5468 else 5469 dig_port->connected = lpt_digital_port_connected; 5470 } else if (display->platform.geminilake || display->platform.broxton) { 5471 dig_port->connected = bdw_digital_port_connected; 5472 } else if (DISPLAY_VER(display) == 9) { 5473 dig_port->connected = lpt_digital_port_connected; 5474 } else if (display->platform.broadwell) { 5475 if (port == PORT_A) 5476 dig_port->connected = bdw_digital_port_connected; 5477 else 5478 dig_port->connected = lpt_digital_port_connected; 5479 } else if (display->platform.haswell) { 5480 if (port == PORT_A) 5481 dig_port->connected = hsw_digital_port_connected; 5482 else 5483 dig_port->connected = lpt_digital_port_connected; 5484 } 5485 5486 intel_infoframe_init(dig_port); 5487 5488 if (init_dp) { 5489 if (intel_ddi_init_dp_connector(dig_port)) 5490 goto err; 5491 5492 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5493 5494 if (dig_port->dp.mso_link_count) 5495 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5496 } 5497 5498 /* 5499 * In theory we don't need the encoder->type check, 5500 * but leave it just in case we have some really bad VBTs... 5501 */ 5502 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5503 if (intel_ddi_init_hdmi_connector(dig_port)) 5504 goto err; 5505 } 5506 5507 return; 5508 5509 err: 5510 drm_encoder_cleanup(&encoder->base); 5511 kfree(dig_port); 5512 } 5513