1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dp_test.h" 58 #include "intel_dp_tunnel.h" 59 #include "intel_dpio_phy.h" 60 #include "intel_dsi.h" 61 #include "intel_encoder.h" 62 #include "intel_fdi.h" 63 #include "intel_fifo_underrun.h" 64 #include "intel_gmbus.h" 65 #include "intel_hdcp.h" 66 #include "intel_hdmi.h" 67 #include "intel_hotplug.h" 68 #include "intel_hti.h" 69 #include "intel_lspcon.h" 70 #include "intel_mg_phy_regs.h" 71 #include "intel_modeset_lock.h" 72 #include "intel_pps.h" 73 #include "intel_psr.h" 74 #include "intel_quirks.h" 75 #include "intel_snps_phy.h" 76 #include "intel_tc.h" 77 #include "intel_vdsc.h" 78 #include "intel_vdsc_regs.h" 79 #include "skl_scaler.h" 80 #include "skl_universal_plane.h" 81 82 static const u8 index_to_dp_signal_levels[] = { 83 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 84 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 85 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 86 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 87 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 88 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 89 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 90 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 91 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 92 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 93 }; 94 95 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 96 const struct intel_ddi_buf_trans *trans) 97 { 98 int level; 99 100 level = intel_bios_hdmi_level_shift(encoder->devdata); 101 if (level < 0) 102 level = trans->hdmi_default_entry; 103 104 return level; 105 } 106 107 static bool has_buf_trans_select(struct drm_i915_private *i915) 108 { 109 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 110 } 111 112 static bool has_iboost(struct drm_i915_private *i915) 113 { 114 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 115 } 116 117 /* 118 * Starting with Haswell, DDI port buffers must be programmed with correct 119 * values in advance. This function programs the correct values for 120 * DP/eDP/FDI use cases. 121 */ 122 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 123 const struct intel_crtc_state *crtc_state) 124 { 125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 126 u32 iboost_bit = 0; 127 int i, n_entries; 128 enum port port = encoder->port; 129 const struct intel_ddi_buf_trans *trans; 130 131 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 132 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 133 return; 134 135 /* If we're boosting the current, set bit 31 of trans1 */ 136 if (has_iboost(dev_priv) && 137 intel_bios_dp_boost_level(encoder->devdata)) 138 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 139 140 for (i = 0; i < n_entries; i++) { 141 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 142 trans->entries[i].hsw.trans1 | iboost_bit); 143 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 144 trans->entries[i].hsw.trans2); 145 } 146 } 147 148 /* 149 * Starting with Haswell, DDI port buffers must be programmed with correct 150 * values in advance. This function programs the correct values for 151 * HDMI/DVI use cases. 152 */ 153 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 154 const struct intel_crtc_state *crtc_state) 155 { 156 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 157 int level = intel_ddi_level(encoder, crtc_state, 0); 158 u32 iboost_bit = 0; 159 int n_entries; 160 enum port port = encoder->port; 161 const struct intel_ddi_buf_trans *trans; 162 163 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 164 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 165 return; 166 167 /* If we're boosting the current, set bit 31 of trans1 */ 168 if (has_iboost(dev_priv) && 169 intel_bios_hdmi_boost_level(encoder->devdata)) 170 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 171 172 /* Entry 9 is for HDMI: */ 173 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 174 trans->entries[level].hsw.trans1 | iboost_bit); 175 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 176 trans->entries[level].hsw.trans2); 177 } 178 179 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 180 { 181 int ret; 182 183 /* FIXME: find out why Bspec's 100us timeout is too short */ 184 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 185 XELPDP_PORT_BUF_PHY_IDLE), 10000); 186 if (ret) 187 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 188 port_name(port)); 189 } 190 191 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 192 enum port port) 193 { 194 if (IS_BROXTON(dev_priv)) { 195 udelay(16); 196 return; 197 } 198 199 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 200 DDI_BUF_IS_IDLE), 8)) 201 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 202 port_name(port)); 203 } 204 205 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 206 { 207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 208 enum port port = encoder->port; 209 int timeout_us; 210 int ret; 211 212 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 213 if (DISPLAY_VER(dev_priv) < 10) { 214 usleep_range(518, 1000); 215 return; 216 } 217 218 if (DISPLAY_VER(dev_priv) >= 14) { 219 timeout_us = 10000; 220 } else if (IS_DG2(dev_priv)) { 221 timeout_us = 1200; 222 } else if (DISPLAY_VER(dev_priv) >= 12) { 223 if (intel_encoder_is_tc(encoder)) 224 timeout_us = 3000; 225 else 226 timeout_us = 1000; 227 } else { 228 timeout_us = 500; 229 } 230 231 if (DISPLAY_VER(dev_priv) >= 14) 232 ret = _wait_for(!(intel_de_read(dev_priv, 233 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 234 XELPDP_PORT_BUF_PHY_IDLE), 235 timeout_us, 10, 10); 236 else 237 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 238 timeout_us, 10, 10); 239 240 if (ret) 241 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 242 port_name(port)); 243 } 244 245 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 246 { 247 switch (pll->info->id) { 248 case DPLL_ID_WRPLL1: 249 return PORT_CLK_SEL_WRPLL1; 250 case DPLL_ID_WRPLL2: 251 return PORT_CLK_SEL_WRPLL2; 252 case DPLL_ID_SPLL: 253 return PORT_CLK_SEL_SPLL; 254 case DPLL_ID_LCPLL_810: 255 return PORT_CLK_SEL_LCPLL_810; 256 case DPLL_ID_LCPLL_1350: 257 return PORT_CLK_SEL_LCPLL_1350; 258 case DPLL_ID_LCPLL_2700: 259 return PORT_CLK_SEL_LCPLL_2700; 260 default: 261 MISSING_CASE(pll->info->id); 262 return PORT_CLK_SEL_NONE; 263 } 264 } 265 266 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 267 const struct intel_crtc_state *crtc_state) 268 { 269 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 270 int clock = crtc_state->port_clock; 271 const enum intel_dpll_id id = pll->info->id; 272 273 switch (id) { 274 default: 275 /* 276 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 277 * here, so do warn if this get passed in 278 */ 279 MISSING_CASE(id); 280 return DDI_CLK_SEL_NONE; 281 case DPLL_ID_ICL_TBTPLL: 282 switch (clock) { 283 case 162000: 284 return DDI_CLK_SEL_TBT_162; 285 case 270000: 286 return DDI_CLK_SEL_TBT_270; 287 case 540000: 288 return DDI_CLK_SEL_TBT_540; 289 case 810000: 290 return DDI_CLK_SEL_TBT_810; 291 default: 292 MISSING_CASE(clock); 293 return DDI_CLK_SEL_NONE; 294 } 295 case DPLL_ID_ICL_MGPLL1: 296 case DPLL_ID_ICL_MGPLL2: 297 case DPLL_ID_ICL_MGPLL3: 298 case DPLL_ID_ICL_MGPLL4: 299 case DPLL_ID_TGL_MGPLL5: 300 case DPLL_ID_TGL_MGPLL6: 301 return DDI_CLK_SEL_MG; 302 } 303 } 304 305 static u32 ddi_buf_phy_link_rate(int port_clock) 306 { 307 switch (port_clock) { 308 case 162000: 309 return DDI_BUF_PHY_LINK_RATE(0); 310 case 216000: 311 return DDI_BUF_PHY_LINK_RATE(4); 312 case 243000: 313 return DDI_BUF_PHY_LINK_RATE(5); 314 case 270000: 315 return DDI_BUF_PHY_LINK_RATE(1); 316 case 324000: 317 return DDI_BUF_PHY_LINK_RATE(6); 318 case 432000: 319 return DDI_BUF_PHY_LINK_RATE(7); 320 case 540000: 321 return DDI_BUF_PHY_LINK_RATE(2); 322 case 810000: 323 return DDI_BUF_PHY_LINK_RATE(3); 324 default: 325 MISSING_CASE(port_clock); 326 return DDI_BUF_PHY_LINK_RATE(0); 327 } 328 } 329 330 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 331 const struct intel_crtc_state *crtc_state) 332 { 333 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 334 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 335 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 336 337 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 338 intel_dp->DP = dig_port->saved_port_bits | 339 DDI_PORT_WIDTH(crtc_state->lane_count) | 340 DDI_BUF_TRANS_SELECT(0); 341 342 if (DISPLAY_VER(i915) >= 14) { 343 if (intel_dp_is_uhbr(crtc_state)) 344 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 345 else 346 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 347 } 348 349 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 350 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 351 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 352 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 353 } 354 } 355 356 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 357 enum port port) 358 { 359 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 360 361 switch (val) { 362 case DDI_CLK_SEL_NONE: 363 return 0; 364 case DDI_CLK_SEL_TBT_162: 365 return 162000; 366 case DDI_CLK_SEL_TBT_270: 367 return 270000; 368 case DDI_CLK_SEL_TBT_540: 369 return 540000; 370 case DDI_CLK_SEL_TBT_810: 371 return 810000; 372 default: 373 MISSING_CASE(val); 374 return 0; 375 } 376 } 377 378 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 379 { 380 /* CRT dotclock is determined via other means */ 381 if (pipe_config->has_pch_encoder) 382 return; 383 384 pipe_config->hw.adjusted_mode.crtc_clock = 385 intel_crtc_dotclock(pipe_config); 386 } 387 388 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 389 const struct drm_connector_state *conn_state) 390 { 391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 393 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 394 u32 temp; 395 396 if (!intel_crtc_has_dp_encoder(crtc_state)) 397 return; 398 399 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 400 401 temp = DP_MSA_MISC_SYNC_CLOCK; 402 403 switch (crtc_state->pipe_bpp) { 404 case 18: 405 temp |= DP_MSA_MISC_6_BPC; 406 break; 407 case 24: 408 temp |= DP_MSA_MISC_8_BPC; 409 break; 410 case 30: 411 temp |= DP_MSA_MISC_10_BPC; 412 break; 413 case 36: 414 temp |= DP_MSA_MISC_12_BPC; 415 break; 416 default: 417 MISSING_CASE(crtc_state->pipe_bpp); 418 break; 419 } 420 421 /* nonsense combination */ 422 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 423 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 424 425 if (crtc_state->limited_color_range) 426 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 427 428 /* 429 * As per DP 1.2 spec section 2.3.4.3 while sending 430 * YCBCR 444 signals we should program MSA MISC1/0 fields with 431 * colorspace information. 432 */ 433 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 434 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 435 436 /* 437 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 438 * of Color Encoding Format and Content Color Gamut] while sending 439 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 440 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 441 */ 442 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 443 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 444 445 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 446 temp); 447 } 448 449 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 450 { 451 if (master_transcoder == TRANSCODER_EDP) 452 return 0; 453 else 454 return master_transcoder + 1; 455 } 456 457 static void 458 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 459 const struct intel_crtc_state *crtc_state) 460 { 461 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 462 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 463 u32 val = 0; 464 465 if (intel_dp_is_uhbr(crtc_state)) 466 val = TRANS_DP2_128B132B_CHANNEL_CODING; 467 468 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 469 } 470 471 /* 472 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 473 * 474 * Only intended to be used by intel_ddi_enable_transcoder_func() and 475 * intel_ddi_config_transcoder_func(). 476 */ 477 static u32 478 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 479 const struct intel_crtc_state *crtc_state) 480 { 481 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 483 enum pipe pipe = crtc->pipe; 484 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 485 enum port port = encoder->port; 486 u32 temp; 487 488 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 489 temp = TRANS_DDI_FUNC_ENABLE; 490 if (DISPLAY_VER(dev_priv) >= 12) 491 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 492 else 493 temp |= TRANS_DDI_SELECT_PORT(port); 494 495 switch (crtc_state->pipe_bpp) { 496 default: 497 MISSING_CASE(crtc_state->pipe_bpp); 498 fallthrough; 499 case 18: 500 temp |= TRANS_DDI_BPC_6; 501 break; 502 case 24: 503 temp |= TRANS_DDI_BPC_8; 504 break; 505 case 30: 506 temp |= TRANS_DDI_BPC_10; 507 break; 508 case 36: 509 temp |= TRANS_DDI_BPC_12; 510 break; 511 } 512 513 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 514 temp |= TRANS_DDI_PVSYNC; 515 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 516 temp |= TRANS_DDI_PHSYNC; 517 518 if (cpu_transcoder == TRANSCODER_EDP) { 519 switch (pipe) { 520 default: 521 MISSING_CASE(pipe); 522 fallthrough; 523 case PIPE_A: 524 /* On Haswell, can only use the always-on power well for 525 * eDP when not using the panel fitter, and when not 526 * using motion blur mitigation (which we don't 527 * support). */ 528 if (crtc_state->pch_pfit.force_thru) 529 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 530 else 531 temp |= TRANS_DDI_EDP_INPUT_A_ON; 532 break; 533 case PIPE_B: 534 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 535 break; 536 case PIPE_C: 537 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 538 break; 539 } 540 } 541 542 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 543 if (crtc_state->has_hdmi_sink) 544 temp |= TRANS_DDI_MODE_SELECT_HDMI; 545 else 546 temp |= TRANS_DDI_MODE_SELECT_DVI; 547 548 if (crtc_state->hdmi_scrambling) 549 temp |= TRANS_DDI_HDMI_SCRAMBLING; 550 if (crtc_state->hdmi_high_tmds_clock_ratio) 551 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 552 if (DISPLAY_VER(dev_priv) >= 14) 553 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 554 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 555 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 556 temp |= (crtc_state->fdi_lanes - 1) << 1; 557 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 558 if (intel_dp_is_uhbr(crtc_state)) 559 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 560 else 561 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 562 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 563 564 if (DISPLAY_VER(dev_priv) >= 12) { 565 enum transcoder master; 566 567 master = crtc_state->mst_master_transcoder; 568 drm_WARN_ON(&dev_priv->drm, 569 master == INVALID_TRANSCODER); 570 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 571 } 572 } else { 573 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 574 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 575 } 576 577 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 578 crtc_state->master_transcoder != INVALID_TRANSCODER) { 579 u8 master_select = 580 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 581 582 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 583 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 584 } 585 586 return temp; 587 } 588 589 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 590 const struct intel_crtc_state *crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 595 596 if (DISPLAY_VER(dev_priv) >= 11) { 597 enum transcoder master_transcoder = crtc_state->master_transcoder; 598 u32 ctl2 = 0; 599 600 if (master_transcoder != INVALID_TRANSCODER) { 601 u8 master_select = 602 bdw_trans_port_sync_master_select(master_transcoder); 603 604 ctl2 |= PORT_SYNC_MODE_ENABLE | 605 PORT_SYNC_MODE_MASTER_SELECT(master_select); 606 } 607 608 intel_de_write(dev_priv, 609 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 610 ctl2); 611 } 612 613 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 614 intel_ddi_transcoder_func_reg_val_get(encoder, 615 crtc_state)); 616 } 617 618 /* 619 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 620 * bit. 621 */ 622 static void 623 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 624 const struct intel_crtc_state *crtc_state) 625 { 626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 628 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 629 u32 ctl; 630 631 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 632 ctl &= ~TRANS_DDI_FUNC_ENABLE; 633 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 634 ctl); 635 } 636 637 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 638 { 639 struct intel_display *display = to_intel_display(crtc_state); 640 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 642 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 643 u32 ctl; 644 645 if (DISPLAY_VER(dev_priv) >= 11) 646 intel_de_write(dev_priv, 647 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 648 0); 649 650 ctl = intel_de_read(dev_priv, 651 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 652 653 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 654 655 ctl &= ~TRANS_DDI_FUNC_ENABLE; 656 657 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 658 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 659 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 660 661 if (DISPLAY_VER(dev_priv) >= 12) { 662 if (!intel_dp_mst_is_master_trans(crtc_state)) { 663 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 664 TRANS_DDI_MODE_SELECT_MASK); 665 } 666 } else { 667 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 668 } 669 670 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 671 ctl); 672 673 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 674 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 675 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 676 /* Quirk time at 100ms for reliable operation */ 677 msleep(100); 678 } 679 } 680 681 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 682 enum transcoder cpu_transcoder, 683 bool enable, u32 hdcp_mask) 684 { 685 struct drm_device *dev = intel_encoder->base.dev; 686 struct drm_i915_private *dev_priv = to_i915(dev); 687 intel_wakeref_t wakeref; 688 int ret = 0; 689 690 wakeref = intel_display_power_get_if_enabled(dev_priv, 691 intel_encoder->power_domain); 692 if (drm_WARN_ON(dev, !wakeref)) 693 return -ENXIO; 694 695 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 696 hdcp_mask, enable ? hdcp_mask : 0); 697 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 698 return ret; 699 } 700 701 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 702 { 703 struct drm_device *dev = intel_connector->base.dev; 704 struct drm_i915_private *dev_priv = to_i915(dev); 705 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 706 int type = intel_connector->base.connector_type; 707 enum port port = encoder->port; 708 enum transcoder cpu_transcoder; 709 intel_wakeref_t wakeref; 710 enum pipe pipe = 0; 711 u32 tmp; 712 bool ret; 713 714 wakeref = intel_display_power_get_if_enabled(dev_priv, 715 encoder->power_domain); 716 if (!wakeref) 717 return false; 718 719 if (!encoder->get_hw_state(encoder, &pipe)) { 720 ret = false; 721 goto out; 722 } 723 724 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 725 cpu_transcoder = TRANSCODER_EDP; 726 else 727 cpu_transcoder = (enum transcoder) pipe; 728 729 tmp = intel_de_read(dev_priv, 730 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 731 732 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 733 case TRANS_DDI_MODE_SELECT_HDMI: 734 case TRANS_DDI_MODE_SELECT_DVI: 735 ret = type == DRM_MODE_CONNECTOR_HDMIA; 736 break; 737 738 case TRANS_DDI_MODE_SELECT_DP_SST: 739 ret = type == DRM_MODE_CONNECTOR_eDP || 740 type == DRM_MODE_CONNECTOR_DisplayPort; 741 break; 742 743 case TRANS_DDI_MODE_SELECT_DP_MST: 744 /* if the transcoder is in MST state then 745 * connector isn't connected */ 746 ret = false; 747 break; 748 749 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 750 if (HAS_DP20(dev_priv)) 751 /* 128b/132b */ 752 ret = false; 753 else 754 /* FDI */ 755 ret = type == DRM_MODE_CONNECTOR_VGA; 756 break; 757 758 default: 759 ret = false; 760 break; 761 } 762 763 out: 764 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 765 766 return ret; 767 } 768 769 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 770 u8 *pipe_mask, bool *is_dp_mst) 771 { 772 struct drm_device *dev = encoder->base.dev; 773 struct drm_i915_private *dev_priv = to_i915(dev); 774 enum port port = encoder->port; 775 intel_wakeref_t wakeref; 776 enum pipe p; 777 u32 tmp; 778 u8 mst_pipe_mask; 779 780 *pipe_mask = 0; 781 *is_dp_mst = false; 782 783 wakeref = intel_display_power_get_if_enabled(dev_priv, 784 encoder->power_domain); 785 if (!wakeref) 786 return; 787 788 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 789 if (!(tmp & DDI_BUF_CTL_ENABLE)) 790 goto out; 791 792 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 793 tmp = intel_de_read(dev_priv, 794 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 795 796 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 797 default: 798 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 799 fallthrough; 800 case TRANS_DDI_EDP_INPUT_A_ON: 801 case TRANS_DDI_EDP_INPUT_A_ONOFF: 802 *pipe_mask = BIT(PIPE_A); 803 break; 804 case TRANS_DDI_EDP_INPUT_B_ONOFF: 805 *pipe_mask = BIT(PIPE_B); 806 break; 807 case TRANS_DDI_EDP_INPUT_C_ONOFF: 808 *pipe_mask = BIT(PIPE_C); 809 break; 810 } 811 812 goto out; 813 } 814 815 mst_pipe_mask = 0; 816 for_each_pipe(dev_priv, p) { 817 enum transcoder cpu_transcoder = (enum transcoder)p; 818 unsigned int port_mask, ddi_select; 819 intel_wakeref_t trans_wakeref; 820 821 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 822 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 823 if (!trans_wakeref) 824 continue; 825 826 if (DISPLAY_VER(dev_priv) >= 12) { 827 port_mask = TGL_TRANS_DDI_PORT_MASK; 828 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 829 } else { 830 port_mask = TRANS_DDI_PORT_MASK; 831 ddi_select = TRANS_DDI_SELECT_PORT(port); 832 } 833 834 tmp = intel_de_read(dev_priv, 835 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 836 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 837 trans_wakeref); 838 839 if ((tmp & port_mask) != ddi_select) 840 continue; 841 842 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 843 (HAS_DP20(dev_priv) && 844 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 845 mst_pipe_mask |= BIT(p); 846 847 *pipe_mask |= BIT(p); 848 } 849 850 if (!*pipe_mask) 851 drm_dbg_kms(&dev_priv->drm, 852 "No pipe for [ENCODER:%d:%s] found\n", 853 encoder->base.base.id, encoder->base.name); 854 855 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 856 drm_dbg_kms(&dev_priv->drm, 857 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 858 encoder->base.base.id, encoder->base.name, 859 *pipe_mask); 860 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 861 } 862 863 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 864 drm_dbg_kms(&dev_priv->drm, 865 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 866 encoder->base.base.id, encoder->base.name, 867 *pipe_mask, mst_pipe_mask); 868 else 869 *is_dp_mst = mst_pipe_mask; 870 871 out: 872 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 873 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 874 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 875 BXT_PHY_LANE_POWERDOWN_ACK | 876 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 877 drm_err(&dev_priv->drm, 878 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 879 encoder->base.base.id, encoder->base.name, tmp); 880 } 881 882 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 883 } 884 885 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 886 enum pipe *pipe) 887 { 888 u8 pipe_mask; 889 bool is_mst; 890 891 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 892 893 if (is_mst || !pipe_mask) 894 return false; 895 896 *pipe = ffs(pipe_mask) - 1; 897 898 return true; 899 } 900 901 static enum intel_display_power_domain 902 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 903 const struct intel_crtc_state *crtc_state) 904 { 905 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 906 907 /* 908 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 909 * DC states enabled at the same time, while for driver initiated AUX 910 * transfers we need the same AUX IOs to be powered but with DC states 911 * disabled. Accordingly use the AUX_IO_<port> power domain here which 912 * leaves DC states enabled. 913 * 914 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 915 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 916 * well, so we can acquire a wider AUX_<port> power domain reference 917 * instead of a specific AUX_IO_<port> reference without powering up any 918 * extra wells. 919 */ 920 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 921 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 922 else if (DISPLAY_VER(i915) < 14 && 923 (intel_crtc_has_dp_encoder(crtc_state) || 924 intel_encoder_is_tc(&dig_port->base))) 925 return intel_aux_power_domain(dig_port); 926 else 927 return POWER_DOMAIN_INVALID; 928 } 929 930 static void 931 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 932 const struct intel_crtc_state *crtc_state) 933 { 934 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 935 enum intel_display_power_domain domain = 936 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 937 938 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 939 940 if (domain == POWER_DOMAIN_INVALID) 941 return; 942 943 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 944 } 945 946 static void 947 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 948 const struct intel_crtc_state *crtc_state) 949 { 950 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 951 enum intel_display_power_domain domain = 952 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 953 intel_wakeref_t wf; 954 955 wf = fetch_and_zero(&dig_port->aux_wakeref); 956 if (!wf) 957 return; 958 959 intel_display_power_put(i915, domain, wf); 960 } 961 962 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 963 struct intel_crtc_state *crtc_state) 964 { 965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 966 struct intel_digital_port *dig_port; 967 968 /* 969 * TODO: Add support for MST encoders. Atm, the following should never 970 * happen since fake-MST encoders don't set their get_power_domains() 971 * hook. 972 */ 973 if (drm_WARN_ON(&dev_priv->drm, 974 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 975 return; 976 977 dig_port = enc_to_dig_port(encoder); 978 979 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 980 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 981 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 982 dig_port->ddi_io_power_domain); 983 } 984 985 main_link_aux_power_domain_get(dig_port, crtc_state); 986 } 987 988 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 989 const struct intel_crtc_state *crtc_state) 990 { 991 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 993 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 994 enum phy phy = intel_encoder_to_phy(encoder); 995 u32 val; 996 997 if (cpu_transcoder == TRANSCODER_EDP) 998 return; 999 1000 if (DISPLAY_VER(dev_priv) >= 13) 1001 val = TGL_TRANS_CLK_SEL_PORT(phy); 1002 else if (DISPLAY_VER(dev_priv) >= 12) 1003 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1004 else 1005 val = TRANS_CLK_SEL_PORT(encoder->port); 1006 1007 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1008 } 1009 1010 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1011 { 1012 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1013 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1014 u32 val; 1015 1016 if (cpu_transcoder == TRANSCODER_EDP) 1017 return; 1018 1019 if (DISPLAY_VER(dev_priv) >= 12) 1020 val = TGL_TRANS_CLK_SEL_DISABLED; 1021 else 1022 val = TRANS_CLK_SEL_DISABLED; 1023 1024 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1025 } 1026 1027 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1028 enum port port, u8 iboost) 1029 { 1030 u32 tmp; 1031 1032 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1033 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1034 if (iboost) 1035 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1036 else 1037 tmp |= BALANCE_LEG_DISABLE(port); 1038 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1039 } 1040 1041 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1042 const struct intel_crtc_state *crtc_state, 1043 int level) 1044 { 1045 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1047 u8 iboost; 1048 1049 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1050 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1051 else 1052 iboost = intel_bios_dp_boost_level(encoder->devdata); 1053 1054 if (iboost == 0) { 1055 const struct intel_ddi_buf_trans *trans; 1056 int n_entries; 1057 1058 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1059 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1060 return; 1061 1062 iboost = trans->entries[level].hsw.i_boost; 1063 } 1064 1065 /* Make sure that the requested I_boost is valid */ 1066 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1067 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1068 return; 1069 } 1070 1071 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1072 1073 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1074 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1075 } 1076 1077 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1078 const struct intel_crtc_state *crtc_state) 1079 { 1080 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1082 int n_entries; 1083 1084 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1085 1086 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1087 n_entries = 1; 1088 if (drm_WARN_ON(&dev_priv->drm, 1089 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1090 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1091 1092 return index_to_dp_signal_levels[n_entries - 1] & 1093 DP_TRAIN_VOLTAGE_SWING_MASK; 1094 } 1095 1096 /* 1097 * We assume that the full set of pre-emphasis values can be 1098 * used on all DDI platforms. Should that change we need to 1099 * rethink this code. 1100 */ 1101 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1102 { 1103 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1104 } 1105 1106 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1107 int lane) 1108 { 1109 if (crtc_state->port_clock > 600000) 1110 return 0; 1111 1112 if (crtc_state->lane_count == 4) 1113 return lane >= 1 ? LOADGEN_SELECT : 0; 1114 else 1115 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1116 } 1117 1118 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1119 const struct intel_crtc_state *crtc_state) 1120 { 1121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1122 const struct intel_ddi_buf_trans *trans; 1123 enum phy phy = intel_encoder_to_phy(encoder); 1124 int n_entries, ln; 1125 u32 val; 1126 1127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1129 return; 1130 1131 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1132 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1133 1134 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1135 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1136 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1137 intel_dp->hobl_active ? val : 0); 1138 } 1139 1140 /* Set PORT_TX_DW5 */ 1141 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1142 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1143 TAP2_DISABLE | TAP3_DISABLE); 1144 val |= SCALING_MODE_SEL(0x2); 1145 val |= RTERM_SELECT(0x6); 1146 val |= TAP3_DISABLE; 1147 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1148 1149 /* Program PORT_TX_DW2 */ 1150 for (ln = 0; ln < 4; ln++) { 1151 int level = intel_ddi_level(encoder, crtc_state, ln); 1152 1153 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1154 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1155 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1156 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1157 RCOMP_SCALAR(0x98)); 1158 } 1159 1160 /* Program PORT_TX_DW4 */ 1161 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1162 for (ln = 0; ln < 4; ln++) { 1163 int level = intel_ddi_level(encoder, crtc_state, ln); 1164 1165 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1166 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1167 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1168 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1169 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1170 } 1171 1172 /* Program PORT_TX_DW7 */ 1173 for (ln = 0; ln < 4; ln++) { 1174 int level = intel_ddi_level(encoder, crtc_state, ln); 1175 1176 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1177 N_SCALAR_MASK, 1178 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1179 } 1180 } 1181 1182 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1183 const struct intel_crtc_state *crtc_state) 1184 { 1185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1186 enum phy phy = intel_encoder_to_phy(encoder); 1187 u32 val; 1188 int ln; 1189 1190 /* 1191 * 1. If port type is eDP or DP, 1192 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1193 * else clear to 0b. 1194 */ 1195 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1196 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1197 val &= ~COMMON_KEEPER_EN; 1198 else 1199 val |= COMMON_KEEPER_EN; 1200 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1201 1202 /* 2. Program loadgen select */ 1203 /* 1204 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1205 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1206 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1207 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1208 */ 1209 for (ln = 0; ln < 4; ln++) { 1210 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1211 LOADGEN_SELECT, 1212 icl_combo_phy_loadgen_select(crtc_state, ln)); 1213 } 1214 1215 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1216 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1217 0, SUS_CLOCK_CONFIG); 1218 1219 /* 4. Clear training enable to change swing values */ 1220 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1221 val &= ~TX_TRAINING_EN; 1222 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1223 1224 /* 5. Program swing and de-emphasis */ 1225 icl_ddi_combo_vswing_program(encoder, crtc_state); 1226 1227 /* 6. Set training enable to trigger update */ 1228 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1229 val |= TX_TRAINING_EN; 1230 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1231 } 1232 1233 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1234 const struct intel_crtc_state *crtc_state) 1235 { 1236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1237 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1238 const struct intel_ddi_buf_trans *trans; 1239 int n_entries, ln; 1240 1241 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1242 return; 1243 1244 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1245 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1246 return; 1247 1248 for (ln = 0; ln < 2; ln++) { 1249 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1250 CRI_USE_FS32, 0); 1251 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1252 CRI_USE_FS32, 0); 1253 } 1254 1255 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1256 for (ln = 0; ln < 2; ln++) { 1257 int level; 1258 1259 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1260 1261 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1262 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1263 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1264 1265 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1266 1267 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1268 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1269 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1270 } 1271 1272 /* Program MG_TX_DRVCTRL with values from vswing table */ 1273 for (ln = 0; ln < 2; ln++) { 1274 int level; 1275 1276 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1277 1278 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1279 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1280 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1281 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1282 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1283 CRI_TXDEEMPH_OVERRIDE_EN); 1284 1285 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1286 1287 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1288 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1289 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1290 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1291 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1292 CRI_TXDEEMPH_OVERRIDE_EN); 1293 1294 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1295 } 1296 1297 /* 1298 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1299 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1300 * values from table for which TX1 and TX2 enabled. 1301 */ 1302 for (ln = 0; ln < 2; ln++) { 1303 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1304 CFG_LOW_RATE_LKREN_EN, 1305 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1306 } 1307 1308 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1309 for (ln = 0; ln < 2; ln++) { 1310 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1311 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1312 CFG_AMI_CK_DIV_OVERRIDE_EN, 1313 crtc_state->port_clock > 500000 ? 1314 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1315 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1316 1317 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1318 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1319 CFG_AMI_CK_DIV_OVERRIDE_EN, 1320 crtc_state->port_clock > 500000 ? 1321 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1322 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1323 } 1324 1325 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1326 for (ln = 0; ln < 2; ln++) { 1327 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1328 0, CRI_CALCINIT); 1329 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1330 0, CRI_CALCINIT); 1331 } 1332 } 1333 1334 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1335 const struct intel_crtc_state *crtc_state) 1336 { 1337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1338 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1339 const struct intel_ddi_buf_trans *trans; 1340 int n_entries, ln; 1341 1342 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1343 return; 1344 1345 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1346 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1347 return; 1348 1349 for (ln = 0; ln < 2; ln++) { 1350 int level; 1351 1352 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1353 1354 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1355 1356 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1357 DKL_TX_PRESHOOT_COEFF_MASK | 1358 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1359 DKL_TX_VSWING_CONTROL_MASK, 1360 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1361 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1362 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1363 1364 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1365 1366 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1367 DKL_TX_PRESHOOT_COEFF_MASK | 1368 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1369 DKL_TX_VSWING_CONTROL_MASK, 1370 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1371 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1372 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1373 1374 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1375 DKL_TX_DP20BITMODE, 0); 1376 1377 if (IS_ALDERLAKE_P(dev_priv)) { 1378 u32 val; 1379 1380 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1381 if (ln == 0) { 1382 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1383 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1384 } else { 1385 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1386 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1387 } 1388 } else { 1389 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1390 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1391 } 1392 1393 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1394 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1395 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1396 val); 1397 } 1398 } 1399 } 1400 1401 static int translate_signal_level(struct intel_dp *intel_dp, 1402 u8 signal_levels) 1403 { 1404 struct intel_display *display = to_intel_display(intel_dp); 1405 int i; 1406 1407 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1408 if (index_to_dp_signal_levels[i] == signal_levels) 1409 return i; 1410 } 1411 1412 drm_WARN(display->drm, 1, 1413 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1414 signal_levels); 1415 1416 return 0; 1417 } 1418 1419 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1420 const struct intel_crtc_state *crtc_state, 1421 int lane) 1422 { 1423 u8 train_set = intel_dp->train_set[lane]; 1424 1425 if (intel_dp_is_uhbr(crtc_state)) { 1426 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1427 } else { 1428 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1429 DP_TRAIN_PRE_EMPHASIS_MASK); 1430 1431 return translate_signal_level(intel_dp, signal_levels); 1432 } 1433 } 1434 1435 int intel_ddi_level(struct intel_encoder *encoder, 1436 const struct intel_crtc_state *crtc_state, 1437 int lane) 1438 { 1439 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1440 const struct intel_ddi_buf_trans *trans; 1441 int level, n_entries; 1442 1443 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1444 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1445 return 0; 1446 1447 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1448 level = intel_ddi_hdmi_level(encoder, trans); 1449 else 1450 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1451 lane); 1452 1453 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1454 level = n_entries - 1; 1455 1456 return level; 1457 } 1458 1459 static void 1460 hsw_set_signal_levels(struct intel_encoder *encoder, 1461 const struct intel_crtc_state *crtc_state) 1462 { 1463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1464 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1465 int level = intel_ddi_level(encoder, crtc_state, 0); 1466 enum port port = encoder->port; 1467 u32 signal_levels; 1468 1469 if (has_iboost(dev_priv)) 1470 skl_ddi_set_iboost(encoder, crtc_state, level); 1471 1472 /* HDMI ignores the rest */ 1473 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1474 return; 1475 1476 signal_levels = DDI_BUF_TRANS_SELECT(level); 1477 1478 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1479 signal_levels); 1480 1481 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1482 intel_dp->DP |= signal_levels; 1483 1484 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1485 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1486 } 1487 1488 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1489 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1490 { 1491 mutex_lock(&i915->display.dpll.lock); 1492 1493 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1494 1495 /* 1496 * "This step and the step before must be 1497 * done with separate register writes." 1498 */ 1499 intel_de_rmw(i915, reg, clk_off, 0); 1500 1501 mutex_unlock(&i915->display.dpll.lock); 1502 } 1503 1504 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1505 u32 clk_off) 1506 { 1507 mutex_lock(&i915->display.dpll.lock); 1508 1509 intel_de_rmw(i915, reg, 0, clk_off); 1510 1511 mutex_unlock(&i915->display.dpll.lock); 1512 } 1513 1514 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1515 u32 clk_off) 1516 { 1517 return !(intel_de_read(i915, reg) & clk_off); 1518 } 1519 1520 static struct intel_shared_dpll * 1521 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1522 u32 clk_sel_mask, u32 clk_sel_shift) 1523 { 1524 enum intel_dpll_id id; 1525 1526 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1527 1528 return intel_get_shared_dpll_by_id(i915, id); 1529 } 1530 1531 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1532 const struct intel_crtc_state *crtc_state) 1533 { 1534 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1535 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1536 enum phy phy = intel_encoder_to_phy(encoder); 1537 1538 if (drm_WARN_ON(&i915->drm, !pll)) 1539 return; 1540 1541 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1542 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1543 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1544 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1545 } 1546 1547 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1548 { 1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1550 enum phy phy = intel_encoder_to_phy(encoder); 1551 1552 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1553 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1554 } 1555 1556 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1557 { 1558 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1559 enum phy phy = intel_encoder_to_phy(encoder); 1560 1561 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1562 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1563 } 1564 1565 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1566 { 1567 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1568 enum phy phy = intel_encoder_to_phy(encoder); 1569 1570 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1571 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1572 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1573 } 1574 1575 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1576 const struct intel_crtc_state *crtc_state) 1577 { 1578 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1579 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1580 enum phy phy = intel_encoder_to_phy(encoder); 1581 1582 if (drm_WARN_ON(&i915->drm, !pll)) 1583 return; 1584 1585 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1586 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1587 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1588 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1589 } 1590 1591 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1592 { 1593 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1594 enum phy phy = intel_encoder_to_phy(encoder); 1595 1596 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1597 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1598 } 1599 1600 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1601 { 1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1603 enum phy phy = intel_encoder_to_phy(encoder); 1604 1605 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1606 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1607 } 1608 1609 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1610 { 1611 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1612 enum phy phy = intel_encoder_to_phy(encoder); 1613 1614 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1615 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1616 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1617 } 1618 1619 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1620 const struct intel_crtc_state *crtc_state) 1621 { 1622 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1623 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1624 enum phy phy = intel_encoder_to_phy(encoder); 1625 1626 if (drm_WARN_ON(&i915->drm, !pll)) 1627 return; 1628 1629 /* 1630 * If we fail this, something went very wrong: first 2 PLLs should be 1631 * used by first 2 phys and last 2 PLLs by last phys 1632 */ 1633 if (drm_WARN_ON(&i915->drm, 1634 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1635 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1636 return; 1637 1638 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1639 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1640 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1641 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1642 } 1643 1644 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1645 { 1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1647 enum phy phy = intel_encoder_to_phy(encoder); 1648 1649 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1650 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1651 } 1652 1653 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1654 { 1655 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 1658 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1659 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1660 } 1661 1662 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1663 { 1664 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1665 enum phy phy = intel_encoder_to_phy(encoder); 1666 enum intel_dpll_id id; 1667 u32 val; 1668 1669 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1670 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1671 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1672 id = val; 1673 1674 /* 1675 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1676 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1677 * bit for phy C and D. 1678 */ 1679 if (phy >= PHY_C) 1680 id += DPLL_ID_DG1_DPLL2; 1681 1682 return intel_get_shared_dpll_by_id(i915, id); 1683 } 1684 1685 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1686 const struct intel_crtc_state *crtc_state) 1687 { 1688 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1689 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1690 enum phy phy = intel_encoder_to_phy(encoder); 1691 1692 if (drm_WARN_ON(&i915->drm, !pll)) 1693 return; 1694 1695 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1696 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1697 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1698 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1699 } 1700 1701 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1702 { 1703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1704 enum phy phy = intel_encoder_to_phy(encoder); 1705 1706 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1707 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1708 } 1709 1710 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1711 { 1712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1713 enum phy phy = intel_encoder_to_phy(encoder); 1714 1715 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1716 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1717 } 1718 1719 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1720 { 1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1722 enum phy phy = intel_encoder_to_phy(encoder); 1723 1724 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1725 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1726 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1727 } 1728 1729 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1730 const struct intel_crtc_state *crtc_state) 1731 { 1732 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1733 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1734 enum port port = encoder->port; 1735 1736 if (drm_WARN_ON(&i915->drm, !pll)) 1737 return; 1738 1739 /* 1740 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1741 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1742 */ 1743 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1744 1745 icl_ddi_combo_enable_clock(encoder, crtc_state); 1746 } 1747 1748 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1749 { 1750 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1751 enum port port = encoder->port; 1752 1753 icl_ddi_combo_disable_clock(encoder); 1754 1755 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1756 } 1757 1758 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1759 { 1760 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1761 enum port port = encoder->port; 1762 u32 tmp; 1763 1764 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1765 1766 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1767 return false; 1768 1769 return icl_ddi_combo_is_clock_enabled(encoder); 1770 } 1771 1772 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1773 const struct intel_crtc_state *crtc_state) 1774 { 1775 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1776 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1777 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1778 enum port port = encoder->port; 1779 1780 if (drm_WARN_ON(&i915->drm, !pll)) 1781 return; 1782 1783 intel_de_write(i915, DDI_CLK_SEL(port), 1784 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1785 1786 mutex_lock(&i915->display.dpll.lock); 1787 1788 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1789 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1790 1791 mutex_unlock(&i915->display.dpll.lock); 1792 } 1793 1794 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1795 { 1796 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1797 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1798 enum port port = encoder->port; 1799 1800 mutex_lock(&i915->display.dpll.lock); 1801 1802 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1803 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1804 1805 mutex_unlock(&i915->display.dpll.lock); 1806 1807 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1808 } 1809 1810 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1811 { 1812 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1813 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1814 enum port port = encoder->port; 1815 u32 tmp; 1816 1817 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1818 1819 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1820 return false; 1821 1822 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1823 1824 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1825 } 1826 1827 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1828 { 1829 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1830 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1831 enum port port = encoder->port; 1832 enum intel_dpll_id id; 1833 u32 tmp; 1834 1835 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1836 1837 switch (tmp & DDI_CLK_SEL_MASK) { 1838 case DDI_CLK_SEL_TBT_162: 1839 case DDI_CLK_SEL_TBT_270: 1840 case DDI_CLK_SEL_TBT_540: 1841 case DDI_CLK_SEL_TBT_810: 1842 id = DPLL_ID_ICL_TBTPLL; 1843 break; 1844 case DDI_CLK_SEL_MG: 1845 id = icl_tc_port_to_pll_id(tc_port); 1846 break; 1847 default: 1848 MISSING_CASE(tmp); 1849 fallthrough; 1850 case DDI_CLK_SEL_NONE: 1851 return NULL; 1852 } 1853 1854 return intel_get_shared_dpll_by_id(i915, id); 1855 } 1856 1857 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1858 { 1859 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1860 enum intel_dpll_id id; 1861 1862 switch (encoder->port) { 1863 case PORT_A: 1864 id = DPLL_ID_SKL_DPLL0; 1865 break; 1866 case PORT_B: 1867 id = DPLL_ID_SKL_DPLL1; 1868 break; 1869 case PORT_C: 1870 id = DPLL_ID_SKL_DPLL2; 1871 break; 1872 default: 1873 MISSING_CASE(encoder->port); 1874 return NULL; 1875 } 1876 1877 return intel_get_shared_dpll_by_id(i915, id); 1878 } 1879 1880 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1881 const struct intel_crtc_state *crtc_state) 1882 { 1883 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1884 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1885 enum port port = encoder->port; 1886 1887 if (drm_WARN_ON(&i915->drm, !pll)) 1888 return; 1889 1890 mutex_lock(&i915->display.dpll.lock); 1891 1892 intel_de_rmw(i915, DPLL_CTRL2, 1893 DPLL_CTRL2_DDI_CLK_OFF(port) | 1894 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1895 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1896 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1897 1898 mutex_unlock(&i915->display.dpll.lock); 1899 } 1900 1901 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1902 { 1903 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1904 enum port port = encoder->port; 1905 1906 mutex_lock(&i915->display.dpll.lock); 1907 1908 intel_de_rmw(i915, DPLL_CTRL2, 1909 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1910 1911 mutex_unlock(&i915->display.dpll.lock); 1912 } 1913 1914 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1915 { 1916 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1917 enum port port = encoder->port; 1918 1919 /* 1920 * FIXME Not sure if the override affects both 1921 * the PLL selection and the CLK_OFF bit. 1922 */ 1923 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1924 } 1925 1926 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1927 { 1928 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1929 enum port port = encoder->port; 1930 enum intel_dpll_id id; 1931 u32 tmp; 1932 1933 tmp = intel_de_read(i915, DPLL_CTRL2); 1934 1935 /* 1936 * FIXME Not sure if the override affects both 1937 * the PLL selection and the CLK_OFF bit. 1938 */ 1939 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1940 return NULL; 1941 1942 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1943 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1944 1945 return intel_get_shared_dpll_by_id(i915, id); 1946 } 1947 1948 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1949 const struct intel_crtc_state *crtc_state) 1950 { 1951 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1952 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1953 enum port port = encoder->port; 1954 1955 if (drm_WARN_ON(&i915->drm, !pll)) 1956 return; 1957 1958 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1959 } 1960 1961 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1962 { 1963 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1964 enum port port = encoder->port; 1965 1966 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1967 } 1968 1969 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1970 { 1971 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1972 enum port port = encoder->port; 1973 1974 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1975 } 1976 1977 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1978 { 1979 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1980 enum port port = encoder->port; 1981 enum intel_dpll_id id; 1982 u32 tmp; 1983 1984 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1985 1986 switch (tmp & PORT_CLK_SEL_MASK) { 1987 case PORT_CLK_SEL_WRPLL1: 1988 id = DPLL_ID_WRPLL1; 1989 break; 1990 case PORT_CLK_SEL_WRPLL2: 1991 id = DPLL_ID_WRPLL2; 1992 break; 1993 case PORT_CLK_SEL_SPLL: 1994 id = DPLL_ID_SPLL; 1995 break; 1996 case PORT_CLK_SEL_LCPLL_810: 1997 id = DPLL_ID_LCPLL_810; 1998 break; 1999 case PORT_CLK_SEL_LCPLL_1350: 2000 id = DPLL_ID_LCPLL_1350; 2001 break; 2002 case PORT_CLK_SEL_LCPLL_2700: 2003 id = DPLL_ID_LCPLL_2700; 2004 break; 2005 default: 2006 MISSING_CASE(tmp); 2007 fallthrough; 2008 case PORT_CLK_SEL_NONE: 2009 return NULL; 2010 } 2011 2012 return intel_get_shared_dpll_by_id(i915, id); 2013 } 2014 2015 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2016 const struct intel_crtc_state *crtc_state) 2017 { 2018 if (encoder->enable_clock) 2019 encoder->enable_clock(encoder, crtc_state); 2020 } 2021 2022 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2023 { 2024 if (encoder->disable_clock) 2025 encoder->disable_clock(encoder); 2026 } 2027 2028 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2029 { 2030 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2031 u32 port_mask; 2032 bool ddi_clk_needed; 2033 2034 /* 2035 * In case of DP MST, we sanitize the primary encoder only, not the 2036 * virtual ones. 2037 */ 2038 if (encoder->type == INTEL_OUTPUT_DP_MST) 2039 return; 2040 2041 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2042 u8 pipe_mask; 2043 bool is_mst; 2044 2045 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2046 /* 2047 * In the unlikely case that BIOS enables DP in MST mode, just 2048 * warn since our MST HW readout is incomplete. 2049 */ 2050 if (drm_WARN_ON(&i915->drm, is_mst)) 2051 return; 2052 } 2053 2054 port_mask = BIT(encoder->port); 2055 ddi_clk_needed = encoder->base.crtc; 2056 2057 if (encoder->type == INTEL_OUTPUT_DSI) { 2058 struct intel_encoder *other_encoder; 2059 2060 port_mask = intel_dsi_encoder_ports(encoder); 2061 /* 2062 * Sanity check that we haven't incorrectly registered another 2063 * encoder using any of the ports of this DSI encoder. 2064 */ 2065 for_each_intel_encoder(&i915->drm, other_encoder) { 2066 if (other_encoder == encoder) 2067 continue; 2068 2069 if (drm_WARN_ON(&i915->drm, 2070 port_mask & BIT(other_encoder->port))) 2071 return; 2072 } 2073 /* 2074 * For DSI we keep the ddi clocks gated 2075 * except during enable/disable sequence. 2076 */ 2077 ddi_clk_needed = false; 2078 } 2079 2080 if (ddi_clk_needed || !encoder->is_clock_enabled || 2081 !encoder->is_clock_enabled(encoder)) 2082 return; 2083 2084 drm_dbg_kms(&i915->drm, 2085 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2086 encoder->base.base.id, encoder->base.name); 2087 2088 encoder->disable_clock(encoder); 2089 } 2090 2091 static void 2092 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2093 const struct intel_crtc_state *crtc_state) 2094 { 2095 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2096 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2097 u32 ln0, ln1, pin_assignment; 2098 u8 width; 2099 2100 if (DISPLAY_VER(dev_priv) >= 14) 2101 return; 2102 2103 if (!intel_encoder_is_tc(&dig_port->base) || 2104 intel_tc_port_in_tbt_alt_mode(dig_port)) 2105 return; 2106 2107 if (DISPLAY_VER(dev_priv) >= 12) { 2108 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2109 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2110 } else { 2111 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2112 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2113 } 2114 2115 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2116 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2117 2118 /* DPPATC */ 2119 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2120 width = crtc_state->lane_count; 2121 2122 switch (pin_assignment) { 2123 case 0x0: 2124 drm_WARN_ON(&dev_priv->drm, 2125 !intel_tc_port_in_legacy_mode(dig_port)); 2126 if (width == 1) { 2127 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2128 } else { 2129 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2130 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2131 } 2132 break; 2133 case 0x1: 2134 if (width == 4) { 2135 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2136 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2137 } 2138 break; 2139 case 0x2: 2140 if (width == 2) { 2141 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2142 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2143 } 2144 break; 2145 case 0x3: 2146 case 0x5: 2147 if (width == 1) { 2148 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2149 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2150 } else { 2151 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2152 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2153 } 2154 break; 2155 case 0x4: 2156 case 0x6: 2157 if (width == 1) { 2158 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2159 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2160 } else { 2161 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2162 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2163 } 2164 break; 2165 default: 2166 MISSING_CASE(pin_assignment); 2167 } 2168 2169 if (DISPLAY_VER(dev_priv) >= 12) { 2170 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2171 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2172 } else { 2173 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2174 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2175 } 2176 } 2177 2178 static enum transcoder 2179 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2180 { 2181 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2182 return crtc_state->mst_master_transcoder; 2183 else 2184 return crtc_state->cpu_transcoder; 2185 } 2186 2187 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2188 const struct intel_crtc_state *crtc_state) 2189 { 2190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2191 2192 if (DISPLAY_VER(dev_priv) >= 12) 2193 return TGL_DP_TP_CTL(dev_priv, 2194 tgl_dp_tp_transcoder(crtc_state)); 2195 else 2196 return DP_TP_CTL(encoder->port); 2197 } 2198 2199 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2200 const struct intel_crtc_state *crtc_state) 2201 { 2202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2203 2204 if (DISPLAY_VER(dev_priv) >= 12) 2205 return TGL_DP_TP_STATUS(dev_priv, 2206 tgl_dp_tp_transcoder(crtc_state)); 2207 else 2208 return DP_TP_STATUS(encoder->port); 2209 } 2210 2211 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2212 const struct intel_crtc_state *crtc_state, 2213 bool enable) 2214 { 2215 struct intel_display *display = to_intel_display(intel_dp); 2216 2217 if (!crtc_state->vrr.enable) 2218 return; 2219 2220 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2221 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2222 drm_dbg_kms(display->drm, 2223 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2224 str_enable_disable(enable)); 2225 } 2226 2227 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2228 const struct intel_crtc_state *crtc_state, 2229 bool enable) 2230 { 2231 struct intel_display *display = to_intel_display(intel_dp); 2232 2233 if (!crtc_state->fec_enable) 2234 return; 2235 2236 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2237 enable ? DP_FEC_READY : 0) <= 0) 2238 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2239 enable ? "enabled" : "disabled"); 2240 2241 if (enable && 2242 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2243 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2244 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2245 } 2246 2247 static int read_fec_detected_status(struct drm_dp_aux *aux) 2248 { 2249 int ret; 2250 u8 status; 2251 2252 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2253 if (ret < 0) 2254 return ret; 2255 2256 return status; 2257 } 2258 2259 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2260 { 2261 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2262 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2263 int status; 2264 int err; 2265 2266 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2267 status & mask || status < 0, 2268 10000, 200000); 2269 2270 if (!err && status >= 0) 2271 return; 2272 2273 if (err == -ETIMEDOUT) 2274 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2275 str_enabled_disabled(enabled)); 2276 else 2277 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2278 } 2279 2280 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2281 const struct intel_crtc_state *crtc_state, 2282 bool enabled) 2283 { 2284 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2286 int ret; 2287 2288 if (!crtc_state->fec_enable) 2289 return; 2290 2291 if (enabled) 2292 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2293 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2294 else 2295 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2296 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2297 2298 if (ret) 2299 drm_err(&i915->drm, 2300 "Timeout waiting for FEC live state to get %s\n", 2301 str_enabled_disabled(enabled)); 2302 2303 /* 2304 * At least the Synoptics MST hub doesn't set the detected flag for 2305 * FEC decoding disabling so skip waiting for that. 2306 */ 2307 if (enabled) 2308 wait_for_fec_detected(&intel_dp->aux, enabled); 2309 } 2310 2311 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2312 const struct intel_crtc_state *crtc_state) 2313 { 2314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2315 2316 if (!crtc_state->fec_enable) 2317 return; 2318 2319 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2320 0, DP_TP_CTL_FEC_ENABLE); 2321 } 2322 2323 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2324 const struct intel_crtc_state *crtc_state) 2325 { 2326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2327 2328 if (!crtc_state->fec_enable) 2329 return; 2330 2331 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2332 DP_TP_CTL_FEC_ENABLE, 0); 2333 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2334 } 2335 2336 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2337 const struct intel_crtc_state *crtc_state) 2338 { 2339 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2340 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2341 2342 if (intel_encoder_is_combo(encoder)) { 2343 enum phy phy = intel_encoder_to_phy(encoder); 2344 bool lane_reversal = 2345 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2346 2347 intel_combo_phy_power_up_lanes(i915, phy, false, 2348 crtc_state->lane_count, 2349 lane_reversal); 2350 } 2351 } 2352 2353 /* 2354 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2355 * platforms. 2356 */ 2357 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2358 { 2359 if (DISPLAY_VER(i915) > 20) 2360 return ~0; 2361 else if (IS_ALDERLAKE_P(i915)) 2362 return BIT(PIPE_A) | BIT(PIPE_B); 2363 else 2364 return BIT(PIPE_A); 2365 } 2366 2367 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2368 struct intel_crtc_state *pipe_config) 2369 { 2370 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2371 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2372 enum pipe pipe = crtc->pipe; 2373 u32 dss1; 2374 2375 if (!HAS_MSO(i915)) 2376 return; 2377 2378 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2379 2380 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2381 if (!pipe_config->splitter.enable) 2382 return; 2383 2384 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2385 pipe_config->splitter.enable = false; 2386 return; 2387 } 2388 2389 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2390 default: 2391 drm_WARN(&i915->drm, true, 2392 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2393 fallthrough; 2394 case SPLITTER_CONFIGURATION_2_SEGMENT: 2395 pipe_config->splitter.link_count = 2; 2396 break; 2397 case SPLITTER_CONFIGURATION_4_SEGMENT: 2398 pipe_config->splitter.link_count = 4; 2399 break; 2400 } 2401 2402 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2403 } 2404 2405 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2406 { 2407 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2408 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2409 enum pipe pipe = crtc->pipe; 2410 u32 dss1 = 0; 2411 2412 if (!HAS_MSO(i915)) 2413 return; 2414 2415 if (crtc_state->splitter.enable) { 2416 dss1 |= SPLITTER_ENABLE; 2417 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2418 if (crtc_state->splitter.link_count == 2) 2419 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2420 else 2421 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2422 } 2423 2424 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2425 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2426 OVERLAP_PIXELS_MASK, dss1); 2427 } 2428 2429 static u8 mtl_get_port_width(u8 lane_count) 2430 { 2431 switch (lane_count) { 2432 case 1: 2433 return 0; 2434 case 2: 2435 return 1; 2436 case 3: 2437 return 4; 2438 case 4: 2439 return 3; 2440 default: 2441 MISSING_CASE(lane_count); 2442 return 4; 2443 } 2444 } 2445 2446 static void 2447 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2448 { 2449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2450 enum port port = encoder->port; 2451 i915_reg_t reg; 2452 u32 set_bits, wait_bits; 2453 2454 if (DISPLAY_VER(dev_priv) >= 20) { 2455 reg = DDI_BUF_CTL(port); 2456 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2457 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2458 } else { 2459 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2460 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2461 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2462 } 2463 2464 intel_de_rmw(dev_priv, reg, 0, set_bits); 2465 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2466 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2467 port_name(port)); 2468 } 2469 } 2470 2471 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2472 const struct intel_crtc_state *crtc_state) 2473 { 2474 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2475 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2476 enum port port = encoder->port; 2477 u32 val; 2478 2479 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2480 val &= ~XELPDP_PORT_WIDTH_MASK; 2481 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2482 2483 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2484 if (intel_dp_is_uhbr(crtc_state)) 2485 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2486 else 2487 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2488 2489 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2490 val |= XELPDP_PORT_REVERSAL; 2491 2492 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2493 } 2494 2495 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2496 { 2497 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2498 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2499 u32 val; 2500 2501 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2502 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2503 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2504 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2505 } 2506 2507 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2508 struct intel_encoder *encoder, 2509 const struct intel_crtc_state *crtc_state, 2510 const struct drm_connector_state *conn_state) 2511 { 2512 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2513 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2514 2515 intel_dp_set_link_params(intel_dp, 2516 crtc_state->port_clock, 2517 crtc_state->lane_count); 2518 2519 /* 2520 * We only configure what the register value will be here. Actual 2521 * enabling happens during link training farther down. 2522 */ 2523 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2524 2525 /* 2526 * 1. Enable Power Wells 2527 * 2528 * This was handled at the beginning of intel_atomic_commit_tail(), 2529 * before we called down into this function. 2530 */ 2531 2532 /* 2. PMdemand was already set */ 2533 2534 /* 3. Select Thunderbolt */ 2535 mtl_port_buf_ctl_io_selection(encoder); 2536 2537 /* 4. Enable Panel Power if PPS is required */ 2538 intel_pps_on(intel_dp); 2539 2540 /* 5. Enable the port PLL */ 2541 intel_ddi_enable_clock(encoder, crtc_state); 2542 2543 /* 2544 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2545 * Transcoder. 2546 */ 2547 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2548 2549 /* 2550 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2551 */ 2552 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2553 2554 /* 2555 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2556 * Transport Select 2557 */ 2558 intel_ddi_config_transcoder_func(encoder, crtc_state); 2559 2560 /* 2561 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2562 */ 2563 intel_ddi_mso_configure(crtc_state); 2564 2565 if (!is_mst) 2566 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2567 2568 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2569 if (!is_mst) 2570 intel_dp_sink_enable_decompression(state, 2571 to_intel_connector(conn_state->connector), 2572 crtc_state); 2573 2574 /* 2575 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2576 * in the FEC_CONFIGURATION register to 1 before initiating link 2577 * training 2578 */ 2579 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2580 2581 intel_dp_check_frl_training(intel_dp); 2582 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2583 2584 /* 2585 * 6. The rest of the below are substeps under the bspec's "Enable and 2586 * Train Display Port" step. Note that steps that are specific to 2587 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2588 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2589 * us when active_mst_links==0, so any steps designated for "single 2590 * stream or multi-stream master transcoder" can just be performed 2591 * unconditionally here. 2592 * 2593 * mtl_ddi_prepare_link_retrain() that is called by 2594 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2595 * 6.i and 6.j 2596 * 2597 * 6.k Follow DisplayPort specification training sequence (see notes for 2598 * failure handling) 2599 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2600 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2601 * (timeout after 800 us) 2602 */ 2603 intel_dp_start_link_train(state, intel_dp, crtc_state); 2604 2605 /* 6.n Set DP_TP_CTL link training to Normal */ 2606 if (!is_trans_port_sync_mode(crtc_state)) 2607 intel_dp_stop_link_train(intel_dp, crtc_state); 2608 2609 /* 6.o Configure and enable FEC if needed */ 2610 intel_ddi_enable_fec(encoder, crtc_state); 2611 2612 if (!is_mst) 2613 intel_dsc_dp_pps_write(encoder, crtc_state); 2614 } 2615 2616 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2617 struct intel_encoder *encoder, 2618 const struct intel_crtc_state *crtc_state, 2619 const struct drm_connector_state *conn_state) 2620 { 2621 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2623 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2624 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2625 2626 intel_dp_set_link_params(intel_dp, 2627 crtc_state->port_clock, 2628 crtc_state->lane_count); 2629 2630 /* 2631 * We only configure what the register value will be here. Actual 2632 * enabling happens during link training farther down. 2633 */ 2634 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2635 2636 /* 2637 * 1. Enable Power Wells 2638 * 2639 * This was handled at the beginning of intel_atomic_commit_tail(), 2640 * before we called down into this function. 2641 */ 2642 2643 /* 2. Enable Panel Power if PPS is required */ 2644 intel_pps_on(intel_dp); 2645 2646 /* 2647 * 3. For non-TBT Type-C ports, set FIA lane count 2648 * (DFLEXDPSP.DPX4TXLATC) 2649 * 2650 * This was done before tgl_ddi_pre_enable_dp by 2651 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2652 */ 2653 2654 /* 2655 * 4. Enable the port PLL. 2656 * 2657 * The PLL enabling itself was already done before this function by 2658 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2659 * configure the PLL to port mapping here. 2660 */ 2661 intel_ddi_enable_clock(encoder, crtc_state); 2662 2663 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2664 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2665 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2666 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2667 dig_port->ddi_io_power_domain); 2668 } 2669 2670 /* 6. Program DP_MODE */ 2671 icl_program_mg_dp_mode(dig_port, crtc_state); 2672 2673 /* 2674 * 7. The rest of the below are substeps under the bspec's "Enable and 2675 * Train Display Port" step. Note that steps that are specific to 2676 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2677 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2678 * us when active_mst_links==0, so any steps designated for "single 2679 * stream or multi-stream master transcoder" can just be performed 2680 * unconditionally here. 2681 */ 2682 2683 /* 2684 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2685 * Transcoder. 2686 */ 2687 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2688 2689 if (HAS_DP20(dev_priv)) 2690 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2691 2692 /* 2693 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2694 * Transport Select 2695 */ 2696 intel_ddi_config_transcoder_func(encoder, crtc_state); 2697 2698 /* 2699 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2700 * selected 2701 * 2702 * This will be handled by the intel_dp_start_link_train() farther 2703 * down this function. 2704 */ 2705 2706 /* 7.e Configure voltage swing and related IO settings */ 2707 encoder->set_signal_levels(encoder, crtc_state); 2708 2709 /* 2710 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2711 * the used lanes of the DDI. 2712 */ 2713 intel_ddi_power_up_lanes(encoder, crtc_state); 2714 2715 /* 2716 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2717 */ 2718 intel_ddi_mso_configure(crtc_state); 2719 2720 if (!is_mst) 2721 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2722 2723 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2724 if (!is_mst) 2725 intel_dp_sink_enable_decompression(state, 2726 to_intel_connector(conn_state->connector), 2727 crtc_state); 2728 /* 2729 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2730 * in the FEC_CONFIGURATION register to 1 before initiating link 2731 * training 2732 */ 2733 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2734 2735 intel_dp_check_frl_training(intel_dp); 2736 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2737 2738 /* 2739 * 7.i Follow DisplayPort specification training sequence (see notes for 2740 * failure handling) 2741 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2742 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2743 * (timeout after 800 us) 2744 */ 2745 intel_dp_start_link_train(state, intel_dp, crtc_state); 2746 2747 /* 7.k Set DP_TP_CTL link training to Normal */ 2748 if (!is_trans_port_sync_mode(crtc_state)) 2749 intel_dp_stop_link_train(intel_dp, crtc_state); 2750 2751 /* 7.l Configure and enable FEC if needed */ 2752 intel_ddi_enable_fec(encoder, crtc_state); 2753 2754 if (!is_mst) 2755 intel_dsc_dp_pps_write(encoder, crtc_state); 2756 } 2757 2758 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2759 struct intel_encoder *encoder, 2760 const struct intel_crtc_state *crtc_state, 2761 const struct drm_connector_state *conn_state) 2762 { 2763 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2764 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2765 enum port port = encoder->port; 2766 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2767 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2768 2769 if (DISPLAY_VER(dev_priv) < 11) 2770 drm_WARN_ON(&dev_priv->drm, 2771 is_mst && (port == PORT_A || port == PORT_E)); 2772 else 2773 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2774 2775 intel_dp_set_link_params(intel_dp, 2776 crtc_state->port_clock, 2777 crtc_state->lane_count); 2778 2779 /* 2780 * We only configure what the register value will be here. Actual 2781 * enabling happens during link training farther down. 2782 */ 2783 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2784 2785 intel_pps_on(intel_dp); 2786 2787 intel_ddi_enable_clock(encoder, crtc_state); 2788 2789 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2790 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2791 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2792 dig_port->ddi_io_power_domain); 2793 } 2794 2795 icl_program_mg_dp_mode(dig_port, crtc_state); 2796 2797 if (has_buf_trans_select(dev_priv)) 2798 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2799 2800 encoder->set_signal_levels(encoder, crtc_state); 2801 2802 intel_ddi_power_up_lanes(encoder, crtc_state); 2803 2804 if (!is_mst) 2805 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2806 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2807 if (!is_mst) 2808 intel_dp_sink_enable_decompression(state, 2809 to_intel_connector(conn_state->connector), 2810 crtc_state); 2811 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2812 intel_dp_start_link_train(state, intel_dp, crtc_state); 2813 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2814 !is_trans_port_sync_mode(crtc_state)) 2815 intel_dp_stop_link_train(intel_dp, crtc_state); 2816 2817 intel_ddi_enable_fec(encoder, crtc_state); 2818 2819 if (!is_mst) { 2820 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2821 intel_dsc_dp_pps_write(encoder, crtc_state); 2822 } 2823 } 2824 2825 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2826 struct intel_encoder *encoder, 2827 const struct intel_crtc_state *crtc_state, 2828 const struct drm_connector_state *conn_state) 2829 { 2830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2831 2832 if (HAS_DP20(dev_priv)) 2833 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2834 crtc_state); 2835 2836 /* Panel replay has to be enabled in sink dpcd before link training. */ 2837 if (crtc_state->has_panel_replay) 2838 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2839 2840 if (DISPLAY_VER(dev_priv) >= 14) 2841 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2842 else if (DISPLAY_VER(dev_priv) >= 12) 2843 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2844 else 2845 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2846 2847 /* MST will call a setting of MSA after an allocating of Virtual Channel 2848 * from MST encoder pre_enable callback. 2849 */ 2850 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2851 intel_ddi_set_dp_msa(crtc_state, conn_state); 2852 } 2853 2854 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2855 struct intel_encoder *encoder, 2856 const struct intel_crtc_state *crtc_state, 2857 const struct drm_connector_state *conn_state) 2858 { 2859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2862 2863 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2864 intel_ddi_enable_clock(encoder, crtc_state); 2865 2866 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2867 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2868 dig_port->ddi_io_power_domain); 2869 2870 icl_program_mg_dp_mode(dig_port, crtc_state); 2871 2872 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2873 2874 dig_port->set_infoframes(encoder, 2875 crtc_state->has_infoframe, 2876 crtc_state, conn_state); 2877 } 2878 2879 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2880 struct intel_encoder *encoder, 2881 const struct intel_crtc_state *crtc_state, 2882 const struct drm_connector_state *conn_state) 2883 { 2884 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2885 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2886 enum pipe pipe = crtc->pipe; 2887 2888 /* 2889 * When called from DP MST code: 2890 * - conn_state will be NULL 2891 * - encoder will be the main encoder (ie. mst->primary) 2892 * - the main connector associated with this port 2893 * won't be active or linked to a crtc 2894 * - crtc_state will be the state of the first stream to 2895 * be activated on this port, and it may not be the same 2896 * stream that will be deactivated last, but each stream 2897 * should have a state that is identical when it comes to 2898 * the DP link parameteres 2899 */ 2900 2901 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2902 2903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2904 2905 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2906 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2907 conn_state); 2908 } else { 2909 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2910 2911 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2912 conn_state); 2913 2914 /* FIXME precompute everything properly */ 2915 /* FIXME how do we turn infoframes off again? */ 2916 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2917 dig_port->set_infoframes(encoder, 2918 crtc_state->has_infoframe, 2919 crtc_state, conn_state); 2920 } 2921 } 2922 2923 static void 2924 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2925 { 2926 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2927 enum port port = encoder->port; 2928 i915_reg_t reg; 2929 u32 clr_bits, wait_bits; 2930 2931 if (DISPLAY_VER(dev_priv) >= 20) { 2932 reg = DDI_BUF_CTL(port); 2933 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2934 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2935 } else { 2936 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2937 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2938 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2939 } 2940 2941 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2942 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2943 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2944 port_name(port)); 2945 } 2946 2947 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2948 const struct intel_crtc_state *crtc_state) 2949 { 2950 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2951 enum port port = encoder->port; 2952 u32 val; 2953 2954 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2955 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2956 if (val & DDI_BUF_CTL_ENABLE) { 2957 val &= ~DDI_BUF_CTL_ENABLE; 2958 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2959 2960 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2961 mtl_wait_ddi_buf_idle(dev_priv, port); 2962 } 2963 2964 /* 3.d Disable D2D Link */ 2965 mtl_ddi_disable_d2d_link(encoder); 2966 2967 /* 3.e Disable DP_TP_CTL */ 2968 if (intel_crtc_has_dp_encoder(crtc_state)) { 2969 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2970 DP_TP_CTL_ENABLE, 0); 2971 } 2972 } 2973 2974 static void disable_ddi_buf(struct intel_encoder *encoder, 2975 const struct intel_crtc_state *crtc_state) 2976 { 2977 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2978 enum port port = encoder->port; 2979 bool wait = false; 2980 u32 val; 2981 2982 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2983 if (val & DDI_BUF_CTL_ENABLE) { 2984 val &= ~DDI_BUF_CTL_ENABLE; 2985 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2986 wait = true; 2987 } 2988 2989 if (intel_crtc_has_dp_encoder(crtc_state)) 2990 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2991 DP_TP_CTL_ENABLE, 0); 2992 2993 intel_ddi_disable_fec(encoder, crtc_state); 2994 2995 if (wait) 2996 intel_wait_ddi_buf_idle(dev_priv, port); 2997 } 2998 2999 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3000 const struct intel_crtc_state *crtc_state) 3001 { 3002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3003 3004 if (DISPLAY_VER(dev_priv) >= 14) { 3005 mtl_disable_ddi_buf(encoder, crtc_state); 3006 3007 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3008 intel_ddi_disable_fec(encoder, crtc_state); 3009 } else { 3010 disable_ddi_buf(encoder, crtc_state); 3011 } 3012 3013 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3014 } 3015 3016 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3017 struct intel_encoder *encoder, 3018 const struct intel_crtc_state *old_crtc_state, 3019 const struct drm_connector_state *old_conn_state) 3020 { 3021 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3022 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3023 struct intel_dp *intel_dp = &dig_port->dp; 3024 intel_wakeref_t wakeref; 3025 bool is_mst = intel_crtc_has_type(old_crtc_state, 3026 INTEL_OUTPUT_DP_MST); 3027 3028 if (!is_mst) 3029 intel_dp_set_infoframes(encoder, false, 3030 old_crtc_state, old_conn_state); 3031 3032 /* 3033 * Power down sink before disabling the port, otherwise we end 3034 * up getting interrupts from the sink on detecting link loss. 3035 */ 3036 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3037 3038 if (DISPLAY_VER(dev_priv) >= 12) { 3039 if (is_mst) { 3040 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3041 3042 intel_de_rmw(dev_priv, 3043 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3044 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3045 0); 3046 } 3047 } else { 3048 if (!is_mst) 3049 intel_ddi_disable_transcoder_clock(old_crtc_state); 3050 } 3051 3052 intel_disable_ddi_buf(encoder, old_crtc_state); 3053 3054 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3055 3056 /* 3057 * From TGL spec: "If single stream or multi-stream master transcoder: 3058 * Configure Transcoder Clock select to direct no clock to the 3059 * transcoder" 3060 */ 3061 if (DISPLAY_VER(dev_priv) >= 12) 3062 intel_ddi_disable_transcoder_clock(old_crtc_state); 3063 3064 intel_pps_vdd_on(intel_dp); 3065 intel_pps_off(intel_dp); 3066 3067 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3068 3069 if (wakeref) 3070 intel_display_power_put(dev_priv, 3071 dig_port->ddi_io_power_domain, 3072 wakeref); 3073 3074 intel_ddi_disable_clock(encoder); 3075 3076 /* De-select Thunderbolt */ 3077 if (DISPLAY_VER(dev_priv) >= 14) 3078 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3079 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3080 } 3081 3082 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3083 struct intel_encoder *encoder, 3084 const struct intel_crtc_state *old_crtc_state, 3085 const struct drm_connector_state *old_conn_state) 3086 { 3087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3088 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3089 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3090 intel_wakeref_t wakeref; 3091 3092 dig_port->set_infoframes(encoder, false, 3093 old_crtc_state, old_conn_state); 3094 3095 if (DISPLAY_VER(dev_priv) < 12) 3096 intel_ddi_disable_transcoder_clock(old_crtc_state); 3097 3098 intel_disable_ddi_buf(encoder, old_crtc_state); 3099 3100 if (DISPLAY_VER(dev_priv) >= 12) 3101 intel_ddi_disable_transcoder_clock(old_crtc_state); 3102 3103 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3104 if (wakeref) 3105 intel_display_power_put(dev_priv, 3106 dig_port->ddi_io_power_domain, 3107 wakeref); 3108 3109 intel_ddi_disable_clock(encoder); 3110 3111 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3112 } 3113 3114 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3115 struct intel_encoder *encoder, 3116 const struct intel_crtc_state *old_crtc_state, 3117 const struct drm_connector_state *old_conn_state) 3118 { 3119 struct intel_display *display = to_intel_display(encoder); 3120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3121 struct intel_crtc *pipe_crtc; 3122 int i; 3123 3124 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3125 const struct intel_crtc_state *old_pipe_crtc_state = 3126 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3127 3128 intel_crtc_vblank_off(old_pipe_crtc_state); 3129 } 3130 3131 intel_disable_transcoder(old_crtc_state); 3132 3133 intel_ddi_disable_transcoder_func(old_crtc_state); 3134 3135 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3136 const struct intel_crtc_state *old_pipe_crtc_state = 3137 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3138 3139 intel_dsc_disable(old_pipe_crtc_state); 3140 3141 if (DISPLAY_VER(dev_priv) >= 9) 3142 skl_scaler_disable(old_pipe_crtc_state); 3143 else 3144 ilk_pfit_disable(old_pipe_crtc_state); 3145 } 3146 } 3147 3148 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3149 struct intel_encoder *encoder, 3150 const struct intel_crtc_state *old_crtc_state, 3151 const struct drm_connector_state *old_conn_state) 3152 { 3153 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3154 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3155 old_conn_state); 3156 3157 /* 3158 * When called from DP MST code: 3159 * - old_conn_state will be NULL 3160 * - encoder will be the main encoder (ie. mst->primary) 3161 * - the main connector associated with this port 3162 * won't be active or linked to a crtc 3163 * - old_crtc_state will be the state of the last stream to 3164 * be deactivated on this port, and it may not be the same 3165 * stream that was activated last, but each stream 3166 * should have a state that is identical when it comes to 3167 * the DP link parameteres 3168 */ 3169 3170 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3171 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3172 old_conn_state); 3173 else 3174 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3175 old_conn_state); 3176 } 3177 3178 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3179 struct intel_encoder *encoder, 3180 const struct intel_crtc_state *old_crtc_state, 3181 const struct drm_connector_state *old_conn_state) 3182 { 3183 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3184 3185 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3186 3187 if (intel_encoder_is_tc(encoder)) 3188 intel_tc_port_put_link(dig_port); 3189 } 3190 3191 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3192 struct intel_encoder *encoder, 3193 const struct intel_crtc_state *crtc_state) 3194 { 3195 const struct drm_connector_state *conn_state; 3196 struct drm_connector *conn; 3197 int i; 3198 3199 if (!crtc_state->sync_mode_slaves_mask) 3200 return; 3201 3202 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3203 struct intel_encoder *slave_encoder = 3204 to_intel_encoder(conn_state->best_encoder); 3205 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3206 const struct intel_crtc_state *slave_crtc_state; 3207 3208 if (!slave_crtc) 3209 continue; 3210 3211 slave_crtc_state = 3212 intel_atomic_get_new_crtc_state(state, slave_crtc); 3213 3214 if (slave_crtc_state->master_transcoder != 3215 crtc_state->cpu_transcoder) 3216 continue; 3217 3218 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3219 slave_crtc_state); 3220 } 3221 3222 usleep_range(200, 400); 3223 3224 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3225 crtc_state); 3226 } 3227 3228 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3229 struct intel_encoder *encoder, 3230 const struct intel_crtc_state *crtc_state, 3231 const struct drm_connector_state *conn_state) 3232 { 3233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3234 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3235 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3236 enum port port = encoder->port; 3237 3238 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3239 intel_dp_stop_link_train(intel_dp, crtc_state); 3240 3241 drm_connector_update_privacy_screen(conn_state); 3242 intel_edp_backlight_on(crtc_state, conn_state); 3243 3244 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3245 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3246 3247 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3248 } 3249 3250 /* FIXME bad home for this function */ 3251 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3252 enum transcoder cpu_transcoder) 3253 { 3254 return DISPLAY_VER(i915) >= 14 ? 3255 MTL_CHICKEN_TRANS(cpu_transcoder) : 3256 CHICKEN_TRANS(cpu_transcoder); 3257 } 3258 3259 static i915_reg_t 3260 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3261 enum port port) 3262 { 3263 static const enum transcoder trans[] = { 3264 [PORT_A] = TRANSCODER_EDP, 3265 [PORT_B] = TRANSCODER_A, 3266 [PORT_C] = TRANSCODER_B, 3267 [PORT_D] = TRANSCODER_C, 3268 [PORT_E] = TRANSCODER_A, 3269 }; 3270 3271 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3272 3273 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3274 port = PORT_A; 3275 3276 return CHICKEN_TRANS(trans[port]); 3277 } 3278 3279 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3280 struct intel_encoder *encoder, 3281 const struct intel_crtc_state *crtc_state, 3282 const struct drm_connector_state *conn_state) 3283 { 3284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3285 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3286 struct drm_connector *connector = conn_state->connector; 3287 enum port port = encoder->port; 3288 u32 buf_ctl; 3289 3290 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3291 crtc_state->hdmi_high_tmds_clock_ratio, 3292 crtc_state->hdmi_scrambling)) 3293 drm_dbg_kms(&dev_priv->drm, 3294 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3295 connector->base.id, connector->name); 3296 3297 if (has_buf_trans_select(dev_priv)) 3298 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3299 3300 /* e. Enable D2D Link for C10/C20 Phy */ 3301 if (DISPLAY_VER(dev_priv) >= 14) 3302 mtl_ddi_enable_d2d(encoder); 3303 3304 encoder->set_signal_levels(encoder, crtc_state); 3305 3306 /* Display WA #1143: skl,kbl,cfl */ 3307 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3308 /* 3309 * For some reason these chicken bits have been 3310 * stuffed into a transcoder register, event though 3311 * the bits affect a specific DDI port rather than 3312 * a specific transcoder. 3313 */ 3314 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3315 u32 val; 3316 3317 val = intel_de_read(dev_priv, reg); 3318 3319 if (port == PORT_E) 3320 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3321 DDIE_TRAINING_OVERRIDE_VALUE; 3322 else 3323 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3324 DDI_TRAINING_OVERRIDE_VALUE; 3325 3326 intel_de_write(dev_priv, reg, val); 3327 intel_de_posting_read(dev_priv, reg); 3328 3329 udelay(1); 3330 3331 if (port == PORT_E) 3332 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3333 DDIE_TRAINING_OVERRIDE_VALUE); 3334 else 3335 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3336 DDI_TRAINING_OVERRIDE_VALUE); 3337 3338 intel_de_write(dev_priv, reg, val); 3339 } 3340 3341 intel_ddi_power_up_lanes(encoder, crtc_state); 3342 3343 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3344 * are ignored so nothing special needs to be done besides 3345 * enabling the port. 3346 * 3347 * On ADL_P the PHY link rate and lane count must be programmed but 3348 * these are both 0 for HDMI. 3349 * 3350 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3351 * is filled with lane count, already set in the crtc_state. 3352 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3353 */ 3354 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3355 if (DISPLAY_VER(dev_priv) >= 14) { 3356 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3357 u32 port_buf = 0; 3358 3359 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3360 3361 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3362 port_buf |= XELPDP_PORT_REVERSAL; 3363 3364 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3365 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3366 3367 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3368 3369 if (DISPLAY_VER(dev_priv) >= 20) 3370 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3371 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3372 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3373 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3374 } 3375 3376 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3377 3378 intel_wait_ddi_buf_active(encoder); 3379 } 3380 3381 static void intel_enable_ddi(struct intel_atomic_state *state, 3382 struct intel_encoder *encoder, 3383 const struct intel_crtc_state *crtc_state, 3384 const struct drm_connector_state *conn_state) 3385 { 3386 struct intel_display *display = to_intel_display(encoder); 3387 struct intel_crtc *pipe_crtc; 3388 int i; 3389 3390 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3391 3392 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3393 intel_audio_sdp_split_update(crtc_state); 3394 3395 intel_enable_transcoder(crtc_state); 3396 3397 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3398 3399 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3400 const struct intel_crtc_state *pipe_crtc_state = 3401 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3402 3403 intel_crtc_vblank_on(pipe_crtc_state); 3404 } 3405 3406 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3407 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3408 else 3409 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3410 3411 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3412 3413 } 3414 3415 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3416 struct intel_encoder *encoder, 3417 const struct intel_crtc_state *old_crtc_state, 3418 const struct drm_connector_state *old_conn_state) 3419 { 3420 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3421 struct intel_connector *connector = 3422 to_intel_connector(old_conn_state->connector); 3423 3424 intel_dp->link_trained = false; 3425 3426 intel_psr_disable(intel_dp, old_crtc_state); 3427 intel_edp_backlight_off(old_conn_state); 3428 /* Disable the decompression in DP Sink */ 3429 intel_dp_sink_disable_decompression(state, 3430 connector, old_crtc_state); 3431 /* Disable Ignore_MSA bit in DP Sink */ 3432 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3433 false); 3434 } 3435 3436 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3437 struct intel_encoder *encoder, 3438 const struct intel_crtc_state *old_crtc_state, 3439 const struct drm_connector_state *old_conn_state) 3440 { 3441 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3442 struct drm_connector *connector = old_conn_state->connector; 3443 3444 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3445 false, false)) 3446 drm_dbg_kms(&i915->drm, 3447 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3448 connector->base.id, connector->name); 3449 } 3450 3451 static void intel_disable_ddi(struct intel_atomic_state *state, 3452 struct intel_encoder *encoder, 3453 const struct intel_crtc_state *old_crtc_state, 3454 const struct drm_connector_state *old_conn_state) 3455 { 3456 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3457 3458 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3459 3460 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3461 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3462 old_conn_state); 3463 else 3464 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3465 old_conn_state); 3466 } 3467 3468 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3469 struct intel_encoder *encoder, 3470 const struct intel_crtc_state *crtc_state, 3471 const struct drm_connector_state *conn_state) 3472 { 3473 intel_ddi_set_dp_msa(crtc_state, conn_state); 3474 3475 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3476 3477 intel_backlight_update(state, encoder, crtc_state, conn_state); 3478 drm_connector_update_privacy_screen(conn_state); 3479 } 3480 3481 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3482 struct intel_encoder *encoder, 3483 const struct intel_crtc_state *crtc_state, 3484 const struct drm_connector_state *conn_state) 3485 { 3486 3487 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3488 !intel_encoder_is_mst(encoder)) 3489 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3490 conn_state); 3491 3492 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3493 } 3494 3495 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3496 struct intel_encoder *encoder, 3497 struct intel_crtc *crtc) 3498 { 3499 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3500 const struct intel_crtc_state *crtc_state = 3501 intel_atomic_get_new_crtc_state(state, crtc); 3502 struct intel_crtc *pipe_crtc; 3503 3504 /* FIXME: Add MTL pll_mgr */ 3505 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3506 return; 3507 3508 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3509 intel_crtc_joined_pipe_mask(crtc_state)) 3510 intel_update_active_dpll(state, pipe_crtc, encoder); 3511 } 3512 3513 static void 3514 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3515 struct intel_encoder *encoder, 3516 const struct intel_crtc_state *crtc_state, 3517 const struct drm_connector_state *conn_state) 3518 { 3519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3520 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3521 bool is_tc_port = intel_encoder_is_tc(encoder); 3522 3523 if (is_tc_port) { 3524 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3525 3526 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3527 intel_ddi_update_active_dpll(state, encoder, crtc); 3528 } 3529 3530 main_link_aux_power_domain_get(dig_port, crtc_state); 3531 3532 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3533 /* 3534 * Program the lane count for static/dynamic connections on 3535 * Type-C ports. Skip this step for TBT. 3536 */ 3537 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3538 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3539 bxt_dpio_phy_set_lane_optim_mask(encoder, 3540 crtc_state->lane_lat_optim_mask); 3541 } 3542 3543 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3544 { 3545 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3546 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3547 int ln; 3548 3549 for (ln = 0; ln < 2; ln++) 3550 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3551 } 3552 3553 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3554 const struct intel_crtc_state *crtc_state) 3555 { 3556 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3557 struct intel_encoder *encoder = &dig_port->base; 3558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3559 enum port port = encoder->port; 3560 u32 dp_tp_ctl; 3561 3562 /* 3563 * TODO: To train with only a different voltage swing entry is not 3564 * necessary disable and enable port 3565 */ 3566 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3567 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3568 mtl_disable_ddi_buf(encoder, crtc_state); 3569 3570 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3571 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3572 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3573 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3574 } else { 3575 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3576 if (crtc_state->enhanced_framing) 3577 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3578 } 3579 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3580 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3581 3582 /* 6.f Enable D2D Link */ 3583 mtl_ddi_enable_d2d(encoder); 3584 3585 /* 6.g Configure voltage swing and related IO settings */ 3586 encoder->set_signal_levels(encoder, crtc_state); 3587 3588 /* 6.h Configure PORT_BUF_CTL1 */ 3589 mtl_port_buf_ctl_program(encoder, crtc_state); 3590 3591 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3592 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3593 if (DISPLAY_VER(dev_priv) >= 20) 3594 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3595 3596 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3597 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3598 3599 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3600 intel_wait_ddi_buf_active(encoder); 3601 } 3602 3603 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3604 const struct intel_crtc_state *crtc_state) 3605 { 3606 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3607 struct intel_encoder *encoder = &dig_port->base; 3608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3609 enum port port = encoder->port; 3610 u32 dp_tp_ctl, ddi_buf_ctl; 3611 bool wait = false; 3612 3613 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3614 3615 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3616 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3617 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3618 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3619 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3620 wait = true; 3621 } 3622 3623 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3624 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3625 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3626 3627 if (wait) 3628 intel_wait_ddi_buf_idle(dev_priv, port); 3629 } 3630 3631 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3632 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3633 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3634 } else { 3635 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3636 if (crtc_state->enhanced_framing) 3637 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3638 } 3639 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3640 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3641 3642 if (IS_ALDERLAKE_P(dev_priv) && 3643 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3644 adlp_tbt_to_dp_alt_switch_wa(encoder); 3645 3646 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3647 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3648 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3649 3650 intel_wait_ddi_buf_active(encoder); 3651 } 3652 3653 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3654 const struct intel_crtc_state *crtc_state, 3655 u8 dp_train_pat) 3656 { 3657 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3658 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3659 u32 temp; 3660 3661 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3662 3663 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3664 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3665 case DP_TRAINING_PATTERN_DISABLE: 3666 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3667 break; 3668 case DP_TRAINING_PATTERN_1: 3669 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3670 break; 3671 case DP_TRAINING_PATTERN_2: 3672 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3673 break; 3674 case DP_TRAINING_PATTERN_3: 3675 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3676 break; 3677 case DP_TRAINING_PATTERN_4: 3678 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3679 break; 3680 } 3681 3682 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3683 } 3684 3685 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3686 const struct intel_crtc_state *crtc_state) 3687 { 3688 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3689 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3690 enum port port = encoder->port; 3691 3692 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3693 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3694 3695 /* 3696 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3697 * reason we need to set idle transmission mode is to work around a HW 3698 * issue where we enable the pipe while not in idle link-training mode. 3699 * In this case there is requirement to wait for a minimum number of 3700 * idle patterns to be sent. 3701 */ 3702 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3703 return; 3704 3705 if (intel_de_wait_for_set(dev_priv, 3706 dp_tp_status_reg(encoder, crtc_state), 3707 DP_TP_STATUS_IDLE_DONE, 2)) 3708 drm_err(&dev_priv->drm, 3709 "Timed out waiting for DP idle patterns\n"); 3710 } 3711 3712 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3713 enum transcoder cpu_transcoder) 3714 { 3715 if (cpu_transcoder == TRANSCODER_EDP) 3716 return false; 3717 3718 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3719 return false; 3720 3721 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3722 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3723 } 3724 3725 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3726 { 3727 if (crtc_state->port_clock > 594000) 3728 return 2; 3729 else 3730 return 0; 3731 } 3732 3733 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3734 { 3735 if (crtc_state->port_clock > 594000) 3736 return 3; 3737 else 3738 return 0; 3739 } 3740 3741 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3742 { 3743 if (crtc_state->port_clock > 594000) 3744 return 1; 3745 else 3746 return 0; 3747 } 3748 3749 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3750 { 3751 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3752 3753 if (DISPLAY_VER(dev_priv) >= 14) 3754 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3755 else if (DISPLAY_VER(dev_priv) >= 12) 3756 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3757 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3758 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3759 else if (DISPLAY_VER(dev_priv) >= 11) 3760 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3761 } 3762 3763 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3764 enum transcoder cpu_transcoder) 3765 { 3766 u32 master_select; 3767 3768 if (DISPLAY_VER(dev_priv) >= 11) { 3769 u32 ctl2 = intel_de_read(dev_priv, 3770 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3771 3772 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3773 return INVALID_TRANSCODER; 3774 3775 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3776 } else { 3777 u32 ctl = intel_de_read(dev_priv, 3778 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3779 3780 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3781 return INVALID_TRANSCODER; 3782 3783 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3784 } 3785 3786 if (master_select == 0) 3787 return TRANSCODER_EDP; 3788 else 3789 return master_select - 1; 3790 } 3791 3792 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3793 { 3794 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3795 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3796 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3797 enum transcoder cpu_transcoder; 3798 3799 crtc_state->master_transcoder = 3800 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3801 3802 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3803 enum intel_display_power_domain power_domain; 3804 intel_wakeref_t trans_wakeref; 3805 3806 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3807 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3808 power_domain); 3809 3810 if (!trans_wakeref) 3811 continue; 3812 3813 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3814 crtc_state->cpu_transcoder) 3815 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3816 3817 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3818 } 3819 3820 drm_WARN_ON(&dev_priv->drm, 3821 crtc_state->master_transcoder != INVALID_TRANSCODER && 3822 crtc_state->sync_mode_slaves_mask); 3823 } 3824 3825 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3826 struct intel_crtc_state *pipe_config) 3827 { 3828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3829 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3830 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3831 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3832 u32 temp, flags = 0; 3833 3834 temp = intel_de_read(dev_priv, 3835 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3836 if (temp & TRANS_DDI_PHSYNC) 3837 flags |= DRM_MODE_FLAG_PHSYNC; 3838 else 3839 flags |= DRM_MODE_FLAG_NHSYNC; 3840 if (temp & TRANS_DDI_PVSYNC) 3841 flags |= DRM_MODE_FLAG_PVSYNC; 3842 else 3843 flags |= DRM_MODE_FLAG_NVSYNC; 3844 3845 pipe_config->hw.adjusted_mode.flags |= flags; 3846 3847 switch (temp & TRANS_DDI_BPC_MASK) { 3848 case TRANS_DDI_BPC_6: 3849 pipe_config->pipe_bpp = 18; 3850 break; 3851 case TRANS_DDI_BPC_8: 3852 pipe_config->pipe_bpp = 24; 3853 break; 3854 case TRANS_DDI_BPC_10: 3855 pipe_config->pipe_bpp = 30; 3856 break; 3857 case TRANS_DDI_BPC_12: 3858 pipe_config->pipe_bpp = 36; 3859 break; 3860 default: 3861 break; 3862 } 3863 3864 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3865 case TRANS_DDI_MODE_SELECT_HDMI: 3866 pipe_config->has_hdmi_sink = true; 3867 3868 pipe_config->infoframes.enable |= 3869 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3870 3871 if (pipe_config->infoframes.enable) 3872 pipe_config->has_infoframe = true; 3873 3874 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3875 pipe_config->hdmi_scrambling = true; 3876 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3877 pipe_config->hdmi_high_tmds_clock_ratio = true; 3878 fallthrough; 3879 case TRANS_DDI_MODE_SELECT_DVI: 3880 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3881 if (DISPLAY_VER(dev_priv) >= 14) 3882 pipe_config->lane_count = 3883 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3884 else 3885 pipe_config->lane_count = 4; 3886 break; 3887 case TRANS_DDI_MODE_SELECT_DP_SST: 3888 if (encoder->type == INTEL_OUTPUT_EDP) 3889 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3890 else 3891 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3892 pipe_config->lane_count = 3893 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3894 3895 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3896 &pipe_config->dp_m_n); 3897 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3898 &pipe_config->dp_m2_n2); 3899 3900 pipe_config->enhanced_framing = 3901 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3902 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3903 3904 if (DISPLAY_VER(dev_priv) >= 11) 3905 pipe_config->fec_enable = 3906 intel_de_read(dev_priv, 3907 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3908 3909 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3910 pipe_config->infoframes.enable |= 3911 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3912 else 3913 pipe_config->infoframes.enable |= 3914 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3915 break; 3916 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3917 if (!HAS_DP20(dev_priv)) { 3918 /* FDI */ 3919 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3920 pipe_config->enhanced_framing = 3921 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3922 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3923 break; 3924 } 3925 fallthrough; /* 128b/132b */ 3926 case TRANS_DDI_MODE_SELECT_DP_MST: 3927 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3928 pipe_config->lane_count = 3929 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3930 3931 if (DISPLAY_VER(dev_priv) >= 12) 3932 pipe_config->mst_master_transcoder = 3933 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3934 3935 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3936 &pipe_config->dp_m_n); 3937 3938 if (DISPLAY_VER(dev_priv) >= 11) 3939 pipe_config->fec_enable = 3940 intel_de_read(dev_priv, 3941 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3942 3943 pipe_config->infoframes.enable |= 3944 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3945 break; 3946 default: 3947 break; 3948 } 3949 } 3950 3951 static void intel_ddi_get_config(struct intel_encoder *encoder, 3952 struct intel_crtc_state *pipe_config) 3953 { 3954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3955 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3956 3957 /* XXX: DSI transcoder paranoia */ 3958 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3959 return; 3960 3961 intel_ddi_read_func_ctl(encoder, pipe_config); 3962 3963 intel_ddi_mso_get_config(encoder, pipe_config); 3964 3965 pipe_config->has_audio = 3966 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3967 3968 if (encoder->type == INTEL_OUTPUT_EDP) 3969 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3970 3971 ddi_dotclock_get(pipe_config); 3972 3973 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3974 pipe_config->lane_lat_optim_mask = 3975 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 3976 3977 intel_ddi_compute_min_voltage_level(pipe_config); 3978 3979 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3980 3981 intel_read_infoframe(encoder, pipe_config, 3982 HDMI_INFOFRAME_TYPE_AVI, 3983 &pipe_config->infoframes.avi); 3984 intel_read_infoframe(encoder, pipe_config, 3985 HDMI_INFOFRAME_TYPE_SPD, 3986 &pipe_config->infoframes.spd); 3987 intel_read_infoframe(encoder, pipe_config, 3988 HDMI_INFOFRAME_TYPE_VENDOR, 3989 &pipe_config->infoframes.hdmi); 3990 intel_read_infoframe(encoder, pipe_config, 3991 HDMI_INFOFRAME_TYPE_DRM, 3992 &pipe_config->infoframes.drm); 3993 3994 if (DISPLAY_VER(dev_priv) >= 8) 3995 bdw_get_trans_port_sync_config(pipe_config); 3996 3997 intel_psr_get_config(encoder, pipe_config); 3998 3999 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4000 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4001 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4002 4003 intel_audio_codec_get_config(encoder, pipe_config); 4004 } 4005 4006 void intel_ddi_get_clock(struct intel_encoder *encoder, 4007 struct intel_crtc_state *crtc_state, 4008 struct intel_shared_dpll *pll) 4009 { 4010 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4011 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4012 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4013 bool pll_active; 4014 4015 if (drm_WARN_ON(&i915->drm, !pll)) 4016 return; 4017 4018 port_dpll->pll = pll; 4019 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4020 drm_WARN_ON(&i915->drm, !pll_active); 4021 4022 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4023 4024 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4025 &crtc_state->dpll_hw_state); 4026 } 4027 4028 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4029 struct intel_crtc_state *crtc_state) 4030 { 4031 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4032 4033 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4034 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4035 else 4036 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4037 4038 intel_ddi_get_config(encoder, crtc_state); 4039 } 4040 4041 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4042 struct intel_crtc_state *crtc_state) 4043 { 4044 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4045 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4046 4047 intel_ddi_get_config(encoder, crtc_state); 4048 } 4049 4050 static void adls_ddi_get_config(struct intel_encoder *encoder, 4051 struct intel_crtc_state *crtc_state) 4052 { 4053 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4054 intel_ddi_get_config(encoder, crtc_state); 4055 } 4056 4057 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4058 struct intel_crtc_state *crtc_state) 4059 { 4060 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4061 intel_ddi_get_config(encoder, crtc_state); 4062 } 4063 4064 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4065 struct intel_crtc_state *crtc_state) 4066 { 4067 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4068 intel_ddi_get_config(encoder, crtc_state); 4069 } 4070 4071 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4072 struct intel_crtc_state *crtc_state) 4073 { 4074 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4075 intel_ddi_get_config(encoder, crtc_state); 4076 } 4077 4078 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4079 { 4080 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4081 } 4082 4083 static enum icl_port_dpll_id 4084 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4085 const struct intel_crtc_state *crtc_state) 4086 { 4087 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4088 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4089 4090 if (drm_WARN_ON(&i915->drm, !pll)) 4091 return ICL_PORT_DPLL_DEFAULT; 4092 4093 if (icl_ddi_tc_pll_is_tbt(pll)) 4094 return ICL_PORT_DPLL_DEFAULT; 4095 else 4096 return ICL_PORT_DPLL_MG_PHY; 4097 } 4098 4099 enum icl_port_dpll_id 4100 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4101 const struct intel_crtc_state *crtc_state) 4102 { 4103 if (!encoder->port_pll_type) 4104 return ICL_PORT_DPLL_DEFAULT; 4105 4106 return encoder->port_pll_type(encoder, crtc_state); 4107 } 4108 4109 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4110 struct intel_crtc_state *crtc_state, 4111 struct intel_shared_dpll *pll) 4112 { 4113 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4114 enum icl_port_dpll_id port_dpll_id; 4115 struct icl_port_dpll *port_dpll; 4116 bool pll_active; 4117 4118 if (drm_WARN_ON(&i915->drm, !pll)) 4119 return; 4120 4121 if (icl_ddi_tc_pll_is_tbt(pll)) 4122 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4123 else 4124 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4125 4126 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4127 4128 port_dpll->pll = pll; 4129 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4130 drm_WARN_ON(&i915->drm, !pll_active); 4131 4132 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4133 4134 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4135 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4136 else 4137 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4138 &crtc_state->dpll_hw_state); 4139 } 4140 4141 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4142 struct intel_crtc_state *crtc_state) 4143 { 4144 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4145 intel_ddi_get_config(encoder, crtc_state); 4146 } 4147 4148 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4149 struct intel_crtc_state *crtc_state) 4150 { 4151 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4152 intel_ddi_get_config(encoder, crtc_state); 4153 } 4154 4155 static void skl_ddi_get_config(struct intel_encoder *encoder, 4156 struct intel_crtc_state *crtc_state) 4157 { 4158 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4159 intel_ddi_get_config(encoder, crtc_state); 4160 } 4161 4162 void hsw_ddi_get_config(struct intel_encoder *encoder, 4163 struct intel_crtc_state *crtc_state) 4164 { 4165 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4166 intel_ddi_get_config(encoder, crtc_state); 4167 } 4168 4169 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4170 const struct intel_crtc_state *crtc_state) 4171 { 4172 if (intel_encoder_is_tc(encoder)) 4173 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4174 crtc_state); 4175 4176 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4177 (!crtc_state && intel_encoder_is_dp(encoder))) 4178 intel_dp_sync_state(encoder, crtc_state); 4179 } 4180 4181 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4182 struct intel_crtc_state *crtc_state) 4183 { 4184 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4185 bool fastset = true; 4186 4187 if (intel_encoder_is_tc(encoder)) { 4188 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4189 encoder->base.base.id, encoder->base.name); 4190 crtc_state->uapi.mode_changed = true; 4191 fastset = false; 4192 } 4193 4194 if (intel_crtc_has_dp_encoder(crtc_state) && 4195 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4196 fastset = false; 4197 4198 return fastset; 4199 } 4200 4201 static enum intel_output_type 4202 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4203 struct intel_crtc_state *crtc_state, 4204 struct drm_connector_state *conn_state) 4205 { 4206 switch (conn_state->connector->connector_type) { 4207 case DRM_MODE_CONNECTOR_HDMIA: 4208 return INTEL_OUTPUT_HDMI; 4209 case DRM_MODE_CONNECTOR_eDP: 4210 return INTEL_OUTPUT_EDP; 4211 case DRM_MODE_CONNECTOR_DisplayPort: 4212 return INTEL_OUTPUT_DP; 4213 default: 4214 MISSING_CASE(conn_state->connector->connector_type); 4215 return INTEL_OUTPUT_UNUSED; 4216 } 4217 } 4218 4219 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4220 struct intel_crtc_state *pipe_config, 4221 struct drm_connector_state *conn_state) 4222 { 4223 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4225 enum port port = encoder->port; 4226 int ret; 4227 4228 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4229 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4230 4231 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4232 pipe_config->has_hdmi_sink = 4233 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4234 4235 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4236 } else { 4237 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4238 } 4239 4240 if (ret) 4241 return ret; 4242 4243 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4244 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4245 pipe_config->pch_pfit.force_thru = 4246 pipe_config->pch_pfit.enabled || 4247 pipe_config->crc_enabled; 4248 4249 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4250 pipe_config->lane_lat_optim_mask = 4251 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4252 4253 intel_ddi_compute_min_voltage_level(pipe_config); 4254 4255 return 0; 4256 } 4257 4258 static bool mode_equal(const struct drm_display_mode *mode1, 4259 const struct drm_display_mode *mode2) 4260 { 4261 return drm_mode_match(mode1, mode2, 4262 DRM_MODE_MATCH_TIMINGS | 4263 DRM_MODE_MATCH_FLAGS | 4264 DRM_MODE_MATCH_3D_FLAGS) && 4265 mode1->clock == mode2->clock; /* we want an exact match */ 4266 } 4267 4268 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4269 const struct intel_link_m_n *m_n_2) 4270 { 4271 return m_n_1->tu == m_n_2->tu && 4272 m_n_1->data_m == m_n_2->data_m && 4273 m_n_1->data_n == m_n_2->data_n && 4274 m_n_1->link_m == m_n_2->link_m && 4275 m_n_1->link_n == m_n_2->link_n; 4276 } 4277 4278 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4279 const struct intel_crtc_state *crtc_state2) 4280 { 4281 /* 4282 * FIXME the modeset sequence is currently wrong and 4283 * can't deal with joiner + port sync at the same time. 4284 */ 4285 return crtc_state1->hw.active && crtc_state2->hw.active && 4286 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4287 crtc_state1->output_types == crtc_state2->output_types && 4288 crtc_state1->output_format == crtc_state2->output_format && 4289 crtc_state1->lane_count == crtc_state2->lane_count && 4290 crtc_state1->port_clock == crtc_state2->port_clock && 4291 mode_equal(&crtc_state1->hw.adjusted_mode, 4292 &crtc_state2->hw.adjusted_mode) && 4293 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4294 } 4295 4296 static u8 4297 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4298 int tile_group_id) 4299 { 4300 struct drm_connector *connector; 4301 const struct drm_connector_state *conn_state; 4302 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4303 struct intel_atomic_state *state = 4304 to_intel_atomic_state(ref_crtc_state->uapi.state); 4305 u8 transcoders = 0; 4306 int i; 4307 4308 /* 4309 * We don't enable port sync on BDW due to missing w/as and 4310 * due to not having adjusted the modeset sequence appropriately. 4311 */ 4312 if (DISPLAY_VER(dev_priv) < 9) 4313 return 0; 4314 4315 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4316 return 0; 4317 4318 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4319 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4320 const struct intel_crtc_state *crtc_state; 4321 4322 if (!crtc) 4323 continue; 4324 4325 if (!connector->has_tile || 4326 connector->tile_group->id != 4327 tile_group_id) 4328 continue; 4329 crtc_state = intel_atomic_get_new_crtc_state(state, 4330 crtc); 4331 if (!crtcs_port_sync_compatible(ref_crtc_state, 4332 crtc_state)) 4333 continue; 4334 transcoders |= BIT(crtc_state->cpu_transcoder); 4335 } 4336 4337 return transcoders; 4338 } 4339 4340 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4341 struct intel_crtc_state *crtc_state, 4342 struct drm_connector_state *conn_state) 4343 { 4344 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4345 struct drm_connector *connector = conn_state->connector; 4346 u8 port_sync_transcoders = 0; 4347 4348 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4349 encoder->base.base.id, encoder->base.name, 4350 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4351 4352 if (connector->has_tile) 4353 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4354 connector->tile_group->id); 4355 4356 /* 4357 * EDP Transcoders cannot be ensalved 4358 * make them a master always when present 4359 */ 4360 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4361 crtc_state->master_transcoder = TRANSCODER_EDP; 4362 else 4363 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4364 4365 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4366 crtc_state->master_transcoder = INVALID_TRANSCODER; 4367 crtc_state->sync_mode_slaves_mask = 4368 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4369 } 4370 4371 return 0; 4372 } 4373 4374 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4375 { 4376 struct drm_i915_private *i915 = to_i915(encoder->dev); 4377 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4378 4379 intel_dp_encoder_flush_work(encoder); 4380 if (intel_encoder_is_tc(&dig_port->base)) 4381 intel_tc_port_cleanup(dig_port); 4382 intel_display_power_flush_work(i915); 4383 4384 drm_encoder_cleanup(encoder); 4385 kfree(dig_port->hdcp_port_data.streams); 4386 kfree(dig_port); 4387 } 4388 4389 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4390 { 4391 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4392 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4393 4394 intel_dp->reset_link_params = true; 4395 4396 intel_pps_encoder_reset(intel_dp); 4397 4398 if (intel_encoder_is_tc(&dig_port->base)) 4399 intel_tc_port_init_mode(dig_port); 4400 } 4401 4402 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4403 { 4404 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4405 4406 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4407 4408 return 0; 4409 } 4410 4411 static const struct drm_encoder_funcs intel_ddi_funcs = { 4412 .reset = intel_ddi_encoder_reset, 4413 .destroy = intel_ddi_encoder_destroy, 4414 .late_register = intel_ddi_encoder_late_register, 4415 }; 4416 4417 static struct intel_connector * 4418 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4419 { 4420 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4421 struct intel_connector *connector; 4422 enum port port = dig_port->base.port; 4423 4424 connector = intel_connector_alloc(); 4425 if (!connector) 4426 return NULL; 4427 4428 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4429 if (DISPLAY_VER(i915) >= 14) 4430 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4431 else 4432 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4433 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4434 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4435 4436 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4437 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4438 4439 if (!intel_dp_init_connector(dig_port, connector)) { 4440 kfree(connector); 4441 return NULL; 4442 } 4443 4444 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4445 struct drm_device *dev = dig_port->base.base.dev; 4446 struct drm_privacy_screen *privacy_screen; 4447 4448 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4449 if (!IS_ERR(privacy_screen)) { 4450 drm_connector_attach_privacy_screen_provider(&connector->base, 4451 privacy_screen); 4452 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4453 drm_warn(dev, "Error getting privacy-screen\n"); 4454 } 4455 } 4456 4457 return connector; 4458 } 4459 4460 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4461 struct drm_modeset_acquire_ctx *ctx) 4462 { 4463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4464 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4465 struct intel_connector *connector = hdmi->attached_connector; 4466 struct i2c_adapter *ddc = connector->base.ddc; 4467 struct drm_connector_state *conn_state; 4468 struct intel_crtc_state *crtc_state; 4469 struct intel_crtc *crtc; 4470 u8 config; 4471 int ret; 4472 4473 if (connector->base.status != connector_status_connected) 4474 return 0; 4475 4476 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4477 ctx); 4478 if (ret) 4479 return ret; 4480 4481 conn_state = connector->base.state; 4482 4483 crtc = to_intel_crtc(conn_state->crtc); 4484 if (!crtc) 4485 return 0; 4486 4487 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4488 if (ret) 4489 return ret; 4490 4491 crtc_state = to_intel_crtc_state(crtc->base.state); 4492 4493 drm_WARN_ON(&dev_priv->drm, 4494 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4495 4496 if (!crtc_state->hw.active) 4497 return 0; 4498 4499 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4500 !crtc_state->hdmi_scrambling) 4501 return 0; 4502 4503 if (conn_state->commit && 4504 !try_wait_for_completion(&conn_state->commit->hw_done)) 4505 return 0; 4506 4507 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4508 if (ret < 0) { 4509 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4510 connector->base.base.id, connector->base.name, ret); 4511 return 0; 4512 } 4513 4514 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4515 crtc_state->hdmi_high_tmds_clock_ratio && 4516 !!(config & SCDC_SCRAMBLING_ENABLE) == 4517 crtc_state->hdmi_scrambling) 4518 return 0; 4519 4520 /* 4521 * HDMI 2.0 says that one should not send scrambled data 4522 * prior to configuring the sink scrambling, and that 4523 * TMDS clock/data transmission should be suspended when 4524 * changing the TMDS clock rate in the sink. So let's 4525 * just do a full modeset here, even though some sinks 4526 * would be perfectly happy if were to just reconfigure 4527 * the SCDC settings on the fly. 4528 */ 4529 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4530 } 4531 4532 static void intel_ddi_link_check(struct intel_encoder *encoder) 4533 { 4534 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4535 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4536 4537 /* TODO: Move checking the HDMI link state here as well. */ 4538 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4539 4540 intel_dp_link_check(encoder); 4541 } 4542 4543 static enum intel_hotplug_state 4544 intel_ddi_hotplug(struct intel_encoder *encoder, 4545 struct intel_connector *connector) 4546 { 4547 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4548 struct intel_dp *intel_dp = &dig_port->dp; 4549 bool is_tc = intel_encoder_is_tc(encoder); 4550 struct drm_modeset_acquire_ctx ctx; 4551 enum intel_hotplug_state state; 4552 int ret; 4553 4554 if (intel_dp_test_phy(intel_dp)) 4555 return INTEL_HOTPLUG_UNCHANGED; 4556 4557 state = intel_encoder_hotplug(encoder, connector); 4558 4559 if (!intel_tc_port_link_reset(dig_port)) { 4560 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4561 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4562 ret = intel_hdmi_reset_link(encoder, &ctx); 4563 drm_WARN_ON(encoder->base.dev, ret); 4564 } else { 4565 intel_dp_check_link_state(intel_dp); 4566 } 4567 } 4568 4569 /* 4570 * Unpowered type-c dongles can take some time to boot and be 4571 * responsible, so here giving some time to those dongles to power up 4572 * and then retrying the probe. 4573 * 4574 * On many platforms the HDMI live state signal is known to be 4575 * unreliable, so we can't use it to detect if a sink is connected or 4576 * not. Instead we detect if it's connected based on whether we can 4577 * read the EDID or not. That in turn has a problem during disconnect, 4578 * since the HPD interrupt may be raised before the DDC lines get 4579 * disconnected (due to how the required length of DDC vs. HPD 4580 * connector pins are specified) and so we'll still be able to get a 4581 * valid EDID. To solve this schedule another detection cycle if this 4582 * time around we didn't detect any change in the sink's connection 4583 * status. 4584 * 4585 * Type-c connectors which get their HPD signal deasserted then 4586 * reasserted, without unplugging/replugging the sink from the 4587 * connector, introduce a delay until the AUX channel communication 4588 * becomes functional. Retry the detection for 5 seconds on type-c 4589 * connectors to account for this delay. 4590 */ 4591 if (state == INTEL_HOTPLUG_UNCHANGED && 4592 connector->hotplug_retries < (is_tc ? 5 : 1) && 4593 !dig_port->dp.is_mst) 4594 state = INTEL_HOTPLUG_RETRY; 4595 4596 return state; 4597 } 4598 4599 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4600 { 4601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4602 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4603 4604 return intel_de_read(dev_priv, SDEISR) & bit; 4605 } 4606 4607 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4608 { 4609 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4610 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4611 4612 return intel_de_read(dev_priv, DEISR) & bit; 4613 } 4614 4615 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4616 { 4617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4618 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4619 4620 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4621 } 4622 4623 static struct intel_connector * 4624 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4625 { 4626 struct intel_connector *connector; 4627 enum port port = dig_port->base.port; 4628 4629 connector = intel_connector_alloc(); 4630 if (!connector) 4631 return NULL; 4632 4633 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4634 intel_hdmi_init_connector(dig_port, connector); 4635 4636 return connector; 4637 } 4638 4639 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4640 { 4641 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4642 4643 if (dig_port->base.port != PORT_A) 4644 return false; 4645 4646 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4647 return false; 4648 4649 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4650 * supported configuration 4651 */ 4652 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4653 return true; 4654 4655 return false; 4656 } 4657 4658 static int 4659 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4660 { 4661 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4662 enum port port = dig_port->base.port; 4663 int max_lanes = 4; 4664 4665 if (DISPLAY_VER(dev_priv) >= 11) 4666 return max_lanes; 4667 4668 if (port == PORT_A || port == PORT_E) { 4669 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4670 max_lanes = port == PORT_A ? 4 : 0; 4671 else 4672 /* Both A and E share 2 lanes */ 4673 max_lanes = 2; 4674 } 4675 4676 /* 4677 * Some BIOS might fail to set this bit on port A if eDP 4678 * wasn't lit up at boot. Force this bit set when needed 4679 * so we use the proper lane count for our calculations. 4680 */ 4681 if (intel_ddi_a_force_4_lanes(dig_port)) { 4682 drm_dbg_kms(&dev_priv->drm, 4683 "Forcing DDI_A_4_LANES for port A\n"); 4684 dig_port->saved_port_bits |= DDI_A_4_LANES; 4685 max_lanes = 4; 4686 } 4687 4688 return max_lanes; 4689 } 4690 4691 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4692 enum port port) 4693 { 4694 if (port >= PORT_D_XELPD) 4695 return HPD_PORT_D + port - PORT_D_XELPD; 4696 else if (port >= PORT_TC1) 4697 return HPD_PORT_TC1 + port - PORT_TC1; 4698 else 4699 return HPD_PORT_A + port - PORT_A; 4700 } 4701 4702 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4703 enum port port) 4704 { 4705 if (port >= PORT_TC1) 4706 return HPD_PORT_C + port - PORT_TC1; 4707 else 4708 return HPD_PORT_A + port - PORT_A; 4709 } 4710 4711 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4712 enum port port) 4713 { 4714 if (port >= PORT_TC1) 4715 return HPD_PORT_TC1 + port - PORT_TC1; 4716 else 4717 return HPD_PORT_A + port - PORT_A; 4718 } 4719 4720 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4721 enum port port) 4722 { 4723 if (HAS_PCH_TGP(dev_priv)) 4724 return tgl_hpd_pin(dev_priv, port); 4725 4726 if (port >= PORT_TC1) 4727 return HPD_PORT_C + port - PORT_TC1; 4728 else 4729 return HPD_PORT_A + port - PORT_A; 4730 } 4731 4732 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4733 enum port port) 4734 { 4735 if (port >= PORT_C) 4736 return HPD_PORT_TC1 + port - PORT_C; 4737 else 4738 return HPD_PORT_A + port - PORT_A; 4739 } 4740 4741 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4742 enum port port) 4743 { 4744 if (port == PORT_D) 4745 return HPD_PORT_A; 4746 4747 if (HAS_PCH_TGP(dev_priv)) 4748 return icl_hpd_pin(dev_priv, port); 4749 4750 return HPD_PORT_A + port - PORT_A; 4751 } 4752 4753 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4754 { 4755 if (HAS_PCH_TGP(dev_priv)) 4756 return icl_hpd_pin(dev_priv, port); 4757 4758 return HPD_PORT_A + port - PORT_A; 4759 } 4760 4761 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4762 { 4763 if (DISPLAY_VER(i915) >= 12) 4764 return port >= PORT_TC1; 4765 else if (DISPLAY_VER(i915) >= 11) 4766 return port >= PORT_C; 4767 else 4768 return false; 4769 } 4770 4771 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4772 { 4773 intel_dp_encoder_suspend(encoder); 4774 } 4775 4776 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4777 { 4778 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4779 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4780 4781 /* 4782 * TODO: Move this to intel_dp_encoder_suspend(), 4783 * once modeset locking around that is removed. 4784 */ 4785 intel_encoder_link_check_flush_work(encoder); 4786 intel_tc_port_suspend(dig_port); 4787 } 4788 4789 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4790 { 4791 intel_dp_encoder_shutdown(encoder); 4792 intel_hdmi_encoder_shutdown(encoder); 4793 } 4794 4795 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4796 { 4797 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4798 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4799 4800 intel_tc_port_cleanup(dig_port); 4801 } 4802 4803 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4804 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4805 4806 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4807 { 4808 /* straps not used on skl+ */ 4809 if (DISPLAY_VER(i915) >= 9) 4810 return true; 4811 4812 switch (port) { 4813 case PORT_A: 4814 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4815 case PORT_B: 4816 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4817 case PORT_C: 4818 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4819 case PORT_D: 4820 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4821 case PORT_E: 4822 return true; /* no strap for DDI-E */ 4823 default: 4824 MISSING_CASE(port); 4825 return false; 4826 } 4827 } 4828 4829 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4830 { 4831 return init_dp || intel_encoder_is_tc(encoder); 4832 } 4833 4834 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4835 { 4836 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4837 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4838 "Platform does not support DSI\n"); 4839 } 4840 4841 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4842 { 4843 struct intel_encoder *encoder; 4844 4845 for_each_intel_encoder(&i915->drm, encoder) { 4846 /* FIXME what about second port for dual link DSI? */ 4847 if (encoder->port == port) 4848 return true; 4849 } 4850 4851 return false; 4852 } 4853 4854 void intel_ddi_init(struct intel_display *display, 4855 const struct intel_bios_encoder_data *devdata) 4856 { 4857 struct drm_i915_private *dev_priv = to_i915(display->drm); 4858 struct intel_digital_port *dig_port; 4859 struct intel_encoder *encoder; 4860 bool init_hdmi, init_dp; 4861 enum port port; 4862 enum phy phy; 4863 4864 port = intel_bios_encoder_port(devdata); 4865 if (port == PORT_NONE) 4866 return; 4867 4868 if (!port_strap_detected(dev_priv, port)) { 4869 drm_dbg_kms(&dev_priv->drm, 4870 "Port %c strap not detected\n", port_name(port)); 4871 return; 4872 } 4873 4874 if (!assert_port_valid(dev_priv, port)) 4875 return; 4876 4877 if (port_in_use(dev_priv, port)) { 4878 drm_dbg_kms(&dev_priv->drm, 4879 "Port %c already claimed\n", port_name(port)); 4880 return; 4881 } 4882 4883 if (intel_bios_encoder_supports_dsi(devdata)) { 4884 /* BXT/GLK handled elsewhere, for now at least */ 4885 if (!assert_has_icl_dsi(dev_priv)) 4886 return; 4887 4888 icl_dsi_init(dev_priv, devdata); 4889 return; 4890 } 4891 4892 phy = intel_port_to_phy(dev_priv, port); 4893 4894 /* 4895 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4896 * have taken over some of the PHYs and made them unavailable to the 4897 * driver. In that case we should skip initializing the corresponding 4898 * outputs. 4899 */ 4900 if (intel_hti_uses_phy(display, phy)) { 4901 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4902 port_name(port), phy_name(phy)); 4903 return; 4904 } 4905 4906 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4907 intel_bios_encoder_supports_hdmi(devdata); 4908 init_dp = intel_bios_encoder_supports_dp(devdata); 4909 4910 if (intel_bios_encoder_is_lspcon(devdata)) { 4911 /* 4912 * Lspcon device needs to be driven with DP connector 4913 * with special detection sequence. So make sure DP 4914 * is initialized before lspcon. 4915 */ 4916 init_dp = true; 4917 init_hdmi = false; 4918 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4919 port_name(port)); 4920 } 4921 4922 if (!init_dp && !init_hdmi) { 4923 drm_dbg_kms(&dev_priv->drm, 4924 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4925 port_name(port)); 4926 return; 4927 } 4928 4929 if (intel_phy_is_snps(dev_priv, phy) && 4930 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4931 drm_dbg_kms(&dev_priv->drm, 4932 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4933 phy_name(phy)); 4934 } 4935 4936 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4937 if (!dig_port) 4938 return; 4939 4940 dig_port->aux_ch = AUX_CH_NONE; 4941 4942 encoder = &dig_port->base; 4943 encoder->devdata = devdata; 4944 4945 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4946 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4947 DRM_MODE_ENCODER_TMDS, 4948 "DDI %c/PHY %c", 4949 port_name(port - PORT_D_XELPD + PORT_D), 4950 phy_name(phy)); 4951 } else if (DISPLAY_VER(dev_priv) >= 12) { 4952 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4953 4954 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4955 DRM_MODE_ENCODER_TMDS, 4956 "DDI %s%c/PHY %s%c", 4957 port >= PORT_TC1 ? "TC" : "", 4958 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4959 tc_port != TC_PORT_NONE ? "TC" : "", 4960 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4961 } else if (DISPLAY_VER(dev_priv) >= 11) { 4962 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4963 4964 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4965 DRM_MODE_ENCODER_TMDS, 4966 "DDI %c%s/PHY %s%c", 4967 port_name(port), 4968 port >= PORT_C ? " (TC)" : "", 4969 tc_port != TC_PORT_NONE ? "TC" : "", 4970 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4971 } else { 4972 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4973 DRM_MODE_ENCODER_TMDS, 4974 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4975 } 4976 4977 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 4978 4979 mutex_init(&dig_port->hdcp_mutex); 4980 dig_port->num_hdcp_streams = 0; 4981 4982 encoder->hotplug = intel_ddi_hotplug; 4983 encoder->compute_output_type = intel_ddi_compute_output_type; 4984 encoder->compute_config = intel_ddi_compute_config; 4985 encoder->compute_config_late = intel_ddi_compute_config_late; 4986 encoder->enable = intel_enable_ddi; 4987 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4988 encoder->pre_enable = intel_ddi_pre_enable; 4989 encoder->disable = intel_disable_ddi; 4990 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4991 encoder->post_disable = intel_ddi_post_disable; 4992 encoder->update_pipe = intel_ddi_update_pipe; 4993 encoder->audio_enable = intel_audio_codec_enable; 4994 encoder->audio_disable = intel_audio_codec_disable; 4995 encoder->get_hw_state = intel_ddi_get_hw_state; 4996 encoder->sync_state = intel_ddi_sync_state; 4997 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4998 encoder->suspend = intel_ddi_encoder_suspend; 4999 encoder->shutdown = intel_ddi_encoder_shutdown; 5000 encoder->get_power_domains = intel_ddi_get_power_domains; 5001 5002 encoder->type = INTEL_OUTPUT_DDI; 5003 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5004 encoder->port = port; 5005 encoder->cloneable = 0; 5006 encoder->pipe_mask = ~0; 5007 5008 if (DISPLAY_VER(dev_priv) >= 14) { 5009 encoder->enable_clock = intel_mtl_pll_enable; 5010 encoder->disable_clock = intel_mtl_pll_disable; 5011 encoder->port_pll_type = intel_mtl_port_pll_type; 5012 encoder->get_config = mtl_ddi_get_config; 5013 } else if (IS_DG2(dev_priv)) { 5014 encoder->enable_clock = intel_mpllb_enable; 5015 encoder->disable_clock = intel_mpllb_disable; 5016 encoder->get_config = dg2_ddi_get_config; 5017 } else if (IS_ALDERLAKE_S(dev_priv)) { 5018 encoder->enable_clock = adls_ddi_enable_clock; 5019 encoder->disable_clock = adls_ddi_disable_clock; 5020 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5021 encoder->get_config = adls_ddi_get_config; 5022 } else if (IS_ROCKETLAKE(dev_priv)) { 5023 encoder->enable_clock = rkl_ddi_enable_clock; 5024 encoder->disable_clock = rkl_ddi_disable_clock; 5025 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5026 encoder->get_config = rkl_ddi_get_config; 5027 } else if (IS_DG1(dev_priv)) { 5028 encoder->enable_clock = dg1_ddi_enable_clock; 5029 encoder->disable_clock = dg1_ddi_disable_clock; 5030 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5031 encoder->get_config = dg1_ddi_get_config; 5032 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5033 if (intel_ddi_is_tc(dev_priv, port)) { 5034 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5035 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5036 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5037 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5038 encoder->get_config = icl_ddi_combo_get_config; 5039 } else { 5040 encoder->enable_clock = icl_ddi_combo_enable_clock; 5041 encoder->disable_clock = icl_ddi_combo_disable_clock; 5042 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5043 encoder->get_config = icl_ddi_combo_get_config; 5044 } 5045 } else if (DISPLAY_VER(dev_priv) >= 11) { 5046 if (intel_ddi_is_tc(dev_priv, port)) { 5047 encoder->enable_clock = icl_ddi_tc_enable_clock; 5048 encoder->disable_clock = icl_ddi_tc_disable_clock; 5049 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5050 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5051 encoder->get_config = icl_ddi_tc_get_config; 5052 } else { 5053 encoder->enable_clock = icl_ddi_combo_enable_clock; 5054 encoder->disable_clock = icl_ddi_combo_disable_clock; 5055 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5056 encoder->get_config = icl_ddi_combo_get_config; 5057 } 5058 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5059 /* BXT/GLK have fixed PLL->port mapping */ 5060 encoder->get_config = bxt_ddi_get_config; 5061 } else if (DISPLAY_VER(dev_priv) == 9) { 5062 encoder->enable_clock = skl_ddi_enable_clock; 5063 encoder->disable_clock = skl_ddi_disable_clock; 5064 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5065 encoder->get_config = skl_ddi_get_config; 5066 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5067 encoder->enable_clock = hsw_ddi_enable_clock; 5068 encoder->disable_clock = hsw_ddi_disable_clock; 5069 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5070 encoder->get_config = hsw_ddi_get_config; 5071 } 5072 5073 if (DISPLAY_VER(dev_priv) >= 14) { 5074 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5075 } else if (IS_DG2(dev_priv)) { 5076 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5077 } else if (DISPLAY_VER(dev_priv) >= 12) { 5078 if (intel_encoder_is_combo(encoder)) 5079 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5080 else 5081 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5082 } else if (DISPLAY_VER(dev_priv) >= 11) { 5083 if (intel_encoder_is_combo(encoder)) 5084 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5085 else 5086 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5087 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5088 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5089 } else { 5090 encoder->set_signal_levels = hsw_set_signal_levels; 5091 } 5092 5093 intel_ddi_buf_trans_init(encoder); 5094 5095 if (DISPLAY_VER(dev_priv) >= 13) 5096 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5097 else if (IS_DG1(dev_priv)) 5098 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5099 else if (IS_ROCKETLAKE(dev_priv)) 5100 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5101 else if (DISPLAY_VER(dev_priv) >= 12) 5102 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5103 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5104 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5105 else if (DISPLAY_VER(dev_priv) == 11) 5106 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5107 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5108 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5109 else 5110 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5111 5112 if (DISPLAY_VER(dev_priv) >= 11) 5113 dig_port->saved_port_bits = 5114 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5115 & DDI_BUF_PORT_REVERSAL; 5116 else 5117 dig_port->saved_port_bits = 5118 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5119 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5120 5121 if (intel_bios_encoder_lane_reversal(devdata)) 5122 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5123 5124 dig_port->dp.output_reg = INVALID_MMIO_REG; 5125 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5126 5127 if (need_aux_ch(encoder, init_dp)) { 5128 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5129 if (dig_port->aux_ch == AUX_CH_NONE) 5130 goto err; 5131 } 5132 5133 if (intel_encoder_is_tc(encoder)) { 5134 bool is_legacy = 5135 !intel_bios_encoder_supports_typec_usb(devdata) && 5136 !intel_bios_encoder_supports_tbt(devdata); 5137 5138 if (!is_legacy && init_hdmi) { 5139 is_legacy = !init_dp; 5140 5141 drm_dbg_kms(&dev_priv->drm, 5142 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5143 port_name(port), 5144 str_yes_no(init_dp), 5145 is_legacy ? "legacy" : "non-legacy"); 5146 } 5147 5148 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5149 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5150 5151 dig_port->lock = intel_tc_port_lock; 5152 dig_port->unlock = intel_tc_port_unlock; 5153 5154 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5155 goto err; 5156 } 5157 5158 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5159 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5160 5161 if (DISPLAY_VER(dev_priv) >= 11) { 5162 if (intel_encoder_is_tc(encoder)) 5163 dig_port->connected = intel_tc_port_connected; 5164 else 5165 dig_port->connected = lpt_digital_port_connected; 5166 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5167 dig_port->connected = bdw_digital_port_connected; 5168 } else if (DISPLAY_VER(dev_priv) == 9) { 5169 dig_port->connected = lpt_digital_port_connected; 5170 } else if (IS_BROADWELL(dev_priv)) { 5171 if (port == PORT_A) 5172 dig_port->connected = bdw_digital_port_connected; 5173 else 5174 dig_port->connected = lpt_digital_port_connected; 5175 } else if (IS_HASWELL(dev_priv)) { 5176 if (port == PORT_A) 5177 dig_port->connected = hsw_digital_port_connected; 5178 else 5179 dig_port->connected = lpt_digital_port_connected; 5180 } 5181 5182 intel_infoframe_init(dig_port); 5183 5184 if (init_dp) { 5185 if (!intel_ddi_init_dp_connector(dig_port)) 5186 goto err; 5187 5188 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5189 5190 if (dig_port->dp.mso_link_count) 5191 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5192 } 5193 5194 /* 5195 * In theory we don't need the encoder->type check, 5196 * but leave it just in case we have some really bad VBTs... 5197 */ 5198 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5199 if (!intel_ddi_init_hdmi_connector(dig_port)) 5200 goto err; 5201 } 5202 5203 return; 5204 5205 err: 5206 drm_encoder_cleanup(&encoder->base); 5207 kfree(dig_port); 5208 } 5209