1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_privacy_screen_consumer.h> 29 #include <drm/drm_scdc_helper.h> 30 31 #include "i915_drv.h" 32 #include "intel_audio.h" 33 #include "intel_backlight.h" 34 #include "intel_combo_phy.h" 35 #include "intel_combo_phy_regs.h" 36 #include "intel_connector.h" 37 #include "intel_crtc.h" 38 #include "intel_ddi.h" 39 #include "intel_ddi_buf_trans.h" 40 #include "intel_de.h" 41 #include "intel_display_types.h" 42 #include "intel_dp.h" 43 #include "intel_dp_link_training.h" 44 #include "intel_dp_mst.h" 45 #include "intel_dpio_phy.h" 46 #include "intel_drrs.h" 47 #include "intel_dsi.h" 48 #include "intel_fdi.h" 49 #include "intel_fifo_underrun.h" 50 #include "intel_gmbus.h" 51 #include "intel_hdcp.h" 52 #include "intel_hdmi.h" 53 #include "intel_hotplug.h" 54 #include "intel_lspcon.h" 55 #include "intel_pps.h" 56 #include "intel_psr.h" 57 #include "intel_snps_phy.h" 58 #include "intel_sprite.h" 59 #include "intel_tc.h" 60 #include "intel_tc_phy_regs.h" 61 #include "intel_vdsc.h" 62 #include "intel_vrr.h" 63 #include "skl_scaler.h" 64 #include "skl_universal_plane.h" 65 66 static const u8 index_to_dp_signal_levels[] = { 67 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 70 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 71 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 72 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 73 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 74 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 75 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 76 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 77 }; 78 79 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 80 const struct intel_ddi_buf_trans *trans) 81 { 82 int level; 83 84 level = intel_bios_hdmi_level_shift(encoder); 85 if (level < 0) 86 level = trans->hdmi_default_entry; 87 88 return level; 89 } 90 91 static bool has_buf_trans_select(struct drm_i915_private *i915) 92 { 93 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 94 } 95 96 static bool has_iboost(struct drm_i915_private *i915) 97 { 98 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 99 } 100 101 /* 102 * Starting with Haswell, DDI port buffers must be programmed with correct 103 * values in advance. This function programs the correct values for 104 * DP/eDP/FDI use cases. 105 */ 106 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 107 const struct intel_crtc_state *crtc_state) 108 { 109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 110 u32 iboost_bit = 0; 111 int i, n_entries; 112 enum port port = encoder->port; 113 const struct intel_ddi_buf_trans *trans; 114 115 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 116 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 117 return; 118 119 /* If we're boosting the current, set bit 31 of trans1 */ 120 if (has_iboost(dev_priv) && 121 intel_bios_encoder_dp_boost_level(encoder->devdata)) 122 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 123 124 for (i = 0; i < n_entries; i++) { 125 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 126 trans->entries[i].hsw.trans1 | iboost_bit); 127 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 128 trans->entries[i].hsw.trans2); 129 } 130 } 131 132 /* 133 * Starting with Haswell, DDI port buffers must be programmed with correct 134 * values in advance. This function programs the correct values for 135 * HDMI/DVI use cases. 136 */ 137 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 138 const struct intel_crtc_state *crtc_state) 139 { 140 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 141 int level = intel_ddi_level(encoder, crtc_state, 0); 142 u32 iboost_bit = 0; 143 int n_entries; 144 enum port port = encoder->port; 145 const struct intel_ddi_buf_trans *trans; 146 147 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 148 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 149 return; 150 151 /* If we're boosting the current, set bit 31 of trans1 */ 152 if (has_iboost(dev_priv) && 153 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 154 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 155 156 /* Entry 9 is for HDMI: */ 157 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 158 trans->entries[level].hsw.trans1 | iboost_bit); 159 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 160 trans->entries[level].hsw.trans2); 161 } 162 163 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 164 enum port port) 165 { 166 if (IS_BROXTON(dev_priv)) { 167 udelay(16); 168 return; 169 } 170 171 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 172 DDI_BUF_IS_IDLE), 8)) 173 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 174 port_name(port)); 175 } 176 177 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 178 enum port port) 179 { 180 int ret; 181 182 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 183 if (DISPLAY_VER(dev_priv) < 10) { 184 usleep_range(518, 1000); 185 return; 186 } 187 188 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 189 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 190 191 if (ret) 192 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 193 port_name(port)); 194 } 195 196 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 197 { 198 switch (pll->info->id) { 199 case DPLL_ID_WRPLL1: 200 return PORT_CLK_SEL_WRPLL1; 201 case DPLL_ID_WRPLL2: 202 return PORT_CLK_SEL_WRPLL2; 203 case DPLL_ID_SPLL: 204 return PORT_CLK_SEL_SPLL; 205 case DPLL_ID_LCPLL_810: 206 return PORT_CLK_SEL_LCPLL_810; 207 case DPLL_ID_LCPLL_1350: 208 return PORT_CLK_SEL_LCPLL_1350; 209 case DPLL_ID_LCPLL_2700: 210 return PORT_CLK_SEL_LCPLL_2700; 211 default: 212 MISSING_CASE(pll->info->id); 213 return PORT_CLK_SEL_NONE; 214 } 215 } 216 217 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 218 const struct intel_crtc_state *crtc_state) 219 { 220 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 221 int clock = crtc_state->port_clock; 222 const enum intel_dpll_id id = pll->info->id; 223 224 switch (id) { 225 default: 226 /* 227 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 228 * here, so do warn if this get passed in 229 */ 230 MISSING_CASE(id); 231 return DDI_CLK_SEL_NONE; 232 case DPLL_ID_ICL_TBTPLL: 233 switch (clock) { 234 case 162000: 235 return DDI_CLK_SEL_TBT_162; 236 case 270000: 237 return DDI_CLK_SEL_TBT_270; 238 case 540000: 239 return DDI_CLK_SEL_TBT_540; 240 case 810000: 241 return DDI_CLK_SEL_TBT_810; 242 default: 243 MISSING_CASE(clock); 244 return DDI_CLK_SEL_NONE; 245 } 246 case DPLL_ID_ICL_MGPLL1: 247 case DPLL_ID_ICL_MGPLL2: 248 case DPLL_ID_ICL_MGPLL3: 249 case DPLL_ID_ICL_MGPLL4: 250 case DPLL_ID_TGL_MGPLL5: 251 case DPLL_ID_TGL_MGPLL6: 252 return DDI_CLK_SEL_MG; 253 } 254 } 255 256 static u32 ddi_buf_phy_link_rate(int port_clock) 257 { 258 switch (port_clock) { 259 case 162000: 260 return DDI_BUF_PHY_LINK_RATE(0); 261 case 216000: 262 return DDI_BUF_PHY_LINK_RATE(4); 263 case 243000: 264 return DDI_BUF_PHY_LINK_RATE(5); 265 case 270000: 266 return DDI_BUF_PHY_LINK_RATE(1); 267 case 324000: 268 return DDI_BUF_PHY_LINK_RATE(6); 269 case 432000: 270 return DDI_BUF_PHY_LINK_RATE(7); 271 case 540000: 272 return DDI_BUF_PHY_LINK_RATE(2); 273 case 810000: 274 return DDI_BUF_PHY_LINK_RATE(3); 275 default: 276 MISSING_CASE(port_clock); 277 return DDI_BUF_PHY_LINK_RATE(0); 278 } 279 } 280 281 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 282 const struct intel_crtc_state *crtc_state) 283 { 284 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 286 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 287 enum phy phy = intel_port_to_phy(i915, encoder->port); 288 289 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 290 intel_dp->DP = dig_port->saved_port_bits | 291 DDI_PORT_WIDTH(crtc_state->lane_count) | 292 DDI_BUF_TRANS_SELECT(0); 293 294 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 295 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 296 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 297 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 298 } 299 } 300 301 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 302 enum port port) 303 { 304 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 305 306 switch (val) { 307 case DDI_CLK_SEL_NONE: 308 return 0; 309 case DDI_CLK_SEL_TBT_162: 310 return 162000; 311 case DDI_CLK_SEL_TBT_270: 312 return 270000; 313 case DDI_CLK_SEL_TBT_540: 314 return 540000; 315 case DDI_CLK_SEL_TBT_810: 316 return 810000; 317 default: 318 MISSING_CASE(val); 319 return 0; 320 } 321 } 322 323 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 324 { 325 int dotclock; 326 327 /* CRT dotclock is determined via other means */ 328 if (pipe_config->has_pch_encoder) 329 return; 330 331 if (intel_crtc_has_dp_encoder(pipe_config)) 332 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 333 &pipe_config->dp_m_n); 334 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 335 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 336 else 337 dotclock = pipe_config->port_clock; 338 339 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 340 !intel_crtc_has_dp_encoder(pipe_config)) 341 dotclock *= 2; 342 343 if (pipe_config->pixel_multiplier) 344 dotclock /= pipe_config->pixel_multiplier; 345 346 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 347 } 348 349 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 350 const struct drm_connector_state *conn_state) 351 { 352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 354 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 355 u32 temp; 356 357 if (!intel_crtc_has_dp_encoder(crtc_state)) 358 return; 359 360 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 361 362 temp = DP_MSA_MISC_SYNC_CLOCK; 363 364 switch (crtc_state->pipe_bpp) { 365 case 18: 366 temp |= DP_MSA_MISC_6_BPC; 367 break; 368 case 24: 369 temp |= DP_MSA_MISC_8_BPC; 370 break; 371 case 30: 372 temp |= DP_MSA_MISC_10_BPC; 373 break; 374 case 36: 375 temp |= DP_MSA_MISC_12_BPC; 376 break; 377 default: 378 MISSING_CASE(crtc_state->pipe_bpp); 379 break; 380 } 381 382 /* nonsense combination */ 383 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 384 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 385 386 if (crtc_state->limited_color_range) 387 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 388 389 /* 390 * As per DP 1.2 spec section 2.3.4.3 while sending 391 * YCBCR 444 signals we should program MSA MISC1/0 fields with 392 * colorspace information. 393 */ 394 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 395 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 396 397 /* 398 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 399 * of Color Encoding Format and Content Color Gamut] while sending 400 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 401 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 402 */ 403 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 404 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 405 406 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 407 } 408 409 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 410 { 411 if (master_transcoder == TRANSCODER_EDP) 412 return 0; 413 else 414 return master_transcoder + 1; 415 } 416 417 static void 418 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 419 const struct intel_crtc_state *crtc_state) 420 { 421 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 422 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 423 u32 val = 0; 424 425 if (intel_dp_is_uhbr(crtc_state)) 426 val = TRANS_DP2_128B132B_CHANNEL_CODING; 427 428 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 429 } 430 431 /* 432 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 433 * 434 * Only intended to be used by intel_ddi_enable_transcoder_func() and 435 * intel_ddi_config_transcoder_func(). 436 */ 437 static u32 438 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 439 const struct intel_crtc_state *crtc_state) 440 { 441 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 443 enum pipe pipe = crtc->pipe; 444 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 445 enum port port = encoder->port; 446 u32 temp; 447 448 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 449 temp = TRANS_DDI_FUNC_ENABLE; 450 if (DISPLAY_VER(dev_priv) >= 12) 451 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 452 else 453 temp |= TRANS_DDI_SELECT_PORT(port); 454 455 switch (crtc_state->pipe_bpp) { 456 case 18: 457 temp |= TRANS_DDI_BPC_6; 458 break; 459 case 24: 460 temp |= TRANS_DDI_BPC_8; 461 break; 462 case 30: 463 temp |= TRANS_DDI_BPC_10; 464 break; 465 case 36: 466 temp |= TRANS_DDI_BPC_12; 467 break; 468 default: 469 BUG(); 470 } 471 472 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 473 temp |= TRANS_DDI_PVSYNC; 474 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 475 temp |= TRANS_DDI_PHSYNC; 476 477 if (cpu_transcoder == TRANSCODER_EDP) { 478 switch (pipe) { 479 case PIPE_A: 480 /* On Haswell, can only use the always-on power well for 481 * eDP when not using the panel fitter, and when not 482 * using motion blur mitigation (which we don't 483 * support). */ 484 if (crtc_state->pch_pfit.force_thru) 485 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 486 else 487 temp |= TRANS_DDI_EDP_INPUT_A_ON; 488 break; 489 case PIPE_B: 490 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 491 break; 492 case PIPE_C: 493 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 494 break; 495 default: 496 BUG(); 497 break; 498 } 499 } 500 501 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 502 if (crtc_state->has_hdmi_sink) 503 temp |= TRANS_DDI_MODE_SELECT_HDMI; 504 else 505 temp |= TRANS_DDI_MODE_SELECT_DVI; 506 507 if (crtc_state->hdmi_scrambling) 508 temp |= TRANS_DDI_HDMI_SCRAMBLING; 509 if (crtc_state->hdmi_high_tmds_clock_ratio) 510 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 511 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 512 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 513 temp |= (crtc_state->fdi_lanes - 1) << 1; 514 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 515 if (intel_dp_is_uhbr(crtc_state)) 516 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 517 else 518 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 519 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 520 521 if (DISPLAY_VER(dev_priv) >= 12) { 522 enum transcoder master; 523 524 master = crtc_state->mst_master_transcoder; 525 drm_WARN_ON(&dev_priv->drm, 526 master == INVALID_TRANSCODER); 527 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 528 } 529 } else { 530 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 531 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 532 } 533 534 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 535 crtc_state->master_transcoder != INVALID_TRANSCODER) { 536 u8 master_select = 537 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 538 539 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 540 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 541 } 542 543 return temp; 544 } 545 546 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 547 const struct intel_crtc_state *crtc_state) 548 { 549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 552 553 if (DISPLAY_VER(dev_priv) >= 11) { 554 enum transcoder master_transcoder = crtc_state->master_transcoder; 555 u32 ctl2 = 0; 556 557 if (master_transcoder != INVALID_TRANSCODER) { 558 u8 master_select = 559 bdw_trans_port_sync_master_select(master_transcoder); 560 561 ctl2 |= PORT_SYNC_MODE_ENABLE | 562 PORT_SYNC_MODE_MASTER_SELECT(master_select); 563 } 564 565 intel_de_write(dev_priv, 566 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 567 } 568 569 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 570 intel_ddi_transcoder_func_reg_val_get(encoder, 571 crtc_state)); 572 } 573 574 /* 575 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 576 * bit. 577 */ 578 static void 579 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 580 const struct intel_crtc_state *crtc_state) 581 { 582 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 583 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 584 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 585 u32 ctl; 586 587 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 588 ctl &= ~TRANS_DDI_FUNC_ENABLE; 589 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 590 } 591 592 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 593 { 594 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 595 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 596 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 597 u32 ctl; 598 599 if (DISPLAY_VER(dev_priv) >= 11) 600 intel_de_write(dev_priv, 601 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 602 603 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 604 605 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 606 607 ctl &= ~TRANS_DDI_FUNC_ENABLE; 608 609 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 610 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 611 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 612 613 if (DISPLAY_VER(dev_priv) >= 12) { 614 if (!intel_dp_mst_is_master_trans(crtc_state)) { 615 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 616 TRANS_DDI_MODE_SELECT_MASK); 617 } 618 } else { 619 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 620 } 621 622 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 623 624 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 625 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 626 drm_dbg_kms(&dev_priv->drm, 627 "Quirk Increase DDI disabled time\n"); 628 /* Quirk time at 100ms for reliable operation */ 629 msleep(100); 630 } 631 } 632 633 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 634 enum transcoder cpu_transcoder, 635 bool enable, u32 hdcp_mask) 636 { 637 struct drm_device *dev = intel_encoder->base.dev; 638 struct drm_i915_private *dev_priv = to_i915(dev); 639 intel_wakeref_t wakeref; 640 int ret = 0; 641 u32 tmp; 642 643 wakeref = intel_display_power_get_if_enabled(dev_priv, 644 intel_encoder->power_domain); 645 if (drm_WARN_ON(dev, !wakeref)) 646 return -ENXIO; 647 648 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 649 if (enable) 650 tmp |= hdcp_mask; 651 else 652 tmp &= ~hdcp_mask; 653 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 654 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 655 return ret; 656 } 657 658 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 659 { 660 struct drm_device *dev = intel_connector->base.dev; 661 struct drm_i915_private *dev_priv = to_i915(dev); 662 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 663 int type = intel_connector->base.connector_type; 664 enum port port = encoder->port; 665 enum transcoder cpu_transcoder; 666 intel_wakeref_t wakeref; 667 enum pipe pipe = 0; 668 u32 tmp; 669 bool ret; 670 671 wakeref = intel_display_power_get_if_enabled(dev_priv, 672 encoder->power_domain); 673 if (!wakeref) 674 return false; 675 676 if (!encoder->get_hw_state(encoder, &pipe)) { 677 ret = false; 678 goto out; 679 } 680 681 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 682 cpu_transcoder = TRANSCODER_EDP; 683 else 684 cpu_transcoder = (enum transcoder) pipe; 685 686 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 687 688 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 689 case TRANS_DDI_MODE_SELECT_HDMI: 690 case TRANS_DDI_MODE_SELECT_DVI: 691 ret = type == DRM_MODE_CONNECTOR_HDMIA; 692 break; 693 694 case TRANS_DDI_MODE_SELECT_DP_SST: 695 ret = type == DRM_MODE_CONNECTOR_eDP || 696 type == DRM_MODE_CONNECTOR_DisplayPort; 697 break; 698 699 case TRANS_DDI_MODE_SELECT_DP_MST: 700 /* if the transcoder is in MST state then 701 * connector isn't connected */ 702 ret = false; 703 break; 704 705 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 706 if (HAS_DP20(dev_priv)) 707 /* 128b/132b */ 708 ret = false; 709 else 710 /* FDI */ 711 ret = type == DRM_MODE_CONNECTOR_VGA; 712 break; 713 714 default: 715 ret = false; 716 break; 717 } 718 719 out: 720 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 721 722 return ret; 723 } 724 725 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 726 u8 *pipe_mask, bool *is_dp_mst) 727 { 728 struct drm_device *dev = encoder->base.dev; 729 struct drm_i915_private *dev_priv = to_i915(dev); 730 enum port port = encoder->port; 731 intel_wakeref_t wakeref; 732 enum pipe p; 733 u32 tmp; 734 u8 mst_pipe_mask; 735 736 *pipe_mask = 0; 737 *is_dp_mst = false; 738 739 wakeref = intel_display_power_get_if_enabled(dev_priv, 740 encoder->power_domain); 741 if (!wakeref) 742 return; 743 744 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 745 if (!(tmp & DDI_BUF_CTL_ENABLE)) 746 goto out; 747 748 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 749 tmp = intel_de_read(dev_priv, 750 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 751 752 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 753 default: 754 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 755 fallthrough; 756 case TRANS_DDI_EDP_INPUT_A_ON: 757 case TRANS_DDI_EDP_INPUT_A_ONOFF: 758 *pipe_mask = BIT(PIPE_A); 759 break; 760 case TRANS_DDI_EDP_INPUT_B_ONOFF: 761 *pipe_mask = BIT(PIPE_B); 762 break; 763 case TRANS_DDI_EDP_INPUT_C_ONOFF: 764 *pipe_mask = BIT(PIPE_C); 765 break; 766 } 767 768 goto out; 769 } 770 771 mst_pipe_mask = 0; 772 for_each_pipe(dev_priv, p) { 773 enum transcoder cpu_transcoder = (enum transcoder)p; 774 unsigned int port_mask, ddi_select; 775 intel_wakeref_t trans_wakeref; 776 777 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 778 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 779 if (!trans_wakeref) 780 continue; 781 782 if (DISPLAY_VER(dev_priv) >= 12) { 783 port_mask = TGL_TRANS_DDI_PORT_MASK; 784 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 785 } else { 786 port_mask = TRANS_DDI_PORT_MASK; 787 ddi_select = TRANS_DDI_SELECT_PORT(port); 788 } 789 790 tmp = intel_de_read(dev_priv, 791 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 792 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 793 trans_wakeref); 794 795 if ((tmp & port_mask) != ddi_select) 796 continue; 797 798 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 799 (HAS_DP20(dev_priv) && 800 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 801 mst_pipe_mask |= BIT(p); 802 803 *pipe_mask |= BIT(p); 804 } 805 806 if (!*pipe_mask) 807 drm_dbg_kms(&dev_priv->drm, 808 "No pipe for [ENCODER:%d:%s] found\n", 809 encoder->base.base.id, encoder->base.name); 810 811 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 812 drm_dbg_kms(&dev_priv->drm, 813 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 814 encoder->base.base.id, encoder->base.name, 815 *pipe_mask); 816 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 817 } 818 819 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 820 drm_dbg_kms(&dev_priv->drm, 821 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 822 encoder->base.base.id, encoder->base.name, 823 *pipe_mask, mst_pipe_mask); 824 else 825 *is_dp_mst = mst_pipe_mask; 826 827 out: 828 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 829 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 830 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 831 BXT_PHY_LANE_POWERDOWN_ACK | 832 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 833 drm_err(&dev_priv->drm, 834 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 835 encoder->base.base.id, encoder->base.name, tmp); 836 } 837 838 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 839 } 840 841 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 842 enum pipe *pipe) 843 { 844 u8 pipe_mask; 845 bool is_mst; 846 847 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 848 849 if (is_mst || !pipe_mask) 850 return false; 851 852 *pipe = ffs(pipe_mask) - 1; 853 854 return true; 855 } 856 857 static enum intel_display_power_domain 858 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 859 { 860 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 861 * DC states enabled at the same time, while for driver initiated AUX 862 * transfers we need the same AUX IOs to be powered but with DC states 863 * disabled. Accordingly use the AUX power domain here which leaves DC 864 * states enabled. 865 * However, for non-A AUX ports the corresponding non-EDP transcoders 866 * would have already enabled power well 2 and DC_OFF. This means we can 867 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 868 * specific AUX_IO reference without powering up any extra wells. 869 * Note that PSR is enabled only on Port A even though this function 870 * returns the correct domain for other ports too. 871 */ 872 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 873 intel_aux_power_domain(dig_port); 874 } 875 876 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 877 struct intel_crtc_state *crtc_state) 878 { 879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 880 struct intel_digital_port *dig_port; 881 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 882 883 /* 884 * TODO: Add support for MST encoders. Atm, the following should never 885 * happen since fake-MST encoders don't set their get_power_domains() 886 * hook. 887 */ 888 if (drm_WARN_ON(&dev_priv->drm, 889 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 890 return; 891 892 dig_port = enc_to_dig_port(encoder); 893 894 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 895 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 896 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 897 dig_port->ddi_io_power_domain); 898 } 899 900 /* 901 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 902 * ports. 903 */ 904 if (intel_crtc_has_dp_encoder(crtc_state) || 905 intel_phy_is_tc(dev_priv, phy)) { 906 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 907 dig_port->aux_wakeref = 908 intel_display_power_get(dev_priv, 909 intel_ddi_main_link_aux_domain(dig_port)); 910 } 911 } 912 913 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 914 const struct intel_crtc_state *crtc_state) 915 { 916 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 917 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 918 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 919 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 920 u32 val; 921 922 if (cpu_transcoder != TRANSCODER_EDP) { 923 if (DISPLAY_VER(dev_priv) >= 13) 924 val = TGL_TRANS_CLK_SEL_PORT(phy); 925 else if (DISPLAY_VER(dev_priv) >= 12) 926 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 927 else 928 val = TRANS_CLK_SEL_PORT(encoder->port); 929 930 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 931 } 932 } 933 934 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 935 { 936 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 937 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 938 939 if (cpu_transcoder != TRANSCODER_EDP) { 940 if (DISPLAY_VER(dev_priv) >= 12) 941 intel_de_write(dev_priv, 942 TRANS_CLK_SEL(cpu_transcoder), 943 TGL_TRANS_CLK_SEL_DISABLED); 944 else 945 intel_de_write(dev_priv, 946 TRANS_CLK_SEL(cpu_transcoder), 947 TRANS_CLK_SEL_DISABLED); 948 } 949 } 950 951 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 952 enum port port, u8 iboost) 953 { 954 u32 tmp; 955 956 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 957 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 958 if (iboost) 959 tmp |= iboost << BALANCE_LEG_SHIFT(port); 960 else 961 tmp |= BALANCE_LEG_DISABLE(port); 962 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 963 } 964 965 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 966 const struct intel_crtc_state *crtc_state, 967 int level) 968 { 969 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 971 u8 iboost; 972 973 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 974 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 975 else 976 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 977 978 if (iboost == 0) { 979 const struct intel_ddi_buf_trans *trans; 980 int n_entries; 981 982 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 983 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 984 return; 985 986 iboost = trans->entries[level].hsw.i_boost; 987 } 988 989 /* Make sure that the requested I_boost is valid */ 990 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 991 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 992 return; 993 } 994 995 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 996 997 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 998 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 999 } 1000 1001 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1002 const struct intel_crtc_state *crtc_state) 1003 { 1004 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 int n_entries; 1007 1008 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1009 1010 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1011 n_entries = 1; 1012 if (drm_WARN_ON(&dev_priv->drm, 1013 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1014 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1015 1016 return index_to_dp_signal_levels[n_entries - 1] & 1017 DP_TRAIN_VOLTAGE_SWING_MASK; 1018 } 1019 1020 /* 1021 * We assume that the full set of pre-emphasis values can be 1022 * used on all DDI platforms. Should that change we need to 1023 * rethink this code. 1024 */ 1025 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1026 { 1027 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1028 } 1029 1030 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1031 int lane) 1032 { 1033 if (crtc_state->port_clock > 600000) 1034 return 0; 1035 1036 if (crtc_state->lane_count == 4) 1037 return lane >= 1 ? LOADGEN_SELECT : 0; 1038 else 1039 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1040 } 1041 1042 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1043 const struct intel_crtc_state *crtc_state) 1044 { 1045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1046 const struct intel_ddi_buf_trans *trans; 1047 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1048 int n_entries, ln; 1049 u32 val; 1050 1051 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1052 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1053 return; 1054 1055 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1056 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1057 1058 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1059 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1060 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1061 intel_dp->hobl_active ? val : 0); 1062 } 1063 1064 /* Set PORT_TX_DW5 */ 1065 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1066 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1067 TAP2_DISABLE | TAP3_DISABLE); 1068 val |= SCALING_MODE_SEL(0x2); 1069 val |= RTERM_SELECT(0x6); 1070 val |= TAP3_DISABLE; 1071 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1072 1073 /* Program PORT_TX_DW2 */ 1074 for (ln = 0; ln < 4; ln++) { 1075 int level = intel_ddi_level(encoder, crtc_state, ln); 1076 1077 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1078 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1079 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1080 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1081 RCOMP_SCALAR(0x98)); 1082 } 1083 1084 /* Program PORT_TX_DW4 */ 1085 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1086 for (ln = 0; ln < 4; ln++) { 1087 int level = intel_ddi_level(encoder, crtc_state, ln); 1088 1089 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1090 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1091 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1092 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1093 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1094 } 1095 1096 /* Program PORT_TX_DW7 */ 1097 for (ln = 0; ln < 4; ln++) { 1098 int level = intel_ddi_level(encoder, crtc_state, ln); 1099 1100 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1101 N_SCALAR_MASK, 1102 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1103 } 1104 } 1105 1106 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1107 const struct intel_crtc_state *crtc_state) 1108 { 1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1110 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1111 u32 val; 1112 int ln; 1113 1114 /* 1115 * 1. If port type is eDP or DP, 1116 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1117 * else clear to 0b. 1118 */ 1119 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1120 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1121 val &= ~COMMON_KEEPER_EN; 1122 else 1123 val |= COMMON_KEEPER_EN; 1124 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1125 1126 /* 2. Program loadgen select */ 1127 /* 1128 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1129 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1130 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1131 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1132 */ 1133 for (ln = 0; ln < 4; ln++) { 1134 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1135 LOADGEN_SELECT, 1136 icl_combo_phy_loadgen_select(crtc_state, ln)); 1137 } 1138 1139 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1140 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1141 0, SUS_CLOCK_CONFIG); 1142 1143 /* 4. Clear training enable to change swing values */ 1144 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1145 val &= ~TX_TRAINING_EN; 1146 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1147 1148 /* 5. Program swing and de-emphasis */ 1149 icl_ddi_combo_vswing_program(encoder, crtc_state); 1150 1151 /* 6. Set training enable to trigger update */ 1152 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1153 val |= TX_TRAINING_EN; 1154 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1155 } 1156 1157 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1158 const struct intel_crtc_state *crtc_state) 1159 { 1160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1161 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1162 const struct intel_ddi_buf_trans *trans; 1163 int n_entries, ln; 1164 1165 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1166 return; 1167 1168 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1169 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1170 return; 1171 1172 for (ln = 0; ln < 2; ln++) { 1173 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1174 CRI_USE_FS32, 0); 1175 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1176 CRI_USE_FS32, 0); 1177 } 1178 1179 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1180 for (ln = 0; ln < 2; ln++) { 1181 int level; 1182 1183 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1184 1185 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1186 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1187 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1188 1189 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1190 1191 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1192 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1193 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1194 } 1195 1196 /* Program MG_TX_DRVCTRL with values from vswing table */ 1197 for (ln = 0; ln < 2; ln++) { 1198 int level; 1199 1200 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1201 1202 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1203 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1204 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1205 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1206 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1207 CRI_TXDEEMPH_OVERRIDE_EN); 1208 1209 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1210 1211 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1212 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1213 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1214 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1215 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1216 CRI_TXDEEMPH_OVERRIDE_EN); 1217 1218 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1219 } 1220 1221 /* 1222 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1223 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1224 * values from table for which TX1 and TX2 enabled. 1225 */ 1226 for (ln = 0; ln < 2; ln++) { 1227 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1228 CFG_LOW_RATE_LKREN_EN, 1229 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1230 } 1231 1232 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1233 for (ln = 0; ln < 2; ln++) { 1234 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1235 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1236 CFG_AMI_CK_DIV_OVERRIDE_EN, 1237 crtc_state->port_clock > 500000 ? 1238 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1239 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1240 1241 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1242 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1243 CFG_AMI_CK_DIV_OVERRIDE_EN, 1244 crtc_state->port_clock > 500000 ? 1245 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1246 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1247 } 1248 1249 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1250 for (ln = 0; ln < 2; ln++) { 1251 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1252 0, CRI_CALCINIT); 1253 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1254 0, CRI_CALCINIT); 1255 } 1256 } 1257 1258 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1259 const struct intel_crtc_state *crtc_state) 1260 { 1261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1262 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1263 const struct intel_ddi_buf_trans *trans; 1264 int n_entries, ln; 1265 1266 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1267 return; 1268 1269 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1270 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1271 return; 1272 1273 for (ln = 0; ln < 2; ln++) { 1274 int level; 1275 1276 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1277 HIP_INDEX_VAL(tc_port, ln)); 1278 1279 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1280 1281 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1282 1283 intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), 1284 DKL_TX_PRESHOOT_COEFF_MASK | 1285 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1286 DKL_TX_VSWING_CONTROL_MASK, 1287 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1288 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1289 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1290 1291 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1292 1293 intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), 1294 DKL_TX_PRESHOOT_COEFF_MASK | 1295 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1296 DKL_TX_VSWING_CONTROL_MASK, 1297 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1298 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1299 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1300 1301 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1302 DKL_TX_DP20BITMODE, 0); 1303 1304 if (IS_ALDERLAKE_P(dev_priv)) { 1305 u32 val; 1306 1307 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1308 if (ln == 0) { 1309 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1310 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1311 } else { 1312 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1313 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1314 } 1315 } else { 1316 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1317 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1318 } 1319 1320 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1321 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1322 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1323 val); 1324 } 1325 } 1326 } 1327 1328 static int translate_signal_level(struct intel_dp *intel_dp, 1329 u8 signal_levels) 1330 { 1331 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1332 int i; 1333 1334 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1335 if (index_to_dp_signal_levels[i] == signal_levels) 1336 return i; 1337 } 1338 1339 drm_WARN(&i915->drm, 1, 1340 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1341 signal_levels); 1342 1343 return 0; 1344 } 1345 1346 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1347 const struct intel_crtc_state *crtc_state, 1348 int lane) 1349 { 1350 u8 train_set = intel_dp->train_set[lane]; 1351 1352 if (intel_dp_is_uhbr(crtc_state)) { 1353 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1354 } else { 1355 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1356 DP_TRAIN_PRE_EMPHASIS_MASK); 1357 1358 return translate_signal_level(intel_dp, signal_levels); 1359 } 1360 } 1361 1362 int intel_ddi_level(struct intel_encoder *encoder, 1363 const struct intel_crtc_state *crtc_state, 1364 int lane) 1365 { 1366 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1367 const struct intel_ddi_buf_trans *trans; 1368 int level, n_entries; 1369 1370 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1371 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1372 return 0; 1373 1374 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1375 level = intel_ddi_hdmi_level(encoder, trans); 1376 else 1377 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1378 lane); 1379 1380 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1381 level = n_entries - 1; 1382 1383 return level; 1384 } 1385 1386 static void 1387 hsw_set_signal_levels(struct intel_encoder *encoder, 1388 const struct intel_crtc_state *crtc_state) 1389 { 1390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1391 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1392 int level = intel_ddi_level(encoder, crtc_state, 0); 1393 enum port port = encoder->port; 1394 u32 signal_levels; 1395 1396 if (has_iboost(dev_priv)) 1397 skl_ddi_set_iboost(encoder, crtc_state, level); 1398 1399 /* HDMI ignores the rest */ 1400 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1401 return; 1402 1403 signal_levels = DDI_BUF_TRANS_SELECT(level); 1404 1405 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1406 signal_levels); 1407 1408 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1409 intel_dp->DP |= signal_levels; 1410 1411 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1412 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1413 } 1414 1415 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1416 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1417 { 1418 mutex_lock(&i915->dpll.lock); 1419 1420 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1421 1422 /* 1423 * "This step and the step before must be 1424 * done with separate register writes." 1425 */ 1426 intel_de_rmw(i915, reg, clk_off, 0); 1427 1428 mutex_unlock(&i915->dpll.lock); 1429 } 1430 1431 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1432 u32 clk_off) 1433 { 1434 mutex_lock(&i915->dpll.lock); 1435 1436 intel_de_rmw(i915, reg, 0, clk_off); 1437 1438 mutex_unlock(&i915->dpll.lock); 1439 } 1440 1441 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1442 u32 clk_off) 1443 { 1444 return !(intel_de_read(i915, reg) & clk_off); 1445 } 1446 1447 static struct intel_shared_dpll * 1448 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1449 u32 clk_sel_mask, u32 clk_sel_shift) 1450 { 1451 enum intel_dpll_id id; 1452 1453 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1454 1455 return intel_get_shared_dpll_by_id(i915, id); 1456 } 1457 1458 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1459 const struct intel_crtc_state *crtc_state) 1460 { 1461 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1462 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1463 enum phy phy = intel_port_to_phy(i915, encoder->port); 1464 1465 if (drm_WARN_ON(&i915->drm, !pll)) 1466 return; 1467 1468 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1469 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1470 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1471 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1472 } 1473 1474 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1475 { 1476 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1477 enum phy phy = intel_port_to_phy(i915, encoder->port); 1478 1479 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1480 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1481 } 1482 1483 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1484 { 1485 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1486 enum phy phy = intel_port_to_phy(i915, encoder->port); 1487 1488 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1489 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1490 } 1491 1492 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1493 { 1494 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1495 enum phy phy = intel_port_to_phy(i915, encoder->port); 1496 1497 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1498 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1499 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1500 } 1501 1502 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1503 const struct intel_crtc_state *crtc_state) 1504 { 1505 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1506 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1507 enum phy phy = intel_port_to_phy(i915, encoder->port); 1508 1509 if (drm_WARN_ON(&i915->drm, !pll)) 1510 return; 1511 1512 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1513 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1514 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1515 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1516 } 1517 1518 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1519 { 1520 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1521 enum phy phy = intel_port_to_phy(i915, encoder->port); 1522 1523 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1524 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1525 } 1526 1527 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1528 { 1529 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1530 enum phy phy = intel_port_to_phy(i915, encoder->port); 1531 1532 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1533 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1534 } 1535 1536 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1537 { 1538 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1539 enum phy phy = intel_port_to_phy(i915, encoder->port); 1540 1541 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1542 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1543 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1544 } 1545 1546 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1547 const struct intel_crtc_state *crtc_state) 1548 { 1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1550 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1551 enum phy phy = intel_port_to_phy(i915, encoder->port); 1552 1553 if (drm_WARN_ON(&i915->drm, !pll)) 1554 return; 1555 1556 /* 1557 * If we fail this, something went very wrong: first 2 PLLs should be 1558 * used by first 2 phys and last 2 PLLs by last phys 1559 */ 1560 if (drm_WARN_ON(&i915->drm, 1561 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1562 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1563 return; 1564 1565 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1566 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1567 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1568 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1569 } 1570 1571 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1572 { 1573 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1574 enum phy phy = intel_port_to_phy(i915, encoder->port); 1575 1576 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1577 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1578 } 1579 1580 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1581 { 1582 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1583 enum phy phy = intel_port_to_phy(i915, encoder->port); 1584 1585 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1586 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1587 } 1588 1589 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1590 { 1591 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1592 enum phy phy = intel_port_to_phy(i915, encoder->port); 1593 enum intel_dpll_id id; 1594 u32 val; 1595 1596 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1597 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1598 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1599 id = val; 1600 1601 /* 1602 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1603 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1604 * bit for phy C and D. 1605 */ 1606 if (phy >= PHY_C) 1607 id += DPLL_ID_DG1_DPLL2; 1608 1609 return intel_get_shared_dpll_by_id(i915, id); 1610 } 1611 1612 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1613 const struct intel_crtc_state *crtc_state) 1614 { 1615 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1616 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1617 enum phy phy = intel_port_to_phy(i915, encoder->port); 1618 1619 if (drm_WARN_ON(&i915->drm, !pll)) 1620 return; 1621 1622 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1623 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1624 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1625 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1626 } 1627 1628 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1629 { 1630 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1631 enum phy phy = intel_port_to_phy(i915, encoder->port); 1632 1633 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1634 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1635 } 1636 1637 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1638 { 1639 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1640 enum phy phy = intel_port_to_phy(i915, encoder->port); 1641 1642 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1643 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1644 } 1645 1646 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1647 { 1648 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1649 enum phy phy = intel_port_to_phy(i915, encoder->port); 1650 1651 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1652 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1653 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1654 } 1655 1656 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1657 const struct intel_crtc_state *crtc_state) 1658 { 1659 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1660 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1661 enum port port = encoder->port; 1662 1663 if (drm_WARN_ON(&i915->drm, !pll)) 1664 return; 1665 1666 /* 1667 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1668 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1669 */ 1670 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1671 1672 icl_ddi_combo_enable_clock(encoder, crtc_state); 1673 } 1674 1675 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1676 { 1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1678 enum port port = encoder->port; 1679 1680 icl_ddi_combo_disable_clock(encoder); 1681 1682 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1683 } 1684 1685 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1686 { 1687 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1688 enum port port = encoder->port; 1689 u32 tmp; 1690 1691 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1692 1693 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1694 return false; 1695 1696 return icl_ddi_combo_is_clock_enabled(encoder); 1697 } 1698 1699 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1700 const struct intel_crtc_state *crtc_state) 1701 { 1702 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1703 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1704 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1705 enum port port = encoder->port; 1706 1707 if (drm_WARN_ON(&i915->drm, !pll)) 1708 return; 1709 1710 intel_de_write(i915, DDI_CLK_SEL(port), 1711 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1712 1713 mutex_lock(&i915->dpll.lock); 1714 1715 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1716 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1717 1718 mutex_unlock(&i915->dpll.lock); 1719 } 1720 1721 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1722 { 1723 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1724 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1725 enum port port = encoder->port; 1726 1727 mutex_lock(&i915->dpll.lock); 1728 1729 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1730 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1731 1732 mutex_unlock(&i915->dpll.lock); 1733 1734 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1735 } 1736 1737 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1738 { 1739 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1740 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1741 enum port port = encoder->port; 1742 u32 tmp; 1743 1744 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1745 1746 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1747 return false; 1748 1749 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1750 1751 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1752 } 1753 1754 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1755 { 1756 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1757 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1758 enum port port = encoder->port; 1759 enum intel_dpll_id id; 1760 u32 tmp; 1761 1762 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1763 1764 switch (tmp & DDI_CLK_SEL_MASK) { 1765 case DDI_CLK_SEL_TBT_162: 1766 case DDI_CLK_SEL_TBT_270: 1767 case DDI_CLK_SEL_TBT_540: 1768 case DDI_CLK_SEL_TBT_810: 1769 id = DPLL_ID_ICL_TBTPLL; 1770 break; 1771 case DDI_CLK_SEL_MG: 1772 id = icl_tc_port_to_pll_id(tc_port); 1773 break; 1774 default: 1775 MISSING_CASE(tmp); 1776 fallthrough; 1777 case DDI_CLK_SEL_NONE: 1778 return NULL; 1779 } 1780 1781 return intel_get_shared_dpll_by_id(i915, id); 1782 } 1783 1784 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1785 { 1786 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1787 enum intel_dpll_id id; 1788 1789 switch (encoder->port) { 1790 case PORT_A: 1791 id = DPLL_ID_SKL_DPLL0; 1792 break; 1793 case PORT_B: 1794 id = DPLL_ID_SKL_DPLL1; 1795 break; 1796 case PORT_C: 1797 id = DPLL_ID_SKL_DPLL2; 1798 break; 1799 default: 1800 MISSING_CASE(encoder->port); 1801 return NULL; 1802 } 1803 1804 return intel_get_shared_dpll_by_id(i915, id); 1805 } 1806 1807 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1808 const struct intel_crtc_state *crtc_state) 1809 { 1810 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1811 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1812 enum port port = encoder->port; 1813 1814 if (drm_WARN_ON(&i915->drm, !pll)) 1815 return; 1816 1817 mutex_lock(&i915->dpll.lock); 1818 1819 intel_de_rmw(i915, DPLL_CTRL2, 1820 DPLL_CTRL2_DDI_CLK_OFF(port) | 1821 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1822 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1823 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1824 1825 mutex_unlock(&i915->dpll.lock); 1826 } 1827 1828 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1829 { 1830 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1831 enum port port = encoder->port; 1832 1833 mutex_lock(&i915->dpll.lock); 1834 1835 intel_de_rmw(i915, DPLL_CTRL2, 1836 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1837 1838 mutex_unlock(&i915->dpll.lock); 1839 } 1840 1841 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1842 { 1843 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1844 enum port port = encoder->port; 1845 1846 /* 1847 * FIXME Not sure if the override affects both 1848 * the PLL selection and the CLK_OFF bit. 1849 */ 1850 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1851 } 1852 1853 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1854 { 1855 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1856 enum port port = encoder->port; 1857 enum intel_dpll_id id; 1858 u32 tmp; 1859 1860 tmp = intel_de_read(i915, DPLL_CTRL2); 1861 1862 /* 1863 * FIXME Not sure if the override affects both 1864 * the PLL selection and the CLK_OFF bit. 1865 */ 1866 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1867 return NULL; 1868 1869 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1870 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1871 1872 return intel_get_shared_dpll_by_id(i915, id); 1873 } 1874 1875 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1876 const struct intel_crtc_state *crtc_state) 1877 { 1878 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1879 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1880 enum port port = encoder->port; 1881 1882 if (drm_WARN_ON(&i915->drm, !pll)) 1883 return; 1884 1885 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1886 } 1887 1888 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1889 { 1890 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1891 enum port port = encoder->port; 1892 1893 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1894 } 1895 1896 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1897 { 1898 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1899 enum port port = encoder->port; 1900 1901 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1902 } 1903 1904 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1905 { 1906 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1907 enum port port = encoder->port; 1908 enum intel_dpll_id id; 1909 u32 tmp; 1910 1911 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1912 1913 switch (tmp & PORT_CLK_SEL_MASK) { 1914 case PORT_CLK_SEL_WRPLL1: 1915 id = DPLL_ID_WRPLL1; 1916 break; 1917 case PORT_CLK_SEL_WRPLL2: 1918 id = DPLL_ID_WRPLL2; 1919 break; 1920 case PORT_CLK_SEL_SPLL: 1921 id = DPLL_ID_SPLL; 1922 break; 1923 case PORT_CLK_SEL_LCPLL_810: 1924 id = DPLL_ID_LCPLL_810; 1925 break; 1926 case PORT_CLK_SEL_LCPLL_1350: 1927 id = DPLL_ID_LCPLL_1350; 1928 break; 1929 case PORT_CLK_SEL_LCPLL_2700: 1930 id = DPLL_ID_LCPLL_2700; 1931 break; 1932 default: 1933 MISSING_CASE(tmp); 1934 fallthrough; 1935 case PORT_CLK_SEL_NONE: 1936 return NULL; 1937 } 1938 1939 return intel_get_shared_dpll_by_id(i915, id); 1940 } 1941 1942 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1943 const struct intel_crtc_state *crtc_state) 1944 { 1945 if (encoder->enable_clock) 1946 encoder->enable_clock(encoder, crtc_state); 1947 } 1948 1949 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1950 { 1951 if (encoder->disable_clock) 1952 encoder->disable_clock(encoder); 1953 } 1954 1955 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1956 { 1957 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1958 u32 port_mask; 1959 bool ddi_clk_needed; 1960 1961 /* 1962 * In case of DP MST, we sanitize the primary encoder only, not the 1963 * virtual ones. 1964 */ 1965 if (encoder->type == INTEL_OUTPUT_DP_MST) 1966 return; 1967 1968 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1969 u8 pipe_mask; 1970 bool is_mst; 1971 1972 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1973 /* 1974 * In the unlikely case that BIOS enables DP in MST mode, just 1975 * warn since our MST HW readout is incomplete. 1976 */ 1977 if (drm_WARN_ON(&i915->drm, is_mst)) 1978 return; 1979 } 1980 1981 port_mask = BIT(encoder->port); 1982 ddi_clk_needed = encoder->base.crtc; 1983 1984 if (encoder->type == INTEL_OUTPUT_DSI) { 1985 struct intel_encoder *other_encoder; 1986 1987 port_mask = intel_dsi_encoder_ports(encoder); 1988 /* 1989 * Sanity check that we haven't incorrectly registered another 1990 * encoder using any of the ports of this DSI encoder. 1991 */ 1992 for_each_intel_encoder(&i915->drm, other_encoder) { 1993 if (other_encoder == encoder) 1994 continue; 1995 1996 if (drm_WARN_ON(&i915->drm, 1997 port_mask & BIT(other_encoder->port))) 1998 return; 1999 } 2000 /* 2001 * For DSI we keep the ddi clocks gated 2002 * except during enable/disable sequence. 2003 */ 2004 ddi_clk_needed = false; 2005 } 2006 2007 if (ddi_clk_needed || !encoder->is_clock_enabled || 2008 !encoder->is_clock_enabled(encoder)) 2009 return; 2010 2011 drm_notice(&i915->drm, 2012 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2013 encoder->base.base.id, encoder->base.name); 2014 2015 encoder->disable_clock(encoder); 2016 } 2017 2018 static void 2019 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2020 const struct intel_crtc_state *crtc_state) 2021 { 2022 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2023 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2024 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2025 u32 ln0, ln1, pin_assignment; 2026 u8 width; 2027 2028 if (!intel_phy_is_tc(dev_priv, phy) || 2029 intel_tc_port_in_tbt_alt_mode(dig_port)) 2030 return; 2031 2032 if (DISPLAY_VER(dev_priv) >= 12) { 2033 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2034 HIP_INDEX_VAL(tc_port, 0x0)); 2035 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2036 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2037 HIP_INDEX_VAL(tc_port, 0x1)); 2038 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2039 } else { 2040 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2041 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2042 } 2043 2044 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2045 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2046 2047 /* DPPATC */ 2048 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2049 width = crtc_state->lane_count; 2050 2051 switch (pin_assignment) { 2052 case 0x0: 2053 drm_WARN_ON(&dev_priv->drm, 2054 !intel_tc_port_in_legacy_mode(dig_port)); 2055 if (width == 1) { 2056 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2057 } else { 2058 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2059 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2060 } 2061 break; 2062 case 0x1: 2063 if (width == 4) { 2064 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2065 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2066 } 2067 break; 2068 case 0x2: 2069 if (width == 2) { 2070 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2071 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2072 } 2073 break; 2074 case 0x3: 2075 case 0x5: 2076 if (width == 1) { 2077 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2078 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2079 } else { 2080 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2081 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2082 } 2083 break; 2084 case 0x4: 2085 case 0x6: 2086 if (width == 1) { 2087 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2088 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2089 } else { 2090 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2091 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2092 } 2093 break; 2094 default: 2095 MISSING_CASE(pin_assignment); 2096 } 2097 2098 if (DISPLAY_VER(dev_priv) >= 12) { 2099 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2100 HIP_INDEX_VAL(tc_port, 0x0)); 2101 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2102 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2103 HIP_INDEX_VAL(tc_port, 0x1)); 2104 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2105 } else { 2106 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2107 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2108 } 2109 } 2110 2111 static enum transcoder 2112 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2113 { 2114 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2115 return crtc_state->mst_master_transcoder; 2116 else 2117 return crtc_state->cpu_transcoder; 2118 } 2119 2120 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2121 const struct intel_crtc_state *crtc_state) 2122 { 2123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2124 2125 if (DISPLAY_VER(dev_priv) >= 12) 2126 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2127 else 2128 return DP_TP_CTL(encoder->port); 2129 } 2130 2131 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2132 const struct intel_crtc_state *crtc_state) 2133 { 2134 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2135 2136 if (DISPLAY_VER(dev_priv) >= 12) 2137 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2138 else 2139 return DP_TP_STATUS(encoder->port); 2140 } 2141 2142 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2143 const struct intel_crtc_state *crtc_state, 2144 bool enable) 2145 { 2146 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2147 2148 if (!crtc_state->vrr.enable) 2149 return; 2150 2151 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2152 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2153 drm_dbg_kms(&i915->drm, 2154 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2155 enabledisable(enable)); 2156 } 2157 2158 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2159 const struct intel_crtc_state *crtc_state) 2160 { 2161 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2162 2163 if (!crtc_state->fec_enable) 2164 return; 2165 2166 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2167 drm_dbg_kms(&i915->drm, 2168 "Failed to set FEC_READY in the sink\n"); 2169 } 2170 2171 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2172 const struct intel_crtc_state *crtc_state) 2173 { 2174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2175 struct intel_dp *intel_dp; 2176 u32 val; 2177 2178 if (!crtc_state->fec_enable) 2179 return; 2180 2181 intel_dp = enc_to_intel_dp(encoder); 2182 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2183 val |= DP_TP_CTL_FEC_ENABLE; 2184 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2185 } 2186 2187 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2188 const struct intel_crtc_state *crtc_state) 2189 { 2190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2191 struct intel_dp *intel_dp; 2192 u32 val; 2193 2194 if (!crtc_state->fec_enable) 2195 return; 2196 2197 intel_dp = enc_to_intel_dp(encoder); 2198 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2199 val &= ~DP_TP_CTL_FEC_ENABLE; 2200 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2201 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2202 } 2203 2204 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2205 const struct intel_crtc_state *crtc_state) 2206 { 2207 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2208 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2209 enum phy phy = intel_port_to_phy(i915, encoder->port); 2210 2211 if (intel_phy_is_combo(i915, phy)) { 2212 bool lane_reversal = 2213 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2214 2215 intel_combo_phy_power_up_lanes(i915, phy, false, 2216 crtc_state->lane_count, 2217 lane_reversal); 2218 } 2219 } 2220 2221 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2222 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2223 { 2224 if (IS_ALDERLAKE_P(i915)) 2225 return BIT(PIPE_A) | BIT(PIPE_B); 2226 else 2227 return BIT(PIPE_A); 2228 } 2229 2230 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2231 struct intel_crtc_state *pipe_config) 2232 { 2233 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2234 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2235 enum pipe pipe = crtc->pipe; 2236 u32 dss1; 2237 2238 if (!HAS_MSO(i915)) 2239 return; 2240 2241 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2242 2243 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2244 if (!pipe_config->splitter.enable) 2245 return; 2246 2247 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2248 pipe_config->splitter.enable = false; 2249 return; 2250 } 2251 2252 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2253 default: 2254 drm_WARN(&i915->drm, true, 2255 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2256 fallthrough; 2257 case SPLITTER_CONFIGURATION_2_SEGMENT: 2258 pipe_config->splitter.link_count = 2; 2259 break; 2260 case SPLITTER_CONFIGURATION_4_SEGMENT: 2261 pipe_config->splitter.link_count = 4; 2262 break; 2263 } 2264 2265 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2266 } 2267 2268 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2269 { 2270 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2271 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2272 enum pipe pipe = crtc->pipe; 2273 u32 dss1 = 0; 2274 2275 if (!HAS_MSO(i915)) 2276 return; 2277 2278 if (crtc_state->splitter.enable) { 2279 dss1 |= SPLITTER_ENABLE; 2280 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2281 if (crtc_state->splitter.link_count == 2) 2282 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2283 else 2284 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2285 } 2286 2287 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2288 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2289 OVERLAP_PIXELS_MASK, dss1); 2290 } 2291 2292 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2293 struct intel_encoder *encoder, 2294 const struct intel_crtc_state *crtc_state, 2295 const struct drm_connector_state *conn_state) 2296 { 2297 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2299 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2300 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2301 2302 intel_dp_set_link_params(intel_dp, 2303 crtc_state->port_clock, 2304 crtc_state->lane_count); 2305 2306 /* 2307 * We only configure what the register value will be here. Actual 2308 * enabling happens during link training farther down. 2309 */ 2310 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2311 2312 /* 2313 * 1. Enable Power Wells 2314 * 2315 * This was handled at the beginning of intel_atomic_commit_tail(), 2316 * before we called down into this function. 2317 */ 2318 2319 /* 2. Enable Panel Power if PPS is required */ 2320 intel_pps_on(intel_dp); 2321 2322 /* 2323 * 3. For non-TBT Type-C ports, set FIA lane count 2324 * (DFLEXDPSP.DPX4TXLATC) 2325 * 2326 * This was done before tgl_ddi_pre_enable_dp by 2327 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2328 */ 2329 2330 /* 2331 * 4. Enable the port PLL. 2332 * 2333 * The PLL enabling itself was already done before this function by 2334 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2335 * configure the PLL to port mapping here. 2336 */ 2337 intel_ddi_enable_clock(encoder, crtc_state); 2338 2339 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2340 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2341 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2342 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2343 dig_port->ddi_io_power_domain); 2344 } 2345 2346 /* 6. Program DP_MODE */ 2347 icl_program_mg_dp_mode(dig_port, crtc_state); 2348 2349 /* 2350 * 7. The rest of the below are substeps under the bspec's "Enable and 2351 * Train Display Port" step. Note that steps that are specific to 2352 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2353 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2354 * us when active_mst_links==0, so any steps designated for "single 2355 * stream or multi-stream master transcoder" can just be performed 2356 * unconditionally here. 2357 */ 2358 2359 /* 2360 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2361 * Transcoder. 2362 */ 2363 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2364 2365 if (HAS_DP20(dev_priv)) 2366 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2367 2368 /* 2369 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2370 * Transport Select 2371 */ 2372 intel_ddi_config_transcoder_func(encoder, crtc_state); 2373 2374 /* 2375 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2376 * selected 2377 * 2378 * This will be handled by the intel_dp_start_link_train() farther 2379 * down this function. 2380 */ 2381 2382 /* 7.e Configure voltage swing and related IO settings */ 2383 encoder->set_signal_levels(encoder, crtc_state); 2384 2385 /* 2386 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2387 * the used lanes of the DDI. 2388 */ 2389 intel_ddi_power_up_lanes(encoder, crtc_state); 2390 2391 /* 2392 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2393 */ 2394 intel_ddi_mso_configure(crtc_state); 2395 2396 if (!is_mst) 2397 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2398 2399 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2400 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2401 /* 2402 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2403 * in the FEC_CONFIGURATION register to 1 before initiating link 2404 * training 2405 */ 2406 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2407 2408 intel_dp_check_frl_training(intel_dp); 2409 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2410 2411 /* 2412 * 7.i Follow DisplayPort specification training sequence (see notes for 2413 * failure handling) 2414 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2415 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2416 * (timeout after 800 us) 2417 */ 2418 intel_dp_start_link_train(intel_dp, crtc_state); 2419 2420 /* 7.k Set DP_TP_CTL link training to Normal */ 2421 if (!is_trans_port_sync_mode(crtc_state)) 2422 intel_dp_stop_link_train(intel_dp, crtc_state); 2423 2424 /* 7.l Configure and enable FEC if needed */ 2425 intel_ddi_enable_fec(encoder, crtc_state); 2426 2427 intel_dsc_dp_pps_write(encoder, crtc_state); 2428 } 2429 2430 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2431 struct intel_encoder *encoder, 2432 const struct intel_crtc_state *crtc_state, 2433 const struct drm_connector_state *conn_state) 2434 { 2435 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2436 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2437 enum port port = encoder->port; 2438 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2439 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2440 2441 if (DISPLAY_VER(dev_priv) < 11) 2442 drm_WARN_ON(&dev_priv->drm, 2443 is_mst && (port == PORT_A || port == PORT_E)); 2444 else 2445 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2446 2447 intel_dp_set_link_params(intel_dp, 2448 crtc_state->port_clock, 2449 crtc_state->lane_count); 2450 2451 /* 2452 * We only configure what the register value will be here. Actual 2453 * enabling happens during link training farther down. 2454 */ 2455 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2456 2457 intel_pps_on(intel_dp); 2458 2459 intel_ddi_enable_clock(encoder, crtc_state); 2460 2461 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2462 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2463 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2464 dig_port->ddi_io_power_domain); 2465 } 2466 2467 icl_program_mg_dp_mode(dig_port, crtc_state); 2468 2469 if (has_buf_trans_select(dev_priv)) 2470 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2471 2472 encoder->set_signal_levels(encoder, crtc_state); 2473 2474 intel_ddi_power_up_lanes(encoder, crtc_state); 2475 2476 if (!is_mst) 2477 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2478 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2479 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2480 true); 2481 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2482 intel_dp_start_link_train(intel_dp, crtc_state); 2483 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2484 !is_trans_port_sync_mode(crtc_state)) 2485 intel_dp_stop_link_train(intel_dp, crtc_state); 2486 2487 intel_ddi_enable_fec(encoder, crtc_state); 2488 2489 if (!is_mst) 2490 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2491 2492 intel_dsc_dp_pps_write(encoder, crtc_state); 2493 } 2494 2495 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2496 struct intel_encoder *encoder, 2497 const struct intel_crtc_state *crtc_state, 2498 const struct drm_connector_state *conn_state) 2499 { 2500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2501 2502 if (DISPLAY_VER(dev_priv) >= 12) 2503 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2504 else 2505 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2506 2507 /* MST will call a setting of MSA after an allocating of Virtual Channel 2508 * from MST encoder pre_enable callback. 2509 */ 2510 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2511 intel_ddi_set_dp_msa(crtc_state, conn_state); 2512 } 2513 2514 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2515 struct intel_encoder *encoder, 2516 const struct intel_crtc_state *crtc_state, 2517 const struct drm_connector_state *conn_state) 2518 { 2519 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2520 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2521 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2522 2523 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2524 intel_ddi_enable_clock(encoder, crtc_state); 2525 2526 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2527 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2528 dig_port->ddi_io_power_domain); 2529 2530 icl_program_mg_dp_mode(dig_port, crtc_state); 2531 2532 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2533 2534 dig_port->set_infoframes(encoder, 2535 crtc_state->has_infoframe, 2536 crtc_state, conn_state); 2537 } 2538 2539 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2540 struct intel_encoder *encoder, 2541 const struct intel_crtc_state *crtc_state, 2542 const struct drm_connector_state *conn_state) 2543 { 2544 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2546 enum pipe pipe = crtc->pipe; 2547 2548 /* 2549 * When called from DP MST code: 2550 * - conn_state will be NULL 2551 * - encoder will be the main encoder (ie. mst->primary) 2552 * - the main connector associated with this port 2553 * won't be active or linked to a crtc 2554 * - crtc_state will be the state of the first stream to 2555 * be activated on this port, and it may not be the same 2556 * stream that will be deactivated last, but each stream 2557 * should have a state that is identical when it comes to 2558 * the DP link parameteres 2559 */ 2560 2561 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2562 2563 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2564 2565 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2566 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2567 conn_state); 2568 } else { 2569 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2570 2571 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2572 conn_state); 2573 2574 /* FIXME precompute everything properly */ 2575 /* FIXME how do we turn infoframes off again? */ 2576 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2577 dig_port->set_infoframes(encoder, 2578 crtc_state->has_infoframe, 2579 crtc_state, conn_state); 2580 } 2581 } 2582 2583 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2584 const struct intel_crtc_state *crtc_state) 2585 { 2586 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2587 enum port port = encoder->port; 2588 bool wait = false; 2589 u32 val; 2590 2591 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2592 if (val & DDI_BUF_CTL_ENABLE) { 2593 val &= ~DDI_BUF_CTL_ENABLE; 2594 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2595 wait = true; 2596 } 2597 2598 if (intel_crtc_has_dp_encoder(crtc_state)) { 2599 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2600 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2601 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2602 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2603 } 2604 2605 /* Disable FEC in DP Sink */ 2606 intel_ddi_disable_fec_state(encoder, crtc_state); 2607 2608 if (wait) 2609 intel_wait_ddi_buf_idle(dev_priv, port); 2610 } 2611 2612 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2613 struct intel_encoder *encoder, 2614 const struct intel_crtc_state *old_crtc_state, 2615 const struct drm_connector_state *old_conn_state) 2616 { 2617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2618 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2619 struct intel_dp *intel_dp = &dig_port->dp; 2620 bool is_mst = intel_crtc_has_type(old_crtc_state, 2621 INTEL_OUTPUT_DP_MST); 2622 2623 if (!is_mst) 2624 intel_dp_set_infoframes(encoder, false, 2625 old_crtc_state, old_conn_state); 2626 2627 /* 2628 * Power down sink before disabling the port, otherwise we end 2629 * up getting interrupts from the sink on detecting link loss. 2630 */ 2631 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2632 2633 if (DISPLAY_VER(dev_priv) >= 12) { 2634 if (is_mst) { 2635 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2636 u32 val; 2637 2638 val = intel_de_read(dev_priv, 2639 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2640 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2641 TRANS_DDI_MODE_SELECT_MASK); 2642 intel_de_write(dev_priv, 2643 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2644 val); 2645 } 2646 } else { 2647 if (!is_mst) 2648 intel_ddi_disable_pipe_clock(old_crtc_state); 2649 } 2650 2651 intel_disable_ddi_buf(encoder, old_crtc_state); 2652 2653 /* 2654 * From TGL spec: "If single stream or multi-stream master transcoder: 2655 * Configure Transcoder Clock select to direct no clock to the 2656 * transcoder" 2657 */ 2658 if (DISPLAY_VER(dev_priv) >= 12) 2659 intel_ddi_disable_pipe_clock(old_crtc_state); 2660 2661 intel_pps_vdd_on(intel_dp); 2662 intel_pps_off(intel_dp); 2663 2664 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2665 intel_display_power_put(dev_priv, 2666 dig_port->ddi_io_power_domain, 2667 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2668 2669 intel_ddi_disable_clock(encoder); 2670 } 2671 2672 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2673 struct intel_encoder *encoder, 2674 const struct intel_crtc_state *old_crtc_state, 2675 const struct drm_connector_state *old_conn_state) 2676 { 2677 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2678 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2679 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2680 2681 dig_port->set_infoframes(encoder, false, 2682 old_crtc_state, old_conn_state); 2683 2684 intel_ddi_disable_pipe_clock(old_crtc_state); 2685 2686 intel_disable_ddi_buf(encoder, old_crtc_state); 2687 2688 intel_display_power_put(dev_priv, 2689 dig_port->ddi_io_power_domain, 2690 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2691 2692 intel_ddi_disable_clock(encoder); 2693 2694 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2695 } 2696 2697 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2698 struct intel_encoder *encoder, 2699 const struct intel_crtc_state *old_crtc_state, 2700 const struct drm_connector_state *old_conn_state) 2701 { 2702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2703 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2704 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2705 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2706 2707 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2708 intel_crtc_vblank_off(old_crtc_state); 2709 2710 intel_disable_transcoder(old_crtc_state); 2711 2712 intel_vrr_disable(old_crtc_state); 2713 2714 intel_ddi_disable_transcoder_func(old_crtc_state); 2715 2716 intel_dsc_disable(old_crtc_state); 2717 2718 if (DISPLAY_VER(dev_priv) >= 9) 2719 skl_scaler_disable(old_crtc_state); 2720 else 2721 ilk_pfit_disable(old_crtc_state); 2722 } 2723 2724 if (old_crtc_state->bigjoiner_linked_crtc) { 2725 struct intel_crtc *slave_crtc = 2726 old_crtc_state->bigjoiner_linked_crtc; 2727 const struct intel_crtc_state *old_slave_crtc_state = 2728 intel_atomic_get_old_crtc_state(state, slave_crtc); 2729 2730 intel_crtc_vblank_off(old_slave_crtc_state); 2731 2732 intel_dsc_disable(old_slave_crtc_state); 2733 skl_scaler_disable(old_slave_crtc_state); 2734 } 2735 2736 /* 2737 * When called from DP MST code: 2738 * - old_conn_state will be NULL 2739 * - encoder will be the main encoder (ie. mst->primary) 2740 * - the main connector associated with this port 2741 * won't be active or linked to a crtc 2742 * - old_crtc_state will be the state of the last stream to 2743 * be deactivated on this port, and it may not be the same 2744 * stream that was activated last, but each stream 2745 * should have a state that is identical when it comes to 2746 * the DP link parameteres 2747 */ 2748 2749 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2750 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2751 old_conn_state); 2752 else 2753 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2754 old_conn_state); 2755 2756 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2757 intel_display_power_put(dev_priv, 2758 intel_ddi_main_link_aux_domain(dig_port), 2759 fetch_and_zero(&dig_port->aux_wakeref)); 2760 2761 if (is_tc_port) 2762 intel_tc_port_put_link(dig_port); 2763 } 2764 2765 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2766 struct intel_encoder *encoder, 2767 const struct intel_crtc_state *crtc_state) 2768 { 2769 const struct drm_connector_state *conn_state; 2770 struct drm_connector *conn; 2771 int i; 2772 2773 if (!crtc_state->sync_mode_slaves_mask) 2774 return; 2775 2776 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2777 struct intel_encoder *slave_encoder = 2778 to_intel_encoder(conn_state->best_encoder); 2779 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2780 const struct intel_crtc_state *slave_crtc_state; 2781 2782 if (!slave_crtc) 2783 continue; 2784 2785 slave_crtc_state = 2786 intel_atomic_get_new_crtc_state(state, slave_crtc); 2787 2788 if (slave_crtc_state->master_transcoder != 2789 crtc_state->cpu_transcoder) 2790 continue; 2791 2792 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2793 slave_crtc_state); 2794 } 2795 2796 usleep_range(200, 400); 2797 2798 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2799 crtc_state); 2800 } 2801 2802 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2803 struct intel_encoder *encoder, 2804 const struct intel_crtc_state *crtc_state, 2805 const struct drm_connector_state *conn_state) 2806 { 2807 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2808 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2809 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2810 enum port port = encoder->port; 2811 2812 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2813 intel_dp_stop_link_train(intel_dp, crtc_state); 2814 2815 drm_connector_update_privacy_screen(conn_state); 2816 intel_edp_backlight_on(crtc_state, conn_state); 2817 2818 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2819 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2820 2821 intel_drrs_enable(intel_dp, crtc_state); 2822 2823 if (crtc_state->has_audio) 2824 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2825 2826 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2827 } 2828 2829 static i915_reg_t 2830 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2831 enum port port) 2832 { 2833 static const enum transcoder trans[] = { 2834 [PORT_A] = TRANSCODER_EDP, 2835 [PORT_B] = TRANSCODER_A, 2836 [PORT_C] = TRANSCODER_B, 2837 [PORT_D] = TRANSCODER_C, 2838 [PORT_E] = TRANSCODER_A, 2839 }; 2840 2841 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2842 2843 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2844 port = PORT_A; 2845 2846 return CHICKEN_TRANS(trans[port]); 2847 } 2848 2849 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2850 struct intel_encoder *encoder, 2851 const struct intel_crtc_state *crtc_state, 2852 const struct drm_connector_state *conn_state) 2853 { 2854 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2855 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2856 struct drm_connector *connector = conn_state->connector; 2857 enum port port = encoder->port; 2858 2859 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2860 crtc_state->hdmi_high_tmds_clock_ratio, 2861 crtc_state->hdmi_scrambling)) 2862 drm_dbg_kms(&dev_priv->drm, 2863 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2864 connector->base.id, connector->name); 2865 2866 if (has_buf_trans_select(dev_priv)) 2867 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2868 2869 encoder->set_signal_levels(encoder, crtc_state); 2870 2871 /* Display WA #1143: skl,kbl,cfl */ 2872 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2873 /* 2874 * For some reason these chicken bits have been 2875 * stuffed into a transcoder register, event though 2876 * the bits affect a specific DDI port rather than 2877 * a specific transcoder. 2878 */ 2879 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2880 u32 val; 2881 2882 val = intel_de_read(dev_priv, reg); 2883 2884 if (port == PORT_E) 2885 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2886 DDIE_TRAINING_OVERRIDE_VALUE; 2887 else 2888 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2889 DDI_TRAINING_OVERRIDE_VALUE; 2890 2891 intel_de_write(dev_priv, reg, val); 2892 intel_de_posting_read(dev_priv, reg); 2893 2894 udelay(1); 2895 2896 if (port == PORT_E) 2897 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2898 DDIE_TRAINING_OVERRIDE_VALUE); 2899 else 2900 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2901 DDI_TRAINING_OVERRIDE_VALUE); 2902 2903 intel_de_write(dev_priv, reg, val); 2904 } 2905 2906 intel_ddi_power_up_lanes(encoder, crtc_state); 2907 2908 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2909 * are ignored so nothing special needs to be done besides 2910 * enabling the port. 2911 * 2912 * On ADL_P the PHY link rate and lane count must be programmed but 2913 * these are both 0 for HDMI. 2914 */ 2915 intel_de_write(dev_priv, DDI_BUF_CTL(port), 2916 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 2917 2918 if (crtc_state->has_audio) 2919 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2920 } 2921 2922 static void intel_enable_ddi(struct intel_atomic_state *state, 2923 struct intel_encoder *encoder, 2924 const struct intel_crtc_state *crtc_state, 2925 const struct drm_connector_state *conn_state) 2926 { 2927 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2928 2929 if (!crtc_state->bigjoiner_slave) 2930 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2931 2932 intel_vrr_enable(encoder, crtc_state); 2933 2934 intel_enable_transcoder(crtc_state); 2935 2936 intel_crtc_vblank_on(crtc_state); 2937 2938 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2939 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2940 else 2941 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2942 2943 /* Enable hdcp if it's desired */ 2944 if (conn_state->content_protection == 2945 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2946 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2947 crtc_state, 2948 (u8)conn_state->hdcp_content_type); 2949 } 2950 2951 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2952 struct intel_encoder *encoder, 2953 const struct intel_crtc_state *old_crtc_state, 2954 const struct drm_connector_state *old_conn_state) 2955 { 2956 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2957 2958 intel_dp->link_trained = false; 2959 2960 if (old_crtc_state->has_audio) 2961 intel_audio_codec_disable(encoder, 2962 old_crtc_state, old_conn_state); 2963 2964 intel_drrs_disable(intel_dp, old_crtc_state); 2965 intel_psr_disable(intel_dp, old_crtc_state); 2966 intel_edp_backlight_off(old_conn_state); 2967 /* Disable the decompression in DP Sink */ 2968 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2969 false); 2970 /* Disable Ignore_MSA bit in DP Sink */ 2971 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2972 false); 2973 } 2974 2975 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2976 struct intel_encoder *encoder, 2977 const struct intel_crtc_state *old_crtc_state, 2978 const struct drm_connector_state *old_conn_state) 2979 { 2980 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2981 struct drm_connector *connector = old_conn_state->connector; 2982 2983 if (old_crtc_state->has_audio) 2984 intel_audio_codec_disable(encoder, 2985 old_crtc_state, old_conn_state); 2986 2987 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2988 false, false)) 2989 drm_dbg_kms(&i915->drm, 2990 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 2991 connector->base.id, connector->name); 2992 } 2993 2994 static void intel_disable_ddi(struct intel_atomic_state *state, 2995 struct intel_encoder *encoder, 2996 const struct intel_crtc_state *old_crtc_state, 2997 const struct drm_connector_state *old_conn_state) 2998 { 2999 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3000 3001 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3002 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3003 old_conn_state); 3004 else 3005 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3006 old_conn_state); 3007 } 3008 3009 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3010 struct intel_encoder *encoder, 3011 const struct intel_crtc_state *crtc_state, 3012 const struct drm_connector_state *conn_state) 3013 { 3014 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3015 3016 intel_ddi_set_dp_msa(crtc_state, conn_state); 3017 3018 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3019 intel_drrs_update(intel_dp, crtc_state); 3020 3021 intel_backlight_update(state, encoder, crtc_state, conn_state); 3022 drm_connector_update_privacy_screen(conn_state); 3023 } 3024 3025 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3026 struct intel_encoder *encoder, 3027 const struct intel_crtc_state *crtc_state, 3028 const struct drm_connector_state *conn_state) 3029 { 3030 3031 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3032 !intel_encoder_is_mst(encoder)) 3033 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3034 conn_state); 3035 3036 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3037 } 3038 3039 static void 3040 intel_ddi_update_prepare(struct intel_atomic_state *state, 3041 struct intel_encoder *encoder, 3042 struct intel_crtc *crtc) 3043 { 3044 struct intel_crtc_state *crtc_state = 3045 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3046 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3047 3048 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3049 3050 intel_tc_port_get_link(enc_to_dig_port(encoder), 3051 required_lanes); 3052 if (crtc_state && crtc_state->hw.active) { 3053 struct intel_crtc *slave_crtc = crtc_state->bigjoiner_linked_crtc; 3054 3055 intel_update_active_dpll(state, crtc, encoder); 3056 3057 if (slave_crtc) 3058 intel_update_active_dpll(state, slave_crtc, encoder); 3059 } 3060 } 3061 3062 static void 3063 intel_ddi_update_complete(struct intel_atomic_state *state, 3064 struct intel_encoder *encoder, 3065 struct intel_crtc *crtc) 3066 { 3067 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3068 } 3069 3070 static void 3071 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3072 struct intel_encoder *encoder, 3073 const struct intel_crtc_state *crtc_state, 3074 const struct drm_connector_state *conn_state) 3075 { 3076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3077 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3078 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3079 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3080 3081 if (is_tc_port) 3082 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3083 3084 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3085 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3086 dig_port->aux_wakeref = 3087 intel_display_power_get(dev_priv, 3088 intel_ddi_main_link_aux_domain(dig_port)); 3089 } 3090 3091 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3092 /* 3093 * Program the lane count for static/dynamic connections on 3094 * Type-C ports. Skip this step for TBT. 3095 */ 3096 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3097 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3098 bxt_ddi_phy_set_lane_optim_mask(encoder, 3099 crtc_state->lane_lat_optim_mask); 3100 } 3101 3102 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3103 const struct intel_crtc_state *crtc_state) 3104 { 3105 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3107 enum port port = encoder->port; 3108 u32 dp_tp_ctl, ddi_buf_ctl; 3109 bool wait = false; 3110 3111 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3112 3113 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3114 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3115 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3116 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3117 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3118 wait = true; 3119 } 3120 3121 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3122 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3123 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3124 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3125 3126 if (wait) 3127 intel_wait_ddi_buf_idle(dev_priv, port); 3128 } 3129 3130 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3131 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3132 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3133 } else { 3134 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3135 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3136 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3137 } 3138 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3139 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3140 3141 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3142 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3143 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3144 3145 intel_wait_ddi_buf_active(dev_priv, port); 3146 } 3147 3148 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3149 const struct intel_crtc_state *crtc_state, 3150 u8 dp_train_pat) 3151 { 3152 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3154 u32 temp; 3155 3156 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3157 3158 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3159 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3160 case DP_TRAINING_PATTERN_DISABLE: 3161 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3162 break; 3163 case DP_TRAINING_PATTERN_1: 3164 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3165 break; 3166 case DP_TRAINING_PATTERN_2: 3167 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3168 break; 3169 case DP_TRAINING_PATTERN_3: 3170 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3171 break; 3172 case DP_TRAINING_PATTERN_4: 3173 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3174 break; 3175 } 3176 3177 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3178 } 3179 3180 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3181 const struct intel_crtc_state *crtc_state) 3182 { 3183 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3185 enum port port = encoder->port; 3186 u32 val; 3187 3188 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3189 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3190 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3191 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3192 3193 /* 3194 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3195 * reason we need to set idle transmission mode is to work around a HW 3196 * issue where we enable the pipe while not in idle link-training mode. 3197 * In this case there is requirement to wait for a minimum number of 3198 * idle patterns to be sent. 3199 */ 3200 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3201 return; 3202 3203 if (intel_de_wait_for_set(dev_priv, 3204 dp_tp_status_reg(encoder, crtc_state), 3205 DP_TP_STATUS_IDLE_DONE, 1)) 3206 drm_err(&dev_priv->drm, 3207 "Timed out waiting for DP idle patterns\n"); 3208 } 3209 3210 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3211 enum transcoder cpu_transcoder) 3212 { 3213 if (cpu_transcoder == TRANSCODER_EDP) 3214 return false; 3215 3216 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3217 return false; 3218 3219 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3220 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3221 } 3222 3223 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3224 struct intel_crtc_state *crtc_state) 3225 { 3226 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3227 crtc_state->min_voltage_level = 2; 3228 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3229 crtc_state->min_voltage_level = 3; 3230 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3231 crtc_state->min_voltage_level = 1; 3232 } 3233 3234 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3235 enum transcoder cpu_transcoder) 3236 { 3237 u32 master_select; 3238 3239 if (DISPLAY_VER(dev_priv) >= 11) { 3240 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3241 3242 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3243 return INVALID_TRANSCODER; 3244 3245 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3246 } else { 3247 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3248 3249 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3250 return INVALID_TRANSCODER; 3251 3252 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3253 } 3254 3255 if (master_select == 0) 3256 return TRANSCODER_EDP; 3257 else 3258 return master_select - 1; 3259 } 3260 3261 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3262 { 3263 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3264 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3265 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3266 enum transcoder cpu_transcoder; 3267 3268 crtc_state->master_transcoder = 3269 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3270 3271 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3272 enum intel_display_power_domain power_domain; 3273 intel_wakeref_t trans_wakeref; 3274 3275 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3276 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3277 power_domain); 3278 3279 if (!trans_wakeref) 3280 continue; 3281 3282 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3283 crtc_state->cpu_transcoder) 3284 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3285 3286 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3287 } 3288 3289 drm_WARN_ON(&dev_priv->drm, 3290 crtc_state->master_transcoder != INVALID_TRANSCODER && 3291 crtc_state->sync_mode_slaves_mask); 3292 } 3293 3294 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3295 struct intel_crtc_state *pipe_config) 3296 { 3297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3298 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3299 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3300 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3301 u32 temp, flags = 0; 3302 3303 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3304 if (temp & TRANS_DDI_PHSYNC) 3305 flags |= DRM_MODE_FLAG_PHSYNC; 3306 else 3307 flags |= DRM_MODE_FLAG_NHSYNC; 3308 if (temp & TRANS_DDI_PVSYNC) 3309 flags |= DRM_MODE_FLAG_PVSYNC; 3310 else 3311 flags |= DRM_MODE_FLAG_NVSYNC; 3312 3313 pipe_config->hw.adjusted_mode.flags |= flags; 3314 3315 switch (temp & TRANS_DDI_BPC_MASK) { 3316 case TRANS_DDI_BPC_6: 3317 pipe_config->pipe_bpp = 18; 3318 break; 3319 case TRANS_DDI_BPC_8: 3320 pipe_config->pipe_bpp = 24; 3321 break; 3322 case TRANS_DDI_BPC_10: 3323 pipe_config->pipe_bpp = 30; 3324 break; 3325 case TRANS_DDI_BPC_12: 3326 pipe_config->pipe_bpp = 36; 3327 break; 3328 default: 3329 break; 3330 } 3331 3332 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3333 case TRANS_DDI_MODE_SELECT_HDMI: 3334 pipe_config->has_hdmi_sink = true; 3335 3336 pipe_config->infoframes.enable |= 3337 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3338 3339 if (pipe_config->infoframes.enable) 3340 pipe_config->has_infoframe = true; 3341 3342 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3343 pipe_config->hdmi_scrambling = true; 3344 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3345 pipe_config->hdmi_high_tmds_clock_ratio = true; 3346 fallthrough; 3347 case TRANS_DDI_MODE_SELECT_DVI: 3348 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3349 pipe_config->lane_count = 4; 3350 break; 3351 case TRANS_DDI_MODE_SELECT_DP_SST: 3352 if (encoder->type == INTEL_OUTPUT_EDP) 3353 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3354 else 3355 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3356 pipe_config->lane_count = 3357 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3358 3359 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3360 &pipe_config->dp_m_n); 3361 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3362 &pipe_config->dp_m2_n2); 3363 3364 if (DISPLAY_VER(dev_priv) >= 11) { 3365 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3366 3367 pipe_config->fec_enable = 3368 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3369 3370 drm_dbg_kms(&dev_priv->drm, 3371 "[ENCODER:%d:%s] Fec status: %u\n", 3372 encoder->base.base.id, encoder->base.name, 3373 pipe_config->fec_enable); 3374 } 3375 3376 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3377 pipe_config->infoframes.enable |= 3378 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3379 else 3380 pipe_config->infoframes.enable |= 3381 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3382 break; 3383 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3384 if (!HAS_DP20(dev_priv)) { 3385 /* FDI */ 3386 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3387 break; 3388 } 3389 fallthrough; /* 128b/132b */ 3390 case TRANS_DDI_MODE_SELECT_DP_MST: 3391 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3392 pipe_config->lane_count = 3393 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3394 3395 if (DISPLAY_VER(dev_priv) >= 12) 3396 pipe_config->mst_master_transcoder = 3397 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3398 3399 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3400 &pipe_config->dp_m_n); 3401 3402 pipe_config->infoframes.enable |= 3403 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3404 break; 3405 default: 3406 break; 3407 } 3408 } 3409 3410 static void intel_ddi_get_config(struct intel_encoder *encoder, 3411 struct intel_crtc_state *pipe_config) 3412 { 3413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3414 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3415 3416 /* XXX: DSI transcoder paranoia */ 3417 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3418 return; 3419 3420 intel_ddi_read_func_ctl(encoder, pipe_config); 3421 3422 intel_ddi_mso_get_config(encoder, pipe_config); 3423 3424 pipe_config->has_audio = 3425 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3426 3427 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3428 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3429 /* 3430 * This is a big fat ugly hack. 3431 * 3432 * Some machines in UEFI boot mode provide us a VBT that has 18 3433 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3434 * unknown we fail to light up. Yet the same BIOS boots up with 3435 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3436 * max, not what it tells us to use. 3437 * 3438 * Note: This will still be broken if the eDP panel is not lit 3439 * up by the BIOS, and thus we can't get the mode at module 3440 * load. 3441 */ 3442 drm_dbg_kms(&dev_priv->drm, 3443 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3444 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3445 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3446 } 3447 3448 ddi_dotclock_get(pipe_config); 3449 3450 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3451 pipe_config->lane_lat_optim_mask = 3452 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3453 3454 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3455 3456 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3457 3458 intel_read_infoframe(encoder, pipe_config, 3459 HDMI_INFOFRAME_TYPE_AVI, 3460 &pipe_config->infoframes.avi); 3461 intel_read_infoframe(encoder, pipe_config, 3462 HDMI_INFOFRAME_TYPE_SPD, 3463 &pipe_config->infoframes.spd); 3464 intel_read_infoframe(encoder, pipe_config, 3465 HDMI_INFOFRAME_TYPE_VENDOR, 3466 &pipe_config->infoframes.hdmi); 3467 intel_read_infoframe(encoder, pipe_config, 3468 HDMI_INFOFRAME_TYPE_DRM, 3469 &pipe_config->infoframes.drm); 3470 3471 if (DISPLAY_VER(dev_priv) >= 8) 3472 bdw_get_trans_port_sync_config(pipe_config); 3473 3474 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3475 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3476 3477 intel_psr_get_config(encoder, pipe_config); 3478 } 3479 3480 void intel_ddi_get_clock(struct intel_encoder *encoder, 3481 struct intel_crtc_state *crtc_state, 3482 struct intel_shared_dpll *pll) 3483 { 3484 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3485 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3486 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3487 bool pll_active; 3488 3489 if (drm_WARN_ON(&i915->drm, !pll)) 3490 return; 3491 3492 port_dpll->pll = pll; 3493 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3494 drm_WARN_ON(&i915->drm, !pll_active); 3495 3496 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3497 3498 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3499 &crtc_state->dpll_hw_state); 3500 } 3501 3502 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3503 struct intel_crtc_state *crtc_state) 3504 { 3505 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3506 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3507 3508 intel_ddi_get_config(encoder, crtc_state); 3509 } 3510 3511 static void adls_ddi_get_config(struct intel_encoder *encoder, 3512 struct intel_crtc_state *crtc_state) 3513 { 3514 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3515 intel_ddi_get_config(encoder, crtc_state); 3516 } 3517 3518 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3519 struct intel_crtc_state *crtc_state) 3520 { 3521 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3522 intel_ddi_get_config(encoder, crtc_state); 3523 } 3524 3525 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3526 struct intel_crtc_state *crtc_state) 3527 { 3528 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3529 intel_ddi_get_config(encoder, crtc_state); 3530 } 3531 3532 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3533 struct intel_crtc_state *crtc_state) 3534 { 3535 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3536 intel_ddi_get_config(encoder, crtc_state); 3537 } 3538 3539 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3540 struct intel_crtc_state *crtc_state, 3541 struct intel_shared_dpll *pll) 3542 { 3543 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3544 enum icl_port_dpll_id port_dpll_id; 3545 struct icl_port_dpll *port_dpll; 3546 bool pll_active; 3547 3548 if (drm_WARN_ON(&i915->drm, !pll)) 3549 return; 3550 3551 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3552 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3553 else 3554 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3555 3556 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3557 3558 port_dpll->pll = pll; 3559 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3560 drm_WARN_ON(&i915->drm, !pll_active); 3561 3562 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3563 3564 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3565 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3566 else 3567 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3568 &crtc_state->dpll_hw_state); 3569 } 3570 3571 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3572 struct intel_crtc_state *crtc_state) 3573 { 3574 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3575 intel_ddi_get_config(encoder, crtc_state); 3576 } 3577 3578 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3579 struct intel_crtc_state *crtc_state) 3580 { 3581 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3582 intel_ddi_get_config(encoder, crtc_state); 3583 } 3584 3585 static void skl_ddi_get_config(struct intel_encoder *encoder, 3586 struct intel_crtc_state *crtc_state) 3587 { 3588 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3589 intel_ddi_get_config(encoder, crtc_state); 3590 } 3591 3592 void hsw_ddi_get_config(struct intel_encoder *encoder, 3593 struct intel_crtc_state *crtc_state) 3594 { 3595 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3596 intel_ddi_get_config(encoder, crtc_state); 3597 } 3598 3599 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3600 const struct intel_crtc_state *crtc_state) 3601 { 3602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3603 enum phy phy = intel_port_to_phy(i915, encoder->port); 3604 3605 if (intel_phy_is_tc(i915, phy)) 3606 intel_tc_port_sanitize(enc_to_dig_port(encoder)); 3607 3608 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3609 intel_dp_sync_state(encoder, crtc_state); 3610 } 3611 3612 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3613 struct intel_crtc_state *crtc_state) 3614 { 3615 if (intel_crtc_has_dp_encoder(crtc_state)) 3616 return intel_dp_initial_fastset_check(encoder, crtc_state); 3617 3618 return true; 3619 } 3620 3621 static enum intel_output_type 3622 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3623 struct intel_crtc_state *crtc_state, 3624 struct drm_connector_state *conn_state) 3625 { 3626 switch (conn_state->connector->connector_type) { 3627 case DRM_MODE_CONNECTOR_HDMIA: 3628 return INTEL_OUTPUT_HDMI; 3629 case DRM_MODE_CONNECTOR_eDP: 3630 return INTEL_OUTPUT_EDP; 3631 case DRM_MODE_CONNECTOR_DisplayPort: 3632 return INTEL_OUTPUT_DP; 3633 default: 3634 MISSING_CASE(conn_state->connector->connector_type); 3635 return INTEL_OUTPUT_UNUSED; 3636 } 3637 } 3638 3639 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3640 struct intel_crtc_state *pipe_config, 3641 struct drm_connector_state *conn_state) 3642 { 3643 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3645 enum port port = encoder->port; 3646 int ret; 3647 3648 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3649 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3650 3651 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3652 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3653 } else { 3654 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3655 } 3656 3657 if (ret) 3658 return ret; 3659 3660 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3661 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3662 pipe_config->pch_pfit.force_thru = 3663 pipe_config->pch_pfit.enabled || 3664 pipe_config->crc_enabled; 3665 3666 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3667 pipe_config->lane_lat_optim_mask = 3668 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3669 3670 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3671 3672 return 0; 3673 } 3674 3675 static bool mode_equal(const struct drm_display_mode *mode1, 3676 const struct drm_display_mode *mode2) 3677 { 3678 return drm_mode_match(mode1, mode2, 3679 DRM_MODE_MATCH_TIMINGS | 3680 DRM_MODE_MATCH_FLAGS | 3681 DRM_MODE_MATCH_3D_FLAGS) && 3682 mode1->clock == mode2->clock; /* we want an exact match */ 3683 } 3684 3685 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3686 const struct intel_link_m_n *m_n_2) 3687 { 3688 return m_n_1->tu == m_n_2->tu && 3689 m_n_1->data_m == m_n_2->data_m && 3690 m_n_1->data_n == m_n_2->data_n && 3691 m_n_1->link_m == m_n_2->link_m && 3692 m_n_1->link_n == m_n_2->link_n; 3693 } 3694 3695 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3696 const struct intel_crtc_state *crtc_state2) 3697 { 3698 return crtc_state1->hw.active && crtc_state2->hw.active && 3699 crtc_state1->output_types == crtc_state2->output_types && 3700 crtc_state1->output_format == crtc_state2->output_format && 3701 crtc_state1->lane_count == crtc_state2->lane_count && 3702 crtc_state1->port_clock == crtc_state2->port_clock && 3703 mode_equal(&crtc_state1->hw.adjusted_mode, 3704 &crtc_state2->hw.adjusted_mode) && 3705 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3706 } 3707 3708 static u8 3709 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3710 int tile_group_id) 3711 { 3712 struct drm_connector *connector; 3713 const struct drm_connector_state *conn_state; 3714 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3715 struct intel_atomic_state *state = 3716 to_intel_atomic_state(ref_crtc_state->uapi.state); 3717 u8 transcoders = 0; 3718 int i; 3719 3720 /* 3721 * We don't enable port sync on BDW due to missing w/as and 3722 * due to not having adjusted the modeset sequence appropriately. 3723 */ 3724 if (DISPLAY_VER(dev_priv) < 9) 3725 return 0; 3726 3727 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3728 return 0; 3729 3730 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3731 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3732 const struct intel_crtc_state *crtc_state; 3733 3734 if (!crtc) 3735 continue; 3736 3737 if (!connector->has_tile || 3738 connector->tile_group->id != 3739 tile_group_id) 3740 continue; 3741 crtc_state = intel_atomic_get_new_crtc_state(state, 3742 crtc); 3743 if (!crtcs_port_sync_compatible(ref_crtc_state, 3744 crtc_state)) 3745 continue; 3746 transcoders |= BIT(crtc_state->cpu_transcoder); 3747 } 3748 3749 return transcoders; 3750 } 3751 3752 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3753 struct intel_crtc_state *crtc_state, 3754 struct drm_connector_state *conn_state) 3755 { 3756 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3757 struct drm_connector *connector = conn_state->connector; 3758 u8 port_sync_transcoders = 0; 3759 3760 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3761 encoder->base.base.id, encoder->base.name, 3762 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3763 3764 if (connector->has_tile) 3765 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3766 connector->tile_group->id); 3767 3768 /* 3769 * EDP Transcoders cannot be ensalved 3770 * make them a master always when present 3771 */ 3772 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3773 crtc_state->master_transcoder = TRANSCODER_EDP; 3774 else 3775 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3776 3777 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3778 crtc_state->master_transcoder = INVALID_TRANSCODER; 3779 crtc_state->sync_mode_slaves_mask = 3780 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3781 } 3782 3783 return 0; 3784 } 3785 3786 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3787 { 3788 struct drm_i915_private *i915 = to_i915(encoder->dev); 3789 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3790 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3791 3792 intel_dp_encoder_flush_work(encoder); 3793 if (intel_phy_is_tc(i915, phy)) 3794 intel_tc_port_flush_work(dig_port); 3795 intel_display_power_flush_work(i915); 3796 3797 drm_encoder_cleanup(encoder); 3798 kfree(dig_port->hdcp_port_data.streams); 3799 kfree(dig_port); 3800 } 3801 3802 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3803 { 3804 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3805 3806 intel_dp->reset_link_params = true; 3807 3808 intel_pps_encoder_reset(intel_dp); 3809 } 3810 3811 static const struct drm_encoder_funcs intel_ddi_funcs = { 3812 .reset = intel_ddi_encoder_reset, 3813 .destroy = intel_ddi_encoder_destroy, 3814 }; 3815 3816 static struct intel_connector * 3817 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3818 { 3819 struct intel_connector *connector; 3820 enum port port = dig_port->base.port; 3821 3822 connector = intel_connector_alloc(); 3823 if (!connector) 3824 return NULL; 3825 3826 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3827 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3828 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3829 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3830 3831 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3832 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3833 3834 if (!intel_dp_init_connector(dig_port, connector)) { 3835 kfree(connector); 3836 return NULL; 3837 } 3838 3839 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3840 struct drm_device *dev = dig_port->base.base.dev; 3841 struct drm_privacy_screen *privacy_screen; 3842 3843 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3844 if (!IS_ERR(privacy_screen)) { 3845 drm_connector_attach_privacy_screen_provider(&connector->base, 3846 privacy_screen); 3847 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3848 drm_warn(dev, "Error getting privacy-screen\n"); 3849 } 3850 } 3851 3852 return connector; 3853 } 3854 3855 static int modeset_pipe(struct drm_crtc *crtc, 3856 struct drm_modeset_acquire_ctx *ctx) 3857 { 3858 struct drm_atomic_state *state; 3859 struct drm_crtc_state *crtc_state; 3860 int ret; 3861 3862 state = drm_atomic_state_alloc(crtc->dev); 3863 if (!state) 3864 return -ENOMEM; 3865 3866 state->acquire_ctx = ctx; 3867 3868 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3869 if (IS_ERR(crtc_state)) { 3870 ret = PTR_ERR(crtc_state); 3871 goto out; 3872 } 3873 3874 crtc_state->connectors_changed = true; 3875 3876 ret = drm_atomic_commit(state); 3877 out: 3878 drm_atomic_state_put(state); 3879 3880 return ret; 3881 } 3882 3883 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3884 struct drm_modeset_acquire_ctx *ctx) 3885 { 3886 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3887 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3888 struct intel_connector *connector = hdmi->attached_connector; 3889 struct i2c_adapter *adapter = 3890 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3891 struct drm_connector_state *conn_state; 3892 struct intel_crtc_state *crtc_state; 3893 struct intel_crtc *crtc; 3894 u8 config; 3895 int ret; 3896 3897 if (!connector || connector->base.status != connector_status_connected) 3898 return 0; 3899 3900 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3901 ctx); 3902 if (ret) 3903 return ret; 3904 3905 conn_state = connector->base.state; 3906 3907 crtc = to_intel_crtc(conn_state->crtc); 3908 if (!crtc) 3909 return 0; 3910 3911 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3912 if (ret) 3913 return ret; 3914 3915 crtc_state = to_intel_crtc_state(crtc->base.state); 3916 3917 drm_WARN_ON(&dev_priv->drm, 3918 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3919 3920 if (!crtc_state->hw.active) 3921 return 0; 3922 3923 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3924 !crtc_state->hdmi_scrambling) 3925 return 0; 3926 3927 if (conn_state->commit && 3928 !try_wait_for_completion(&conn_state->commit->hw_done)) 3929 return 0; 3930 3931 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3932 if (ret < 0) { 3933 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3934 ret); 3935 return 0; 3936 } 3937 3938 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3939 crtc_state->hdmi_high_tmds_clock_ratio && 3940 !!(config & SCDC_SCRAMBLING_ENABLE) == 3941 crtc_state->hdmi_scrambling) 3942 return 0; 3943 3944 /* 3945 * HDMI 2.0 says that one should not send scrambled data 3946 * prior to configuring the sink scrambling, and that 3947 * TMDS clock/data transmission should be suspended when 3948 * changing the TMDS clock rate in the sink. So let's 3949 * just do a full modeset here, even though some sinks 3950 * would be perfectly happy if were to just reconfigure 3951 * the SCDC settings on the fly. 3952 */ 3953 return modeset_pipe(&crtc->base, ctx); 3954 } 3955 3956 static enum intel_hotplug_state 3957 intel_ddi_hotplug(struct intel_encoder *encoder, 3958 struct intel_connector *connector) 3959 { 3960 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3961 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3962 struct intel_dp *intel_dp = &dig_port->dp; 3963 enum phy phy = intel_port_to_phy(i915, encoder->port); 3964 bool is_tc = intel_phy_is_tc(i915, phy); 3965 struct drm_modeset_acquire_ctx ctx; 3966 enum intel_hotplug_state state; 3967 int ret; 3968 3969 if (intel_dp->compliance.test_active && 3970 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 3971 intel_dp_phy_test(encoder); 3972 /* just do the PHY test and nothing else */ 3973 return INTEL_HOTPLUG_UNCHANGED; 3974 } 3975 3976 state = intel_encoder_hotplug(encoder, connector); 3977 3978 drm_modeset_acquire_init(&ctx, 0); 3979 3980 for (;;) { 3981 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 3982 ret = intel_hdmi_reset_link(encoder, &ctx); 3983 else 3984 ret = intel_dp_retrain_link(encoder, &ctx); 3985 3986 if (ret == -EDEADLK) { 3987 drm_modeset_backoff(&ctx); 3988 continue; 3989 } 3990 3991 break; 3992 } 3993 3994 drm_modeset_drop_locks(&ctx); 3995 drm_modeset_acquire_fini(&ctx); 3996 drm_WARN(encoder->base.dev, ret, 3997 "Acquiring modeset locks failed with %i\n", ret); 3998 3999 /* 4000 * Unpowered type-c dongles can take some time to boot and be 4001 * responsible, so here giving some time to those dongles to power up 4002 * and then retrying the probe. 4003 * 4004 * On many platforms the HDMI live state signal is known to be 4005 * unreliable, so we can't use it to detect if a sink is connected or 4006 * not. Instead we detect if it's connected based on whether we can 4007 * read the EDID or not. That in turn has a problem during disconnect, 4008 * since the HPD interrupt may be raised before the DDC lines get 4009 * disconnected (due to how the required length of DDC vs. HPD 4010 * connector pins are specified) and so we'll still be able to get a 4011 * valid EDID. To solve this schedule another detection cycle if this 4012 * time around we didn't detect any change in the sink's connection 4013 * status. 4014 * 4015 * Type-c connectors which get their HPD signal deasserted then 4016 * reasserted, without unplugging/replugging the sink from the 4017 * connector, introduce a delay until the AUX channel communication 4018 * becomes functional. Retry the detection for 5 seconds on type-c 4019 * connectors to account for this delay. 4020 */ 4021 if (state == INTEL_HOTPLUG_UNCHANGED && 4022 connector->hotplug_retries < (is_tc ? 5 : 1) && 4023 !dig_port->dp.is_mst) 4024 state = INTEL_HOTPLUG_RETRY; 4025 4026 return state; 4027 } 4028 4029 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4030 { 4031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4032 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4033 4034 return intel_de_read(dev_priv, SDEISR) & bit; 4035 } 4036 4037 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4038 { 4039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4040 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4041 4042 return intel_de_read(dev_priv, DEISR) & bit; 4043 } 4044 4045 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4046 { 4047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4048 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4049 4050 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4051 } 4052 4053 static struct intel_connector * 4054 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4055 { 4056 struct intel_connector *connector; 4057 enum port port = dig_port->base.port; 4058 4059 connector = intel_connector_alloc(); 4060 if (!connector) 4061 return NULL; 4062 4063 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4064 intel_hdmi_init_connector(dig_port, connector); 4065 4066 return connector; 4067 } 4068 4069 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4070 { 4071 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4072 4073 if (dig_port->base.port != PORT_A) 4074 return false; 4075 4076 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4077 return false; 4078 4079 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4080 * supported configuration 4081 */ 4082 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4083 return true; 4084 4085 return false; 4086 } 4087 4088 static int 4089 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4090 { 4091 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4092 enum port port = dig_port->base.port; 4093 int max_lanes = 4; 4094 4095 if (DISPLAY_VER(dev_priv) >= 11) 4096 return max_lanes; 4097 4098 if (port == PORT_A || port == PORT_E) { 4099 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4100 max_lanes = port == PORT_A ? 4 : 0; 4101 else 4102 /* Both A and E share 2 lanes */ 4103 max_lanes = 2; 4104 } 4105 4106 /* 4107 * Some BIOS might fail to set this bit on port A if eDP 4108 * wasn't lit up at boot. Force this bit set when needed 4109 * so we use the proper lane count for our calculations. 4110 */ 4111 if (intel_ddi_a_force_4_lanes(dig_port)) { 4112 drm_dbg_kms(&dev_priv->drm, 4113 "Forcing DDI_A_4_LANES for port A\n"); 4114 dig_port->saved_port_bits |= DDI_A_4_LANES; 4115 max_lanes = 4; 4116 } 4117 4118 return max_lanes; 4119 } 4120 4121 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4122 { 4123 return i915->hti_state & HDPORT_ENABLED && 4124 i915->hti_state & HDPORT_DDI_USED(phy); 4125 } 4126 4127 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4128 enum port port) 4129 { 4130 if (port >= PORT_D_XELPD) 4131 return HPD_PORT_D + port - PORT_D_XELPD; 4132 else if (port >= PORT_TC1) 4133 return HPD_PORT_TC1 + port - PORT_TC1; 4134 else 4135 return HPD_PORT_A + port - PORT_A; 4136 } 4137 4138 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4139 enum port port) 4140 { 4141 if (port >= PORT_TC1) 4142 return HPD_PORT_C + port - PORT_TC1; 4143 else 4144 return HPD_PORT_A + port - PORT_A; 4145 } 4146 4147 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4148 enum port port) 4149 { 4150 if (port >= PORT_TC1) 4151 return HPD_PORT_TC1 + port - PORT_TC1; 4152 else 4153 return HPD_PORT_A + port - PORT_A; 4154 } 4155 4156 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4157 enum port port) 4158 { 4159 if (HAS_PCH_TGP(dev_priv)) 4160 return tgl_hpd_pin(dev_priv, port); 4161 4162 if (port >= PORT_TC1) 4163 return HPD_PORT_C + port - PORT_TC1; 4164 else 4165 return HPD_PORT_A + port - PORT_A; 4166 } 4167 4168 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4169 enum port port) 4170 { 4171 if (port >= PORT_C) 4172 return HPD_PORT_TC1 + port - PORT_C; 4173 else 4174 return HPD_PORT_A + port - PORT_A; 4175 } 4176 4177 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4178 enum port port) 4179 { 4180 if (port == PORT_D) 4181 return HPD_PORT_A; 4182 4183 if (HAS_PCH_MCC(dev_priv)) 4184 return icl_hpd_pin(dev_priv, port); 4185 4186 return HPD_PORT_A + port - PORT_A; 4187 } 4188 4189 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4190 { 4191 if (HAS_PCH_TGP(dev_priv)) 4192 return icl_hpd_pin(dev_priv, port); 4193 4194 return HPD_PORT_A + port - PORT_A; 4195 } 4196 4197 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4198 { 4199 if (DISPLAY_VER(i915) >= 12) 4200 return port >= PORT_TC1; 4201 else if (DISPLAY_VER(i915) >= 11) 4202 return port >= PORT_C; 4203 else 4204 return false; 4205 } 4206 4207 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4208 { 4209 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4210 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4211 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4212 enum phy phy = intel_port_to_phy(i915, encoder->port); 4213 4214 intel_dp_encoder_suspend(encoder); 4215 4216 if (!intel_phy_is_tc(i915, phy)) 4217 return; 4218 4219 intel_tc_port_flush_work(dig_port); 4220 } 4221 4222 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4223 { 4224 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4225 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4226 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4227 enum phy phy = intel_port_to_phy(i915, encoder->port); 4228 4229 intel_dp_encoder_shutdown(encoder); 4230 intel_hdmi_encoder_shutdown(encoder); 4231 4232 if (!intel_phy_is_tc(i915, phy)) 4233 return; 4234 4235 intel_tc_port_flush_work(dig_port); 4236 } 4237 4238 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4239 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4240 4241 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4242 { 4243 struct intel_digital_port *dig_port; 4244 struct intel_encoder *encoder; 4245 const struct intel_bios_encoder_data *devdata; 4246 bool init_hdmi, init_dp; 4247 enum phy phy = intel_port_to_phy(dev_priv, port); 4248 4249 /* 4250 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4251 * have taken over some of the PHYs and made them unavailable to the 4252 * driver. In that case we should skip initializing the corresponding 4253 * outputs. 4254 */ 4255 if (hti_uses_phy(dev_priv, phy)) { 4256 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4257 port_name(port), phy_name(phy)); 4258 return; 4259 } 4260 4261 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4262 if (!devdata) { 4263 drm_dbg_kms(&dev_priv->drm, 4264 "VBT says port %c is not present\n", 4265 port_name(port)); 4266 return; 4267 } 4268 4269 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4270 intel_bios_encoder_supports_hdmi(devdata); 4271 init_dp = intel_bios_encoder_supports_dp(devdata); 4272 4273 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4274 /* 4275 * Lspcon device needs to be driven with DP connector 4276 * with special detection sequence. So make sure DP 4277 * is initialized before lspcon. 4278 */ 4279 init_dp = true; 4280 init_hdmi = false; 4281 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4282 port_name(port)); 4283 } 4284 4285 if (!init_dp && !init_hdmi) { 4286 drm_dbg_kms(&dev_priv->drm, 4287 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4288 port_name(port)); 4289 return; 4290 } 4291 4292 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4293 if (!dig_port) 4294 return; 4295 4296 encoder = &dig_port->base; 4297 encoder->devdata = devdata; 4298 4299 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4300 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4301 DRM_MODE_ENCODER_TMDS, 4302 "DDI %c/PHY %c", 4303 port_name(port - PORT_D_XELPD + PORT_D), 4304 phy_name(phy)); 4305 } else if (DISPLAY_VER(dev_priv) >= 12) { 4306 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4307 4308 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4309 DRM_MODE_ENCODER_TMDS, 4310 "DDI %s%c/PHY %s%c", 4311 port >= PORT_TC1 ? "TC" : "", 4312 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4313 tc_port != TC_PORT_NONE ? "TC" : "", 4314 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4315 } else if (DISPLAY_VER(dev_priv) >= 11) { 4316 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4317 4318 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4319 DRM_MODE_ENCODER_TMDS, 4320 "DDI %c%s/PHY %s%c", 4321 port_name(port), 4322 port >= PORT_C ? " (TC)" : "", 4323 tc_port != TC_PORT_NONE ? "TC" : "", 4324 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4325 } else { 4326 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4327 DRM_MODE_ENCODER_TMDS, 4328 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4329 } 4330 4331 mutex_init(&dig_port->hdcp_mutex); 4332 dig_port->num_hdcp_streams = 0; 4333 4334 encoder->hotplug = intel_ddi_hotplug; 4335 encoder->compute_output_type = intel_ddi_compute_output_type; 4336 encoder->compute_config = intel_ddi_compute_config; 4337 encoder->compute_config_late = intel_ddi_compute_config_late; 4338 encoder->enable = intel_enable_ddi; 4339 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4340 encoder->pre_enable = intel_ddi_pre_enable; 4341 encoder->disable = intel_disable_ddi; 4342 encoder->post_disable = intel_ddi_post_disable; 4343 encoder->update_pipe = intel_ddi_update_pipe; 4344 encoder->get_hw_state = intel_ddi_get_hw_state; 4345 encoder->sync_state = intel_ddi_sync_state; 4346 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4347 encoder->suspend = intel_ddi_encoder_suspend; 4348 encoder->shutdown = intel_ddi_encoder_shutdown; 4349 encoder->get_power_domains = intel_ddi_get_power_domains; 4350 4351 encoder->type = INTEL_OUTPUT_DDI; 4352 encoder->power_domain = intel_port_to_power_domain(port); 4353 encoder->port = port; 4354 encoder->cloneable = 0; 4355 encoder->pipe_mask = ~0; 4356 4357 if (IS_DG2(dev_priv)) { 4358 encoder->enable_clock = intel_mpllb_enable; 4359 encoder->disable_clock = intel_mpllb_disable; 4360 encoder->get_config = dg2_ddi_get_config; 4361 } else if (IS_ALDERLAKE_S(dev_priv)) { 4362 encoder->enable_clock = adls_ddi_enable_clock; 4363 encoder->disable_clock = adls_ddi_disable_clock; 4364 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4365 encoder->get_config = adls_ddi_get_config; 4366 } else if (IS_ROCKETLAKE(dev_priv)) { 4367 encoder->enable_clock = rkl_ddi_enable_clock; 4368 encoder->disable_clock = rkl_ddi_disable_clock; 4369 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4370 encoder->get_config = rkl_ddi_get_config; 4371 } else if (IS_DG1(dev_priv)) { 4372 encoder->enable_clock = dg1_ddi_enable_clock; 4373 encoder->disable_clock = dg1_ddi_disable_clock; 4374 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4375 encoder->get_config = dg1_ddi_get_config; 4376 } else if (IS_JSL_EHL(dev_priv)) { 4377 if (intel_ddi_is_tc(dev_priv, port)) { 4378 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4379 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4380 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4381 encoder->get_config = icl_ddi_combo_get_config; 4382 } else { 4383 encoder->enable_clock = icl_ddi_combo_enable_clock; 4384 encoder->disable_clock = icl_ddi_combo_disable_clock; 4385 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4386 encoder->get_config = icl_ddi_combo_get_config; 4387 } 4388 } else if (DISPLAY_VER(dev_priv) >= 11) { 4389 if (intel_ddi_is_tc(dev_priv, port)) { 4390 encoder->enable_clock = icl_ddi_tc_enable_clock; 4391 encoder->disable_clock = icl_ddi_tc_disable_clock; 4392 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4393 encoder->get_config = icl_ddi_tc_get_config; 4394 } else { 4395 encoder->enable_clock = icl_ddi_combo_enable_clock; 4396 encoder->disable_clock = icl_ddi_combo_disable_clock; 4397 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4398 encoder->get_config = icl_ddi_combo_get_config; 4399 } 4400 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4401 /* BXT/GLK have fixed PLL->port mapping */ 4402 encoder->get_config = bxt_ddi_get_config; 4403 } else if (DISPLAY_VER(dev_priv) == 9) { 4404 encoder->enable_clock = skl_ddi_enable_clock; 4405 encoder->disable_clock = skl_ddi_disable_clock; 4406 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4407 encoder->get_config = skl_ddi_get_config; 4408 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4409 encoder->enable_clock = hsw_ddi_enable_clock; 4410 encoder->disable_clock = hsw_ddi_disable_clock; 4411 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4412 encoder->get_config = hsw_ddi_get_config; 4413 } 4414 4415 if (IS_DG2(dev_priv)) { 4416 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4417 } else if (DISPLAY_VER(dev_priv) >= 12) { 4418 if (intel_phy_is_combo(dev_priv, phy)) 4419 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4420 else 4421 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4422 } else if (DISPLAY_VER(dev_priv) >= 11) { 4423 if (intel_phy_is_combo(dev_priv, phy)) 4424 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4425 else 4426 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4427 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4428 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4429 } else { 4430 encoder->set_signal_levels = hsw_set_signal_levels; 4431 } 4432 4433 intel_ddi_buf_trans_init(encoder); 4434 4435 if (DISPLAY_VER(dev_priv) >= 13) 4436 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4437 else if (IS_DG1(dev_priv)) 4438 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4439 else if (IS_ROCKETLAKE(dev_priv)) 4440 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4441 else if (DISPLAY_VER(dev_priv) >= 12) 4442 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4443 else if (IS_JSL_EHL(dev_priv)) 4444 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4445 else if (DISPLAY_VER(dev_priv) == 11) 4446 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4447 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4448 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4449 else 4450 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4451 4452 if (DISPLAY_VER(dev_priv) >= 11) 4453 dig_port->saved_port_bits = 4454 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4455 & DDI_BUF_PORT_REVERSAL; 4456 else 4457 dig_port->saved_port_bits = 4458 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4459 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4460 4461 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4462 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4463 4464 dig_port->dp.output_reg = INVALID_MMIO_REG; 4465 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4466 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4467 4468 if (intel_phy_is_tc(dev_priv, phy)) { 4469 bool is_legacy = 4470 !intel_bios_encoder_supports_typec_usb(devdata) && 4471 !intel_bios_encoder_supports_tbt(devdata); 4472 4473 intel_tc_port_init(dig_port, is_legacy); 4474 4475 encoder->update_prepare = intel_ddi_update_prepare; 4476 encoder->update_complete = intel_ddi_update_complete; 4477 } 4478 4479 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4480 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4481 port - PORT_A; 4482 4483 if (init_dp) { 4484 if (!intel_ddi_init_dp_connector(dig_port)) 4485 goto err; 4486 4487 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4488 4489 if (dig_port->dp.mso_link_count) 4490 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4491 } 4492 4493 /* In theory we don't need the encoder->type check, but leave it just in 4494 * case we have some really bad VBTs... */ 4495 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4496 if (!intel_ddi_init_hdmi_connector(dig_port)) 4497 goto err; 4498 } 4499 4500 if (DISPLAY_VER(dev_priv) >= 11) { 4501 if (intel_phy_is_tc(dev_priv, phy)) 4502 dig_port->connected = intel_tc_port_connected; 4503 else 4504 dig_port->connected = lpt_digital_port_connected; 4505 } else if (DISPLAY_VER(dev_priv) >= 8) { 4506 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4507 IS_BROXTON(dev_priv)) 4508 dig_port->connected = bdw_digital_port_connected; 4509 else 4510 dig_port->connected = lpt_digital_port_connected; 4511 } else { 4512 if (port == PORT_A) 4513 dig_port->connected = hsw_digital_port_connected; 4514 else 4515 dig_port->connected = lpt_digital_port_connected; 4516 } 4517 4518 intel_infoframe_init(dig_port); 4519 4520 return; 4521 4522 err: 4523 drm_encoder_cleanup(&encoder->base); 4524 kfree(dig_port); 4525 } 4526