1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_privacy_screen_consumer.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "icl_dsi.h" 38 #include "intel_audio.h" 39 #include "intel_audio_regs.h" 40 #include "intel_backlight.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_cx0_phy.h" 46 #include "intel_cx0_phy_regs.h" 47 #include "intel_ddi.h" 48 #include "intel_ddi_buf_trans.h" 49 #include "intel_de.h" 50 #include "intel_display_power.h" 51 #include "intel_display_types.h" 52 #include "intel_dkl_phy.h" 53 #include "intel_dkl_phy_regs.h" 54 #include "intel_dp.h" 55 #include "intel_dp_aux.h" 56 #include "intel_dp_link_training.h" 57 #include "intel_dp_mst.h" 58 #include "intel_dp_test.h" 59 #include "intel_dp_tunnel.h" 60 #include "intel_dpio_phy.h" 61 #include "intel_dsi.h" 62 #include "intel_encoder.h" 63 #include "intel_fdi.h" 64 #include "intel_fifo_underrun.h" 65 #include "intel_gmbus.h" 66 #include "intel_hdcp.h" 67 #include "intel_hdmi.h" 68 #include "intel_hotplug.h" 69 #include "intel_hti.h" 70 #include "intel_lspcon.h" 71 #include "intel_mg_phy_regs.h" 72 #include "intel_modeset_lock.h" 73 #include "intel_pps.h" 74 #include "intel_psr.h" 75 #include "intel_quirks.h" 76 #include "intel_snps_phy.h" 77 #include "intel_tc.h" 78 #include "intel_vdsc.h" 79 #include "intel_vdsc_regs.h" 80 #include "skl_scaler.h" 81 #include "skl_universal_plane.h" 82 83 static const u8 index_to_dp_signal_levels[] = { 84 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 88 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 91 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 }; 95 96 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 97 const struct intel_ddi_buf_trans *trans) 98 { 99 int level; 100 101 level = intel_bios_hdmi_level_shift(encoder->devdata); 102 if (level < 0) 103 level = trans->hdmi_default_entry; 104 105 return level; 106 } 107 108 static bool has_buf_trans_select(struct drm_i915_private *i915) 109 { 110 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 111 } 112 113 static bool has_iboost(struct drm_i915_private *i915) 114 { 115 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 116 } 117 118 /* 119 * Starting with Haswell, DDI port buffers must be programmed with correct 120 * values in advance. This function programs the correct values for 121 * DP/eDP/FDI use cases. 122 */ 123 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 124 const struct intel_crtc_state *crtc_state) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 u32 iboost_bit = 0; 128 int i, n_entries; 129 enum port port = encoder->port; 130 const struct intel_ddi_buf_trans *trans; 131 132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 134 return; 135 136 /* If we're boosting the current, set bit 31 of trans1 */ 137 if (has_iboost(dev_priv) && 138 intel_bios_dp_boost_level(encoder->devdata)) 139 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 140 141 for (i = 0; i < n_entries; i++) { 142 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 143 trans->entries[i].hsw.trans1 | iboost_bit); 144 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 145 trans->entries[i].hsw.trans2); 146 } 147 } 148 149 /* 150 * Starting with Haswell, DDI port buffers must be programmed with correct 151 * values in advance. This function programs the correct values for 152 * HDMI/DVI use cases. 153 */ 154 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 155 const struct intel_crtc_state *crtc_state) 156 { 157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 158 int level = intel_ddi_level(encoder, crtc_state, 0); 159 u32 iboost_bit = 0; 160 int n_entries; 161 enum port port = encoder->port; 162 const struct intel_ddi_buf_trans *trans; 163 164 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 165 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 166 return; 167 168 /* If we're boosting the current, set bit 31 of trans1 */ 169 if (has_iboost(dev_priv) && 170 intel_bios_hdmi_boost_level(encoder->devdata)) 171 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 172 173 /* Entry 9 is for HDMI: */ 174 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 175 trans->entries[level].hsw.trans1 | iboost_bit); 176 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 177 trans->entries[level].hsw.trans2); 178 } 179 180 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 181 { 182 int ret; 183 184 /* FIXME: find out why Bspec's 100us timeout is too short */ 185 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 186 XELPDP_PORT_BUF_PHY_IDLE), 10000); 187 if (ret) 188 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 189 port_name(port)); 190 } 191 192 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 193 enum port port) 194 { 195 if (IS_BROXTON(dev_priv)) { 196 udelay(16); 197 return; 198 } 199 200 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 201 DDI_BUF_IS_IDLE), 8)) 202 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 203 port_name(port)); 204 } 205 206 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 207 { 208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 209 enum port port = encoder->port; 210 int timeout_us; 211 int ret; 212 213 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 214 if (DISPLAY_VER(dev_priv) < 10) { 215 usleep_range(518, 1000); 216 return; 217 } 218 219 if (DISPLAY_VER(dev_priv) >= 14) { 220 timeout_us = 10000; 221 } else if (IS_DG2(dev_priv)) { 222 timeout_us = 1200; 223 } else if (DISPLAY_VER(dev_priv) >= 12) { 224 if (intel_encoder_is_tc(encoder)) 225 timeout_us = 3000; 226 else 227 timeout_us = 1000; 228 } else { 229 timeout_us = 500; 230 } 231 232 if (DISPLAY_VER(dev_priv) >= 14) 233 ret = _wait_for(!(intel_de_read(dev_priv, 234 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 235 XELPDP_PORT_BUF_PHY_IDLE), 236 timeout_us, 10, 10); 237 else 238 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 239 timeout_us, 10, 10); 240 241 if (ret) 242 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state) 333 { 334 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 336 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 337 338 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 339 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 340 DDI_BUF_TRANS_SELECT(0); 341 342 if (dig_port->lane_reversal) 343 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 344 if (dig_port->ddi_a_4_lanes) 345 intel_dp->DP |= DDI_A_4_LANES; 346 347 if (DISPLAY_VER(i915) >= 14) { 348 if (intel_dp_is_uhbr(crtc_state)) 349 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 350 else 351 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 352 } 353 354 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 355 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 356 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 357 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 358 } 359 } 360 361 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 362 enum port port) 363 { 364 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 365 366 switch (val) { 367 case DDI_CLK_SEL_NONE: 368 return 0; 369 case DDI_CLK_SEL_TBT_162: 370 return 162000; 371 case DDI_CLK_SEL_TBT_270: 372 return 270000; 373 case DDI_CLK_SEL_TBT_540: 374 return 540000; 375 case DDI_CLK_SEL_TBT_810: 376 return 810000; 377 default: 378 MISSING_CASE(val); 379 return 0; 380 } 381 } 382 383 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 384 { 385 /* CRT dotclock is determined via other means */ 386 if (pipe_config->has_pch_encoder) 387 return; 388 389 pipe_config->hw.adjusted_mode.crtc_clock = 390 intel_crtc_dotclock(pipe_config); 391 } 392 393 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 394 const struct drm_connector_state *conn_state) 395 { 396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 398 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 399 u32 temp; 400 401 if (!intel_crtc_has_dp_encoder(crtc_state)) 402 return; 403 404 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 405 406 temp = DP_MSA_MISC_SYNC_CLOCK; 407 408 switch (crtc_state->pipe_bpp) { 409 case 18: 410 temp |= DP_MSA_MISC_6_BPC; 411 break; 412 case 24: 413 temp |= DP_MSA_MISC_8_BPC; 414 break; 415 case 30: 416 temp |= DP_MSA_MISC_10_BPC; 417 break; 418 case 36: 419 temp |= DP_MSA_MISC_12_BPC; 420 break; 421 default: 422 MISSING_CASE(crtc_state->pipe_bpp); 423 break; 424 } 425 426 /* nonsense combination */ 427 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 428 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 429 430 if (crtc_state->limited_color_range) 431 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 432 433 /* 434 * As per DP 1.2 spec section 2.3.4.3 while sending 435 * YCBCR 444 signals we should program MSA MISC1/0 fields with 436 * colorspace information. 437 */ 438 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 439 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 440 441 /* 442 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 443 * of Color Encoding Format and Content Color Gamut] while sending 444 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 445 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 446 */ 447 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 448 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 449 450 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 451 temp); 452 } 453 454 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 455 { 456 if (master_transcoder == TRANSCODER_EDP) 457 return 0; 458 else 459 return master_transcoder + 1; 460 } 461 462 static void 463 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 464 bool enable) 465 { 466 struct intel_display *display = to_intel_display(crtc_state); 467 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 468 u32 val = 0; 469 470 if (!HAS_DP20(display)) 471 return; 472 473 if (enable && intel_dp_is_uhbr(crtc_state)) 474 val = TRANS_DP2_128B132B_CHANNEL_CODING; 475 476 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 477 } 478 479 /* 480 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 481 * 482 * Only intended to be used by intel_ddi_enable_transcoder_func() and 483 * intel_ddi_config_transcoder_func(). 484 */ 485 static u32 486 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 487 const struct intel_crtc_state *crtc_state) 488 { 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 enum pipe pipe = crtc->pipe; 492 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 493 enum port port = encoder->port; 494 u32 temp; 495 496 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 497 temp = TRANS_DDI_FUNC_ENABLE; 498 if (DISPLAY_VER(dev_priv) >= 12) 499 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 500 else 501 temp |= TRANS_DDI_SELECT_PORT(port); 502 503 switch (crtc_state->pipe_bpp) { 504 default: 505 MISSING_CASE(crtc_state->pipe_bpp); 506 fallthrough; 507 case 18: 508 temp |= TRANS_DDI_BPC_6; 509 break; 510 case 24: 511 temp |= TRANS_DDI_BPC_8; 512 break; 513 case 30: 514 temp |= TRANS_DDI_BPC_10; 515 break; 516 case 36: 517 temp |= TRANS_DDI_BPC_12; 518 break; 519 } 520 521 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 522 temp |= TRANS_DDI_PVSYNC; 523 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 524 temp |= TRANS_DDI_PHSYNC; 525 526 if (cpu_transcoder == TRANSCODER_EDP) { 527 switch (pipe) { 528 default: 529 MISSING_CASE(pipe); 530 fallthrough; 531 case PIPE_A: 532 /* On Haswell, can only use the always-on power well for 533 * eDP when not using the panel fitter, and when not 534 * using motion blur mitigation (which we don't 535 * support). */ 536 if (crtc_state->pch_pfit.force_thru) 537 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 538 else 539 temp |= TRANS_DDI_EDP_INPUT_A_ON; 540 break; 541 case PIPE_B: 542 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 543 break; 544 case PIPE_C: 545 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 546 break; 547 } 548 } 549 550 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 551 if (crtc_state->has_hdmi_sink) 552 temp |= TRANS_DDI_MODE_SELECT_HDMI; 553 else 554 temp |= TRANS_DDI_MODE_SELECT_DVI; 555 556 if (crtc_state->hdmi_scrambling) 557 temp |= TRANS_DDI_HDMI_SCRAMBLING; 558 if (crtc_state->hdmi_high_tmds_clock_ratio) 559 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 560 if (DISPLAY_VER(dev_priv) >= 14) 561 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 562 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 563 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 564 temp |= (crtc_state->fdi_lanes - 1) << 1; 565 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 566 intel_dp_is_uhbr(crtc_state)) { 567 if (intel_dp_is_uhbr(crtc_state)) 568 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 569 else 570 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 573 if (DISPLAY_VER(dev_priv) >= 12) { 574 enum transcoder master; 575 576 master = crtc_state->mst_master_transcoder; 577 drm_WARN_ON(&dev_priv->drm, 578 master == INVALID_TRANSCODER); 579 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 580 } 581 } else { 582 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 583 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 584 } 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 587 crtc_state->master_transcoder != INVALID_TRANSCODER) { 588 u8 master_select = 589 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 590 591 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 592 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 593 } 594 595 return temp; 596 } 597 598 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 599 const struct intel_crtc_state *crtc_state) 600 { 601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 603 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 604 605 if (DISPLAY_VER(dev_priv) >= 11) { 606 enum transcoder master_transcoder = crtc_state->master_transcoder; 607 u32 ctl2 = 0; 608 609 if (master_transcoder != INVALID_TRANSCODER) { 610 u8 master_select = 611 bdw_trans_port_sync_master_select(master_transcoder); 612 613 ctl2 |= PORT_SYNC_MODE_ENABLE | 614 PORT_SYNC_MODE_MASTER_SELECT(master_select); 615 } 616 617 intel_de_write(dev_priv, 618 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 619 ctl2); 620 } 621 622 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 623 intel_ddi_transcoder_func_reg_val_get(encoder, 624 crtc_state)); 625 } 626 627 /* 628 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 629 * bit for the DDI function and enables the DP2 configuration. Called for all 630 * transcoder types. 631 */ 632 void 633 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 634 const struct intel_crtc_state *crtc_state) 635 { 636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 638 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 639 u32 ctl; 640 641 intel_ddi_config_transcoder_dp2(crtc_state, true); 642 643 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 644 ctl &= ~TRANS_DDI_FUNC_ENABLE; 645 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 646 ctl); 647 } 648 649 /* 650 * Disable the DDI function and port syncing. 651 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 652 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 653 * transcoders these are done later in intel_ddi_post_disable_dp(). 654 */ 655 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 656 { 657 struct intel_display *display = to_intel_display(crtc_state); 658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 660 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 661 u32 ctl; 662 663 if (DISPLAY_VER(dev_priv) >= 11) 664 intel_de_write(dev_priv, 665 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 666 0); 667 668 ctl = intel_de_read(dev_priv, 669 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 670 671 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 672 673 ctl &= ~TRANS_DDI_FUNC_ENABLE; 674 675 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 676 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 677 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 678 679 if (DISPLAY_VER(dev_priv) >= 12) { 680 if (!intel_dp_mst_is_master_trans(crtc_state)) { 681 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 682 TRANS_DDI_MODE_SELECT_MASK); 683 } 684 } else { 685 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 686 } 687 688 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 689 ctl); 690 691 if (intel_dp_mst_is_slave_trans(crtc_state)) 692 intel_ddi_config_transcoder_dp2(crtc_state, false); 693 694 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 695 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 696 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 697 /* Quirk time at 100ms for reliable operation */ 698 msleep(100); 699 } 700 } 701 702 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 703 enum transcoder cpu_transcoder, 704 bool enable, u32 hdcp_mask) 705 { 706 struct drm_device *dev = intel_encoder->base.dev; 707 struct drm_i915_private *dev_priv = to_i915(dev); 708 intel_wakeref_t wakeref; 709 int ret = 0; 710 711 wakeref = intel_display_power_get_if_enabled(dev_priv, 712 intel_encoder->power_domain); 713 if (drm_WARN_ON(dev, !wakeref)) 714 return -ENXIO; 715 716 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 717 hdcp_mask, enable ? hdcp_mask : 0); 718 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 719 return ret; 720 } 721 722 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 723 { 724 struct intel_display *display = to_intel_display(intel_connector); 725 struct drm_i915_private *dev_priv = to_i915(display->drm); 726 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 727 int type = intel_connector->base.connector_type; 728 enum port port = encoder->port; 729 enum transcoder cpu_transcoder; 730 intel_wakeref_t wakeref; 731 enum pipe pipe = 0; 732 u32 ddi_mode; 733 bool ret; 734 735 wakeref = intel_display_power_get_if_enabled(dev_priv, 736 encoder->power_domain); 737 if (!wakeref) 738 return false; 739 740 /* Note: This returns false for DP MST primary encoders. */ 741 if (!encoder->get_hw_state(encoder, &pipe)) { 742 ret = false; 743 goto out; 744 } 745 746 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 747 cpu_transcoder = TRANSCODER_EDP; 748 else 749 cpu_transcoder = (enum transcoder) pipe; 750 751 ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 752 TRANS_DDI_MODE_SELECT_MASK; 753 754 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 755 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 756 ret = type == DRM_MODE_CONNECTOR_HDMIA; 757 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 758 ret = type == DRM_MODE_CONNECTOR_VGA; 759 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 760 ret = type == DRM_MODE_CONNECTOR_eDP || 761 type == DRM_MODE_CONNECTOR_DisplayPort; 762 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 763 /* 764 * encoder->get_hw_state() should have bailed out on MST. This 765 * must be SST and non-eDP. 766 */ 767 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 768 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 769 /* encoder->get_hw_state() should have bailed out on MST. */ 770 ret = false; 771 } else { 772 ret = false; 773 } 774 775 out: 776 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 777 778 return ret; 779 } 780 781 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 782 u8 *pipe_mask, bool *is_dp_mst) 783 { 784 struct intel_display *display = to_intel_display(encoder); 785 struct drm_i915_private *dev_priv = to_i915(display->drm); 786 enum port port = encoder->port; 787 intel_wakeref_t wakeref; 788 enum pipe p; 789 u32 tmp; 790 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 791 792 *pipe_mask = 0; 793 *is_dp_mst = false; 794 795 wakeref = intel_display_power_get_if_enabled(dev_priv, 796 encoder->power_domain); 797 if (!wakeref) 798 return; 799 800 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 801 if (!(tmp & DDI_BUF_CTL_ENABLE)) 802 goto out; 803 804 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 805 tmp = intel_de_read(dev_priv, 806 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 807 808 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 809 default: 810 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 811 fallthrough; 812 case TRANS_DDI_EDP_INPUT_A_ON: 813 case TRANS_DDI_EDP_INPUT_A_ONOFF: 814 *pipe_mask = BIT(PIPE_A); 815 break; 816 case TRANS_DDI_EDP_INPUT_B_ONOFF: 817 *pipe_mask = BIT(PIPE_B); 818 break; 819 case TRANS_DDI_EDP_INPUT_C_ONOFF: 820 *pipe_mask = BIT(PIPE_C); 821 break; 822 } 823 824 goto out; 825 } 826 827 for_each_pipe(dev_priv, p) { 828 enum transcoder cpu_transcoder = (enum transcoder)p; 829 u32 port_mask, ddi_select, ddi_mode; 830 intel_wakeref_t trans_wakeref; 831 832 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 833 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 834 if (!trans_wakeref) 835 continue; 836 837 if (DISPLAY_VER(dev_priv) >= 12) { 838 port_mask = TGL_TRANS_DDI_PORT_MASK; 839 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 840 } else { 841 port_mask = TRANS_DDI_PORT_MASK; 842 ddi_select = TRANS_DDI_SELECT_PORT(port); 843 } 844 845 tmp = intel_de_read(dev_priv, 846 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 847 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 848 trans_wakeref); 849 850 if ((tmp & port_mask) != ddi_select) 851 continue; 852 853 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 854 855 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 856 mst_pipe_mask |= BIT(p); 857 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 858 dp128b132b_pipe_mask |= BIT(p); 859 860 *pipe_mask |= BIT(p); 861 } 862 863 if (!*pipe_mask) 864 drm_dbg_kms(&dev_priv->drm, 865 "No pipe for [ENCODER:%d:%s] found\n", 866 encoder->base.base.id, encoder->base.name); 867 868 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 869 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 870 871 /* 872 * If we don't have 8b/10b MST, but have more than one 873 * transcoder in 128b/132b mode, we know it must be 128b/132b 874 * MST. 875 * 876 * Otherwise, we fall back to checking the current MST 877 * state. It's not accurate for hardware takeover at probe, but 878 * we don't expect MST to have been enabled at that point, and 879 * can assume it's SST. 880 */ 881 if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst) 882 mst_pipe_mask = dp128b132b_pipe_mask; 883 } 884 885 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 886 drm_dbg_kms(&dev_priv->drm, 887 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 888 encoder->base.base.id, encoder->base.name, 889 *pipe_mask); 890 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 891 } 892 893 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 894 drm_dbg_kms(&dev_priv->drm, 895 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 896 encoder->base.base.id, encoder->base.name, 897 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 898 else 899 *is_dp_mst = mst_pipe_mask; 900 901 out: 902 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 903 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 904 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 905 BXT_PHY_LANE_POWERDOWN_ACK | 906 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 907 drm_err(&dev_priv->drm, 908 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 909 encoder->base.base.id, encoder->base.name, tmp); 910 } 911 912 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 913 } 914 915 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 916 enum pipe *pipe) 917 { 918 u8 pipe_mask; 919 bool is_mst; 920 921 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 922 923 if (is_mst || !pipe_mask) 924 return false; 925 926 *pipe = ffs(pipe_mask) - 1; 927 928 return true; 929 } 930 931 static enum intel_display_power_domain 932 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 933 const struct intel_crtc_state *crtc_state) 934 { 935 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 936 937 /* 938 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 939 * DC states enabled at the same time, while for driver initiated AUX 940 * transfers we need the same AUX IOs to be powered but with DC states 941 * disabled. Accordingly use the AUX_IO_<port> power domain here which 942 * leaves DC states enabled. 943 * 944 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 945 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 946 * well, so we can acquire a wider AUX_<port> power domain reference 947 * instead of a specific AUX_IO_<port> reference without powering up any 948 * extra wells. 949 */ 950 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 951 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 952 else if (DISPLAY_VER(i915) < 14 && 953 (intel_crtc_has_dp_encoder(crtc_state) || 954 intel_encoder_is_tc(&dig_port->base))) 955 return intel_aux_power_domain(dig_port); 956 else 957 return POWER_DOMAIN_INVALID; 958 } 959 960 static void 961 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 962 const struct intel_crtc_state *crtc_state) 963 { 964 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 965 enum intel_display_power_domain domain = 966 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 967 968 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 969 970 if (domain == POWER_DOMAIN_INVALID) 971 return; 972 973 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 974 } 975 976 static void 977 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 978 const struct intel_crtc_state *crtc_state) 979 { 980 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 981 enum intel_display_power_domain domain = 982 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 983 intel_wakeref_t wf; 984 985 wf = fetch_and_zero(&dig_port->aux_wakeref); 986 if (!wf) 987 return; 988 989 intel_display_power_put(i915, domain, wf); 990 } 991 992 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 993 struct intel_crtc_state *crtc_state) 994 { 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 struct intel_digital_port *dig_port; 997 998 /* 999 * TODO: Add support for MST encoders. Atm, the following should never 1000 * happen since fake-MST encoders don't set their get_power_domains() 1001 * hook. 1002 */ 1003 if (drm_WARN_ON(&dev_priv->drm, 1004 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1005 return; 1006 1007 dig_port = enc_to_dig_port(encoder); 1008 1009 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1010 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 1011 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 1012 dig_port->ddi_io_power_domain); 1013 } 1014 1015 main_link_aux_power_domain_get(dig_port, crtc_state); 1016 } 1017 1018 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1019 const struct intel_crtc_state *crtc_state) 1020 { 1021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1024 enum phy phy = intel_encoder_to_phy(encoder); 1025 u32 val; 1026 1027 if (cpu_transcoder == TRANSCODER_EDP) 1028 return; 1029 1030 if (DISPLAY_VER(dev_priv) >= 13) 1031 val = TGL_TRANS_CLK_SEL_PORT(phy); 1032 else if (DISPLAY_VER(dev_priv) >= 12) 1033 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1034 else 1035 val = TRANS_CLK_SEL_PORT(encoder->port); 1036 1037 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1038 } 1039 1040 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1041 { 1042 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1043 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1044 u32 val; 1045 1046 if (cpu_transcoder == TRANSCODER_EDP) 1047 return; 1048 1049 if (DISPLAY_VER(dev_priv) >= 12) 1050 val = TGL_TRANS_CLK_SEL_DISABLED; 1051 else 1052 val = TRANS_CLK_SEL_DISABLED; 1053 1054 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1055 } 1056 1057 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1058 enum port port, u8 iboost) 1059 { 1060 u32 tmp; 1061 1062 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1063 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1064 if (iboost) 1065 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1066 else 1067 tmp |= BALANCE_LEG_DISABLE(port); 1068 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1069 } 1070 1071 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1072 const struct intel_crtc_state *crtc_state, 1073 int level) 1074 { 1075 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1077 u8 iboost; 1078 1079 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1080 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1081 else 1082 iboost = intel_bios_dp_boost_level(encoder->devdata); 1083 1084 if (iboost == 0) { 1085 const struct intel_ddi_buf_trans *trans; 1086 int n_entries; 1087 1088 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1089 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1090 return; 1091 1092 iboost = trans->entries[level].hsw.i_boost; 1093 } 1094 1095 /* Make sure that the requested I_boost is valid */ 1096 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1097 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1098 return; 1099 } 1100 1101 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1102 1103 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1104 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1105 } 1106 1107 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1108 const struct intel_crtc_state *crtc_state) 1109 { 1110 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 int n_entries; 1113 1114 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1115 1116 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1117 n_entries = 1; 1118 if (drm_WARN_ON(&dev_priv->drm, 1119 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1120 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1121 1122 return index_to_dp_signal_levels[n_entries - 1] & 1123 DP_TRAIN_VOLTAGE_SWING_MASK; 1124 } 1125 1126 /* 1127 * We assume that the full set of pre-emphasis values can be 1128 * used on all DDI platforms. Should that change we need to 1129 * rethink this code. 1130 */ 1131 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1132 { 1133 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1134 } 1135 1136 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1137 int lane) 1138 { 1139 if (crtc_state->port_clock > 600000) 1140 return 0; 1141 1142 if (crtc_state->lane_count == 4) 1143 return lane >= 1 ? LOADGEN_SELECT : 0; 1144 else 1145 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1146 } 1147 1148 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1149 const struct intel_crtc_state *crtc_state) 1150 { 1151 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1152 const struct intel_ddi_buf_trans *trans; 1153 enum phy phy = intel_encoder_to_phy(encoder); 1154 int n_entries, ln; 1155 u32 val; 1156 1157 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1158 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1159 return; 1160 1161 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1162 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1163 1164 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1165 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1166 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1167 intel_dp->hobl_active ? val : 0); 1168 } 1169 1170 /* Set PORT_TX_DW5 */ 1171 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1172 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1173 TAP2_DISABLE | TAP3_DISABLE); 1174 val |= SCALING_MODE_SEL(0x2); 1175 val |= RTERM_SELECT(0x6); 1176 val |= TAP3_DISABLE; 1177 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1178 1179 /* Program PORT_TX_DW2 */ 1180 for (ln = 0; ln < 4; ln++) { 1181 int level = intel_ddi_level(encoder, crtc_state, ln); 1182 1183 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1184 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1185 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1186 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1187 RCOMP_SCALAR(0x98)); 1188 } 1189 1190 /* Program PORT_TX_DW4 */ 1191 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1192 for (ln = 0; ln < 4; ln++) { 1193 int level = intel_ddi_level(encoder, crtc_state, ln); 1194 1195 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1196 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1197 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1198 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1199 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1200 } 1201 1202 /* Program PORT_TX_DW7 */ 1203 for (ln = 0; ln < 4; ln++) { 1204 int level = intel_ddi_level(encoder, crtc_state, ln); 1205 1206 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1207 N_SCALAR_MASK, 1208 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1209 } 1210 } 1211 1212 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1213 const struct intel_crtc_state *crtc_state) 1214 { 1215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1216 enum phy phy = intel_encoder_to_phy(encoder); 1217 u32 val; 1218 int ln; 1219 1220 /* 1221 * 1. If port type is eDP or DP, 1222 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1223 * else clear to 0b. 1224 */ 1225 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1226 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1227 val &= ~COMMON_KEEPER_EN; 1228 else 1229 val |= COMMON_KEEPER_EN; 1230 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1231 1232 /* 2. Program loadgen select */ 1233 /* 1234 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1235 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1236 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1237 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1238 */ 1239 for (ln = 0; ln < 4; ln++) { 1240 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1241 LOADGEN_SELECT, 1242 icl_combo_phy_loadgen_select(crtc_state, ln)); 1243 } 1244 1245 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1246 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1247 0, SUS_CLOCK_CONFIG); 1248 1249 /* 4. Clear training enable to change swing values */ 1250 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1251 val &= ~TX_TRAINING_EN; 1252 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1253 1254 /* 5. Program swing and de-emphasis */ 1255 icl_ddi_combo_vswing_program(encoder, crtc_state); 1256 1257 /* 6. Set training enable to trigger update */ 1258 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1259 val |= TX_TRAINING_EN; 1260 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1261 } 1262 1263 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1264 const struct intel_crtc_state *crtc_state) 1265 { 1266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1267 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1268 const struct intel_ddi_buf_trans *trans; 1269 int n_entries, ln; 1270 1271 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1272 return; 1273 1274 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1275 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1276 return; 1277 1278 for (ln = 0; ln < 2; ln++) { 1279 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1280 CRI_USE_FS32, 0); 1281 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1282 CRI_USE_FS32, 0); 1283 } 1284 1285 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1286 for (ln = 0; ln < 2; ln++) { 1287 int level; 1288 1289 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1290 1291 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1292 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1293 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1294 1295 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1296 1297 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1298 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1299 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1300 } 1301 1302 /* Program MG_TX_DRVCTRL with values from vswing table */ 1303 for (ln = 0; ln < 2; ln++) { 1304 int level; 1305 1306 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1307 1308 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1309 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1310 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1311 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1312 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1313 CRI_TXDEEMPH_OVERRIDE_EN); 1314 1315 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1316 1317 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1318 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1319 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1320 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1321 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1322 CRI_TXDEEMPH_OVERRIDE_EN); 1323 1324 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1325 } 1326 1327 /* 1328 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1329 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1330 * values from table for which TX1 and TX2 enabled. 1331 */ 1332 for (ln = 0; ln < 2; ln++) { 1333 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1334 CFG_LOW_RATE_LKREN_EN, 1335 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1336 } 1337 1338 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1339 for (ln = 0; ln < 2; ln++) { 1340 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1341 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1342 CFG_AMI_CK_DIV_OVERRIDE_EN, 1343 crtc_state->port_clock > 500000 ? 1344 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1345 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1346 1347 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1348 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1349 CFG_AMI_CK_DIV_OVERRIDE_EN, 1350 crtc_state->port_clock > 500000 ? 1351 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1352 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1353 } 1354 1355 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1356 for (ln = 0; ln < 2; ln++) { 1357 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1358 0, CRI_CALCINIT); 1359 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1360 0, CRI_CALCINIT); 1361 } 1362 } 1363 1364 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1365 const struct intel_crtc_state *crtc_state) 1366 { 1367 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1368 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1369 const struct intel_ddi_buf_trans *trans; 1370 int n_entries, ln; 1371 1372 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1373 return; 1374 1375 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1376 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1377 return; 1378 1379 for (ln = 0; ln < 2; ln++) { 1380 int level; 1381 1382 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1383 1384 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1385 1386 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1387 DKL_TX_PRESHOOT_COEFF_MASK | 1388 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1389 DKL_TX_VSWING_CONTROL_MASK, 1390 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1391 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1392 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1393 1394 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1395 1396 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1397 DKL_TX_PRESHOOT_COEFF_MASK | 1398 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1399 DKL_TX_VSWING_CONTROL_MASK, 1400 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1401 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1402 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1403 1404 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1405 DKL_TX_DP20BITMODE, 0); 1406 1407 if (IS_ALDERLAKE_P(dev_priv)) { 1408 u32 val; 1409 1410 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1411 if (ln == 0) { 1412 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1413 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1414 } else { 1415 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1416 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1417 } 1418 } else { 1419 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1420 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1421 } 1422 1423 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1424 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1425 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1426 val); 1427 } 1428 } 1429 } 1430 1431 static int translate_signal_level(struct intel_dp *intel_dp, 1432 u8 signal_levels) 1433 { 1434 struct intel_display *display = to_intel_display(intel_dp); 1435 int i; 1436 1437 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1438 if (index_to_dp_signal_levels[i] == signal_levels) 1439 return i; 1440 } 1441 1442 drm_WARN(display->drm, 1, 1443 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1444 signal_levels); 1445 1446 return 0; 1447 } 1448 1449 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1450 const struct intel_crtc_state *crtc_state, 1451 int lane) 1452 { 1453 u8 train_set = intel_dp->train_set[lane]; 1454 1455 if (intel_dp_is_uhbr(crtc_state)) { 1456 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1457 } else { 1458 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1459 DP_TRAIN_PRE_EMPHASIS_MASK); 1460 1461 return translate_signal_level(intel_dp, signal_levels); 1462 } 1463 } 1464 1465 int intel_ddi_level(struct intel_encoder *encoder, 1466 const struct intel_crtc_state *crtc_state, 1467 int lane) 1468 { 1469 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1470 const struct intel_ddi_buf_trans *trans; 1471 int level, n_entries; 1472 1473 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1474 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1475 return 0; 1476 1477 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1478 level = intel_ddi_hdmi_level(encoder, trans); 1479 else 1480 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1481 lane); 1482 1483 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1484 level = n_entries - 1; 1485 1486 return level; 1487 } 1488 1489 static void 1490 hsw_set_signal_levels(struct intel_encoder *encoder, 1491 const struct intel_crtc_state *crtc_state) 1492 { 1493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1494 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1495 int level = intel_ddi_level(encoder, crtc_state, 0); 1496 enum port port = encoder->port; 1497 u32 signal_levels; 1498 1499 if (has_iboost(dev_priv)) 1500 skl_ddi_set_iboost(encoder, crtc_state, level); 1501 1502 /* HDMI ignores the rest */ 1503 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1504 return; 1505 1506 signal_levels = DDI_BUF_TRANS_SELECT(level); 1507 1508 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1509 signal_levels); 1510 1511 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1512 intel_dp->DP |= signal_levels; 1513 1514 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1515 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1516 } 1517 1518 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1519 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1520 { 1521 mutex_lock(&i915->display.dpll.lock); 1522 1523 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1524 1525 /* 1526 * "This step and the step before must be 1527 * done with separate register writes." 1528 */ 1529 intel_de_rmw(i915, reg, clk_off, 0); 1530 1531 mutex_unlock(&i915->display.dpll.lock); 1532 } 1533 1534 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1535 u32 clk_off) 1536 { 1537 mutex_lock(&i915->display.dpll.lock); 1538 1539 intel_de_rmw(i915, reg, 0, clk_off); 1540 1541 mutex_unlock(&i915->display.dpll.lock); 1542 } 1543 1544 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1545 u32 clk_off) 1546 { 1547 return !(intel_de_read(i915, reg) & clk_off); 1548 } 1549 1550 static struct intel_shared_dpll * 1551 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1552 u32 clk_sel_mask, u32 clk_sel_shift) 1553 { 1554 enum intel_dpll_id id; 1555 1556 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1557 1558 return intel_get_shared_dpll_by_id(i915, id); 1559 } 1560 1561 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1562 const struct intel_crtc_state *crtc_state) 1563 { 1564 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1565 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1566 enum phy phy = intel_encoder_to_phy(encoder); 1567 1568 if (drm_WARN_ON(&i915->drm, !pll)) 1569 return; 1570 1571 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1572 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1573 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1574 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1575 } 1576 1577 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1578 { 1579 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1580 enum phy phy = intel_encoder_to_phy(encoder); 1581 1582 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1583 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1584 } 1585 1586 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1587 { 1588 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1589 enum phy phy = intel_encoder_to_phy(encoder); 1590 1591 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1592 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1593 } 1594 1595 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1596 { 1597 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1598 enum phy phy = intel_encoder_to_phy(encoder); 1599 1600 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1601 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1602 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1603 } 1604 1605 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1606 const struct intel_crtc_state *crtc_state) 1607 { 1608 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1609 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1610 enum phy phy = intel_encoder_to_phy(encoder); 1611 1612 if (drm_WARN_ON(&i915->drm, !pll)) 1613 return; 1614 1615 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1616 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1617 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1618 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1619 } 1620 1621 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1622 { 1623 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1624 enum phy phy = intel_encoder_to_phy(encoder); 1625 1626 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1627 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1628 } 1629 1630 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1631 { 1632 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1633 enum phy phy = intel_encoder_to_phy(encoder); 1634 1635 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1636 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1637 } 1638 1639 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1640 { 1641 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1642 enum phy phy = intel_encoder_to_phy(encoder); 1643 1644 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1645 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1646 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1647 } 1648 1649 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1650 const struct intel_crtc_state *crtc_state) 1651 { 1652 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1653 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1654 enum phy phy = intel_encoder_to_phy(encoder); 1655 1656 if (drm_WARN_ON(&i915->drm, !pll)) 1657 return; 1658 1659 /* 1660 * If we fail this, something went very wrong: first 2 PLLs should be 1661 * used by first 2 phys and last 2 PLLs by last phys 1662 */ 1663 if (drm_WARN_ON(&i915->drm, 1664 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1665 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1666 return; 1667 1668 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1669 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1670 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1671 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1672 } 1673 1674 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1675 { 1676 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1677 enum phy phy = intel_encoder_to_phy(encoder); 1678 1679 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1680 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1681 } 1682 1683 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1684 { 1685 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1686 enum phy phy = intel_encoder_to_phy(encoder); 1687 1688 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1689 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1690 } 1691 1692 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 enum phy phy = intel_encoder_to_phy(encoder); 1696 enum intel_dpll_id id; 1697 u32 val; 1698 1699 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1700 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1701 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1702 id = val; 1703 1704 /* 1705 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1706 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1707 * bit for phy C and D. 1708 */ 1709 if (phy >= PHY_C) 1710 id += DPLL_ID_DG1_DPLL2; 1711 1712 return intel_get_shared_dpll_by_id(i915, id); 1713 } 1714 1715 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1716 const struct intel_crtc_state *crtc_state) 1717 { 1718 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1719 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1720 enum phy phy = intel_encoder_to_phy(encoder); 1721 1722 if (drm_WARN_ON(&i915->drm, !pll)) 1723 return; 1724 1725 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1726 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1727 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1728 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1729 } 1730 1731 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1732 { 1733 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1734 enum phy phy = intel_encoder_to_phy(encoder); 1735 1736 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1737 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1738 } 1739 1740 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1741 { 1742 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1743 enum phy phy = intel_encoder_to_phy(encoder); 1744 1745 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1746 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1747 } 1748 1749 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1750 { 1751 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1752 enum phy phy = intel_encoder_to_phy(encoder); 1753 1754 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1755 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1756 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1757 } 1758 1759 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1760 const struct intel_crtc_state *crtc_state) 1761 { 1762 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1763 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1764 enum port port = encoder->port; 1765 1766 if (drm_WARN_ON(&i915->drm, !pll)) 1767 return; 1768 1769 /* 1770 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1771 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1772 */ 1773 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1774 1775 icl_ddi_combo_enable_clock(encoder, crtc_state); 1776 } 1777 1778 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1779 { 1780 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1781 enum port port = encoder->port; 1782 1783 icl_ddi_combo_disable_clock(encoder); 1784 1785 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1786 } 1787 1788 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1789 { 1790 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1791 enum port port = encoder->port; 1792 u32 tmp; 1793 1794 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1795 1796 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1797 return false; 1798 1799 return icl_ddi_combo_is_clock_enabled(encoder); 1800 } 1801 1802 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1803 const struct intel_crtc_state *crtc_state) 1804 { 1805 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1806 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1807 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1808 enum port port = encoder->port; 1809 1810 if (drm_WARN_ON(&i915->drm, !pll)) 1811 return; 1812 1813 intel_de_write(i915, DDI_CLK_SEL(port), 1814 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1815 1816 mutex_lock(&i915->display.dpll.lock); 1817 1818 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1819 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1820 1821 mutex_unlock(&i915->display.dpll.lock); 1822 } 1823 1824 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1825 { 1826 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1827 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1828 enum port port = encoder->port; 1829 1830 mutex_lock(&i915->display.dpll.lock); 1831 1832 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1833 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1834 1835 mutex_unlock(&i915->display.dpll.lock); 1836 1837 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1838 } 1839 1840 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1841 { 1842 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1843 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1844 enum port port = encoder->port; 1845 u32 tmp; 1846 1847 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1848 1849 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1850 return false; 1851 1852 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1853 1854 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1855 } 1856 1857 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1858 { 1859 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1860 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1861 enum port port = encoder->port; 1862 enum intel_dpll_id id; 1863 u32 tmp; 1864 1865 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1866 1867 switch (tmp & DDI_CLK_SEL_MASK) { 1868 case DDI_CLK_SEL_TBT_162: 1869 case DDI_CLK_SEL_TBT_270: 1870 case DDI_CLK_SEL_TBT_540: 1871 case DDI_CLK_SEL_TBT_810: 1872 id = DPLL_ID_ICL_TBTPLL; 1873 break; 1874 case DDI_CLK_SEL_MG: 1875 id = icl_tc_port_to_pll_id(tc_port); 1876 break; 1877 default: 1878 MISSING_CASE(tmp); 1879 fallthrough; 1880 case DDI_CLK_SEL_NONE: 1881 return NULL; 1882 } 1883 1884 return intel_get_shared_dpll_by_id(i915, id); 1885 } 1886 1887 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1888 { 1889 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1890 enum intel_dpll_id id; 1891 1892 switch (encoder->port) { 1893 case PORT_A: 1894 id = DPLL_ID_SKL_DPLL0; 1895 break; 1896 case PORT_B: 1897 id = DPLL_ID_SKL_DPLL1; 1898 break; 1899 case PORT_C: 1900 id = DPLL_ID_SKL_DPLL2; 1901 break; 1902 default: 1903 MISSING_CASE(encoder->port); 1904 return NULL; 1905 } 1906 1907 return intel_get_shared_dpll_by_id(i915, id); 1908 } 1909 1910 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1911 const struct intel_crtc_state *crtc_state) 1912 { 1913 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1914 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1915 enum port port = encoder->port; 1916 1917 if (drm_WARN_ON(&i915->drm, !pll)) 1918 return; 1919 1920 mutex_lock(&i915->display.dpll.lock); 1921 1922 intel_de_rmw(i915, DPLL_CTRL2, 1923 DPLL_CTRL2_DDI_CLK_OFF(port) | 1924 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1925 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1926 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1927 1928 mutex_unlock(&i915->display.dpll.lock); 1929 } 1930 1931 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1932 { 1933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1934 enum port port = encoder->port; 1935 1936 mutex_lock(&i915->display.dpll.lock); 1937 1938 intel_de_rmw(i915, DPLL_CTRL2, 1939 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1940 1941 mutex_unlock(&i915->display.dpll.lock); 1942 } 1943 1944 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1945 { 1946 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1947 enum port port = encoder->port; 1948 1949 /* 1950 * FIXME Not sure if the override affects both 1951 * the PLL selection and the CLK_OFF bit. 1952 */ 1953 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1954 } 1955 1956 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1957 { 1958 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1959 enum port port = encoder->port; 1960 enum intel_dpll_id id; 1961 u32 tmp; 1962 1963 tmp = intel_de_read(i915, DPLL_CTRL2); 1964 1965 /* 1966 * FIXME Not sure if the override affects both 1967 * the PLL selection and the CLK_OFF bit. 1968 */ 1969 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1970 return NULL; 1971 1972 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1973 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1974 1975 return intel_get_shared_dpll_by_id(i915, id); 1976 } 1977 1978 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1979 const struct intel_crtc_state *crtc_state) 1980 { 1981 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1982 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1983 enum port port = encoder->port; 1984 1985 if (drm_WARN_ON(&i915->drm, !pll)) 1986 return; 1987 1988 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1989 } 1990 1991 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1992 { 1993 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1994 enum port port = encoder->port; 1995 1996 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1997 } 1998 1999 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2000 { 2001 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2002 enum port port = encoder->port; 2003 2004 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2005 } 2006 2007 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2008 { 2009 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2010 enum port port = encoder->port; 2011 enum intel_dpll_id id; 2012 u32 tmp; 2013 2014 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2015 2016 switch (tmp & PORT_CLK_SEL_MASK) { 2017 case PORT_CLK_SEL_WRPLL1: 2018 id = DPLL_ID_WRPLL1; 2019 break; 2020 case PORT_CLK_SEL_WRPLL2: 2021 id = DPLL_ID_WRPLL2; 2022 break; 2023 case PORT_CLK_SEL_SPLL: 2024 id = DPLL_ID_SPLL; 2025 break; 2026 case PORT_CLK_SEL_LCPLL_810: 2027 id = DPLL_ID_LCPLL_810; 2028 break; 2029 case PORT_CLK_SEL_LCPLL_1350: 2030 id = DPLL_ID_LCPLL_1350; 2031 break; 2032 case PORT_CLK_SEL_LCPLL_2700: 2033 id = DPLL_ID_LCPLL_2700; 2034 break; 2035 default: 2036 MISSING_CASE(tmp); 2037 fallthrough; 2038 case PORT_CLK_SEL_NONE: 2039 return NULL; 2040 } 2041 2042 return intel_get_shared_dpll_by_id(i915, id); 2043 } 2044 2045 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2046 const struct intel_crtc_state *crtc_state) 2047 { 2048 if (encoder->enable_clock) 2049 encoder->enable_clock(encoder, crtc_state); 2050 } 2051 2052 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2053 { 2054 if (encoder->disable_clock) 2055 encoder->disable_clock(encoder); 2056 } 2057 2058 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2059 { 2060 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2061 u32 port_mask; 2062 bool ddi_clk_needed; 2063 2064 /* 2065 * In case of DP MST, we sanitize the primary encoder only, not the 2066 * virtual ones. 2067 */ 2068 if (encoder->type == INTEL_OUTPUT_DP_MST) 2069 return; 2070 2071 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2072 u8 pipe_mask; 2073 bool is_mst; 2074 2075 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2076 /* 2077 * In the unlikely case that BIOS enables DP in MST mode, just 2078 * warn since our MST HW readout is incomplete. 2079 */ 2080 if (drm_WARN_ON(&i915->drm, is_mst)) 2081 return; 2082 } 2083 2084 port_mask = BIT(encoder->port); 2085 ddi_clk_needed = encoder->base.crtc; 2086 2087 if (encoder->type == INTEL_OUTPUT_DSI) { 2088 struct intel_encoder *other_encoder; 2089 2090 port_mask = intel_dsi_encoder_ports(encoder); 2091 /* 2092 * Sanity check that we haven't incorrectly registered another 2093 * encoder using any of the ports of this DSI encoder. 2094 */ 2095 for_each_intel_encoder(&i915->drm, other_encoder) { 2096 if (other_encoder == encoder) 2097 continue; 2098 2099 if (drm_WARN_ON(&i915->drm, 2100 port_mask & BIT(other_encoder->port))) 2101 return; 2102 } 2103 /* 2104 * For DSI we keep the ddi clocks gated 2105 * except during enable/disable sequence. 2106 */ 2107 ddi_clk_needed = false; 2108 } 2109 2110 if (ddi_clk_needed || !encoder->is_clock_enabled || 2111 !encoder->is_clock_enabled(encoder)) 2112 return; 2113 2114 drm_dbg_kms(&i915->drm, 2115 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2116 encoder->base.base.id, encoder->base.name); 2117 2118 encoder->disable_clock(encoder); 2119 } 2120 2121 static void 2122 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2123 const struct intel_crtc_state *crtc_state) 2124 { 2125 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2126 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2127 u32 ln0, ln1, pin_assignment; 2128 u8 width; 2129 2130 if (DISPLAY_VER(dev_priv) >= 14) 2131 return; 2132 2133 if (!intel_encoder_is_tc(&dig_port->base) || 2134 intel_tc_port_in_tbt_alt_mode(dig_port)) 2135 return; 2136 2137 if (DISPLAY_VER(dev_priv) >= 12) { 2138 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2139 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2140 } else { 2141 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2142 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2143 } 2144 2145 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2146 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2147 2148 /* DPPATC */ 2149 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2150 width = crtc_state->lane_count; 2151 2152 switch (pin_assignment) { 2153 case 0x0: 2154 drm_WARN_ON(&dev_priv->drm, 2155 !intel_tc_port_in_legacy_mode(dig_port)); 2156 if (width == 1) { 2157 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2158 } else { 2159 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2160 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2161 } 2162 break; 2163 case 0x1: 2164 if (width == 4) { 2165 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2166 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2167 } 2168 break; 2169 case 0x2: 2170 if (width == 2) { 2171 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2172 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2173 } 2174 break; 2175 case 0x3: 2176 case 0x5: 2177 if (width == 1) { 2178 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2179 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2180 } else { 2181 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2182 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2183 } 2184 break; 2185 case 0x4: 2186 case 0x6: 2187 if (width == 1) { 2188 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2189 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2190 } else { 2191 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2192 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2193 } 2194 break; 2195 default: 2196 MISSING_CASE(pin_assignment); 2197 } 2198 2199 if (DISPLAY_VER(dev_priv) >= 12) { 2200 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2201 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2202 } else { 2203 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2204 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2205 } 2206 } 2207 2208 static enum transcoder 2209 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2210 { 2211 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2212 return crtc_state->mst_master_transcoder; 2213 else 2214 return crtc_state->cpu_transcoder; 2215 } 2216 2217 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2218 const struct intel_crtc_state *crtc_state) 2219 { 2220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2221 2222 if (DISPLAY_VER(dev_priv) >= 12) 2223 return TGL_DP_TP_CTL(dev_priv, 2224 tgl_dp_tp_transcoder(crtc_state)); 2225 else 2226 return DP_TP_CTL(encoder->port); 2227 } 2228 2229 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2230 const struct intel_crtc_state *crtc_state) 2231 { 2232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2233 2234 if (DISPLAY_VER(dev_priv) >= 12) 2235 return TGL_DP_TP_STATUS(dev_priv, 2236 tgl_dp_tp_transcoder(crtc_state)); 2237 else 2238 return DP_TP_STATUS(encoder->port); 2239 } 2240 2241 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2242 const struct intel_crtc_state *crtc_state) 2243 { 2244 struct intel_display *display = to_intel_display(encoder); 2245 2246 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2247 DP_TP_STATUS_ACT_SENT); 2248 } 2249 2250 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2251 const struct intel_crtc_state *crtc_state) 2252 { 2253 struct intel_display *display = to_intel_display(encoder); 2254 2255 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2256 DP_TP_STATUS_ACT_SENT, 1)) 2257 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2258 } 2259 2260 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2261 const struct intel_crtc_state *crtc_state, 2262 bool enable) 2263 { 2264 struct intel_display *display = to_intel_display(intel_dp); 2265 2266 if (!crtc_state->vrr.enable) 2267 return; 2268 2269 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2270 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2271 drm_dbg_kms(display->drm, 2272 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2273 str_enable_disable(enable)); 2274 } 2275 2276 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2277 const struct intel_crtc_state *crtc_state, 2278 bool enable) 2279 { 2280 struct intel_display *display = to_intel_display(intel_dp); 2281 2282 if (!crtc_state->fec_enable) 2283 return; 2284 2285 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2286 enable ? DP_FEC_READY : 0) <= 0) 2287 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2288 str_enabled_disabled(enable)); 2289 2290 if (enable && 2291 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2292 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2293 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2294 } 2295 2296 static int read_fec_detected_status(struct drm_dp_aux *aux) 2297 { 2298 int ret; 2299 u8 status; 2300 2301 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2302 if (ret < 0) 2303 return ret; 2304 2305 return status; 2306 } 2307 2308 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2309 { 2310 struct intel_display *display = to_intel_display(aux->drm_dev); 2311 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2312 int status; 2313 int err; 2314 2315 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2316 status & mask || status < 0, 2317 10000, 200000); 2318 2319 if (err || status < 0) { 2320 drm_dbg_kms(display->drm, 2321 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2322 str_enabled_disabled(enabled), err, status); 2323 return err ? err : status; 2324 } 2325 2326 return 0; 2327 } 2328 2329 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2330 const struct intel_crtc_state *crtc_state, 2331 bool enabled) 2332 { 2333 struct intel_display *display = to_intel_display(encoder); 2334 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2335 int ret; 2336 2337 if (!crtc_state->fec_enable) 2338 return 0; 2339 2340 if (enabled) 2341 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2342 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2343 else 2344 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2345 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2346 2347 if (ret) { 2348 drm_err(display->drm, 2349 "Timeout waiting for FEC live state to get %s\n", 2350 str_enabled_disabled(enabled)); 2351 return ret; 2352 } 2353 /* 2354 * At least the Synoptics MST hub doesn't set the detected flag for 2355 * FEC decoding disabling so skip waiting for that. 2356 */ 2357 if (enabled) { 2358 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2359 if (ret) 2360 return ret; 2361 } 2362 2363 return 0; 2364 } 2365 2366 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2367 const struct intel_crtc_state *crtc_state) 2368 { 2369 struct intel_display *display = to_intel_display(encoder); 2370 int i; 2371 int ret; 2372 2373 if (!crtc_state->fec_enable) 2374 return; 2375 2376 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2377 0, DP_TP_CTL_FEC_ENABLE); 2378 2379 if (DISPLAY_VER(display) < 30) 2380 return; 2381 2382 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2383 if (!ret) 2384 return; 2385 2386 for (i = 0; i < 3; i++) { 2387 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2388 2389 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2390 DP_TP_CTL_FEC_ENABLE, 0); 2391 2392 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2393 if (ret) 2394 continue; 2395 2396 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2397 0, DP_TP_CTL_FEC_ENABLE); 2398 2399 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2400 if (!ret) 2401 return; 2402 } 2403 2404 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2405 } 2406 2407 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2408 const struct intel_crtc_state *crtc_state) 2409 { 2410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2411 2412 if (!crtc_state->fec_enable) 2413 return; 2414 2415 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2416 DP_TP_CTL_FEC_ENABLE, 0); 2417 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2418 } 2419 2420 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2421 const struct intel_crtc_state *crtc_state) 2422 { 2423 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2424 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2425 2426 if (intel_encoder_is_combo(encoder)) { 2427 enum phy phy = intel_encoder_to_phy(encoder); 2428 2429 intel_combo_phy_power_up_lanes(i915, phy, false, 2430 crtc_state->lane_count, 2431 dig_port->lane_reversal); 2432 } 2433 } 2434 2435 /* 2436 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2437 * platforms. 2438 */ 2439 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2440 { 2441 if (DISPLAY_VER(i915) > 20) 2442 return ~0; 2443 else if (IS_ALDERLAKE_P(i915)) 2444 return BIT(PIPE_A) | BIT(PIPE_B); 2445 else 2446 return BIT(PIPE_A); 2447 } 2448 2449 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2450 struct intel_crtc_state *pipe_config) 2451 { 2452 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2453 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2454 enum pipe pipe = crtc->pipe; 2455 u32 dss1; 2456 2457 if (!HAS_MSO(i915)) 2458 return; 2459 2460 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2461 2462 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2463 if (!pipe_config->splitter.enable) 2464 return; 2465 2466 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2467 pipe_config->splitter.enable = false; 2468 return; 2469 } 2470 2471 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2472 default: 2473 drm_WARN(&i915->drm, true, 2474 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2475 fallthrough; 2476 case SPLITTER_CONFIGURATION_2_SEGMENT: 2477 pipe_config->splitter.link_count = 2; 2478 break; 2479 case SPLITTER_CONFIGURATION_4_SEGMENT: 2480 pipe_config->splitter.link_count = 4; 2481 break; 2482 } 2483 2484 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2485 } 2486 2487 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2488 { 2489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2490 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2491 enum pipe pipe = crtc->pipe; 2492 u32 dss1 = 0; 2493 2494 if (!HAS_MSO(i915)) 2495 return; 2496 2497 if (crtc_state->splitter.enable) { 2498 dss1 |= SPLITTER_ENABLE; 2499 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2500 if (crtc_state->splitter.link_count == 2) 2501 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2502 else 2503 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2504 } 2505 2506 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2507 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2508 OVERLAP_PIXELS_MASK, dss1); 2509 } 2510 2511 static u8 mtl_get_port_width(u8 lane_count) 2512 { 2513 switch (lane_count) { 2514 case 1: 2515 return 0; 2516 case 2: 2517 return 1; 2518 case 3: 2519 return 4; 2520 case 4: 2521 return 3; 2522 default: 2523 MISSING_CASE(lane_count); 2524 return 4; 2525 } 2526 } 2527 2528 static void 2529 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2530 { 2531 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2532 enum port port = encoder->port; 2533 i915_reg_t reg; 2534 u32 set_bits, wait_bits; 2535 2536 if (DISPLAY_VER(dev_priv) >= 20) { 2537 reg = DDI_BUF_CTL(port); 2538 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2539 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2540 } else { 2541 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2542 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2543 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2544 } 2545 2546 intel_de_rmw(dev_priv, reg, 0, set_bits); 2547 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2548 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2549 port_name(port)); 2550 } 2551 } 2552 2553 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2554 const struct intel_crtc_state *crtc_state) 2555 { 2556 struct intel_display *display = to_intel_display(encoder); 2557 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2558 enum port port = encoder->port; 2559 u32 val = 0; 2560 2561 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2562 2563 if (intel_dp_is_uhbr(crtc_state)) 2564 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2565 else 2566 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2567 2568 if (dig_port->lane_reversal) 2569 val |= XELPDP_PORT_REVERSAL; 2570 2571 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2572 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2573 val); 2574 } 2575 2576 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2577 { 2578 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2579 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2580 u32 val; 2581 2582 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2583 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2584 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2585 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2586 } 2587 2588 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2589 struct intel_encoder *encoder, 2590 const struct intel_crtc_state *crtc_state, 2591 const struct drm_connector_state *conn_state) 2592 { 2593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2594 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2595 int ret; 2596 2597 intel_dp_set_link_params(intel_dp, 2598 crtc_state->port_clock, 2599 crtc_state->lane_count); 2600 2601 /* 2602 * We only configure what the register value will be here. Actual 2603 * enabling happens during link training farther down. 2604 */ 2605 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2606 2607 /* 2608 * 1. Enable Power Wells 2609 * 2610 * This was handled at the beginning of intel_atomic_commit_tail(), 2611 * before we called down into this function. 2612 */ 2613 2614 /* 2. PMdemand was already set */ 2615 2616 /* 3. Select Thunderbolt */ 2617 mtl_port_buf_ctl_io_selection(encoder); 2618 2619 /* 4. Enable Panel Power if PPS is required */ 2620 intel_pps_on(intel_dp); 2621 2622 /* 5. Enable the port PLL */ 2623 intel_ddi_enable_clock(encoder, crtc_state); 2624 2625 /* 2626 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2627 * Transcoder. 2628 */ 2629 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2630 2631 /* 2632 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2633 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2634 * Transport Select 2635 */ 2636 intel_ddi_config_transcoder_func(encoder, crtc_state); 2637 2638 /* 2639 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2640 */ 2641 intel_ddi_mso_configure(crtc_state); 2642 2643 if (!is_mst) 2644 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2645 2646 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2647 if (!is_mst) 2648 intel_dp_sink_enable_decompression(state, 2649 to_intel_connector(conn_state->connector), 2650 crtc_state); 2651 2652 /* 2653 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2654 * in the FEC_CONFIGURATION register to 1 before initiating link 2655 * training 2656 */ 2657 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2658 2659 intel_dp_check_frl_training(intel_dp); 2660 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2661 2662 /* 2663 * 6. The rest of the below are substeps under the bspec's "Enable and 2664 * Train Display Port" step. Note that steps that are specific to 2665 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2666 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2667 * us when active_mst_links==0, so any steps designated for "single 2668 * stream or multi-stream master transcoder" can just be performed 2669 * unconditionally here. 2670 * 2671 * mtl_ddi_prepare_link_retrain() that is called by 2672 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2673 * 6.i and 6.j 2674 * 2675 * 6.k Follow DisplayPort specification training sequence (see notes for 2676 * failure handling) 2677 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2678 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2679 * (timeout after 800 us) 2680 */ 2681 intel_dp_start_link_train(state, intel_dp, crtc_state); 2682 2683 /* 6.n Set DP_TP_CTL link training to Normal */ 2684 if (!is_trans_port_sync_mode(crtc_state)) 2685 intel_dp_stop_link_train(intel_dp, crtc_state); 2686 2687 /* 6.o Configure and enable FEC if needed */ 2688 intel_ddi_enable_fec(encoder, crtc_state); 2689 2690 /* 7.a 128b/132b SST. */ 2691 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2692 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2693 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2694 if (ret < 0) 2695 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2696 } 2697 2698 if (!is_mst) 2699 intel_dsc_dp_pps_write(encoder, crtc_state); 2700 } 2701 2702 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2703 struct intel_encoder *encoder, 2704 const struct intel_crtc_state *crtc_state, 2705 const struct drm_connector_state *conn_state) 2706 { 2707 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2708 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2709 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2710 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2711 int ret; 2712 2713 intel_dp_set_link_params(intel_dp, 2714 crtc_state->port_clock, 2715 crtc_state->lane_count); 2716 2717 /* 2718 * We only configure what the register value will be here. Actual 2719 * enabling happens during link training farther down. 2720 */ 2721 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2722 2723 /* 2724 * 1. Enable Power Wells 2725 * 2726 * This was handled at the beginning of intel_atomic_commit_tail(), 2727 * before we called down into this function. 2728 */ 2729 2730 /* 2. Enable Panel Power if PPS is required */ 2731 intel_pps_on(intel_dp); 2732 2733 /* 2734 * 3. For non-TBT Type-C ports, set FIA lane count 2735 * (DFLEXDPSP.DPX4TXLATC) 2736 * 2737 * This was done before tgl_ddi_pre_enable_dp by 2738 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2739 */ 2740 2741 /* 2742 * 4. Enable the port PLL. 2743 * 2744 * The PLL enabling itself was already done before this function by 2745 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2746 * configure the PLL to port mapping here. 2747 */ 2748 intel_ddi_enable_clock(encoder, crtc_state); 2749 2750 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2751 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2752 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2753 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2754 dig_port->ddi_io_power_domain); 2755 } 2756 2757 /* 6. Program DP_MODE */ 2758 icl_program_mg_dp_mode(dig_port, crtc_state); 2759 2760 /* 2761 * 7. The rest of the below are substeps under the bspec's "Enable and 2762 * Train Display Port" step. Note that steps that are specific to 2763 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2764 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2765 * us when active_mst_links==0, so any steps designated for "single 2766 * stream or multi-stream master transcoder" can just be performed 2767 * unconditionally here. 2768 */ 2769 2770 /* 2771 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2772 * Transcoder. 2773 */ 2774 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2775 2776 /* 2777 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2778 * Transport Select 2779 */ 2780 intel_ddi_config_transcoder_func(encoder, crtc_state); 2781 2782 /* 2783 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2784 * selected 2785 * 2786 * This will be handled by the intel_dp_start_link_train() farther 2787 * down this function. 2788 */ 2789 2790 /* 7.e Configure voltage swing and related IO settings */ 2791 encoder->set_signal_levels(encoder, crtc_state); 2792 2793 /* 2794 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2795 * the used lanes of the DDI. 2796 */ 2797 intel_ddi_power_up_lanes(encoder, crtc_state); 2798 2799 /* 2800 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2801 */ 2802 intel_ddi_mso_configure(crtc_state); 2803 2804 if (!is_mst) 2805 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2806 2807 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2808 if (!is_mst) 2809 intel_dp_sink_enable_decompression(state, 2810 to_intel_connector(conn_state->connector), 2811 crtc_state); 2812 /* 2813 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2814 * in the FEC_CONFIGURATION register to 1 before initiating link 2815 * training 2816 */ 2817 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2818 2819 intel_dp_check_frl_training(intel_dp); 2820 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2821 2822 /* 2823 * 7.i Follow DisplayPort specification training sequence (see notes for 2824 * failure handling) 2825 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2826 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2827 * (timeout after 800 us) 2828 */ 2829 intel_dp_start_link_train(state, intel_dp, crtc_state); 2830 2831 /* 7.k Set DP_TP_CTL link training to Normal */ 2832 if (!is_trans_port_sync_mode(crtc_state)) 2833 intel_dp_stop_link_train(intel_dp, crtc_state); 2834 2835 /* 7.l Configure and enable FEC if needed */ 2836 intel_ddi_enable_fec(encoder, crtc_state); 2837 2838 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2839 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2840 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2841 if (ret < 0) 2842 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2843 } 2844 2845 if (!is_mst) 2846 intel_dsc_dp_pps_write(encoder, crtc_state); 2847 } 2848 2849 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2850 struct intel_encoder *encoder, 2851 const struct intel_crtc_state *crtc_state, 2852 const struct drm_connector_state *conn_state) 2853 { 2854 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2855 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2856 enum port port = encoder->port; 2857 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2858 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2859 2860 if (DISPLAY_VER(dev_priv) < 11) 2861 drm_WARN_ON(&dev_priv->drm, 2862 is_mst && (port == PORT_A || port == PORT_E)); 2863 else 2864 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2865 2866 intel_dp_set_link_params(intel_dp, 2867 crtc_state->port_clock, 2868 crtc_state->lane_count); 2869 2870 /* 2871 * We only configure what the register value will be here. Actual 2872 * enabling happens during link training farther down. 2873 */ 2874 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2875 2876 intel_pps_on(intel_dp); 2877 2878 intel_ddi_enable_clock(encoder, crtc_state); 2879 2880 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2881 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2882 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2883 dig_port->ddi_io_power_domain); 2884 } 2885 2886 icl_program_mg_dp_mode(dig_port, crtc_state); 2887 2888 if (has_buf_trans_select(dev_priv)) 2889 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2890 2891 encoder->set_signal_levels(encoder, crtc_state); 2892 2893 intel_ddi_power_up_lanes(encoder, crtc_state); 2894 2895 if (!is_mst) 2896 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2897 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2898 if (!is_mst) 2899 intel_dp_sink_enable_decompression(state, 2900 to_intel_connector(conn_state->connector), 2901 crtc_state); 2902 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2903 intel_dp_start_link_train(state, intel_dp, crtc_state); 2904 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2905 !is_trans_port_sync_mode(crtc_state)) 2906 intel_dp_stop_link_train(intel_dp, crtc_state); 2907 2908 intel_ddi_enable_fec(encoder, crtc_state); 2909 2910 if (!is_mst) { 2911 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2912 intel_dsc_dp_pps_write(encoder, crtc_state); 2913 } 2914 } 2915 2916 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2917 struct intel_encoder *encoder, 2918 const struct intel_crtc_state *crtc_state, 2919 const struct drm_connector_state *conn_state) 2920 { 2921 struct intel_display *display = to_intel_display(encoder); 2922 2923 if (HAS_DP20(display)) 2924 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2925 crtc_state); 2926 2927 /* Panel replay has to be enabled in sink dpcd before link training. */ 2928 if (crtc_state->has_panel_replay) 2929 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2930 2931 if (DISPLAY_VER(display) >= 14) 2932 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2933 else if (DISPLAY_VER(display) >= 12) 2934 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2935 else 2936 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2937 2938 /* MST will call a setting of MSA after an allocating of Virtual Channel 2939 * from MST encoder pre_enable callback. 2940 */ 2941 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2942 intel_ddi_set_dp_msa(crtc_state, conn_state); 2943 } 2944 2945 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2946 struct intel_encoder *encoder, 2947 const struct intel_crtc_state *crtc_state, 2948 const struct drm_connector_state *conn_state) 2949 { 2950 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2951 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2952 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2953 2954 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2955 intel_ddi_enable_clock(encoder, crtc_state); 2956 2957 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2958 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2959 dig_port->ddi_io_power_domain); 2960 2961 icl_program_mg_dp_mode(dig_port, crtc_state); 2962 2963 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2964 2965 dig_port->set_infoframes(encoder, 2966 crtc_state->has_infoframe, 2967 crtc_state, conn_state); 2968 } 2969 2970 /* 2971 * Note: Also called from the ->pre_enable of the first active MST stream 2972 * encoder on its primary encoder. 2973 * 2974 * When called from DP MST code: 2975 * 2976 * - conn_state will be NULL 2977 * 2978 * - encoder will be the primary encoder (i.e. mst->primary) 2979 * 2980 * - the main connector associated with this port won't be active or linked to a 2981 * crtc 2982 * 2983 * - crtc_state will be the state of the first stream to be activated on this 2984 * port, and it may not be the same stream that will be deactivated last, but 2985 * each stream should have a state that is identical when it comes to the DP 2986 * link parameteres 2987 */ 2988 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2989 struct intel_encoder *encoder, 2990 const struct intel_crtc_state *crtc_state, 2991 const struct drm_connector_state *conn_state) 2992 { 2993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2995 enum pipe pipe = crtc->pipe; 2996 2997 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2998 2999 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3000 3001 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3002 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3003 conn_state); 3004 } else { 3005 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3006 3007 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3008 conn_state); 3009 3010 /* FIXME precompute everything properly */ 3011 /* FIXME how do we turn infoframes off again? */ 3012 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3013 dig_port->set_infoframes(encoder, 3014 crtc_state->has_infoframe, 3015 crtc_state, conn_state); 3016 } 3017 } 3018 3019 static void 3020 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 3021 { 3022 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3023 enum port port = encoder->port; 3024 i915_reg_t reg; 3025 u32 clr_bits, wait_bits; 3026 3027 if (DISPLAY_VER(dev_priv) >= 20) { 3028 reg = DDI_BUF_CTL(port); 3029 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3030 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3031 } else { 3032 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 3033 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3034 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3035 } 3036 3037 intel_de_rmw(dev_priv, reg, clr_bits, 0); 3038 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 3039 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3040 port_name(port)); 3041 } 3042 3043 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 3044 const struct intel_crtc_state *crtc_state) 3045 { 3046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3047 enum port port = encoder->port; 3048 u32 val; 3049 3050 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 3051 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3052 if (val & DDI_BUF_CTL_ENABLE) { 3053 val &= ~DDI_BUF_CTL_ENABLE; 3054 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3055 3056 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 3057 mtl_wait_ddi_buf_idle(dev_priv, port); 3058 } 3059 3060 /* 3.d Disable D2D Link */ 3061 mtl_ddi_disable_d2d_link(encoder); 3062 3063 /* 3.e Disable DP_TP_CTL */ 3064 if (intel_crtc_has_dp_encoder(crtc_state)) { 3065 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3066 DP_TP_CTL_ENABLE, 0); 3067 } 3068 } 3069 3070 static void disable_ddi_buf(struct intel_encoder *encoder, 3071 const struct intel_crtc_state *crtc_state) 3072 { 3073 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3074 enum port port = encoder->port; 3075 bool wait = false; 3076 u32 val; 3077 3078 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3079 if (val & DDI_BUF_CTL_ENABLE) { 3080 val &= ~DDI_BUF_CTL_ENABLE; 3081 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3082 wait = true; 3083 } 3084 3085 if (intel_crtc_has_dp_encoder(crtc_state)) 3086 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3087 DP_TP_CTL_ENABLE, 0); 3088 3089 intel_ddi_disable_fec(encoder, crtc_state); 3090 3091 if (wait) 3092 intel_wait_ddi_buf_idle(dev_priv, port); 3093 } 3094 3095 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3096 const struct intel_crtc_state *crtc_state) 3097 { 3098 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3099 3100 if (DISPLAY_VER(dev_priv) >= 14) { 3101 mtl_disable_ddi_buf(encoder, crtc_state); 3102 3103 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3104 intel_ddi_disable_fec(encoder, crtc_state); 3105 } else { 3106 disable_ddi_buf(encoder, crtc_state); 3107 } 3108 3109 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3110 } 3111 3112 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3113 struct intel_encoder *encoder, 3114 const struct intel_crtc_state *old_crtc_state, 3115 const struct drm_connector_state *old_conn_state) 3116 { 3117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3118 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3119 struct intel_dp *intel_dp = &dig_port->dp; 3120 intel_wakeref_t wakeref; 3121 bool is_mst = intel_crtc_has_type(old_crtc_state, 3122 INTEL_OUTPUT_DP_MST); 3123 3124 if (!is_mst) 3125 intel_dp_set_infoframes(encoder, false, 3126 old_crtc_state, old_conn_state); 3127 3128 /* 3129 * Power down sink before disabling the port, otherwise we end 3130 * up getting interrupts from the sink on detecting link loss. 3131 */ 3132 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3133 3134 if (DISPLAY_VER(dev_priv) >= 12) { 3135 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3136 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3137 3138 intel_de_rmw(dev_priv, 3139 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3140 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3141 0); 3142 } 3143 } else { 3144 if (!is_mst) 3145 intel_ddi_disable_transcoder_clock(old_crtc_state); 3146 } 3147 3148 intel_disable_ddi_buf(encoder, old_crtc_state); 3149 3150 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3151 3152 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3153 3154 /* 3155 * From TGL spec: "If single stream or multi-stream master transcoder: 3156 * Configure Transcoder Clock select to direct no clock to the 3157 * transcoder" 3158 */ 3159 if (DISPLAY_VER(dev_priv) >= 12) 3160 intel_ddi_disable_transcoder_clock(old_crtc_state); 3161 3162 intel_pps_vdd_on(intel_dp); 3163 intel_pps_off(intel_dp); 3164 3165 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3166 3167 if (wakeref) 3168 intel_display_power_put(dev_priv, 3169 dig_port->ddi_io_power_domain, 3170 wakeref); 3171 3172 intel_ddi_disable_clock(encoder); 3173 3174 /* De-select Thunderbolt */ 3175 if (DISPLAY_VER(dev_priv) >= 14) 3176 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3177 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3178 } 3179 3180 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3181 struct intel_encoder *encoder, 3182 const struct intel_crtc_state *old_crtc_state, 3183 const struct drm_connector_state *old_conn_state) 3184 { 3185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3186 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3187 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3188 intel_wakeref_t wakeref; 3189 3190 dig_port->set_infoframes(encoder, false, 3191 old_crtc_state, old_conn_state); 3192 3193 if (DISPLAY_VER(dev_priv) < 12) 3194 intel_ddi_disable_transcoder_clock(old_crtc_state); 3195 3196 intel_disable_ddi_buf(encoder, old_crtc_state); 3197 3198 if (DISPLAY_VER(dev_priv) >= 12) 3199 intel_ddi_disable_transcoder_clock(old_crtc_state); 3200 3201 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3202 if (wakeref) 3203 intel_display_power_put(dev_priv, 3204 dig_port->ddi_io_power_domain, 3205 wakeref); 3206 3207 intel_ddi_disable_clock(encoder); 3208 3209 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3210 } 3211 3212 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3213 struct intel_encoder *encoder, 3214 const struct intel_crtc_state *old_crtc_state, 3215 const struct drm_connector_state *old_conn_state) 3216 { 3217 struct intel_display *display = to_intel_display(encoder); 3218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3219 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3220 struct intel_crtc *pipe_crtc; 3221 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3222 int i; 3223 3224 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3225 const struct intel_crtc_state *old_pipe_crtc_state = 3226 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3227 3228 intel_crtc_vblank_off(old_pipe_crtc_state); 3229 } 3230 3231 intel_disable_transcoder(old_crtc_state); 3232 3233 /* 128b/132b SST */ 3234 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3235 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3236 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3237 3238 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3239 3240 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3241 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3242 3243 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3244 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3245 } 3246 3247 intel_ddi_disable_transcoder_func(old_crtc_state); 3248 3249 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3250 const struct intel_crtc_state *old_pipe_crtc_state = 3251 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3252 3253 intel_dsc_disable(old_pipe_crtc_state); 3254 3255 if (DISPLAY_VER(dev_priv) >= 9) 3256 skl_scaler_disable(old_pipe_crtc_state); 3257 else 3258 ilk_pfit_disable(old_pipe_crtc_state); 3259 } 3260 } 3261 3262 /* 3263 * Note: Also called from the ->post_disable of the last active MST stream 3264 * encoder on its primary encoder. See also the comment for 3265 * intel_ddi_pre_enable(). 3266 */ 3267 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3268 struct intel_encoder *encoder, 3269 const struct intel_crtc_state *old_crtc_state, 3270 const struct drm_connector_state *old_conn_state) 3271 { 3272 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3273 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3274 old_conn_state); 3275 3276 /* 3277 * When called from DP MST code: 3278 * - old_conn_state will be NULL 3279 * - encoder will be the main encoder (ie. mst->primary) 3280 * - the main connector associated with this port 3281 * won't be active or linked to a crtc 3282 * - old_crtc_state will be the state of the last stream to 3283 * be deactivated on this port, and it may not be the same 3284 * stream that was activated last, but each stream 3285 * should have a state that is identical when it comes to 3286 * the DP link parameteres 3287 */ 3288 3289 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3290 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3291 old_conn_state); 3292 else 3293 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3294 old_conn_state); 3295 } 3296 3297 /* 3298 * Note: Also called from the ->post_pll_disable of the last active MST stream 3299 * encoder on its primary encoder. See also the comment for 3300 * intel_ddi_pre_enable(). 3301 */ 3302 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3303 struct intel_encoder *encoder, 3304 const struct intel_crtc_state *old_crtc_state, 3305 const struct drm_connector_state *old_conn_state) 3306 { 3307 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3308 3309 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3310 3311 if (intel_encoder_is_tc(encoder)) 3312 intel_tc_port_put_link(dig_port); 3313 } 3314 3315 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3316 struct intel_encoder *encoder, 3317 const struct intel_crtc_state *crtc_state) 3318 { 3319 const struct drm_connector_state *conn_state; 3320 struct drm_connector *conn; 3321 int i; 3322 3323 if (!crtc_state->sync_mode_slaves_mask) 3324 return; 3325 3326 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3327 struct intel_encoder *slave_encoder = 3328 to_intel_encoder(conn_state->best_encoder); 3329 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3330 const struct intel_crtc_state *slave_crtc_state; 3331 3332 if (!slave_crtc) 3333 continue; 3334 3335 slave_crtc_state = 3336 intel_atomic_get_new_crtc_state(state, slave_crtc); 3337 3338 if (slave_crtc_state->master_transcoder != 3339 crtc_state->cpu_transcoder) 3340 continue; 3341 3342 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3343 slave_crtc_state); 3344 } 3345 3346 usleep_range(200, 400); 3347 3348 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3349 crtc_state); 3350 } 3351 3352 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3353 struct intel_encoder *encoder, 3354 const struct intel_crtc_state *crtc_state, 3355 const struct drm_connector_state *conn_state) 3356 { 3357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3358 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3359 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3360 enum port port = encoder->port; 3361 3362 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3363 intel_dp_stop_link_train(intel_dp, crtc_state); 3364 3365 drm_connector_update_privacy_screen(conn_state); 3366 intel_edp_backlight_on(crtc_state, conn_state); 3367 3368 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3369 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3370 3371 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3372 } 3373 3374 static i915_reg_t 3375 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3376 { 3377 static const enum transcoder trans[] = { 3378 [PORT_A] = TRANSCODER_EDP, 3379 [PORT_B] = TRANSCODER_A, 3380 [PORT_C] = TRANSCODER_B, 3381 [PORT_D] = TRANSCODER_C, 3382 [PORT_E] = TRANSCODER_A, 3383 }; 3384 3385 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3386 3387 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3388 port = PORT_A; 3389 3390 return CHICKEN_TRANS(display, trans[port]); 3391 } 3392 3393 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3394 struct intel_encoder *encoder, 3395 const struct intel_crtc_state *crtc_state, 3396 const struct drm_connector_state *conn_state) 3397 { 3398 struct intel_display *display = to_intel_display(encoder); 3399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3400 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3401 struct drm_connector *connector = conn_state->connector; 3402 enum port port = encoder->port; 3403 u32 buf_ctl; 3404 3405 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3406 crtc_state->hdmi_high_tmds_clock_ratio, 3407 crtc_state->hdmi_scrambling)) 3408 drm_dbg_kms(&dev_priv->drm, 3409 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3410 connector->base.id, connector->name); 3411 3412 if (has_buf_trans_select(dev_priv)) 3413 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3414 3415 /* e. Enable D2D Link for C10/C20 Phy */ 3416 if (DISPLAY_VER(dev_priv) >= 14) 3417 mtl_ddi_enable_d2d(encoder); 3418 3419 encoder->set_signal_levels(encoder, crtc_state); 3420 3421 /* Display WA #1143: skl,kbl,cfl */ 3422 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3423 /* 3424 * For some reason these chicken bits have been 3425 * stuffed into a transcoder register, event though 3426 * the bits affect a specific DDI port rather than 3427 * a specific transcoder. 3428 */ 3429 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3430 u32 val; 3431 3432 val = intel_de_read(dev_priv, reg); 3433 3434 if (port == PORT_E) 3435 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3436 DDIE_TRAINING_OVERRIDE_VALUE; 3437 else 3438 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3439 DDI_TRAINING_OVERRIDE_VALUE; 3440 3441 intel_de_write(dev_priv, reg, val); 3442 intel_de_posting_read(dev_priv, reg); 3443 3444 udelay(1); 3445 3446 if (port == PORT_E) 3447 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3448 DDIE_TRAINING_OVERRIDE_VALUE); 3449 else 3450 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3451 DDI_TRAINING_OVERRIDE_VALUE); 3452 3453 intel_de_write(dev_priv, reg, val); 3454 } 3455 3456 intel_ddi_power_up_lanes(encoder, crtc_state); 3457 3458 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3459 * are ignored so nothing special needs to be done besides 3460 * enabling the port. 3461 * 3462 * On ADL_P the PHY link rate and lane count must be programmed but 3463 * these are both 0 for HDMI. 3464 * 3465 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3466 * is filled with lane count, already set in the crtc_state. 3467 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3468 */ 3469 buf_ctl = DDI_BUF_CTL_ENABLE; 3470 3471 if (dig_port->lane_reversal) 3472 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3473 if (dig_port->ddi_a_4_lanes) 3474 buf_ctl |= DDI_A_4_LANES; 3475 3476 if (DISPLAY_VER(dev_priv) >= 14) { 3477 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3478 u32 port_buf = 0; 3479 3480 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3481 3482 if (dig_port->lane_reversal) 3483 port_buf |= XELPDP_PORT_REVERSAL; 3484 3485 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3486 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3487 3488 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3489 3490 if (DISPLAY_VER(dev_priv) >= 20) 3491 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3492 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3493 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3494 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3495 } 3496 3497 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3498 3499 intel_wait_ddi_buf_active(encoder); 3500 } 3501 3502 static void intel_ddi_enable(struct intel_atomic_state *state, 3503 struct intel_encoder *encoder, 3504 const struct intel_crtc_state *crtc_state, 3505 const struct drm_connector_state *conn_state) 3506 { 3507 struct intel_display *display = to_intel_display(encoder); 3508 struct intel_crtc *pipe_crtc; 3509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3510 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3511 int i; 3512 3513 /* 128b/132b SST */ 3514 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3515 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3516 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3517 3518 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3519 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3520 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3521 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3522 } 3523 3524 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3525 3526 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3527 intel_audio_sdp_split_update(crtc_state); 3528 3529 /* 128b/132b SST */ 3530 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3531 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3532 3533 intel_ddi_clear_act_sent(encoder, crtc_state); 3534 3535 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3536 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3537 3538 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3539 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3540 } 3541 3542 intel_enable_transcoder(crtc_state); 3543 3544 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3545 3546 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3547 const struct intel_crtc_state *pipe_crtc_state = 3548 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3549 3550 intel_crtc_vblank_on(pipe_crtc_state); 3551 } 3552 3553 if (is_hdmi) 3554 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3555 else 3556 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3557 3558 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3559 3560 } 3561 3562 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3563 struct intel_encoder *encoder, 3564 const struct intel_crtc_state *old_crtc_state, 3565 const struct drm_connector_state *old_conn_state) 3566 { 3567 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3568 struct intel_connector *connector = 3569 to_intel_connector(old_conn_state->connector); 3570 3571 intel_dp->link_trained = false; 3572 3573 intel_psr_disable(intel_dp, old_crtc_state); 3574 intel_edp_backlight_off(old_conn_state); 3575 /* Disable the decompression in DP Sink */ 3576 intel_dp_sink_disable_decompression(state, 3577 connector, old_crtc_state); 3578 /* Disable Ignore_MSA bit in DP Sink */ 3579 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3580 false); 3581 } 3582 3583 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3584 struct intel_encoder *encoder, 3585 const struct intel_crtc_state *old_crtc_state, 3586 const struct drm_connector_state *old_conn_state) 3587 { 3588 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3589 struct drm_connector *connector = old_conn_state->connector; 3590 3591 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3592 false, false)) 3593 drm_dbg_kms(&i915->drm, 3594 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3595 connector->base.id, connector->name); 3596 } 3597 3598 static void intel_ddi_disable(struct intel_atomic_state *state, 3599 struct intel_encoder *encoder, 3600 const struct intel_crtc_state *old_crtc_state, 3601 const struct drm_connector_state *old_conn_state) 3602 { 3603 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3604 3605 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3606 3607 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3608 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3609 old_conn_state); 3610 else 3611 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3612 old_conn_state); 3613 } 3614 3615 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3616 struct intel_encoder *encoder, 3617 const struct intel_crtc_state *crtc_state, 3618 const struct drm_connector_state *conn_state) 3619 { 3620 intel_ddi_set_dp_msa(crtc_state, conn_state); 3621 3622 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3623 3624 intel_backlight_update(state, encoder, crtc_state, conn_state); 3625 drm_connector_update_privacy_screen(conn_state); 3626 } 3627 3628 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3629 const struct intel_crtc_state *crtc_state, 3630 const struct drm_connector_state *conn_state) 3631 { 3632 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3633 } 3634 3635 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3636 struct intel_encoder *encoder, 3637 const struct intel_crtc_state *crtc_state, 3638 const struct drm_connector_state *conn_state) 3639 { 3640 3641 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3642 !intel_encoder_is_mst(encoder)) 3643 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3644 conn_state); 3645 3646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3647 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3648 conn_state); 3649 3650 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3651 } 3652 3653 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3654 struct intel_encoder *encoder, 3655 struct intel_crtc *crtc) 3656 { 3657 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3658 const struct intel_crtc_state *crtc_state = 3659 intel_atomic_get_new_crtc_state(state, crtc); 3660 struct intel_crtc *pipe_crtc; 3661 3662 /* FIXME: Add MTL pll_mgr */ 3663 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3664 return; 3665 3666 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3667 intel_crtc_joined_pipe_mask(crtc_state)) 3668 intel_update_active_dpll(state, pipe_crtc, encoder); 3669 } 3670 3671 /* 3672 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3673 * encoder on its primary encoder. See also the comment for 3674 * intel_ddi_pre_enable(). 3675 */ 3676 static void 3677 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3678 struct intel_encoder *encoder, 3679 const struct intel_crtc_state *crtc_state, 3680 const struct drm_connector_state *conn_state) 3681 { 3682 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3683 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3684 bool is_tc_port = intel_encoder_is_tc(encoder); 3685 3686 if (is_tc_port) { 3687 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3688 3689 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3690 intel_ddi_update_active_dpll(state, encoder, crtc); 3691 } 3692 3693 main_link_aux_power_domain_get(dig_port, crtc_state); 3694 3695 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3696 /* 3697 * Program the lane count for static/dynamic connections on 3698 * Type-C ports. Skip this step for TBT. 3699 */ 3700 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3701 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3702 bxt_dpio_phy_set_lane_optim_mask(encoder, 3703 crtc_state->lane_lat_optim_mask); 3704 } 3705 3706 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3707 { 3708 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3709 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3710 int ln; 3711 3712 for (ln = 0; ln < 2; ln++) 3713 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3714 } 3715 3716 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3717 const struct intel_crtc_state *crtc_state) 3718 { 3719 struct intel_display *display = to_intel_display(crtc_state); 3720 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3721 struct intel_encoder *encoder = &dig_port->base; 3722 enum port port = encoder->port; 3723 u32 dp_tp_ctl; 3724 3725 /* 3726 * TODO: To train with only a different voltage swing entry is not 3727 * necessary disable and enable port 3728 */ 3729 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3730 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3731 mtl_disable_ddi_buf(encoder, crtc_state); 3732 3733 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3734 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3735 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3736 intel_dp_is_uhbr(crtc_state)) { 3737 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3738 } else { 3739 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3740 if (crtc_state->enhanced_framing) 3741 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3742 } 3743 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3744 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3745 3746 /* 6.f Enable D2D Link */ 3747 mtl_ddi_enable_d2d(encoder); 3748 3749 /* 6.g Configure voltage swing and related IO settings */ 3750 encoder->set_signal_levels(encoder, crtc_state); 3751 3752 /* 6.h Configure PORT_BUF_CTL1 */ 3753 mtl_port_buf_ctl_program(encoder, crtc_state); 3754 3755 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3756 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3757 if (DISPLAY_VER(display) >= 20) 3758 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3759 3760 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 3761 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3762 3763 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3764 intel_wait_ddi_buf_active(encoder); 3765 } 3766 3767 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3768 const struct intel_crtc_state *crtc_state) 3769 { 3770 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3771 struct intel_encoder *encoder = &dig_port->base; 3772 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3773 enum port port = encoder->port; 3774 u32 dp_tp_ctl, ddi_buf_ctl; 3775 bool wait = false; 3776 3777 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3778 3779 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3780 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3781 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3782 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3783 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3784 wait = true; 3785 } 3786 3787 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3788 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3789 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3790 3791 if (wait) 3792 intel_wait_ddi_buf_idle(dev_priv, port); 3793 } 3794 3795 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3796 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3797 intel_dp_is_uhbr(crtc_state)) { 3798 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3799 } else { 3800 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3801 if (crtc_state->enhanced_framing) 3802 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3803 } 3804 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3805 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3806 3807 if (IS_ALDERLAKE_P(dev_priv) && 3808 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3809 adlp_tbt_to_dp_alt_switch_wa(encoder); 3810 3811 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3812 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3813 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3814 3815 intel_wait_ddi_buf_active(encoder); 3816 } 3817 3818 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3819 const struct intel_crtc_state *crtc_state, 3820 u8 dp_train_pat) 3821 { 3822 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3823 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3824 u32 temp; 3825 3826 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3827 3828 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3829 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3830 case DP_TRAINING_PATTERN_DISABLE: 3831 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3832 break; 3833 case DP_TRAINING_PATTERN_1: 3834 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3835 break; 3836 case DP_TRAINING_PATTERN_2: 3837 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3838 break; 3839 case DP_TRAINING_PATTERN_3: 3840 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3841 break; 3842 case DP_TRAINING_PATTERN_4: 3843 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3844 break; 3845 } 3846 3847 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3848 } 3849 3850 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3851 const struct intel_crtc_state *crtc_state) 3852 { 3853 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3854 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3855 enum port port = encoder->port; 3856 3857 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3858 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3859 3860 /* 3861 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3862 * reason we need to set idle transmission mode is to work around a HW 3863 * issue where we enable the pipe while not in idle link-training mode. 3864 * In this case there is requirement to wait for a minimum number of 3865 * idle patterns to be sent. 3866 */ 3867 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3868 return; 3869 3870 if (intel_de_wait_for_set(dev_priv, 3871 dp_tp_status_reg(encoder, crtc_state), 3872 DP_TP_STATUS_IDLE_DONE, 2)) 3873 drm_err(&dev_priv->drm, 3874 "Timed out waiting for DP idle patterns\n"); 3875 } 3876 3877 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3878 enum transcoder cpu_transcoder) 3879 { 3880 if (cpu_transcoder == TRANSCODER_EDP) 3881 return false; 3882 3883 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3884 return false; 3885 3886 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3887 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3888 } 3889 3890 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3891 { 3892 if (crtc_state->port_clock > 594000) 3893 return 2; 3894 else 3895 return 0; 3896 } 3897 3898 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3899 { 3900 if (crtc_state->port_clock > 594000) 3901 return 3; 3902 else 3903 return 0; 3904 } 3905 3906 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3907 { 3908 if (crtc_state->port_clock > 594000) 3909 return 1; 3910 else 3911 return 0; 3912 } 3913 3914 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3915 { 3916 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3917 3918 if (DISPLAY_VER(dev_priv) >= 14) 3919 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3920 else if (DISPLAY_VER(dev_priv) >= 12) 3921 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3922 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3923 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3924 else if (DISPLAY_VER(dev_priv) >= 11) 3925 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3926 } 3927 3928 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3929 enum transcoder cpu_transcoder) 3930 { 3931 u32 master_select; 3932 3933 if (DISPLAY_VER(dev_priv) >= 11) { 3934 u32 ctl2 = intel_de_read(dev_priv, 3935 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3936 3937 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3938 return INVALID_TRANSCODER; 3939 3940 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3941 } else { 3942 u32 ctl = intel_de_read(dev_priv, 3943 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3944 3945 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3946 return INVALID_TRANSCODER; 3947 3948 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3949 } 3950 3951 if (master_select == 0) 3952 return TRANSCODER_EDP; 3953 else 3954 return master_select - 1; 3955 } 3956 3957 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3958 { 3959 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3960 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3961 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3962 enum transcoder cpu_transcoder; 3963 3964 crtc_state->master_transcoder = 3965 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3966 3967 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3968 enum intel_display_power_domain power_domain; 3969 intel_wakeref_t trans_wakeref; 3970 3971 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3972 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3973 power_domain); 3974 3975 if (!trans_wakeref) 3976 continue; 3977 3978 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3979 crtc_state->cpu_transcoder) 3980 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3981 3982 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3983 } 3984 3985 drm_WARN_ON(&dev_priv->drm, 3986 crtc_state->master_transcoder != INVALID_TRANSCODER && 3987 crtc_state->sync_mode_slaves_mask); 3988 } 3989 3990 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3991 struct intel_crtc_state *crtc_state, 3992 u32 ddi_func_ctl) 3993 { 3994 struct intel_display *display = to_intel_display(encoder); 3995 3996 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3997 if (DISPLAY_VER(display) >= 14) 3998 crtc_state->lane_count = 3999 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4000 else 4001 crtc_state->lane_count = 4; 4002 } 4003 4004 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4005 struct intel_crtc_state *crtc_state, 4006 u32 ddi_func_ctl) 4007 { 4008 crtc_state->has_hdmi_sink = true; 4009 4010 crtc_state->infoframes.enable |= 4011 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4012 4013 if (crtc_state->infoframes.enable) 4014 crtc_state->has_infoframe = true; 4015 4016 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4017 crtc_state->hdmi_scrambling = true; 4018 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4019 crtc_state->hdmi_high_tmds_clock_ratio = true; 4020 4021 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4022 } 4023 4024 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4025 struct intel_crtc_state *crtc_state, 4026 u32 ddi_func_ctl) 4027 { 4028 struct intel_display *display = to_intel_display(encoder); 4029 4030 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4031 crtc_state->enhanced_framing = 4032 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4033 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4034 } 4035 4036 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4037 struct intel_crtc_state *crtc_state, 4038 u32 ddi_func_ctl) 4039 { 4040 struct intel_display *display = to_intel_display(encoder); 4041 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4042 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4043 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4044 4045 if (encoder->type == INTEL_OUTPUT_EDP) 4046 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4047 else 4048 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4049 crtc_state->lane_count = 4050 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4051 4052 if (DISPLAY_VER(display) >= 12 && 4053 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4054 crtc_state->mst_master_transcoder = 4055 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4056 4057 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4058 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4059 4060 crtc_state->enhanced_framing = 4061 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4062 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4063 4064 if (DISPLAY_VER(display) >= 11) 4065 crtc_state->fec_enable = 4066 intel_de_read(display, 4067 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4068 4069 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 4070 crtc_state->infoframes.enable |= 4071 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4072 else 4073 crtc_state->infoframes.enable |= 4074 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4075 } 4076 4077 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4078 struct intel_crtc_state *crtc_state, 4079 u32 ddi_func_ctl) 4080 { 4081 struct intel_display *display = to_intel_display(encoder); 4082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4083 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4084 4085 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4086 crtc_state->lane_count = 4087 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4088 4089 if (DISPLAY_VER(display) >= 12) 4090 crtc_state->mst_master_transcoder = 4091 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4092 4093 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4094 4095 if (DISPLAY_VER(display) >= 11) 4096 crtc_state->fec_enable = 4097 intel_de_read(display, 4098 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4099 4100 crtc_state->infoframes.enable |= 4101 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4102 } 4103 4104 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4105 struct intel_crtc_state *pipe_config) 4106 { 4107 struct intel_display *display = to_intel_display(encoder); 4108 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4109 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4110 u32 ddi_func_ctl, ddi_mode, flags = 0; 4111 4112 ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 4113 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4114 flags |= DRM_MODE_FLAG_PHSYNC; 4115 else 4116 flags |= DRM_MODE_FLAG_NHSYNC; 4117 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4118 flags |= DRM_MODE_FLAG_PVSYNC; 4119 else 4120 flags |= DRM_MODE_FLAG_NVSYNC; 4121 4122 pipe_config->hw.adjusted_mode.flags |= flags; 4123 4124 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4125 case TRANS_DDI_BPC_6: 4126 pipe_config->pipe_bpp = 18; 4127 break; 4128 case TRANS_DDI_BPC_8: 4129 pipe_config->pipe_bpp = 24; 4130 break; 4131 case TRANS_DDI_BPC_10: 4132 pipe_config->pipe_bpp = 30; 4133 break; 4134 case TRANS_DDI_BPC_12: 4135 pipe_config->pipe_bpp = 36; 4136 break; 4137 default: 4138 break; 4139 } 4140 4141 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4142 4143 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4144 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4145 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4146 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4147 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4148 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4150 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4152 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4153 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4154 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4155 4156 /* 4157 * If this is true, we know we're being called from mst stream 4158 * encoder's ->get_config(). 4159 */ 4160 if (intel_dp->is_mst) 4161 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4162 else 4163 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4164 } 4165 } 4166 4167 /* 4168 * Note: Also called from the ->get_config of the MST stream encoders on their 4169 * primary encoder, via the platform specific hooks here. See also the comment 4170 * for intel_ddi_pre_enable(). 4171 */ 4172 static void intel_ddi_get_config(struct intel_encoder *encoder, 4173 struct intel_crtc_state *pipe_config) 4174 { 4175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4176 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4177 4178 /* XXX: DSI transcoder paranoia */ 4179 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4180 return; 4181 4182 intel_ddi_read_func_ctl(encoder, pipe_config); 4183 4184 intel_ddi_mso_get_config(encoder, pipe_config); 4185 4186 pipe_config->has_audio = 4187 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4188 4189 if (encoder->type == INTEL_OUTPUT_EDP) 4190 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4191 4192 ddi_dotclock_get(pipe_config); 4193 4194 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4195 pipe_config->lane_lat_optim_mask = 4196 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4197 4198 intel_ddi_compute_min_voltage_level(pipe_config); 4199 4200 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4201 4202 intel_read_infoframe(encoder, pipe_config, 4203 HDMI_INFOFRAME_TYPE_AVI, 4204 &pipe_config->infoframes.avi); 4205 intel_read_infoframe(encoder, pipe_config, 4206 HDMI_INFOFRAME_TYPE_SPD, 4207 &pipe_config->infoframes.spd); 4208 intel_read_infoframe(encoder, pipe_config, 4209 HDMI_INFOFRAME_TYPE_VENDOR, 4210 &pipe_config->infoframes.hdmi); 4211 intel_read_infoframe(encoder, pipe_config, 4212 HDMI_INFOFRAME_TYPE_DRM, 4213 &pipe_config->infoframes.drm); 4214 4215 if (DISPLAY_VER(dev_priv) >= 8) 4216 bdw_get_trans_port_sync_config(pipe_config); 4217 4218 intel_psr_get_config(encoder, pipe_config); 4219 4220 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4221 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4222 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4223 4224 intel_audio_codec_get_config(encoder, pipe_config); 4225 } 4226 4227 void intel_ddi_get_clock(struct intel_encoder *encoder, 4228 struct intel_crtc_state *crtc_state, 4229 struct intel_shared_dpll *pll) 4230 { 4231 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4232 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4233 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4234 bool pll_active; 4235 4236 if (drm_WARN_ON(&i915->drm, !pll)) 4237 return; 4238 4239 port_dpll->pll = pll; 4240 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4241 drm_WARN_ON(&i915->drm, !pll_active); 4242 4243 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4244 4245 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4246 &crtc_state->dpll_hw_state); 4247 } 4248 4249 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4250 struct intel_crtc_state *crtc_state) 4251 { 4252 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4253 4254 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4255 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4256 else 4257 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4258 4259 intel_ddi_get_config(encoder, crtc_state); 4260 } 4261 4262 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4263 struct intel_crtc_state *crtc_state) 4264 { 4265 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4266 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4267 4268 intel_ddi_get_config(encoder, crtc_state); 4269 } 4270 4271 static void adls_ddi_get_config(struct intel_encoder *encoder, 4272 struct intel_crtc_state *crtc_state) 4273 { 4274 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4275 intel_ddi_get_config(encoder, crtc_state); 4276 } 4277 4278 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4279 struct intel_crtc_state *crtc_state) 4280 { 4281 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4282 intel_ddi_get_config(encoder, crtc_state); 4283 } 4284 4285 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4286 struct intel_crtc_state *crtc_state) 4287 { 4288 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4289 intel_ddi_get_config(encoder, crtc_state); 4290 } 4291 4292 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4293 struct intel_crtc_state *crtc_state) 4294 { 4295 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4296 intel_ddi_get_config(encoder, crtc_state); 4297 } 4298 4299 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4300 { 4301 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4302 } 4303 4304 static enum icl_port_dpll_id 4305 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4306 const struct intel_crtc_state *crtc_state) 4307 { 4308 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4309 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4310 4311 if (drm_WARN_ON(&i915->drm, !pll)) 4312 return ICL_PORT_DPLL_DEFAULT; 4313 4314 if (icl_ddi_tc_pll_is_tbt(pll)) 4315 return ICL_PORT_DPLL_DEFAULT; 4316 else 4317 return ICL_PORT_DPLL_MG_PHY; 4318 } 4319 4320 enum icl_port_dpll_id 4321 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4322 const struct intel_crtc_state *crtc_state) 4323 { 4324 if (!encoder->port_pll_type) 4325 return ICL_PORT_DPLL_DEFAULT; 4326 4327 return encoder->port_pll_type(encoder, crtc_state); 4328 } 4329 4330 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4331 struct intel_crtc_state *crtc_state, 4332 struct intel_shared_dpll *pll) 4333 { 4334 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4335 enum icl_port_dpll_id port_dpll_id; 4336 struct icl_port_dpll *port_dpll; 4337 bool pll_active; 4338 4339 if (drm_WARN_ON(&i915->drm, !pll)) 4340 return; 4341 4342 if (icl_ddi_tc_pll_is_tbt(pll)) 4343 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4344 else 4345 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4346 4347 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4348 4349 port_dpll->pll = pll; 4350 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4351 drm_WARN_ON(&i915->drm, !pll_active); 4352 4353 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4354 4355 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4356 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4357 else 4358 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4359 &crtc_state->dpll_hw_state); 4360 } 4361 4362 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4363 struct intel_crtc_state *crtc_state) 4364 { 4365 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4366 intel_ddi_get_config(encoder, crtc_state); 4367 } 4368 4369 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4370 struct intel_crtc_state *crtc_state) 4371 { 4372 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4373 intel_ddi_get_config(encoder, crtc_state); 4374 } 4375 4376 static void skl_ddi_get_config(struct intel_encoder *encoder, 4377 struct intel_crtc_state *crtc_state) 4378 { 4379 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4380 intel_ddi_get_config(encoder, crtc_state); 4381 } 4382 4383 void hsw_ddi_get_config(struct intel_encoder *encoder, 4384 struct intel_crtc_state *crtc_state) 4385 { 4386 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4387 intel_ddi_get_config(encoder, crtc_state); 4388 } 4389 4390 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4391 const struct intel_crtc_state *crtc_state) 4392 { 4393 if (intel_encoder_is_tc(encoder)) 4394 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4395 crtc_state); 4396 4397 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4398 (!crtc_state && intel_encoder_is_dp(encoder))) 4399 intel_dp_sync_state(encoder, crtc_state); 4400 } 4401 4402 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4403 struct intel_crtc_state *crtc_state) 4404 { 4405 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4406 bool fastset = true; 4407 4408 if (intel_encoder_is_tc(encoder)) { 4409 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4410 encoder->base.base.id, encoder->base.name); 4411 crtc_state->uapi.mode_changed = true; 4412 fastset = false; 4413 } 4414 4415 if (intel_crtc_has_dp_encoder(crtc_state) && 4416 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4417 fastset = false; 4418 4419 return fastset; 4420 } 4421 4422 static enum intel_output_type 4423 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4424 struct intel_crtc_state *crtc_state, 4425 struct drm_connector_state *conn_state) 4426 { 4427 switch (conn_state->connector->connector_type) { 4428 case DRM_MODE_CONNECTOR_HDMIA: 4429 return INTEL_OUTPUT_HDMI; 4430 case DRM_MODE_CONNECTOR_eDP: 4431 return INTEL_OUTPUT_EDP; 4432 case DRM_MODE_CONNECTOR_DisplayPort: 4433 return INTEL_OUTPUT_DP; 4434 default: 4435 MISSING_CASE(conn_state->connector->connector_type); 4436 return INTEL_OUTPUT_UNUSED; 4437 } 4438 } 4439 4440 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4441 struct intel_crtc_state *pipe_config, 4442 struct drm_connector_state *conn_state) 4443 { 4444 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4445 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4446 enum port port = encoder->port; 4447 int ret; 4448 4449 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4450 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4451 4452 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4453 pipe_config->has_hdmi_sink = 4454 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4455 4456 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4457 } else { 4458 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4459 } 4460 4461 if (ret) 4462 return ret; 4463 4464 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4465 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4466 pipe_config->pch_pfit.force_thru = 4467 pipe_config->pch_pfit.enabled || 4468 pipe_config->crc_enabled; 4469 4470 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4471 pipe_config->lane_lat_optim_mask = 4472 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4473 4474 intel_ddi_compute_min_voltage_level(pipe_config); 4475 4476 return 0; 4477 } 4478 4479 static bool mode_equal(const struct drm_display_mode *mode1, 4480 const struct drm_display_mode *mode2) 4481 { 4482 return drm_mode_match(mode1, mode2, 4483 DRM_MODE_MATCH_TIMINGS | 4484 DRM_MODE_MATCH_FLAGS | 4485 DRM_MODE_MATCH_3D_FLAGS) && 4486 mode1->clock == mode2->clock; /* we want an exact match */ 4487 } 4488 4489 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4490 const struct intel_link_m_n *m_n_2) 4491 { 4492 return m_n_1->tu == m_n_2->tu && 4493 m_n_1->data_m == m_n_2->data_m && 4494 m_n_1->data_n == m_n_2->data_n && 4495 m_n_1->link_m == m_n_2->link_m && 4496 m_n_1->link_n == m_n_2->link_n; 4497 } 4498 4499 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4500 const struct intel_crtc_state *crtc_state2) 4501 { 4502 /* 4503 * FIXME the modeset sequence is currently wrong and 4504 * can't deal with joiner + port sync at the same time. 4505 */ 4506 return crtc_state1->hw.active && crtc_state2->hw.active && 4507 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4508 crtc_state1->output_types == crtc_state2->output_types && 4509 crtc_state1->output_format == crtc_state2->output_format && 4510 crtc_state1->lane_count == crtc_state2->lane_count && 4511 crtc_state1->port_clock == crtc_state2->port_clock && 4512 mode_equal(&crtc_state1->hw.adjusted_mode, 4513 &crtc_state2->hw.adjusted_mode) && 4514 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4515 } 4516 4517 static u8 4518 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4519 int tile_group_id) 4520 { 4521 struct drm_connector *connector; 4522 const struct drm_connector_state *conn_state; 4523 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4524 struct intel_atomic_state *state = 4525 to_intel_atomic_state(ref_crtc_state->uapi.state); 4526 u8 transcoders = 0; 4527 int i; 4528 4529 /* 4530 * We don't enable port sync on BDW due to missing w/as and 4531 * due to not having adjusted the modeset sequence appropriately. 4532 */ 4533 if (DISPLAY_VER(dev_priv) < 9) 4534 return 0; 4535 4536 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4537 return 0; 4538 4539 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4540 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4541 const struct intel_crtc_state *crtc_state; 4542 4543 if (!crtc) 4544 continue; 4545 4546 if (!connector->has_tile || 4547 connector->tile_group->id != 4548 tile_group_id) 4549 continue; 4550 crtc_state = intel_atomic_get_new_crtc_state(state, 4551 crtc); 4552 if (!crtcs_port_sync_compatible(ref_crtc_state, 4553 crtc_state)) 4554 continue; 4555 transcoders |= BIT(crtc_state->cpu_transcoder); 4556 } 4557 4558 return transcoders; 4559 } 4560 4561 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4562 struct intel_crtc_state *crtc_state, 4563 struct drm_connector_state *conn_state) 4564 { 4565 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4566 struct drm_connector *connector = conn_state->connector; 4567 u8 port_sync_transcoders = 0; 4568 4569 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4570 encoder->base.base.id, encoder->base.name, 4571 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4572 4573 if (connector->has_tile) 4574 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4575 connector->tile_group->id); 4576 4577 /* 4578 * EDP Transcoders cannot be ensalved 4579 * make them a master always when present 4580 */ 4581 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4582 crtc_state->master_transcoder = TRANSCODER_EDP; 4583 else 4584 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4585 4586 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4587 crtc_state->master_transcoder = INVALID_TRANSCODER; 4588 crtc_state->sync_mode_slaves_mask = 4589 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4590 } 4591 4592 return 0; 4593 } 4594 4595 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4596 { 4597 struct drm_i915_private *i915 = to_i915(encoder->dev); 4598 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4599 4600 intel_dp_encoder_flush_work(encoder); 4601 if (intel_encoder_is_tc(&dig_port->base)) 4602 intel_tc_port_cleanup(dig_port); 4603 intel_display_power_flush_work(i915); 4604 4605 drm_encoder_cleanup(encoder); 4606 kfree(dig_port->hdcp_port_data.streams); 4607 kfree(dig_port); 4608 } 4609 4610 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4611 { 4612 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4613 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4614 4615 intel_dp->reset_link_params = true; 4616 intel_dp_invalidate_source_oui(intel_dp); 4617 4618 intel_pps_encoder_reset(intel_dp); 4619 4620 if (intel_encoder_is_tc(&dig_port->base)) 4621 intel_tc_port_init_mode(dig_port); 4622 } 4623 4624 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4625 { 4626 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4627 4628 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4629 4630 return 0; 4631 } 4632 4633 static const struct drm_encoder_funcs intel_ddi_funcs = { 4634 .reset = intel_ddi_encoder_reset, 4635 .destroy = intel_ddi_encoder_destroy, 4636 .late_register = intel_ddi_encoder_late_register, 4637 }; 4638 4639 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4640 { 4641 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4642 struct intel_connector *connector; 4643 enum port port = dig_port->base.port; 4644 4645 connector = intel_connector_alloc(); 4646 if (!connector) 4647 return -ENOMEM; 4648 4649 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4650 if (DISPLAY_VER(i915) >= 14) 4651 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4652 else 4653 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4654 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4655 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4656 4657 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4658 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4659 4660 if (!intel_dp_init_connector(dig_port, connector)) { 4661 kfree(connector); 4662 return -EINVAL; 4663 } 4664 4665 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4666 struct drm_device *dev = dig_port->base.base.dev; 4667 struct drm_privacy_screen *privacy_screen; 4668 4669 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4670 if (!IS_ERR(privacy_screen)) { 4671 drm_connector_attach_privacy_screen_provider(&connector->base, 4672 privacy_screen); 4673 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4674 drm_warn(dev, "Error getting privacy-screen\n"); 4675 } 4676 } 4677 4678 return 0; 4679 } 4680 4681 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4682 struct drm_modeset_acquire_ctx *ctx) 4683 { 4684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4685 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4686 struct intel_connector *connector = hdmi->attached_connector; 4687 struct i2c_adapter *ddc = connector->base.ddc; 4688 struct drm_connector_state *conn_state; 4689 struct intel_crtc_state *crtc_state; 4690 struct intel_crtc *crtc; 4691 u8 config; 4692 int ret; 4693 4694 if (connector->base.status != connector_status_connected) 4695 return 0; 4696 4697 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4698 ctx); 4699 if (ret) 4700 return ret; 4701 4702 conn_state = connector->base.state; 4703 4704 crtc = to_intel_crtc(conn_state->crtc); 4705 if (!crtc) 4706 return 0; 4707 4708 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4709 if (ret) 4710 return ret; 4711 4712 crtc_state = to_intel_crtc_state(crtc->base.state); 4713 4714 drm_WARN_ON(&dev_priv->drm, 4715 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4716 4717 if (!crtc_state->hw.active) 4718 return 0; 4719 4720 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4721 !crtc_state->hdmi_scrambling) 4722 return 0; 4723 4724 if (conn_state->commit && 4725 !try_wait_for_completion(&conn_state->commit->hw_done)) 4726 return 0; 4727 4728 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4729 if (ret < 0) { 4730 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4731 connector->base.base.id, connector->base.name, ret); 4732 return 0; 4733 } 4734 4735 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4736 crtc_state->hdmi_high_tmds_clock_ratio && 4737 !!(config & SCDC_SCRAMBLING_ENABLE) == 4738 crtc_state->hdmi_scrambling) 4739 return 0; 4740 4741 /* 4742 * HDMI 2.0 says that one should not send scrambled data 4743 * prior to configuring the sink scrambling, and that 4744 * TMDS clock/data transmission should be suspended when 4745 * changing the TMDS clock rate in the sink. So let's 4746 * just do a full modeset here, even though some sinks 4747 * would be perfectly happy if were to just reconfigure 4748 * the SCDC settings on the fly. 4749 */ 4750 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4751 } 4752 4753 static void intel_ddi_link_check(struct intel_encoder *encoder) 4754 { 4755 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4756 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4757 4758 /* TODO: Move checking the HDMI link state here as well. */ 4759 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4760 4761 intel_dp_link_check(encoder); 4762 } 4763 4764 static enum intel_hotplug_state 4765 intel_ddi_hotplug(struct intel_encoder *encoder, 4766 struct intel_connector *connector) 4767 { 4768 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4769 struct intel_dp *intel_dp = &dig_port->dp; 4770 bool is_tc = intel_encoder_is_tc(encoder); 4771 struct drm_modeset_acquire_ctx ctx; 4772 enum intel_hotplug_state state; 4773 int ret; 4774 4775 if (intel_dp_test_phy(intel_dp)) 4776 return INTEL_HOTPLUG_UNCHANGED; 4777 4778 state = intel_encoder_hotplug(encoder, connector); 4779 4780 if (!intel_tc_port_link_reset(dig_port)) { 4781 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4782 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4783 ret = intel_hdmi_reset_link(encoder, &ctx); 4784 drm_WARN_ON(encoder->base.dev, ret); 4785 } else { 4786 intel_dp_check_link_state(intel_dp); 4787 } 4788 } 4789 4790 /* 4791 * Unpowered type-c dongles can take some time to boot and be 4792 * responsible, so here giving some time to those dongles to power up 4793 * and then retrying the probe. 4794 * 4795 * On many platforms the HDMI live state signal is known to be 4796 * unreliable, so we can't use it to detect if a sink is connected or 4797 * not. Instead we detect if it's connected based on whether we can 4798 * read the EDID or not. That in turn has a problem during disconnect, 4799 * since the HPD interrupt may be raised before the DDC lines get 4800 * disconnected (due to how the required length of DDC vs. HPD 4801 * connector pins are specified) and so we'll still be able to get a 4802 * valid EDID. To solve this schedule another detection cycle if this 4803 * time around we didn't detect any change in the sink's connection 4804 * status. 4805 * 4806 * Type-c connectors which get their HPD signal deasserted then 4807 * reasserted, without unplugging/replugging the sink from the 4808 * connector, introduce a delay until the AUX channel communication 4809 * becomes functional. Retry the detection for 5 seconds on type-c 4810 * connectors to account for this delay. 4811 */ 4812 if (state == INTEL_HOTPLUG_UNCHANGED && 4813 connector->hotplug_retries < (is_tc ? 5 : 1) && 4814 !dig_port->dp.is_mst) 4815 state = INTEL_HOTPLUG_RETRY; 4816 4817 return state; 4818 } 4819 4820 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4821 { 4822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4823 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4824 4825 return intel_de_read(dev_priv, SDEISR) & bit; 4826 } 4827 4828 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4829 { 4830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4831 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4832 4833 return intel_de_read(dev_priv, DEISR) & bit; 4834 } 4835 4836 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4837 { 4838 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4839 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4840 4841 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4842 } 4843 4844 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4845 { 4846 struct intel_connector *connector; 4847 enum port port = dig_port->base.port; 4848 4849 connector = intel_connector_alloc(); 4850 if (!connector) 4851 return -ENOMEM; 4852 4853 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4854 4855 if (!intel_hdmi_init_connector(dig_port, connector)) { 4856 /* 4857 * HDMI connector init failures may just mean conflicting DDC 4858 * pins or not having enough lanes. Handle them gracefully, but 4859 * don't fail the entire DDI init. 4860 */ 4861 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4862 kfree(connector); 4863 } 4864 4865 return 0; 4866 } 4867 4868 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4869 { 4870 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4871 4872 if (dig_port->base.port != PORT_A) 4873 return false; 4874 4875 if (dig_port->ddi_a_4_lanes) 4876 return false; 4877 4878 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4879 * supported configuration 4880 */ 4881 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4882 return true; 4883 4884 return false; 4885 } 4886 4887 static int 4888 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4889 { 4890 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4891 enum port port = dig_port->base.port; 4892 int max_lanes = 4; 4893 4894 if (DISPLAY_VER(dev_priv) >= 11) 4895 return max_lanes; 4896 4897 if (port == PORT_A || port == PORT_E) { 4898 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4899 max_lanes = port == PORT_A ? 4 : 0; 4900 else 4901 /* Both A and E share 2 lanes */ 4902 max_lanes = 2; 4903 } 4904 4905 /* 4906 * Some BIOS might fail to set this bit on port A if eDP 4907 * wasn't lit up at boot. Force this bit set when needed 4908 * so we use the proper lane count for our calculations. 4909 */ 4910 if (intel_ddi_a_force_4_lanes(dig_port)) { 4911 drm_dbg_kms(&dev_priv->drm, 4912 "Forcing DDI_A_4_LANES for port A\n"); 4913 dig_port->ddi_a_4_lanes = true; 4914 max_lanes = 4; 4915 } 4916 4917 return max_lanes; 4918 } 4919 4920 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4921 enum port port) 4922 { 4923 if (port >= PORT_D_XELPD) 4924 return HPD_PORT_D + port - PORT_D_XELPD; 4925 else if (port >= PORT_TC1) 4926 return HPD_PORT_TC1 + port - PORT_TC1; 4927 else 4928 return HPD_PORT_A + port - PORT_A; 4929 } 4930 4931 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4932 enum port port) 4933 { 4934 if (port >= PORT_TC1) 4935 return HPD_PORT_C + port - PORT_TC1; 4936 else 4937 return HPD_PORT_A + port - PORT_A; 4938 } 4939 4940 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4941 enum port port) 4942 { 4943 if (port >= PORT_TC1) 4944 return HPD_PORT_TC1 + port - PORT_TC1; 4945 else 4946 return HPD_PORT_A + port - PORT_A; 4947 } 4948 4949 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4950 enum port port) 4951 { 4952 if (HAS_PCH_TGP(dev_priv)) 4953 return tgl_hpd_pin(dev_priv, port); 4954 4955 if (port >= PORT_TC1) 4956 return HPD_PORT_C + port - PORT_TC1; 4957 else 4958 return HPD_PORT_A + port - PORT_A; 4959 } 4960 4961 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4962 enum port port) 4963 { 4964 if (port >= PORT_C) 4965 return HPD_PORT_TC1 + port - PORT_C; 4966 else 4967 return HPD_PORT_A + port - PORT_A; 4968 } 4969 4970 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4971 enum port port) 4972 { 4973 if (port == PORT_D) 4974 return HPD_PORT_A; 4975 4976 if (HAS_PCH_TGP(dev_priv)) 4977 return icl_hpd_pin(dev_priv, port); 4978 4979 return HPD_PORT_A + port - PORT_A; 4980 } 4981 4982 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4983 { 4984 if (HAS_PCH_TGP(dev_priv)) 4985 return icl_hpd_pin(dev_priv, port); 4986 4987 return HPD_PORT_A + port - PORT_A; 4988 } 4989 4990 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4991 { 4992 if (DISPLAY_VER(i915) >= 12) 4993 return port >= PORT_TC1; 4994 else if (DISPLAY_VER(i915) >= 11) 4995 return port >= PORT_C; 4996 else 4997 return false; 4998 } 4999 5000 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5001 { 5002 intel_dp_encoder_suspend(encoder); 5003 } 5004 5005 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5006 { 5007 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5008 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5009 5010 /* 5011 * TODO: Move this to intel_dp_encoder_suspend(), 5012 * once modeset locking around that is removed. 5013 */ 5014 intel_encoder_link_check_flush_work(encoder); 5015 intel_tc_port_suspend(dig_port); 5016 } 5017 5018 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5019 { 5020 if (intel_encoder_is_dp(encoder)) 5021 intel_dp_encoder_shutdown(encoder); 5022 if (intel_encoder_is_hdmi(encoder)) 5023 intel_hdmi_encoder_shutdown(encoder); 5024 } 5025 5026 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5027 { 5028 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5029 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5030 5031 intel_tc_port_cleanup(dig_port); 5032 } 5033 5034 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5035 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5036 5037 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 5038 { 5039 /* straps not used on skl+ */ 5040 if (DISPLAY_VER(i915) >= 9) 5041 return true; 5042 5043 switch (port) { 5044 case PORT_A: 5045 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5046 case PORT_B: 5047 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5048 case PORT_C: 5049 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5050 case PORT_D: 5051 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5052 case PORT_E: 5053 return true; /* no strap for DDI-E */ 5054 default: 5055 MISSING_CASE(port); 5056 return false; 5057 } 5058 } 5059 5060 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5061 { 5062 return init_dp || intel_encoder_is_tc(encoder); 5063 } 5064 5065 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 5066 { 5067 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 5068 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 5069 "Platform does not support DSI\n"); 5070 } 5071 5072 static bool port_in_use(struct drm_i915_private *i915, enum port port) 5073 { 5074 struct intel_encoder *encoder; 5075 5076 for_each_intel_encoder(&i915->drm, encoder) { 5077 /* FIXME what about second port for dual link DSI? */ 5078 if (encoder->port == port) 5079 return true; 5080 } 5081 5082 return false; 5083 } 5084 5085 void intel_ddi_init(struct intel_display *display, 5086 const struct intel_bios_encoder_data *devdata) 5087 { 5088 struct drm_i915_private *dev_priv = to_i915(display->drm); 5089 struct intel_digital_port *dig_port; 5090 struct intel_encoder *encoder; 5091 bool init_hdmi, init_dp; 5092 enum port port; 5093 enum phy phy; 5094 u32 ddi_buf_ctl; 5095 5096 port = intel_bios_encoder_port(devdata); 5097 if (port == PORT_NONE) 5098 return; 5099 5100 if (!port_strap_detected(dev_priv, port)) { 5101 drm_dbg_kms(&dev_priv->drm, 5102 "Port %c strap not detected\n", port_name(port)); 5103 return; 5104 } 5105 5106 if (!assert_port_valid(dev_priv, port)) 5107 return; 5108 5109 if (port_in_use(dev_priv, port)) { 5110 drm_dbg_kms(&dev_priv->drm, 5111 "Port %c already claimed\n", port_name(port)); 5112 return; 5113 } 5114 5115 if (intel_bios_encoder_supports_dsi(devdata)) { 5116 /* BXT/GLK handled elsewhere, for now at least */ 5117 if (!assert_has_icl_dsi(dev_priv)) 5118 return; 5119 5120 icl_dsi_init(display, devdata); 5121 return; 5122 } 5123 5124 phy = intel_port_to_phy(dev_priv, port); 5125 5126 /* 5127 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5128 * have taken over some of the PHYs and made them unavailable to the 5129 * driver. In that case we should skip initializing the corresponding 5130 * outputs. 5131 */ 5132 if (intel_hti_uses_phy(display, phy)) { 5133 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5134 port_name(port), phy_name(phy)); 5135 return; 5136 } 5137 5138 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5139 intel_bios_encoder_supports_hdmi(devdata); 5140 init_dp = intel_bios_encoder_supports_dp(devdata); 5141 5142 if (intel_bios_encoder_is_lspcon(devdata)) { 5143 /* 5144 * Lspcon device needs to be driven with DP connector 5145 * with special detection sequence. So make sure DP 5146 * is initialized before lspcon. 5147 */ 5148 init_dp = true; 5149 init_hdmi = false; 5150 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5151 port_name(port)); 5152 } 5153 5154 if (!init_dp && !init_hdmi) { 5155 drm_dbg_kms(&dev_priv->drm, 5156 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5157 port_name(port)); 5158 return; 5159 } 5160 5161 if (intel_phy_is_snps(dev_priv, phy) && 5162 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 5163 drm_dbg_kms(&dev_priv->drm, 5164 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5165 phy_name(phy)); 5166 } 5167 5168 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5169 if (!dig_port) 5170 return; 5171 5172 dig_port->aux_ch = AUX_CH_NONE; 5173 5174 encoder = &dig_port->base; 5175 encoder->devdata = devdata; 5176 5177 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 5178 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5179 DRM_MODE_ENCODER_TMDS, 5180 "DDI %c/PHY %c", 5181 port_name(port - PORT_D_XELPD + PORT_D), 5182 phy_name(phy)); 5183 } else if (DISPLAY_VER(dev_priv) >= 12) { 5184 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5185 5186 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5187 DRM_MODE_ENCODER_TMDS, 5188 "DDI %s%c/PHY %s%c", 5189 port >= PORT_TC1 ? "TC" : "", 5190 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5191 tc_port != TC_PORT_NONE ? "TC" : "", 5192 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5193 } else if (DISPLAY_VER(dev_priv) >= 11) { 5194 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5195 5196 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5197 DRM_MODE_ENCODER_TMDS, 5198 "DDI %c%s/PHY %s%c", 5199 port_name(port), 5200 port >= PORT_C ? " (TC)" : "", 5201 tc_port != TC_PORT_NONE ? "TC" : "", 5202 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5203 } else { 5204 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5205 DRM_MODE_ENCODER_TMDS, 5206 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5207 } 5208 5209 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5210 5211 mutex_init(&dig_port->hdcp_mutex); 5212 dig_port->num_hdcp_streams = 0; 5213 5214 encoder->hotplug = intel_ddi_hotplug; 5215 encoder->compute_output_type = intel_ddi_compute_output_type; 5216 encoder->compute_config = intel_ddi_compute_config; 5217 encoder->compute_config_late = intel_ddi_compute_config_late; 5218 encoder->enable = intel_ddi_enable; 5219 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5220 encoder->pre_enable = intel_ddi_pre_enable; 5221 encoder->disable = intel_ddi_disable; 5222 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5223 encoder->post_disable = intel_ddi_post_disable; 5224 encoder->update_pipe = intel_ddi_update_pipe; 5225 encoder->audio_enable = intel_audio_codec_enable; 5226 encoder->audio_disable = intel_audio_codec_disable; 5227 encoder->get_hw_state = intel_ddi_get_hw_state; 5228 encoder->sync_state = intel_ddi_sync_state; 5229 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5230 encoder->suspend = intel_ddi_encoder_suspend; 5231 encoder->shutdown = intel_ddi_encoder_shutdown; 5232 encoder->get_power_domains = intel_ddi_get_power_domains; 5233 5234 encoder->type = INTEL_OUTPUT_DDI; 5235 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5236 encoder->port = port; 5237 encoder->cloneable = 0; 5238 encoder->pipe_mask = ~0; 5239 5240 if (DISPLAY_VER(dev_priv) >= 14) { 5241 encoder->enable_clock = intel_mtl_pll_enable; 5242 encoder->disable_clock = intel_mtl_pll_disable; 5243 encoder->port_pll_type = intel_mtl_port_pll_type; 5244 encoder->get_config = mtl_ddi_get_config; 5245 } else if (IS_DG2(dev_priv)) { 5246 encoder->enable_clock = intel_mpllb_enable; 5247 encoder->disable_clock = intel_mpllb_disable; 5248 encoder->get_config = dg2_ddi_get_config; 5249 } else if (IS_ALDERLAKE_S(dev_priv)) { 5250 encoder->enable_clock = adls_ddi_enable_clock; 5251 encoder->disable_clock = adls_ddi_disable_clock; 5252 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5253 encoder->get_config = adls_ddi_get_config; 5254 } else if (IS_ROCKETLAKE(dev_priv)) { 5255 encoder->enable_clock = rkl_ddi_enable_clock; 5256 encoder->disable_clock = rkl_ddi_disable_clock; 5257 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5258 encoder->get_config = rkl_ddi_get_config; 5259 } else if (IS_DG1(dev_priv)) { 5260 encoder->enable_clock = dg1_ddi_enable_clock; 5261 encoder->disable_clock = dg1_ddi_disable_clock; 5262 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5263 encoder->get_config = dg1_ddi_get_config; 5264 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5265 if (intel_ddi_is_tc(dev_priv, port)) { 5266 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5267 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5268 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5269 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5270 encoder->get_config = icl_ddi_combo_get_config; 5271 } else { 5272 encoder->enable_clock = icl_ddi_combo_enable_clock; 5273 encoder->disable_clock = icl_ddi_combo_disable_clock; 5274 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5275 encoder->get_config = icl_ddi_combo_get_config; 5276 } 5277 } else if (DISPLAY_VER(dev_priv) >= 11) { 5278 if (intel_ddi_is_tc(dev_priv, port)) { 5279 encoder->enable_clock = icl_ddi_tc_enable_clock; 5280 encoder->disable_clock = icl_ddi_tc_disable_clock; 5281 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5282 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5283 encoder->get_config = icl_ddi_tc_get_config; 5284 } else { 5285 encoder->enable_clock = icl_ddi_combo_enable_clock; 5286 encoder->disable_clock = icl_ddi_combo_disable_clock; 5287 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5288 encoder->get_config = icl_ddi_combo_get_config; 5289 } 5290 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5291 /* BXT/GLK have fixed PLL->port mapping */ 5292 encoder->get_config = bxt_ddi_get_config; 5293 } else if (DISPLAY_VER(dev_priv) == 9) { 5294 encoder->enable_clock = skl_ddi_enable_clock; 5295 encoder->disable_clock = skl_ddi_disable_clock; 5296 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5297 encoder->get_config = skl_ddi_get_config; 5298 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5299 encoder->enable_clock = hsw_ddi_enable_clock; 5300 encoder->disable_clock = hsw_ddi_disable_clock; 5301 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5302 encoder->get_config = hsw_ddi_get_config; 5303 } 5304 5305 if (DISPLAY_VER(dev_priv) >= 14) { 5306 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5307 } else if (IS_DG2(dev_priv)) { 5308 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5309 } else if (DISPLAY_VER(dev_priv) >= 12) { 5310 if (intel_encoder_is_combo(encoder)) 5311 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5312 else 5313 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5314 } else if (DISPLAY_VER(dev_priv) >= 11) { 5315 if (intel_encoder_is_combo(encoder)) 5316 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5317 else 5318 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5319 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5320 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5321 } else { 5322 encoder->set_signal_levels = hsw_set_signal_levels; 5323 } 5324 5325 intel_ddi_buf_trans_init(encoder); 5326 5327 if (DISPLAY_VER(dev_priv) >= 13) 5328 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5329 else if (IS_DG1(dev_priv)) 5330 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5331 else if (IS_ROCKETLAKE(dev_priv)) 5332 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5333 else if (DISPLAY_VER(dev_priv) >= 12) 5334 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5335 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5336 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5337 else if (DISPLAY_VER(dev_priv) == 11) 5338 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5339 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5340 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5341 else 5342 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5343 5344 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 5345 5346 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5347 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5348 5349 dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5350 5351 dig_port->dp.output_reg = INVALID_MMIO_REG; 5352 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5353 5354 if (need_aux_ch(encoder, init_dp)) { 5355 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5356 if (dig_port->aux_ch == AUX_CH_NONE) 5357 goto err; 5358 } 5359 5360 if (intel_encoder_is_tc(encoder)) { 5361 bool is_legacy = 5362 !intel_bios_encoder_supports_typec_usb(devdata) && 5363 !intel_bios_encoder_supports_tbt(devdata); 5364 5365 if (!is_legacy && init_hdmi) { 5366 is_legacy = !init_dp; 5367 5368 drm_dbg_kms(&dev_priv->drm, 5369 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5370 port_name(port), 5371 str_yes_no(init_dp), 5372 is_legacy ? "legacy" : "non-legacy"); 5373 } 5374 5375 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5376 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5377 5378 dig_port->lock = intel_tc_port_lock; 5379 dig_port->unlock = intel_tc_port_unlock; 5380 5381 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5382 goto err; 5383 } 5384 5385 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5386 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5387 5388 if (DISPLAY_VER(dev_priv) >= 11) { 5389 if (intel_encoder_is_tc(encoder)) 5390 dig_port->connected = intel_tc_port_connected; 5391 else 5392 dig_port->connected = lpt_digital_port_connected; 5393 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5394 dig_port->connected = bdw_digital_port_connected; 5395 } else if (DISPLAY_VER(dev_priv) == 9) { 5396 dig_port->connected = lpt_digital_port_connected; 5397 } else if (IS_BROADWELL(dev_priv)) { 5398 if (port == PORT_A) 5399 dig_port->connected = bdw_digital_port_connected; 5400 else 5401 dig_port->connected = lpt_digital_port_connected; 5402 } else if (IS_HASWELL(dev_priv)) { 5403 if (port == PORT_A) 5404 dig_port->connected = hsw_digital_port_connected; 5405 else 5406 dig_port->connected = lpt_digital_port_connected; 5407 } 5408 5409 intel_infoframe_init(dig_port); 5410 5411 if (init_dp) { 5412 if (intel_ddi_init_dp_connector(dig_port)) 5413 goto err; 5414 5415 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5416 5417 if (dig_port->dp.mso_link_count) 5418 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5419 } 5420 5421 /* 5422 * In theory we don't need the encoder->type check, 5423 * but leave it just in case we have some really bad VBTs... 5424 */ 5425 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5426 if (intel_ddi_init_hdmi_connector(dig_port)) 5427 goto err; 5428 } 5429 5430 return; 5431 5432 err: 5433 drm_encoder_cleanup(&encoder->base); 5434 kfree(dig_port); 5435 } 5436