1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_privacy_screen_consumer.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "icl_dsi.h" 38 #include "intel_audio.h" 39 #include "intel_audio_regs.h" 40 #include "intel_backlight.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_cx0_phy.h" 46 #include "intel_cx0_phy_regs.h" 47 #include "intel_ddi.h" 48 #include "intel_ddi_buf_trans.h" 49 #include "intel_de.h" 50 #include "intel_display_power.h" 51 #include "intel_display_types.h" 52 #include "intel_dkl_phy.h" 53 #include "intel_dkl_phy_regs.h" 54 #include "intel_dp.h" 55 #include "intel_dp_aux.h" 56 #include "intel_dp_link_training.h" 57 #include "intel_dp_mst.h" 58 #include "intel_dp_test.h" 59 #include "intel_dp_tunnel.h" 60 #include "intel_dpio_phy.h" 61 #include "intel_dsi.h" 62 #include "intel_encoder.h" 63 #include "intel_fdi.h" 64 #include "intel_fifo_underrun.h" 65 #include "intel_gmbus.h" 66 #include "intel_hdcp.h" 67 #include "intel_hdmi.h" 68 #include "intel_hotplug.h" 69 #include "intel_hti.h" 70 #include "intel_lspcon.h" 71 #include "intel_mg_phy_regs.h" 72 #include "intel_modeset_lock.h" 73 #include "intel_pfit.h" 74 #include "intel_pps.h" 75 #include "intel_psr.h" 76 #include "intel_quirks.h" 77 #include "intel_snps_phy.h" 78 #include "intel_tc.h" 79 #include "intel_vdsc.h" 80 #include "intel_vdsc_regs.h" 81 #include "intel_vrr.h" 82 #include "skl_scaler.h" 83 #include "skl_universal_plane.h" 84 85 static const u8 index_to_dp_signal_levels[] = { 86 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 87 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 88 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 89 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 90 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 91 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 92 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 93 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 95 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 }; 97 98 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 99 const struct intel_ddi_buf_trans *trans) 100 { 101 int level; 102 103 level = intel_bios_hdmi_level_shift(encoder->devdata); 104 if (level < 0) 105 level = trans->hdmi_default_entry; 106 107 return level; 108 } 109 110 static bool has_buf_trans_select(struct intel_display *display) 111 { 112 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 113 } 114 115 static bool has_iboost(struct intel_display *display) 116 { 117 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 118 } 119 120 /* 121 * Starting with Haswell, DDI port buffers must be programmed with correct 122 * values in advance. This function programs the correct values for 123 * DP/eDP/FDI use cases. 124 */ 125 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 126 const struct intel_crtc_state *crtc_state) 127 { 128 struct intel_display *display = to_intel_display(encoder); 129 u32 iboost_bit = 0; 130 int i, n_entries; 131 enum port port = encoder->port; 132 const struct intel_ddi_buf_trans *trans; 133 134 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 135 if (drm_WARN_ON_ONCE(display->drm, !trans)) 136 return; 137 138 /* If we're boosting the current, set bit 31 of trans1 */ 139 if (has_iboost(display) && 140 intel_bios_dp_boost_level(encoder->devdata)) 141 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 142 143 for (i = 0; i < n_entries; i++) { 144 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 145 trans->entries[i].hsw.trans1 | iboost_bit); 146 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 147 trans->entries[i].hsw.trans2); 148 } 149 } 150 151 /* 152 * Starting with Haswell, DDI port buffers must be programmed with correct 153 * values in advance. This function programs the correct values for 154 * HDMI/DVI use cases. 155 */ 156 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 157 const struct intel_crtc_state *crtc_state) 158 { 159 struct intel_display *display = to_intel_display(encoder); 160 int level = intel_ddi_level(encoder, crtc_state, 0); 161 u32 iboost_bit = 0; 162 int n_entries; 163 enum port port = encoder->port; 164 const struct intel_ddi_buf_trans *trans; 165 166 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 167 if (drm_WARN_ON_ONCE(display->drm, !trans)) 168 return; 169 170 /* If we're boosting the current, set bit 31 of trans1 */ 171 if (has_iboost(display) && 172 intel_bios_hdmi_boost_level(encoder->devdata)) 173 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 174 175 /* Entry 9 is for HDMI: */ 176 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 177 trans->entries[level].hsw.trans1 | iboost_bit); 178 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 179 trans->entries[level].hsw.trans2); 180 } 181 182 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 183 { 184 if (DISPLAY_VER(display) >= 14) 185 return XELPDP_PORT_BUF_CTL1(display, port); 186 else 187 return DDI_BUF_CTL(port); 188 } 189 190 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 191 { 192 /* 193 * Bspec's platform specific timeouts: 194 * MTL+ : 100 us 195 * BXT : fixed 16 us 196 * HSW-ADL: 8 us 197 * 198 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 199 */ 200 if (display->platform.broxton) { 201 udelay(16); 202 return; 203 } 204 205 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 206 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 207 DDI_BUF_IS_IDLE, 10)) 208 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 209 port_name(port)); 210 } 211 212 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 213 { 214 struct intel_display *display = to_intel_display(encoder); 215 enum port port = encoder->port; 216 217 /* 218 * Bspec's platform specific timeouts: 219 * MTL+ : 10000 us 220 * DG2 : 1200 us 221 * TGL-ADL combo PHY: 1000 us 222 * TGL-ADL TypeC PHY: 3000 us 223 * HSW-ICL : fixed 518 us 224 */ 225 if (DISPLAY_VER(display) < 10) { 226 usleep_range(518, 1000); 227 return; 228 } 229 230 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 231 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 232 DDI_BUF_IS_IDLE, 10)) 233 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 234 port_name(port)); 235 } 236 237 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 238 { 239 switch (pll->info->id) { 240 case DPLL_ID_WRPLL1: 241 return PORT_CLK_SEL_WRPLL1; 242 case DPLL_ID_WRPLL2: 243 return PORT_CLK_SEL_WRPLL2; 244 case DPLL_ID_SPLL: 245 return PORT_CLK_SEL_SPLL; 246 case DPLL_ID_LCPLL_810: 247 return PORT_CLK_SEL_LCPLL_810; 248 case DPLL_ID_LCPLL_1350: 249 return PORT_CLK_SEL_LCPLL_1350; 250 case DPLL_ID_LCPLL_2700: 251 return PORT_CLK_SEL_LCPLL_2700; 252 default: 253 MISSING_CASE(pll->info->id); 254 return PORT_CLK_SEL_NONE; 255 } 256 } 257 258 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 259 const struct intel_crtc_state *crtc_state) 260 { 261 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 262 int clock = crtc_state->port_clock; 263 const enum intel_dpll_id id = pll->info->id; 264 265 switch (id) { 266 default: 267 /* 268 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 269 * here, so do warn if this get passed in 270 */ 271 MISSING_CASE(id); 272 return DDI_CLK_SEL_NONE; 273 case DPLL_ID_ICL_TBTPLL: 274 switch (clock) { 275 case 162000: 276 return DDI_CLK_SEL_TBT_162; 277 case 270000: 278 return DDI_CLK_SEL_TBT_270; 279 case 540000: 280 return DDI_CLK_SEL_TBT_540; 281 case 810000: 282 return DDI_CLK_SEL_TBT_810; 283 default: 284 MISSING_CASE(clock); 285 return DDI_CLK_SEL_NONE; 286 } 287 case DPLL_ID_ICL_MGPLL1: 288 case DPLL_ID_ICL_MGPLL2: 289 case DPLL_ID_ICL_MGPLL3: 290 case DPLL_ID_ICL_MGPLL4: 291 case DPLL_ID_TGL_MGPLL5: 292 case DPLL_ID_TGL_MGPLL6: 293 return DDI_CLK_SEL_MG; 294 } 295 } 296 297 static u32 ddi_buf_phy_link_rate(int port_clock) 298 { 299 switch (port_clock) { 300 case 162000: 301 return DDI_BUF_PHY_LINK_RATE(0); 302 case 216000: 303 return DDI_BUF_PHY_LINK_RATE(4); 304 case 243000: 305 return DDI_BUF_PHY_LINK_RATE(5); 306 case 270000: 307 return DDI_BUF_PHY_LINK_RATE(1); 308 case 324000: 309 return DDI_BUF_PHY_LINK_RATE(6); 310 case 432000: 311 return DDI_BUF_PHY_LINK_RATE(7); 312 case 540000: 313 return DDI_BUF_PHY_LINK_RATE(2); 314 case 810000: 315 return DDI_BUF_PHY_LINK_RATE(3); 316 default: 317 MISSING_CASE(port_clock); 318 return DDI_BUF_PHY_LINK_RATE(0); 319 } 320 } 321 322 static int dp_phy_lane_stagger_delay(int port_clock) 323 { 324 /* 325 * Return the number of symbol clocks delay used to stagger the 326 * assertion/desassertion of the port lane enables. The target delay 327 * time is 100 ns or greater, return the number of symbols specific to 328 * the provided port_clock (aka link clock) corresponding to this delay 329 * time, i.e. so that 330 * 331 * number_of_symbols * duration_of_one_symbol >= 100 ns 332 * 333 * The delay must be applied only on TypeC DP outputs, for everything else 334 * the delay must be set to 0. 335 * 336 * Return the number of link symbols per 100 ns: 337 * port_clock (10 kHz) -> bits / 100 us 338 * / symbol_size -> symbols / 100 us 339 * / 1000 -> symbols / 100 ns 340 */ 341 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 342 } 343 344 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 345 const struct intel_crtc_state *crtc_state) 346 { 347 struct intel_display *display = to_intel_display(encoder); 348 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 349 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 350 351 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 352 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 353 DDI_BUF_TRANS_SELECT(0); 354 355 if (dig_port->lane_reversal) 356 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 357 if (dig_port->ddi_a_4_lanes) 358 intel_dp->DP |= DDI_A_4_LANES; 359 360 if (DISPLAY_VER(display) >= 14) { 361 if (intel_dp_is_uhbr(crtc_state)) 362 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 363 else 364 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 365 } 366 367 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 368 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 369 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 370 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 371 } 372 373 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 374 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 375 376 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 377 } 378 } 379 380 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 381 { 382 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 383 384 switch (val) { 385 case DDI_CLK_SEL_NONE: 386 return 0; 387 case DDI_CLK_SEL_TBT_162: 388 return 162000; 389 case DDI_CLK_SEL_TBT_270: 390 return 270000; 391 case DDI_CLK_SEL_TBT_540: 392 return 540000; 393 case DDI_CLK_SEL_TBT_810: 394 return 810000; 395 default: 396 MISSING_CASE(val); 397 return 0; 398 } 399 } 400 401 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 402 { 403 /* CRT dotclock is determined via other means */ 404 if (pipe_config->has_pch_encoder) 405 return; 406 407 pipe_config->hw.adjusted_mode.crtc_clock = 408 intel_crtc_dotclock(pipe_config); 409 } 410 411 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 412 const struct drm_connector_state *conn_state) 413 { 414 struct intel_display *display = to_intel_display(crtc_state); 415 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 416 u32 temp; 417 418 if (!intel_crtc_has_dp_encoder(crtc_state)) 419 return; 420 421 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 422 423 temp = DP_MSA_MISC_SYNC_CLOCK; 424 425 switch (crtc_state->pipe_bpp) { 426 case 18: 427 temp |= DP_MSA_MISC_6_BPC; 428 break; 429 case 24: 430 temp |= DP_MSA_MISC_8_BPC; 431 break; 432 case 30: 433 temp |= DP_MSA_MISC_10_BPC; 434 break; 435 case 36: 436 temp |= DP_MSA_MISC_12_BPC; 437 break; 438 default: 439 MISSING_CASE(crtc_state->pipe_bpp); 440 break; 441 } 442 443 /* nonsense combination */ 444 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 445 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 446 447 if (crtc_state->limited_color_range) 448 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 449 450 /* 451 * As per DP 1.2 spec section 2.3.4.3 while sending 452 * YCBCR 444 signals we should program MSA MISC1/0 fields with 453 * colorspace information. 454 */ 455 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 456 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 457 458 /* 459 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 460 * of Color Encoding Format and Content Color Gamut] while sending 461 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 462 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 463 */ 464 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 465 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 466 467 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 468 temp); 469 } 470 471 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 472 { 473 if (master_transcoder == TRANSCODER_EDP) 474 return 0; 475 else 476 return master_transcoder + 1; 477 } 478 479 static void 480 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 481 bool enable) 482 { 483 struct intel_display *display = to_intel_display(crtc_state); 484 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 485 u32 val = 0; 486 487 if (!HAS_DP20(display)) 488 return; 489 490 if (enable && intel_dp_is_uhbr(crtc_state)) 491 val = TRANS_DP2_128B132B_CHANNEL_CODING; 492 493 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 494 } 495 496 /* 497 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 498 * 499 * Only intended to be used by intel_ddi_enable_transcoder_func() and 500 * intel_ddi_config_transcoder_func(). 501 */ 502 static u32 503 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state) 505 { 506 struct intel_display *display = to_intel_display(crtc_state); 507 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 508 enum pipe pipe = crtc->pipe; 509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 510 enum port port = encoder->port; 511 u32 temp; 512 513 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 514 temp = TRANS_DDI_FUNC_ENABLE; 515 if (DISPLAY_VER(display) >= 12) 516 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 517 else 518 temp |= TRANS_DDI_SELECT_PORT(port); 519 520 switch (crtc_state->pipe_bpp) { 521 default: 522 MISSING_CASE(crtc_state->pipe_bpp); 523 fallthrough; 524 case 18: 525 temp |= TRANS_DDI_BPC_6; 526 break; 527 case 24: 528 temp |= TRANS_DDI_BPC_8; 529 break; 530 case 30: 531 temp |= TRANS_DDI_BPC_10; 532 break; 533 case 36: 534 temp |= TRANS_DDI_BPC_12; 535 break; 536 } 537 538 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 539 temp |= TRANS_DDI_PVSYNC; 540 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 541 temp |= TRANS_DDI_PHSYNC; 542 543 if (cpu_transcoder == TRANSCODER_EDP) { 544 switch (pipe) { 545 default: 546 MISSING_CASE(pipe); 547 fallthrough; 548 case PIPE_A: 549 /* On Haswell, can only use the always-on power well for 550 * eDP when not using the panel fitter, and when not 551 * using motion blur mitigation (which we don't 552 * support). */ 553 if (crtc_state->pch_pfit.force_thru) 554 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 555 else 556 temp |= TRANS_DDI_EDP_INPUT_A_ON; 557 break; 558 case PIPE_B: 559 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 560 break; 561 case PIPE_C: 562 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 563 break; 564 } 565 } 566 567 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 568 if (crtc_state->has_hdmi_sink) 569 temp |= TRANS_DDI_MODE_SELECT_HDMI; 570 else 571 temp |= TRANS_DDI_MODE_SELECT_DVI; 572 573 if (crtc_state->hdmi_scrambling) 574 temp |= TRANS_DDI_HDMI_SCRAMBLING; 575 if (crtc_state->hdmi_high_tmds_clock_ratio) 576 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 577 if (DISPLAY_VER(display) >= 14) 578 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 579 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 580 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 581 temp |= (crtc_state->fdi_lanes - 1) << 1; 582 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 583 intel_dp_is_uhbr(crtc_state)) { 584 if (intel_dp_is_uhbr(crtc_state)) 585 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 586 else 587 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 588 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 589 590 if (DISPLAY_VER(display) >= 12) { 591 enum transcoder master; 592 593 master = crtc_state->mst_master_transcoder; 594 drm_WARN_ON(display->drm, 595 master == INVALID_TRANSCODER); 596 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 597 } 598 } else { 599 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 600 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 601 } 602 603 if (IS_DISPLAY_VER(display, 8, 10) && 604 crtc_state->master_transcoder != INVALID_TRANSCODER) { 605 u8 master_select = 606 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 607 608 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 609 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 610 } 611 612 return temp; 613 } 614 615 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 616 const struct intel_crtc_state *crtc_state) 617 { 618 struct intel_display *display = to_intel_display(crtc_state); 619 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 620 621 if (DISPLAY_VER(display) >= 11) { 622 enum transcoder master_transcoder = crtc_state->master_transcoder; 623 u32 ctl2 = 0; 624 625 if (master_transcoder != INVALID_TRANSCODER) { 626 u8 master_select = 627 bdw_trans_port_sync_master_select(master_transcoder); 628 629 ctl2 |= PORT_SYNC_MODE_ENABLE | 630 PORT_SYNC_MODE_MASTER_SELECT(master_select); 631 } 632 633 intel_de_write(display, 634 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 635 ctl2); 636 } 637 638 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 639 intel_ddi_transcoder_func_reg_val_get(encoder, 640 crtc_state)); 641 } 642 643 /* 644 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 645 * bit for the DDI function and enables the DP2 configuration. Called for all 646 * transcoder types. 647 */ 648 void 649 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 650 const struct intel_crtc_state *crtc_state) 651 { 652 struct intel_display *display = to_intel_display(crtc_state); 653 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 654 u32 ctl; 655 656 intel_ddi_config_transcoder_dp2(crtc_state, true); 657 658 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 659 ctl &= ~TRANS_DDI_FUNC_ENABLE; 660 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 661 ctl); 662 } 663 664 /* 665 * Disable the DDI function and port syncing. 666 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 667 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 668 * transcoders these are done later in intel_ddi_post_disable_dp(). 669 */ 670 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 671 { 672 struct intel_display *display = to_intel_display(crtc_state); 673 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 674 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 675 u32 ctl; 676 677 if (DISPLAY_VER(display) >= 11) 678 intel_de_write(display, 679 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 680 0); 681 682 ctl = intel_de_read(display, 683 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 684 685 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 686 687 ctl &= ~TRANS_DDI_FUNC_ENABLE; 688 689 if (IS_DISPLAY_VER(display, 8, 10)) 690 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 691 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 692 693 if (DISPLAY_VER(display) >= 12) { 694 if (!intel_dp_mst_is_master_trans(crtc_state)) { 695 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 696 TRANS_DDI_MODE_SELECT_MASK); 697 } 698 } else { 699 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 700 } 701 702 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 703 ctl); 704 705 if (intel_dp_mst_is_slave_trans(crtc_state)) 706 intel_ddi_config_transcoder_dp2(crtc_state, false); 707 708 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 709 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 710 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 711 /* Quirk time at 100ms for reliable operation */ 712 msleep(100); 713 } 714 } 715 716 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 717 enum transcoder cpu_transcoder, 718 bool enable, u32 hdcp_mask) 719 { 720 struct intel_display *display = to_intel_display(intel_encoder); 721 intel_wakeref_t wakeref; 722 int ret = 0; 723 724 wakeref = intel_display_power_get_if_enabled(display, 725 intel_encoder->power_domain); 726 if (drm_WARN_ON(display->drm, !wakeref)) 727 return -ENXIO; 728 729 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 730 hdcp_mask, enable ? hdcp_mask : 0); 731 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 732 return ret; 733 } 734 735 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 736 { 737 struct intel_display *display = to_intel_display(intel_connector); 738 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 739 int type = intel_connector->base.connector_type; 740 enum port port = encoder->port; 741 enum transcoder cpu_transcoder; 742 intel_wakeref_t wakeref; 743 enum pipe pipe = 0; 744 u32 ddi_mode; 745 bool ret; 746 747 wakeref = intel_display_power_get_if_enabled(display, 748 encoder->power_domain); 749 if (!wakeref) 750 return false; 751 752 /* Note: This returns false for DP MST primary encoders. */ 753 if (!encoder->get_hw_state(encoder, &pipe)) { 754 ret = false; 755 goto out; 756 } 757 758 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 759 cpu_transcoder = TRANSCODER_EDP; 760 else 761 cpu_transcoder = (enum transcoder) pipe; 762 763 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 764 TRANS_DDI_MODE_SELECT_MASK; 765 766 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 767 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 768 ret = type == DRM_MODE_CONNECTOR_HDMIA; 769 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 770 ret = type == DRM_MODE_CONNECTOR_VGA; 771 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 772 ret = type == DRM_MODE_CONNECTOR_eDP || 773 type == DRM_MODE_CONNECTOR_DisplayPort; 774 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 775 /* 776 * encoder->get_hw_state() should have bailed out on MST. This 777 * must be SST and non-eDP. 778 */ 779 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 780 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 781 /* encoder->get_hw_state() should have bailed out on MST. */ 782 ret = false; 783 } else { 784 ret = false; 785 } 786 787 out: 788 intel_display_power_put(display, encoder->power_domain, wakeref); 789 790 return ret; 791 } 792 793 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 794 u8 *pipe_mask, bool *is_dp_mst) 795 { 796 struct intel_display *display = to_intel_display(encoder); 797 enum port port = encoder->port; 798 intel_wakeref_t wakeref; 799 enum pipe p; 800 u32 tmp; 801 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 802 803 *pipe_mask = 0; 804 *is_dp_mst = false; 805 806 wakeref = intel_display_power_get_if_enabled(display, 807 encoder->power_domain); 808 if (!wakeref) 809 return; 810 811 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 812 if (!(tmp & DDI_BUF_CTL_ENABLE)) 813 goto out; 814 815 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 816 tmp = intel_de_read(display, 817 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 818 819 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 820 default: 821 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 822 fallthrough; 823 case TRANS_DDI_EDP_INPUT_A_ON: 824 case TRANS_DDI_EDP_INPUT_A_ONOFF: 825 *pipe_mask = BIT(PIPE_A); 826 break; 827 case TRANS_DDI_EDP_INPUT_B_ONOFF: 828 *pipe_mask = BIT(PIPE_B); 829 break; 830 case TRANS_DDI_EDP_INPUT_C_ONOFF: 831 *pipe_mask = BIT(PIPE_C); 832 break; 833 } 834 835 goto out; 836 } 837 838 for_each_pipe(display, p) { 839 enum transcoder cpu_transcoder = (enum transcoder)p; 840 u32 port_mask, ddi_select, ddi_mode; 841 intel_wakeref_t trans_wakeref; 842 843 trans_wakeref = intel_display_power_get_if_enabled(display, 844 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 845 if (!trans_wakeref) 846 continue; 847 848 if (DISPLAY_VER(display) >= 12) { 849 port_mask = TGL_TRANS_DDI_PORT_MASK; 850 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 851 } else { 852 port_mask = TRANS_DDI_PORT_MASK; 853 ddi_select = TRANS_DDI_SELECT_PORT(port); 854 } 855 856 tmp = intel_de_read(display, 857 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 858 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 859 trans_wakeref); 860 861 if ((tmp & port_mask) != ddi_select) 862 continue; 863 864 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 865 866 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 867 mst_pipe_mask |= BIT(p); 868 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 869 dp128b132b_pipe_mask |= BIT(p); 870 871 *pipe_mask |= BIT(p); 872 } 873 874 if (!*pipe_mask) 875 drm_dbg_kms(display->drm, 876 "No pipe for [ENCODER:%d:%s] found\n", 877 encoder->base.base.id, encoder->base.name); 878 879 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 880 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 881 882 /* 883 * If we don't have 8b/10b MST, but have more than one 884 * transcoder in 128b/132b mode, we know it must be 128b/132b 885 * MST. 886 * 887 * Otherwise, we fall back to checking the current MST 888 * state. It's not accurate for hardware takeover at probe, but 889 * we don't expect MST to have been enabled at that point, and 890 * can assume it's SST. 891 */ 892 if (hweight8(dp128b132b_pipe_mask) > 1 || 893 intel_dp_mst_active_streams(intel_dp)) 894 mst_pipe_mask = dp128b132b_pipe_mask; 895 } 896 897 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 898 drm_dbg_kms(display->drm, 899 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 900 encoder->base.base.id, encoder->base.name, 901 *pipe_mask); 902 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 903 } 904 905 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 906 drm_dbg_kms(display->drm, 907 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 908 encoder->base.base.id, encoder->base.name, 909 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 910 else 911 *is_dp_mst = mst_pipe_mask; 912 913 out: 914 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 915 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 916 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 917 BXT_PHY_LANE_POWERDOWN_ACK | 918 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 919 drm_err(display->drm, 920 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 921 encoder->base.base.id, encoder->base.name, tmp); 922 } 923 924 intel_display_power_put(display, encoder->power_domain, wakeref); 925 } 926 927 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 928 enum pipe *pipe) 929 { 930 u8 pipe_mask; 931 bool is_mst; 932 933 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 934 935 if (is_mst || !pipe_mask) 936 return false; 937 938 *pipe = ffs(pipe_mask) - 1; 939 940 return true; 941 } 942 943 static enum intel_display_power_domain 944 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 945 const struct intel_crtc_state *crtc_state) 946 { 947 struct intel_display *display = to_intel_display(dig_port); 948 949 /* 950 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 951 * DC states enabled at the same time, while for driver initiated AUX 952 * transfers we need the same AUX IOs to be powered but with DC states 953 * disabled. Accordingly use the AUX_IO_<port> power domain here which 954 * leaves DC states enabled. 955 * 956 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 957 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 958 * well, so we can acquire a wider AUX_<port> power domain reference 959 * instead of a specific AUX_IO_<port> reference without powering up any 960 * extra wells. 961 */ 962 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 963 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 964 else if (DISPLAY_VER(display) < 14 && 965 (intel_crtc_has_dp_encoder(crtc_state) || 966 intel_encoder_is_tc(&dig_port->base))) 967 return intel_aux_power_domain(dig_port); 968 else 969 return POWER_DOMAIN_INVALID; 970 } 971 972 static void 973 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 974 const struct intel_crtc_state *crtc_state) 975 { 976 struct intel_display *display = to_intel_display(dig_port); 977 enum intel_display_power_domain domain = 978 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 979 980 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 981 982 if (domain == POWER_DOMAIN_INVALID) 983 return; 984 985 dig_port->aux_wakeref = intel_display_power_get(display, domain); 986 } 987 988 static void 989 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 990 const struct intel_crtc_state *crtc_state) 991 { 992 struct intel_display *display = to_intel_display(dig_port); 993 enum intel_display_power_domain domain = 994 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 995 intel_wakeref_t wf; 996 997 wf = fetch_and_zero(&dig_port->aux_wakeref); 998 if (!wf) 999 return; 1000 1001 intel_display_power_put(display, domain, wf); 1002 } 1003 1004 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1005 struct intel_crtc_state *crtc_state) 1006 { 1007 struct intel_display *display = to_intel_display(encoder); 1008 struct intel_digital_port *dig_port; 1009 1010 /* 1011 * TODO: Add support for MST encoders. Atm, the following should never 1012 * happen since fake-MST encoders don't set their get_power_domains() 1013 * hook. 1014 */ 1015 if (drm_WARN_ON(display->drm, 1016 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1017 return; 1018 1019 dig_port = enc_to_dig_port(encoder); 1020 1021 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1022 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1023 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1024 dig_port->ddi_io_power_domain); 1025 } 1026 1027 main_link_aux_power_domain_get(dig_port, crtc_state); 1028 } 1029 1030 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1031 const struct intel_crtc_state *crtc_state) 1032 { 1033 struct intel_display *display = to_intel_display(crtc_state); 1034 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1035 enum phy phy = intel_encoder_to_phy(encoder); 1036 u32 val; 1037 1038 if (cpu_transcoder == TRANSCODER_EDP) 1039 return; 1040 1041 if (DISPLAY_VER(display) >= 13) 1042 val = TGL_TRANS_CLK_SEL_PORT(phy); 1043 else if (DISPLAY_VER(display) >= 12) 1044 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1045 else 1046 val = TRANS_CLK_SEL_PORT(encoder->port); 1047 1048 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1049 } 1050 1051 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1052 { 1053 struct intel_display *display = to_intel_display(crtc_state); 1054 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1055 u32 val; 1056 1057 if (cpu_transcoder == TRANSCODER_EDP) 1058 return; 1059 1060 if (DISPLAY_VER(display) >= 12) 1061 val = TGL_TRANS_CLK_SEL_DISABLED; 1062 else 1063 val = TRANS_CLK_SEL_DISABLED; 1064 1065 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1066 } 1067 1068 static void _skl_ddi_set_iboost(struct intel_display *display, 1069 enum port port, u8 iboost) 1070 { 1071 u32 tmp; 1072 1073 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1074 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1075 if (iboost) 1076 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1077 else 1078 tmp |= BALANCE_LEG_DISABLE(port); 1079 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1080 } 1081 1082 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1083 const struct intel_crtc_state *crtc_state, 1084 int level) 1085 { 1086 struct intel_display *display = to_intel_display(encoder); 1087 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1088 u8 iboost; 1089 1090 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1091 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1092 else 1093 iboost = intel_bios_dp_boost_level(encoder->devdata); 1094 1095 if (iboost == 0) { 1096 const struct intel_ddi_buf_trans *trans; 1097 int n_entries; 1098 1099 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1100 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1101 return; 1102 1103 iboost = trans->entries[level].hsw.i_boost; 1104 } 1105 1106 /* Make sure that the requested I_boost is valid */ 1107 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1108 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1109 return; 1110 } 1111 1112 _skl_ddi_set_iboost(display, encoder->port, iboost); 1113 1114 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1115 _skl_ddi_set_iboost(display, PORT_E, iboost); 1116 } 1117 1118 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1119 const struct intel_crtc_state *crtc_state) 1120 { 1121 struct intel_display *display = to_intel_display(intel_dp); 1122 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1123 int n_entries; 1124 1125 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1126 1127 if (drm_WARN_ON(display->drm, n_entries < 1)) 1128 n_entries = 1; 1129 if (drm_WARN_ON(display->drm, 1130 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1131 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1132 1133 return index_to_dp_signal_levels[n_entries - 1] & 1134 DP_TRAIN_VOLTAGE_SWING_MASK; 1135 } 1136 1137 /* 1138 * We assume that the full set of pre-emphasis values can be 1139 * used on all DDI platforms. Should that change we need to 1140 * rethink this code. 1141 */ 1142 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1143 { 1144 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1145 } 1146 1147 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1148 int lane) 1149 { 1150 if (crtc_state->port_clock > 600000) 1151 return 0; 1152 1153 if (crtc_state->lane_count == 4) 1154 return lane >= 1 ? LOADGEN_SELECT : 0; 1155 else 1156 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1157 } 1158 1159 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1160 const struct intel_crtc_state *crtc_state) 1161 { 1162 struct intel_display *display = to_intel_display(encoder); 1163 const struct intel_ddi_buf_trans *trans; 1164 enum phy phy = intel_encoder_to_phy(encoder); 1165 int n_entries, ln; 1166 u32 val; 1167 1168 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1169 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1170 return; 1171 1172 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1173 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1174 1175 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1176 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1177 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1178 intel_dp->hobl_active ? val : 0); 1179 } 1180 1181 /* Set PORT_TX_DW5 */ 1182 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1183 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1184 COEFF_POLARITY | CURSOR_PROGRAM | 1185 TAP2_DISABLE | TAP3_DISABLE); 1186 val |= SCALING_MODE_SEL(0x2); 1187 val |= RTERM_SELECT(0x6); 1188 val |= TAP3_DISABLE; 1189 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1190 1191 /* Program PORT_TX_DW2 */ 1192 for (ln = 0; ln < 4; ln++) { 1193 int level = intel_ddi_level(encoder, crtc_state, ln); 1194 1195 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1196 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1197 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1198 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1199 RCOMP_SCALAR(0x98)); 1200 } 1201 1202 /* Program PORT_TX_DW4 */ 1203 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1204 for (ln = 0; ln < 4; ln++) { 1205 int level = intel_ddi_level(encoder, crtc_state, ln); 1206 1207 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1208 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1209 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1210 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1211 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1212 } 1213 1214 /* Program PORT_TX_DW7 */ 1215 for (ln = 0; ln < 4; ln++) { 1216 int level = intel_ddi_level(encoder, crtc_state, ln); 1217 1218 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1219 N_SCALAR_MASK, 1220 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1221 } 1222 } 1223 1224 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1225 const struct intel_crtc_state *crtc_state) 1226 { 1227 struct intel_display *display = to_intel_display(encoder); 1228 enum phy phy = intel_encoder_to_phy(encoder); 1229 u32 val; 1230 int ln; 1231 1232 /* 1233 * 1. If port type is eDP or DP, 1234 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1235 * else clear to 0b. 1236 */ 1237 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1238 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1239 val &= ~COMMON_KEEPER_EN; 1240 else 1241 val |= COMMON_KEEPER_EN; 1242 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1243 1244 /* 2. Program loadgen select */ 1245 /* 1246 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1247 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1248 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1249 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1250 */ 1251 for (ln = 0; ln < 4; ln++) { 1252 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1253 LOADGEN_SELECT, 1254 icl_combo_phy_loadgen_select(crtc_state, ln)); 1255 } 1256 1257 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1258 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1259 0, SUS_CLOCK_CONFIG); 1260 1261 /* 4. Clear training enable to change swing values */ 1262 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1263 val &= ~TX_TRAINING_EN; 1264 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1265 1266 /* 5. Program swing and de-emphasis */ 1267 icl_ddi_combo_vswing_program(encoder, crtc_state); 1268 1269 /* 6. Set training enable to trigger update */ 1270 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1271 val |= TX_TRAINING_EN; 1272 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1273 } 1274 1275 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1276 const struct intel_crtc_state *crtc_state) 1277 { 1278 struct intel_display *display = to_intel_display(encoder); 1279 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1280 const struct intel_ddi_buf_trans *trans; 1281 int n_entries, ln; 1282 1283 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1284 return; 1285 1286 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1287 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1288 return; 1289 1290 for (ln = 0; ln < 2; ln++) { 1291 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1292 CRI_USE_FS32, 0); 1293 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1294 CRI_USE_FS32, 0); 1295 } 1296 1297 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1298 for (ln = 0; ln < 2; ln++) { 1299 int level; 1300 1301 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1302 1303 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1304 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1305 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1306 1307 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1308 1309 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1310 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1311 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1312 } 1313 1314 /* Program MG_TX_DRVCTRL with values from vswing table */ 1315 for (ln = 0; ln < 2; ln++) { 1316 int level; 1317 1318 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1319 1320 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1321 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1322 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1323 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1324 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1325 CRI_TXDEEMPH_OVERRIDE_EN); 1326 1327 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1328 1329 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1330 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1331 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1332 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1333 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1334 CRI_TXDEEMPH_OVERRIDE_EN); 1335 1336 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1337 } 1338 1339 /* 1340 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1341 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1342 * values from table for which TX1 and TX2 enabled. 1343 */ 1344 for (ln = 0; ln < 2; ln++) { 1345 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1346 CFG_LOW_RATE_LKREN_EN, 1347 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1348 } 1349 1350 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1351 for (ln = 0; ln < 2; ln++) { 1352 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1353 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1354 CFG_AMI_CK_DIV_OVERRIDE_EN, 1355 crtc_state->port_clock > 500000 ? 1356 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1357 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1358 1359 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1360 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1361 CFG_AMI_CK_DIV_OVERRIDE_EN, 1362 crtc_state->port_clock > 500000 ? 1363 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1364 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1365 } 1366 1367 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1368 for (ln = 0; ln < 2; ln++) { 1369 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1370 0, CRI_CALCINIT); 1371 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1372 0, CRI_CALCINIT); 1373 } 1374 } 1375 1376 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1377 const struct intel_crtc_state *crtc_state) 1378 { 1379 struct intel_display *display = to_intel_display(encoder); 1380 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1381 const struct intel_ddi_buf_trans *trans; 1382 int n_entries, ln; 1383 1384 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1385 return; 1386 1387 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1388 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1389 return; 1390 1391 for (ln = 0; ln < 2; ln++) { 1392 int level; 1393 1394 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1395 1396 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1397 1398 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1399 DKL_TX_PRESHOOT_COEFF_MASK | 1400 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1401 DKL_TX_VSWING_CONTROL_MASK, 1402 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1403 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1404 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1405 1406 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1407 1408 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1409 DKL_TX_PRESHOOT_COEFF_MASK | 1410 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1411 DKL_TX_VSWING_CONTROL_MASK, 1412 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1413 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1414 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1415 1416 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1417 DKL_TX_DP20BITMODE, 0); 1418 1419 if (display->platform.alderlake_p) { 1420 u32 val; 1421 1422 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1423 if (ln == 0) { 1424 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1425 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1426 } else { 1427 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1428 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1429 } 1430 } else { 1431 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1432 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1433 } 1434 1435 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1436 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1437 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1438 val); 1439 } 1440 } 1441 } 1442 1443 static int translate_signal_level(struct intel_dp *intel_dp, 1444 u8 signal_levels) 1445 { 1446 struct intel_display *display = to_intel_display(intel_dp); 1447 int i; 1448 1449 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1450 if (index_to_dp_signal_levels[i] == signal_levels) 1451 return i; 1452 } 1453 1454 drm_WARN(display->drm, 1, 1455 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1456 signal_levels); 1457 1458 return 0; 1459 } 1460 1461 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1462 const struct intel_crtc_state *crtc_state, 1463 int lane) 1464 { 1465 u8 train_set = intel_dp->train_set[lane]; 1466 1467 if (intel_dp_is_uhbr(crtc_state)) { 1468 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1469 } else { 1470 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1471 DP_TRAIN_PRE_EMPHASIS_MASK); 1472 1473 return translate_signal_level(intel_dp, signal_levels); 1474 } 1475 } 1476 1477 int intel_ddi_level(struct intel_encoder *encoder, 1478 const struct intel_crtc_state *crtc_state, 1479 int lane) 1480 { 1481 struct intel_display *display = to_intel_display(encoder); 1482 const struct intel_ddi_buf_trans *trans; 1483 int level, n_entries; 1484 1485 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1486 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1487 return 0; 1488 1489 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1490 level = intel_ddi_hdmi_level(encoder, trans); 1491 else 1492 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1493 lane); 1494 1495 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1496 level = n_entries - 1; 1497 1498 return level; 1499 } 1500 1501 static void 1502 hsw_set_signal_levels(struct intel_encoder *encoder, 1503 const struct intel_crtc_state *crtc_state) 1504 { 1505 struct intel_display *display = to_intel_display(encoder); 1506 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1507 int level = intel_ddi_level(encoder, crtc_state, 0); 1508 enum port port = encoder->port; 1509 u32 signal_levels; 1510 1511 if (has_iboost(display)) 1512 skl_ddi_set_iboost(encoder, crtc_state, level); 1513 1514 /* HDMI ignores the rest */ 1515 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1516 return; 1517 1518 signal_levels = DDI_BUF_TRANS_SELECT(level); 1519 1520 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1521 signal_levels); 1522 1523 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1524 intel_dp->DP |= signal_levels; 1525 1526 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1527 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1528 } 1529 1530 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1531 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1532 { 1533 mutex_lock(&display->dpll.lock); 1534 1535 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1536 1537 /* 1538 * "This step and the step before must be 1539 * done with separate register writes." 1540 */ 1541 intel_de_rmw(display, reg, clk_off, 0); 1542 1543 mutex_unlock(&display->dpll.lock); 1544 } 1545 1546 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1547 u32 clk_off) 1548 { 1549 mutex_lock(&display->dpll.lock); 1550 1551 intel_de_rmw(display, reg, 0, clk_off); 1552 1553 mutex_unlock(&display->dpll.lock); 1554 } 1555 1556 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1557 u32 clk_off) 1558 { 1559 return !(intel_de_read(display, reg) & clk_off); 1560 } 1561 1562 static struct intel_shared_dpll * 1563 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1564 u32 clk_sel_mask, u32 clk_sel_shift) 1565 { 1566 enum intel_dpll_id id; 1567 1568 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1569 1570 return intel_get_shared_dpll_by_id(display, id); 1571 } 1572 1573 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1574 const struct intel_crtc_state *crtc_state) 1575 { 1576 struct intel_display *display = to_intel_display(encoder); 1577 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1578 enum phy phy = intel_encoder_to_phy(encoder); 1579 1580 if (drm_WARN_ON(display->drm, !pll)) 1581 return; 1582 1583 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1584 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1585 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1586 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1587 } 1588 1589 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1590 { 1591 struct intel_display *display = to_intel_display(encoder); 1592 enum phy phy = intel_encoder_to_phy(encoder); 1593 1594 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1595 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1596 } 1597 1598 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1599 { 1600 struct intel_display *display = to_intel_display(encoder); 1601 enum phy phy = intel_encoder_to_phy(encoder); 1602 1603 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1604 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1605 } 1606 1607 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1608 { 1609 struct intel_display *display = to_intel_display(encoder); 1610 enum phy phy = intel_encoder_to_phy(encoder); 1611 1612 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1613 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1614 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1615 } 1616 1617 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1618 const struct intel_crtc_state *crtc_state) 1619 { 1620 struct intel_display *display = to_intel_display(encoder); 1621 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1622 enum phy phy = intel_encoder_to_phy(encoder); 1623 1624 if (drm_WARN_ON(display->drm, !pll)) 1625 return; 1626 1627 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1628 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1629 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1630 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1631 } 1632 1633 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1634 { 1635 struct intel_display *display = to_intel_display(encoder); 1636 enum phy phy = intel_encoder_to_phy(encoder); 1637 1638 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1639 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1640 } 1641 1642 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1643 { 1644 struct intel_display *display = to_intel_display(encoder); 1645 enum phy phy = intel_encoder_to_phy(encoder); 1646 1647 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1648 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1649 } 1650 1651 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1652 { 1653 struct intel_display *display = to_intel_display(encoder); 1654 enum phy phy = intel_encoder_to_phy(encoder); 1655 1656 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1657 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1658 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1659 } 1660 1661 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1662 const struct intel_crtc_state *crtc_state) 1663 { 1664 struct intel_display *display = to_intel_display(encoder); 1665 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1666 enum phy phy = intel_encoder_to_phy(encoder); 1667 1668 if (drm_WARN_ON(display->drm, !pll)) 1669 return; 1670 1671 /* 1672 * If we fail this, something went very wrong: first 2 PLLs should be 1673 * used by first 2 phys and last 2 PLLs by last phys 1674 */ 1675 if (drm_WARN_ON(display->drm, 1676 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1677 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1678 return; 1679 1680 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1681 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1682 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1683 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1684 } 1685 1686 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1687 { 1688 struct intel_display *display = to_intel_display(encoder); 1689 enum phy phy = intel_encoder_to_phy(encoder); 1690 1691 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1692 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1693 } 1694 1695 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1696 { 1697 struct intel_display *display = to_intel_display(encoder); 1698 enum phy phy = intel_encoder_to_phy(encoder); 1699 1700 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1701 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1702 } 1703 1704 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1705 { 1706 struct intel_display *display = to_intel_display(encoder); 1707 enum phy phy = intel_encoder_to_phy(encoder); 1708 enum intel_dpll_id id; 1709 u32 val; 1710 1711 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1712 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1713 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1714 id = val; 1715 1716 /* 1717 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1718 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1719 * bit for phy C and D. 1720 */ 1721 if (phy >= PHY_C) 1722 id += DPLL_ID_DG1_DPLL2; 1723 1724 return intel_get_shared_dpll_by_id(display, id); 1725 } 1726 1727 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1728 const struct intel_crtc_state *crtc_state) 1729 { 1730 struct intel_display *display = to_intel_display(encoder); 1731 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1732 enum phy phy = intel_encoder_to_phy(encoder); 1733 1734 if (drm_WARN_ON(display->drm, !pll)) 1735 return; 1736 1737 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1738 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1739 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1740 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1741 } 1742 1743 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1744 { 1745 struct intel_display *display = to_intel_display(encoder); 1746 enum phy phy = intel_encoder_to_phy(encoder); 1747 1748 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1749 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1750 } 1751 1752 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1753 { 1754 struct intel_display *display = to_intel_display(encoder); 1755 enum phy phy = intel_encoder_to_phy(encoder); 1756 1757 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1758 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1759 } 1760 1761 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1762 { 1763 struct intel_display *display = to_intel_display(encoder); 1764 enum phy phy = intel_encoder_to_phy(encoder); 1765 1766 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1767 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1768 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1769 } 1770 1771 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1772 const struct intel_crtc_state *crtc_state) 1773 { 1774 struct intel_display *display = to_intel_display(encoder); 1775 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1776 enum port port = encoder->port; 1777 1778 if (drm_WARN_ON(display->drm, !pll)) 1779 return; 1780 1781 /* 1782 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1783 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1784 */ 1785 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1786 1787 icl_ddi_combo_enable_clock(encoder, crtc_state); 1788 } 1789 1790 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1791 { 1792 struct intel_display *display = to_intel_display(encoder); 1793 enum port port = encoder->port; 1794 1795 icl_ddi_combo_disable_clock(encoder); 1796 1797 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1798 } 1799 1800 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1801 { 1802 struct intel_display *display = to_intel_display(encoder); 1803 enum port port = encoder->port; 1804 u32 tmp; 1805 1806 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1807 1808 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1809 return false; 1810 1811 return icl_ddi_combo_is_clock_enabled(encoder); 1812 } 1813 1814 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1815 const struct intel_crtc_state *crtc_state) 1816 { 1817 struct intel_display *display = to_intel_display(encoder); 1818 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1819 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1820 enum port port = encoder->port; 1821 1822 if (drm_WARN_ON(display->drm, !pll)) 1823 return; 1824 1825 intel_de_write(display, DDI_CLK_SEL(port), 1826 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1827 1828 mutex_lock(&display->dpll.lock); 1829 1830 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1831 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1832 1833 mutex_unlock(&display->dpll.lock); 1834 } 1835 1836 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1837 { 1838 struct intel_display *display = to_intel_display(encoder); 1839 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1840 enum port port = encoder->port; 1841 1842 mutex_lock(&display->dpll.lock); 1843 1844 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1845 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1846 1847 mutex_unlock(&display->dpll.lock); 1848 1849 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1850 } 1851 1852 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1853 { 1854 struct intel_display *display = to_intel_display(encoder); 1855 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1856 enum port port = encoder->port; 1857 u32 tmp; 1858 1859 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1860 1861 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1862 return false; 1863 1864 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1865 1866 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1867 } 1868 1869 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1870 { 1871 struct intel_display *display = to_intel_display(encoder); 1872 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1873 enum port port = encoder->port; 1874 enum intel_dpll_id id; 1875 u32 tmp; 1876 1877 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1878 1879 switch (tmp & DDI_CLK_SEL_MASK) { 1880 case DDI_CLK_SEL_TBT_162: 1881 case DDI_CLK_SEL_TBT_270: 1882 case DDI_CLK_SEL_TBT_540: 1883 case DDI_CLK_SEL_TBT_810: 1884 id = DPLL_ID_ICL_TBTPLL; 1885 break; 1886 case DDI_CLK_SEL_MG: 1887 id = icl_tc_port_to_pll_id(tc_port); 1888 break; 1889 default: 1890 MISSING_CASE(tmp); 1891 fallthrough; 1892 case DDI_CLK_SEL_NONE: 1893 return NULL; 1894 } 1895 1896 return intel_get_shared_dpll_by_id(display, id); 1897 } 1898 1899 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1900 { 1901 struct intel_display *display = to_intel_display(encoder->base.dev); 1902 enum intel_dpll_id id; 1903 1904 switch (encoder->port) { 1905 case PORT_A: 1906 id = DPLL_ID_SKL_DPLL0; 1907 break; 1908 case PORT_B: 1909 id = DPLL_ID_SKL_DPLL1; 1910 break; 1911 case PORT_C: 1912 id = DPLL_ID_SKL_DPLL2; 1913 break; 1914 default: 1915 MISSING_CASE(encoder->port); 1916 return NULL; 1917 } 1918 1919 return intel_get_shared_dpll_by_id(display, id); 1920 } 1921 1922 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1923 const struct intel_crtc_state *crtc_state) 1924 { 1925 struct intel_display *display = to_intel_display(encoder); 1926 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1927 enum port port = encoder->port; 1928 1929 if (drm_WARN_ON(display->drm, !pll)) 1930 return; 1931 1932 mutex_lock(&display->dpll.lock); 1933 1934 intel_de_rmw(display, DPLL_CTRL2, 1935 DPLL_CTRL2_DDI_CLK_OFF(port) | 1936 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1937 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1938 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1939 1940 mutex_unlock(&display->dpll.lock); 1941 } 1942 1943 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1944 { 1945 struct intel_display *display = to_intel_display(encoder); 1946 enum port port = encoder->port; 1947 1948 mutex_lock(&display->dpll.lock); 1949 1950 intel_de_rmw(display, DPLL_CTRL2, 1951 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1952 1953 mutex_unlock(&display->dpll.lock); 1954 } 1955 1956 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1957 { 1958 struct intel_display *display = to_intel_display(encoder); 1959 enum port port = encoder->port; 1960 1961 /* 1962 * FIXME Not sure if the override affects both 1963 * the PLL selection and the CLK_OFF bit. 1964 */ 1965 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1966 } 1967 1968 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1969 { 1970 struct intel_display *display = to_intel_display(encoder); 1971 enum port port = encoder->port; 1972 enum intel_dpll_id id; 1973 u32 tmp; 1974 1975 tmp = intel_de_read(display, DPLL_CTRL2); 1976 1977 /* 1978 * FIXME Not sure if the override affects both 1979 * the PLL selection and the CLK_OFF bit. 1980 */ 1981 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1982 return NULL; 1983 1984 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1985 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1986 1987 return intel_get_shared_dpll_by_id(display, id); 1988 } 1989 1990 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1991 const struct intel_crtc_state *crtc_state) 1992 { 1993 struct intel_display *display = to_intel_display(encoder); 1994 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1995 enum port port = encoder->port; 1996 1997 if (drm_WARN_ON(display->drm, !pll)) 1998 return; 1999 2000 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2001 } 2002 2003 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2004 { 2005 struct intel_display *display = to_intel_display(encoder); 2006 enum port port = encoder->port; 2007 2008 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2009 } 2010 2011 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2012 { 2013 struct intel_display *display = to_intel_display(encoder); 2014 enum port port = encoder->port; 2015 2016 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2017 } 2018 2019 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2020 { 2021 struct intel_display *display = to_intel_display(encoder); 2022 enum port port = encoder->port; 2023 enum intel_dpll_id id; 2024 u32 tmp; 2025 2026 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2027 2028 switch (tmp & PORT_CLK_SEL_MASK) { 2029 case PORT_CLK_SEL_WRPLL1: 2030 id = DPLL_ID_WRPLL1; 2031 break; 2032 case PORT_CLK_SEL_WRPLL2: 2033 id = DPLL_ID_WRPLL2; 2034 break; 2035 case PORT_CLK_SEL_SPLL: 2036 id = DPLL_ID_SPLL; 2037 break; 2038 case PORT_CLK_SEL_LCPLL_810: 2039 id = DPLL_ID_LCPLL_810; 2040 break; 2041 case PORT_CLK_SEL_LCPLL_1350: 2042 id = DPLL_ID_LCPLL_1350; 2043 break; 2044 case PORT_CLK_SEL_LCPLL_2700: 2045 id = DPLL_ID_LCPLL_2700; 2046 break; 2047 default: 2048 MISSING_CASE(tmp); 2049 fallthrough; 2050 case PORT_CLK_SEL_NONE: 2051 return NULL; 2052 } 2053 2054 return intel_get_shared_dpll_by_id(display, id); 2055 } 2056 2057 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2058 const struct intel_crtc_state *crtc_state) 2059 { 2060 if (encoder->enable_clock) 2061 encoder->enable_clock(encoder, crtc_state); 2062 } 2063 2064 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2065 { 2066 if (encoder->disable_clock) 2067 encoder->disable_clock(encoder); 2068 } 2069 2070 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2071 { 2072 struct intel_display *display = to_intel_display(encoder); 2073 u32 port_mask; 2074 bool ddi_clk_needed; 2075 2076 /* 2077 * In case of DP MST, we sanitize the primary encoder only, not the 2078 * virtual ones. 2079 */ 2080 if (encoder->type == INTEL_OUTPUT_DP_MST) 2081 return; 2082 2083 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2084 u8 pipe_mask; 2085 bool is_mst; 2086 2087 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2088 /* 2089 * In the unlikely case that BIOS enables DP in MST mode, just 2090 * warn since our MST HW readout is incomplete. 2091 */ 2092 if (drm_WARN_ON(display->drm, is_mst)) 2093 return; 2094 } 2095 2096 port_mask = BIT(encoder->port); 2097 ddi_clk_needed = encoder->base.crtc; 2098 2099 if (encoder->type == INTEL_OUTPUT_DSI) { 2100 struct intel_encoder *other_encoder; 2101 2102 port_mask = intel_dsi_encoder_ports(encoder); 2103 /* 2104 * Sanity check that we haven't incorrectly registered another 2105 * encoder using any of the ports of this DSI encoder. 2106 */ 2107 for_each_intel_encoder(display->drm, other_encoder) { 2108 if (other_encoder == encoder) 2109 continue; 2110 2111 if (drm_WARN_ON(display->drm, 2112 port_mask & BIT(other_encoder->port))) 2113 return; 2114 } 2115 /* 2116 * For DSI we keep the ddi clocks gated 2117 * except during enable/disable sequence. 2118 */ 2119 ddi_clk_needed = false; 2120 } 2121 2122 if (ddi_clk_needed || !encoder->is_clock_enabled || 2123 !encoder->is_clock_enabled(encoder)) 2124 return; 2125 2126 drm_dbg_kms(display->drm, 2127 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2128 encoder->base.base.id, encoder->base.name); 2129 2130 encoder->disable_clock(encoder); 2131 } 2132 2133 static void 2134 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2135 enum tc_port tc_port, u32 ln0, u32 ln1) 2136 { 2137 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2138 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2139 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2140 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2141 } 2142 2143 static void 2144 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2145 const struct intel_crtc_state *crtc_state) 2146 { 2147 struct intel_display *display = to_intel_display(crtc_state); 2148 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2149 u32 ln0, ln1, pin_assignment; 2150 u8 width; 2151 2152 if (DISPLAY_VER(display) >= 14) 2153 return; 2154 2155 if (!intel_encoder_is_tc(&dig_port->base) || 2156 intel_tc_port_in_tbt_alt_mode(dig_port)) 2157 return; 2158 2159 if (DISPLAY_VER(display) >= 12) { 2160 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2161 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2162 } else { 2163 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2164 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2165 } 2166 2167 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2168 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2169 2170 /* DPPATC */ 2171 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2172 width = crtc_state->lane_count; 2173 2174 switch (pin_assignment) { 2175 case 0x0: 2176 drm_WARN_ON(display->drm, 2177 !intel_tc_port_in_legacy_mode(dig_port)); 2178 if (width == 1) { 2179 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2180 } else { 2181 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2182 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2183 } 2184 break; 2185 case 0x1: 2186 if (width == 4) { 2187 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2188 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2189 } 2190 break; 2191 case 0x2: 2192 if (width == 2) { 2193 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2194 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2195 } 2196 break; 2197 case 0x3: 2198 case 0x5: 2199 if (width == 1) { 2200 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2201 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2202 } else { 2203 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2204 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2205 } 2206 break; 2207 case 0x4: 2208 case 0x6: 2209 if (width == 1) { 2210 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2211 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2212 } else { 2213 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2214 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2215 } 2216 break; 2217 default: 2218 MISSING_CASE(pin_assignment); 2219 } 2220 2221 if (DISPLAY_VER(display) >= 12) { 2222 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2223 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2224 /* WA_14018221282 */ 2225 if (IS_DISPLAY_VER(display, 12, 13)) 2226 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2227 2228 } else { 2229 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2230 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2231 } 2232 } 2233 2234 static enum transcoder 2235 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2236 { 2237 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2238 return crtc_state->mst_master_transcoder; 2239 else 2240 return crtc_state->cpu_transcoder; 2241 } 2242 2243 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2244 const struct intel_crtc_state *crtc_state) 2245 { 2246 struct intel_display *display = to_intel_display(encoder); 2247 2248 if (DISPLAY_VER(display) >= 12) 2249 return TGL_DP_TP_CTL(display, 2250 tgl_dp_tp_transcoder(crtc_state)); 2251 else 2252 return DP_TP_CTL(encoder->port); 2253 } 2254 2255 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2256 const struct intel_crtc_state *crtc_state) 2257 { 2258 struct intel_display *display = to_intel_display(encoder); 2259 2260 if (DISPLAY_VER(display) >= 12) 2261 return TGL_DP_TP_STATUS(display, 2262 tgl_dp_tp_transcoder(crtc_state)); 2263 else 2264 return DP_TP_STATUS(encoder->port); 2265 } 2266 2267 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2268 const struct intel_crtc_state *crtc_state) 2269 { 2270 struct intel_display *display = to_intel_display(encoder); 2271 2272 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2273 DP_TP_STATUS_ACT_SENT); 2274 } 2275 2276 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2277 const struct intel_crtc_state *crtc_state) 2278 { 2279 struct intel_display *display = to_intel_display(encoder); 2280 2281 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2282 DP_TP_STATUS_ACT_SENT, 1)) 2283 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2284 } 2285 2286 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2287 const struct intel_crtc_state *crtc_state, 2288 bool enable) 2289 { 2290 struct intel_display *display = to_intel_display(intel_dp); 2291 2292 if (!crtc_state->vrr.enable) 2293 return; 2294 2295 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2296 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2297 drm_dbg_kms(display->drm, 2298 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2299 str_enable_disable(enable)); 2300 } 2301 2302 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2303 const struct intel_crtc_state *crtc_state, 2304 bool enable) 2305 { 2306 struct intel_display *display = to_intel_display(intel_dp); 2307 2308 if (!crtc_state->fec_enable) 2309 return; 2310 2311 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2312 enable ? DP_FEC_READY : 0) <= 0) 2313 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2314 str_enabled_disabled(enable)); 2315 2316 if (enable && 2317 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2318 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2319 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2320 } 2321 2322 static int read_fec_detected_status(struct drm_dp_aux *aux) 2323 { 2324 int ret; 2325 u8 status; 2326 2327 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2328 if (ret < 0) 2329 return ret; 2330 2331 return status; 2332 } 2333 2334 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2335 { 2336 struct intel_display *display = to_intel_display(aux->drm_dev); 2337 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2338 int status; 2339 int err; 2340 2341 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2342 status & mask || status < 0, 2343 10000, 200000); 2344 2345 if (err || status < 0) { 2346 drm_dbg_kms(display->drm, 2347 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2348 str_enabled_disabled(enabled), err, status); 2349 return err ? err : status; 2350 } 2351 2352 return 0; 2353 } 2354 2355 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2356 const struct intel_crtc_state *crtc_state, 2357 bool enabled) 2358 { 2359 struct intel_display *display = to_intel_display(encoder); 2360 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2361 int ret; 2362 2363 if (!crtc_state->fec_enable) 2364 return 0; 2365 2366 if (enabled) 2367 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2368 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2369 else 2370 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2371 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2372 2373 if (ret) { 2374 drm_err(display->drm, 2375 "Timeout waiting for FEC live state to get %s\n", 2376 str_enabled_disabled(enabled)); 2377 return ret; 2378 } 2379 /* 2380 * At least the Synoptics MST hub doesn't set the detected flag for 2381 * FEC decoding disabling so skip waiting for that. 2382 */ 2383 if (enabled) { 2384 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2385 if (ret) 2386 return ret; 2387 } 2388 2389 return 0; 2390 } 2391 2392 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2393 const struct intel_crtc_state *crtc_state) 2394 { 2395 struct intel_display *display = to_intel_display(encoder); 2396 int i; 2397 int ret; 2398 2399 if (!crtc_state->fec_enable) 2400 return; 2401 2402 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2403 0, DP_TP_CTL_FEC_ENABLE); 2404 2405 if (DISPLAY_VER(display) < 30) 2406 return; 2407 2408 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2409 if (!ret) 2410 return; 2411 2412 for (i = 0; i < 3; i++) { 2413 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2414 2415 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2416 DP_TP_CTL_FEC_ENABLE, 0); 2417 2418 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2419 if (ret) 2420 continue; 2421 2422 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2423 0, DP_TP_CTL_FEC_ENABLE); 2424 2425 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2426 if (!ret) 2427 return; 2428 } 2429 2430 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2431 } 2432 2433 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2434 const struct intel_crtc_state *crtc_state) 2435 { 2436 struct intel_display *display = to_intel_display(encoder); 2437 2438 if (!crtc_state->fec_enable) 2439 return; 2440 2441 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2442 DP_TP_CTL_FEC_ENABLE, 0); 2443 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2444 } 2445 2446 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2447 const struct intel_crtc_state *crtc_state) 2448 { 2449 struct intel_display *display = to_intel_display(encoder); 2450 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2451 2452 if (intel_encoder_is_combo(encoder)) { 2453 enum phy phy = intel_encoder_to_phy(encoder); 2454 2455 intel_combo_phy_power_up_lanes(display, phy, false, 2456 crtc_state->lane_count, 2457 dig_port->lane_reversal); 2458 } 2459 } 2460 2461 /* 2462 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2463 * platforms. 2464 */ 2465 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2466 { 2467 if (DISPLAY_VER(display) > 20) 2468 return ~0; 2469 else if (display->platform.alderlake_p) 2470 return BIT(PIPE_A) | BIT(PIPE_B); 2471 else 2472 return BIT(PIPE_A); 2473 } 2474 2475 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2476 struct intel_crtc_state *pipe_config) 2477 { 2478 struct intel_display *display = to_intel_display(pipe_config); 2479 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2480 enum pipe pipe = crtc->pipe; 2481 u32 dss1; 2482 2483 if (!HAS_MSO(display)) 2484 return; 2485 2486 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2487 2488 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2489 if (!pipe_config->splitter.enable) 2490 return; 2491 2492 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2493 pipe_config->splitter.enable = false; 2494 return; 2495 } 2496 2497 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2498 default: 2499 drm_WARN(display->drm, true, 2500 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2501 fallthrough; 2502 case SPLITTER_CONFIGURATION_2_SEGMENT: 2503 pipe_config->splitter.link_count = 2; 2504 break; 2505 case SPLITTER_CONFIGURATION_4_SEGMENT: 2506 pipe_config->splitter.link_count = 4; 2507 break; 2508 } 2509 2510 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2511 } 2512 2513 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2514 { 2515 struct intel_display *display = to_intel_display(crtc_state); 2516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2517 enum pipe pipe = crtc->pipe; 2518 u32 dss1 = 0; 2519 2520 if (!HAS_MSO(display)) 2521 return; 2522 2523 if (crtc_state->splitter.enable) { 2524 dss1 |= SPLITTER_ENABLE; 2525 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2526 if (crtc_state->splitter.link_count == 2) 2527 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2528 else 2529 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2530 } 2531 2532 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2533 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2534 OVERLAP_PIXELS_MASK, dss1); 2535 } 2536 2537 static void 2538 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2539 { 2540 struct intel_display *display = to_intel_display(encoder); 2541 enum port port = encoder->port; 2542 i915_reg_t reg; 2543 u32 set_bits, wait_bits; 2544 2545 if (DISPLAY_VER(display) < 14) 2546 return; 2547 2548 if (DISPLAY_VER(display) >= 20) { 2549 reg = DDI_BUF_CTL(port); 2550 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2551 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2552 } else { 2553 reg = XELPDP_PORT_BUF_CTL1(display, port); 2554 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2555 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2556 } 2557 2558 intel_de_rmw(display, reg, 0, set_bits); 2559 if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { 2560 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2561 port_name(port)); 2562 } 2563 } 2564 2565 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2566 const struct intel_crtc_state *crtc_state) 2567 { 2568 struct intel_display *display = to_intel_display(encoder); 2569 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2570 enum port port = encoder->port; 2571 u32 val = 0; 2572 2573 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2574 2575 if (intel_dp_is_uhbr(crtc_state)) 2576 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2577 else 2578 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2579 2580 if (dig_port->lane_reversal) 2581 val |= XELPDP_PORT_REVERSAL; 2582 2583 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2584 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2585 val); 2586 } 2587 2588 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2589 { 2590 struct intel_display *display = to_intel_display(encoder); 2591 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2592 u32 val; 2593 2594 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2595 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2596 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2597 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2598 } 2599 2600 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2601 struct intel_encoder *encoder, 2602 const struct intel_crtc_state *crtc_state, 2603 const struct drm_connector_state *conn_state) 2604 { 2605 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2606 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2607 bool transparent_mode; 2608 int ret; 2609 2610 intel_dp_set_link_params(intel_dp, 2611 crtc_state->port_clock, 2612 crtc_state->lane_count); 2613 2614 /* 2615 * We only configure what the register value will be here. Actual 2616 * enabling happens during link training farther down. 2617 */ 2618 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2619 2620 /* 2621 * 1. Enable Power Wells 2622 * 2623 * This was handled at the beginning of intel_atomic_commit_tail(), 2624 * before we called down into this function. 2625 */ 2626 2627 /* 2. PMdemand was already set */ 2628 2629 /* 3. Select Thunderbolt */ 2630 mtl_port_buf_ctl_io_selection(encoder); 2631 2632 /* 4. Enable Panel Power if PPS is required */ 2633 intel_pps_on(intel_dp); 2634 2635 /* 5. Enable the port PLL */ 2636 intel_ddi_enable_clock(encoder, crtc_state); 2637 2638 /* 2639 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2640 * Transcoder. 2641 */ 2642 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2643 2644 /* 2645 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2646 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2647 * Transport Select 2648 */ 2649 intel_ddi_config_transcoder_func(encoder, crtc_state); 2650 2651 /* 2652 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2653 */ 2654 intel_ddi_mso_configure(crtc_state); 2655 2656 if (!is_mst) 2657 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2658 2659 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2660 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2661 2662 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2663 if (!is_mst) 2664 intel_dp_sink_enable_decompression(state, 2665 to_intel_connector(conn_state->connector), 2666 crtc_state); 2667 2668 /* 2669 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2670 * in the FEC_CONFIGURATION register to 1 before initiating link 2671 * training 2672 */ 2673 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2674 2675 intel_dp_check_frl_training(intel_dp); 2676 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2677 2678 /* 2679 * 6. The rest of the below are substeps under the bspec's "Enable and 2680 * Train Display Port" step. Note that steps that are specific to 2681 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2682 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2683 * us when active_mst_links==0, so any steps designated for "single 2684 * stream or multi-stream master transcoder" can just be performed 2685 * unconditionally here. 2686 * 2687 * mtl_ddi_prepare_link_retrain() that is called by 2688 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2689 * 6.i and 6.j 2690 * 2691 * 6.k Follow DisplayPort specification training sequence (see notes for 2692 * failure handling) 2693 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2694 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2695 * (timeout after 800 us) 2696 */ 2697 intel_dp_start_link_train(state, intel_dp, crtc_state); 2698 2699 /* 6.n Set DP_TP_CTL link training to Normal */ 2700 if (!is_trans_port_sync_mode(crtc_state)) 2701 intel_dp_stop_link_train(intel_dp, crtc_state); 2702 2703 /* 6.o Configure and enable FEC if needed */ 2704 intel_ddi_enable_fec(encoder, crtc_state); 2705 2706 /* 7.a 128b/132b SST. */ 2707 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2708 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2709 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2710 if (ret < 0) 2711 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2712 } 2713 2714 if (!is_mst) 2715 intel_dsc_dp_pps_write(encoder, crtc_state); 2716 } 2717 2718 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2719 struct intel_encoder *encoder, 2720 const struct intel_crtc_state *crtc_state, 2721 const struct drm_connector_state *conn_state) 2722 { 2723 struct intel_display *display = to_intel_display(encoder); 2724 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2725 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2726 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2727 int ret; 2728 2729 intel_dp_set_link_params(intel_dp, 2730 crtc_state->port_clock, 2731 crtc_state->lane_count); 2732 2733 /* 2734 * We only configure what the register value will be here. Actual 2735 * enabling happens during link training farther down. 2736 */ 2737 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2738 2739 /* 2740 * 1. Enable Power Wells 2741 * 2742 * This was handled at the beginning of intel_atomic_commit_tail(), 2743 * before we called down into this function. 2744 */ 2745 2746 /* 2. Enable Panel Power if PPS is required */ 2747 intel_pps_on(intel_dp); 2748 2749 /* 2750 * 3. For non-TBT Type-C ports, set FIA lane count 2751 * (DFLEXDPSP.DPX4TXLATC) 2752 * 2753 * This was done before tgl_ddi_pre_enable_dp by 2754 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2755 */ 2756 2757 /* 2758 * 4. Enable the port PLL. 2759 * 2760 * The PLL enabling itself was already done before this function by 2761 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2762 * configure the PLL to port mapping here. 2763 */ 2764 intel_ddi_enable_clock(encoder, crtc_state); 2765 2766 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2767 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2768 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2769 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2770 dig_port->ddi_io_power_domain); 2771 } 2772 2773 /* 6. Program DP_MODE */ 2774 icl_program_mg_dp_mode(dig_port, crtc_state); 2775 2776 /* 2777 * 7. The rest of the below are substeps under the bspec's "Enable and 2778 * Train Display Port" step. Note that steps that are specific to 2779 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2780 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2781 * us when active_mst_links==0, so any steps designated for "single 2782 * stream or multi-stream master transcoder" can just be performed 2783 * unconditionally here. 2784 */ 2785 2786 /* 2787 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2788 * Transcoder. 2789 */ 2790 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2791 2792 /* 2793 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2794 * Transport Select 2795 */ 2796 intel_ddi_config_transcoder_func(encoder, crtc_state); 2797 2798 /* 2799 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2800 * selected 2801 * 2802 * This will be handled by the intel_dp_start_link_train() farther 2803 * down this function. 2804 */ 2805 2806 /* 7.e Configure voltage swing and related IO settings */ 2807 encoder->set_signal_levels(encoder, crtc_state); 2808 2809 /* 2810 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2811 * the used lanes of the DDI. 2812 */ 2813 intel_ddi_power_up_lanes(encoder, crtc_state); 2814 2815 /* 2816 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2817 */ 2818 intel_ddi_mso_configure(crtc_state); 2819 2820 if (!is_mst) 2821 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2822 2823 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2824 if (!is_mst) 2825 intel_dp_sink_enable_decompression(state, 2826 to_intel_connector(conn_state->connector), 2827 crtc_state); 2828 /* 2829 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2830 * in the FEC_CONFIGURATION register to 1 before initiating link 2831 * training 2832 */ 2833 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2834 2835 intel_dp_check_frl_training(intel_dp); 2836 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2837 2838 /* 2839 * 7.i Follow DisplayPort specification training sequence (see notes for 2840 * failure handling) 2841 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2842 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2843 * (timeout after 800 us) 2844 */ 2845 intel_dp_start_link_train(state, intel_dp, crtc_state); 2846 2847 /* 7.k Set DP_TP_CTL link training to Normal */ 2848 if (!is_trans_port_sync_mode(crtc_state)) 2849 intel_dp_stop_link_train(intel_dp, crtc_state); 2850 2851 /* 7.l Configure and enable FEC if needed */ 2852 intel_ddi_enable_fec(encoder, crtc_state); 2853 2854 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2855 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2856 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2857 if (ret < 0) 2858 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2859 } 2860 2861 if (!is_mst) 2862 intel_dsc_dp_pps_write(encoder, crtc_state); 2863 } 2864 2865 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2866 struct intel_encoder *encoder, 2867 const struct intel_crtc_state *crtc_state, 2868 const struct drm_connector_state *conn_state) 2869 { 2870 struct intel_display *display = to_intel_display(encoder); 2871 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2872 enum port port = encoder->port; 2873 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2874 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2875 2876 if (DISPLAY_VER(display) < 11) 2877 drm_WARN_ON(display->drm, 2878 is_mst && (port == PORT_A || port == PORT_E)); 2879 else 2880 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2881 2882 intel_dp_set_link_params(intel_dp, 2883 crtc_state->port_clock, 2884 crtc_state->lane_count); 2885 2886 /* 2887 * We only configure what the register value will be here. Actual 2888 * enabling happens during link training farther down. 2889 */ 2890 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2891 2892 intel_pps_on(intel_dp); 2893 2894 intel_ddi_enable_clock(encoder, crtc_state); 2895 2896 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2897 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2898 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2899 dig_port->ddi_io_power_domain); 2900 } 2901 2902 icl_program_mg_dp_mode(dig_port, crtc_state); 2903 2904 if (has_buf_trans_select(display)) 2905 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2906 2907 encoder->set_signal_levels(encoder, crtc_state); 2908 2909 intel_ddi_power_up_lanes(encoder, crtc_state); 2910 2911 if (!is_mst) 2912 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2913 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2914 if (!is_mst) 2915 intel_dp_sink_enable_decompression(state, 2916 to_intel_connector(conn_state->connector), 2917 crtc_state); 2918 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2919 intel_dp_start_link_train(state, intel_dp, crtc_state); 2920 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2921 !is_trans_port_sync_mode(crtc_state)) 2922 intel_dp_stop_link_train(intel_dp, crtc_state); 2923 2924 intel_ddi_enable_fec(encoder, crtc_state); 2925 2926 if (!is_mst) { 2927 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2928 intel_dsc_dp_pps_write(encoder, crtc_state); 2929 } 2930 } 2931 2932 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2933 struct intel_encoder *encoder, 2934 const struct intel_crtc_state *crtc_state, 2935 const struct drm_connector_state *conn_state) 2936 { 2937 struct intel_display *display = to_intel_display(encoder); 2938 2939 if (HAS_DP20(display)) 2940 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2941 crtc_state); 2942 2943 /* Panel replay has to be enabled in sink dpcd before link training. */ 2944 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2945 2946 if (DISPLAY_VER(display) >= 14) 2947 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2948 else if (DISPLAY_VER(display) >= 12) 2949 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2950 else 2951 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2952 2953 /* MST will call a setting of MSA after an allocating of Virtual Channel 2954 * from MST encoder pre_enable callback. 2955 */ 2956 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2957 intel_ddi_set_dp_msa(crtc_state, conn_state); 2958 } 2959 2960 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2961 struct intel_encoder *encoder, 2962 const struct intel_crtc_state *crtc_state, 2963 const struct drm_connector_state *conn_state) 2964 { 2965 struct intel_display *display = to_intel_display(encoder); 2966 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2967 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2968 2969 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2970 intel_ddi_enable_clock(encoder, crtc_state); 2971 2972 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2973 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2974 dig_port->ddi_io_power_domain); 2975 2976 icl_program_mg_dp_mode(dig_port, crtc_state); 2977 2978 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2979 2980 dig_port->set_infoframes(encoder, 2981 crtc_state->has_infoframe, 2982 crtc_state, conn_state); 2983 } 2984 2985 /* 2986 * Note: Also called from the ->pre_enable of the first active MST stream 2987 * encoder on its primary encoder. 2988 * 2989 * When called from DP MST code: 2990 * 2991 * - conn_state will be NULL 2992 * 2993 * - encoder will be the primary encoder (i.e. mst->primary) 2994 * 2995 * - the main connector associated with this port won't be active or linked to a 2996 * crtc 2997 * 2998 * - crtc_state will be the state of the first stream to be activated on this 2999 * port, and it may not be the same stream that will be deactivated last, but 3000 * each stream should have a state that is identical when it comes to the DP 3001 * link parameters. 3002 */ 3003 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3004 struct intel_encoder *encoder, 3005 const struct intel_crtc_state *crtc_state, 3006 const struct drm_connector_state *conn_state) 3007 { 3008 struct intel_display *display = to_intel_display(state); 3009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3010 enum pipe pipe = crtc->pipe; 3011 3012 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3013 3014 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3015 3016 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3017 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3018 conn_state); 3019 } else { 3020 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3021 3022 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3023 conn_state); 3024 3025 /* FIXME precompute everything properly */ 3026 /* FIXME how do we turn infoframes off again? */ 3027 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3028 dig_port->set_infoframes(encoder, 3029 crtc_state->has_infoframe, 3030 crtc_state, conn_state); 3031 } 3032 } 3033 3034 static void 3035 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3036 { 3037 struct intel_display *display = to_intel_display(encoder); 3038 enum port port = encoder->port; 3039 i915_reg_t reg; 3040 u32 clr_bits, wait_bits; 3041 3042 if (DISPLAY_VER(display) < 14) 3043 return; 3044 3045 if (DISPLAY_VER(display) >= 20) { 3046 reg = DDI_BUF_CTL(port); 3047 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3048 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3049 } else { 3050 reg = XELPDP_PORT_BUF_CTL1(display, port); 3051 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3052 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3053 } 3054 3055 intel_de_rmw(display, reg, clr_bits, 0); 3056 if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) 3057 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3058 port_name(port)); 3059 } 3060 3061 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3062 { 3063 struct intel_display *display = to_intel_display(encoder); 3064 enum port port = encoder->port; 3065 3066 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3067 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3068 3069 intel_wait_ddi_buf_active(encoder); 3070 } 3071 3072 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3073 const struct intel_crtc_state *crtc_state) 3074 { 3075 struct intel_display *display = to_intel_display(encoder); 3076 enum port port = encoder->port; 3077 3078 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3079 3080 if (DISPLAY_VER(display) >= 14) 3081 intel_wait_ddi_buf_idle(display, port); 3082 3083 mtl_ddi_disable_d2d(encoder); 3084 3085 if (intel_crtc_has_dp_encoder(crtc_state)) { 3086 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3087 DP_TP_CTL_ENABLE, 0); 3088 } 3089 3090 intel_ddi_disable_fec(encoder, crtc_state); 3091 3092 if (DISPLAY_VER(display) < 14) 3093 intel_wait_ddi_buf_idle(display, port); 3094 3095 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3096 } 3097 3098 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3099 struct intel_encoder *encoder, 3100 const struct intel_crtc_state *old_crtc_state, 3101 const struct drm_connector_state *old_conn_state) 3102 { 3103 struct intel_display *display = to_intel_display(encoder); 3104 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3105 struct intel_dp *intel_dp = &dig_port->dp; 3106 intel_wakeref_t wakeref; 3107 bool is_mst = intel_crtc_has_type(old_crtc_state, 3108 INTEL_OUTPUT_DP_MST); 3109 3110 if (!is_mst) 3111 intel_dp_set_infoframes(encoder, false, 3112 old_crtc_state, old_conn_state); 3113 3114 /* 3115 * Power down sink before disabling the port, otherwise we end 3116 * up getting interrupts from the sink on detecting link loss. 3117 */ 3118 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3119 3120 if (DISPLAY_VER(display) >= 12) { 3121 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3122 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3123 3124 intel_de_rmw(display, 3125 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3126 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3127 0); 3128 } 3129 } else { 3130 if (!is_mst) 3131 intel_ddi_disable_transcoder_clock(old_crtc_state); 3132 } 3133 3134 intel_ddi_buf_disable(encoder, old_crtc_state); 3135 3136 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3137 3138 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3139 3140 /* 3141 * From TGL spec: "If single stream or multi-stream master transcoder: 3142 * Configure Transcoder Clock select to direct no clock to the 3143 * transcoder" 3144 */ 3145 if (DISPLAY_VER(display) >= 12) 3146 intel_ddi_disable_transcoder_clock(old_crtc_state); 3147 3148 intel_pps_vdd_on(intel_dp); 3149 intel_pps_off(intel_dp); 3150 3151 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3152 3153 if (wakeref) 3154 intel_display_power_put(display, 3155 dig_port->ddi_io_power_domain, 3156 wakeref); 3157 3158 intel_ddi_disable_clock(encoder); 3159 3160 /* De-select Thunderbolt */ 3161 if (DISPLAY_VER(display) >= 14) 3162 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3163 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3164 } 3165 3166 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3167 struct intel_encoder *encoder, 3168 const struct intel_crtc_state *old_crtc_state, 3169 const struct drm_connector_state *old_conn_state) 3170 { 3171 struct intel_display *display = to_intel_display(encoder); 3172 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3173 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3174 intel_wakeref_t wakeref; 3175 3176 dig_port->set_infoframes(encoder, false, 3177 old_crtc_state, old_conn_state); 3178 3179 if (DISPLAY_VER(display) < 12) 3180 intel_ddi_disable_transcoder_clock(old_crtc_state); 3181 3182 intel_ddi_buf_disable(encoder, old_crtc_state); 3183 3184 if (DISPLAY_VER(display) >= 12) 3185 intel_ddi_disable_transcoder_clock(old_crtc_state); 3186 3187 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3188 if (wakeref) 3189 intel_display_power_put(display, 3190 dig_port->ddi_io_power_domain, 3191 wakeref); 3192 3193 intel_ddi_disable_clock(encoder); 3194 3195 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3196 } 3197 3198 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3199 struct intel_encoder *encoder, 3200 const struct intel_crtc_state *old_crtc_state, 3201 const struct drm_connector_state *old_conn_state) 3202 { 3203 struct intel_display *display = to_intel_display(encoder); 3204 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3205 struct intel_crtc *pipe_crtc; 3206 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3207 int i; 3208 3209 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3210 const struct intel_crtc_state *old_pipe_crtc_state = 3211 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3212 3213 intel_crtc_vblank_off(old_pipe_crtc_state); 3214 } 3215 3216 intel_disable_transcoder(old_crtc_state); 3217 3218 /* 128b/132b SST */ 3219 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3220 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3221 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3222 3223 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3224 3225 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3226 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3227 3228 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3229 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3230 } 3231 3232 intel_vrr_transcoder_disable(old_crtc_state); 3233 3234 intel_ddi_disable_transcoder_func(old_crtc_state); 3235 3236 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3237 const struct intel_crtc_state *old_pipe_crtc_state = 3238 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3239 3240 intel_dsc_disable(old_pipe_crtc_state); 3241 3242 if (DISPLAY_VER(display) >= 9) 3243 skl_scaler_disable(old_pipe_crtc_state); 3244 else 3245 ilk_pfit_disable(old_pipe_crtc_state); 3246 } 3247 } 3248 3249 /* 3250 * Note: Also called from the ->post_disable of the last active MST stream 3251 * encoder on its primary encoder. See also the comment for 3252 * intel_ddi_pre_enable(). 3253 */ 3254 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3255 struct intel_encoder *encoder, 3256 const struct intel_crtc_state *old_crtc_state, 3257 const struct drm_connector_state *old_conn_state) 3258 { 3259 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3260 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3261 old_conn_state); 3262 3263 /* 3264 * When called from DP MST code: 3265 * - old_conn_state will be NULL 3266 * - encoder will be the main encoder (ie. mst->primary) 3267 * - the main connector associated with this port 3268 * won't be active or linked to a crtc 3269 * - old_crtc_state will be the state of the last stream to 3270 * be deactivated on this port, and it may not be the same 3271 * stream that was activated last, but each stream 3272 * should have a state that is identical when it comes to 3273 * the DP link parameters 3274 */ 3275 3276 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3277 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3278 old_conn_state); 3279 else 3280 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3281 old_conn_state); 3282 } 3283 3284 /* 3285 * Note: Also called from the ->post_pll_disable of the last active MST stream 3286 * encoder on its primary encoder. See also the comment for 3287 * intel_ddi_pre_enable(). 3288 */ 3289 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3290 struct intel_encoder *encoder, 3291 const struct intel_crtc_state *old_crtc_state, 3292 const struct drm_connector_state *old_conn_state) 3293 { 3294 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3295 3296 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3297 3298 if (intel_encoder_is_tc(encoder)) 3299 intel_tc_port_put_link(dig_port); 3300 } 3301 3302 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3303 struct intel_encoder *encoder, 3304 const struct intel_crtc_state *crtc_state) 3305 { 3306 const struct drm_connector_state *conn_state; 3307 struct drm_connector *conn; 3308 int i; 3309 3310 if (!crtc_state->sync_mode_slaves_mask) 3311 return; 3312 3313 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3314 struct intel_encoder *slave_encoder = 3315 to_intel_encoder(conn_state->best_encoder); 3316 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3317 const struct intel_crtc_state *slave_crtc_state; 3318 3319 if (!slave_crtc) 3320 continue; 3321 3322 slave_crtc_state = 3323 intel_atomic_get_new_crtc_state(state, slave_crtc); 3324 3325 if (slave_crtc_state->master_transcoder != 3326 crtc_state->cpu_transcoder) 3327 continue; 3328 3329 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3330 slave_crtc_state); 3331 } 3332 3333 usleep_range(200, 400); 3334 3335 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3336 crtc_state); 3337 } 3338 3339 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3340 struct intel_encoder *encoder, 3341 const struct intel_crtc_state *crtc_state, 3342 const struct drm_connector_state *conn_state) 3343 { 3344 struct intel_display *display = to_intel_display(encoder); 3345 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3346 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3347 enum port port = encoder->port; 3348 3349 if (port == PORT_A && DISPLAY_VER(display) < 9) 3350 intel_dp_stop_link_train(intel_dp, crtc_state); 3351 3352 drm_connector_update_privacy_screen(conn_state); 3353 intel_edp_backlight_on(crtc_state, conn_state); 3354 3355 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3356 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3357 3358 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3359 } 3360 3361 static i915_reg_t 3362 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3363 { 3364 static const enum transcoder trans[] = { 3365 [PORT_A] = TRANSCODER_EDP, 3366 [PORT_B] = TRANSCODER_A, 3367 [PORT_C] = TRANSCODER_B, 3368 [PORT_D] = TRANSCODER_C, 3369 [PORT_E] = TRANSCODER_A, 3370 }; 3371 3372 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3373 3374 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3375 port = PORT_A; 3376 3377 return CHICKEN_TRANS(display, trans[port]); 3378 } 3379 3380 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3381 struct intel_encoder *encoder, 3382 const struct intel_crtc_state *crtc_state, 3383 const struct drm_connector_state *conn_state) 3384 { 3385 struct intel_display *display = to_intel_display(encoder); 3386 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3387 struct drm_connector *connector = conn_state->connector; 3388 enum port port = encoder->port; 3389 u32 buf_ctl = 0; 3390 3391 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3392 crtc_state->hdmi_high_tmds_clock_ratio, 3393 crtc_state->hdmi_scrambling)) 3394 drm_dbg_kms(display->drm, 3395 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3396 connector->base.id, connector->name); 3397 3398 if (has_buf_trans_select(display)) 3399 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3400 3401 /* e. Enable D2D Link for C10/C20 Phy */ 3402 mtl_ddi_enable_d2d(encoder); 3403 3404 encoder->set_signal_levels(encoder, crtc_state); 3405 3406 /* Display WA #1143: skl,kbl,cfl */ 3407 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3408 /* 3409 * For some reason these chicken bits have been 3410 * stuffed into a transcoder register, event though 3411 * the bits affect a specific DDI port rather than 3412 * a specific transcoder. 3413 */ 3414 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3415 u32 val; 3416 3417 val = intel_de_read(display, reg); 3418 3419 if (port == PORT_E) 3420 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3421 DDIE_TRAINING_OVERRIDE_VALUE; 3422 else 3423 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3424 DDI_TRAINING_OVERRIDE_VALUE; 3425 3426 intel_de_write(display, reg, val); 3427 intel_de_posting_read(display, reg); 3428 3429 udelay(1); 3430 3431 if (port == PORT_E) 3432 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3433 DDIE_TRAINING_OVERRIDE_VALUE); 3434 else 3435 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3436 DDI_TRAINING_OVERRIDE_VALUE); 3437 3438 intel_de_write(display, reg, val); 3439 } 3440 3441 intel_ddi_power_up_lanes(encoder, crtc_state); 3442 3443 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3444 * are ignored so nothing special needs to be done besides 3445 * enabling the port. 3446 * 3447 * On ADL_P the PHY link rate and lane count must be programmed but 3448 * these are both 0 for HDMI. 3449 * 3450 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3451 * is filled with lane count, already set in the crtc_state. 3452 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3453 */ 3454 if (dig_port->lane_reversal) 3455 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3456 if (dig_port->ddi_a_4_lanes) 3457 buf_ctl |= DDI_A_4_LANES; 3458 3459 if (DISPLAY_VER(display) >= 14) { 3460 u32 port_buf = 0; 3461 3462 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3463 3464 if (dig_port->lane_reversal) 3465 port_buf |= XELPDP_PORT_REVERSAL; 3466 3467 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3468 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3469 3470 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3471 3472 if (DISPLAY_VER(display) >= 20) 3473 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3474 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3475 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3476 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3477 } 3478 3479 intel_ddi_buf_enable(encoder, buf_ctl); 3480 } 3481 3482 static void intel_ddi_enable(struct intel_atomic_state *state, 3483 struct intel_encoder *encoder, 3484 const struct intel_crtc_state *crtc_state, 3485 const struct drm_connector_state *conn_state) 3486 { 3487 struct intel_display *display = to_intel_display(encoder); 3488 struct intel_crtc *pipe_crtc; 3489 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3490 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3491 int i; 3492 3493 /* 128b/132b SST */ 3494 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3495 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3496 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3497 3498 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3499 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3500 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3501 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3502 } 3503 3504 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3505 3506 intel_vrr_transcoder_enable(crtc_state); 3507 3508 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3509 intel_audio_sdp_split_update(crtc_state); 3510 3511 /* 128b/132b SST */ 3512 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3513 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3514 3515 intel_ddi_clear_act_sent(encoder, crtc_state); 3516 3517 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3518 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3519 3520 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3521 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3522 } 3523 3524 intel_enable_transcoder(crtc_state); 3525 3526 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3527 3528 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3529 const struct intel_crtc_state *pipe_crtc_state = 3530 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3531 3532 intel_crtc_vblank_on(pipe_crtc_state); 3533 } 3534 3535 if (is_hdmi) 3536 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3537 else 3538 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3539 3540 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3541 3542 } 3543 3544 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3545 struct intel_encoder *encoder, 3546 const struct intel_crtc_state *old_crtc_state, 3547 const struct drm_connector_state *old_conn_state) 3548 { 3549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3550 struct intel_connector *connector = 3551 to_intel_connector(old_conn_state->connector); 3552 3553 intel_dp->link.active = false; 3554 3555 intel_psr_disable(intel_dp, old_crtc_state); 3556 intel_edp_backlight_off(old_conn_state); 3557 /* Disable the decompression in DP Sink */ 3558 intel_dp_sink_disable_decompression(state, 3559 connector, old_crtc_state); 3560 /* Disable Ignore_MSA bit in DP Sink */ 3561 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3562 false); 3563 } 3564 3565 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3566 struct intel_encoder *encoder, 3567 const struct intel_crtc_state *old_crtc_state, 3568 const struct drm_connector_state *old_conn_state) 3569 { 3570 struct intel_display *display = to_intel_display(encoder); 3571 struct drm_connector *connector = old_conn_state->connector; 3572 3573 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3574 false, false)) 3575 drm_dbg_kms(display->drm, 3576 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3577 connector->base.id, connector->name); 3578 } 3579 3580 static void intel_ddi_disable(struct intel_atomic_state *state, 3581 struct intel_encoder *encoder, 3582 const struct intel_crtc_state *old_crtc_state, 3583 const struct drm_connector_state *old_conn_state) 3584 { 3585 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3586 3587 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3588 3589 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3590 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3591 old_conn_state); 3592 else 3593 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3594 old_conn_state); 3595 } 3596 3597 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3598 struct intel_encoder *encoder, 3599 const struct intel_crtc_state *crtc_state, 3600 const struct drm_connector_state *conn_state) 3601 { 3602 intel_ddi_set_dp_msa(crtc_state, conn_state); 3603 3604 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3605 3606 intel_backlight_update(state, encoder, crtc_state, conn_state); 3607 drm_connector_update_privacy_screen(conn_state); 3608 } 3609 3610 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3611 const struct intel_crtc_state *crtc_state, 3612 const struct drm_connector_state *conn_state) 3613 { 3614 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3615 } 3616 3617 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3618 struct intel_encoder *encoder, 3619 const struct intel_crtc_state *crtc_state, 3620 const struct drm_connector_state *conn_state) 3621 { 3622 3623 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3624 !intel_encoder_is_mst(encoder)) 3625 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3626 conn_state); 3627 3628 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3629 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3630 conn_state); 3631 3632 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3633 } 3634 3635 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3636 struct intel_encoder *encoder, 3637 struct intel_crtc *crtc) 3638 { 3639 struct intel_display *display = to_intel_display(encoder); 3640 const struct intel_crtc_state *crtc_state = 3641 intel_atomic_get_new_crtc_state(state, crtc); 3642 struct intel_crtc *pipe_crtc; 3643 3644 /* FIXME: Add MTL pll_mgr */ 3645 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3646 return; 3647 3648 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3649 intel_crtc_joined_pipe_mask(crtc_state)) 3650 intel_update_active_dpll(state, pipe_crtc, encoder); 3651 } 3652 3653 /* 3654 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3655 * encoder on its primary encoder. See also the comment for 3656 * intel_ddi_pre_enable(). 3657 */ 3658 static void 3659 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3660 struct intel_encoder *encoder, 3661 const struct intel_crtc_state *crtc_state, 3662 const struct drm_connector_state *conn_state) 3663 { 3664 struct intel_display *display = to_intel_display(encoder); 3665 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3666 bool is_tc_port = intel_encoder_is_tc(encoder); 3667 3668 if (is_tc_port) { 3669 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3670 3671 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3672 intel_ddi_update_active_dpll(state, encoder, crtc); 3673 } 3674 3675 main_link_aux_power_domain_get(dig_port, crtc_state); 3676 3677 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3678 /* 3679 * Program the lane count for static/dynamic connections on 3680 * Type-C ports. Skip this step for TBT. 3681 */ 3682 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3683 else if (display->platform.geminilake || display->platform.broxton) 3684 bxt_dpio_phy_set_lane_optim_mask(encoder, 3685 crtc_state->lane_lat_optim_mask); 3686 } 3687 3688 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3689 { 3690 struct intel_display *display = to_intel_display(encoder); 3691 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3692 int ln; 3693 3694 for (ln = 0; ln < 2; ln++) 3695 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3696 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3697 } 3698 3699 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3700 const struct intel_crtc_state *crtc_state) 3701 { 3702 struct intel_display *display = to_intel_display(crtc_state); 3703 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3704 struct intel_encoder *encoder = &dig_port->base; 3705 u32 dp_tp_ctl; 3706 3707 /* 3708 * TODO: To train with only a different voltage swing entry is not 3709 * necessary disable and enable port 3710 */ 3711 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3712 3713 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3714 3715 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3716 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3717 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3718 intel_dp_is_uhbr(crtc_state)) { 3719 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3720 } else { 3721 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3722 if (crtc_state->enhanced_framing) 3723 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3724 } 3725 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3726 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3727 3728 /* 6.f Enable D2D Link */ 3729 mtl_ddi_enable_d2d(encoder); 3730 3731 /* 6.g Configure voltage swing and related IO settings */ 3732 encoder->set_signal_levels(encoder, crtc_state); 3733 3734 /* 6.h Configure PORT_BUF_CTL1 */ 3735 mtl_port_buf_ctl_program(encoder, crtc_state); 3736 3737 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3738 if (DISPLAY_VER(display) >= 20) 3739 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3740 3741 intel_ddi_buf_enable(encoder, intel_dp->DP); 3742 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3743 } 3744 3745 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3746 const struct intel_crtc_state *crtc_state) 3747 { 3748 struct intel_display *display = to_intel_display(intel_dp); 3749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3750 struct intel_encoder *encoder = &dig_port->base; 3751 u32 dp_tp_ctl; 3752 3753 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3754 3755 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3756 3757 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3758 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3759 intel_dp_is_uhbr(crtc_state)) { 3760 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3761 } else { 3762 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3763 if (crtc_state->enhanced_framing) 3764 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3765 } 3766 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3767 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3768 3769 if (display->platform.alderlake_p && 3770 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3771 adlp_tbt_to_dp_alt_switch_wa(encoder); 3772 3773 intel_ddi_buf_enable(encoder, intel_dp->DP); 3774 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3775 } 3776 3777 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3778 const struct intel_crtc_state *crtc_state, 3779 u8 dp_train_pat) 3780 { 3781 struct intel_display *display = to_intel_display(intel_dp); 3782 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3783 u32 temp; 3784 3785 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3786 3787 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3788 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3789 case DP_TRAINING_PATTERN_DISABLE: 3790 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3791 break; 3792 case DP_TRAINING_PATTERN_1: 3793 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3794 break; 3795 case DP_TRAINING_PATTERN_2: 3796 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3797 break; 3798 case DP_TRAINING_PATTERN_3: 3799 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3800 break; 3801 case DP_TRAINING_PATTERN_4: 3802 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3803 break; 3804 } 3805 3806 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3807 } 3808 3809 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3810 const struct intel_crtc_state *crtc_state) 3811 { 3812 struct intel_display *display = to_intel_display(intel_dp); 3813 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3814 enum port port = encoder->port; 3815 3816 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3817 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3818 3819 /* 3820 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3821 * reason we need to set idle transmission mode is to work around a HW 3822 * issue where we enable the pipe while not in idle link-training mode. 3823 * In this case there is requirement to wait for a minimum number of 3824 * idle patterns to be sent. 3825 */ 3826 if (port == PORT_A && DISPLAY_VER(display) < 12) 3827 return; 3828 3829 if (intel_de_wait_for_set(display, 3830 dp_tp_status_reg(encoder, crtc_state), 3831 DP_TP_STATUS_IDLE_DONE, 2)) 3832 drm_err(display->drm, 3833 "Timed out waiting for DP idle patterns\n"); 3834 } 3835 3836 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3837 enum transcoder cpu_transcoder) 3838 { 3839 if (cpu_transcoder == TRANSCODER_EDP) 3840 return false; 3841 3842 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3843 return false; 3844 3845 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3846 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3847 } 3848 3849 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3850 { 3851 if (crtc_state->port_clock > 594000) 3852 return 2; 3853 else 3854 return 0; 3855 } 3856 3857 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3858 { 3859 if (crtc_state->port_clock > 594000) 3860 return 3; 3861 else 3862 return 0; 3863 } 3864 3865 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3866 { 3867 if (crtc_state->port_clock > 594000) 3868 return 1; 3869 else 3870 return 0; 3871 } 3872 3873 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3874 { 3875 struct intel_display *display = to_intel_display(crtc_state); 3876 3877 if (DISPLAY_VER(display) >= 14) 3878 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3879 else if (DISPLAY_VER(display) >= 12) 3880 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3881 else if (display->platform.jasperlake || display->platform.elkhartlake) 3882 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3883 else if (DISPLAY_VER(display) >= 11) 3884 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3885 } 3886 3887 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3888 enum transcoder cpu_transcoder) 3889 { 3890 u32 master_select; 3891 3892 if (DISPLAY_VER(display) >= 11) { 3893 u32 ctl2 = intel_de_read(display, 3894 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3895 3896 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3897 return INVALID_TRANSCODER; 3898 3899 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3900 } else { 3901 u32 ctl = intel_de_read(display, 3902 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3903 3904 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3905 return INVALID_TRANSCODER; 3906 3907 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3908 } 3909 3910 if (master_select == 0) 3911 return TRANSCODER_EDP; 3912 else 3913 return master_select - 1; 3914 } 3915 3916 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3917 { 3918 struct intel_display *display = to_intel_display(crtc_state); 3919 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3920 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3921 enum transcoder cpu_transcoder; 3922 3923 crtc_state->master_transcoder = 3924 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3925 3926 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3927 enum intel_display_power_domain power_domain; 3928 intel_wakeref_t trans_wakeref; 3929 3930 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3931 trans_wakeref = intel_display_power_get_if_enabled(display, 3932 power_domain); 3933 3934 if (!trans_wakeref) 3935 continue; 3936 3937 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3938 crtc_state->cpu_transcoder) 3939 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3940 3941 intel_display_power_put(display, power_domain, trans_wakeref); 3942 } 3943 3944 drm_WARN_ON(display->drm, 3945 crtc_state->master_transcoder != INVALID_TRANSCODER && 3946 crtc_state->sync_mode_slaves_mask); 3947 } 3948 3949 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3950 struct intel_crtc_state *crtc_state, 3951 u32 ddi_func_ctl) 3952 { 3953 struct intel_display *display = to_intel_display(encoder); 3954 3955 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3956 if (DISPLAY_VER(display) >= 14) 3957 crtc_state->lane_count = 3958 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3959 else 3960 crtc_state->lane_count = 4; 3961 } 3962 3963 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3964 struct intel_crtc_state *crtc_state, 3965 u32 ddi_func_ctl) 3966 { 3967 crtc_state->has_hdmi_sink = true; 3968 3969 crtc_state->infoframes.enable |= 3970 intel_hdmi_infoframes_enabled(encoder, crtc_state); 3971 3972 if (crtc_state->infoframes.enable) 3973 crtc_state->has_infoframe = true; 3974 3975 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 3976 crtc_state->hdmi_scrambling = true; 3977 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3978 crtc_state->hdmi_high_tmds_clock_ratio = true; 3979 3980 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 3981 } 3982 3983 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 3984 struct intel_crtc_state *crtc_state, 3985 u32 ddi_func_ctl) 3986 { 3987 struct intel_display *display = to_intel_display(encoder); 3988 3989 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3990 crtc_state->enhanced_framing = 3991 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 3992 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3993 } 3994 3995 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 3996 struct intel_crtc_state *crtc_state, 3997 u32 ddi_func_ctl) 3998 { 3999 struct intel_display *display = to_intel_display(encoder); 4000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4001 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4002 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4003 4004 if (encoder->type == INTEL_OUTPUT_EDP) 4005 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4006 else 4007 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4008 crtc_state->lane_count = 4009 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4010 4011 if (DISPLAY_VER(display) >= 12 && 4012 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4013 crtc_state->mst_master_transcoder = 4014 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4015 4016 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4017 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4018 4019 crtc_state->enhanced_framing = 4020 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4021 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4022 4023 if (DISPLAY_VER(display) >= 11) 4024 crtc_state->fec_enable = 4025 intel_de_read(display, 4026 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4027 4028 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4029 crtc_state->infoframes.enable |= 4030 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4031 else 4032 crtc_state->infoframes.enable |= 4033 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4034 } 4035 4036 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4037 struct intel_crtc_state *crtc_state, 4038 u32 ddi_func_ctl) 4039 { 4040 struct intel_display *display = to_intel_display(encoder); 4041 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4042 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4043 4044 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4045 crtc_state->lane_count = 4046 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4047 4048 if (DISPLAY_VER(display) >= 12) 4049 crtc_state->mst_master_transcoder = 4050 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4051 4052 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4053 4054 if (DISPLAY_VER(display) >= 11) 4055 crtc_state->fec_enable = 4056 intel_de_read(display, 4057 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4058 4059 crtc_state->infoframes.enable |= 4060 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4061 } 4062 4063 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4064 struct intel_crtc_state *pipe_config) 4065 { 4066 struct intel_display *display = to_intel_display(encoder); 4067 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4068 u32 ddi_func_ctl, ddi_mode, flags = 0; 4069 4070 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4071 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4072 flags |= DRM_MODE_FLAG_PHSYNC; 4073 else 4074 flags |= DRM_MODE_FLAG_NHSYNC; 4075 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4076 flags |= DRM_MODE_FLAG_PVSYNC; 4077 else 4078 flags |= DRM_MODE_FLAG_NVSYNC; 4079 4080 pipe_config->hw.adjusted_mode.flags |= flags; 4081 4082 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4083 case TRANS_DDI_BPC_6: 4084 pipe_config->pipe_bpp = 18; 4085 break; 4086 case TRANS_DDI_BPC_8: 4087 pipe_config->pipe_bpp = 24; 4088 break; 4089 case TRANS_DDI_BPC_10: 4090 pipe_config->pipe_bpp = 30; 4091 break; 4092 case TRANS_DDI_BPC_12: 4093 pipe_config->pipe_bpp = 36; 4094 break; 4095 default: 4096 break; 4097 } 4098 4099 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4100 4101 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4102 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4103 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4104 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4105 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4106 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4107 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4108 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4109 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4110 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4111 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4112 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4113 4114 /* 4115 * If this is true, we know we're being called from mst stream 4116 * encoder's ->get_config(). 4117 */ 4118 if (intel_dp_mst_active_streams(intel_dp)) 4119 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4120 else 4121 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4122 } 4123 } 4124 4125 /* 4126 * Note: Also called from the ->get_config of the MST stream encoders on their 4127 * primary encoder, via the platform specific hooks here. See also the comment 4128 * for intel_ddi_pre_enable(). 4129 */ 4130 static void intel_ddi_get_config(struct intel_encoder *encoder, 4131 struct intel_crtc_state *pipe_config) 4132 { 4133 struct intel_display *display = to_intel_display(encoder); 4134 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4135 4136 /* XXX: DSI transcoder paranoia */ 4137 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4138 return; 4139 4140 intel_ddi_read_func_ctl(encoder, pipe_config); 4141 4142 intel_ddi_mso_get_config(encoder, pipe_config); 4143 4144 pipe_config->has_audio = 4145 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4146 4147 if (encoder->type == INTEL_OUTPUT_EDP) 4148 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4149 4150 ddi_dotclock_get(pipe_config); 4151 4152 if (display->platform.geminilake || display->platform.broxton) 4153 pipe_config->lane_lat_optim_mask = 4154 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4155 4156 intel_ddi_compute_min_voltage_level(pipe_config); 4157 4158 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4159 4160 intel_read_infoframe(encoder, pipe_config, 4161 HDMI_INFOFRAME_TYPE_AVI, 4162 &pipe_config->infoframes.avi); 4163 intel_read_infoframe(encoder, pipe_config, 4164 HDMI_INFOFRAME_TYPE_SPD, 4165 &pipe_config->infoframes.spd); 4166 intel_read_infoframe(encoder, pipe_config, 4167 HDMI_INFOFRAME_TYPE_VENDOR, 4168 &pipe_config->infoframes.hdmi); 4169 intel_read_infoframe(encoder, pipe_config, 4170 HDMI_INFOFRAME_TYPE_DRM, 4171 &pipe_config->infoframes.drm); 4172 4173 if (DISPLAY_VER(display) >= 8) 4174 bdw_get_trans_port_sync_config(pipe_config); 4175 4176 intel_psr_get_config(encoder, pipe_config); 4177 4178 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4179 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4180 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4181 4182 intel_audio_codec_get_config(encoder, pipe_config); 4183 } 4184 4185 void intel_ddi_get_clock(struct intel_encoder *encoder, 4186 struct intel_crtc_state *crtc_state, 4187 struct intel_shared_dpll *pll) 4188 { 4189 struct intel_display *display = to_intel_display(encoder); 4190 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4191 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4192 bool pll_active; 4193 4194 if (drm_WARN_ON(display->drm, !pll)) 4195 return; 4196 4197 port_dpll->pll = pll; 4198 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4199 drm_WARN_ON(display->drm, !pll_active); 4200 4201 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4202 4203 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, 4204 &crtc_state->dpll_hw_state); 4205 } 4206 4207 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4208 struct intel_crtc_state *crtc_state) 4209 { 4210 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4211 4212 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4213 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4214 else 4215 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4216 4217 intel_ddi_get_config(encoder, crtc_state); 4218 } 4219 4220 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4221 struct intel_crtc_state *crtc_state) 4222 { 4223 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4224 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4225 4226 intel_ddi_get_config(encoder, crtc_state); 4227 } 4228 4229 static void adls_ddi_get_config(struct intel_encoder *encoder, 4230 struct intel_crtc_state *crtc_state) 4231 { 4232 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4233 intel_ddi_get_config(encoder, crtc_state); 4234 } 4235 4236 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4237 struct intel_crtc_state *crtc_state) 4238 { 4239 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4240 intel_ddi_get_config(encoder, crtc_state); 4241 } 4242 4243 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4244 struct intel_crtc_state *crtc_state) 4245 { 4246 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4247 intel_ddi_get_config(encoder, crtc_state); 4248 } 4249 4250 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4251 struct intel_crtc_state *crtc_state) 4252 { 4253 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4254 intel_ddi_get_config(encoder, crtc_state); 4255 } 4256 4257 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4258 { 4259 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4260 } 4261 4262 static enum icl_port_dpll_id 4263 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4264 const struct intel_crtc_state *crtc_state) 4265 { 4266 struct intel_display *display = to_intel_display(encoder); 4267 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4268 4269 if (drm_WARN_ON(display->drm, !pll)) 4270 return ICL_PORT_DPLL_DEFAULT; 4271 4272 if (icl_ddi_tc_pll_is_tbt(pll)) 4273 return ICL_PORT_DPLL_DEFAULT; 4274 else 4275 return ICL_PORT_DPLL_MG_PHY; 4276 } 4277 4278 enum icl_port_dpll_id 4279 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4280 const struct intel_crtc_state *crtc_state) 4281 { 4282 if (!encoder->port_pll_type) 4283 return ICL_PORT_DPLL_DEFAULT; 4284 4285 return encoder->port_pll_type(encoder, crtc_state); 4286 } 4287 4288 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4289 struct intel_crtc_state *crtc_state, 4290 struct intel_shared_dpll *pll) 4291 { 4292 struct intel_display *display = to_intel_display(encoder); 4293 enum icl_port_dpll_id port_dpll_id; 4294 struct icl_port_dpll *port_dpll; 4295 bool pll_active; 4296 4297 if (drm_WARN_ON(display->drm, !pll)) 4298 return; 4299 4300 if (icl_ddi_tc_pll_is_tbt(pll)) 4301 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4302 else 4303 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4304 4305 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4306 4307 port_dpll->pll = pll; 4308 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4309 drm_WARN_ON(display->drm, !pll_active); 4310 4311 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4312 4313 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4314 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4315 else 4316 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, 4317 &crtc_state->dpll_hw_state); 4318 } 4319 4320 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4321 struct intel_crtc_state *crtc_state) 4322 { 4323 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4324 intel_ddi_get_config(encoder, crtc_state); 4325 } 4326 4327 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4328 struct intel_crtc_state *crtc_state) 4329 { 4330 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4331 intel_ddi_get_config(encoder, crtc_state); 4332 } 4333 4334 static void skl_ddi_get_config(struct intel_encoder *encoder, 4335 struct intel_crtc_state *crtc_state) 4336 { 4337 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4338 intel_ddi_get_config(encoder, crtc_state); 4339 } 4340 4341 void hsw_ddi_get_config(struct intel_encoder *encoder, 4342 struct intel_crtc_state *crtc_state) 4343 { 4344 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4345 intel_ddi_get_config(encoder, crtc_state); 4346 } 4347 4348 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4349 const struct intel_crtc_state *crtc_state) 4350 { 4351 if (intel_encoder_is_tc(encoder)) 4352 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4353 crtc_state); 4354 4355 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4356 (!crtc_state && intel_encoder_is_dp(encoder))) 4357 intel_dp_sync_state(encoder, crtc_state); 4358 } 4359 4360 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4361 struct intel_crtc_state *crtc_state) 4362 { 4363 struct intel_display *display = to_intel_display(encoder); 4364 bool fastset = true; 4365 4366 if (intel_encoder_is_tc(encoder)) { 4367 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4368 encoder->base.base.id, encoder->base.name); 4369 crtc_state->uapi.mode_changed = true; 4370 fastset = false; 4371 } 4372 4373 if (intel_crtc_has_dp_encoder(crtc_state) && 4374 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4375 fastset = false; 4376 4377 return fastset; 4378 } 4379 4380 static enum intel_output_type 4381 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4382 struct intel_crtc_state *crtc_state, 4383 struct drm_connector_state *conn_state) 4384 { 4385 switch (conn_state->connector->connector_type) { 4386 case DRM_MODE_CONNECTOR_HDMIA: 4387 return INTEL_OUTPUT_HDMI; 4388 case DRM_MODE_CONNECTOR_eDP: 4389 return INTEL_OUTPUT_EDP; 4390 case DRM_MODE_CONNECTOR_DisplayPort: 4391 return INTEL_OUTPUT_DP; 4392 default: 4393 MISSING_CASE(conn_state->connector->connector_type); 4394 return INTEL_OUTPUT_UNUSED; 4395 } 4396 } 4397 4398 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4399 struct intel_crtc_state *pipe_config, 4400 struct drm_connector_state *conn_state) 4401 { 4402 struct intel_display *display = to_intel_display(encoder); 4403 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4404 enum port port = encoder->port; 4405 int ret; 4406 4407 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4408 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4409 4410 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4411 pipe_config->has_hdmi_sink = 4412 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4413 4414 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4415 } else { 4416 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4417 } 4418 4419 if (ret) 4420 return ret; 4421 4422 if (display->platform.haswell && crtc->pipe == PIPE_A && 4423 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4424 pipe_config->pch_pfit.force_thru = 4425 pipe_config->pch_pfit.enabled || 4426 pipe_config->crc_enabled; 4427 4428 if (display->platform.geminilake || display->platform.broxton) 4429 pipe_config->lane_lat_optim_mask = 4430 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4431 4432 intel_ddi_compute_min_voltage_level(pipe_config); 4433 4434 return 0; 4435 } 4436 4437 static bool mode_equal(const struct drm_display_mode *mode1, 4438 const struct drm_display_mode *mode2) 4439 { 4440 return drm_mode_match(mode1, mode2, 4441 DRM_MODE_MATCH_TIMINGS | 4442 DRM_MODE_MATCH_FLAGS | 4443 DRM_MODE_MATCH_3D_FLAGS) && 4444 mode1->clock == mode2->clock; /* we want an exact match */ 4445 } 4446 4447 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4448 const struct intel_link_m_n *m_n_2) 4449 { 4450 return m_n_1->tu == m_n_2->tu && 4451 m_n_1->data_m == m_n_2->data_m && 4452 m_n_1->data_n == m_n_2->data_n && 4453 m_n_1->link_m == m_n_2->link_m && 4454 m_n_1->link_n == m_n_2->link_n; 4455 } 4456 4457 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4458 const struct intel_crtc_state *crtc_state2) 4459 { 4460 /* 4461 * FIXME the modeset sequence is currently wrong and 4462 * can't deal with joiner + port sync at the same time. 4463 */ 4464 return crtc_state1->hw.active && crtc_state2->hw.active && 4465 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4466 crtc_state1->output_types == crtc_state2->output_types && 4467 crtc_state1->output_format == crtc_state2->output_format && 4468 crtc_state1->lane_count == crtc_state2->lane_count && 4469 crtc_state1->port_clock == crtc_state2->port_clock && 4470 mode_equal(&crtc_state1->hw.adjusted_mode, 4471 &crtc_state2->hw.adjusted_mode) && 4472 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4473 } 4474 4475 static u8 4476 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4477 int tile_group_id) 4478 { 4479 struct intel_display *display = to_intel_display(ref_crtc_state); 4480 struct drm_connector *connector; 4481 const struct drm_connector_state *conn_state; 4482 struct intel_atomic_state *state = 4483 to_intel_atomic_state(ref_crtc_state->uapi.state); 4484 u8 transcoders = 0; 4485 int i; 4486 4487 /* 4488 * We don't enable port sync on BDW due to missing w/as and 4489 * due to not having adjusted the modeset sequence appropriately. 4490 */ 4491 if (DISPLAY_VER(display) < 9) 4492 return 0; 4493 4494 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4495 return 0; 4496 4497 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4498 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4499 const struct intel_crtc_state *crtc_state; 4500 4501 if (!crtc) 4502 continue; 4503 4504 if (!connector->has_tile || 4505 connector->tile_group->id != 4506 tile_group_id) 4507 continue; 4508 crtc_state = intel_atomic_get_new_crtc_state(state, 4509 crtc); 4510 if (!crtcs_port_sync_compatible(ref_crtc_state, 4511 crtc_state)) 4512 continue; 4513 transcoders |= BIT(crtc_state->cpu_transcoder); 4514 } 4515 4516 return transcoders; 4517 } 4518 4519 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4520 struct intel_crtc_state *crtc_state, 4521 struct drm_connector_state *conn_state) 4522 { 4523 struct intel_display *display = to_intel_display(encoder); 4524 struct drm_connector *connector = conn_state->connector; 4525 u8 port_sync_transcoders = 0; 4526 4527 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4528 encoder->base.base.id, encoder->base.name, 4529 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4530 4531 if (connector->has_tile) 4532 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4533 connector->tile_group->id); 4534 4535 /* 4536 * EDP Transcoders cannot be ensalved 4537 * make them a master always when present 4538 */ 4539 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4540 crtc_state->master_transcoder = TRANSCODER_EDP; 4541 else 4542 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4543 4544 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4545 crtc_state->master_transcoder = INVALID_TRANSCODER; 4546 crtc_state->sync_mode_slaves_mask = 4547 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4548 } 4549 4550 return 0; 4551 } 4552 4553 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4554 { 4555 struct intel_display *display = to_intel_display(encoder->dev); 4556 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4557 4558 intel_dp_encoder_flush_work(encoder); 4559 if (intel_encoder_is_tc(&dig_port->base)) 4560 intel_tc_port_cleanup(dig_port); 4561 intel_display_power_flush_work(display); 4562 4563 drm_encoder_cleanup(encoder); 4564 kfree(dig_port->hdcp.port_data.streams); 4565 kfree(dig_port); 4566 } 4567 4568 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4569 { 4570 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4571 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4572 4573 intel_dp->reset_link_params = true; 4574 intel_dp_invalidate_source_oui(intel_dp); 4575 4576 intel_pps_encoder_reset(intel_dp); 4577 4578 if (intel_encoder_is_tc(&dig_port->base)) 4579 intel_tc_port_init_mode(dig_port); 4580 } 4581 4582 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4583 { 4584 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4585 4586 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4587 4588 return 0; 4589 } 4590 4591 static const struct drm_encoder_funcs intel_ddi_funcs = { 4592 .reset = intel_ddi_encoder_reset, 4593 .destroy = intel_ddi_encoder_destroy, 4594 .late_register = intel_ddi_encoder_late_register, 4595 }; 4596 4597 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4598 { 4599 struct intel_display *display = to_intel_display(dig_port); 4600 struct intel_connector *connector; 4601 enum port port = dig_port->base.port; 4602 4603 connector = intel_connector_alloc(); 4604 if (!connector) 4605 return -ENOMEM; 4606 4607 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4608 if (DISPLAY_VER(display) >= 14) 4609 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4610 else 4611 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4612 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4613 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4614 4615 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4616 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4617 4618 if (!intel_dp_init_connector(dig_port, connector)) { 4619 kfree(connector); 4620 return -EINVAL; 4621 } 4622 4623 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4624 struct drm_privacy_screen *privacy_screen; 4625 4626 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4627 if (!IS_ERR(privacy_screen)) { 4628 drm_connector_attach_privacy_screen_provider(&connector->base, 4629 privacy_screen); 4630 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4631 drm_warn(display->drm, "Error getting privacy-screen\n"); 4632 } 4633 } 4634 4635 return 0; 4636 } 4637 4638 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4639 struct drm_modeset_acquire_ctx *ctx) 4640 { 4641 struct intel_display *display = to_intel_display(encoder); 4642 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4643 struct intel_connector *connector = hdmi->attached_connector; 4644 struct i2c_adapter *ddc = connector->base.ddc; 4645 struct drm_connector_state *conn_state; 4646 struct intel_crtc_state *crtc_state; 4647 struct intel_crtc *crtc; 4648 u8 config; 4649 int ret; 4650 4651 if (connector->base.status != connector_status_connected) 4652 return 0; 4653 4654 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4655 ctx); 4656 if (ret) 4657 return ret; 4658 4659 conn_state = connector->base.state; 4660 4661 crtc = to_intel_crtc(conn_state->crtc); 4662 if (!crtc) 4663 return 0; 4664 4665 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4666 if (ret) 4667 return ret; 4668 4669 crtc_state = to_intel_crtc_state(crtc->base.state); 4670 4671 drm_WARN_ON(display->drm, 4672 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4673 4674 if (!crtc_state->hw.active) 4675 return 0; 4676 4677 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4678 !crtc_state->hdmi_scrambling) 4679 return 0; 4680 4681 if (conn_state->commit && 4682 !try_wait_for_completion(&conn_state->commit->hw_done)) 4683 return 0; 4684 4685 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4686 if (ret < 0) { 4687 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4688 connector->base.base.id, connector->base.name, ret); 4689 return 0; 4690 } 4691 4692 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4693 crtc_state->hdmi_high_tmds_clock_ratio && 4694 !!(config & SCDC_SCRAMBLING_ENABLE) == 4695 crtc_state->hdmi_scrambling) 4696 return 0; 4697 4698 /* 4699 * HDMI 2.0 says that one should not send scrambled data 4700 * prior to configuring the sink scrambling, and that 4701 * TMDS clock/data transmission should be suspended when 4702 * changing the TMDS clock rate in the sink. So let's 4703 * just do a full modeset here, even though some sinks 4704 * would be perfectly happy if were to just reconfigure 4705 * the SCDC settings on the fly. 4706 */ 4707 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4708 } 4709 4710 static void intel_ddi_link_check(struct intel_encoder *encoder) 4711 { 4712 struct intel_display *display = to_intel_display(encoder); 4713 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4714 4715 /* TODO: Move checking the HDMI link state here as well. */ 4716 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4717 4718 intel_dp_link_check(encoder); 4719 } 4720 4721 static enum intel_hotplug_state 4722 intel_ddi_hotplug(struct intel_encoder *encoder, 4723 struct intel_connector *connector) 4724 { 4725 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4726 struct intel_dp *intel_dp = &dig_port->dp; 4727 bool is_tc = intel_encoder_is_tc(encoder); 4728 struct drm_modeset_acquire_ctx ctx; 4729 enum intel_hotplug_state state; 4730 int ret; 4731 4732 if (intel_dp_test_phy(intel_dp)) 4733 return INTEL_HOTPLUG_UNCHANGED; 4734 4735 state = intel_encoder_hotplug(encoder, connector); 4736 4737 if (!intel_tc_port_link_reset(dig_port)) { 4738 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4739 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4740 ret = intel_hdmi_reset_link(encoder, &ctx); 4741 drm_WARN_ON(encoder->base.dev, ret); 4742 } else { 4743 intel_dp_check_link_state(intel_dp); 4744 } 4745 } 4746 4747 /* 4748 * Unpowered type-c dongles can take some time to boot and be 4749 * responsible, so here giving some time to those dongles to power up 4750 * and then retrying the probe. 4751 * 4752 * On many platforms the HDMI live state signal is known to be 4753 * unreliable, so we can't use it to detect if a sink is connected or 4754 * not. Instead we detect if it's connected based on whether we can 4755 * read the EDID or not. That in turn has a problem during disconnect, 4756 * since the HPD interrupt may be raised before the DDC lines get 4757 * disconnected (due to how the required length of DDC vs. HPD 4758 * connector pins are specified) and so we'll still be able to get a 4759 * valid EDID. To solve this schedule another detection cycle if this 4760 * time around we didn't detect any change in the sink's connection 4761 * status. 4762 * 4763 * Type-c connectors which get their HPD signal deasserted then 4764 * reasserted, without unplugging/replugging the sink from the 4765 * connector, introduce a delay until the AUX channel communication 4766 * becomes functional. Retry the detection for 5 seconds on type-c 4767 * connectors to account for this delay. 4768 */ 4769 if (state == INTEL_HOTPLUG_UNCHANGED && 4770 connector->hotplug_retries < (is_tc ? 5 : 1) && 4771 !dig_port->dp.is_mst) 4772 state = INTEL_HOTPLUG_RETRY; 4773 4774 return state; 4775 } 4776 4777 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4778 { 4779 struct intel_display *display = to_intel_display(encoder); 4780 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4781 4782 return intel_de_read(display, SDEISR) & bit; 4783 } 4784 4785 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4786 { 4787 struct intel_display *display = to_intel_display(encoder); 4788 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4789 4790 return intel_de_read(display, DEISR) & bit; 4791 } 4792 4793 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4794 { 4795 struct intel_display *display = to_intel_display(encoder); 4796 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4797 4798 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4799 } 4800 4801 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4802 { 4803 struct intel_connector *connector; 4804 enum port port = dig_port->base.port; 4805 4806 connector = intel_connector_alloc(); 4807 if (!connector) 4808 return -ENOMEM; 4809 4810 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4811 4812 if (!intel_hdmi_init_connector(dig_port, connector)) { 4813 /* 4814 * HDMI connector init failures may just mean conflicting DDC 4815 * pins or not having enough lanes. Handle them gracefully, but 4816 * don't fail the entire DDI init. 4817 */ 4818 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4819 kfree(connector); 4820 } 4821 4822 return 0; 4823 } 4824 4825 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4826 { 4827 struct intel_display *display = to_intel_display(dig_port); 4828 4829 if (dig_port->base.port != PORT_A) 4830 return false; 4831 4832 if (dig_port->ddi_a_4_lanes) 4833 return false; 4834 4835 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4836 * supported configuration 4837 */ 4838 if (display->platform.geminilake || display->platform.broxton) 4839 return true; 4840 4841 return false; 4842 } 4843 4844 static int 4845 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4846 { 4847 struct intel_display *display = to_intel_display(dig_port); 4848 enum port port = dig_port->base.port; 4849 int max_lanes = 4; 4850 4851 if (DISPLAY_VER(display) >= 11) 4852 return max_lanes; 4853 4854 if (port == PORT_A || port == PORT_E) { 4855 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4856 max_lanes = port == PORT_A ? 4 : 0; 4857 else 4858 /* Both A and E share 2 lanes */ 4859 max_lanes = 2; 4860 } 4861 4862 /* 4863 * Some BIOS might fail to set this bit on port A if eDP 4864 * wasn't lit up at boot. Force this bit set when needed 4865 * so we use the proper lane count for our calculations. 4866 */ 4867 if (intel_ddi_a_force_4_lanes(dig_port)) { 4868 drm_dbg_kms(display->drm, 4869 "Forcing DDI_A_4_LANES for port A\n"); 4870 dig_port->ddi_a_4_lanes = true; 4871 max_lanes = 4; 4872 } 4873 4874 return max_lanes; 4875 } 4876 4877 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4878 { 4879 if (port >= PORT_D_XELPD) 4880 return HPD_PORT_D + port - PORT_D_XELPD; 4881 else if (port >= PORT_TC1) 4882 return HPD_PORT_TC1 + port - PORT_TC1; 4883 else 4884 return HPD_PORT_A + port - PORT_A; 4885 } 4886 4887 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4888 { 4889 if (port >= PORT_TC1) 4890 return HPD_PORT_C + port - PORT_TC1; 4891 else 4892 return HPD_PORT_A + port - PORT_A; 4893 } 4894 4895 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4896 { 4897 if (port >= PORT_TC1) 4898 return HPD_PORT_TC1 + port - PORT_TC1; 4899 else 4900 return HPD_PORT_A + port - PORT_A; 4901 } 4902 4903 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4904 { 4905 struct drm_i915_private *dev_priv = to_i915(display->drm); 4906 4907 if (HAS_PCH_TGP(dev_priv)) 4908 return tgl_hpd_pin(display, port); 4909 4910 if (port >= PORT_TC1) 4911 return HPD_PORT_C + port - PORT_TC1; 4912 else 4913 return HPD_PORT_A + port - PORT_A; 4914 } 4915 4916 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4917 { 4918 if (port >= PORT_C) 4919 return HPD_PORT_TC1 + port - PORT_C; 4920 else 4921 return HPD_PORT_A + port - PORT_A; 4922 } 4923 4924 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4925 { 4926 struct drm_i915_private *dev_priv = to_i915(display->drm); 4927 4928 if (port == PORT_D) 4929 return HPD_PORT_A; 4930 4931 if (HAS_PCH_TGP(dev_priv)) 4932 return icl_hpd_pin(display, port); 4933 4934 return HPD_PORT_A + port - PORT_A; 4935 } 4936 4937 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4938 { 4939 struct drm_i915_private *dev_priv = to_i915(display->drm); 4940 4941 if (HAS_PCH_TGP(dev_priv)) 4942 return icl_hpd_pin(display, port); 4943 4944 return HPD_PORT_A + port - PORT_A; 4945 } 4946 4947 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 4948 { 4949 if (DISPLAY_VER(display) >= 12) 4950 return port >= PORT_TC1; 4951 else if (DISPLAY_VER(display) >= 11) 4952 return port >= PORT_C; 4953 else 4954 return false; 4955 } 4956 4957 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4958 { 4959 intel_dp_encoder_suspend(encoder); 4960 } 4961 4962 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4963 { 4964 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4965 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4966 4967 /* 4968 * TODO: Move this to intel_dp_encoder_suspend(), 4969 * once modeset locking around that is removed. 4970 */ 4971 intel_encoder_link_check_flush_work(encoder); 4972 intel_tc_port_suspend(dig_port); 4973 } 4974 4975 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4976 { 4977 if (intel_encoder_is_dp(encoder)) 4978 intel_dp_encoder_shutdown(encoder); 4979 if (intel_encoder_is_hdmi(encoder)) 4980 intel_hdmi_encoder_shutdown(encoder); 4981 } 4982 4983 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4984 { 4985 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4986 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4987 4988 intel_tc_port_cleanup(dig_port); 4989 } 4990 4991 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4992 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4993 4994 static bool port_strap_detected(struct intel_display *display, enum port port) 4995 { 4996 /* straps not used on skl+ */ 4997 if (DISPLAY_VER(display) >= 9) 4998 return true; 4999 5000 switch (port) { 5001 case PORT_A: 5002 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5003 case PORT_B: 5004 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5005 case PORT_C: 5006 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5007 case PORT_D: 5008 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5009 case PORT_E: 5010 return true; /* no strap for DDI-E */ 5011 default: 5012 MISSING_CASE(port); 5013 return false; 5014 } 5015 } 5016 5017 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5018 { 5019 return init_dp || intel_encoder_is_tc(encoder); 5020 } 5021 5022 static bool assert_has_icl_dsi(struct intel_display *display) 5023 { 5024 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5025 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5026 "Platform does not support DSI\n"); 5027 } 5028 5029 static bool port_in_use(struct intel_display *display, enum port port) 5030 { 5031 struct intel_encoder *encoder; 5032 5033 for_each_intel_encoder(display->drm, encoder) { 5034 /* FIXME what about second port for dual link DSI? */ 5035 if (encoder->port == port) 5036 return true; 5037 } 5038 5039 return false; 5040 } 5041 5042 void intel_ddi_init(struct intel_display *display, 5043 const struct intel_bios_encoder_data *devdata) 5044 { 5045 struct intel_digital_port *dig_port; 5046 struct intel_encoder *encoder; 5047 bool init_hdmi, init_dp; 5048 enum port port; 5049 enum phy phy; 5050 u32 ddi_buf_ctl; 5051 5052 port = intel_bios_encoder_port(devdata); 5053 if (port == PORT_NONE) 5054 return; 5055 5056 if (!port_strap_detected(display, port)) { 5057 drm_dbg_kms(display->drm, 5058 "Port %c strap not detected\n", port_name(port)); 5059 return; 5060 } 5061 5062 if (!assert_port_valid(display, port)) 5063 return; 5064 5065 if (port_in_use(display, port)) { 5066 drm_dbg_kms(display->drm, 5067 "Port %c already claimed\n", port_name(port)); 5068 return; 5069 } 5070 5071 if (intel_bios_encoder_supports_dsi(devdata)) { 5072 /* BXT/GLK handled elsewhere, for now at least */ 5073 if (!assert_has_icl_dsi(display)) 5074 return; 5075 5076 icl_dsi_init(display, devdata); 5077 return; 5078 } 5079 5080 phy = intel_port_to_phy(display, port); 5081 5082 /* 5083 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5084 * have taken over some of the PHYs and made them unavailable to the 5085 * driver. In that case we should skip initializing the corresponding 5086 * outputs. 5087 */ 5088 if (intel_hti_uses_phy(display, phy)) { 5089 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5090 port_name(port), phy_name(phy)); 5091 return; 5092 } 5093 5094 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5095 intel_bios_encoder_supports_hdmi(devdata); 5096 init_dp = intel_bios_encoder_supports_dp(devdata); 5097 5098 if (intel_bios_encoder_is_lspcon(devdata)) { 5099 /* 5100 * Lspcon device needs to be driven with DP connector 5101 * with special detection sequence. So make sure DP 5102 * is initialized before lspcon. 5103 */ 5104 init_dp = true; 5105 init_hdmi = false; 5106 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5107 port_name(port)); 5108 } 5109 5110 if (!init_dp && !init_hdmi) { 5111 drm_dbg_kms(display->drm, 5112 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5113 port_name(port)); 5114 return; 5115 } 5116 5117 if (intel_phy_is_snps(display, phy) && 5118 display->snps.phy_failed_calibration & BIT(phy)) { 5119 drm_dbg_kms(display->drm, 5120 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5121 phy_name(phy)); 5122 } 5123 5124 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5125 if (!dig_port) 5126 return; 5127 5128 dig_port->aux_ch = AUX_CH_NONE; 5129 5130 encoder = &dig_port->base; 5131 encoder->devdata = devdata; 5132 5133 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5134 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5135 DRM_MODE_ENCODER_TMDS, 5136 "DDI %c/PHY %c", 5137 port_name(port - PORT_D_XELPD + PORT_D), 5138 phy_name(phy)); 5139 } else if (DISPLAY_VER(display) >= 12) { 5140 enum tc_port tc_port = intel_port_to_tc(display, port); 5141 5142 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5143 DRM_MODE_ENCODER_TMDS, 5144 "DDI %s%c/PHY %s%c", 5145 port >= PORT_TC1 ? "TC" : "", 5146 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5147 tc_port != TC_PORT_NONE ? "TC" : "", 5148 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5149 } else if (DISPLAY_VER(display) >= 11) { 5150 enum tc_port tc_port = intel_port_to_tc(display, port); 5151 5152 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5153 DRM_MODE_ENCODER_TMDS, 5154 "DDI %c%s/PHY %s%c", 5155 port_name(port), 5156 port >= PORT_C ? " (TC)" : "", 5157 tc_port != TC_PORT_NONE ? "TC" : "", 5158 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5159 } else { 5160 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5161 DRM_MODE_ENCODER_TMDS, 5162 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5163 } 5164 5165 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5166 5167 mutex_init(&dig_port->hdcp.mutex); 5168 dig_port->hdcp.num_streams = 0; 5169 5170 encoder->hotplug = intel_ddi_hotplug; 5171 encoder->compute_output_type = intel_ddi_compute_output_type; 5172 encoder->compute_config = intel_ddi_compute_config; 5173 encoder->compute_config_late = intel_ddi_compute_config_late; 5174 encoder->enable = intel_ddi_enable; 5175 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5176 encoder->pre_enable = intel_ddi_pre_enable; 5177 encoder->disable = intel_ddi_disable; 5178 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5179 encoder->post_disable = intel_ddi_post_disable; 5180 encoder->update_pipe = intel_ddi_update_pipe; 5181 encoder->audio_enable = intel_audio_codec_enable; 5182 encoder->audio_disable = intel_audio_codec_disable; 5183 encoder->get_hw_state = intel_ddi_get_hw_state; 5184 encoder->sync_state = intel_ddi_sync_state; 5185 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5186 encoder->suspend = intel_ddi_encoder_suspend; 5187 encoder->shutdown = intel_ddi_encoder_shutdown; 5188 encoder->get_power_domains = intel_ddi_get_power_domains; 5189 5190 encoder->type = INTEL_OUTPUT_DDI; 5191 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5192 encoder->port = port; 5193 encoder->cloneable = 0; 5194 encoder->pipe_mask = ~0; 5195 5196 if (DISPLAY_VER(display) >= 14) { 5197 encoder->enable_clock = intel_mtl_pll_enable; 5198 encoder->disable_clock = intel_mtl_pll_disable; 5199 encoder->port_pll_type = intel_mtl_port_pll_type; 5200 encoder->get_config = mtl_ddi_get_config; 5201 } else if (display->platform.dg2) { 5202 encoder->enable_clock = intel_mpllb_enable; 5203 encoder->disable_clock = intel_mpllb_disable; 5204 encoder->get_config = dg2_ddi_get_config; 5205 } else if (display->platform.alderlake_s) { 5206 encoder->enable_clock = adls_ddi_enable_clock; 5207 encoder->disable_clock = adls_ddi_disable_clock; 5208 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5209 encoder->get_config = adls_ddi_get_config; 5210 } else if (display->platform.rocketlake) { 5211 encoder->enable_clock = rkl_ddi_enable_clock; 5212 encoder->disable_clock = rkl_ddi_disable_clock; 5213 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5214 encoder->get_config = rkl_ddi_get_config; 5215 } else if (display->platform.dg1) { 5216 encoder->enable_clock = dg1_ddi_enable_clock; 5217 encoder->disable_clock = dg1_ddi_disable_clock; 5218 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5219 encoder->get_config = dg1_ddi_get_config; 5220 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5221 if (intel_ddi_is_tc(display, port)) { 5222 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5223 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5224 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5225 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5226 encoder->get_config = icl_ddi_combo_get_config; 5227 } else { 5228 encoder->enable_clock = icl_ddi_combo_enable_clock; 5229 encoder->disable_clock = icl_ddi_combo_disable_clock; 5230 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5231 encoder->get_config = icl_ddi_combo_get_config; 5232 } 5233 } else if (DISPLAY_VER(display) >= 11) { 5234 if (intel_ddi_is_tc(display, port)) { 5235 encoder->enable_clock = icl_ddi_tc_enable_clock; 5236 encoder->disable_clock = icl_ddi_tc_disable_clock; 5237 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5238 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5239 encoder->get_config = icl_ddi_tc_get_config; 5240 } else { 5241 encoder->enable_clock = icl_ddi_combo_enable_clock; 5242 encoder->disable_clock = icl_ddi_combo_disable_clock; 5243 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5244 encoder->get_config = icl_ddi_combo_get_config; 5245 } 5246 } else if (display->platform.geminilake || display->platform.broxton) { 5247 /* BXT/GLK have fixed PLL->port mapping */ 5248 encoder->get_config = bxt_ddi_get_config; 5249 } else if (DISPLAY_VER(display) == 9) { 5250 encoder->enable_clock = skl_ddi_enable_clock; 5251 encoder->disable_clock = skl_ddi_disable_clock; 5252 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5253 encoder->get_config = skl_ddi_get_config; 5254 } else if (display->platform.broadwell || display->platform.haswell) { 5255 encoder->enable_clock = hsw_ddi_enable_clock; 5256 encoder->disable_clock = hsw_ddi_disable_clock; 5257 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5258 encoder->get_config = hsw_ddi_get_config; 5259 } 5260 5261 if (DISPLAY_VER(display) >= 14) { 5262 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5263 } else if (display->platform.dg2) { 5264 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5265 } else if (DISPLAY_VER(display) >= 12) { 5266 if (intel_encoder_is_combo(encoder)) 5267 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5268 else 5269 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5270 } else if (DISPLAY_VER(display) >= 11) { 5271 if (intel_encoder_is_combo(encoder)) 5272 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5273 else 5274 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5275 } else if (display->platform.geminilake || display->platform.broxton) { 5276 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5277 } else { 5278 encoder->set_signal_levels = hsw_set_signal_levels; 5279 } 5280 5281 intel_ddi_buf_trans_init(encoder); 5282 5283 if (DISPLAY_VER(display) >= 13) 5284 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5285 else if (display->platform.dg1) 5286 encoder->hpd_pin = dg1_hpd_pin(display, port); 5287 else if (display->platform.rocketlake) 5288 encoder->hpd_pin = rkl_hpd_pin(display, port); 5289 else if (DISPLAY_VER(display) >= 12) 5290 encoder->hpd_pin = tgl_hpd_pin(display, port); 5291 else if (display->platform.jasperlake || display->platform.elkhartlake) 5292 encoder->hpd_pin = ehl_hpd_pin(display, port); 5293 else if (DISPLAY_VER(display) == 11) 5294 encoder->hpd_pin = icl_hpd_pin(display, port); 5295 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5296 encoder->hpd_pin = skl_hpd_pin(display, port); 5297 else 5298 encoder->hpd_pin = intel_hpd_pin_default(port); 5299 5300 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5301 5302 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5303 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5304 5305 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5306 5307 dig_port->dp.output_reg = INVALID_MMIO_REG; 5308 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5309 5310 if (need_aux_ch(encoder, init_dp)) { 5311 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5312 if (dig_port->aux_ch == AUX_CH_NONE) 5313 goto err; 5314 } 5315 5316 if (intel_encoder_is_tc(encoder)) { 5317 bool is_legacy = 5318 !intel_bios_encoder_supports_typec_usb(devdata) && 5319 !intel_bios_encoder_supports_tbt(devdata); 5320 5321 if (!is_legacy && init_hdmi) { 5322 is_legacy = !init_dp; 5323 5324 drm_dbg_kms(display->drm, 5325 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5326 port_name(port), 5327 str_yes_no(init_dp), 5328 is_legacy ? "legacy" : "non-legacy"); 5329 } 5330 5331 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5332 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5333 5334 dig_port->lock = intel_tc_port_lock; 5335 dig_port->unlock = intel_tc_port_unlock; 5336 5337 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5338 goto err; 5339 } 5340 5341 drm_WARN_ON(display->drm, port > PORT_I); 5342 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5343 5344 if (DISPLAY_VER(display) >= 11) { 5345 if (intel_encoder_is_tc(encoder)) 5346 dig_port->connected = intel_tc_port_connected; 5347 else 5348 dig_port->connected = lpt_digital_port_connected; 5349 } else if (display->platform.geminilake || display->platform.broxton) { 5350 dig_port->connected = bdw_digital_port_connected; 5351 } else if (DISPLAY_VER(display) == 9) { 5352 dig_port->connected = lpt_digital_port_connected; 5353 } else if (display->platform.broadwell) { 5354 if (port == PORT_A) 5355 dig_port->connected = bdw_digital_port_connected; 5356 else 5357 dig_port->connected = lpt_digital_port_connected; 5358 } else if (display->platform.haswell) { 5359 if (port == PORT_A) 5360 dig_port->connected = hsw_digital_port_connected; 5361 else 5362 dig_port->connected = lpt_digital_port_connected; 5363 } 5364 5365 intel_infoframe_init(dig_port); 5366 5367 if (init_dp) { 5368 if (intel_ddi_init_dp_connector(dig_port)) 5369 goto err; 5370 5371 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5372 5373 if (dig_port->dp.mso_link_count) 5374 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5375 } 5376 5377 /* 5378 * In theory we don't need the encoder->type check, 5379 * but leave it just in case we have some really bad VBTs... 5380 */ 5381 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5382 if (intel_ddi_init_hdmi_connector(dig_port)) 5383 goto err; 5384 } 5385 5386 return; 5387 5388 err: 5389 drm_encoder_cleanup(&encoder->base); 5390 kfree(dig_port); 5391 } 5392