1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_11_6; 587 u32 cri_txdeemph_override_5_0; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x18, 0x00, 0x00 }, /* 0 0 */ 594 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 595 { 0x24, 0x00, 0x0C }, /* 0 2 */ 596 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 597 { 0x21, 0x00, 0x00 }, /* 1 0 */ 598 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 599 { 0x30, 0x00, 0x0F }, /* 1 2 */ 600 { 0x31, 0x00, 0x03 }, /* 2 0 */ 601 { 0x34, 0x00, 0x0B }, /* 2 1 */ 602 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 606 /* Voltage swing pre-emphasis */ 607 { 0x18, 0x00, 0x00 }, /* 0 0 */ 608 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 609 { 0x24, 0x00, 0x0C }, /* 0 2 */ 610 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 611 { 0x26, 0x00, 0x00 }, /* 1 0 */ 612 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 613 { 0x33, 0x00, 0x0C }, /* 1 2 */ 614 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 615 { 0x36, 0x00, 0x09 }, /* 2 1 */ 616 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 617 }; 618 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 620 /* HDMI Preset VS Pre-emph */ 621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 631 }; 632 633 struct tgl_dkl_phy_ddi_buf_trans { 634 u32 dkl_vswing_control; 635 u32 dkl_preshoot_control; 636 u32 dkl_de_emphasis_control; 637 }; 638 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 640 /* VS pre-emp Non-trans mV Pre-emph dB */ 641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 651 }; 652 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 654 /* VS pre-emp Non-trans mV Pre-emph dB */ 655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 665 }; 666 667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 668 /* HDMI Preset VS Pre-emph */ 669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 679 }; 680 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 682 /* NT mV Trans mV db */ 683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 693 }; 694 695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 696 /* NT mV Trans mV db */ 697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 707 }; 708 709 static const struct ddi_buf_trans * 710 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 711 { 712 if (dev_priv->vbt.edp.low_vswing) { 713 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 714 return bdw_ddi_translations_edp; 715 } else { 716 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 717 return bdw_ddi_translations_dp; 718 } 719 } 720 721 static const struct ddi_buf_trans * 722 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 723 { 724 if (IS_SKL_ULX(dev_priv)) { 725 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 726 return skl_y_ddi_translations_dp; 727 } else if (IS_SKL_ULT(dev_priv)) { 728 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 729 return skl_u_ddi_translations_dp; 730 } else { 731 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 732 return skl_ddi_translations_dp; 733 } 734 } 735 736 static const struct ddi_buf_trans * 737 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 738 { 739 if (IS_KBL_ULX(dev_priv) || 740 IS_CFL_ULX(dev_priv) || 741 IS_CML_ULX(dev_priv)) { 742 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 743 return kbl_y_ddi_translations_dp; 744 } else if (IS_KBL_ULT(dev_priv) || 745 IS_CFL_ULT(dev_priv) || 746 IS_CML_ULT(dev_priv)) { 747 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 748 return kbl_u_ddi_translations_dp; 749 } else { 750 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 751 return kbl_ddi_translations_dp; 752 } 753 } 754 755 static const struct ddi_buf_trans * 756 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 757 { 758 if (dev_priv->vbt.edp.low_vswing) { 759 if (IS_SKL_ULX(dev_priv) || 760 IS_KBL_ULX(dev_priv) || 761 IS_CFL_ULX(dev_priv) || 762 IS_CML_ULX(dev_priv)) { 763 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 764 return skl_y_ddi_translations_edp; 765 } else if (IS_SKL_ULT(dev_priv) || 766 IS_KBL_ULT(dev_priv) || 767 IS_CFL_ULT(dev_priv) || 768 IS_CML_ULT(dev_priv)) { 769 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 770 return skl_u_ddi_translations_edp; 771 } else { 772 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 773 return skl_ddi_translations_edp; 774 } 775 } 776 777 if (IS_KABYLAKE(dev_priv) || 778 IS_COFFEELAKE(dev_priv) || 779 IS_COMETLAKE(dev_priv)) 780 return kbl_get_buf_trans_dp(dev_priv, n_entries); 781 else 782 return skl_get_buf_trans_dp(dev_priv, n_entries); 783 } 784 785 static const struct ddi_buf_trans * 786 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 787 { 788 if (IS_SKL_ULX(dev_priv) || 789 IS_KBL_ULX(dev_priv) || 790 IS_CFL_ULX(dev_priv) || 791 IS_CML_ULX(dev_priv)) { 792 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 793 return skl_y_ddi_translations_hdmi; 794 } else { 795 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 796 return skl_ddi_translations_hdmi; 797 } 798 } 799 800 static int skl_buf_trans_num_entries(enum port port, int n_entries) 801 { 802 /* Only DDIA and DDIE can select the 10th register with DP */ 803 if (port == PORT_A || port == PORT_E) 804 return min(n_entries, 10); 805 else 806 return min(n_entries, 9); 807 } 808 809 static const struct ddi_buf_trans * 810 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 811 enum port port, int *n_entries) 812 { 813 if (IS_KABYLAKE(dev_priv) || 814 IS_COFFEELAKE(dev_priv) || 815 IS_COMETLAKE(dev_priv)) { 816 const struct ddi_buf_trans *ddi_translations = 817 kbl_get_buf_trans_dp(dev_priv, n_entries); 818 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 819 return ddi_translations; 820 } else if (IS_SKYLAKE(dev_priv)) { 821 const struct ddi_buf_trans *ddi_translations = 822 skl_get_buf_trans_dp(dev_priv, n_entries); 823 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 824 return ddi_translations; 825 } else if (IS_BROADWELL(dev_priv)) { 826 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 827 return bdw_ddi_translations_dp; 828 } else if (IS_HASWELL(dev_priv)) { 829 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 830 return hsw_ddi_translations_dp; 831 } 832 833 *n_entries = 0; 834 return NULL; 835 } 836 837 static const struct ddi_buf_trans * 838 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 839 enum port port, int *n_entries) 840 { 841 if (IS_GEN9_BC(dev_priv)) { 842 const struct ddi_buf_trans *ddi_translations = 843 skl_get_buf_trans_edp(dev_priv, n_entries); 844 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 845 return ddi_translations; 846 } else if (IS_BROADWELL(dev_priv)) { 847 return bdw_get_buf_trans_edp(dev_priv, n_entries); 848 } else if (IS_HASWELL(dev_priv)) { 849 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 850 return hsw_ddi_translations_dp; 851 } 852 853 *n_entries = 0; 854 return NULL; 855 } 856 857 static const struct ddi_buf_trans * 858 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 859 int *n_entries) 860 { 861 if (IS_BROADWELL(dev_priv)) { 862 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 863 return bdw_ddi_translations_fdi; 864 } else if (IS_HASWELL(dev_priv)) { 865 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 866 return hsw_ddi_translations_fdi; 867 } 868 869 *n_entries = 0; 870 return NULL; 871 } 872 873 static const struct ddi_buf_trans * 874 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 875 int *n_entries) 876 { 877 if (IS_GEN9_BC(dev_priv)) { 878 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 879 } else if (IS_BROADWELL(dev_priv)) { 880 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 881 return bdw_ddi_translations_hdmi; 882 } else if (IS_HASWELL(dev_priv)) { 883 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 884 return hsw_ddi_translations_hdmi; 885 } 886 887 *n_entries = 0; 888 return NULL; 889 } 890 891 static const struct bxt_ddi_buf_trans * 892 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 893 { 894 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 895 return bxt_ddi_translations_dp; 896 } 897 898 static const struct bxt_ddi_buf_trans * 899 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 900 { 901 if (dev_priv->vbt.edp.low_vswing) { 902 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 903 return bxt_ddi_translations_edp; 904 } 905 906 return bxt_get_buf_trans_dp(dev_priv, n_entries); 907 } 908 909 static const struct bxt_ddi_buf_trans * 910 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 911 { 912 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 913 return bxt_ddi_translations_hdmi; 914 } 915 916 static const struct cnl_ddi_buf_trans * 917 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 918 { 919 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 920 921 if (voltage == VOLTAGE_INFO_0_85V) { 922 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 923 return cnl_ddi_translations_hdmi_0_85V; 924 } else if (voltage == VOLTAGE_INFO_0_95V) { 925 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 926 return cnl_ddi_translations_hdmi_0_95V; 927 } else if (voltage == VOLTAGE_INFO_1_05V) { 928 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 929 return cnl_ddi_translations_hdmi_1_05V; 930 } else { 931 *n_entries = 1; /* shut up gcc */ 932 MISSING_CASE(voltage); 933 } 934 return NULL; 935 } 936 937 static const struct cnl_ddi_buf_trans * 938 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 939 { 940 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 941 942 if (voltage == VOLTAGE_INFO_0_85V) { 943 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 944 return cnl_ddi_translations_dp_0_85V; 945 } else if (voltage == VOLTAGE_INFO_0_95V) { 946 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 947 return cnl_ddi_translations_dp_0_95V; 948 } else if (voltage == VOLTAGE_INFO_1_05V) { 949 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 950 return cnl_ddi_translations_dp_1_05V; 951 } else { 952 *n_entries = 1; /* shut up gcc */ 953 MISSING_CASE(voltage); 954 } 955 return NULL; 956 } 957 958 static const struct cnl_ddi_buf_trans * 959 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 960 { 961 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 962 963 if (dev_priv->vbt.edp.low_vswing) { 964 if (voltage == VOLTAGE_INFO_0_85V) { 965 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 966 return cnl_ddi_translations_edp_0_85V; 967 } else if (voltage == VOLTAGE_INFO_0_95V) { 968 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 969 return cnl_ddi_translations_edp_0_95V; 970 } else if (voltage == VOLTAGE_INFO_1_05V) { 971 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 972 return cnl_ddi_translations_edp_1_05V; 973 } else { 974 *n_entries = 1; /* shut up gcc */ 975 MISSING_CASE(voltage); 976 } 977 return NULL; 978 } else { 979 return cnl_get_buf_trans_dp(dev_priv, n_entries); 980 } 981 } 982 983 static const struct cnl_ddi_buf_trans * 984 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 985 int *n_entries) 986 { 987 if (type == INTEL_OUTPUT_HDMI) { 988 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 989 return icl_combo_phy_ddi_translations_hdmi; 990 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 991 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 992 return icl_combo_phy_ddi_translations_edp_hbr3; 993 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 994 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 995 return icl_combo_phy_ddi_translations_edp_hbr2; 996 } 997 998 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 999 return icl_combo_phy_ddi_translations_dp_hbr2; 1000 } 1001 1002 static const struct icl_mg_phy_ddi_buf_trans * 1003 icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1004 int *n_entries) 1005 { 1006 if (type == INTEL_OUTPUT_HDMI) { 1007 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1008 return icl_mg_phy_ddi_translations_hdmi; 1009 } else if (rate > 270000) { 1010 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1011 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1012 } 1013 1014 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1015 return icl_mg_phy_ddi_translations_rbr_hbr; 1016 } 1017 1018 static const struct cnl_ddi_buf_trans * 1019 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1020 int *n_entries) 1021 { 1022 if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) { 1023 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1024 return ehl_combo_phy_ddi_translations_dp; 1025 } 1026 1027 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 1028 } 1029 1030 static const struct cnl_ddi_buf_trans * 1031 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1032 int *n_entries) 1033 { 1034 if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { 1035 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 1036 } else if (rate > 270000) { 1037 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1038 return tgl_combo_phy_ddi_translations_dp_hbr2; 1039 } 1040 1041 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1042 return tgl_combo_phy_ddi_translations_dp_hbr; 1043 } 1044 1045 static const struct tgl_dkl_phy_ddi_buf_trans * 1046 tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1047 int *n_entries) 1048 { 1049 if (type == INTEL_OUTPUT_HDMI) { 1050 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1051 return tgl_dkl_phy_hdmi_ddi_trans; 1052 } else if (rate > 270000) { 1053 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1054 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1055 } 1056 1057 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1058 return tgl_dkl_phy_dp_ddi_trans; 1059 } 1060 1061 static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 1062 { 1063 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1064 int n_entries, level, default_entry; 1065 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1066 1067 if (INTEL_GEN(dev_priv) >= 12) { 1068 if (intel_phy_is_combo(dev_priv, phy)) 1069 tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 1070 0, &n_entries); 1071 else 1072 tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, 1073 &n_entries); 1074 default_entry = n_entries - 1; 1075 } else if (INTEL_GEN(dev_priv) == 11) { 1076 if (intel_phy_is_combo(dev_priv, phy)) 1077 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 1078 0, &n_entries); 1079 else 1080 icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, 1081 &n_entries); 1082 default_entry = n_entries - 1; 1083 } else if (IS_CANNONLAKE(dev_priv)) { 1084 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 1085 default_entry = n_entries - 1; 1086 } else if (IS_GEN9_LP(dev_priv)) { 1087 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 1088 default_entry = n_entries - 1; 1089 } else if (IS_GEN9_BC(dev_priv)) { 1090 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1091 default_entry = 8; 1092 } else if (IS_BROADWELL(dev_priv)) { 1093 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1094 default_entry = 7; 1095 } else if (IS_HASWELL(dev_priv)) { 1096 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1097 default_entry = 6; 1098 } else { 1099 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1100 return 0; 1101 } 1102 1103 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1104 return 0; 1105 1106 level = intel_bios_hdmi_level_shift(encoder); 1107 if (level < 0) 1108 level = default_entry; 1109 1110 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1111 level = n_entries - 1; 1112 1113 return level; 1114 } 1115 1116 /* 1117 * Starting with Haswell, DDI port buffers must be programmed with correct 1118 * values in advance. This function programs the correct values for 1119 * DP/eDP/FDI use cases. 1120 */ 1121 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1122 const struct intel_crtc_state *crtc_state) 1123 { 1124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1125 u32 iboost_bit = 0; 1126 int i, n_entries; 1127 enum port port = encoder->port; 1128 const struct ddi_buf_trans *ddi_translations; 1129 1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1131 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1132 &n_entries); 1133 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1134 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 1135 &n_entries); 1136 else 1137 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 1138 &n_entries); 1139 1140 /* If we're boosting the current, set bit 31 of trans1 */ 1141 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1142 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1143 1144 for (i = 0; i < n_entries; i++) { 1145 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1146 ddi_translations[i].trans1 | iboost_bit); 1147 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1148 ddi_translations[i].trans2); 1149 } 1150 } 1151 1152 /* 1153 * Starting with Haswell, DDI port buffers must be programmed with correct 1154 * values in advance. This function programs the correct values for 1155 * HDMI/DVI use cases. 1156 */ 1157 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1158 int level) 1159 { 1160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1161 u32 iboost_bit = 0; 1162 int n_entries; 1163 enum port port = encoder->port; 1164 const struct ddi_buf_trans *ddi_translations; 1165 1166 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1167 1168 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1169 return; 1170 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1171 level = n_entries - 1; 1172 1173 /* If we're boosting the current, set bit 31 of trans1 */ 1174 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1175 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1176 1177 /* Entry 9 is for HDMI: */ 1178 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1179 ddi_translations[level].trans1 | iboost_bit); 1180 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1181 ddi_translations[level].trans2); 1182 } 1183 1184 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1185 enum port port) 1186 { 1187 i915_reg_t reg = DDI_BUF_CTL(port); 1188 int i; 1189 1190 for (i = 0; i < 16; i++) { 1191 udelay(1); 1192 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) 1193 return; 1194 } 1195 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", 1196 port_name(port)); 1197 } 1198 1199 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1200 { 1201 switch (pll->info->id) { 1202 case DPLL_ID_WRPLL1: 1203 return PORT_CLK_SEL_WRPLL1; 1204 case DPLL_ID_WRPLL2: 1205 return PORT_CLK_SEL_WRPLL2; 1206 case DPLL_ID_SPLL: 1207 return PORT_CLK_SEL_SPLL; 1208 case DPLL_ID_LCPLL_810: 1209 return PORT_CLK_SEL_LCPLL_810; 1210 case DPLL_ID_LCPLL_1350: 1211 return PORT_CLK_SEL_LCPLL_1350; 1212 case DPLL_ID_LCPLL_2700: 1213 return PORT_CLK_SEL_LCPLL_2700; 1214 default: 1215 MISSING_CASE(pll->info->id); 1216 return PORT_CLK_SEL_NONE; 1217 } 1218 } 1219 1220 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1221 const struct intel_crtc_state *crtc_state) 1222 { 1223 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1224 int clock = crtc_state->port_clock; 1225 const enum intel_dpll_id id = pll->info->id; 1226 1227 switch (id) { 1228 default: 1229 /* 1230 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1231 * here, so do warn if this get passed in 1232 */ 1233 MISSING_CASE(id); 1234 return DDI_CLK_SEL_NONE; 1235 case DPLL_ID_ICL_TBTPLL: 1236 switch (clock) { 1237 case 162000: 1238 return DDI_CLK_SEL_TBT_162; 1239 case 270000: 1240 return DDI_CLK_SEL_TBT_270; 1241 case 540000: 1242 return DDI_CLK_SEL_TBT_540; 1243 case 810000: 1244 return DDI_CLK_SEL_TBT_810; 1245 default: 1246 MISSING_CASE(clock); 1247 return DDI_CLK_SEL_NONE; 1248 } 1249 case DPLL_ID_ICL_MGPLL1: 1250 case DPLL_ID_ICL_MGPLL2: 1251 case DPLL_ID_ICL_MGPLL3: 1252 case DPLL_ID_ICL_MGPLL4: 1253 case DPLL_ID_TGL_MGPLL5: 1254 case DPLL_ID_TGL_MGPLL6: 1255 return DDI_CLK_SEL_MG; 1256 } 1257 } 1258 1259 /* Starting with Haswell, different DDI ports can work in FDI mode for 1260 * connection to the PCH-located connectors. For this, it is necessary to train 1261 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1262 * 1263 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1264 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1265 * DDI A (which is used for eDP) 1266 */ 1267 1268 void hsw_fdi_link_train(struct intel_encoder *encoder, 1269 const struct intel_crtc_state *crtc_state) 1270 { 1271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1272 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1273 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1274 1275 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1276 1277 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1278 * mode set "sequence for CRT port" document: 1279 * - TP1 to TP2 time with the default value 1280 * - FDI delay to 90h 1281 * 1282 * WaFDIAutoLinkSetTimingOverrride:hsw 1283 */ 1284 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1285 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1286 1287 /* Enable the PCH Receiver FDI PLL */ 1288 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1289 FDI_RX_PLL_ENABLE | 1290 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1291 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1292 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1293 udelay(220); 1294 1295 /* Switch from Rawclk to PCDclk */ 1296 rx_ctl_val |= FDI_PCDCLK; 1297 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1298 1299 /* Configure Port Clock Select */ 1300 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1301 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1302 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1303 1304 /* Start the training iterating through available voltages and emphasis, 1305 * testing each value twice. */ 1306 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1307 /* Configure DP_TP_CTL with auto-training */ 1308 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1309 DP_TP_CTL_FDI_AUTOTRAIN | 1310 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1311 DP_TP_CTL_LINK_TRAIN_PAT1 | 1312 DP_TP_CTL_ENABLE); 1313 1314 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1315 * DDI E does not support port reversal, the functionality is 1316 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1317 * port reversal bit */ 1318 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1319 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1320 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1321 1322 udelay(600); 1323 1324 /* Program PCH FDI Receiver TU */ 1325 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1326 1327 /* Enable PCH FDI Receiver with auto-training */ 1328 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1329 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1330 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1331 1332 /* Wait for FDI receiver lane calibration */ 1333 udelay(30); 1334 1335 /* Unset FDI_RX_MISC pwrdn lanes */ 1336 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1337 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1338 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1339 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1340 1341 /* Wait for FDI auto training time */ 1342 udelay(5); 1343 1344 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1345 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1346 drm_dbg_kms(&dev_priv->drm, 1347 "FDI link training done on step %d\n", i); 1348 break; 1349 } 1350 1351 /* 1352 * Leave things enabled even if we failed to train FDI. 1353 * Results in less fireworks from the state checker. 1354 */ 1355 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1356 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1357 break; 1358 } 1359 1360 rx_ctl_val &= ~FDI_RX_ENABLE; 1361 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1362 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1363 1364 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1365 temp &= ~DDI_BUF_CTL_ENABLE; 1366 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1367 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1368 1369 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1370 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1371 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1372 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1373 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1374 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1375 1376 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1377 1378 /* Reset FDI_RX_MISC pwrdn lanes */ 1379 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1380 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1381 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1382 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1383 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1384 } 1385 1386 /* Enable normal pixel sending for FDI */ 1387 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1388 DP_TP_CTL_FDI_AUTOTRAIN | 1389 DP_TP_CTL_LINK_TRAIN_NORMAL | 1390 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1391 DP_TP_CTL_ENABLE); 1392 } 1393 1394 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1395 { 1396 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1397 struct intel_digital_port *intel_dig_port = 1398 enc_to_dig_port(encoder); 1399 1400 intel_dp->DP = intel_dig_port->saved_port_bits | 1401 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1402 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1403 } 1404 1405 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1406 enum port port) 1407 { 1408 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1409 1410 switch (val) { 1411 case DDI_CLK_SEL_NONE: 1412 return 0; 1413 case DDI_CLK_SEL_TBT_162: 1414 return 162000; 1415 case DDI_CLK_SEL_TBT_270: 1416 return 270000; 1417 case DDI_CLK_SEL_TBT_540: 1418 return 540000; 1419 case DDI_CLK_SEL_TBT_810: 1420 return 810000; 1421 default: 1422 MISSING_CASE(val); 1423 return 0; 1424 } 1425 } 1426 1427 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1428 { 1429 int dotclock; 1430 1431 if (pipe_config->has_pch_encoder) 1432 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1433 &pipe_config->fdi_m_n); 1434 else if (intel_crtc_has_dp_encoder(pipe_config)) 1435 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1436 &pipe_config->dp_m_n); 1437 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1438 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1439 else 1440 dotclock = pipe_config->port_clock; 1441 1442 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1443 !intel_crtc_has_dp_encoder(pipe_config)) 1444 dotclock *= 2; 1445 1446 if (pipe_config->pixel_multiplier) 1447 dotclock /= pipe_config->pixel_multiplier; 1448 1449 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1450 } 1451 1452 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1453 struct intel_crtc_state *pipe_config) 1454 { 1455 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1456 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1457 1458 if (intel_phy_is_tc(dev_priv, phy) && 1459 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1460 DPLL_ID_ICL_TBTPLL) 1461 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1462 encoder->port); 1463 else 1464 pipe_config->port_clock = 1465 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1466 1467 ddi_dotclock_get(pipe_config); 1468 } 1469 1470 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1471 const struct drm_connector_state *conn_state) 1472 { 1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1475 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1476 u32 temp; 1477 1478 if (!intel_crtc_has_dp_encoder(crtc_state)) 1479 return; 1480 1481 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1482 1483 temp = DP_MSA_MISC_SYNC_CLOCK; 1484 1485 switch (crtc_state->pipe_bpp) { 1486 case 18: 1487 temp |= DP_MSA_MISC_6_BPC; 1488 break; 1489 case 24: 1490 temp |= DP_MSA_MISC_8_BPC; 1491 break; 1492 case 30: 1493 temp |= DP_MSA_MISC_10_BPC; 1494 break; 1495 case 36: 1496 temp |= DP_MSA_MISC_12_BPC; 1497 break; 1498 default: 1499 MISSING_CASE(crtc_state->pipe_bpp); 1500 break; 1501 } 1502 1503 /* nonsense combination */ 1504 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1505 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1506 1507 if (crtc_state->limited_color_range) 1508 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1509 1510 /* 1511 * As per DP 1.2 spec section 2.3.4.3 while sending 1512 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1513 * colorspace information. 1514 */ 1515 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1516 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1517 1518 /* 1519 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1520 * of Color Encoding Format and Content Color Gamut] while sending 1521 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1522 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1523 */ 1524 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1525 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1526 1527 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1528 } 1529 1530 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1531 { 1532 if (master_transcoder == TRANSCODER_EDP) 1533 return 0; 1534 else 1535 return master_transcoder + 1; 1536 } 1537 1538 /* 1539 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1540 * 1541 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1542 * intel_ddi_config_transcoder_func(). 1543 */ 1544 static u32 1545 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1546 const struct intel_crtc_state *crtc_state) 1547 { 1548 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1550 enum pipe pipe = crtc->pipe; 1551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1552 enum port port = encoder->port; 1553 u32 temp; 1554 1555 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1556 temp = TRANS_DDI_FUNC_ENABLE; 1557 if (INTEL_GEN(dev_priv) >= 12) 1558 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1559 else 1560 temp |= TRANS_DDI_SELECT_PORT(port); 1561 1562 switch (crtc_state->pipe_bpp) { 1563 case 18: 1564 temp |= TRANS_DDI_BPC_6; 1565 break; 1566 case 24: 1567 temp |= TRANS_DDI_BPC_8; 1568 break; 1569 case 30: 1570 temp |= TRANS_DDI_BPC_10; 1571 break; 1572 case 36: 1573 temp |= TRANS_DDI_BPC_12; 1574 break; 1575 default: 1576 BUG(); 1577 } 1578 1579 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1580 temp |= TRANS_DDI_PVSYNC; 1581 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1582 temp |= TRANS_DDI_PHSYNC; 1583 1584 if (cpu_transcoder == TRANSCODER_EDP) { 1585 switch (pipe) { 1586 case PIPE_A: 1587 /* On Haswell, can only use the always-on power well for 1588 * eDP when not using the panel fitter, and when not 1589 * using motion blur mitigation (which we don't 1590 * support). */ 1591 if (crtc_state->pch_pfit.force_thru) 1592 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1593 else 1594 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1595 break; 1596 case PIPE_B: 1597 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1598 break; 1599 case PIPE_C: 1600 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1601 break; 1602 default: 1603 BUG(); 1604 break; 1605 } 1606 } 1607 1608 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1609 if (crtc_state->has_hdmi_sink) 1610 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1611 else 1612 temp |= TRANS_DDI_MODE_SELECT_DVI; 1613 1614 if (crtc_state->hdmi_scrambling) 1615 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1616 if (crtc_state->hdmi_high_tmds_clock_ratio) 1617 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1618 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1619 temp |= TRANS_DDI_MODE_SELECT_FDI; 1620 temp |= (crtc_state->fdi_lanes - 1) << 1; 1621 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1622 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1623 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1624 1625 if (INTEL_GEN(dev_priv) >= 12) { 1626 enum transcoder master; 1627 1628 master = crtc_state->mst_master_transcoder; 1629 drm_WARN_ON(&dev_priv->drm, 1630 master == INVALID_TRANSCODER); 1631 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1632 } 1633 } else { 1634 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1635 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1636 } 1637 1638 if (IS_GEN_RANGE(dev_priv, 8, 10) && 1639 crtc_state->master_transcoder != INVALID_TRANSCODER) { 1640 u8 master_select = 1641 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 1642 1643 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 1644 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 1645 } 1646 1647 return temp; 1648 } 1649 1650 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 1651 const struct intel_crtc_state *crtc_state) 1652 { 1653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1655 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1656 1657 if (INTEL_GEN(dev_priv) >= 11) { 1658 enum transcoder master_transcoder = crtc_state->master_transcoder; 1659 u32 ctl2 = 0; 1660 1661 if (master_transcoder != INVALID_TRANSCODER) { 1662 u8 master_select = 1663 bdw_trans_port_sync_master_select(master_transcoder); 1664 1665 ctl2 |= PORT_SYNC_MODE_ENABLE | 1666 PORT_SYNC_MODE_MASTER_SELECT(master_select); 1667 } 1668 1669 intel_de_write(dev_priv, 1670 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 1671 } 1672 1673 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 1674 intel_ddi_transcoder_func_reg_val_get(encoder, 1675 crtc_state)); 1676 } 1677 1678 /* 1679 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1680 * bit. 1681 */ 1682 static void 1683 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 1684 const struct intel_crtc_state *crtc_state) 1685 { 1686 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1687 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1688 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1689 u32 ctl; 1690 1691 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1692 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1693 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1694 } 1695 1696 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1697 { 1698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1700 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1701 u32 ctl; 1702 1703 if (INTEL_GEN(dev_priv) >= 11) 1704 intel_de_write(dev_priv, 1705 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 1706 1707 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1708 1709 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1710 1711 if (IS_GEN_RANGE(dev_priv, 8, 10)) 1712 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 1713 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 1714 1715 if (INTEL_GEN(dev_priv) >= 12) { 1716 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1717 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 1718 TRANS_DDI_MODE_SELECT_MASK); 1719 } 1720 } else { 1721 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1722 } 1723 1724 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1725 1726 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1727 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1728 drm_dbg_kms(&dev_priv->drm, 1729 "Quirk Increase DDI disabled time\n"); 1730 /* Quirk time at 100ms for reliable operation */ 1731 msleep(100); 1732 } 1733 } 1734 1735 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1736 bool enable) 1737 { 1738 struct drm_device *dev = intel_encoder->base.dev; 1739 struct drm_i915_private *dev_priv = to_i915(dev); 1740 intel_wakeref_t wakeref; 1741 enum pipe pipe = 0; 1742 int ret = 0; 1743 u32 tmp; 1744 1745 wakeref = intel_display_power_get_if_enabled(dev_priv, 1746 intel_encoder->power_domain); 1747 if (drm_WARN_ON(dev, !wakeref)) 1748 return -ENXIO; 1749 1750 if (drm_WARN_ON(dev, 1751 !intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1752 ret = -EIO; 1753 goto out; 1754 } 1755 1756 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); 1757 if (enable) 1758 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1759 else 1760 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1761 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); 1762 out: 1763 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1764 return ret; 1765 } 1766 1767 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1768 { 1769 struct drm_device *dev = intel_connector->base.dev; 1770 struct drm_i915_private *dev_priv = to_i915(dev); 1771 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1772 int type = intel_connector->base.connector_type; 1773 enum port port = encoder->port; 1774 enum transcoder cpu_transcoder; 1775 intel_wakeref_t wakeref; 1776 enum pipe pipe = 0; 1777 u32 tmp; 1778 bool ret; 1779 1780 wakeref = intel_display_power_get_if_enabled(dev_priv, 1781 encoder->power_domain); 1782 if (!wakeref) 1783 return false; 1784 1785 if (!encoder->get_hw_state(encoder, &pipe)) { 1786 ret = false; 1787 goto out; 1788 } 1789 1790 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 1791 cpu_transcoder = TRANSCODER_EDP; 1792 else 1793 cpu_transcoder = (enum transcoder) pipe; 1794 1795 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1796 1797 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1798 case TRANS_DDI_MODE_SELECT_HDMI: 1799 case TRANS_DDI_MODE_SELECT_DVI: 1800 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1801 break; 1802 1803 case TRANS_DDI_MODE_SELECT_DP_SST: 1804 ret = type == DRM_MODE_CONNECTOR_eDP || 1805 type == DRM_MODE_CONNECTOR_DisplayPort; 1806 break; 1807 1808 case TRANS_DDI_MODE_SELECT_DP_MST: 1809 /* if the transcoder is in MST state then 1810 * connector isn't connected */ 1811 ret = false; 1812 break; 1813 1814 case TRANS_DDI_MODE_SELECT_FDI: 1815 ret = type == DRM_MODE_CONNECTOR_VGA; 1816 break; 1817 1818 default: 1819 ret = false; 1820 break; 1821 } 1822 1823 out: 1824 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1825 1826 return ret; 1827 } 1828 1829 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1830 u8 *pipe_mask, bool *is_dp_mst) 1831 { 1832 struct drm_device *dev = encoder->base.dev; 1833 struct drm_i915_private *dev_priv = to_i915(dev); 1834 enum port port = encoder->port; 1835 intel_wakeref_t wakeref; 1836 enum pipe p; 1837 u32 tmp; 1838 u8 mst_pipe_mask; 1839 1840 *pipe_mask = 0; 1841 *is_dp_mst = false; 1842 1843 wakeref = intel_display_power_get_if_enabled(dev_priv, 1844 encoder->power_domain); 1845 if (!wakeref) 1846 return; 1847 1848 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1849 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1850 goto out; 1851 1852 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 1853 tmp = intel_de_read(dev_priv, 1854 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1855 1856 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1857 default: 1858 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1859 /* fallthrough */ 1860 case TRANS_DDI_EDP_INPUT_A_ON: 1861 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1862 *pipe_mask = BIT(PIPE_A); 1863 break; 1864 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1865 *pipe_mask = BIT(PIPE_B); 1866 break; 1867 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1868 *pipe_mask = BIT(PIPE_C); 1869 break; 1870 } 1871 1872 goto out; 1873 } 1874 1875 mst_pipe_mask = 0; 1876 for_each_pipe(dev_priv, p) { 1877 enum transcoder cpu_transcoder = (enum transcoder)p; 1878 unsigned int port_mask, ddi_select; 1879 intel_wakeref_t trans_wakeref; 1880 1881 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 1882 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 1883 if (!trans_wakeref) 1884 continue; 1885 1886 if (INTEL_GEN(dev_priv) >= 12) { 1887 port_mask = TGL_TRANS_DDI_PORT_MASK; 1888 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 1889 } else { 1890 port_mask = TRANS_DDI_PORT_MASK; 1891 ddi_select = TRANS_DDI_SELECT_PORT(port); 1892 } 1893 1894 tmp = intel_de_read(dev_priv, 1895 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1896 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 1897 trans_wakeref); 1898 1899 if ((tmp & port_mask) != ddi_select) 1900 continue; 1901 1902 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1903 TRANS_DDI_MODE_SELECT_DP_MST) 1904 mst_pipe_mask |= BIT(p); 1905 1906 *pipe_mask |= BIT(p); 1907 } 1908 1909 if (!*pipe_mask) 1910 drm_dbg_kms(&dev_priv->drm, 1911 "No pipe for [ENCODER:%d:%s] found\n", 1912 encoder->base.base.id, encoder->base.name); 1913 1914 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 1915 drm_dbg_kms(&dev_priv->drm, 1916 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 1917 encoder->base.base.id, encoder->base.name, 1918 *pipe_mask); 1919 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 1920 } 1921 1922 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 1923 drm_dbg_kms(&dev_priv->drm, 1924 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 1925 encoder->base.base.id, encoder->base.name, 1926 *pipe_mask, mst_pipe_mask); 1927 else 1928 *is_dp_mst = mst_pipe_mask; 1929 1930 out: 1931 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 1932 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 1933 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 1934 BXT_PHY_LANE_POWERDOWN_ACK | 1935 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 1936 drm_err(&dev_priv->drm, 1937 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 1938 encoder->base.base.id, encoder->base.name, tmp); 1939 } 1940 1941 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1942 } 1943 1944 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1945 enum pipe *pipe) 1946 { 1947 u8 pipe_mask; 1948 bool is_mst; 1949 1950 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1951 1952 if (is_mst || !pipe_mask) 1953 return false; 1954 1955 *pipe = ffs(pipe_mask) - 1; 1956 1957 return true; 1958 } 1959 1960 static enum intel_display_power_domain 1961 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 1962 { 1963 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 1964 * DC states enabled at the same time, while for driver initiated AUX 1965 * transfers we need the same AUX IOs to be powered but with DC states 1966 * disabled. Accordingly use the AUX power domain here which leaves DC 1967 * states enabled. 1968 * However, for non-A AUX ports the corresponding non-EDP transcoders 1969 * would have already enabled power well 2 and DC_OFF. This means we can 1970 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 1971 * specific AUX_IO reference without powering up any extra wells. 1972 * Note that PSR is enabled only on Port A even though this function 1973 * returns the correct domain for other ports too. 1974 */ 1975 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 1976 intel_aux_power_domain(dig_port); 1977 } 1978 1979 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1980 struct intel_crtc_state *crtc_state) 1981 { 1982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1983 struct intel_digital_port *dig_port; 1984 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1985 1986 /* 1987 * TODO: Add support for MST encoders. Atm, the following should never 1988 * happen since fake-MST encoders don't set their get_power_domains() 1989 * hook. 1990 */ 1991 if (drm_WARN_ON(&dev_priv->drm, 1992 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1993 return; 1994 1995 dig_port = enc_to_dig_port(encoder); 1996 1997 if (!intel_phy_is_tc(dev_priv, phy) || 1998 dig_port->tc_mode != TC_PORT_TBT_ALT) 1999 intel_display_power_get(dev_priv, 2000 dig_port->ddi_io_power_domain); 2001 2002 /* 2003 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2004 * ports. 2005 */ 2006 if (intel_crtc_has_dp_encoder(crtc_state) || 2007 intel_phy_is_tc(dev_priv, phy)) 2008 intel_display_power_get(dev_priv, 2009 intel_ddi_main_link_aux_domain(dig_port)); 2010 2011 /* 2012 * VDSC power is needed when DSC is enabled 2013 */ 2014 if (crtc_state->dsc.compression_enable) 2015 intel_display_power_get(dev_priv, 2016 intel_dsc_power_domain(crtc_state)); 2017 } 2018 2019 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 2020 const struct intel_crtc_state *crtc_state) 2021 { 2022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2024 enum port port = encoder->port; 2025 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2026 2027 if (cpu_transcoder != TRANSCODER_EDP) { 2028 if (INTEL_GEN(dev_priv) >= 12) 2029 intel_de_write(dev_priv, 2030 TRANS_CLK_SEL(cpu_transcoder), 2031 TGL_TRANS_CLK_SEL_PORT(port)); 2032 else 2033 intel_de_write(dev_priv, 2034 TRANS_CLK_SEL(cpu_transcoder), 2035 TRANS_CLK_SEL_PORT(port)); 2036 } 2037 } 2038 2039 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2040 { 2041 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2042 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2043 2044 if (cpu_transcoder != TRANSCODER_EDP) { 2045 if (INTEL_GEN(dev_priv) >= 12) 2046 intel_de_write(dev_priv, 2047 TRANS_CLK_SEL(cpu_transcoder), 2048 TGL_TRANS_CLK_SEL_DISABLED); 2049 else 2050 intel_de_write(dev_priv, 2051 TRANS_CLK_SEL(cpu_transcoder), 2052 TRANS_CLK_SEL_DISABLED); 2053 } 2054 } 2055 2056 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2057 enum port port, u8 iboost) 2058 { 2059 u32 tmp; 2060 2061 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2062 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2063 if (iboost) 2064 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2065 else 2066 tmp |= BALANCE_LEG_DISABLE(port); 2067 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2068 } 2069 2070 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2071 int level, enum intel_output_type type) 2072 { 2073 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2075 enum port port = encoder->port; 2076 u8 iboost; 2077 2078 if (type == INTEL_OUTPUT_HDMI) 2079 iboost = intel_bios_hdmi_boost_level(encoder); 2080 else 2081 iboost = intel_bios_dp_boost_level(encoder); 2082 2083 if (iboost == 0) { 2084 const struct ddi_buf_trans *ddi_translations; 2085 int n_entries; 2086 2087 if (type == INTEL_OUTPUT_HDMI) 2088 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2089 else if (type == INTEL_OUTPUT_EDP) 2090 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2091 else 2092 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2093 2094 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2095 return; 2096 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2097 level = n_entries - 1; 2098 2099 iboost = ddi_translations[level].i_boost; 2100 } 2101 2102 /* Make sure that the requested I_boost is valid */ 2103 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2104 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2105 return; 2106 } 2107 2108 _skl_ddi_set_iboost(dev_priv, port, iboost); 2109 2110 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2111 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2112 } 2113 2114 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2115 int level, enum intel_output_type type) 2116 { 2117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2118 const struct bxt_ddi_buf_trans *ddi_translations; 2119 enum port port = encoder->port; 2120 int n_entries; 2121 2122 if (type == INTEL_OUTPUT_HDMI) 2123 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2124 else if (type == INTEL_OUTPUT_EDP) 2125 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2126 else 2127 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2128 2129 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2130 return; 2131 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2132 level = n_entries - 1; 2133 2134 bxt_ddi_phy_set_signal_level(dev_priv, port, 2135 ddi_translations[level].margin, 2136 ddi_translations[level].scale, 2137 ddi_translations[level].enable, 2138 ddi_translations[level].deemphasis); 2139 } 2140 2141 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) 2142 { 2143 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2145 enum port port = encoder->port; 2146 enum phy phy = intel_port_to_phy(dev_priv, port); 2147 int n_entries; 2148 2149 if (INTEL_GEN(dev_priv) >= 12) { 2150 if (intel_phy_is_combo(dev_priv, phy)) 2151 tgl_get_combo_buf_trans(dev_priv, encoder->type, 2152 intel_dp->link_rate, &n_entries); 2153 else 2154 tgl_get_dkl_buf_trans(dev_priv, encoder->type, 2155 intel_dp->link_rate, &n_entries); 2156 } else if (INTEL_GEN(dev_priv) == 11) { 2157 if (IS_ELKHARTLAKE(dev_priv)) 2158 ehl_get_combo_buf_trans(dev_priv, encoder->type, 2159 intel_dp->link_rate, &n_entries); 2160 else if (intel_phy_is_combo(dev_priv, phy)) 2161 icl_get_combo_buf_trans(dev_priv, encoder->type, 2162 intel_dp->link_rate, &n_entries); 2163 else 2164 icl_get_mg_buf_trans(dev_priv, encoder->type, 2165 intel_dp->link_rate, &n_entries); 2166 } else if (IS_CANNONLAKE(dev_priv)) { 2167 if (encoder->type == INTEL_OUTPUT_EDP) 2168 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2169 else 2170 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2171 } else if (IS_GEN9_LP(dev_priv)) { 2172 if (encoder->type == INTEL_OUTPUT_EDP) 2173 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2174 else 2175 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2176 } else { 2177 if (encoder->type == INTEL_OUTPUT_EDP) 2178 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2179 else 2180 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2181 } 2182 2183 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2184 n_entries = 1; 2185 if (drm_WARN_ON(&dev_priv->drm, 2186 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2187 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2188 2189 return index_to_dp_signal_levels[n_entries - 1] & 2190 DP_TRAIN_VOLTAGE_SWING_MASK; 2191 } 2192 2193 /* 2194 * We assume that the full set of pre-emphasis values can be 2195 * used on all DDI platforms. Should that change we need to 2196 * rethink this code. 2197 */ 2198 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 2199 { 2200 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2201 } 2202 2203 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2204 int level, enum intel_output_type type) 2205 { 2206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2207 const struct cnl_ddi_buf_trans *ddi_translations; 2208 enum port port = encoder->port; 2209 int n_entries, ln; 2210 u32 val; 2211 2212 if (type == INTEL_OUTPUT_HDMI) 2213 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2214 else if (type == INTEL_OUTPUT_EDP) 2215 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2216 else 2217 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2218 2219 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2220 return; 2221 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2222 level = n_entries - 1; 2223 2224 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2225 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2226 val &= ~SCALING_MODE_SEL_MASK; 2227 val |= SCALING_MODE_SEL(2); 2228 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2229 2230 /* Program PORT_TX_DW2 */ 2231 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2232 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2233 RCOMP_SCALAR_MASK); 2234 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2235 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2236 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2237 val |= RCOMP_SCALAR(0x98); 2238 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2239 2240 /* Program PORT_TX_DW4 */ 2241 /* We cannot write to GRP. It would overrite individual loadgen */ 2242 for (ln = 0; ln < 4; ln++) { 2243 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2244 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2245 CURSOR_COEFF_MASK); 2246 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2247 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2248 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2249 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2250 } 2251 2252 /* Program PORT_TX_DW5 */ 2253 /* All DW5 values are fixed for every table entry */ 2254 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2255 val &= ~RTERM_SELECT_MASK; 2256 val |= RTERM_SELECT(6); 2257 val |= TAP3_DISABLE; 2258 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2259 2260 /* Program PORT_TX_DW7 */ 2261 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2262 val &= ~N_SCALAR_MASK; 2263 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2264 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2265 } 2266 2267 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2268 int level, enum intel_output_type type) 2269 { 2270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2271 enum port port = encoder->port; 2272 int width, rate, ln; 2273 u32 val; 2274 2275 if (type == INTEL_OUTPUT_HDMI) { 2276 width = 4; 2277 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2278 } else { 2279 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2280 2281 width = intel_dp->lane_count; 2282 rate = intel_dp->link_rate; 2283 } 2284 2285 /* 2286 * 1. If port type is eDP or DP, 2287 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2288 * else clear to 0b. 2289 */ 2290 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2291 if (type != INTEL_OUTPUT_HDMI) 2292 val |= COMMON_KEEPER_EN; 2293 else 2294 val &= ~COMMON_KEEPER_EN; 2295 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2296 2297 /* 2. Program loadgen select */ 2298 /* 2299 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2300 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2301 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2302 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2303 */ 2304 for (ln = 0; ln <= 3; ln++) { 2305 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2306 val &= ~LOADGEN_SELECT; 2307 2308 if ((rate <= 600000 && width == 4 && ln >= 1) || 2309 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2310 val |= LOADGEN_SELECT; 2311 } 2312 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2313 } 2314 2315 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2316 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2317 val |= SUS_CLOCK_CONFIG; 2318 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2319 2320 /* 4. Clear training enable to change swing values */ 2321 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2322 val &= ~TX_TRAINING_EN; 2323 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2324 2325 /* 5. Program swing and de-emphasis */ 2326 cnl_ddi_vswing_program(encoder, level, type); 2327 2328 /* 6. Set training enable to trigger update */ 2329 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2330 val |= TX_TRAINING_EN; 2331 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2332 } 2333 2334 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2335 u32 level, enum phy phy, int type, 2336 int rate) 2337 { 2338 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2339 u32 n_entries, val; 2340 int ln; 2341 2342 if (INTEL_GEN(dev_priv) >= 12) 2343 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, 2344 &n_entries); 2345 else if (IS_ELKHARTLAKE(dev_priv)) 2346 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, 2347 &n_entries); 2348 else 2349 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2350 &n_entries); 2351 if (!ddi_translations) 2352 return; 2353 2354 if (level >= n_entries) { 2355 drm_dbg_kms(&dev_priv->drm, 2356 "DDI translation not found for level %d. Using %d instead.", 2357 level, n_entries - 1); 2358 level = n_entries - 1; 2359 } 2360 2361 /* Set PORT_TX_DW5 */ 2362 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2363 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2364 TAP2_DISABLE | TAP3_DISABLE); 2365 val |= SCALING_MODE_SEL(0x2); 2366 val |= RTERM_SELECT(0x6); 2367 val |= TAP3_DISABLE; 2368 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2369 2370 /* Program PORT_TX_DW2 */ 2371 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2372 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2373 RCOMP_SCALAR_MASK); 2374 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2375 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2376 /* Program Rcomp scalar for every table entry */ 2377 val |= RCOMP_SCALAR(0x98); 2378 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2379 2380 /* Program PORT_TX_DW4 */ 2381 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2382 for (ln = 0; ln <= 3; ln++) { 2383 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2384 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2385 CURSOR_COEFF_MASK); 2386 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2387 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2388 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2389 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2390 } 2391 2392 /* Program PORT_TX_DW7 */ 2393 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2394 val &= ~N_SCALAR_MASK; 2395 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2396 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2397 } 2398 2399 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2400 u32 level, 2401 enum intel_output_type type) 2402 { 2403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2404 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2405 int width = 0; 2406 int rate = 0; 2407 u32 val; 2408 int ln = 0; 2409 2410 if (type == INTEL_OUTPUT_HDMI) { 2411 width = 4; 2412 /* Rate is always < than 6GHz for HDMI */ 2413 } else { 2414 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2415 2416 width = intel_dp->lane_count; 2417 rate = intel_dp->link_rate; 2418 } 2419 2420 /* 2421 * 1. If port type is eDP or DP, 2422 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2423 * else clear to 0b. 2424 */ 2425 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2426 if (type == INTEL_OUTPUT_HDMI) 2427 val &= ~COMMON_KEEPER_EN; 2428 else 2429 val |= COMMON_KEEPER_EN; 2430 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2431 2432 /* 2. Program loadgen select */ 2433 /* 2434 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2435 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2436 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2437 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2438 */ 2439 for (ln = 0; ln <= 3; ln++) { 2440 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2441 val &= ~LOADGEN_SELECT; 2442 2443 if ((rate <= 600000 && width == 4 && ln >= 1) || 2444 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2445 val |= LOADGEN_SELECT; 2446 } 2447 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2448 } 2449 2450 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2451 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2452 val |= SUS_CLOCK_CONFIG; 2453 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2454 2455 /* 4. Clear training enable to change swing values */ 2456 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2457 val &= ~TX_TRAINING_EN; 2458 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2459 2460 /* 5. Program swing and de-emphasis */ 2461 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2462 2463 /* 6. Set training enable to trigger update */ 2464 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2465 val |= TX_TRAINING_EN; 2466 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2467 } 2468 2469 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2470 int link_clock, u32 level, 2471 enum intel_output_type type) 2472 { 2473 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2474 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2475 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2476 u32 n_entries, val; 2477 int ln, rate = 0; 2478 2479 if (type != INTEL_OUTPUT_HDMI) { 2480 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2481 2482 rate = intel_dp->link_rate; 2483 } 2484 2485 ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate, 2486 &n_entries); 2487 /* The table does not have values for level 3 and level 9. */ 2488 if (level >= n_entries || level == 3 || level == 9) { 2489 drm_dbg_kms(&dev_priv->drm, 2490 "DDI translation not found for level %d. Using %d instead.", 2491 level, n_entries - 2); 2492 level = n_entries - 2; 2493 } 2494 2495 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2496 for (ln = 0; ln < 2; ln++) { 2497 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2498 val &= ~CRI_USE_FS32; 2499 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2500 2501 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2502 val &= ~CRI_USE_FS32; 2503 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2504 } 2505 2506 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2507 for (ln = 0; ln < 2; ln++) { 2508 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2509 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2510 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2511 ddi_translations[level].cri_txdeemph_override_17_12); 2512 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2513 2514 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2515 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2516 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2517 ddi_translations[level].cri_txdeemph_override_17_12); 2518 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2519 } 2520 2521 /* Program MG_TX_DRVCTRL with values from vswing table */ 2522 for (ln = 0; ln < 2; ln++) { 2523 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2524 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2525 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2526 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2527 ddi_translations[level].cri_txdeemph_override_5_0) | 2528 CRI_TXDEEMPH_OVERRIDE_11_6( 2529 ddi_translations[level].cri_txdeemph_override_11_6) | 2530 CRI_TXDEEMPH_OVERRIDE_EN; 2531 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2532 2533 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2534 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2535 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2536 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2537 ddi_translations[level].cri_txdeemph_override_5_0) | 2538 CRI_TXDEEMPH_OVERRIDE_11_6( 2539 ddi_translations[level].cri_txdeemph_override_11_6) | 2540 CRI_TXDEEMPH_OVERRIDE_EN; 2541 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2542 2543 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2544 } 2545 2546 /* 2547 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2548 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2549 * values from table for which TX1 and TX2 enabled. 2550 */ 2551 for (ln = 0; ln < 2; ln++) { 2552 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2553 if (link_clock < 300000) 2554 val |= CFG_LOW_RATE_LKREN_EN; 2555 else 2556 val &= ~CFG_LOW_RATE_LKREN_EN; 2557 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2558 } 2559 2560 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2561 for (ln = 0; ln < 2; ln++) { 2562 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2563 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2564 if (link_clock <= 500000) { 2565 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2566 } else { 2567 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2568 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2569 } 2570 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2571 2572 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2573 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2574 if (link_clock <= 500000) { 2575 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2576 } else { 2577 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2578 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2579 } 2580 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2581 } 2582 2583 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2584 for (ln = 0; ln < 2; ln++) { 2585 val = intel_de_read(dev_priv, 2586 MG_TX1_PISO_READLOAD(ln, tc_port)); 2587 val |= CRI_CALCINIT; 2588 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2589 val); 2590 2591 val = intel_de_read(dev_priv, 2592 MG_TX2_PISO_READLOAD(ln, tc_port)); 2593 val |= CRI_CALCINIT; 2594 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2595 val); 2596 } 2597 } 2598 2599 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2600 int link_clock, 2601 u32 level, 2602 enum intel_output_type type) 2603 { 2604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2605 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2606 2607 if (intel_phy_is_combo(dev_priv, phy)) 2608 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2609 else 2610 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level, 2611 type); 2612 } 2613 2614 static void 2615 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2616 u32 level, enum intel_output_type type) 2617 { 2618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2619 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2620 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2621 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2622 int rate = 0; 2623 2624 if (type == INTEL_OUTPUT_HDMI) { 2625 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2626 2627 rate = intel_dp->link_rate; 2628 } 2629 2630 ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate, 2631 &n_entries); 2632 2633 if (level >= n_entries) 2634 level = n_entries - 1; 2635 2636 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2637 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2638 DKL_TX_VSWING_CONTROL_MASK); 2639 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2640 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2641 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2642 2643 for (ln = 0; ln < 2; ln++) { 2644 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2645 HIP_INDEX_VAL(tc_port, ln)); 2646 2647 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2648 2649 /* All the registers are RMW */ 2650 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2651 val &= ~dpcnt_mask; 2652 val |= dpcnt_val; 2653 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2654 2655 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2656 val &= ~dpcnt_mask; 2657 val |= dpcnt_val; 2658 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2659 2660 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2661 val &= ~DKL_TX_DP20BITMODE; 2662 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2663 } 2664 } 2665 2666 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2667 int link_clock, 2668 u32 level, 2669 enum intel_output_type type) 2670 { 2671 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2672 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2673 2674 if (intel_phy_is_combo(dev_priv, phy)) 2675 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2676 else 2677 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); 2678 } 2679 2680 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) 2681 { 2682 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2683 int i; 2684 2685 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2686 if (index_to_dp_signal_levels[i] == signal_levels) 2687 return i; 2688 } 2689 2690 drm_WARN(&i915->drm, 1, 2691 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2692 signal_levels); 2693 2694 return 0; 2695 } 2696 2697 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2698 { 2699 u8 train_set = intel_dp->train_set[0]; 2700 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2701 DP_TRAIN_PRE_EMPHASIS_MASK); 2702 2703 return translate_signal_level(intel_dp, signal_levels); 2704 } 2705 2706 static void 2707 tgl_set_signal_levels(struct intel_dp *intel_dp) 2708 { 2709 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2710 int level = intel_ddi_dp_level(intel_dp); 2711 2712 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2713 level, encoder->type); 2714 } 2715 2716 static void 2717 icl_set_signal_levels(struct intel_dp *intel_dp) 2718 { 2719 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2720 int level = intel_ddi_dp_level(intel_dp); 2721 2722 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2723 level, encoder->type); 2724 } 2725 2726 static void 2727 cnl_set_signal_levels(struct intel_dp *intel_dp) 2728 { 2729 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2730 int level = intel_ddi_dp_level(intel_dp); 2731 2732 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2733 } 2734 2735 static void 2736 bxt_set_signal_levels(struct intel_dp *intel_dp) 2737 { 2738 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2739 int level = intel_ddi_dp_level(intel_dp); 2740 2741 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2742 } 2743 2744 static void 2745 hsw_set_signal_levels(struct intel_dp *intel_dp) 2746 { 2747 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2749 int level = intel_ddi_dp_level(intel_dp); 2750 enum port port = encoder->port; 2751 u32 signal_levels; 2752 2753 signal_levels = DDI_BUF_TRANS_SELECT(level); 2754 2755 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 2756 signal_levels); 2757 2758 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 2759 intel_dp->DP |= signal_levels; 2760 2761 if (IS_GEN9_BC(dev_priv)) 2762 skl_ddi_set_iboost(encoder, level, encoder->type); 2763 2764 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 2765 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 2766 } 2767 2768 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2769 enum phy phy) 2770 { 2771 if (intel_phy_is_combo(dev_priv, phy)) { 2772 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2773 } else if (intel_phy_is_tc(dev_priv, phy)) { 2774 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2775 (enum port)phy); 2776 2777 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2778 } 2779 2780 return 0; 2781 } 2782 2783 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2784 const struct intel_crtc_state *crtc_state) 2785 { 2786 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2787 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2788 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2789 u32 val; 2790 2791 mutex_lock(&dev_priv->dpll.lock); 2792 2793 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2794 drm_WARN_ON(&dev_priv->drm, 2795 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2796 2797 if (intel_phy_is_combo(dev_priv, phy)) { 2798 /* 2799 * Even though this register references DDIs, note that we 2800 * want to pass the PHY rather than the port (DDI). For 2801 * ICL, port=phy in all cases so it doesn't matter, but for 2802 * EHL the bspec notes the following: 2803 * 2804 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2805 * Clock Select chooses the PLL for both DDIA and DDID and 2806 * drives port A in all cases." 2807 */ 2808 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2809 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2810 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2811 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 2812 } 2813 2814 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2815 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2816 2817 mutex_unlock(&dev_priv->dpll.lock); 2818 } 2819 2820 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2821 { 2822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2823 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2824 u32 val; 2825 2826 mutex_lock(&dev_priv->dpll.lock); 2827 2828 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2829 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2830 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2831 2832 mutex_unlock(&dev_priv->dpll.lock); 2833 } 2834 2835 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 2836 u32 port_mask, bool ddi_clk_needed) 2837 { 2838 enum port port; 2839 u32 val; 2840 2841 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2842 for_each_port_masked(port, port_mask) { 2843 enum phy phy = intel_port_to_phy(dev_priv, port); 2844 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 2845 phy); 2846 2847 if (ddi_clk_needed == !ddi_clk_off) 2848 continue; 2849 2850 /* 2851 * Punt on the case now where clock is gated, but it would 2852 * be needed by the port. Something else is really broken then. 2853 */ 2854 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 2855 continue; 2856 2857 drm_notice(&dev_priv->drm, 2858 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2859 phy_name(phy)); 2860 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2861 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2862 } 2863 } 2864 2865 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2866 { 2867 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2868 u32 port_mask; 2869 bool ddi_clk_needed; 2870 2871 /* 2872 * In case of DP MST, we sanitize the primary encoder only, not the 2873 * virtual ones. 2874 */ 2875 if (encoder->type == INTEL_OUTPUT_DP_MST) 2876 return; 2877 2878 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2879 u8 pipe_mask; 2880 bool is_mst; 2881 2882 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2883 /* 2884 * In the unlikely case that BIOS enables DP in MST mode, just 2885 * warn since our MST HW readout is incomplete. 2886 */ 2887 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 2888 return; 2889 } 2890 2891 port_mask = BIT(encoder->port); 2892 ddi_clk_needed = encoder->base.crtc; 2893 2894 if (encoder->type == INTEL_OUTPUT_DSI) { 2895 struct intel_encoder *other_encoder; 2896 2897 port_mask = intel_dsi_encoder_ports(encoder); 2898 /* 2899 * Sanity check that we haven't incorrectly registered another 2900 * encoder using any of the ports of this DSI encoder. 2901 */ 2902 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 2903 if (other_encoder == encoder) 2904 continue; 2905 2906 if (drm_WARN_ON(&dev_priv->drm, 2907 port_mask & BIT(other_encoder->port))) 2908 return; 2909 } 2910 /* 2911 * For DSI we keep the ddi clocks gated 2912 * except during enable/disable sequence. 2913 */ 2914 ddi_clk_needed = false; 2915 } 2916 2917 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 2918 } 2919 2920 static void intel_ddi_clk_select(struct intel_encoder *encoder, 2921 const struct intel_crtc_state *crtc_state) 2922 { 2923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2924 enum port port = encoder->port; 2925 enum phy phy = intel_port_to_phy(dev_priv, port); 2926 u32 val; 2927 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2928 2929 if (drm_WARN_ON(&dev_priv->drm, !pll)) 2930 return; 2931 2932 mutex_lock(&dev_priv->dpll.lock); 2933 2934 if (INTEL_GEN(dev_priv) >= 11) { 2935 if (!intel_phy_is_combo(dev_priv, phy)) 2936 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2937 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 2938 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 2939 /* 2940 * MG does not exist but the programming is required 2941 * to ungate DDIC and DDID 2942 */ 2943 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2944 DDI_CLK_SEL_MG); 2945 } else if (IS_CANNONLAKE(dev_priv)) { 2946 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 2947 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2948 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 2949 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 2950 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2951 2952 /* 2953 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 2954 * This step and the step before must be done with separate 2955 * register writes. 2956 */ 2957 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2958 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 2959 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2960 } else if (IS_GEN9_BC(dev_priv)) { 2961 /* DDI -> PLL mapping */ 2962 val = intel_de_read(dev_priv, DPLL_CTRL2); 2963 2964 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2965 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2966 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2967 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2968 2969 intel_de_write(dev_priv, DPLL_CTRL2, val); 2970 2971 } else if (INTEL_GEN(dev_priv) < 9) { 2972 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2973 hsw_pll_to_ddi_pll_sel(pll)); 2974 } 2975 2976 mutex_unlock(&dev_priv->dpll.lock); 2977 } 2978 2979 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 2980 { 2981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2982 enum port port = encoder->port; 2983 enum phy phy = intel_port_to_phy(dev_priv, port); 2984 2985 if (INTEL_GEN(dev_priv) >= 11) { 2986 if (!intel_phy_is_combo(dev_priv, phy) || 2987 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 2988 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2989 DDI_CLK_SEL_NONE); 2990 } else if (IS_CANNONLAKE(dev_priv)) { 2991 intel_de_write(dev_priv, DPCLKA_CFGCR0, 2992 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2993 } else if (IS_GEN9_BC(dev_priv)) { 2994 intel_de_write(dev_priv, DPLL_CTRL2, 2995 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 2996 } else if (INTEL_GEN(dev_priv) < 9) { 2997 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2998 PORT_CLK_SEL_NONE); 2999 } 3000 } 3001 3002 static void 3003 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 3004 const struct intel_crtc_state *crtc_state) 3005 { 3006 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3007 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 3008 u32 ln0, ln1, pin_assignment; 3009 u8 width; 3010 3011 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3012 return; 3013 3014 if (INTEL_GEN(dev_priv) >= 12) { 3015 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3016 HIP_INDEX_VAL(tc_port, 0x0)); 3017 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3018 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3019 HIP_INDEX_VAL(tc_port, 0x1)); 3020 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3021 } else { 3022 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3023 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3024 } 3025 3026 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3027 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3028 3029 /* DPPATC */ 3030 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 3031 width = crtc_state->lane_count; 3032 3033 switch (pin_assignment) { 3034 case 0x0: 3035 drm_WARN_ON(&dev_priv->drm, 3036 intel_dig_port->tc_mode != TC_PORT_LEGACY); 3037 if (width == 1) { 3038 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3039 } else { 3040 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3041 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3042 } 3043 break; 3044 case 0x1: 3045 if (width == 4) { 3046 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3047 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3048 } 3049 break; 3050 case 0x2: 3051 if (width == 2) { 3052 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3053 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3054 } 3055 break; 3056 case 0x3: 3057 case 0x5: 3058 if (width == 1) { 3059 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3060 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3061 } else { 3062 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3063 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3064 } 3065 break; 3066 case 0x4: 3067 case 0x6: 3068 if (width == 1) { 3069 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3070 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3071 } else { 3072 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3073 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3074 } 3075 break; 3076 default: 3077 MISSING_CASE(pin_assignment); 3078 } 3079 3080 if (INTEL_GEN(dev_priv) >= 12) { 3081 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3082 HIP_INDEX_VAL(tc_port, 0x0)); 3083 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3084 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3085 HIP_INDEX_VAL(tc_port, 0x1)); 3086 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3087 } else { 3088 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3089 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3090 } 3091 } 3092 3093 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3094 const struct intel_crtc_state *crtc_state) 3095 { 3096 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3097 3098 if (!crtc_state->fec_enable) 3099 return; 3100 3101 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3102 drm_dbg_kms(&i915->drm, 3103 "Failed to set FEC_READY in the sink\n"); 3104 } 3105 3106 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3107 const struct intel_crtc_state *crtc_state) 3108 { 3109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3110 struct intel_dp *intel_dp; 3111 u32 val; 3112 3113 if (!crtc_state->fec_enable) 3114 return; 3115 3116 intel_dp = enc_to_intel_dp(encoder); 3117 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3118 val |= DP_TP_CTL_FEC_ENABLE; 3119 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3120 3121 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3122 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3123 drm_err(&dev_priv->drm, 3124 "Timed out waiting for FEC Enable Status\n"); 3125 } 3126 3127 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3128 const struct intel_crtc_state *crtc_state) 3129 { 3130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3131 struct intel_dp *intel_dp; 3132 u32 val; 3133 3134 if (!crtc_state->fec_enable) 3135 return; 3136 3137 intel_dp = enc_to_intel_dp(encoder); 3138 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3139 val &= ~DP_TP_CTL_FEC_ENABLE; 3140 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3141 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3142 } 3143 3144 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3145 struct intel_encoder *encoder, 3146 const struct intel_crtc_state *crtc_state, 3147 const struct drm_connector_state *conn_state) 3148 { 3149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3151 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3152 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3153 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3154 int level = intel_ddi_dp_level(intel_dp); 3155 enum transcoder transcoder = crtc_state->cpu_transcoder; 3156 3157 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3158 crtc_state->lane_count, is_mst); 3159 3160 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3161 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3162 3163 /* 3164 * 1. Enable Power Wells 3165 * 3166 * This was handled at the beginning of intel_atomic_commit_tail(), 3167 * before we called down into this function. 3168 */ 3169 3170 /* 2. Enable Panel Power if PPS is required */ 3171 intel_edp_panel_on(intel_dp); 3172 3173 /* 3174 * 3. For non-TBT Type-C ports, set FIA lane count 3175 * (DFLEXDPSP.DPX4TXLATC) 3176 * 3177 * This was done before tgl_ddi_pre_enable_dp by 3178 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3179 */ 3180 3181 /* 3182 * 4. Enable the port PLL. 3183 * 3184 * The PLL enabling itself was already done before this function by 3185 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3186 * configure the PLL to port mapping here. 3187 */ 3188 intel_ddi_clk_select(encoder, crtc_state); 3189 3190 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3191 if (!intel_phy_is_tc(dev_priv, phy) || 3192 dig_port->tc_mode != TC_PORT_TBT_ALT) 3193 intel_display_power_get(dev_priv, 3194 dig_port->ddi_io_power_domain); 3195 3196 /* 6. Program DP_MODE */ 3197 icl_program_mg_dp_mode(dig_port, crtc_state); 3198 3199 /* 3200 * 7. The rest of the below are substeps under the bspec's "Enable and 3201 * Train Display Port" step. Note that steps that are specific to 3202 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3203 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3204 * us when active_mst_links==0, so any steps designated for "single 3205 * stream or multi-stream master transcoder" can just be performed 3206 * unconditionally here. 3207 */ 3208 3209 /* 3210 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3211 * Transcoder. 3212 */ 3213 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3214 3215 /* 3216 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3217 * Transport Select 3218 */ 3219 intel_ddi_config_transcoder_func(encoder, crtc_state); 3220 3221 /* 3222 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3223 * selected 3224 * 3225 * This will be handled by the intel_dp_start_link_train() farther 3226 * down this function. 3227 */ 3228 3229 /* 7.e Configure voltage swing and related IO settings */ 3230 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3231 encoder->type); 3232 3233 /* 3234 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3235 * the used lanes of the DDI. 3236 */ 3237 if (intel_phy_is_combo(dev_priv, phy)) { 3238 bool lane_reversal = 3239 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3240 3241 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3242 crtc_state->lane_count, 3243 lane_reversal); 3244 } 3245 3246 /* 3247 * 7.g Configure and enable DDI_BUF_CTL 3248 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3249 * after 500 us. 3250 * 3251 * We only configure what the register value will be here. Actual 3252 * enabling happens during link training farther down. 3253 */ 3254 intel_ddi_init_dp_buf_reg(encoder); 3255 3256 if (!is_mst) 3257 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3258 3259 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3260 /* 3261 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3262 * in the FEC_CONFIGURATION register to 1 before initiating link 3263 * training 3264 */ 3265 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3266 3267 /* 3268 * 7.i Follow DisplayPort specification training sequence (see notes for 3269 * failure handling) 3270 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3271 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3272 * (timeout after 800 us) 3273 */ 3274 intel_dp_start_link_train(intel_dp); 3275 3276 /* 7.k Set DP_TP_CTL link training to Normal */ 3277 if (!is_trans_port_sync_mode(crtc_state)) 3278 intel_dp_stop_link_train(intel_dp); 3279 3280 /* 7.l Configure and enable FEC if needed */ 3281 intel_ddi_enable_fec(encoder, crtc_state); 3282 intel_dsc_enable(encoder, crtc_state); 3283 } 3284 3285 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3286 struct intel_encoder *encoder, 3287 const struct intel_crtc_state *crtc_state, 3288 const struct drm_connector_state *conn_state) 3289 { 3290 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3292 enum port port = encoder->port; 3293 enum phy phy = intel_port_to_phy(dev_priv, port); 3294 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3295 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3296 int level = intel_ddi_dp_level(intel_dp); 3297 3298 if (INTEL_GEN(dev_priv) < 11) 3299 drm_WARN_ON(&dev_priv->drm, 3300 is_mst && (port == PORT_A || port == PORT_E)); 3301 else 3302 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3303 3304 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3305 crtc_state->lane_count, is_mst); 3306 3307 intel_edp_panel_on(intel_dp); 3308 3309 intel_ddi_clk_select(encoder, crtc_state); 3310 3311 if (!intel_phy_is_tc(dev_priv, phy) || 3312 dig_port->tc_mode != TC_PORT_TBT_ALT) 3313 intel_display_power_get(dev_priv, 3314 dig_port->ddi_io_power_domain); 3315 3316 icl_program_mg_dp_mode(dig_port, crtc_state); 3317 3318 if (INTEL_GEN(dev_priv) >= 11) 3319 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3320 level, encoder->type); 3321 else if (IS_CANNONLAKE(dev_priv)) 3322 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3323 else if (IS_GEN9_LP(dev_priv)) 3324 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3325 else 3326 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3327 3328 if (intel_phy_is_combo(dev_priv, phy)) { 3329 bool lane_reversal = 3330 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3331 3332 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3333 crtc_state->lane_count, 3334 lane_reversal); 3335 } 3336 3337 intel_ddi_init_dp_buf_reg(encoder); 3338 if (!is_mst) 3339 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3340 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3341 true); 3342 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3343 intel_dp_start_link_train(intel_dp); 3344 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3345 !is_trans_port_sync_mode(crtc_state)) 3346 intel_dp_stop_link_train(intel_dp); 3347 3348 intel_ddi_enable_fec(encoder, crtc_state); 3349 3350 if (!is_mst) 3351 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3352 3353 intel_dsc_enable(encoder, crtc_state); 3354 } 3355 3356 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3357 struct intel_encoder *encoder, 3358 const struct intel_crtc_state *crtc_state, 3359 const struct drm_connector_state *conn_state) 3360 { 3361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3362 3363 if (INTEL_GEN(dev_priv) >= 12) 3364 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3365 else 3366 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3367 3368 /* MST will call a setting of MSA after an allocating of Virtual Channel 3369 * from MST encoder pre_enable callback. 3370 */ 3371 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3372 intel_ddi_set_dp_msa(crtc_state, conn_state); 3373 3374 intel_dp_set_m_n(crtc_state, M1_N1); 3375 } 3376 } 3377 3378 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3379 struct intel_encoder *encoder, 3380 const struct intel_crtc_state *crtc_state, 3381 const struct drm_connector_state *conn_state) 3382 { 3383 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3384 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3385 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3386 int level = intel_ddi_hdmi_level(encoder); 3387 3388 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3389 intel_ddi_clk_select(encoder, crtc_state); 3390 3391 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3392 3393 icl_program_mg_dp_mode(dig_port, crtc_state); 3394 3395 if (INTEL_GEN(dev_priv) >= 12) 3396 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3397 level, INTEL_OUTPUT_HDMI); 3398 else if (INTEL_GEN(dev_priv) == 11) 3399 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3400 level, INTEL_OUTPUT_HDMI); 3401 else if (IS_CANNONLAKE(dev_priv)) 3402 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3403 else if (IS_GEN9_LP(dev_priv)) 3404 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3405 else 3406 intel_prepare_hdmi_ddi_buffers(encoder, level); 3407 3408 if (IS_GEN9_BC(dev_priv)) 3409 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3410 3411 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3412 3413 dig_port->set_infoframes(encoder, 3414 crtc_state->has_infoframe, 3415 crtc_state, conn_state); 3416 } 3417 3418 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3419 struct intel_encoder *encoder, 3420 const struct intel_crtc_state *crtc_state, 3421 const struct drm_connector_state *conn_state) 3422 { 3423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3424 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3425 enum pipe pipe = crtc->pipe; 3426 3427 /* 3428 * When called from DP MST code: 3429 * - conn_state will be NULL 3430 * - encoder will be the main encoder (ie. mst->primary) 3431 * - the main connector associated with this port 3432 * won't be active or linked to a crtc 3433 * - crtc_state will be the state of the first stream to 3434 * be activated on this port, and it may not be the same 3435 * stream that will be deactivated last, but each stream 3436 * should have a state that is identical when it comes to 3437 * the DP link parameteres 3438 */ 3439 3440 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3441 3442 if (INTEL_GEN(dev_priv) >= 11) 3443 icl_map_plls_to_ports(encoder, crtc_state); 3444 3445 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3446 3447 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3448 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3449 conn_state); 3450 } else { 3451 struct intel_lspcon *lspcon = 3452 enc_to_intel_lspcon(encoder); 3453 3454 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3455 conn_state); 3456 if (lspcon->active) { 3457 struct intel_digital_port *dig_port = 3458 enc_to_dig_port(encoder); 3459 3460 dig_port->set_infoframes(encoder, 3461 crtc_state->has_infoframe, 3462 crtc_state, conn_state); 3463 } 3464 } 3465 } 3466 3467 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3468 const struct intel_crtc_state *crtc_state) 3469 { 3470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3471 enum port port = encoder->port; 3472 bool wait = false; 3473 u32 val; 3474 3475 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3476 if (val & DDI_BUF_CTL_ENABLE) { 3477 val &= ~DDI_BUF_CTL_ENABLE; 3478 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3479 wait = true; 3480 } 3481 3482 if (intel_crtc_has_dp_encoder(crtc_state)) { 3483 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3484 3485 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3486 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3487 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3488 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3489 } 3490 3491 /* Disable FEC in DP Sink */ 3492 intel_ddi_disable_fec_state(encoder, crtc_state); 3493 3494 if (wait) 3495 intel_wait_ddi_buf_idle(dev_priv, port); 3496 } 3497 3498 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3499 struct intel_encoder *encoder, 3500 const struct intel_crtc_state *old_crtc_state, 3501 const struct drm_connector_state *old_conn_state) 3502 { 3503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3504 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3505 struct intel_dp *intel_dp = &dig_port->dp; 3506 bool is_mst = intel_crtc_has_type(old_crtc_state, 3507 INTEL_OUTPUT_DP_MST); 3508 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3509 3510 if (!is_mst) 3511 intel_dp_set_infoframes(encoder, false, 3512 old_crtc_state, old_conn_state); 3513 3514 /* 3515 * Power down sink before disabling the port, otherwise we end 3516 * up getting interrupts from the sink on detecting link loss. 3517 */ 3518 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3519 3520 if (INTEL_GEN(dev_priv) >= 12) { 3521 if (is_mst) { 3522 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3523 u32 val; 3524 3525 val = intel_de_read(dev_priv, 3526 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3527 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3528 TRANS_DDI_MODE_SELECT_MASK); 3529 intel_de_write(dev_priv, 3530 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3531 val); 3532 } 3533 } else { 3534 if (!is_mst) 3535 intel_ddi_disable_pipe_clock(old_crtc_state); 3536 } 3537 3538 intel_disable_ddi_buf(encoder, old_crtc_state); 3539 3540 /* 3541 * From TGL spec: "If single stream or multi-stream master transcoder: 3542 * Configure Transcoder Clock select to direct no clock to the 3543 * transcoder" 3544 */ 3545 if (INTEL_GEN(dev_priv) >= 12) 3546 intel_ddi_disable_pipe_clock(old_crtc_state); 3547 3548 intel_edp_panel_vdd_on(intel_dp); 3549 intel_edp_panel_off(intel_dp); 3550 3551 if (!intel_phy_is_tc(dev_priv, phy) || 3552 dig_port->tc_mode != TC_PORT_TBT_ALT) 3553 intel_display_power_put_unchecked(dev_priv, 3554 dig_port->ddi_io_power_domain); 3555 3556 intel_ddi_clk_disable(encoder); 3557 } 3558 3559 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3560 struct intel_encoder *encoder, 3561 const struct intel_crtc_state *old_crtc_state, 3562 const struct drm_connector_state *old_conn_state) 3563 { 3564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3565 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3566 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3567 3568 dig_port->set_infoframes(encoder, false, 3569 old_crtc_state, old_conn_state); 3570 3571 intel_ddi_disable_pipe_clock(old_crtc_state); 3572 3573 intel_disable_ddi_buf(encoder, old_crtc_state); 3574 3575 intel_display_power_put_unchecked(dev_priv, 3576 dig_port->ddi_io_power_domain); 3577 3578 intel_ddi_clk_disable(encoder); 3579 3580 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3581 } 3582 3583 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3584 struct intel_encoder *encoder, 3585 const struct intel_crtc_state *old_crtc_state, 3586 const struct drm_connector_state *old_conn_state) 3587 { 3588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3589 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3590 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3591 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3592 3593 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3594 intel_crtc_vblank_off(old_crtc_state); 3595 3596 intel_disable_pipe(old_crtc_state); 3597 3598 intel_ddi_disable_transcoder_func(old_crtc_state); 3599 3600 intel_dsc_disable(old_crtc_state); 3601 3602 if (INTEL_GEN(dev_priv) >= 9) 3603 skl_scaler_disable(old_crtc_state); 3604 else 3605 ilk_pfit_disable(old_crtc_state); 3606 } 3607 3608 /* 3609 * When called from DP MST code: 3610 * - old_conn_state will be NULL 3611 * - encoder will be the main encoder (ie. mst->primary) 3612 * - the main connector associated with this port 3613 * won't be active or linked to a crtc 3614 * - old_crtc_state will be the state of the last stream to 3615 * be deactivated on this port, and it may not be the same 3616 * stream that was activated last, but each stream 3617 * should have a state that is identical when it comes to 3618 * the DP link parameteres 3619 */ 3620 3621 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3622 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3623 old_conn_state); 3624 else 3625 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3626 old_conn_state); 3627 3628 if (INTEL_GEN(dev_priv) >= 11) 3629 icl_unmap_plls_to_ports(encoder); 3630 3631 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3632 intel_display_power_put_unchecked(dev_priv, 3633 intel_ddi_main_link_aux_domain(dig_port)); 3634 3635 if (is_tc_port) 3636 intel_tc_port_put_link(dig_port); 3637 } 3638 3639 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3640 struct intel_encoder *encoder, 3641 const struct intel_crtc_state *old_crtc_state, 3642 const struct drm_connector_state *old_conn_state) 3643 { 3644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3645 u32 val; 3646 3647 /* 3648 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3649 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3650 * step 13 is the correct place for it. Step 18 is where it was 3651 * originally before the BUN. 3652 */ 3653 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3654 val &= ~FDI_RX_ENABLE; 3655 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3656 3657 intel_disable_ddi_buf(encoder, old_crtc_state); 3658 intel_ddi_clk_disable(encoder); 3659 3660 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3661 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3662 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3663 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3664 3665 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3666 val &= ~FDI_PCDCLK; 3667 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3668 3669 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3670 val &= ~FDI_RX_PLL_ENABLE; 3671 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3672 } 3673 3674 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3675 struct intel_encoder *encoder, 3676 const struct intel_crtc_state *crtc_state) 3677 { 3678 const struct drm_connector_state *conn_state; 3679 struct drm_connector *conn; 3680 int i; 3681 3682 if (!crtc_state->sync_mode_slaves_mask) 3683 return; 3684 3685 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3686 struct intel_encoder *slave_encoder = 3687 to_intel_encoder(conn_state->best_encoder); 3688 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3689 const struct intel_crtc_state *slave_crtc_state; 3690 3691 if (!slave_crtc) 3692 continue; 3693 3694 slave_crtc_state = 3695 intel_atomic_get_new_crtc_state(state, slave_crtc); 3696 3697 if (slave_crtc_state->master_transcoder != 3698 crtc_state->cpu_transcoder) 3699 continue; 3700 3701 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder)); 3702 } 3703 3704 usleep_range(200, 400); 3705 3706 intel_dp_stop_link_train(enc_to_intel_dp(encoder)); 3707 } 3708 3709 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3710 struct intel_encoder *encoder, 3711 const struct intel_crtc_state *crtc_state, 3712 const struct drm_connector_state *conn_state) 3713 { 3714 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3715 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3716 enum port port = encoder->port; 3717 3718 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3719 intel_dp_stop_link_train(intel_dp); 3720 3721 intel_edp_backlight_on(crtc_state, conn_state); 3722 intel_psr_enable(intel_dp, crtc_state, conn_state); 3723 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3724 intel_edp_drrs_enable(intel_dp, crtc_state); 3725 3726 if (crtc_state->has_audio) 3727 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3728 3729 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3730 } 3731 3732 static i915_reg_t 3733 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3734 enum port port) 3735 { 3736 static const enum transcoder trans[] = { 3737 [PORT_A] = TRANSCODER_EDP, 3738 [PORT_B] = TRANSCODER_A, 3739 [PORT_C] = TRANSCODER_B, 3740 [PORT_D] = TRANSCODER_C, 3741 [PORT_E] = TRANSCODER_A, 3742 }; 3743 3744 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3745 3746 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3747 port = PORT_A; 3748 3749 return CHICKEN_TRANS(trans[port]); 3750 } 3751 3752 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3753 struct intel_encoder *encoder, 3754 const struct intel_crtc_state *crtc_state, 3755 const struct drm_connector_state *conn_state) 3756 { 3757 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3758 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3759 struct drm_connector *connector = conn_state->connector; 3760 enum port port = encoder->port; 3761 3762 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3763 crtc_state->hdmi_high_tmds_clock_ratio, 3764 crtc_state->hdmi_scrambling)) 3765 drm_dbg_kms(&dev_priv->drm, 3766 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3767 connector->base.id, connector->name); 3768 3769 /* Display WA #1143: skl,kbl,cfl */ 3770 if (IS_GEN9_BC(dev_priv)) { 3771 /* 3772 * For some reason these chicken bits have been 3773 * stuffed into a transcoder register, event though 3774 * the bits affect a specific DDI port rather than 3775 * a specific transcoder. 3776 */ 3777 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3778 u32 val; 3779 3780 val = intel_de_read(dev_priv, reg); 3781 3782 if (port == PORT_E) 3783 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3784 DDIE_TRAINING_OVERRIDE_VALUE; 3785 else 3786 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3787 DDI_TRAINING_OVERRIDE_VALUE; 3788 3789 intel_de_write(dev_priv, reg, val); 3790 intel_de_posting_read(dev_priv, reg); 3791 3792 udelay(1); 3793 3794 if (port == PORT_E) 3795 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3796 DDIE_TRAINING_OVERRIDE_VALUE); 3797 else 3798 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3799 DDI_TRAINING_OVERRIDE_VALUE); 3800 3801 intel_de_write(dev_priv, reg, val); 3802 } 3803 3804 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3805 * are ignored so nothing special needs to be done besides 3806 * enabling the port. 3807 */ 3808 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3809 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3810 3811 if (crtc_state->has_audio) 3812 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3813 } 3814 3815 static void intel_enable_ddi(struct intel_atomic_state *state, 3816 struct intel_encoder *encoder, 3817 const struct intel_crtc_state *crtc_state, 3818 const struct drm_connector_state *conn_state) 3819 { 3820 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3821 3822 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3823 3824 intel_enable_pipe(crtc_state); 3825 3826 intel_crtc_vblank_on(crtc_state); 3827 3828 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3829 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3830 else 3831 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3832 3833 /* Enable hdcp if it's desired */ 3834 if (conn_state->content_protection == 3835 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3836 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3837 crtc_state->cpu_transcoder, 3838 (u8)conn_state->hdcp_content_type); 3839 } 3840 3841 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3842 struct intel_encoder *encoder, 3843 const struct intel_crtc_state *old_crtc_state, 3844 const struct drm_connector_state *old_conn_state) 3845 { 3846 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3847 3848 intel_dp->link_trained = false; 3849 3850 if (old_crtc_state->has_audio) 3851 intel_audio_codec_disable(encoder, 3852 old_crtc_state, old_conn_state); 3853 3854 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3855 intel_psr_disable(intel_dp, old_crtc_state); 3856 intel_edp_backlight_off(old_conn_state); 3857 /* Disable the decompression in DP Sink */ 3858 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3859 false); 3860 } 3861 3862 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3863 struct intel_encoder *encoder, 3864 const struct intel_crtc_state *old_crtc_state, 3865 const struct drm_connector_state *old_conn_state) 3866 { 3867 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3868 struct drm_connector *connector = old_conn_state->connector; 3869 3870 if (old_crtc_state->has_audio) 3871 intel_audio_codec_disable(encoder, 3872 old_crtc_state, old_conn_state); 3873 3874 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3875 false, false)) 3876 drm_dbg_kms(&i915->drm, 3877 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3878 connector->base.id, connector->name); 3879 } 3880 3881 static void intel_disable_ddi(struct intel_atomic_state *state, 3882 struct intel_encoder *encoder, 3883 const struct intel_crtc_state *old_crtc_state, 3884 const struct drm_connector_state *old_conn_state) 3885 { 3886 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3887 3888 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3889 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3890 old_conn_state); 3891 else 3892 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3893 old_conn_state); 3894 } 3895 3896 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3897 struct intel_encoder *encoder, 3898 const struct intel_crtc_state *crtc_state, 3899 const struct drm_connector_state *conn_state) 3900 { 3901 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3902 3903 intel_ddi_set_dp_msa(crtc_state, conn_state); 3904 3905 intel_psr_update(intel_dp, crtc_state, conn_state); 3906 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3907 intel_edp_drrs_enable(intel_dp, crtc_state); 3908 3909 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3910 } 3911 3912 static void intel_ddi_update_pipe(struct intel_atomic_state *state, 3913 struct intel_encoder *encoder, 3914 const struct intel_crtc_state *crtc_state, 3915 const struct drm_connector_state *conn_state) 3916 { 3917 3918 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3919 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3920 conn_state); 3921 3922 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3923 } 3924 3925 static void 3926 intel_ddi_update_prepare(struct intel_atomic_state *state, 3927 struct intel_encoder *encoder, 3928 struct intel_crtc *crtc) 3929 { 3930 struct intel_crtc_state *crtc_state = 3931 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3932 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3933 3934 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3935 3936 intel_tc_port_get_link(enc_to_dig_port(encoder), 3937 required_lanes); 3938 if (crtc_state && crtc_state->hw.active) 3939 intel_update_active_dpll(state, crtc, encoder); 3940 } 3941 3942 static void 3943 intel_ddi_update_complete(struct intel_atomic_state *state, 3944 struct intel_encoder *encoder, 3945 struct intel_crtc *crtc) 3946 { 3947 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3948 } 3949 3950 static void 3951 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3952 struct intel_encoder *encoder, 3953 const struct intel_crtc_state *crtc_state, 3954 const struct drm_connector_state *conn_state) 3955 { 3956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3957 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3958 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3959 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3960 3961 if (is_tc_port) 3962 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3963 3964 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3965 intel_display_power_get(dev_priv, 3966 intel_ddi_main_link_aux_domain(dig_port)); 3967 3968 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3969 /* 3970 * Program the lane count for static/dynamic connections on 3971 * Type-C ports. Skip this step for TBT. 3972 */ 3973 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3974 else if (IS_GEN9_LP(dev_priv)) 3975 bxt_ddi_phy_set_lane_optim_mask(encoder, 3976 crtc_state->lane_lat_optim_mask); 3977 } 3978 3979 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3980 { 3981 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3982 struct drm_i915_private *dev_priv = 3983 to_i915(intel_dig_port->base.base.dev); 3984 enum port port = intel_dig_port->base.port; 3985 u32 dp_tp_ctl, ddi_buf_ctl; 3986 bool wait = false; 3987 3988 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3989 3990 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3991 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3992 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3993 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3994 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3995 wait = true; 3996 } 3997 3998 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3999 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4000 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4001 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4002 4003 if (wait) 4004 intel_wait_ddi_buf_idle(dev_priv, port); 4005 } 4006 4007 dp_tp_ctl = DP_TP_CTL_ENABLE | 4008 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4009 if (intel_dp->link_mst) 4010 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4011 else { 4012 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4013 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4014 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4015 } 4016 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4017 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4018 4019 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4020 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4021 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4022 4023 udelay(600); 4024 } 4025 4026 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 4027 u8 dp_train_pat) 4028 { 4029 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4030 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); 4031 enum port port = dp_to_dig_port(intel_dp)->base.port; 4032 u32 temp; 4033 4034 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4035 4036 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 4037 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 4038 else 4039 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 4040 4041 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4042 switch (dp_train_pat & train_pat_mask) { 4043 case DP_TRAINING_PATTERN_DISABLE: 4044 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4045 break; 4046 case DP_TRAINING_PATTERN_1: 4047 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4048 break; 4049 case DP_TRAINING_PATTERN_2: 4050 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4051 break; 4052 case DP_TRAINING_PATTERN_3: 4053 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4054 break; 4055 case DP_TRAINING_PATTERN_4: 4056 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4057 break; 4058 } 4059 4060 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); 4061 4062 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4063 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4064 } 4065 4066 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp) 4067 { 4068 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4069 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4070 enum port port = encoder->port; 4071 u32 val; 4072 4073 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4074 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4075 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4076 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 4077 4078 /* 4079 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4080 * reason we need to set idle transmission mode is to work around a HW 4081 * issue where we enable the pipe while not in idle link-training mode. 4082 * In this case there is requirement to wait for a minimum number of 4083 * idle patterns to be sent. 4084 */ 4085 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4086 return; 4087 4088 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 4089 DP_TP_STATUS_IDLE_DONE, 1)) 4090 drm_err(&dev_priv->drm, 4091 "Timed out waiting for DP idle patterns\n"); 4092 } 4093 4094 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4095 enum transcoder cpu_transcoder) 4096 { 4097 if (cpu_transcoder == TRANSCODER_EDP) 4098 return false; 4099 4100 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4101 return false; 4102 4103 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4104 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4105 } 4106 4107 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4108 struct intel_crtc_state *crtc_state) 4109 { 4110 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4111 crtc_state->min_voltage_level = 2; 4112 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 4113 crtc_state->min_voltage_level = 3; 4114 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4115 crtc_state->min_voltage_level = 1; 4116 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4117 crtc_state->min_voltage_level = 2; 4118 } 4119 4120 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4121 enum transcoder cpu_transcoder) 4122 { 4123 u32 master_select; 4124 4125 if (INTEL_GEN(dev_priv) >= 11) { 4126 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4127 4128 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4129 return INVALID_TRANSCODER; 4130 4131 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4132 } else { 4133 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4134 4135 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4136 return INVALID_TRANSCODER; 4137 4138 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4139 } 4140 4141 if (master_select == 0) 4142 return TRANSCODER_EDP; 4143 else 4144 return master_select - 1; 4145 } 4146 4147 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4148 { 4149 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4150 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4151 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4152 enum transcoder cpu_transcoder; 4153 4154 crtc_state->master_transcoder = 4155 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4156 4157 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4158 enum intel_display_power_domain power_domain; 4159 intel_wakeref_t trans_wakeref; 4160 4161 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4162 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4163 power_domain); 4164 4165 if (!trans_wakeref) 4166 continue; 4167 4168 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4169 crtc_state->cpu_transcoder) 4170 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4171 4172 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4173 } 4174 4175 drm_WARN_ON(&dev_priv->drm, 4176 crtc_state->master_transcoder != INVALID_TRANSCODER && 4177 crtc_state->sync_mode_slaves_mask); 4178 } 4179 4180 void intel_ddi_get_config(struct intel_encoder *encoder, 4181 struct intel_crtc_state *pipe_config) 4182 { 4183 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4184 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4185 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4186 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4187 u32 temp, flags = 0; 4188 4189 /* XXX: DSI transcoder paranoia */ 4190 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4191 return; 4192 4193 intel_dsc_get_config(encoder, pipe_config); 4194 4195 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4196 if (temp & TRANS_DDI_PHSYNC) 4197 flags |= DRM_MODE_FLAG_PHSYNC; 4198 else 4199 flags |= DRM_MODE_FLAG_NHSYNC; 4200 if (temp & TRANS_DDI_PVSYNC) 4201 flags |= DRM_MODE_FLAG_PVSYNC; 4202 else 4203 flags |= DRM_MODE_FLAG_NVSYNC; 4204 4205 pipe_config->hw.adjusted_mode.flags |= flags; 4206 4207 switch (temp & TRANS_DDI_BPC_MASK) { 4208 case TRANS_DDI_BPC_6: 4209 pipe_config->pipe_bpp = 18; 4210 break; 4211 case TRANS_DDI_BPC_8: 4212 pipe_config->pipe_bpp = 24; 4213 break; 4214 case TRANS_DDI_BPC_10: 4215 pipe_config->pipe_bpp = 30; 4216 break; 4217 case TRANS_DDI_BPC_12: 4218 pipe_config->pipe_bpp = 36; 4219 break; 4220 default: 4221 break; 4222 } 4223 4224 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4225 case TRANS_DDI_MODE_SELECT_HDMI: 4226 pipe_config->has_hdmi_sink = true; 4227 4228 pipe_config->infoframes.enable |= 4229 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4230 4231 if (pipe_config->infoframes.enable) 4232 pipe_config->has_infoframe = true; 4233 4234 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4235 pipe_config->hdmi_scrambling = true; 4236 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4237 pipe_config->hdmi_high_tmds_clock_ratio = true; 4238 /* fall through */ 4239 case TRANS_DDI_MODE_SELECT_DVI: 4240 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4241 pipe_config->lane_count = 4; 4242 break; 4243 case TRANS_DDI_MODE_SELECT_FDI: 4244 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4245 break; 4246 case TRANS_DDI_MODE_SELECT_DP_SST: 4247 if (encoder->type == INTEL_OUTPUT_EDP) 4248 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4249 else 4250 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4251 pipe_config->lane_count = 4252 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4253 intel_dp_get_m_n(intel_crtc, pipe_config); 4254 4255 if (INTEL_GEN(dev_priv) >= 11) { 4256 i915_reg_t dp_tp_ctl; 4257 4258 if (IS_GEN(dev_priv, 11)) 4259 dp_tp_ctl = DP_TP_CTL(encoder->port); 4260 else 4261 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4262 4263 pipe_config->fec_enable = 4264 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4265 4266 drm_dbg_kms(&dev_priv->drm, 4267 "[ENCODER:%d:%s] Fec status: %u\n", 4268 encoder->base.base.id, encoder->base.name, 4269 pipe_config->fec_enable); 4270 } 4271 4272 pipe_config->infoframes.enable |= 4273 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4274 4275 break; 4276 case TRANS_DDI_MODE_SELECT_DP_MST: 4277 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4278 pipe_config->lane_count = 4279 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4280 4281 if (INTEL_GEN(dev_priv) >= 12) 4282 pipe_config->mst_master_transcoder = 4283 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4284 4285 intel_dp_get_m_n(intel_crtc, pipe_config); 4286 4287 pipe_config->infoframes.enable |= 4288 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4289 break; 4290 default: 4291 break; 4292 } 4293 4294 if (INTEL_GEN(dev_priv) >= 12) { 4295 enum transcoder transcoder = 4296 intel_dp_mst_is_slave_trans(pipe_config) ? 4297 pipe_config->mst_master_transcoder : 4298 pipe_config->cpu_transcoder; 4299 4300 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 4301 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 4302 } 4303 4304 pipe_config->has_audio = 4305 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4306 4307 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4308 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4309 /* 4310 * This is a big fat ugly hack. 4311 * 4312 * Some machines in UEFI boot mode provide us a VBT that has 18 4313 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4314 * unknown we fail to light up. Yet the same BIOS boots up with 4315 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4316 * max, not what it tells us to use. 4317 * 4318 * Note: This will still be broken if the eDP panel is not lit 4319 * up by the BIOS, and thus we can't get the mode at module 4320 * load. 4321 */ 4322 drm_dbg_kms(&dev_priv->drm, 4323 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4324 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4325 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4326 } 4327 4328 intel_ddi_clock_get(encoder, pipe_config); 4329 4330 if (IS_GEN9_LP(dev_priv)) 4331 pipe_config->lane_lat_optim_mask = 4332 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4333 4334 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4335 4336 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4337 4338 intel_read_infoframe(encoder, pipe_config, 4339 HDMI_INFOFRAME_TYPE_AVI, 4340 &pipe_config->infoframes.avi); 4341 intel_read_infoframe(encoder, pipe_config, 4342 HDMI_INFOFRAME_TYPE_SPD, 4343 &pipe_config->infoframes.spd); 4344 intel_read_infoframe(encoder, pipe_config, 4345 HDMI_INFOFRAME_TYPE_VENDOR, 4346 &pipe_config->infoframes.hdmi); 4347 intel_read_infoframe(encoder, pipe_config, 4348 HDMI_INFOFRAME_TYPE_DRM, 4349 &pipe_config->infoframes.drm); 4350 4351 if (INTEL_GEN(dev_priv) >= 8) 4352 bdw_get_trans_port_sync_config(pipe_config); 4353 4354 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4355 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4356 } 4357 4358 static enum intel_output_type 4359 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4360 struct intel_crtc_state *crtc_state, 4361 struct drm_connector_state *conn_state) 4362 { 4363 switch (conn_state->connector->connector_type) { 4364 case DRM_MODE_CONNECTOR_HDMIA: 4365 return INTEL_OUTPUT_HDMI; 4366 case DRM_MODE_CONNECTOR_eDP: 4367 return INTEL_OUTPUT_EDP; 4368 case DRM_MODE_CONNECTOR_DisplayPort: 4369 return INTEL_OUTPUT_DP; 4370 default: 4371 MISSING_CASE(conn_state->connector->connector_type); 4372 return INTEL_OUTPUT_UNUSED; 4373 } 4374 } 4375 4376 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4377 struct intel_crtc_state *pipe_config, 4378 struct drm_connector_state *conn_state) 4379 { 4380 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4382 enum port port = encoder->port; 4383 int ret; 4384 4385 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4386 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4387 4388 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4389 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4390 } else { 4391 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4392 } 4393 4394 if (ret) 4395 return ret; 4396 4397 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4398 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4399 pipe_config->pch_pfit.force_thru = 4400 pipe_config->pch_pfit.enabled || 4401 pipe_config->crc_enabled; 4402 4403 if (IS_GEN9_LP(dev_priv)) 4404 pipe_config->lane_lat_optim_mask = 4405 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4406 4407 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4408 4409 return 0; 4410 } 4411 4412 static bool mode_equal(const struct drm_display_mode *mode1, 4413 const struct drm_display_mode *mode2) 4414 { 4415 return drm_mode_match(mode1, mode2, 4416 DRM_MODE_MATCH_TIMINGS | 4417 DRM_MODE_MATCH_FLAGS | 4418 DRM_MODE_MATCH_3D_FLAGS) && 4419 mode1->clock == mode2->clock; /* we want an exact match */ 4420 } 4421 4422 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4423 const struct intel_link_m_n *m_n_2) 4424 { 4425 return m_n_1->tu == m_n_2->tu && 4426 m_n_1->gmch_m == m_n_2->gmch_m && 4427 m_n_1->gmch_n == m_n_2->gmch_n && 4428 m_n_1->link_m == m_n_2->link_m && 4429 m_n_1->link_n == m_n_2->link_n; 4430 } 4431 4432 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4433 const struct intel_crtc_state *crtc_state2) 4434 { 4435 return crtc_state1->hw.active && crtc_state2->hw.active && 4436 crtc_state1->output_types == crtc_state2->output_types && 4437 crtc_state1->output_format == crtc_state2->output_format && 4438 crtc_state1->lane_count == crtc_state2->lane_count && 4439 crtc_state1->port_clock == crtc_state2->port_clock && 4440 mode_equal(&crtc_state1->hw.adjusted_mode, 4441 &crtc_state2->hw.adjusted_mode) && 4442 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4443 } 4444 4445 static u8 4446 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4447 int tile_group_id) 4448 { 4449 struct drm_connector *connector; 4450 const struct drm_connector_state *conn_state; 4451 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4452 struct intel_atomic_state *state = 4453 to_intel_atomic_state(ref_crtc_state->uapi.state); 4454 u8 transcoders = 0; 4455 int i; 4456 4457 /* 4458 * We don't enable port sync on BDW due to missing w/as and 4459 * due to not having adjusted the modeset sequence appropriately. 4460 */ 4461 if (INTEL_GEN(dev_priv) < 9) 4462 return 0; 4463 4464 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4465 return 0; 4466 4467 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4468 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4469 const struct intel_crtc_state *crtc_state; 4470 4471 if (!crtc) 4472 continue; 4473 4474 if (!connector->has_tile || 4475 connector->tile_group->id != 4476 tile_group_id) 4477 continue; 4478 crtc_state = intel_atomic_get_new_crtc_state(state, 4479 crtc); 4480 if (!crtcs_port_sync_compatible(ref_crtc_state, 4481 crtc_state)) 4482 continue; 4483 transcoders |= BIT(crtc_state->cpu_transcoder); 4484 } 4485 4486 return transcoders; 4487 } 4488 4489 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4490 struct intel_crtc_state *crtc_state, 4491 struct drm_connector_state *conn_state) 4492 { 4493 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4494 struct drm_connector *connector = conn_state->connector; 4495 u8 port_sync_transcoders = 0; 4496 4497 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4498 encoder->base.base.id, encoder->base.name, 4499 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4500 4501 if (connector->has_tile) 4502 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4503 connector->tile_group->id); 4504 4505 /* 4506 * EDP Transcoders cannot be ensalved 4507 * make them a master always when present 4508 */ 4509 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4510 crtc_state->master_transcoder = TRANSCODER_EDP; 4511 else 4512 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4513 4514 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4515 crtc_state->master_transcoder = INVALID_TRANSCODER; 4516 crtc_state->sync_mode_slaves_mask = 4517 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4518 } 4519 4520 return 0; 4521 } 4522 4523 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4524 { 4525 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4526 4527 intel_dp_encoder_flush_work(encoder); 4528 4529 drm_encoder_cleanup(encoder); 4530 kfree(dig_port); 4531 } 4532 4533 static const struct drm_encoder_funcs intel_ddi_funcs = { 4534 .reset = intel_dp_encoder_reset, 4535 .destroy = intel_ddi_encoder_destroy, 4536 }; 4537 4538 static struct intel_connector * 4539 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4540 { 4541 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 4542 struct intel_connector *connector; 4543 enum port port = intel_dig_port->base.port; 4544 4545 connector = intel_connector_alloc(); 4546 if (!connector) 4547 return NULL; 4548 4549 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4550 intel_dig_port->dp.prepare_link_retrain = 4551 intel_ddi_prepare_link_retrain; 4552 intel_dig_port->dp.set_link_train = intel_ddi_set_link_train; 4553 intel_dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4554 4555 if (INTEL_GEN(dev_priv) >= 12) 4556 intel_dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4557 else if (INTEL_GEN(dev_priv) >= 11) 4558 intel_dig_port->dp.set_signal_levels = icl_set_signal_levels; 4559 else if (IS_CANNONLAKE(dev_priv)) 4560 intel_dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4561 else if (IS_GEN9_LP(dev_priv)) 4562 intel_dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4563 else 4564 intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4565 4566 intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4567 intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4568 4569 if (INTEL_GEN(dev_priv) < 12) { 4570 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); 4571 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); 4572 } 4573 4574 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4575 kfree(connector); 4576 return NULL; 4577 } 4578 4579 return connector; 4580 } 4581 4582 static int modeset_pipe(struct drm_crtc *crtc, 4583 struct drm_modeset_acquire_ctx *ctx) 4584 { 4585 struct drm_atomic_state *state; 4586 struct drm_crtc_state *crtc_state; 4587 int ret; 4588 4589 state = drm_atomic_state_alloc(crtc->dev); 4590 if (!state) 4591 return -ENOMEM; 4592 4593 state->acquire_ctx = ctx; 4594 4595 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4596 if (IS_ERR(crtc_state)) { 4597 ret = PTR_ERR(crtc_state); 4598 goto out; 4599 } 4600 4601 crtc_state->connectors_changed = true; 4602 4603 ret = drm_atomic_commit(state); 4604 out: 4605 drm_atomic_state_put(state); 4606 4607 return ret; 4608 } 4609 4610 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4611 struct drm_modeset_acquire_ctx *ctx) 4612 { 4613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4614 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4615 struct intel_connector *connector = hdmi->attached_connector; 4616 struct i2c_adapter *adapter = 4617 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4618 struct drm_connector_state *conn_state; 4619 struct intel_crtc_state *crtc_state; 4620 struct intel_crtc *crtc; 4621 u8 config; 4622 int ret; 4623 4624 if (!connector || connector->base.status != connector_status_connected) 4625 return 0; 4626 4627 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4628 ctx); 4629 if (ret) 4630 return ret; 4631 4632 conn_state = connector->base.state; 4633 4634 crtc = to_intel_crtc(conn_state->crtc); 4635 if (!crtc) 4636 return 0; 4637 4638 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4639 if (ret) 4640 return ret; 4641 4642 crtc_state = to_intel_crtc_state(crtc->base.state); 4643 4644 drm_WARN_ON(&dev_priv->drm, 4645 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4646 4647 if (!crtc_state->hw.active) 4648 return 0; 4649 4650 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4651 !crtc_state->hdmi_scrambling) 4652 return 0; 4653 4654 if (conn_state->commit && 4655 !try_wait_for_completion(&conn_state->commit->hw_done)) 4656 return 0; 4657 4658 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4659 if (ret < 0) { 4660 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4661 ret); 4662 return 0; 4663 } 4664 4665 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4666 crtc_state->hdmi_high_tmds_clock_ratio && 4667 !!(config & SCDC_SCRAMBLING_ENABLE) == 4668 crtc_state->hdmi_scrambling) 4669 return 0; 4670 4671 /* 4672 * HDMI 2.0 says that one should not send scrambled data 4673 * prior to configuring the sink scrambling, and that 4674 * TMDS clock/data transmission should be suspended when 4675 * changing the TMDS clock rate in the sink. So let's 4676 * just do a full modeset here, even though some sinks 4677 * would be perfectly happy if were to just reconfigure 4678 * the SCDC settings on the fly. 4679 */ 4680 return modeset_pipe(&crtc->base, ctx); 4681 } 4682 4683 static enum intel_hotplug_state 4684 intel_ddi_hotplug(struct intel_encoder *encoder, 4685 struct intel_connector *connector) 4686 { 4687 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4688 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4689 enum phy phy = intel_port_to_phy(i915, encoder->port); 4690 bool is_tc = intel_phy_is_tc(i915, phy); 4691 struct drm_modeset_acquire_ctx ctx; 4692 enum intel_hotplug_state state; 4693 int ret; 4694 4695 state = intel_encoder_hotplug(encoder, connector); 4696 4697 drm_modeset_acquire_init(&ctx, 0); 4698 4699 for (;;) { 4700 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4701 ret = intel_hdmi_reset_link(encoder, &ctx); 4702 else 4703 ret = intel_dp_retrain_link(encoder, &ctx); 4704 4705 if (ret == -EDEADLK) { 4706 drm_modeset_backoff(&ctx); 4707 continue; 4708 } 4709 4710 break; 4711 } 4712 4713 drm_modeset_drop_locks(&ctx); 4714 drm_modeset_acquire_fini(&ctx); 4715 drm_WARN(encoder->base.dev, ret, 4716 "Acquiring modeset locks failed with %i\n", ret); 4717 4718 /* 4719 * Unpowered type-c dongles can take some time to boot and be 4720 * responsible, so here giving some time to those dongles to power up 4721 * and then retrying the probe. 4722 * 4723 * On many platforms the HDMI live state signal is known to be 4724 * unreliable, so we can't use it to detect if a sink is connected or 4725 * not. Instead we detect if it's connected based on whether we can 4726 * read the EDID or not. That in turn has a problem during disconnect, 4727 * since the HPD interrupt may be raised before the DDC lines get 4728 * disconnected (due to how the required length of DDC vs. HPD 4729 * connector pins are specified) and so we'll still be able to get a 4730 * valid EDID. To solve this schedule another detection cycle if this 4731 * time around we didn't detect any change in the sink's connection 4732 * status. 4733 * 4734 * Type-c connectors which get their HPD signal deasserted then 4735 * reasserted, without unplugging/replugging the sink from the 4736 * connector, introduce a delay until the AUX channel communication 4737 * becomes functional. Retry the detection for 5 seconds on type-c 4738 * connectors to account for this delay. 4739 */ 4740 if (state == INTEL_HOTPLUG_UNCHANGED && 4741 connector->hotplug_retries < (is_tc ? 5 : 1) && 4742 !dig_port->dp.is_mst) 4743 state = INTEL_HOTPLUG_RETRY; 4744 4745 return state; 4746 } 4747 4748 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4749 { 4750 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4751 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4752 4753 return intel_de_read(dev_priv, SDEISR) & bit; 4754 } 4755 4756 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4757 { 4758 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4759 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4760 4761 return intel_de_read(dev_priv, DEISR) & bit; 4762 } 4763 4764 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4765 { 4766 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4767 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4768 4769 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4770 } 4771 4772 static struct intel_connector * 4773 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4774 { 4775 struct intel_connector *connector; 4776 enum port port = intel_dig_port->base.port; 4777 4778 connector = intel_connector_alloc(); 4779 if (!connector) 4780 return NULL; 4781 4782 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4783 intel_hdmi_init_connector(intel_dig_port, connector); 4784 4785 return connector; 4786 } 4787 4788 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4789 { 4790 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4791 4792 if (dport->base.port != PORT_A) 4793 return false; 4794 4795 if (dport->saved_port_bits & DDI_A_4_LANES) 4796 return false; 4797 4798 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4799 * supported configuration 4800 */ 4801 if (IS_GEN9_LP(dev_priv)) 4802 return true; 4803 4804 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4805 * one who does also have a full A/E split called 4806 * DDI_F what makes DDI_E useless. However for this 4807 * case let's trust VBT info. 4808 */ 4809 if (IS_CANNONLAKE(dev_priv) && 4810 !intel_bios_is_port_present(dev_priv, PORT_E)) 4811 return true; 4812 4813 return false; 4814 } 4815 4816 static int 4817 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4818 { 4819 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4820 enum port port = intel_dport->base.port; 4821 int max_lanes = 4; 4822 4823 if (INTEL_GEN(dev_priv) >= 11) 4824 return max_lanes; 4825 4826 if (port == PORT_A || port == PORT_E) { 4827 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4828 max_lanes = port == PORT_A ? 4 : 0; 4829 else 4830 /* Both A and E share 2 lanes */ 4831 max_lanes = 2; 4832 } 4833 4834 /* 4835 * Some BIOS might fail to set this bit on port A if eDP 4836 * wasn't lit up at boot. Force this bit set when needed 4837 * so we use the proper lane count for our calculations. 4838 */ 4839 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4840 drm_dbg_kms(&dev_priv->drm, 4841 "Forcing DDI_A_4_LANES for port A\n"); 4842 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4843 max_lanes = 4; 4844 } 4845 4846 return max_lanes; 4847 } 4848 4849 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4850 { 4851 struct intel_digital_port *intel_dig_port; 4852 struct intel_encoder *encoder; 4853 bool init_hdmi, init_dp, init_lspcon = false; 4854 enum phy phy = intel_port_to_phy(dev_priv, port); 4855 4856 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 4857 intel_bios_port_supports_hdmi(dev_priv, port); 4858 init_dp = intel_bios_port_supports_dp(dev_priv, port); 4859 4860 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4861 /* 4862 * Lspcon device needs to be driven with DP connector 4863 * with special detection sequence. So make sure DP 4864 * is initialized before lspcon. 4865 */ 4866 init_dp = true; 4867 init_lspcon = true; 4868 init_hdmi = false; 4869 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4870 port_name(port)); 4871 } 4872 4873 if (!init_dp && !init_hdmi) { 4874 drm_dbg_kms(&dev_priv->drm, 4875 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4876 port_name(port)); 4877 return; 4878 } 4879 4880 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4881 if (!intel_dig_port) 4882 return; 4883 4884 encoder = &intel_dig_port->base; 4885 4886 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4887 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4888 4889 encoder->hotplug = intel_ddi_hotplug; 4890 encoder->compute_output_type = intel_ddi_compute_output_type; 4891 encoder->compute_config = intel_ddi_compute_config; 4892 encoder->compute_config_late = intel_ddi_compute_config_late; 4893 encoder->enable = intel_enable_ddi; 4894 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4895 encoder->pre_enable = intel_ddi_pre_enable; 4896 encoder->disable = intel_disable_ddi; 4897 encoder->post_disable = intel_ddi_post_disable; 4898 encoder->update_pipe = intel_ddi_update_pipe; 4899 encoder->get_hw_state = intel_ddi_get_hw_state; 4900 encoder->get_config = intel_ddi_get_config; 4901 encoder->suspend = intel_dp_encoder_suspend; 4902 encoder->get_power_domains = intel_ddi_get_power_domains; 4903 4904 encoder->type = INTEL_OUTPUT_DDI; 4905 encoder->power_domain = intel_port_to_power_domain(port); 4906 encoder->port = port; 4907 encoder->cloneable = 0; 4908 encoder->pipe_mask = ~0; 4909 4910 if (INTEL_GEN(dev_priv) >= 11) 4911 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4912 DDI_BUF_CTL(port)) & 4913 DDI_BUF_PORT_REVERSAL; 4914 else 4915 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4916 DDI_BUF_CTL(port)) & 4917 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4918 4919 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4920 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4921 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4922 4923 if (intel_phy_is_tc(dev_priv, phy)) { 4924 bool is_legacy = 4925 !intel_bios_port_supports_typec_usb(dev_priv, port) && 4926 !intel_bios_port_supports_tbt(dev_priv, port); 4927 4928 intel_tc_port_init(intel_dig_port, is_legacy); 4929 4930 encoder->update_prepare = intel_ddi_update_prepare; 4931 encoder->update_complete = intel_ddi_update_complete; 4932 } 4933 4934 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4935 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4936 port - PORT_A; 4937 4938 if (init_dp) { 4939 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4940 goto err; 4941 4942 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4943 } 4944 4945 /* In theory we don't need the encoder->type check, but leave it just in 4946 * case we have some really bad VBTs... */ 4947 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4948 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4949 goto err; 4950 } 4951 4952 if (init_lspcon) { 4953 if (lspcon_init(intel_dig_port)) 4954 /* TODO: handle hdmi info frame part */ 4955 drm_dbg_kms(&dev_priv->drm, 4956 "LSPCON init success on port %c\n", 4957 port_name(port)); 4958 else 4959 /* 4960 * LSPCON init faied, but DP init was success, so 4961 * lets try to drive as DP++ port. 4962 */ 4963 drm_err(&dev_priv->drm, 4964 "LSPCON init failed on port %c\n", 4965 port_name(port)); 4966 } 4967 4968 if (INTEL_GEN(dev_priv) >= 11) { 4969 if (intel_phy_is_tc(dev_priv, phy)) 4970 intel_dig_port->connected = intel_tc_port_connected; 4971 else 4972 intel_dig_port->connected = lpt_digital_port_connected; 4973 } else if (INTEL_GEN(dev_priv) >= 8) { 4974 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 4975 intel_dig_port->connected = bdw_digital_port_connected; 4976 else 4977 intel_dig_port->connected = lpt_digital_port_connected; 4978 } else { 4979 if (port == PORT_A) 4980 intel_dig_port->connected = hsw_digital_port_connected; 4981 else 4982 intel_dig_port->connected = lpt_digital_port_connected; 4983 } 4984 4985 intel_infoframe_init(intel_dig_port); 4986 4987 return; 4988 4989 err: 4990 drm_encoder_cleanup(&encoder->base); 4991 kfree(intel_dig_port); 4992 } 4993