1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 37 #include "i915_reg.h" 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_display_utils.h" 56 #include "intel_dkl_phy.h" 57 #include "intel_dkl_phy_regs.h" 58 #include "intel_dp.h" 59 #include "intel_dp_aux.h" 60 #include "intel_dp_link_training.h" 61 #include "intel_dp_mst.h" 62 #include "intel_dp_test.h" 63 #include "intel_dp_tunnel.h" 64 #include "intel_dpio_phy.h" 65 #include "intel_dsi.h" 66 #include "intel_encoder.h" 67 #include "intel_fdi.h" 68 #include "intel_fifo_underrun.h" 69 #include "intel_gmbus.h" 70 #include "intel_hdcp.h" 71 #include "intel_hdmi.h" 72 #include "intel_hotplug.h" 73 #include "intel_hti.h" 74 #include "intel_lspcon.h" 75 #include "intel_lt_phy.h" 76 #include "intel_mg_phy_regs.h" 77 #include "intel_modeset_lock.h" 78 #include "intel_panel.h" 79 #include "intel_pfit.h" 80 #include "intel_pps.h" 81 #include "intel_psr.h" 82 #include "intel_quirks.h" 83 #include "intel_snps_phy.h" 84 #include "intel_step.h" 85 #include "intel_tc.h" 86 #include "intel_vdsc.h" 87 #include "intel_vdsc_regs.h" 88 #include "intel_vrr.h" 89 #include "skl_scaler.h" 90 #include "skl_universal_plane.h" 91 92 static const u8 index_to_dp_signal_levels[] = { 93 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 95 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 96 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 97 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 98 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 99 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 100 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 101 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 102 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 103 }; 104 105 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 106 const struct intel_ddi_buf_trans *trans) 107 { 108 int level; 109 110 level = intel_bios_hdmi_level_shift(encoder->devdata); 111 if (level < 0) 112 level = trans->hdmi_default_entry; 113 114 return level; 115 } 116 117 static bool has_buf_trans_select(struct intel_display *display) 118 { 119 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 120 } 121 122 static bool has_iboost(struct intel_display *display) 123 { 124 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 125 } 126 127 /* 128 * Starting with Haswell, DDI port buffers must be programmed with correct 129 * values in advance. This function programs the correct values for 130 * DP/eDP/FDI use cases. 131 */ 132 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 133 const struct intel_crtc_state *crtc_state) 134 { 135 struct intel_display *display = to_intel_display(encoder); 136 u32 iboost_bit = 0; 137 int i, n_entries; 138 enum port port = encoder->port; 139 const struct intel_ddi_buf_trans *trans; 140 141 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 142 if (drm_WARN_ON_ONCE(display->drm, !trans)) 143 return; 144 145 /* If we're boosting the current, set bit 31 of trans1 */ 146 if (has_iboost(display) && 147 intel_bios_dp_boost_level(encoder->devdata)) 148 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 149 150 for (i = 0; i < n_entries; i++) { 151 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 152 trans->entries[i].hsw.trans1 | iboost_bit); 153 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 154 trans->entries[i].hsw.trans2); 155 } 156 } 157 158 /* 159 * Starting with Haswell, DDI port buffers must be programmed with correct 160 * values in advance. This function programs the correct values for 161 * HDMI/DVI use cases. 162 */ 163 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 164 const struct intel_crtc_state *crtc_state) 165 { 166 struct intel_display *display = to_intel_display(encoder); 167 int level = intel_ddi_level(encoder, crtc_state, 0); 168 u32 iboost_bit = 0; 169 int n_entries; 170 enum port port = encoder->port; 171 const struct intel_ddi_buf_trans *trans; 172 173 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 174 if (drm_WARN_ON_ONCE(display->drm, !trans)) 175 return; 176 177 /* If we're boosting the current, set bit 31 of trans1 */ 178 if (has_iboost(display) && 179 intel_bios_hdmi_boost_level(encoder->devdata)) 180 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 181 182 /* Entry 9 is for HDMI: */ 183 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 184 trans->entries[level].hsw.trans1 | iboost_bit); 185 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 186 trans->entries[level].hsw.trans2); 187 } 188 189 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 190 { 191 if (DISPLAY_VER(display) >= 14) 192 return XELPDP_PORT_BUF_CTL1(display, port); 193 else 194 return DDI_BUF_CTL(port); 195 } 196 197 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 198 { 199 /* 200 * Bspec's platform specific timeouts: 201 * MTL+ : 100 us 202 * BXT : fixed 16 us 203 * HSW-ADL: 8 us 204 * 205 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 206 */ 207 if (display->platform.broxton) { 208 udelay(16); 209 return; 210 } 211 212 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 213 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 214 DDI_BUF_IS_IDLE, 10)) 215 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 216 port_name(port)); 217 } 218 219 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 220 { 221 struct intel_display *display = to_intel_display(encoder); 222 enum port port = encoder->port; 223 224 /* 225 * Bspec's platform specific timeouts: 226 * MTL+ : 10000 us 227 * DG2 : 1200 us 228 * TGL-ADL combo PHY: 1000 us 229 * TGL-ADL TypeC PHY: 3000 us 230 * HSW-ICL : fixed 518 us 231 */ 232 if (DISPLAY_VER(display) < 10) { 233 usleep_range(518, 1000); 234 return; 235 } 236 237 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 238 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 239 DDI_BUF_IS_IDLE, 10)) 240 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 241 port_name(port)); 242 } 243 244 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 245 { 246 switch (pll->info->id) { 247 case DPLL_ID_WRPLL1: 248 return PORT_CLK_SEL_WRPLL1; 249 case DPLL_ID_WRPLL2: 250 return PORT_CLK_SEL_WRPLL2; 251 case DPLL_ID_SPLL: 252 return PORT_CLK_SEL_SPLL; 253 case DPLL_ID_LCPLL_810: 254 return PORT_CLK_SEL_LCPLL_810; 255 case DPLL_ID_LCPLL_1350: 256 return PORT_CLK_SEL_LCPLL_1350; 257 case DPLL_ID_LCPLL_2700: 258 return PORT_CLK_SEL_LCPLL_2700; 259 default: 260 MISSING_CASE(pll->info->id); 261 return PORT_CLK_SEL_NONE; 262 } 263 } 264 265 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 266 const struct intel_crtc_state *crtc_state) 267 { 268 const struct intel_dpll *pll = crtc_state->intel_dpll; 269 int clock = crtc_state->port_clock; 270 const enum intel_dpll_id id = pll->info->id; 271 272 switch (id) { 273 default: 274 /* 275 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 276 * here, so do warn if this get passed in 277 */ 278 MISSING_CASE(id); 279 return DDI_CLK_SEL_NONE; 280 case DPLL_ID_ICL_TBTPLL: 281 switch (clock) { 282 case 162000: 283 return DDI_CLK_SEL_TBT_162; 284 case 270000: 285 return DDI_CLK_SEL_TBT_270; 286 case 540000: 287 return DDI_CLK_SEL_TBT_540; 288 case 810000: 289 return DDI_CLK_SEL_TBT_810; 290 default: 291 MISSING_CASE(clock); 292 return DDI_CLK_SEL_NONE; 293 } 294 case DPLL_ID_ICL_MGPLL1: 295 case DPLL_ID_ICL_MGPLL2: 296 case DPLL_ID_ICL_MGPLL3: 297 case DPLL_ID_ICL_MGPLL4: 298 case DPLL_ID_TGL_MGPLL5: 299 case DPLL_ID_TGL_MGPLL6: 300 return DDI_CLK_SEL_MG; 301 } 302 } 303 304 static u32 ddi_buf_phy_link_rate(int port_clock) 305 { 306 switch (port_clock) { 307 case 162000: 308 return DDI_BUF_PHY_LINK_RATE(0); 309 case 216000: 310 return DDI_BUF_PHY_LINK_RATE(4); 311 case 243000: 312 return DDI_BUF_PHY_LINK_RATE(5); 313 case 270000: 314 return DDI_BUF_PHY_LINK_RATE(1); 315 case 324000: 316 return DDI_BUF_PHY_LINK_RATE(6); 317 case 432000: 318 return DDI_BUF_PHY_LINK_RATE(7); 319 case 540000: 320 return DDI_BUF_PHY_LINK_RATE(2); 321 case 810000: 322 return DDI_BUF_PHY_LINK_RATE(3); 323 default: 324 MISSING_CASE(port_clock); 325 return DDI_BUF_PHY_LINK_RATE(0); 326 } 327 } 328 329 static int dp_phy_lane_stagger_delay(int port_clock) 330 { 331 /* 332 * Return the number of symbol clocks delay used to stagger the 333 * assertion/desassertion of the port lane enables. The target delay 334 * time is 100 ns or greater, return the number of symbols specific to 335 * the provided port_clock (aka link clock) corresponding to this delay 336 * time, i.e. so that 337 * 338 * number_of_symbols * duration_of_one_symbol >= 100 ns 339 * 340 * The delay must be applied only on TypeC DP outputs, for everything else 341 * the delay must be set to 0. 342 * 343 * Return the number of link symbols per 100 ns: 344 * port_clock (10 kHz) -> bits / 100 us 345 * / symbol_size -> symbols / 100 us 346 * / 1000 -> symbols / 100 ns 347 */ 348 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 349 } 350 351 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 352 const struct intel_crtc_state *crtc_state) 353 { 354 struct intel_display *display = to_intel_display(encoder); 355 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 356 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 357 358 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 359 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 360 DDI_BUF_TRANS_SELECT(0); 361 362 if (dig_port->lane_reversal) 363 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 364 if (dig_port->ddi_a_4_lanes) 365 intel_dp->DP |= DDI_A_4_LANES; 366 367 if (DISPLAY_VER(display) >= 14) { 368 if (intel_dp_is_uhbr(crtc_state)) 369 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 370 else 371 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 372 } 373 374 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 375 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 376 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 377 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 378 } 379 380 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 381 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 382 383 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 384 } 385 } 386 387 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 388 { 389 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 390 391 switch (val) { 392 case DDI_CLK_SEL_NONE: 393 return 0; 394 case DDI_CLK_SEL_TBT_162: 395 return 162000; 396 case DDI_CLK_SEL_TBT_270: 397 return 270000; 398 case DDI_CLK_SEL_TBT_540: 399 return 540000; 400 case DDI_CLK_SEL_TBT_810: 401 return 810000; 402 default: 403 MISSING_CASE(val); 404 return 0; 405 } 406 } 407 408 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 409 { 410 /* CRT dotclock is determined via other means */ 411 if (pipe_config->has_pch_encoder) 412 return; 413 414 pipe_config->hw.adjusted_mode.crtc_clock = 415 intel_crtc_dotclock(pipe_config); 416 } 417 418 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 419 const struct drm_connector_state *conn_state) 420 { 421 struct intel_display *display = to_intel_display(crtc_state); 422 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 423 u32 temp; 424 425 if (!intel_crtc_has_dp_encoder(crtc_state)) 426 return; 427 428 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 429 430 temp = DP_MSA_MISC_SYNC_CLOCK; 431 432 switch (crtc_state->pipe_bpp) { 433 case 18: 434 temp |= DP_MSA_MISC_6_BPC; 435 break; 436 case 24: 437 temp |= DP_MSA_MISC_8_BPC; 438 break; 439 case 30: 440 temp |= DP_MSA_MISC_10_BPC; 441 break; 442 case 36: 443 temp |= DP_MSA_MISC_12_BPC; 444 break; 445 default: 446 MISSING_CASE(crtc_state->pipe_bpp); 447 break; 448 } 449 450 /* nonsense combination */ 451 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 452 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 453 454 if (crtc_state->limited_color_range) 455 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 456 457 /* 458 * As per DP 1.2 spec section 2.3.4.3 while sending 459 * YCBCR 444 signals we should program MSA MISC1/0 fields with 460 * colorspace information. 461 */ 462 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 463 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 464 465 /* 466 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 467 * of Color Encoding Format and Content Color Gamut] while sending 468 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 469 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 470 */ 471 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 472 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 473 474 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 475 temp); 476 } 477 478 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 479 { 480 if (master_transcoder == TRANSCODER_EDP) 481 return 0; 482 else 483 return master_transcoder + 1; 484 } 485 486 static void 487 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 488 bool enable) 489 { 490 struct intel_display *display = to_intel_display(crtc_state); 491 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 492 u32 val = 0; 493 494 if (!HAS_DP20(display)) 495 return; 496 497 if (enable && intel_dp_is_uhbr(crtc_state)) 498 val = TRANS_DP2_128B132B_CHANNEL_CODING; 499 500 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 501 } 502 503 /* 504 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 505 * 506 * Only intended to be used by intel_ddi_enable_transcoder_func() and 507 * intel_ddi_config_transcoder_func(). 508 */ 509 static u32 510 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 511 const struct intel_crtc_state *crtc_state) 512 { 513 struct intel_display *display = to_intel_display(crtc_state); 514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 515 enum pipe pipe = crtc->pipe; 516 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 517 enum port port = encoder->port; 518 u32 temp; 519 520 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 521 temp = TRANS_DDI_FUNC_ENABLE; 522 if (DISPLAY_VER(display) >= 12) 523 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 524 else 525 temp |= TRANS_DDI_SELECT_PORT(port); 526 527 switch (crtc_state->pipe_bpp) { 528 default: 529 MISSING_CASE(crtc_state->pipe_bpp); 530 fallthrough; 531 case 18: 532 temp |= TRANS_DDI_BPC_6; 533 break; 534 case 24: 535 temp |= TRANS_DDI_BPC_8; 536 break; 537 case 30: 538 temp |= TRANS_DDI_BPC_10; 539 break; 540 case 36: 541 temp |= TRANS_DDI_BPC_12; 542 break; 543 } 544 545 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 546 temp |= TRANS_DDI_PVSYNC; 547 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 548 temp |= TRANS_DDI_PHSYNC; 549 550 if (cpu_transcoder == TRANSCODER_EDP) { 551 switch (pipe) { 552 default: 553 MISSING_CASE(pipe); 554 fallthrough; 555 case PIPE_A: 556 /* On Haswell, can only use the always-on power well for 557 * eDP when not using the panel fitter, and when not 558 * using motion blur mitigation (which we don't 559 * support). */ 560 if (crtc_state->pch_pfit.force_thru) 561 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 562 else 563 temp |= TRANS_DDI_EDP_INPUT_A_ON; 564 break; 565 case PIPE_B: 566 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 567 break; 568 case PIPE_C: 569 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 570 break; 571 } 572 } 573 574 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 575 if (crtc_state->has_hdmi_sink) 576 temp |= TRANS_DDI_MODE_SELECT_HDMI; 577 else 578 temp |= TRANS_DDI_MODE_SELECT_DVI; 579 580 if (crtc_state->hdmi_scrambling) 581 temp |= TRANS_DDI_HDMI_SCRAMBLING; 582 if (crtc_state->hdmi_high_tmds_clock_ratio) 583 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 584 if (DISPLAY_VER(display) >= 14) 585 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 586 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 587 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 588 temp |= (crtc_state->fdi_lanes - 1) << 1; 589 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 590 intel_dp_is_uhbr(crtc_state)) { 591 if (intel_dp_is_uhbr(crtc_state)) 592 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 593 else 594 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 595 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 596 597 if (DISPLAY_VER(display) >= 12) { 598 enum transcoder master; 599 600 master = crtc_state->mst_master_transcoder; 601 if (drm_WARN_ON(display->drm, 602 master == INVALID_TRANSCODER)) 603 master = TRANSCODER_A; 604 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 605 } 606 } else { 607 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 608 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 609 } 610 611 if (IS_DISPLAY_VER(display, 8, 10) && 612 crtc_state->master_transcoder != INVALID_TRANSCODER) { 613 u8 master_select = 614 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 615 616 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 617 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 618 } 619 620 return temp; 621 } 622 623 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 624 const struct intel_crtc_state *crtc_state) 625 { 626 struct intel_display *display = to_intel_display(crtc_state); 627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 628 629 if (DISPLAY_VER(display) >= 11) { 630 enum transcoder master_transcoder = crtc_state->master_transcoder; 631 u32 ctl2 = 0; 632 633 if (master_transcoder != INVALID_TRANSCODER) { 634 u8 master_select = 635 bdw_trans_port_sync_master_select(master_transcoder); 636 637 ctl2 |= PORT_SYNC_MODE_ENABLE | 638 PORT_SYNC_MODE_MASTER_SELECT(master_select); 639 } 640 641 intel_de_write(display, 642 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 643 ctl2); 644 } 645 646 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 647 intel_ddi_transcoder_func_reg_val_get(encoder, 648 crtc_state)); 649 } 650 651 /* 652 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 653 * bit for the DDI function and enables the DP2 configuration. Called for all 654 * transcoder types. 655 */ 656 void 657 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 658 const struct intel_crtc_state *crtc_state) 659 { 660 struct intel_display *display = to_intel_display(crtc_state); 661 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 662 u32 ctl; 663 664 intel_ddi_config_transcoder_dp2(crtc_state, true); 665 666 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 667 ctl &= ~TRANS_DDI_FUNC_ENABLE; 668 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 669 ctl); 670 } 671 672 /* 673 * Disable the DDI function and port syncing. 674 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 675 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 676 * transcoders these are done later in intel_ddi_post_disable_dp(). 677 */ 678 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 679 { 680 struct intel_display *display = to_intel_display(crtc_state); 681 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 682 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 683 u32 ctl; 684 685 if (DISPLAY_VER(display) >= 11) 686 intel_de_write(display, 687 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 688 0); 689 690 ctl = intel_de_read(display, 691 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 692 693 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 694 695 ctl &= ~TRANS_DDI_FUNC_ENABLE; 696 697 if (IS_DISPLAY_VER(display, 8, 10)) 698 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 699 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 700 701 if (DISPLAY_VER(display) >= 12) { 702 if (!intel_dp_mst_is_master_trans(crtc_state)) { 703 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 704 TRANS_DDI_MODE_SELECT_MASK); 705 } 706 } else { 707 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 708 } 709 710 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 711 ctl); 712 713 if (intel_dp_mst_is_slave_trans(crtc_state)) 714 intel_ddi_config_transcoder_dp2(crtc_state, false); 715 716 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 717 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 718 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 719 /* Quirk time at 100ms for reliable operation */ 720 msleep(100); 721 } 722 } 723 724 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 725 enum transcoder cpu_transcoder, 726 bool enable, u32 hdcp_mask) 727 { 728 struct intel_display *display = to_intel_display(intel_encoder); 729 intel_wakeref_t wakeref; 730 int ret = 0; 731 732 wakeref = intel_display_power_get_if_enabled(display, 733 intel_encoder->power_domain); 734 if (drm_WARN_ON(display->drm, !wakeref)) 735 return -ENXIO; 736 737 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 738 hdcp_mask, enable ? hdcp_mask : 0); 739 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 740 return ret; 741 } 742 743 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 744 { 745 struct intel_display *display = to_intel_display(intel_connector); 746 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 747 int type = intel_connector->base.connector_type; 748 enum port port = encoder->port; 749 enum transcoder cpu_transcoder; 750 intel_wakeref_t wakeref; 751 enum pipe pipe = 0; 752 u32 ddi_mode; 753 bool ret; 754 755 wakeref = intel_display_power_get_if_enabled(display, 756 encoder->power_domain); 757 if (!wakeref) 758 return false; 759 760 /* Note: This returns false for DP MST primary encoders. */ 761 if (!encoder->get_hw_state(encoder, &pipe)) { 762 ret = false; 763 goto out; 764 } 765 766 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 767 cpu_transcoder = TRANSCODER_EDP; 768 else 769 cpu_transcoder = (enum transcoder) pipe; 770 771 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 772 TRANS_DDI_MODE_SELECT_MASK; 773 774 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 775 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 776 ret = type == DRM_MODE_CONNECTOR_HDMIA; 777 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 778 ret = type == DRM_MODE_CONNECTOR_VGA; 779 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 780 ret = type == DRM_MODE_CONNECTOR_eDP || 781 type == DRM_MODE_CONNECTOR_DisplayPort; 782 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 783 /* 784 * encoder->get_hw_state() should have bailed out on MST. This 785 * must be SST and non-eDP. 786 */ 787 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 788 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 789 /* encoder->get_hw_state() should have bailed out on MST. */ 790 ret = false; 791 } else { 792 ret = false; 793 } 794 795 out: 796 intel_display_power_put(display, encoder->power_domain, wakeref); 797 798 return ret; 799 } 800 801 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 802 u8 *pipe_mask, bool *is_dp_mst) 803 { 804 struct intel_display *display = to_intel_display(encoder); 805 enum port port = encoder->port; 806 intel_wakeref_t wakeref; 807 enum pipe p; 808 u32 tmp; 809 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 810 811 *pipe_mask = 0; 812 *is_dp_mst = false; 813 814 wakeref = intel_display_power_get_if_enabled(display, 815 encoder->power_domain); 816 if (!wakeref) 817 return; 818 819 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 820 if (!(tmp & DDI_BUF_CTL_ENABLE)) 821 goto out; 822 823 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 824 tmp = intel_de_read(display, 825 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 826 827 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 828 default: 829 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 830 fallthrough; 831 case TRANS_DDI_EDP_INPUT_A_ON: 832 case TRANS_DDI_EDP_INPUT_A_ONOFF: 833 *pipe_mask = BIT(PIPE_A); 834 break; 835 case TRANS_DDI_EDP_INPUT_B_ONOFF: 836 *pipe_mask = BIT(PIPE_B); 837 break; 838 case TRANS_DDI_EDP_INPUT_C_ONOFF: 839 *pipe_mask = BIT(PIPE_C); 840 break; 841 } 842 843 goto out; 844 } 845 846 for_each_pipe(display, p) { 847 enum transcoder cpu_transcoder = (enum transcoder)p; 848 u32 port_mask, ddi_select, ddi_mode; 849 intel_wakeref_t trans_wakeref; 850 851 trans_wakeref = intel_display_power_get_if_enabled(display, 852 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 853 if (!trans_wakeref) 854 continue; 855 856 if (DISPLAY_VER(display) >= 12) { 857 port_mask = TGL_TRANS_DDI_PORT_MASK; 858 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 859 } else { 860 port_mask = TRANS_DDI_PORT_MASK; 861 ddi_select = TRANS_DDI_SELECT_PORT(port); 862 } 863 864 tmp = intel_de_read(display, 865 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 866 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 867 trans_wakeref); 868 869 if ((tmp & port_mask) != ddi_select) 870 continue; 871 872 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 873 874 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 875 mst_pipe_mask |= BIT(p); 876 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 877 dp128b132b_pipe_mask |= BIT(p); 878 879 *pipe_mask |= BIT(p); 880 } 881 882 if (!*pipe_mask) 883 drm_dbg_kms(display->drm, 884 "No pipe for [ENCODER:%d:%s] found\n", 885 encoder->base.base.id, encoder->base.name); 886 887 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 888 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 889 890 /* 891 * If we don't have 8b/10b MST, but have more than one 892 * transcoder in 128b/132b mode, we know it must be 128b/132b 893 * MST. 894 * 895 * Otherwise, we fall back to checking the current MST 896 * state. It's not accurate for hardware takeover at probe, but 897 * we don't expect MST to have been enabled at that point, and 898 * can assume it's SST. 899 */ 900 if (hweight8(dp128b132b_pipe_mask) > 1 || 901 intel_dp_mst_active_streams(intel_dp)) 902 mst_pipe_mask = dp128b132b_pipe_mask; 903 } 904 905 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 906 drm_dbg_kms(display->drm, 907 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 908 encoder->base.base.id, encoder->base.name, 909 *pipe_mask); 910 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 911 } 912 913 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 914 drm_dbg_kms(display->drm, 915 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 916 encoder->base.base.id, encoder->base.name, 917 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 918 else 919 *is_dp_mst = mst_pipe_mask; 920 921 out: 922 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 923 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 924 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 925 BXT_PHY_LANE_POWERDOWN_ACK | 926 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 927 drm_err(display->drm, 928 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 929 encoder->base.base.id, encoder->base.name, tmp); 930 } 931 932 intel_display_power_put(display, encoder->power_domain, wakeref); 933 } 934 935 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 936 enum pipe *pipe) 937 { 938 u8 pipe_mask; 939 bool is_mst; 940 941 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 942 943 if (is_mst || !pipe_mask) 944 return false; 945 946 *pipe = ffs(pipe_mask) - 1; 947 948 return true; 949 } 950 951 static enum intel_display_power_domain 952 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 953 const struct intel_crtc_state *crtc_state) 954 { 955 struct intel_display *display = to_intel_display(dig_port); 956 957 /* 958 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 959 * DC states enabled at the same time, while for driver initiated AUX 960 * transfers we need the same AUX IOs to be powered but with DC states 961 * disabled. Accordingly use the AUX_IO_<port> power domain here which 962 * leaves DC states enabled. 963 * 964 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 965 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 966 * well, so we can acquire a wider AUX_<port> power domain reference 967 * instead of a specific AUX_IO_<port> reference without powering up any 968 * extra wells. 969 */ 970 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 971 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 972 else if (DISPLAY_VER(display) < 14 && 973 (intel_crtc_has_dp_encoder(crtc_state) || 974 intel_encoder_is_tc(&dig_port->base))) 975 return intel_aux_power_domain(dig_port); 976 else 977 return POWER_DOMAIN_INVALID; 978 } 979 980 static void 981 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 982 const struct intel_crtc_state *crtc_state) 983 { 984 struct intel_display *display = to_intel_display(dig_port); 985 enum intel_display_power_domain domain = 986 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 987 988 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 989 990 if (domain == POWER_DOMAIN_INVALID) 991 return; 992 993 dig_port->aux_wakeref = intel_display_power_get(display, domain); 994 } 995 996 static void 997 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 998 const struct intel_crtc_state *crtc_state) 999 { 1000 struct intel_display *display = to_intel_display(dig_port); 1001 enum intel_display_power_domain domain = 1002 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1003 intel_wakeref_t wf; 1004 1005 wf = fetch_and_zero(&dig_port->aux_wakeref); 1006 if (!wf) 1007 return; 1008 1009 intel_display_power_put(display, domain, wf); 1010 } 1011 1012 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1013 struct intel_crtc_state *crtc_state) 1014 { 1015 struct intel_display *display = to_intel_display(encoder); 1016 struct intel_digital_port *dig_port; 1017 1018 /* 1019 * TODO: Add support for MST encoders. Atm, the following should never 1020 * happen since fake-MST encoders don't set their get_power_domains() 1021 * hook. 1022 */ 1023 if (drm_WARN_ON(display->drm, 1024 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1025 return; 1026 1027 dig_port = enc_to_dig_port(encoder); 1028 1029 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1030 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1031 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1032 dig_port->ddi_io_power_domain); 1033 } 1034 1035 main_link_aux_power_domain_get(dig_port, crtc_state); 1036 } 1037 1038 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1039 const struct intel_crtc_state *crtc_state) 1040 { 1041 struct intel_display *display = to_intel_display(crtc_state); 1042 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1043 enum phy phy = intel_encoder_to_phy(encoder); 1044 u32 val; 1045 1046 if (cpu_transcoder == TRANSCODER_EDP) 1047 return; 1048 1049 if (DISPLAY_VER(display) >= 13) 1050 val = TGL_TRANS_CLK_SEL_PORT(phy); 1051 else if (DISPLAY_VER(display) >= 12) 1052 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1053 else 1054 val = TRANS_CLK_SEL_PORT(encoder->port); 1055 1056 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1057 } 1058 1059 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1060 { 1061 struct intel_display *display = to_intel_display(crtc_state); 1062 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1063 u32 val; 1064 1065 if (cpu_transcoder == TRANSCODER_EDP) 1066 return; 1067 1068 if (DISPLAY_VER(display) >= 12) 1069 val = TGL_TRANS_CLK_SEL_DISABLED; 1070 else 1071 val = TRANS_CLK_SEL_DISABLED; 1072 1073 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1074 } 1075 1076 static void _skl_ddi_set_iboost(struct intel_display *display, 1077 enum port port, u8 iboost) 1078 { 1079 u32 tmp; 1080 1081 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1082 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1083 if (iboost) 1084 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1085 else 1086 tmp |= BALANCE_LEG_DISABLE(port); 1087 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1088 } 1089 1090 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1091 const struct intel_crtc_state *crtc_state, 1092 int level) 1093 { 1094 struct intel_display *display = to_intel_display(encoder); 1095 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1096 u8 iboost; 1097 1098 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1099 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1100 else 1101 iboost = intel_bios_dp_boost_level(encoder->devdata); 1102 1103 if (iboost == 0) { 1104 const struct intel_ddi_buf_trans *trans; 1105 int n_entries; 1106 1107 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1108 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1109 return; 1110 1111 iboost = trans->entries[level].hsw.i_boost; 1112 } 1113 1114 /* Make sure that the requested I_boost is valid */ 1115 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1116 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1117 return; 1118 } 1119 1120 _skl_ddi_set_iboost(display, encoder->port, iboost); 1121 1122 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1123 _skl_ddi_set_iboost(display, PORT_E, iboost); 1124 } 1125 1126 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1127 const struct intel_crtc_state *crtc_state) 1128 { 1129 struct intel_display *display = to_intel_display(intel_dp); 1130 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1131 int n_entries; 1132 1133 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1134 1135 if (drm_WARN_ON(display->drm, n_entries < 1)) 1136 n_entries = 1; 1137 if (drm_WARN_ON(display->drm, 1138 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1139 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1140 1141 return index_to_dp_signal_levels[n_entries - 1] & 1142 DP_TRAIN_VOLTAGE_SWING_MASK; 1143 } 1144 1145 /* 1146 * We assume that the full set of pre-emphasis values can be 1147 * used on all DDI platforms. Should that change we need to 1148 * rethink this code. 1149 */ 1150 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1151 { 1152 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1153 } 1154 1155 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1156 int lane) 1157 { 1158 if (crtc_state->port_clock > 600000) 1159 return 0; 1160 1161 if (crtc_state->lane_count == 4) 1162 return lane >= 1 ? LOADGEN_SELECT : 0; 1163 else 1164 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1165 } 1166 1167 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1168 const struct intel_crtc_state *crtc_state) 1169 { 1170 struct intel_display *display = to_intel_display(encoder); 1171 const struct intel_ddi_buf_trans *trans; 1172 enum phy phy = intel_encoder_to_phy(encoder); 1173 int n_entries, ln; 1174 u32 val; 1175 1176 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1177 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1178 return; 1179 1180 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1181 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1182 1183 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1184 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1185 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1186 intel_dp->hobl_active ? val : 0); 1187 } 1188 1189 /* Set PORT_TX_DW5 */ 1190 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1191 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1192 COEFF_POLARITY | CURSOR_PROGRAM | 1193 TAP2_DISABLE | TAP3_DISABLE); 1194 val |= SCALING_MODE_SEL(0x2); 1195 val |= RTERM_SELECT(0x6); 1196 val |= TAP3_DISABLE; 1197 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1198 1199 /* Program PORT_TX_DW2 */ 1200 for (ln = 0; ln < 4; ln++) { 1201 int level = intel_ddi_level(encoder, crtc_state, ln); 1202 1203 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1204 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1205 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1206 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1207 RCOMP_SCALAR(0x98)); 1208 } 1209 1210 /* Program PORT_TX_DW4 */ 1211 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1212 for (ln = 0; ln < 4; ln++) { 1213 int level = intel_ddi_level(encoder, crtc_state, ln); 1214 1215 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1216 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1217 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1218 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1219 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1220 } 1221 1222 /* Program PORT_TX_DW7 */ 1223 for (ln = 0; ln < 4; ln++) { 1224 int level = intel_ddi_level(encoder, crtc_state, ln); 1225 1226 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1227 N_SCALAR_MASK, 1228 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1229 } 1230 } 1231 1232 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1233 const struct intel_crtc_state *crtc_state) 1234 { 1235 struct intel_display *display = to_intel_display(encoder); 1236 enum phy phy = intel_encoder_to_phy(encoder); 1237 u32 val; 1238 int ln; 1239 1240 /* 1241 * 1. If port type is eDP or DP, 1242 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1243 * else clear to 0b. 1244 */ 1245 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1246 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1247 val &= ~COMMON_KEEPER_EN; 1248 else 1249 val |= COMMON_KEEPER_EN; 1250 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1251 1252 /* 2. Program loadgen select */ 1253 /* 1254 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1255 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1256 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1257 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1258 */ 1259 for (ln = 0; ln < 4; ln++) { 1260 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1261 LOADGEN_SELECT, 1262 icl_combo_phy_loadgen_select(crtc_state, ln)); 1263 } 1264 1265 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1266 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1267 0, SUS_CLOCK_CONFIG); 1268 1269 /* 4. Clear training enable to change swing values */ 1270 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1271 val &= ~TX_TRAINING_EN; 1272 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1273 1274 /* 5. Program swing and de-emphasis */ 1275 icl_ddi_combo_vswing_program(encoder, crtc_state); 1276 1277 /* 6. Set training enable to trigger update */ 1278 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1279 val |= TX_TRAINING_EN; 1280 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1281 } 1282 1283 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1284 const struct intel_crtc_state *crtc_state) 1285 { 1286 struct intel_display *display = to_intel_display(encoder); 1287 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1288 const struct intel_ddi_buf_trans *trans; 1289 int n_entries, ln; 1290 1291 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1292 return; 1293 1294 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1295 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1296 return; 1297 1298 for (ln = 0; ln < 2; ln++) { 1299 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1300 CRI_USE_FS32, 0); 1301 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1302 CRI_USE_FS32, 0); 1303 } 1304 1305 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1306 for (ln = 0; ln < 2; ln++) { 1307 int level; 1308 1309 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1310 1311 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1312 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1313 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1314 1315 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1316 1317 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1318 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1319 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1320 } 1321 1322 /* Program MG_TX_DRVCTRL with values from vswing table */ 1323 for (ln = 0; ln < 2; ln++) { 1324 int level; 1325 1326 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1327 1328 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1329 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1330 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1331 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1332 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1333 CRI_TXDEEMPH_OVERRIDE_EN); 1334 1335 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1336 1337 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1338 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1339 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1340 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1341 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1342 CRI_TXDEEMPH_OVERRIDE_EN); 1343 1344 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1345 } 1346 1347 /* 1348 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1349 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1350 * values from table for which TX1 and TX2 enabled. 1351 */ 1352 for (ln = 0; ln < 2; ln++) { 1353 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1354 CFG_LOW_RATE_LKREN_EN, 1355 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1356 } 1357 1358 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1359 for (ln = 0; ln < 2; ln++) { 1360 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1361 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1362 CFG_AMI_CK_DIV_OVERRIDE_EN, 1363 crtc_state->port_clock > 500000 ? 1364 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1365 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1366 1367 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1368 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1369 CFG_AMI_CK_DIV_OVERRIDE_EN, 1370 crtc_state->port_clock > 500000 ? 1371 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1372 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1373 } 1374 1375 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1376 for (ln = 0; ln < 2; ln++) { 1377 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1378 0, CRI_CALCINIT); 1379 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1380 0, CRI_CALCINIT); 1381 } 1382 } 1383 1384 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1385 const struct intel_crtc_state *crtc_state) 1386 { 1387 struct intel_display *display = to_intel_display(encoder); 1388 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1389 const struct intel_ddi_buf_trans *trans; 1390 int n_entries, ln; 1391 1392 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1393 return; 1394 1395 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1396 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1397 return; 1398 1399 for (ln = 0; ln < 2; ln++) { 1400 int level; 1401 1402 /* Wa_16011342517:adl-p */ 1403 if (display->platform.alderlake_p && 1404 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) { 1405 if ((intel_encoder_is_hdmi(encoder) && 1406 crtc_state->port_clock == 594000) || 1407 (intel_encoder_is_dp(encoder) && 1408 crtc_state->port_clock == 162000)) { 1409 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1410 LOADGEN_SHARING_PMD_DISABLE, 1); 1411 } else { 1412 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1413 LOADGEN_SHARING_PMD_DISABLE, 0); 1414 } 1415 } 1416 1417 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1418 1419 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1420 1421 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1422 DKL_TX_PRESHOOT_COEFF_MASK | 1423 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1424 DKL_TX_VSWING_CONTROL_MASK, 1425 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1426 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1427 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1428 1429 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1430 1431 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1432 DKL_TX_PRESHOOT_COEFF_MASK | 1433 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1434 DKL_TX_VSWING_CONTROL_MASK, 1435 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1436 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1437 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1438 1439 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1440 DKL_TX_DP20BITMODE, 0); 1441 1442 if (display->platform.alderlake_p) { 1443 u32 val; 1444 1445 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1446 if (ln == 0) { 1447 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1448 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1449 } else { 1450 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1451 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1452 } 1453 } else { 1454 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1455 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1456 } 1457 1458 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1459 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1460 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1461 val); 1462 } 1463 } 1464 } 1465 1466 static int translate_signal_level(struct intel_dp *intel_dp, 1467 u8 signal_levels) 1468 { 1469 struct intel_display *display = to_intel_display(intel_dp); 1470 const u8 *signal_array; 1471 size_t array_size; 1472 int i; 1473 1474 signal_array = index_to_dp_signal_levels; 1475 array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1476 1477 for (i = 0; i < array_size; i++) { 1478 if (signal_array[i] == signal_levels) 1479 return i; 1480 } 1481 1482 drm_WARN(display->drm, 1, 1483 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1484 signal_levels); 1485 1486 return 0; 1487 } 1488 1489 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1490 const struct intel_crtc_state *crtc_state, 1491 int lane) 1492 { 1493 u8 train_set = intel_dp->train_set[lane]; 1494 1495 if (intel_dp_is_uhbr(crtc_state)) { 1496 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1497 } else { 1498 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1499 DP_TRAIN_PRE_EMPHASIS_MASK); 1500 1501 return translate_signal_level(intel_dp, signal_levels); 1502 } 1503 } 1504 1505 int intel_ddi_level(struct intel_encoder *encoder, 1506 const struct intel_crtc_state *crtc_state, 1507 int lane) 1508 { 1509 struct intel_display *display = to_intel_display(encoder); 1510 const struct intel_ddi_buf_trans *trans; 1511 int level, n_entries; 1512 1513 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1514 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1515 return 0; 1516 1517 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1518 level = intel_ddi_hdmi_level(encoder, trans); 1519 else 1520 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1521 lane); 1522 1523 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1524 level = n_entries - 1; 1525 1526 return level; 1527 } 1528 1529 static void 1530 hsw_set_signal_levels(struct intel_encoder *encoder, 1531 const struct intel_crtc_state *crtc_state) 1532 { 1533 struct intel_display *display = to_intel_display(encoder); 1534 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1535 int level = intel_ddi_level(encoder, crtc_state, 0); 1536 enum port port = encoder->port; 1537 u32 signal_levels; 1538 1539 if (has_iboost(display)) 1540 skl_ddi_set_iboost(encoder, crtc_state, level); 1541 1542 /* HDMI ignores the rest */ 1543 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1544 return; 1545 1546 signal_levels = DDI_BUF_TRANS_SELECT(level); 1547 1548 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1549 signal_levels); 1550 1551 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1552 intel_dp->DP |= signal_levels; 1553 1554 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1555 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1556 } 1557 1558 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1559 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1560 { 1561 mutex_lock(&display->dpll.lock); 1562 1563 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1564 1565 /* 1566 * "This step and the step before must be 1567 * done with separate register writes." 1568 */ 1569 intel_de_rmw(display, reg, clk_off, 0); 1570 1571 mutex_unlock(&display->dpll.lock); 1572 } 1573 1574 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1575 u32 clk_off) 1576 { 1577 mutex_lock(&display->dpll.lock); 1578 1579 intel_de_rmw(display, reg, 0, clk_off); 1580 1581 mutex_unlock(&display->dpll.lock); 1582 } 1583 1584 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1585 u32 clk_off) 1586 { 1587 return !(intel_de_read(display, reg) & clk_off); 1588 } 1589 1590 static struct intel_dpll * 1591 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1592 u32 clk_sel_mask, u32 clk_sel_shift) 1593 { 1594 enum intel_dpll_id id; 1595 1596 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1597 1598 return intel_get_dpll_by_id(display, id); 1599 } 1600 1601 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1602 const struct intel_crtc_state *crtc_state) 1603 { 1604 struct intel_display *display = to_intel_display(encoder); 1605 const struct intel_dpll *pll = crtc_state->intel_dpll; 1606 enum phy phy = intel_encoder_to_phy(encoder); 1607 1608 if (drm_WARN_ON(display->drm, !pll)) 1609 return; 1610 1611 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1612 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1613 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1614 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1615 } 1616 1617 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1618 { 1619 struct intel_display *display = to_intel_display(encoder); 1620 enum phy phy = intel_encoder_to_phy(encoder); 1621 1622 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1623 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1624 } 1625 1626 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1627 { 1628 struct intel_display *display = to_intel_display(encoder); 1629 enum phy phy = intel_encoder_to_phy(encoder); 1630 1631 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1632 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1633 } 1634 1635 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1636 { 1637 struct intel_display *display = to_intel_display(encoder); 1638 enum phy phy = intel_encoder_to_phy(encoder); 1639 1640 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1641 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1642 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1643 } 1644 1645 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1646 const struct intel_crtc_state *crtc_state) 1647 { 1648 struct intel_display *display = to_intel_display(encoder); 1649 const struct intel_dpll *pll = crtc_state->intel_dpll; 1650 enum phy phy = intel_encoder_to_phy(encoder); 1651 1652 if (drm_WARN_ON(display->drm, !pll)) 1653 return; 1654 1655 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1656 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1657 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1658 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1659 } 1660 1661 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1662 { 1663 struct intel_display *display = to_intel_display(encoder); 1664 enum phy phy = intel_encoder_to_phy(encoder); 1665 1666 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1667 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1668 } 1669 1670 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1671 { 1672 struct intel_display *display = to_intel_display(encoder); 1673 enum phy phy = intel_encoder_to_phy(encoder); 1674 1675 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1676 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1677 } 1678 1679 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1680 { 1681 struct intel_display *display = to_intel_display(encoder); 1682 enum phy phy = intel_encoder_to_phy(encoder); 1683 1684 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1685 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1686 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1687 } 1688 1689 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1690 const struct intel_crtc_state *crtc_state) 1691 { 1692 struct intel_display *display = to_intel_display(encoder); 1693 const struct intel_dpll *pll = crtc_state->intel_dpll; 1694 enum phy phy = intel_encoder_to_phy(encoder); 1695 1696 if (drm_WARN_ON(display->drm, !pll)) 1697 return; 1698 1699 /* 1700 * If we fail this, something went very wrong: first 2 PLLs should be 1701 * used by first 2 phys and last 2 PLLs by last phys 1702 */ 1703 if (drm_WARN_ON(display->drm, 1704 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1705 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1706 return; 1707 1708 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1709 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1710 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1711 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1712 } 1713 1714 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1715 { 1716 struct intel_display *display = to_intel_display(encoder); 1717 enum phy phy = intel_encoder_to_phy(encoder); 1718 1719 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1720 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1721 } 1722 1723 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1724 { 1725 struct intel_display *display = to_intel_display(encoder); 1726 enum phy phy = intel_encoder_to_phy(encoder); 1727 1728 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1729 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1730 } 1731 1732 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1733 { 1734 struct intel_display *display = to_intel_display(encoder); 1735 enum phy phy = intel_encoder_to_phy(encoder); 1736 enum intel_dpll_id id; 1737 u32 val; 1738 1739 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1740 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1741 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1742 id = val; 1743 1744 /* 1745 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1746 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1747 * bit for phy C and D. 1748 */ 1749 if (phy >= PHY_C) 1750 id += DPLL_ID_DG1_DPLL2; 1751 1752 return intel_get_dpll_by_id(display, id); 1753 } 1754 1755 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1756 const struct intel_crtc_state *crtc_state) 1757 { 1758 struct intel_display *display = to_intel_display(encoder); 1759 const struct intel_dpll *pll = crtc_state->intel_dpll; 1760 enum phy phy = intel_encoder_to_phy(encoder); 1761 1762 if (drm_WARN_ON(display->drm, !pll)) 1763 return; 1764 1765 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1766 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1767 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1768 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1769 } 1770 1771 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1772 { 1773 struct intel_display *display = to_intel_display(encoder); 1774 enum phy phy = intel_encoder_to_phy(encoder); 1775 1776 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1777 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1778 } 1779 1780 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1781 { 1782 struct intel_display *display = to_intel_display(encoder); 1783 enum phy phy = intel_encoder_to_phy(encoder); 1784 1785 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1786 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1787 } 1788 1789 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1790 { 1791 struct intel_display *display = to_intel_display(encoder); 1792 enum phy phy = intel_encoder_to_phy(encoder); 1793 1794 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1795 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1796 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1797 } 1798 1799 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1800 const struct intel_crtc_state *crtc_state) 1801 { 1802 struct intel_display *display = to_intel_display(encoder); 1803 const struct intel_dpll *pll = crtc_state->intel_dpll; 1804 enum port port = encoder->port; 1805 1806 if (drm_WARN_ON(display->drm, !pll)) 1807 return; 1808 1809 /* 1810 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1811 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1812 */ 1813 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1814 1815 icl_ddi_combo_enable_clock(encoder, crtc_state); 1816 } 1817 1818 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1819 { 1820 struct intel_display *display = to_intel_display(encoder); 1821 enum port port = encoder->port; 1822 1823 icl_ddi_combo_disable_clock(encoder); 1824 1825 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1826 } 1827 1828 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1829 { 1830 struct intel_display *display = to_intel_display(encoder); 1831 enum port port = encoder->port; 1832 u32 tmp; 1833 1834 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1835 1836 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1837 return false; 1838 1839 return icl_ddi_combo_is_clock_enabled(encoder); 1840 } 1841 1842 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1843 const struct intel_crtc_state *crtc_state) 1844 { 1845 struct intel_display *display = to_intel_display(encoder); 1846 const struct intel_dpll *pll = crtc_state->intel_dpll; 1847 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1848 enum port port = encoder->port; 1849 1850 if (drm_WARN_ON(display->drm, !pll)) 1851 return; 1852 1853 intel_de_write(display, DDI_CLK_SEL(port), 1854 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1855 1856 mutex_lock(&display->dpll.lock); 1857 1858 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1859 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1860 1861 mutex_unlock(&display->dpll.lock); 1862 } 1863 1864 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1865 { 1866 struct intel_display *display = to_intel_display(encoder); 1867 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1868 enum port port = encoder->port; 1869 1870 mutex_lock(&display->dpll.lock); 1871 1872 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1873 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1874 1875 mutex_unlock(&display->dpll.lock); 1876 1877 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1878 } 1879 1880 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1881 { 1882 struct intel_display *display = to_intel_display(encoder); 1883 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1884 enum port port = encoder->port; 1885 u32 tmp; 1886 1887 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1888 1889 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1890 return false; 1891 1892 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1893 1894 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1895 } 1896 1897 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1898 { 1899 struct intel_display *display = to_intel_display(encoder); 1900 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1901 enum port port = encoder->port; 1902 enum intel_dpll_id id; 1903 u32 tmp; 1904 1905 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1906 1907 switch (tmp & DDI_CLK_SEL_MASK) { 1908 case DDI_CLK_SEL_TBT_162: 1909 case DDI_CLK_SEL_TBT_270: 1910 case DDI_CLK_SEL_TBT_540: 1911 case DDI_CLK_SEL_TBT_810: 1912 id = DPLL_ID_ICL_TBTPLL; 1913 break; 1914 case DDI_CLK_SEL_MG: 1915 id = icl_tc_port_to_pll_id(tc_port); 1916 break; 1917 default: 1918 MISSING_CASE(tmp); 1919 fallthrough; 1920 case DDI_CLK_SEL_NONE: 1921 return NULL; 1922 } 1923 1924 return intel_get_dpll_by_id(display, id); 1925 } 1926 1927 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1928 { 1929 struct intel_display *display = to_intel_display(encoder->base.dev); 1930 enum intel_dpll_id id; 1931 1932 switch (encoder->port) { 1933 case PORT_A: 1934 id = DPLL_ID_SKL_DPLL0; 1935 break; 1936 case PORT_B: 1937 id = DPLL_ID_SKL_DPLL1; 1938 break; 1939 case PORT_C: 1940 id = DPLL_ID_SKL_DPLL2; 1941 break; 1942 default: 1943 MISSING_CASE(encoder->port); 1944 return NULL; 1945 } 1946 1947 return intel_get_dpll_by_id(display, id); 1948 } 1949 1950 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1951 const struct intel_crtc_state *crtc_state) 1952 { 1953 struct intel_display *display = to_intel_display(encoder); 1954 const struct intel_dpll *pll = crtc_state->intel_dpll; 1955 enum port port = encoder->port; 1956 1957 if (drm_WARN_ON(display->drm, !pll)) 1958 return; 1959 1960 mutex_lock(&display->dpll.lock); 1961 1962 intel_de_rmw(display, DPLL_CTRL2, 1963 DPLL_CTRL2_DDI_CLK_OFF(port) | 1964 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1965 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1966 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1967 1968 mutex_unlock(&display->dpll.lock); 1969 } 1970 1971 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1972 { 1973 struct intel_display *display = to_intel_display(encoder); 1974 enum port port = encoder->port; 1975 1976 mutex_lock(&display->dpll.lock); 1977 1978 intel_de_rmw(display, DPLL_CTRL2, 1979 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1980 1981 mutex_unlock(&display->dpll.lock); 1982 } 1983 1984 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1985 { 1986 struct intel_display *display = to_intel_display(encoder); 1987 enum port port = encoder->port; 1988 1989 /* 1990 * FIXME Not sure if the override affects both 1991 * the PLL selection and the CLK_OFF bit. 1992 */ 1993 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1994 } 1995 1996 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1997 { 1998 struct intel_display *display = to_intel_display(encoder); 1999 enum port port = encoder->port; 2000 enum intel_dpll_id id; 2001 u32 tmp; 2002 2003 tmp = intel_de_read(display, DPLL_CTRL2); 2004 2005 /* 2006 * FIXME Not sure if the override affects both 2007 * the PLL selection and the CLK_OFF bit. 2008 */ 2009 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2010 return NULL; 2011 2012 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2013 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2014 2015 return intel_get_dpll_by_id(display, id); 2016 } 2017 2018 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2019 const struct intel_crtc_state *crtc_state) 2020 { 2021 struct intel_display *display = to_intel_display(encoder); 2022 const struct intel_dpll *pll = crtc_state->intel_dpll; 2023 enum port port = encoder->port; 2024 2025 if (drm_WARN_ON(display->drm, !pll)) 2026 return; 2027 2028 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2029 } 2030 2031 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2032 { 2033 struct intel_display *display = to_intel_display(encoder); 2034 enum port port = encoder->port; 2035 2036 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2037 } 2038 2039 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2040 { 2041 struct intel_display *display = to_intel_display(encoder); 2042 enum port port = encoder->port; 2043 2044 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2045 } 2046 2047 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2048 { 2049 struct intel_display *display = to_intel_display(encoder); 2050 enum port port = encoder->port; 2051 enum intel_dpll_id id; 2052 u32 tmp; 2053 2054 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2055 2056 switch (tmp & PORT_CLK_SEL_MASK) { 2057 case PORT_CLK_SEL_WRPLL1: 2058 id = DPLL_ID_WRPLL1; 2059 break; 2060 case PORT_CLK_SEL_WRPLL2: 2061 id = DPLL_ID_WRPLL2; 2062 break; 2063 case PORT_CLK_SEL_SPLL: 2064 id = DPLL_ID_SPLL; 2065 break; 2066 case PORT_CLK_SEL_LCPLL_810: 2067 id = DPLL_ID_LCPLL_810; 2068 break; 2069 case PORT_CLK_SEL_LCPLL_1350: 2070 id = DPLL_ID_LCPLL_1350; 2071 break; 2072 case PORT_CLK_SEL_LCPLL_2700: 2073 id = DPLL_ID_LCPLL_2700; 2074 break; 2075 default: 2076 MISSING_CASE(tmp); 2077 fallthrough; 2078 case PORT_CLK_SEL_NONE: 2079 return NULL; 2080 } 2081 2082 return intel_get_dpll_by_id(display, id); 2083 } 2084 2085 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2086 const struct intel_crtc_state *crtc_state) 2087 { 2088 if (encoder->enable_clock) 2089 encoder->enable_clock(encoder, crtc_state); 2090 } 2091 2092 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2093 { 2094 if (encoder->disable_clock) 2095 encoder->disable_clock(encoder); 2096 } 2097 2098 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2099 { 2100 struct intel_display *display = to_intel_display(encoder); 2101 u32 port_mask; 2102 bool ddi_clk_needed; 2103 2104 /* 2105 * In case of DP MST, we sanitize the primary encoder only, not the 2106 * virtual ones. 2107 */ 2108 if (encoder->type == INTEL_OUTPUT_DP_MST) 2109 return; 2110 2111 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2112 u8 pipe_mask; 2113 bool is_mst; 2114 2115 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2116 /* 2117 * In the unlikely case that BIOS enables DP in MST mode, just 2118 * warn since our MST HW readout is incomplete. 2119 */ 2120 if (drm_WARN_ON(display->drm, is_mst)) 2121 return; 2122 } 2123 2124 port_mask = BIT(encoder->port); 2125 ddi_clk_needed = encoder->base.crtc; 2126 2127 if (encoder->type == INTEL_OUTPUT_DSI) { 2128 struct intel_encoder *other_encoder; 2129 2130 port_mask = intel_dsi_encoder_ports(encoder); 2131 /* 2132 * Sanity check that we haven't incorrectly registered another 2133 * encoder using any of the ports of this DSI encoder. 2134 */ 2135 for_each_intel_encoder(display->drm, other_encoder) { 2136 if (other_encoder == encoder) 2137 continue; 2138 2139 if (drm_WARN_ON(display->drm, 2140 port_mask & BIT(other_encoder->port))) 2141 return; 2142 } 2143 /* 2144 * For DSI we keep the ddi clocks gated 2145 * except during enable/disable sequence. 2146 */ 2147 ddi_clk_needed = false; 2148 } 2149 2150 if (ddi_clk_needed || !encoder->is_clock_enabled || 2151 !encoder->is_clock_enabled(encoder)) 2152 return; 2153 2154 drm_dbg_kms(display->drm, 2155 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2156 encoder->base.base.id, encoder->base.name); 2157 2158 encoder->disable_clock(encoder); 2159 } 2160 2161 static void 2162 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2163 enum tc_port tc_port, u32 ln0, u32 ln1) 2164 { 2165 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2166 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2167 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2168 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2169 } 2170 2171 static void 2172 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2173 const struct intel_crtc_state *crtc_state) 2174 { 2175 struct intel_display *display = to_intel_display(crtc_state); 2176 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2177 enum intel_tc_pin_assignment pin_assignment; 2178 u32 ln0, ln1; 2179 u8 width; 2180 2181 if (DISPLAY_VER(display) >= 14) 2182 return; 2183 2184 if (!intel_encoder_is_tc(&dig_port->base) || 2185 intel_tc_port_in_tbt_alt_mode(dig_port)) 2186 return; 2187 2188 if (DISPLAY_VER(display) >= 12) { 2189 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2190 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2191 } else { 2192 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2193 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2194 } 2195 2196 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2197 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2198 2199 /* DPPATC */ 2200 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2201 width = crtc_state->lane_count; 2202 2203 switch (pin_assignment) { 2204 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2205 drm_WARN_ON(display->drm, 2206 !intel_tc_port_in_legacy_mode(dig_port)); 2207 if (width == 1) { 2208 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2209 } else { 2210 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2211 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2212 } 2213 break; 2214 case INTEL_TC_PIN_ASSIGNMENT_A: 2215 if (width == 4) { 2216 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2217 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2218 } 2219 break; 2220 case INTEL_TC_PIN_ASSIGNMENT_B: 2221 if (width == 2) { 2222 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2223 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2224 } 2225 break; 2226 case INTEL_TC_PIN_ASSIGNMENT_C: 2227 case INTEL_TC_PIN_ASSIGNMENT_E: 2228 if (width == 1) { 2229 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2230 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2231 } else { 2232 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2233 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2234 } 2235 break; 2236 case INTEL_TC_PIN_ASSIGNMENT_D: 2237 case INTEL_TC_PIN_ASSIGNMENT_F: 2238 if (width == 1) { 2239 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2240 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2241 } else { 2242 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2243 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2244 } 2245 break; 2246 default: 2247 MISSING_CASE(pin_assignment); 2248 } 2249 2250 if (DISPLAY_VER(display) >= 12) { 2251 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2252 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2253 /* WA_14018221282 */ 2254 if (IS_DISPLAY_VER(display, 12, 13)) 2255 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2256 2257 } else { 2258 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2259 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2260 } 2261 } 2262 2263 static enum transcoder 2264 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2265 { 2266 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2267 return crtc_state->mst_master_transcoder; 2268 else 2269 return crtc_state->cpu_transcoder; 2270 } 2271 2272 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2273 const struct intel_crtc_state *crtc_state) 2274 { 2275 struct intel_display *display = to_intel_display(encoder); 2276 2277 if (DISPLAY_VER(display) >= 12) 2278 return TGL_DP_TP_CTL(display, 2279 tgl_dp_tp_transcoder(crtc_state)); 2280 else 2281 return DP_TP_CTL(encoder->port); 2282 } 2283 2284 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2285 const struct intel_crtc_state *crtc_state) 2286 { 2287 struct intel_display *display = to_intel_display(encoder); 2288 2289 if (DISPLAY_VER(display) >= 12) 2290 return TGL_DP_TP_STATUS(display, 2291 tgl_dp_tp_transcoder(crtc_state)); 2292 else 2293 return DP_TP_STATUS(encoder->port); 2294 } 2295 2296 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2297 const struct intel_crtc_state *crtc_state) 2298 { 2299 struct intel_display *display = to_intel_display(encoder); 2300 2301 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2302 DP_TP_STATUS_ACT_SENT); 2303 } 2304 2305 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2306 const struct intel_crtc_state *crtc_state) 2307 { 2308 struct intel_display *display = to_intel_display(encoder); 2309 2310 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2311 DP_TP_STATUS_ACT_SENT, 1)) 2312 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2313 } 2314 2315 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2316 const struct intel_crtc_state *crtc_state, 2317 bool enable) 2318 { 2319 struct intel_display *display = to_intel_display(intel_dp); 2320 2321 if (!crtc_state->vrr.enable) 2322 return; 2323 2324 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2325 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2326 drm_dbg_kms(display->drm, 2327 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2328 str_enable_disable(enable)); 2329 } 2330 2331 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2332 const struct intel_crtc_state *crtc_state, 2333 bool enable) 2334 { 2335 struct intel_display *display = to_intel_display(intel_dp); 2336 2337 if (!crtc_state->fec_enable) 2338 return; 2339 2340 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2341 enable ? DP_FEC_READY : 0) <= 0) 2342 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2343 str_enabled_disabled(enable)); 2344 2345 if (enable && 2346 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2347 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2348 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2349 } 2350 2351 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2352 { 2353 struct intel_display *display = to_intel_display(aux->drm_dev); 2354 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2355 u8 status = 0; 2356 int ret, err; 2357 2358 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2359 err || (status & mask), 2360 10 * 1000, 200 * 1000, false); 2361 2362 /* Either can be non-zero, but not both */ 2363 ret = ret ?: err; 2364 if (ret) { 2365 drm_dbg_kms(display->drm, 2366 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2367 str_enabled_disabled(enabled), ret, status); 2368 return ret; 2369 } 2370 2371 return 0; 2372 } 2373 2374 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2375 const struct intel_crtc_state *crtc_state, 2376 bool enabled) 2377 { 2378 struct intel_display *display = to_intel_display(encoder); 2379 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2380 int ret; 2381 2382 if (!crtc_state->fec_enable) 2383 return 0; 2384 2385 if (enabled) 2386 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2387 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2388 else 2389 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2390 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2391 2392 if (ret) { 2393 drm_err(display->drm, 2394 "Timeout waiting for FEC live state to get %s\n", 2395 str_enabled_disabled(enabled)); 2396 return ret; 2397 } 2398 /* 2399 * At least the Synoptics MST hub doesn't set the detected flag for 2400 * FEC decoding disabling so skip waiting for that. 2401 */ 2402 if (enabled) { 2403 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2404 if (ret) 2405 return ret; 2406 } 2407 2408 return 0; 2409 } 2410 2411 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2412 const struct intel_crtc_state *crtc_state) 2413 { 2414 struct intel_display *display = to_intel_display(encoder); 2415 int i; 2416 int ret; 2417 2418 if (!crtc_state->fec_enable) 2419 return; 2420 2421 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2422 0, DP_TP_CTL_FEC_ENABLE); 2423 2424 if (DISPLAY_VER(display) < 30) 2425 return; 2426 2427 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2428 if (!ret) 2429 return; 2430 2431 for (i = 0; i < 3; i++) { 2432 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2433 2434 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2435 DP_TP_CTL_FEC_ENABLE, 0); 2436 2437 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2438 if (ret) 2439 continue; 2440 2441 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2442 0, DP_TP_CTL_FEC_ENABLE); 2443 2444 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2445 if (!ret) 2446 return; 2447 } 2448 2449 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2450 } 2451 2452 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2453 const struct intel_crtc_state *crtc_state) 2454 { 2455 struct intel_display *display = to_intel_display(encoder); 2456 2457 if (!crtc_state->fec_enable) 2458 return; 2459 2460 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2461 DP_TP_CTL_FEC_ENABLE, 0); 2462 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2463 } 2464 2465 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2466 const struct intel_crtc_state *crtc_state) 2467 { 2468 struct intel_display *display = to_intel_display(encoder); 2469 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2470 2471 if (intel_encoder_is_combo(encoder)) { 2472 enum phy phy = intel_encoder_to_phy(encoder); 2473 2474 intel_combo_phy_power_up_lanes(display, phy, false, 2475 crtc_state->lane_count, 2476 dig_port->lane_reversal); 2477 } 2478 } 2479 2480 /* 2481 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2482 * platforms. 2483 */ 2484 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2485 { 2486 if (DISPLAY_VER(display) > 20) 2487 return ~0; 2488 else if (display->platform.alderlake_p) 2489 return BIT(PIPE_A) | BIT(PIPE_B); 2490 else 2491 return BIT(PIPE_A); 2492 } 2493 2494 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2495 struct intel_crtc_state *pipe_config) 2496 { 2497 struct intel_display *display = to_intel_display(pipe_config); 2498 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2499 enum pipe pipe = crtc->pipe; 2500 u32 dss1; 2501 2502 if (!HAS_MSO(display)) 2503 return; 2504 2505 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2506 2507 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2508 if (!pipe_config->splitter.enable) 2509 return; 2510 2511 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2512 pipe_config->splitter.enable = false; 2513 return; 2514 } 2515 2516 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2517 default: 2518 drm_WARN(display->drm, true, 2519 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2520 fallthrough; 2521 case SPLITTER_CONFIGURATION_2_SEGMENT: 2522 pipe_config->splitter.link_count = 2; 2523 break; 2524 case SPLITTER_CONFIGURATION_4_SEGMENT: 2525 pipe_config->splitter.link_count = 4; 2526 break; 2527 } 2528 2529 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2530 } 2531 2532 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2533 { 2534 struct intel_display *display = to_intel_display(crtc_state); 2535 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2536 enum pipe pipe = crtc->pipe; 2537 u32 dss1 = 0; 2538 2539 if (!HAS_MSO(display)) 2540 return; 2541 2542 if (crtc_state->splitter.enable) { 2543 dss1 |= SPLITTER_ENABLE; 2544 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2545 if (crtc_state->splitter.link_count == 2) 2546 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2547 else 2548 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2549 } 2550 2551 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2552 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2553 OVERLAP_PIXELS_MASK, dss1); 2554 } 2555 2556 static void 2557 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2558 { 2559 struct intel_display *display = to_intel_display(encoder); 2560 enum port port = encoder->port; 2561 i915_reg_t reg; 2562 u32 set_bits, wait_bits; 2563 int ret; 2564 2565 if (DISPLAY_VER(display) < 14) 2566 return; 2567 2568 if (DISPLAY_VER(display) >= 20) { 2569 reg = DDI_BUF_CTL(port); 2570 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2571 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2572 } else { 2573 reg = XELPDP_PORT_BUF_CTL1(display, port); 2574 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2575 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2576 } 2577 2578 intel_de_rmw(display, reg, 0, set_bits); 2579 2580 ret = intel_de_wait_custom(display, reg, 2581 wait_bits, wait_bits, 2582 100, 0, NULL); 2583 if (ret) { 2584 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2585 port_name(port)); 2586 } 2587 } 2588 2589 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2590 const struct intel_crtc_state *crtc_state) 2591 { 2592 struct intel_display *display = to_intel_display(encoder); 2593 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2594 enum port port = encoder->port; 2595 u32 val = 0; 2596 2597 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2598 2599 if (intel_dp_is_uhbr(crtc_state)) 2600 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2601 else 2602 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2603 2604 if (dig_port->lane_reversal) 2605 val |= XELPDP_PORT_REVERSAL; 2606 2607 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2608 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2609 val); 2610 } 2611 2612 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2613 { 2614 struct intel_display *display = to_intel_display(encoder); 2615 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2616 u32 val; 2617 2618 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2619 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2620 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2621 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2622 } 2623 2624 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2625 struct intel_encoder *encoder, 2626 const struct intel_crtc_state *crtc_state, 2627 const struct drm_connector_state *conn_state) 2628 { 2629 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2630 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2631 bool transparent_mode; 2632 int ret; 2633 2634 intel_dp_set_link_params(intel_dp, 2635 crtc_state->port_clock, 2636 crtc_state->lane_count); 2637 2638 /* 2639 * We only configure what the register value will be here. Actual 2640 * enabling happens during link training farther down. 2641 */ 2642 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2643 2644 /* 2645 * 1. Enable Power Wells 2646 * 2647 * This was handled at the beginning of intel_atomic_commit_tail(), 2648 * before we called down into this function. 2649 */ 2650 2651 /* 2. PMdemand was already set */ 2652 2653 /* 3. Select Thunderbolt */ 2654 mtl_port_buf_ctl_io_selection(encoder); 2655 2656 /* 4. Enable Panel Power if PPS is required */ 2657 intel_pps_on(intel_dp); 2658 2659 /* 5. Enable the port PLL */ 2660 intel_ddi_enable_clock(encoder, crtc_state); 2661 2662 /* 2663 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2664 * Transcoder. 2665 */ 2666 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2667 2668 /* 2669 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2670 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2671 * Transport Select 2672 */ 2673 intel_ddi_config_transcoder_func(encoder, crtc_state); 2674 2675 /* 2676 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2677 */ 2678 intel_ddi_mso_configure(crtc_state); 2679 2680 if (!is_mst) 2681 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2682 2683 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2684 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2685 2686 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2687 if (!is_mst) 2688 intel_dp_sink_enable_decompression(state, 2689 to_intel_connector(conn_state->connector), 2690 crtc_state); 2691 2692 /* 2693 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2694 * in the FEC_CONFIGURATION register to 1 before initiating link 2695 * training 2696 */ 2697 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2698 2699 intel_dp_check_frl_training(intel_dp); 2700 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2701 2702 /* 2703 * 6. The rest of the below are substeps under the bspec's "Enable and 2704 * Train Display Port" step. Note that steps that are specific to 2705 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2706 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2707 * us when active_mst_links==0, so any steps designated for "single 2708 * stream or multi-stream master transcoder" can just be performed 2709 * unconditionally here. 2710 * 2711 * mtl_ddi_prepare_link_retrain() that is called by 2712 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2713 * 6.i and 6.j 2714 * 2715 * 6.k Follow DisplayPort specification training sequence (see notes for 2716 * failure handling) 2717 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2718 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2719 * (timeout after 800 us) 2720 */ 2721 intel_dp_start_link_train(state, intel_dp, crtc_state); 2722 2723 /* 6.n Set DP_TP_CTL link training to Normal */ 2724 if (!is_trans_port_sync_mode(crtc_state)) 2725 intel_dp_stop_link_train(intel_dp, crtc_state); 2726 2727 /* 6.o Configure and enable FEC if needed */ 2728 intel_ddi_enable_fec(encoder, crtc_state); 2729 2730 /* 7.a 128b/132b SST. */ 2731 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2732 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2733 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2734 if (ret < 0) 2735 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2736 } 2737 2738 if (!is_mst) 2739 intel_dsc_dp_pps_write(encoder, crtc_state); 2740 } 2741 2742 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2743 struct intel_encoder *encoder, 2744 const struct intel_crtc_state *crtc_state, 2745 const struct drm_connector_state *conn_state) 2746 { 2747 struct intel_display *display = to_intel_display(encoder); 2748 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2749 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2750 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2751 int ret; 2752 2753 intel_dp_set_link_params(intel_dp, 2754 crtc_state->port_clock, 2755 crtc_state->lane_count); 2756 2757 /* 2758 * We only configure what the register value will be here. Actual 2759 * enabling happens during link training farther down. 2760 */ 2761 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2762 2763 /* 2764 * 1. Enable Power Wells 2765 * 2766 * This was handled at the beginning of intel_atomic_commit_tail(), 2767 * before we called down into this function. 2768 */ 2769 2770 /* 2. Enable Panel Power if PPS is required */ 2771 intel_pps_on(intel_dp); 2772 2773 /* 2774 * 3. For non-TBT Type-C ports, set FIA lane count 2775 * (DFLEXDPSP.DPX4TXLATC) 2776 * 2777 * This was done before tgl_ddi_pre_enable_dp by 2778 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2779 */ 2780 2781 /* 2782 * 4. Enable the port PLL. 2783 * 2784 * The PLL enabling itself was already done before this function by 2785 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2786 * configure the PLL to port mapping here. 2787 */ 2788 intel_ddi_enable_clock(encoder, crtc_state); 2789 2790 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2791 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2792 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2793 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2794 dig_port->ddi_io_power_domain); 2795 } 2796 2797 /* 6. Program DP_MODE */ 2798 icl_program_mg_dp_mode(dig_port, crtc_state); 2799 2800 /* 2801 * 7. The rest of the below are substeps under the bspec's "Enable and 2802 * Train Display Port" step. Note that steps that are specific to 2803 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2804 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2805 * us when active_mst_links==0, so any steps designated for "single 2806 * stream or multi-stream master transcoder" can just be performed 2807 * unconditionally here. 2808 */ 2809 2810 /* 2811 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2812 * Transcoder. 2813 */ 2814 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2815 2816 /* 2817 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2818 * Transport Select 2819 */ 2820 intel_ddi_config_transcoder_func(encoder, crtc_state); 2821 2822 /* 2823 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2824 * selected 2825 * 2826 * This will be handled by the intel_dp_start_link_train() farther 2827 * down this function. 2828 */ 2829 2830 /* 7.e Configure voltage swing and related IO settings */ 2831 encoder->set_signal_levels(encoder, crtc_state); 2832 2833 /* 2834 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2835 * the used lanes of the DDI. 2836 */ 2837 intel_ddi_power_up_lanes(encoder, crtc_state); 2838 2839 /* 2840 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2841 */ 2842 intel_ddi_mso_configure(crtc_state); 2843 2844 if (!is_mst) 2845 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2846 2847 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2848 if (!is_mst) 2849 intel_dp_sink_enable_decompression(state, 2850 to_intel_connector(conn_state->connector), 2851 crtc_state); 2852 /* 2853 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2854 * in the FEC_CONFIGURATION register to 1 before initiating link 2855 * training 2856 */ 2857 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2858 2859 intel_dp_check_frl_training(intel_dp); 2860 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2861 2862 /* 2863 * 7.i Follow DisplayPort specification training sequence (see notes for 2864 * failure handling) 2865 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2866 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2867 * (timeout after 800 us) 2868 */ 2869 intel_dp_start_link_train(state, intel_dp, crtc_state); 2870 2871 /* 7.k Set DP_TP_CTL link training to Normal */ 2872 if (!is_trans_port_sync_mode(crtc_state)) 2873 intel_dp_stop_link_train(intel_dp, crtc_state); 2874 2875 /* 7.l Configure and enable FEC if needed */ 2876 intel_ddi_enable_fec(encoder, crtc_state); 2877 2878 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2879 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2880 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2881 if (ret < 0) 2882 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2883 } 2884 2885 if (!is_mst) 2886 intel_dsc_dp_pps_write(encoder, crtc_state); 2887 } 2888 2889 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2890 struct intel_encoder *encoder, 2891 const struct intel_crtc_state *crtc_state, 2892 const struct drm_connector_state *conn_state) 2893 { 2894 struct intel_display *display = to_intel_display(encoder); 2895 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2896 enum port port = encoder->port; 2897 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2898 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2899 2900 if (DISPLAY_VER(display) < 11) 2901 drm_WARN_ON(display->drm, 2902 is_mst && (port == PORT_A || port == PORT_E)); 2903 else 2904 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2905 2906 intel_dp_set_link_params(intel_dp, 2907 crtc_state->port_clock, 2908 crtc_state->lane_count); 2909 2910 /* 2911 * We only configure what the register value will be here. Actual 2912 * enabling happens during link training farther down. 2913 */ 2914 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2915 2916 intel_pps_on(intel_dp); 2917 2918 intel_ddi_enable_clock(encoder, crtc_state); 2919 2920 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2921 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2922 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2923 dig_port->ddi_io_power_domain); 2924 } 2925 2926 icl_program_mg_dp_mode(dig_port, crtc_state); 2927 2928 if (has_buf_trans_select(display)) 2929 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2930 2931 encoder->set_signal_levels(encoder, crtc_state); 2932 2933 intel_ddi_power_up_lanes(encoder, crtc_state); 2934 2935 if (!is_mst) 2936 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2937 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2938 if (!is_mst) 2939 intel_dp_sink_enable_decompression(state, 2940 to_intel_connector(conn_state->connector), 2941 crtc_state); 2942 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2943 intel_dp_start_link_train(state, intel_dp, crtc_state); 2944 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2945 !is_trans_port_sync_mode(crtc_state)) 2946 intel_dp_stop_link_train(intel_dp, crtc_state); 2947 2948 intel_ddi_enable_fec(encoder, crtc_state); 2949 2950 if (!is_mst) { 2951 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2952 intel_dsc_dp_pps_write(encoder, crtc_state); 2953 } 2954 } 2955 2956 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2957 struct intel_encoder *encoder, 2958 const struct intel_crtc_state *crtc_state, 2959 const struct drm_connector_state *conn_state) 2960 { 2961 struct intel_display *display = to_intel_display(encoder); 2962 2963 if (HAS_DP20(display)) 2964 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2965 crtc_state); 2966 2967 /* Panel replay has to be enabled in sink dpcd before link training. */ 2968 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2969 2970 if (DISPLAY_VER(display) >= 14) 2971 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2972 else if (DISPLAY_VER(display) >= 12) 2973 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2974 else 2975 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2976 2977 /* MST will call a setting of MSA after an allocating of Virtual Channel 2978 * from MST encoder pre_enable callback. 2979 */ 2980 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2981 intel_ddi_set_dp_msa(crtc_state, conn_state); 2982 } 2983 2984 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2985 struct intel_encoder *encoder, 2986 const struct intel_crtc_state *crtc_state, 2987 const struct drm_connector_state *conn_state) 2988 { 2989 struct intel_display *display = to_intel_display(encoder); 2990 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2991 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2992 2993 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2994 intel_ddi_enable_clock(encoder, crtc_state); 2995 2996 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2997 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2998 dig_port->ddi_io_power_domain); 2999 3000 icl_program_mg_dp_mode(dig_port, crtc_state); 3001 3002 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3003 3004 dig_port->set_infoframes(encoder, 3005 crtc_state->has_infoframe, 3006 crtc_state, conn_state); 3007 } 3008 3009 /* 3010 * Note: Also called from the ->pre_enable of the first active MST stream 3011 * encoder on its primary encoder. 3012 * 3013 * When called from DP MST code: 3014 * 3015 * - conn_state will be NULL 3016 * 3017 * - encoder will be the primary encoder (i.e. mst->primary) 3018 * 3019 * - the main connector associated with this port won't be active or linked to a 3020 * crtc 3021 * 3022 * - crtc_state will be the state of the first stream to be activated on this 3023 * port, and it may not be the same stream that will be deactivated last, but 3024 * each stream should have a state that is identical when it comes to the DP 3025 * link parameters. 3026 */ 3027 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3028 struct intel_encoder *encoder, 3029 const struct intel_crtc_state *crtc_state, 3030 const struct drm_connector_state *conn_state) 3031 { 3032 struct intel_display *display = to_intel_display(state); 3033 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3034 enum pipe pipe = crtc->pipe; 3035 3036 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3037 3038 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3039 3040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3041 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3042 conn_state); 3043 } else { 3044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3045 3046 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3047 conn_state); 3048 3049 /* FIXME precompute everything properly */ 3050 /* FIXME how do we turn infoframes off again? */ 3051 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3052 dig_port->set_infoframes(encoder, 3053 crtc_state->has_infoframe, 3054 crtc_state, conn_state); 3055 } 3056 } 3057 3058 static void 3059 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3060 { 3061 struct intel_display *display = to_intel_display(encoder); 3062 enum port port = encoder->port; 3063 i915_reg_t reg; 3064 u32 clr_bits, wait_bits; 3065 int ret; 3066 3067 if (DISPLAY_VER(display) < 14) 3068 return; 3069 3070 if (DISPLAY_VER(display) >= 20) { 3071 reg = DDI_BUF_CTL(port); 3072 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3073 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3074 } else { 3075 reg = XELPDP_PORT_BUF_CTL1(display, port); 3076 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3077 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3078 } 3079 3080 intel_de_rmw(display, reg, clr_bits, 0); 3081 3082 ret = intel_de_wait_custom(display, reg, 3083 wait_bits, 0, 3084 100, 0, NULL); 3085 if (ret) 3086 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3087 port_name(port)); 3088 } 3089 3090 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3091 { 3092 struct intel_display *display = to_intel_display(encoder); 3093 enum port port = encoder->port; 3094 3095 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3096 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3097 3098 intel_wait_ddi_buf_active(encoder); 3099 } 3100 3101 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3102 const struct intel_crtc_state *crtc_state) 3103 { 3104 struct intel_display *display = to_intel_display(encoder); 3105 enum port port = encoder->port; 3106 3107 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3108 3109 if (DISPLAY_VER(display) >= 14) 3110 intel_wait_ddi_buf_idle(display, port); 3111 3112 mtl_ddi_disable_d2d(encoder); 3113 3114 if (intel_crtc_has_dp_encoder(crtc_state)) { 3115 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3116 DP_TP_CTL_ENABLE, 0); 3117 } 3118 3119 intel_ddi_disable_fec(encoder, crtc_state); 3120 3121 if (DISPLAY_VER(display) < 14) 3122 intel_wait_ddi_buf_idle(display, port); 3123 3124 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3125 } 3126 3127 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3128 struct intel_encoder *encoder, 3129 const struct intel_crtc_state *old_crtc_state, 3130 const struct drm_connector_state *old_conn_state) 3131 { 3132 struct intel_display *display = to_intel_display(encoder); 3133 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3134 struct intel_dp *intel_dp = &dig_port->dp; 3135 intel_wakeref_t wakeref; 3136 bool is_mst = intel_crtc_has_type(old_crtc_state, 3137 INTEL_OUTPUT_DP_MST); 3138 3139 if (!is_mst) 3140 intel_dp_set_infoframes(encoder, false, 3141 old_crtc_state, old_conn_state); 3142 3143 /* 3144 * Power down sink before disabling the port, otherwise we end 3145 * up getting interrupts from the sink on detecting link loss. 3146 */ 3147 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3148 3149 if (DISPLAY_VER(display) >= 12) { 3150 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3151 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3152 3153 intel_de_rmw(display, 3154 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3155 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3156 0); 3157 } 3158 } else { 3159 if (!is_mst) 3160 intel_ddi_disable_transcoder_clock(old_crtc_state); 3161 } 3162 3163 intel_ddi_buf_disable(encoder, old_crtc_state); 3164 3165 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3166 3167 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3168 3169 /* 3170 * From TGL spec: "If single stream or multi-stream master transcoder: 3171 * Configure Transcoder Clock select to direct no clock to the 3172 * transcoder" 3173 */ 3174 if (DISPLAY_VER(display) >= 12) 3175 intel_ddi_disable_transcoder_clock(old_crtc_state); 3176 3177 intel_pps_vdd_on(intel_dp); 3178 intel_pps_off(intel_dp); 3179 3180 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3181 3182 if (wakeref) 3183 intel_display_power_put(display, 3184 dig_port->ddi_io_power_domain, 3185 wakeref); 3186 3187 intel_ddi_disable_clock(encoder); 3188 3189 /* De-select Thunderbolt */ 3190 if (DISPLAY_VER(display) >= 14) 3191 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3192 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3193 } 3194 3195 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3196 struct intel_encoder *encoder, 3197 const struct intel_crtc_state *old_crtc_state, 3198 const struct drm_connector_state *old_conn_state) 3199 { 3200 struct intel_display *display = to_intel_display(encoder); 3201 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3202 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3203 intel_wakeref_t wakeref; 3204 3205 dig_port->set_infoframes(encoder, false, 3206 old_crtc_state, old_conn_state); 3207 3208 if (DISPLAY_VER(display) < 12) 3209 intel_ddi_disable_transcoder_clock(old_crtc_state); 3210 3211 intel_ddi_buf_disable(encoder, old_crtc_state); 3212 3213 if (DISPLAY_VER(display) >= 12) 3214 intel_ddi_disable_transcoder_clock(old_crtc_state); 3215 3216 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3217 if (wakeref) 3218 intel_display_power_put(display, 3219 dig_port->ddi_io_power_domain, 3220 wakeref); 3221 3222 intel_ddi_disable_clock(encoder); 3223 3224 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3225 } 3226 3227 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3228 struct intel_encoder *encoder, 3229 const struct intel_crtc_state *old_crtc_state, 3230 const struct drm_connector_state *old_conn_state) 3231 { 3232 struct intel_display *display = to_intel_display(encoder); 3233 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3234 struct intel_crtc *pipe_crtc; 3235 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3236 int i; 3237 3238 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3239 const struct intel_crtc_state *old_pipe_crtc_state = 3240 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3241 3242 intel_crtc_vblank_off(old_pipe_crtc_state); 3243 } 3244 3245 intel_disable_transcoder(old_crtc_state); 3246 3247 /* 128b/132b SST */ 3248 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3249 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3250 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3251 3252 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3253 3254 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3255 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3256 3257 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3258 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3259 } 3260 3261 intel_vrr_transcoder_disable(old_crtc_state); 3262 3263 intel_ddi_disable_transcoder_func(old_crtc_state); 3264 3265 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3266 const struct intel_crtc_state *old_pipe_crtc_state = 3267 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3268 3269 intel_dsc_disable(old_pipe_crtc_state); 3270 3271 if (DISPLAY_VER(display) >= 9) 3272 skl_scaler_disable(old_pipe_crtc_state); 3273 else 3274 ilk_pfit_disable(old_pipe_crtc_state); 3275 } 3276 } 3277 3278 /* 3279 * Note: Also called from the ->post_disable of the last active MST stream 3280 * encoder on its primary encoder. See also the comment for 3281 * intel_ddi_pre_enable(). 3282 */ 3283 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3284 struct intel_encoder *encoder, 3285 const struct intel_crtc_state *old_crtc_state, 3286 const struct drm_connector_state *old_conn_state) 3287 { 3288 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3289 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3290 old_conn_state); 3291 3292 /* 3293 * When called from DP MST code: 3294 * - old_conn_state will be NULL 3295 * - encoder will be the main encoder (ie. mst->primary) 3296 * - the main connector associated with this port 3297 * won't be active or linked to a crtc 3298 * - old_crtc_state will be the state of the last stream to 3299 * be deactivated on this port, and it may not be the same 3300 * stream that was activated last, but each stream 3301 * should have a state that is identical when it comes to 3302 * the DP link parameters 3303 */ 3304 3305 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3306 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3307 old_conn_state); 3308 else 3309 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3310 old_conn_state); 3311 } 3312 3313 /* 3314 * Note: Also called from the ->post_pll_disable of the last active MST stream 3315 * encoder on its primary encoder. See also the comment for 3316 * intel_ddi_pre_enable(). 3317 */ 3318 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3319 struct intel_encoder *encoder, 3320 const struct intel_crtc_state *old_crtc_state, 3321 const struct drm_connector_state *old_conn_state) 3322 { 3323 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3324 3325 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3326 3327 if (intel_encoder_is_tc(encoder)) 3328 intel_tc_port_put_link(dig_port); 3329 } 3330 3331 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3332 struct intel_encoder *encoder, 3333 const struct intel_crtc_state *crtc_state) 3334 { 3335 const struct drm_connector_state *conn_state; 3336 struct drm_connector *conn; 3337 int i; 3338 3339 if (!crtc_state->sync_mode_slaves_mask) 3340 return; 3341 3342 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3343 struct intel_encoder *slave_encoder = 3344 to_intel_encoder(conn_state->best_encoder); 3345 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3346 const struct intel_crtc_state *slave_crtc_state; 3347 3348 if (!slave_crtc) 3349 continue; 3350 3351 slave_crtc_state = 3352 intel_atomic_get_new_crtc_state(state, slave_crtc); 3353 3354 if (slave_crtc_state->master_transcoder != 3355 crtc_state->cpu_transcoder) 3356 continue; 3357 3358 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3359 slave_crtc_state); 3360 } 3361 3362 usleep_range(200, 400); 3363 3364 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3365 crtc_state); 3366 } 3367 3368 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3369 struct intel_encoder *encoder, 3370 const struct intel_crtc_state *crtc_state, 3371 const struct drm_connector_state *conn_state) 3372 { 3373 struct intel_display *display = to_intel_display(encoder); 3374 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3375 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3376 enum port port = encoder->port; 3377 3378 if (port == PORT_A && DISPLAY_VER(display) < 9) 3379 intel_dp_stop_link_train(intel_dp, crtc_state); 3380 3381 drm_connector_update_privacy_screen(conn_state); 3382 intel_edp_backlight_on(crtc_state, conn_state); 3383 3384 intel_panel_prepare(crtc_state, conn_state); 3385 3386 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3387 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3388 3389 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3390 } 3391 3392 static i915_reg_t 3393 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3394 { 3395 static const enum transcoder trans[] = { 3396 [PORT_A] = TRANSCODER_EDP, 3397 [PORT_B] = TRANSCODER_A, 3398 [PORT_C] = TRANSCODER_B, 3399 [PORT_D] = TRANSCODER_C, 3400 [PORT_E] = TRANSCODER_A, 3401 }; 3402 3403 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3404 3405 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3406 port = PORT_A; 3407 3408 return CHICKEN_TRANS(display, trans[port]); 3409 } 3410 3411 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3412 struct intel_encoder *encoder, 3413 const struct intel_crtc_state *crtc_state, 3414 const struct drm_connector_state *conn_state) 3415 { 3416 struct intel_display *display = to_intel_display(encoder); 3417 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3418 struct drm_connector *connector = conn_state->connector; 3419 enum port port = encoder->port; 3420 u32 buf_ctl = 0; 3421 3422 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3423 crtc_state->hdmi_high_tmds_clock_ratio, 3424 crtc_state->hdmi_scrambling)) 3425 drm_dbg_kms(display->drm, 3426 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3427 connector->base.id, connector->name); 3428 3429 if (has_buf_trans_select(display)) 3430 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3431 3432 /* e. Enable D2D Link for C10/C20 Phy */ 3433 mtl_ddi_enable_d2d(encoder); 3434 3435 encoder->set_signal_levels(encoder, crtc_state); 3436 3437 /* Display WA #1143: skl,kbl,cfl */ 3438 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3439 /* 3440 * For some reason these chicken bits have been 3441 * stuffed into a transcoder register, event though 3442 * the bits affect a specific DDI port rather than 3443 * a specific transcoder. 3444 */ 3445 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3446 u32 val; 3447 3448 val = intel_de_read(display, reg); 3449 3450 if (port == PORT_E) 3451 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3452 DDIE_TRAINING_OVERRIDE_VALUE; 3453 else 3454 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3455 DDI_TRAINING_OVERRIDE_VALUE; 3456 3457 intel_de_write(display, reg, val); 3458 intel_de_posting_read(display, reg); 3459 3460 udelay(1); 3461 3462 if (port == PORT_E) 3463 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3464 DDIE_TRAINING_OVERRIDE_VALUE); 3465 else 3466 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3467 DDI_TRAINING_OVERRIDE_VALUE); 3468 3469 intel_de_write(display, reg, val); 3470 } 3471 3472 intel_ddi_power_up_lanes(encoder, crtc_state); 3473 3474 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3475 * are ignored so nothing special needs to be done besides 3476 * enabling the port. 3477 * 3478 * On ADL_P the PHY link rate and lane count must be programmed but 3479 * these are both 0 for HDMI. 3480 * 3481 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3482 * is filled with lane count, already set in the crtc_state. 3483 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3484 */ 3485 if (dig_port->lane_reversal) 3486 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3487 if (dig_port->ddi_a_4_lanes) 3488 buf_ctl |= DDI_A_4_LANES; 3489 3490 if (DISPLAY_VER(display) >= 14) { 3491 u32 port_buf = 0; 3492 3493 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3494 3495 if (dig_port->lane_reversal) 3496 port_buf |= XELPDP_PORT_REVERSAL; 3497 3498 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3499 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3500 3501 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3502 3503 if (DISPLAY_VER(display) >= 20) 3504 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3505 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3506 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3507 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3508 } 3509 3510 intel_ddi_buf_enable(encoder, buf_ctl); 3511 } 3512 3513 static void intel_ddi_enable(struct intel_atomic_state *state, 3514 struct intel_encoder *encoder, 3515 const struct intel_crtc_state *crtc_state, 3516 const struct drm_connector_state *conn_state) 3517 { 3518 struct intel_display *display = to_intel_display(encoder); 3519 struct intel_crtc *pipe_crtc; 3520 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3521 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3522 int i; 3523 3524 /* 128b/132b SST */ 3525 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3526 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3527 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3528 3529 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3530 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3531 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3532 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3533 } 3534 3535 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3536 3537 intel_vrr_transcoder_enable(crtc_state); 3538 3539 /* 128b/132b SST */ 3540 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3541 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3542 3543 intel_ddi_clear_act_sent(encoder, crtc_state); 3544 3545 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3546 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3547 3548 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3549 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3550 } 3551 3552 intel_enable_transcoder(crtc_state); 3553 3554 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3555 3556 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3557 const struct intel_crtc_state *pipe_crtc_state = 3558 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3559 3560 intel_crtc_vblank_on(pipe_crtc_state); 3561 } 3562 3563 if (is_hdmi) 3564 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3565 else 3566 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3567 3568 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3569 3570 } 3571 3572 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3573 struct intel_encoder *encoder, 3574 const struct intel_crtc_state *old_crtc_state, 3575 const struct drm_connector_state *old_conn_state) 3576 { 3577 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3578 struct intel_connector *connector = 3579 to_intel_connector(old_conn_state->connector); 3580 3581 intel_dp->link.active = false; 3582 3583 intel_panel_unprepare(old_conn_state); 3584 intel_psr_disable(intel_dp, old_crtc_state); 3585 intel_alpm_disable(intel_dp); 3586 intel_edp_backlight_off(old_conn_state); 3587 /* Disable the decompression in DP Sink */ 3588 intel_dp_sink_disable_decompression(state, 3589 connector, old_crtc_state); 3590 /* Disable Ignore_MSA bit in DP Sink */ 3591 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3592 false); 3593 } 3594 3595 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3596 struct intel_encoder *encoder, 3597 const struct intel_crtc_state *old_crtc_state, 3598 const struct drm_connector_state *old_conn_state) 3599 { 3600 struct intel_display *display = to_intel_display(encoder); 3601 struct drm_connector *connector = old_conn_state->connector; 3602 3603 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3604 false, false)) 3605 drm_dbg_kms(display->drm, 3606 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3607 connector->base.id, connector->name); 3608 } 3609 3610 static void intel_ddi_disable(struct intel_atomic_state *state, 3611 struct intel_encoder *encoder, 3612 const struct intel_crtc_state *old_crtc_state, 3613 const struct drm_connector_state *old_conn_state) 3614 { 3615 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3616 3617 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3618 3619 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3620 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3621 old_conn_state); 3622 else 3623 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3624 old_conn_state); 3625 } 3626 3627 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3628 struct intel_encoder *encoder, 3629 const struct intel_crtc_state *crtc_state, 3630 const struct drm_connector_state *conn_state) 3631 { 3632 intel_ddi_set_dp_msa(crtc_state, conn_state); 3633 3634 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3635 3636 intel_backlight_update(state, encoder, crtc_state, conn_state); 3637 drm_connector_update_privacy_screen(conn_state); 3638 } 3639 3640 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3641 const struct intel_crtc_state *crtc_state, 3642 const struct drm_connector_state *conn_state) 3643 { 3644 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3645 } 3646 3647 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3648 struct intel_encoder *encoder, 3649 const struct intel_crtc_state *crtc_state, 3650 const struct drm_connector_state *conn_state) 3651 { 3652 3653 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3654 !intel_encoder_is_mst(encoder)) 3655 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3656 conn_state); 3657 3658 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3659 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3660 conn_state); 3661 3662 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3663 } 3664 3665 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3666 struct intel_encoder *encoder, 3667 struct intel_crtc *crtc) 3668 { 3669 struct intel_display *display = to_intel_display(encoder); 3670 const struct intel_crtc_state *crtc_state = 3671 intel_atomic_get_new_crtc_state(state, crtc); 3672 struct intel_crtc *pipe_crtc; 3673 3674 /* FIXME: Add MTL pll_mgr */ 3675 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3676 return; 3677 3678 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3679 intel_crtc_joined_pipe_mask(crtc_state)) 3680 intel_dpll_update_active(state, pipe_crtc, encoder); 3681 } 3682 3683 /* 3684 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3685 * encoder on its primary encoder. See also the comment for 3686 * intel_ddi_pre_enable(). 3687 */ 3688 static void 3689 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3690 struct intel_encoder *encoder, 3691 const struct intel_crtc_state *crtc_state, 3692 const struct drm_connector_state *conn_state) 3693 { 3694 struct intel_display *display = to_intel_display(encoder); 3695 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3696 bool is_tc_port = intel_encoder_is_tc(encoder); 3697 3698 if (is_tc_port) { 3699 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3700 3701 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3702 intel_ddi_update_active_dpll(state, encoder, crtc); 3703 } 3704 3705 main_link_aux_power_domain_get(dig_port, crtc_state); 3706 3707 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3708 /* 3709 * Program the lane count for static/dynamic connections on 3710 * Type-C ports. Skip this step for TBT. 3711 */ 3712 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3713 else if (display->platform.geminilake || display->platform.broxton) 3714 bxt_dpio_phy_set_lane_optim_mask(encoder, 3715 crtc_state->lane_lat_optim_mask); 3716 } 3717 3718 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3719 { 3720 struct intel_display *display = to_intel_display(encoder); 3721 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3722 int ln; 3723 3724 for (ln = 0; ln < 2; ln++) 3725 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3726 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3727 } 3728 3729 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3730 const struct intel_crtc_state *crtc_state) 3731 { 3732 struct intel_display *display = to_intel_display(crtc_state); 3733 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3734 struct intel_encoder *encoder = &dig_port->base; 3735 u32 dp_tp_ctl; 3736 3737 /* 3738 * TODO: To train with only a different voltage swing entry is not 3739 * necessary disable and enable port 3740 */ 3741 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3742 3743 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3744 3745 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3746 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3747 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3748 intel_dp_is_uhbr(crtc_state)) { 3749 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3750 } else { 3751 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3752 if (crtc_state->enhanced_framing) 3753 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3754 } 3755 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3756 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3757 3758 /* 6.f Enable D2D Link */ 3759 mtl_ddi_enable_d2d(encoder); 3760 3761 /* 6.g Configure voltage swing and related IO settings */ 3762 encoder->set_signal_levels(encoder, crtc_state); 3763 3764 /* 6.h Configure PORT_BUF_CTL1 */ 3765 mtl_port_buf_ctl_program(encoder, crtc_state); 3766 3767 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3768 if (DISPLAY_VER(display) >= 20) 3769 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3770 3771 intel_ddi_buf_enable(encoder, intel_dp->DP); 3772 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3773 3774 /* 3775 * 6.k If AUX-Less ALPM is going to be enabled: 3776 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3777 */ 3778 intel_alpm_port_configure(intel_dp, crtc_state); 3779 3780 /* 3781 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3782 * register 3783 */ 3784 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3785 } 3786 3787 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3788 const struct intel_crtc_state *crtc_state) 3789 { 3790 struct intel_display *display = to_intel_display(intel_dp); 3791 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3792 struct intel_encoder *encoder = &dig_port->base; 3793 u32 dp_tp_ctl; 3794 3795 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3796 3797 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3798 3799 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3800 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3801 intel_dp_is_uhbr(crtc_state)) { 3802 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3803 } else { 3804 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3805 if (crtc_state->enhanced_framing) 3806 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3807 } 3808 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3809 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3810 3811 if (display->platform.alderlake_p && 3812 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3813 adlp_tbt_to_dp_alt_switch_wa(encoder); 3814 3815 intel_ddi_buf_enable(encoder, intel_dp->DP); 3816 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3817 } 3818 3819 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3820 const struct intel_crtc_state *crtc_state, 3821 u8 dp_train_pat) 3822 { 3823 struct intel_display *display = to_intel_display(intel_dp); 3824 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3825 u32 temp; 3826 3827 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3828 3829 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3830 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3831 case DP_TRAINING_PATTERN_DISABLE: 3832 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3833 break; 3834 case DP_TRAINING_PATTERN_1: 3835 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3836 break; 3837 case DP_TRAINING_PATTERN_2: 3838 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3839 break; 3840 case DP_TRAINING_PATTERN_3: 3841 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3842 break; 3843 case DP_TRAINING_PATTERN_4: 3844 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3845 break; 3846 } 3847 3848 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3849 } 3850 3851 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3852 const struct intel_crtc_state *crtc_state) 3853 { 3854 struct intel_display *display = to_intel_display(intel_dp); 3855 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3856 enum port port = encoder->port; 3857 3858 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3859 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3860 3861 /* 3862 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3863 * reason we need to set idle transmission mode is to work around a HW 3864 * issue where we enable the pipe while not in idle link-training mode. 3865 * In this case there is requirement to wait for a minimum number of 3866 * idle patterns to be sent. 3867 */ 3868 if (port == PORT_A && DISPLAY_VER(display) < 12) 3869 return; 3870 3871 if (intel_de_wait_for_set(display, 3872 dp_tp_status_reg(encoder, crtc_state), 3873 DP_TP_STATUS_IDLE_DONE, 2)) 3874 drm_err(display->drm, 3875 "Timed out waiting for DP idle patterns\n"); 3876 } 3877 3878 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3879 enum transcoder cpu_transcoder) 3880 { 3881 if (cpu_transcoder == TRANSCODER_EDP) 3882 return false; 3883 3884 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3885 return false; 3886 3887 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3888 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3889 } 3890 3891 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3892 { 3893 if (crtc_state->port_clock > 594000) 3894 return 2; 3895 else 3896 return 0; 3897 } 3898 3899 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3900 { 3901 if (crtc_state->port_clock > 594000) 3902 return 3; 3903 else 3904 return 0; 3905 } 3906 3907 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3908 { 3909 if (crtc_state->port_clock > 594000) 3910 return 1; 3911 else 3912 return 0; 3913 } 3914 3915 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3916 { 3917 struct intel_display *display = to_intel_display(crtc_state); 3918 3919 if (DISPLAY_VER(display) >= 14) 3920 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3921 else if (DISPLAY_VER(display) >= 12) 3922 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3923 else if (display->platform.jasperlake || display->platform.elkhartlake) 3924 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3925 else if (DISPLAY_VER(display) >= 11) 3926 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3927 } 3928 3929 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3930 enum transcoder cpu_transcoder) 3931 { 3932 u32 master_select; 3933 3934 if (DISPLAY_VER(display) >= 11) { 3935 u32 ctl2 = intel_de_read(display, 3936 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3937 3938 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3939 return INVALID_TRANSCODER; 3940 3941 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3942 } else { 3943 u32 ctl = intel_de_read(display, 3944 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3945 3946 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3947 return INVALID_TRANSCODER; 3948 3949 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3950 } 3951 3952 if (master_select == 0) 3953 return TRANSCODER_EDP; 3954 else 3955 return master_select - 1; 3956 } 3957 3958 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3959 { 3960 struct intel_display *display = to_intel_display(crtc_state); 3961 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3962 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3963 enum transcoder cpu_transcoder; 3964 3965 crtc_state->master_transcoder = 3966 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3967 3968 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3969 enum intel_display_power_domain power_domain; 3970 intel_wakeref_t trans_wakeref; 3971 3972 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3973 trans_wakeref = intel_display_power_get_if_enabled(display, 3974 power_domain); 3975 3976 if (!trans_wakeref) 3977 continue; 3978 3979 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3980 crtc_state->cpu_transcoder) 3981 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3982 3983 intel_display_power_put(display, power_domain, trans_wakeref); 3984 } 3985 3986 drm_WARN_ON(display->drm, 3987 crtc_state->master_transcoder != INVALID_TRANSCODER && 3988 crtc_state->sync_mode_slaves_mask); 3989 } 3990 3991 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3992 struct intel_crtc_state *crtc_state, 3993 u32 ddi_func_ctl) 3994 { 3995 struct intel_display *display = to_intel_display(encoder); 3996 3997 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3998 if (DISPLAY_VER(display) >= 14) 3999 crtc_state->lane_count = 4000 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4001 else 4002 crtc_state->lane_count = 4; 4003 } 4004 4005 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4006 struct intel_crtc_state *crtc_state, 4007 u32 ddi_func_ctl) 4008 { 4009 crtc_state->has_hdmi_sink = true; 4010 4011 crtc_state->infoframes.enable |= 4012 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4013 4014 if (crtc_state->infoframes.enable) 4015 crtc_state->has_infoframe = true; 4016 4017 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4018 crtc_state->hdmi_scrambling = true; 4019 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4020 crtc_state->hdmi_high_tmds_clock_ratio = true; 4021 4022 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4023 } 4024 4025 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4026 struct intel_crtc_state *crtc_state, 4027 u32 ddi_func_ctl) 4028 { 4029 struct intel_display *display = to_intel_display(encoder); 4030 4031 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4032 crtc_state->enhanced_framing = 4033 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4034 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4035 } 4036 4037 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4038 struct intel_crtc_state *crtc_state, 4039 u32 ddi_func_ctl) 4040 { 4041 struct intel_display *display = to_intel_display(encoder); 4042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4043 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4045 4046 if (encoder->type == INTEL_OUTPUT_EDP) 4047 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4048 else 4049 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4050 crtc_state->lane_count = 4051 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4052 4053 if (DISPLAY_VER(display) >= 12 && 4054 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4055 crtc_state->mst_master_transcoder = 4056 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4057 4058 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4059 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4060 4061 crtc_state->enhanced_framing = 4062 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4063 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4064 4065 if (DISPLAY_VER(display) >= 11) 4066 crtc_state->fec_enable = 4067 intel_de_read(display, 4068 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4069 4070 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4071 crtc_state->infoframes.enable |= 4072 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4073 else 4074 crtc_state->infoframes.enable |= 4075 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4076 } 4077 4078 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4079 struct intel_crtc_state *crtc_state, 4080 u32 ddi_func_ctl) 4081 { 4082 struct intel_display *display = to_intel_display(encoder); 4083 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4084 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4085 4086 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4087 crtc_state->lane_count = 4088 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4089 4090 if (DISPLAY_VER(display) >= 12) 4091 crtc_state->mst_master_transcoder = 4092 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4093 4094 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4095 4096 if (DISPLAY_VER(display) >= 11) 4097 crtc_state->fec_enable = 4098 intel_de_read(display, 4099 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4100 4101 crtc_state->infoframes.enable |= 4102 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4103 } 4104 4105 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4106 struct intel_crtc_state *pipe_config) 4107 { 4108 struct intel_display *display = to_intel_display(encoder); 4109 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4110 u32 ddi_func_ctl, ddi_mode, flags = 0; 4111 4112 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4113 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4114 flags |= DRM_MODE_FLAG_PHSYNC; 4115 else 4116 flags |= DRM_MODE_FLAG_NHSYNC; 4117 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4118 flags |= DRM_MODE_FLAG_PVSYNC; 4119 else 4120 flags |= DRM_MODE_FLAG_NVSYNC; 4121 4122 pipe_config->hw.adjusted_mode.flags |= flags; 4123 4124 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4125 case TRANS_DDI_BPC_6: 4126 pipe_config->pipe_bpp = 18; 4127 break; 4128 case TRANS_DDI_BPC_8: 4129 pipe_config->pipe_bpp = 24; 4130 break; 4131 case TRANS_DDI_BPC_10: 4132 pipe_config->pipe_bpp = 30; 4133 break; 4134 case TRANS_DDI_BPC_12: 4135 pipe_config->pipe_bpp = 36; 4136 break; 4137 default: 4138 break; 4139 } 4140 4141 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4142 4143 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4144 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4145 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4146 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4147 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4148 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4150 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4152 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4153 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4154 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4155 4156 /* 4157 * If this is true, we know we're being called from mst stream 4158 * encoder's ->get_config(). 4159 */ 4160 if (intel_dp_mst_active_streams(intel_dp)) 4161 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4162 else 4163 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4164 } 4165 } 4166 4167 /* 4168 * Note: Also called from the ->get_config of the MST stream encoders on their 4169 * primary encoder, via the platform specific hooks here. See also the comment 4170 * for intel_ddi_pre_enable(). 4171 */ 4172 static void intel_ddi_get_config(struct intel_encoder *encoder, 4173 struct intel_crtc_state *pipe_config) 4174 { 4175 struct intel_display *display = to_intel_display(encoder); 4176 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4177 4178 /* XXX: DSI transcoder paranoia */ 4179 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4180 return; 4181 4182 intel_ddi_read_func_ctl(encoder, pipe_config); 4183 4184 intel_ddi_mso_get_config(encoder, pipe_config); 4185 4186 pipe_config->has_audio = 4187 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4188 4189 if (encoder->type == INTEL_OUTPUT_EDP) 4190 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4191 4192 ddi_dotclock_get(pipe_config); 4193 4194 if (display->platform.geminilake || display->platform.broxton) 4195 pipe_config->lane_lat_optim_mask = 4196 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4197 4198 intel_ddi_compute_min_voltage_level(pipe_config); 4199 4200 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4201 4202 intel_read_infoframe(encoder, pipe_config, 4203 HDMI_INFOFRAME_TYPE_AVI, 4204 &pipe_config->infoframes.avi); 4205 intel_read_infoframe(encoder, pipe_config, 4206 HDMI_INFOFRAME_TYPE_SPD, 4207 &pipe_config->infoframes.spd); 4208 intel_read_infoframe(encoder, pipe_config, 4209 HDMI_INFOFRAME_TYPE_VENDOR, 4210 &pipe_config->infoframes.hdmi); 4211 intel_read_infoframe(encoder, pipe_config, 4212 HDMI_INFOFRAME_TYPE_DRM, 4213 &pipe_config->infoframes.drm); 4214 4215 if (DISPLAY_VER(display) >= 8) 4216 bdw_get_trans_port_sync_config(pipe_config); 4217 4218 intel_psr_get_config(encoder, pipe_config); 4219 4220 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4221 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4222 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4223 4224 intel_audio_codec_get_config(encoder, pipe_config); 4225 } 4226 4227 void intel_ddi_get_clock(struct intel_encoder *encoder, 4228 struct intel_crtc_state *crtc_state, 4229 struct intel_dpll *pll) 4230 { 4231 struct intel_display *display = to_intel_display(encoder); 4232 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4233 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4234 bool pll_active; 4235 4236 if (drm_WARN_ON(display->drm, !pll)) 4237 return; 4238 4239 port_dpll->pll = pll; 4240 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4241 drm_WARN_ON(display->drm, !pll_active); 4242 4243 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4244 4245 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4246 &crtc_state->dpll_hw_state); 4247 } 4248 4249 static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, 4250 struct intel_crtc_state *crtc_state) 4251 { 4252 intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll); 4253 4254 if (crtc_state->dpll_hw_state.ltpll.tbt_mode) 4255 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4256 else 4257 crtc_state->port_clock = 4258 intel_lt_phy_calc_port_clock(encoder, crtc_state); 4259 intel_ddi_get_config(encoder, crtc_state); 4260 } 4261 4262 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4263 struct intel_crtc_state *crtc_state) 4264 { 4265 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4266 4267 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4268 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4269 else 4270 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4271 4272 intel_ddi_get_config(encoder, crtc_state); 4273 } 4274 4275 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4276 struct intel_crtc_state *crtc_state) 4277 { 4278 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4279 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4280 4281 intel_ddi_get_config(encoder, crtc_state); 4282 } 4283 4284 static void adls_ddi_get_config(struct intel_encoder *encoder, 4285 struct intel_crtc_state *crtc_state) 4286 { 4287 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4288 intel_ddi_get_config(encoder, crtc_state); 4289 } 4290 4291 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4292 struct intel_crtc_state *crtc_state) 4293 { 4294 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4295 intel_ddi_get_config(encoder, crtc_state); 4296 } 4297 4298 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4299 struct intel_crtc_state *crtc_state) 4300 { 4301 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4302 intel_ddi_get_config(encoder, crtc_state); 4303 } 4304 4305 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4306 struct intel_crtc_state *crtc_state) 4307 { 4308 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4309 intel_ddi_get_config(encoder, crtc_state); 4310 } 4311 4312 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4313 { 4314 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4315 } 4316 4317 static enum icl_port_dpll_id 4318 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4319 const struct intel_crtc_state *crtc_state) 4320 { 4321 struct intel_display *display = to_intel_display(encoder); 4322 const struct intel_dpll *pll = crtc_state->intel_dpll; 4323 4324 if (drm_WARN_ON(display->drm, !pll)) 4325 return ICL_PORT_DPLL_DEFAULT; 4326 4327 if (icl_ddi_tc_pll_is_tbt(pll)) 4328 return ICL_PORT_DPLL_DEFAULT; 4329 else 4330 return ICL_PORT_DPLL_MG_PHY; 4331 } 4332 4333 enum icl_port_dpll_id 4334 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4335 const struct intel_crtc_state *crtc_state) 4336 { 4337 if (!encoder->port_pll_type) 4338 return ICL_PORT_DPLL_DEFAULT; 4339 4340 return encoder->port_pll_type(encoder, crtc_state); 4341 } 4342 4343 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4344 struct intel_crtc_state *crtc_state, 4345 struct intel_dpll *pll) 4346 { 4347 struct intel_display *display = to_intel_display(encoder); 4348 enum icl_port_dpll_id port_dpll_id; 4349 struct icl_port_dpll *port_dpll; 4350 bool pll_active; 4351 4352 if (drm_WARN_ON(display->drm, !pll)) 4353 return; 4354 4355 if (icl_ddi_tc_pll_is_tbt(pll)) 4356 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4357 else 4358 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4359 4360 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4361 4362 port_dpll->pll = pll; 4363 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4364 drm_WARN_ON(display->drm, !pll_active); 4365 4366 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4367 4368 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4369 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4370 else 4371 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4372 &crtc_state->dpll_hw_state); 4373 } 4374 4375 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4376 struct intel_crtc_state *crtc_state) 4377 { 4378 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4379 intel_ddi_get_config(encoder, crtc_state); 4380 } 4381 4382 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4383 struct intel_crtc_state *crtc_state) 4384 { 4385 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4386 intel_ddi_get_config(encoder, crtc_state); 4387 } 4388 4389 static void skl_ddi_get_config(struct intel_encoder *encoder, 4390 struct intel_crtc_state *crtc_state) 4391 { 4392 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4393 intel_ddi_get_config(encoder, crtc_state); 4394 } 4395 4396 void hsw_ddi_get_config(struct intel_encoder *encoder, 4397 struct intel_crtc_state *crtc_state) 4398 { 4399 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4400 intel_ddi_get_config(encoder, crtc_state); 4401 } 4402 4403 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4404 const struct intel_crtc_state *crtc_state) 4405 { 4406 if (intel_encoder_is_tc(encoder)) 4407 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4408 crtc_state); 4409 4410 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4411 (!crtc_state && intel_encoder_is_dp(encoder))) 4412 intel_dp_sync_state(encoder, crtc_state); 4413 } 4414 4415 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4416 struct intel_crtc_state *crtc_state) 4417 { 4418 struct intel_display *display = to_intel_display(encoder); 4419 bool fastset = true; 4420 4421 if (intel_encoder_is_tc(encoder)) { 4422 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4423 encoder->base.base.id, encoder->base.name); 4424 crtc_state->uapi.mode_changed = true; 4425 fastset = false; 4426 } 4427 4428 if (intel_crtc_has_dp_encoder(crtc_state) && 4429 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4430 fastset = false; 4431 4432 return fastset; 4433 } 4434 4435 static enum intel_output_type 4436 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4437 struct intel_crtc_state *crtc_state, 4438 struct drm_connector_state *conn_state) 4439 { 4440 switch (conn_state->connector->connector_type) { 4441 case DRM_MODE_CONNECTOR_HDMIA: 4442 return INTEL_OUTPUT_HDMI; 4443 case DRM_MODE_CONNECTOR_eDP: 4444 return INTEL_OUTPUT_EDP; 4445 case DRM_MODE_CONNECTOR_DisplayPort: 4446 return INTEL_OUTPUT_DP; 4447 default: 4448 MISSING_CASE(conn_state->connector->connector_type); 4449 return INTEL_OUTPUT_UNUSED; 4450 } 4451 } 4452 4453 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4454 struct intel_crtc_state *pipe_config, 4455 struct drm_connector_state *conn_state) 4456 { 4457 struct intel_display *display = to_intel_display(encoder); 4458 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4459 enum port port = encoder->port; 4460 int ret; 4461 4462 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4463 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4464 4465 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4466 pipe_config->has_hdmi_sink = 4467 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4468 4469 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4470 } else { 4471 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4472 } 4473 4474 if (ret) 4475 return ret; 4476 4477 if (display->platform.haswell && crtc->pipe == PIPE_A && 4478 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4479 pipe_config->pch_pfit.force_thru = 4480 pipe_config->pch_pfit.enabled || 4481 pipe_config->crc_enabled; 4482 4483 if (display->platform.geminilake || display->platform.broxton) 4484 pipe_config->lane_lat_optim_mask = 4485 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4486 4487 intel_ddi_compute_min_voltage_level(pipe_config); 4488 4489 return 0; 4490 } 4491 4492 static bool mode_equal(const struct drm_display_mode *mode1, 4493 const struct drm_display_mode *mode2) 4494 { 4495 return drm_mode_match(mode1, mode2, 4496 DRM_MODE_MATCH_TIMINGS | 4497 DRM_MODE_MATCH_FLAGS | 4498 DRM_MODE_MATCH_3D_FLAGS) && 4499 mode1->clock == mode2->clock; /* we want an exact match */ 4500 } 4501 4502 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4503 const struct intel_link_m_n *m_n_2) 4504 { 4505 return m_n_1->tu == m_n_2->tu && 4506 m_n_1->data_m == m_n_2->data_m && 4507 m_n_1->data_n == m_n_2->data_n && 4508 m_n_1->link_m == m_n_2->link_m && 4509 m_n_1->link_n == m_n_2->link_n; 4510 } 4511 4512 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4513 const struct intel_crtc_state *crtc_state2) 4514 { 4515 /* 4516 * FIXME the modeset sequence is currently wrong and 4517 * can't deal with joiner + port sync at the same time. 4518 */ 4519 return crtc_state1->hw.active && crtc_state2->hw.active && 4520 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4521 crtc_state1->output_types == crtc_state2->output_types && 4522 crtc_state1->output_format == crtc_state2->output_format && 4523 crtc_state1->lane_count == crtc_state2->lane_count && 4524 crtc_state1->port_clock == crtc_state2->port_clock && 4525 mode_equal(&crtc_state1->hw.adjusted_mode, 4526 &crtc_state2->hw.adjusted_mode) && 4527 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4528 } 4529 4530 static u8 4531 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4532 int tile_group_id) 4533 { 4534 struct intel_display *display = to_intel_display(ref_crtc_state); 4535 struct drm_connector *connector; 4536 const struct drm_connector_state *conn_state; 4537 struct intel_atomic_state *state = 4538 to_intel_atomic_state(ref_crtc_state->uapi.state); 4539 u8 transcoders = 0; 4540 int i; 4541 4542 /* 4543 * We don't enable port sync on BDW due to missing w/as and 4544 * due to not having adjusted the modeset sequence appropriately. 4545 */ 4546 if (DISPLAY_VER(display) < 9) 4547 return 0; 4548 4549 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4550 return 0; 4551 4552 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4553 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4554 const struct intel_crtc_state *crtc_state; 4555 4556 if (!crtc) 4557 continue; 4558 4559 if (!connector->has_tile || 4560 connector->tile_group->id != 4561 tile_group_id) 4562 continue; 4563 crtc_state = intel_atomic_get_new_crtc_state(state, 4564 crtc); 4565 if (!crtcs_port_sync_compatible(ref_crtc_state, 4566 crtc_state)) 4567 continue; 4568 transcoders |= BIT(crtc_state->cpu_transcoder); 4569 } 4570 4571 return transcoders; 4572 } 4573 4574 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4575 struct intel_crtc_state *crtc_state, 4576 struct drm_connector_state *conn_state) 4577 { 4578 struct intel_display *display = to_intel_display(encoder); 4579 struct drm_connector *connector = conn_state->connector; 4580 u8 port_sync_transcoders = 0; 4581 int ret = 0; 4582 4583 if (intel_crtc_has_dp_encoder(crtc_state)) 4584 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); 4585 4586 if (ret) 4587 return ret; 4588 4589 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4590 encoder->base.base.id, encoder->base.name, 4591 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4592 4593 if (connector->has_tile) 4594 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4595 connector->tile_group->id); 4596 4597 /* 4598 * EDP Transcoders cannot be ensalved 4599 * make them a master always when present 4600 */ 4601 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4602 crtc_state->master_transcoder = TRANSCODER_EDP; 4603 else 4604 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4605 4606 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4607 crtc_state->master_transcoder = INVALID_TRANSCODER; 4608 crtc_state->sync_mode_slaves_mask = 4609 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4610 } 4611 4612 return 0; 4613 } 4614 4615 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4616 { 4617 struct intel_display *display = to_intel_display(encoder->dev); 4618 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4619 4620 intel_dp_encoder_flush_work(encoder); 4621 if (intel_encoder_is_tc(&dig_port->base)) 4622 intel_tc_port_cleanup(dig_port); 4623 intel_display_power_flush_work(display); 4624 4625 drm_encoder_cleanup(encoder); 4626 kfree(dig_port->hdcp.port_data.streams); 4627 kfree(dig_port); 4628 } 4629 4630 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4631 { 4632 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4633 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4634 4635 intel_dp->reset_link_params = true; 4636 intel_dp_invalidate_source_oui(intel_dp); 4637 4638 intel_pps_encoder_reset(intel_dp); 4639 4640 if (intel_encoder_is_tc(&dig_port->base)) 4641 intel_tc_port_init_mode(dig_port); 4642 } 4643 4644 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4645 { 4646 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4647 4648 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4649 4650 return 0; 4651 } 4652 4653 static const struct drm_encoder_funcs intel_ddi_funcs = { 4654 .reset = intel_ddi_encoder_reset, 4655 .destroy = intel_ddi_encoder_destroy, 4656 .late_register = intel_ddi_encoder_late_register, 4657 }; 4658 4659 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4660 { 4661 struct intel_display *display = to_intel_display(dig_port); 4662 struct intel_connector *connector; 4663 enum port port = dig_port->base.port; 4664 4665 connector = intel_connector_alloc(); 4666 if (!connector) 4667 return -ENOMEM; 4668 4669 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4670 if (DISPLAY_VER(display) >= 14) 4671 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4672 else 4673 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4674 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4675 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4676 4677 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4678 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4679 4680 if (!intel_dp_init_connector(dig_port, connector)) { 4681 kfree(connector); 4682 return -EINVAL; 4683 } 4684 4685 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4686 struct drm_privacy_screen *privacy_screen; 4687 4688 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4689 if (!IS_ERR(privacy_screen)) { 4690 drm_connector_attach_privacy_screen_provider(&connector->base, 4691 privacy_screen); 4692 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4693 drm_warn(display->drm, "Error getting privacy-screen\n"); 4694 } 4695 } 4696 4697 return 0; 4698 } 4699 4700 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4701 struct drm_modeset_acquire_ctx *ctx) 4702 { 4703 struct intel_display *display = to_intel_display(encoder); 4704 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4705 struct intel_connector *connector = hdmi->attached_connector; 4706 struct i2c_adapter *ddc = connector->base.ddc; 4707 struct drm_connector_state *conn_state; 4708 struct intel_crtc_state *crtc_state; 4709 struct intel_crtc *crtc; 4710 u8 config; 4711 int ret; 4712 4713 if (connector->base.status != connector_status_connected) 4714 return 0; 4715 4716 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4717 ctx); 4718 if (ret) 4719 return ret; 4720 4721 conn_state = connector->base.state; 4722 4723 crtc = to_intel_crtc(conn_state->crtc); 4724 if (!crtc) 4725 return 0; 4726 4727 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4728 if (ret) 4729 return ret; 4730 4731 crtc_state = to_intel_crtc_state(crtc->base.state); 4732 4733 drm_WARN_ON(display->drm, 4734 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4735 4736 if (!crtc_state->hw.active) 4737 return 0; 4738 4739 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4740 !crtc_state->hdmi_scrambling) 4741 return 0; 4742 4743 if (conn_state->commit && 4744 !try_wait_for_completion(&conn_state->commit->hw_done)) 4745 return 0; 4746 4747 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4748 if (ret < 0) { 4749 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4750 connector->base.base.id, connector->base.name, ret); 4751 return 0; 4752 } 4753 4754 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4755 crtc_state->hdmi_high_tmds_clock_ratio && 4756 !!(config & SCDC_SCRAMBLING_ENABLE) == 4757 crtc_state->hdmi_scrambling) 4758 return 0; 4759 4760 /* 4761 * HDMI 2.0 says that one should not send scrambled data 4762 * prior to configuring the sink scrambling, and that 4763 * TMDS clock/data transmission should be suspended when 4764 * changing the TMDS clock rate in the sink. So let's 4765 * just do a full modeset here, even though some sinks 4766 * would be perfectly happy if were to just reconfigure 4767 * the SCDC settings on the fly. 4768 */ 4769 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4770 } 4771 4772 static void intel_ddi_link_check(struct intel_encoder *encoder) 4773 { 4774 struct intel_display *display = to_intel_display(encoder); 4775 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4776 4777 /* TODO: Move checking the HDMI link state here as well. */ 4778 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4779 4780 intel_dp_link_check(encoder); 4781 } 4782 4783 static enum intel_hotplug_state 4784 intel_ddi_hotplug(struct intel_encoder *encoder, 4785 struct intel_connector *connector) 4786 { 4787 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4788 struct intel_dp *intel_dp = &dig_port->dp; 4789 bool is_tc = intel_encoder_is_tc(encoder); 4790 struct drm_modeset_acquire_ctx ctx; 4791 enum intel_hotplug_state state; 4792 int ret; 4793 4794 if (intel_dp_test_phy(intel_dp)) 4795 return INTEL_HOTPLUG_UNCHANGED; 4796 4797 state = intel_encoder_hotplug(encoder, connector); 4798 4799 if (!intel_tc_port_link_reset(dig_port)) { 4800 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4801 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4802 ret = intel_hdmi_reset_link(encoder, &ctx); 4803 drm_WARN_ON(encoder->base.dev, ret); 4804 } else { 4805 intel_dp_check_link_state(intel_dp); 4806 } 4807 } 4808 4809 /* 4810 * Unpowered type-c dongles can take some time to boot and be 4811 * responsible, so here giving some time to those dongles to power up 4812 * and then retrying the probe. 4813 * 4814 * On many platforms the HDMI live state signal is known to be 4815 * unreliable, so we can't use it to detect if a sink is connected or 4816 * not. Instead we detect if it's connected based on whether we can 4817 * read the EDID or not. That in turn has a problem during disconnect, 4818 * since the HPD interrupt may be raised before the DDC lines get 4819 * disconnected (due to how the required length of DDC vs. HPD 4820 * connector pins are specified) and so we'll still be able to get a 4821 * valid EDID. To solve this schedule another detection cycle if this 4822 * time around we didn't detect any change in the sink's connection 4823 * status. 4824 * 4825 * Type-c connectors which get their HPD signal deasserted then 4826 * reasserted, without unplugging/replugging the sink from the 4827 * connector, introduce a delay until the AUX channel communication 4828 * becomes functional. Retry the detection for 5 seconds on type-c 4829 * connectors to account for this delay. 4830 */ 4831 if (state == INTEL_HOTPLUG_UNCHANGED && 4832 connector->hotplug_retries < (is_tc ? 5 : 1) && 4833 !dig_port->dp.is_mst) 4834 state = INTEL_HOTPLUG_RETRY; 4835 4836 return state; 4837 } 4838 4839 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4840 { 4841 struct intel_display *display = to_intel_display(encoder); 4842 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4843 4844 return intel_de_read(display, SDEISR) & bit; 4845 } 4846 4847 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4848 { 4849 struct intel_display *display = to_intel_display(encoder); 4850 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4851 4852 return intel_de_read(display, DEISR) & bit; 4853 } 4854 4855 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4856 { 4857 struct intel_display *display = to_intel_display(encoder); 4858 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4859 4860 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4861 } 4862 4863 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4864 { 4865 struct intel_connector *connector; 4866 enum port port = dig_port->base.port; 4867 4868 connector = intel_connector_alloc(); 4869 if (!connector) 4870 return -ENOMEM; 4871 4872 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4873 4874 if (!intel_hdmi_init_connector(dig_port, connector)) { 4875 /* 4876 * HDMI connector init failures may just mean conflicting DDC 4877 * pins or not having enough lanes. Handle them gracefully, but 4878 * don't fail the entire DDI init. 4879 */ 4880 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4881 kfree(connector); 4882 } 4883 4884 return 0; 4885 } 4886 4887 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4888 { 4889 struct intel_display *display = to_intel_display(dig_port); 4890 4891 if (dig_port->base.port != PORT_A) 4892 return false; 4893 4894 if (dig_port->ddi_a_4_lanes) 4895 return false; 4896 4897 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4898 * supported configuration 4899 */ 4900 if (display->platform.geminilake || display->platform.broxton) 4901 return true; 4902 4903 return false; 4904 } 4905 4906 static int 4907 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4908 { 4909 struct intel_display *display = to_intel_display(dig_port); 4910 enum port port = dig_port->base.port; 4911 int max_lanes = 4; 4912 4913 if (DISPLAY_VER(display) >= 11) 4914 return max_lanes; 4915 4916 if (port == PORT_A || port == PORT_E) { 4917 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4918 max_lanes = port == PORT_A ? 4 : 0; 4919 else 4920 /* Both A and E share 2 lanes */ 4921 max_lanes = 2; 4922 } 4923 4924 /* 4925 * Some BIOS might fail to set this bit on port A if eDP 4926 * wasn't lit up at boot. Force this bit set when needed 4927 * so we use the proper lane count for our calculations. 4928 */ 4929 if (intel_ddi_a_force_4_lanes(dig_port)) { 4930 drm_dbg_kms(display->drm, 4931 "Forcing DDI_A_4_LANES for port A\n"); 4932 dig_port->ddi_a_4_lanes = true; 4933 max_lanes = 4; 4934 } 4935 4936 return max_lanes; 4937 } 4938 4939 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4940 { 4941 if (port >= PORT_D_XELPD) 4942 return HPD_PORT_D + port - PORT_D_XELPD; 4943 else if (port >= PORT_TC1) 4944 return HPD_PORT_TC1 + port - PORT_TC1; 4945 else 4946 return HPD_PORT_A + port - PORT_A; 4947 } 4948 4949 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4950 { 4951 if (port >= PORT_TC1) 4952 return HPD_PORT_C + port - PORT_TC1; 4953 else 4954 return HPD_PORT_A + port - PORT_A; 4955 } 4956 4957 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4958 { 4959 if (port >= PORT_TC1) 4960 return HPD_PORT_TC1 + port - PORT_TC1; 4961 else 4962 return HPD_PORT_A + port - PORT_A; 4963 } 4964 4965 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4966 { 4967 if (HAS_PCH_TGP(display)) 4968 return tgl_hpd_pin(display, port); 4969 4970 if (port >= PORT_TC1) 4971 return HPD_PORT_C + port - PORT_TC1; 4972 else 4973 return HPD_PORT_A + port - PORT_A; 4974 } 4975 4976 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4977 { 4978 if (port >= PORT_C) 4979 return HPD_PORT_TC1 + port - PORT_C; 4980 else 4981 return HPD_PORT_A + port - PORT_A; 4982 } 4983 4984 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4985 { 4986 if (port == PORT_D) 4987 return HPD_PORT_A; 4988 4989 if (HAS_PCH_TGP(display)) 4990 return icl_hpd_pin(display, port); 4991 4992 return HPD_PORT_A + port - PORT_A; 4993 } 4994 4995 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4996 { 4997 if (HAS_PCH_TGP(display)) 4998 return icl_hpd_pin(display, port); 4999 5000 return HPD_PORT_A + port - PORT_A; 5001 } 5002 5003 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 5004 { 5005 if (DISPLAY_VER(display) >= 12) 5006 return port >= PORT_TC1; 5007 else if (DISPLAY_VER(display) >= 11) 5008 return port >= PORT_C; 5009 else 5010 return false; 5011 } 5012 5013 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5014 { 5015 intel_dp_encoder_suspend(encoder); 5016 } 5017 5018 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5019 { 5020 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5021 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5022 5023 /* 5024 * TODO: Move this to intel_dp_encoder_suspend(), 5025 * once modeset locking around that is removed. 5026 */ 5027 intel_encoder_link_check_flush_work(encoder); 5028 intel_tc_port_suspend(dig_port); 5029 } 5030 5031 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5032 { 5033 if (intel_encoder_is_dp(encoder)) 5034 intel_dp_encoder_shutdown(encoder); 5035 if (intel_encoder_is_hdmi(encoder)) 5036 intel_hdmi_encoder_shutdown(encoder); 5037 } 5038 5039 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5040 { 5041 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5042 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5043 5044 intel_tc_port_cleanup(dig_port); 5045 } 5046 5047 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5048 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5049 5050 static bool port_strap_detected(struct intel_display *display, enum port port) 5051 { 5052 /* straps not used on skl+ */ 5053 if (DISPLAY_VER(display) >= 9) 5054 return true; 5055 5056 switch (port) { 5057 case PORT_A: 5058 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5059 case PORT_B: 5060 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5061 case PORT_C: 5062 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5063 case PORT_D: 5064 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5065 case PORT_E: 5066 return true; /* no strap for DDI-E */ 5067 default: 5068 MISSING_CASE(port); 5069 return false; 5070 } 5071 } 5072 5073 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5074 { 5075 return init_dp || intel_encoder_is_tc(encoder); 5076 } 5077 5078 static bool assert_has_icl_dsi(struct intel_display *display) 5079 { 5080 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5081 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5082 "Platform does not support DSI\n"); 5083 } 5084 5085 static bool port_in_use(struct intel_display *display, enum port port) 5086 { 5087 struct intel_encoder *encoder; 5088 5089 for_each_intel_encoder(display->drm, encoder) { 5090 /* FIXME what about second port for dual link DSI? */ 5091 if (encoder->port == port) 5092 return true; 5093 } 5094 5095 return false; 5096 } 5097 5098 static const char *intel_ddi_encoder_name(struct intel_display *display, 5099 enum port port, enum phy phy, 5100 struct seq_buf *s) 5101 { 5102 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5103 seq_buf_printf(s, "DDI %c/PHY %c", 5104 port_name(port - PORT_D_XELPD + PORT_D), 5105 phy_name(phy)); 5106 } else if (DISPLAY_VER(display) >= 12) { 5107 enum tc_port tc_port = intel_port_to_tc(display, port); 5108 5109 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5110 port >= PORT_TC1 ? "TC" : "", 5111 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5112 tc_port != TC_PORT_NONE ? "TC" : "", 5113 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5114 } else if (DISPLAY_VER(display) >= 11) { 5115 enum tc_port tc_port = intel_port_to_tc(display, port); 5116 5117 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5118 port_name(port), 5119 port >= PORT_C ? " (TC)" : "", 5120 tc_port != TC_PORT_NONE ? "TC" : "", 5121 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5122 } else { 5123 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5124 } 5125 5126 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5127 5128 return seq_buf_str(s); 5129 } 5130 5131 void intel_ddi_init(struct intel_display *display, 5132 const struct intel_bios_encoder_data *devdata) 5133 { 5134 struct intel_digital_port *dig_port; 5135 struct intel_encoder *encoder; 5136 DECLARE_SEQ_BUF(encoder_name, 20); 5137 bool init_hdmi, init_dp; 5138 enum port port; 5139 enum phy phy; 5140 u32 ddi_buf_ctl; 5141 5142 port = intel_bios_encoder_port(devdata); 5143 if (port == PORT_NONE) 5144 return; 5145 5146 if (!port_strap_detected(display, port)) { 5147 drm_dbg_kms(display->drm, 5148 "Port %c strap not detected\n", port_name(port)); 5149 return; 5150 } 5151 5152 if (!assert_port_valid(display, port)) 5153 return; 5154 5155 if (port_in_use(display, port)) { 5156 drm_dbg_kms(display->drm, 5157 "Port %c already claimed\n", port_name(port)); 5158 return; 5159 } 5160 5161 if (intel_bios_encoder_supports_dsi(devdata)) { 5162 /* BXT/GLK handled elsewhere, for now at least */ 5163 if (!assert_has_icl_dsi(display)) 5164 return; 5165 5166 icl_dsi_init(display, devdata); 5167 return; 5168 } 5169 5170 phy = intel_port_to_phy(display, port); 5171 5172 /* 5173 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5174 * have taken over some of the PHYs and made them unavailable to the 5175 * driver. In that case we should skip initializing the corresponding 5176 * outputs. 5177 */ 5178 if (intel_hti_uses_phy(display, phy)) { 5179 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5180 port_name(port), phy_name(phy)); 5181 return; 5182 } 5183 5184 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5185 intel_bios_encoder_supports_hdmi(devdata); 5186 init_dp = intel_bios_encoder_supports_dp(devdata); 5187 5188 if (intel_bios_encoder_is_lspcon(devdata)) { 5189 /* 5190 * Lspcon device needs to be driven with DP connector 5191 * with special detection sequence. So make sure DP 5192 * is initialized before lspcon. 5193 */ 5194 init_dp = true; 5195 init_hdmi = false; 5196 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5197 port_name(port)); 5198 } 5199 5200 if (!init_dp && !init_hdmi) { 5201 drm_dbg_kms(display->drm, 5202 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5203 port_name(port)); 5204 return; 5205 } 5206 5207 if (intel_phy_is_snps(display, phy) && 5208 display->snps.phy_failed_calibration & BIT(phy)) { 5209 drm_dbg_kms(display->drm, 5210 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5211 phy_name(phy)); 5212 } 5213 5214 dig_port = intel_dig_port_alloc(); 5215 if (!dig_port) 5216 return; 5217 5218 encoder = &dig_port->base; 5219 encoder->devdata = devdata; 5220 5221 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5222 DRM_MODE_ENCODER_TMDS, "%s", 5223 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5224 5225 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5226 5227 encoder->hotplug = intel_ddi_hotplug; 5228 encoder->compute_output_type = intel_ddi_compute_output_type; 5229 encoder->compute_config = intel_ddi_compute_config; 5230 encoder->compute_config_late = intel_ddi_compute_config_late; 5231 encoder->enable = intel_ddi_enable; 5232 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5233 encoder->pre_enable = intel_ddi_pre_enable; 5234 encoder->disable = intel_ddi_disable; 5235 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5236 encoder->post_disable = intel_ddi_post_disable; 5237 encoder->update_pipe = intel_ddi_update_pipe; 5238 encoder->audio_enable = intel_audio_codec_enable; 5239 encoder->audio_disable = intel_audio_codec_disable; 5240 encoder->get_hw_state = intel_ddi_get_hw_state; 5241 encoder->sync_state = intel_ddi_sync_state; 5242 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5243 encoder->suspend = intel_ddi_encoder_suspend; 5244 encoder->shutdown = intel_ddi_encoder_shutdown; 5245 encoder->get_power_domains = intel_ddi_get_power_domains; 5246 5247 encoder->type = INTEL_OUTPUT_DDI; 5248 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5249 encoder->port = port; 5250 encoder->cloneable = 0; 5251 encoder->pipe_mask = ~0; 5252 5253 if (HAS_LT_PHY(display)) { 5254 encoder->enable_clock = intel_xe3plpd_pll_enable; 5255 encoder->disable_clock = intel_xe3plpd_pll_disable; 5256 encoder->port_pll_type = intel_mtl_port_pll_type; 5257 encoder->get_config = xe3plpd_ddi_get_config; 5258 } else if (DISPLAY_VER(display) >= 14) { 5259 encoder->enable_clock = intel_mtl_pll_enable; 5260 encoder->disable_clock = intel_mtl_pll_disable; 5261 encoder->port_pll_type = intel_mtl_port_pll_type; 5262 encoder->get_config = mtl_ddi_get_config; 5263 } else if (display->platform.dg2) { 5264 encoder->enable_clock = intel_mpllb_enable; 5265 encoder->disable_clock = intel_mpllb_disable; 5266 encoder->get_config = dg2_ddi_get_config; 5267 } else if (display->platform.alderlake_s) { 5268 encoder->enable_clock = adls_ddi_enable_clock; 5269 encoder->disable_clock = adls_ddi_disable_clock; 5270 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5271 encoder->get_config = adls_ddi_get_config; 5272 } else if (display->platform.rocketlake) { 5273 encoder->enable_clock = rkl_ddi_enable_clock; 5274 encoder->disable_clock = rkl_ddi_disable_clock; 5275 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5276 encoder->get_config = rkl_ddi_get_config; 5277 } else if (display->platform.dg1) { 5278 encoder->enable_clock = dg1_ddi_enable_clock; 5279 encoder->disable_clock = dg1_ddi_disable_clock; 5280 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5281 encoder->get_config = dg1_ddi_get_config; 5282 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5283 if (intel_ddi_is_tc(display, port)) { 5284 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5285 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5286 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5287 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5288 encoder->get_config = icl_ddi_combo_get_config; 5289 } else { 5290 encoder->enable_clock = icl_ddi_combo_enable_clock; 5291 encoder->disable_clock = icl_ddi_combo_disable_clock; 5292 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5293 encoder->get_config = icl_ddi_combo_get_config; 5294 } 5295 } else if (DISPLAY_VER(display) >= 11) { 5296 if (intel_ddi_is_tc(display, port)) { 5297 encoder->enable_clock = icl_ddi_tc_enable_clock; 5298 encoder->disable_clock = icl_ddi_tc_disable_clock; 5299 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5300 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5301 encoder->get_config = icl_ddi_tc_get_config; 5302 } else { 5303 encoder->enable_clock = icl_ddi_combo_enable_clock; 5304 encoder->disable_clock = icl_ddi_combo_disable_clock; 5305 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5306 encoder->get_config = icl_ddi_combo_get_config; 5307 } 5308 } else if (display->platform.geminilake || display->platform.broxton) { 5309 /* BXT/GLK have fixed PLL->port mapping */ 5310 encoder->get_config = bxt_ddi_get_config; 5311 } else if (DISPLAY_VER(display) == 9) { 5312 encoder->enable_clock = skl_ddi_enable_clock; 5313 encoder->disable_clock = skl_ddi_disable_clock; 5314 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5315 encoder->get_config = skl_ddi_get_config; 5316 } else if (display->platform.broadwell || display->platform.haswell) { 5317 encoder->enable_clock = hsw_ddi_enable_clock; 5318 encoder->disable_clock = hsw_ddi_disable_clock; 5319 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5320 encoder->get_config = hsw_ddi_get_config; 5321 } 5322 5323 if (HAS_LT_PHY(display)) { 5324 encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5325 } else if (DISPLAY_VER(display) >= 14) { 5326 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5327 } else if (display->platform.dg2) { 5328 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5329 } else if (DISPLAY_VER(display) >= 12) { 5330 if (intel_encoder_is_combo(encoder)) 5331 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5332 else 5333 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5334 } else if (DISPLAY_VER(display) >= 11) { 5335 if (intel_encoder_is_combo(encoder)) 5336 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5337 else 5338 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5339 } else if (display->platform.geminilake || display->platform.broxton) { 5340 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5341 } else { 5342 encoder->set_signal_levels = hsw_set_signal_levels; 5343 } 5344 5345 intel_ddi_buf_trans_init(encoder); 5346 5347 if (DISPLAY_VER(display) >= 13) 5348 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5349 else if (display->platform.dg1) 5350 encoder->hpd_pin = dg1_hpd_pin(display, port); 5351 else if (display->platform.rocketlake) 5352 encoder->hpd_pin = rkl_hpd_pin(display, port); 5353 else if (DISPLAY_VER(display) >= 12) 5354 encoder->hpd_pin = tgl_hpd_pin(display, port); 5355 else if (display->platform.jasperlake || display->platform.elkhartlake) 5356 encoder->hpd_pin = ehl_hpd_pin(display, port); 5357 else if (DISPLAY_VER(display) == 11) 5358 encoder->hpd_pin = icl_hpd_pin(display, port); 5359 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5360 encoder->hpd_pin = skl_hpd_pin(display, port); 5361 else 5362 encoder->hpd_pin = intel_hpd_pin_default(port); 5363 5364 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5365 5366 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5367 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5368 5369 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5370 5371 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5372 5373 if (need_aux_ch(encoder, init_dp)) { 5374 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5375 if (dig_port->aux_ch == AUX_CH_NONE) 5376 goto err; 5377 } 5378 5379 if (intel_encoder_is_tc(encoder)) { 5380 bool is_legacy = 5381 !intel_bios_encoder_supports_typec_usb(devdata) && 5382 !intel_bios_encoder_supports_tbt(devdata); 5383 5384 if (!is_legacy && init_hdmi) { 5385 is_legacy = !init_dp; 5386 5387 drm_dbg_kms(display->drm, 5388 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5389 port_name(port), 5390 str_yes_no(init_dp), 5391 is_legacy ? "legacy" : "non-legacy"); 5392 } 5393 5394 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5395 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5396 5397 dig_port->lock = intel_tc_port_lock; 5398 dig_port->unlock = intel_tc_port_unlock; 5399 5400 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5401 goto err; 5402 } 5403 5404 drm_WARN_ON(display->drm, port > PORT_I); 5405 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5406 5407 if (DISPLAY_VER(display) >= 11) { 5408 if (intel_encoder_is_tc(encoder)) 5409 dig_port->connected = intel_tc_port_connected; 5410 else 5411 dig_port->connected = lpt_digital_port_connected; 5412 } else if (display->platform.geminilake || display->platform.broxton) { 5413 dig_port->connected = bdw_digital_port_connected; 5414 } else if (DISPLAY_VER(display) == 9) { 5415 dig_port->connected = lpt_digital_port_connected; 5416 } else if (display->platform.broadwell) { 5417 if (port == PORT_A) 5418 dig_port->connected = bdw_digital_port_connected; 5419 else 5420 dig_port->connected = lpt_digital_port_connected; 5421 } else if (display->platform.haswell) { 5422 if (port == PORT_A) 5423 dig_port->connected = hsw_digital_port_connected; 5424 else 5425 dig_port->connected = lpt_digital_port_connected; 5426 } 5427 5428 intel_infoframe_init(dig_port); 5429 5430 if (init_dp) { 5431 if (intel_ddi_init_dp_connector(dig_port)) 5432 goto err; 5433 5434 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5435 5436 if (dig_port->dp.mso_link_count) 5437 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5438 } 5439 5440 /* 5441 * In theory we don't need the encoder->type check, 5442 * but leave it just in case we have some really bad VBTs... 5443 */ 5444 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5445 if (intel_ddi_init_hdmi_connector(dig_port)) 5446 goto err; 5447 } 5448 5449 return; 5450 5451 err: 5452 drm_encoder_cleanup(&encoder->base); 5453 kfree(dig_port); 5454 } 5455