1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_11_6; 587 u32 cri_txdeemph_override_5_0; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x18, 0x00, 0x00 }, /* 0 0 */ 594 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 595 { 0x24, 0x00, 0x0C }, /* 0 2 */ 596 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 597 { 0x21, 0x00, 0x00 }, /* 1 0 */ 598 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 599 { 0x30, 0x00, 0x0F }, /* 1 2 */ 600 { 0x31, 0x00, 0x03 }, /* 2 0 */ 601 { 0x34, 0x00, 0x0B }, /* 2 1 */ 602 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 606 /* Voltage swing pre-emphasis */ 607 { 0x18, 0x00, 0x00 }, /* 0 0 */ 608 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 609 { 0x24, 0x00, 0x0C }, /* 0 2 */ 610 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 611 { 0x26, 0x00, 0x00 }, /* 1 0 */ 612 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 613 { 0x33, 0x00, 0x0C }, /* 1 2 */ 614 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 615 { 0x36, 0x00, 0x09 }, /* 2 1 */ 616 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 617 }; 618 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 620 /* HDMI Preset VS Pre-emph */ 621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 631 }; 632 633 struct tgl_dkl_phy_ddi_buf_trans { 634 u32 dkl_vswing_control; 635 u32 dkl_preshoot_control; 636 u32 dkl_de_emphasis_control; 637 }; 638 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 640 /* VS pre-emp Non-trans mV Pre-emph dB */ 641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 651 }; 652 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 654 /* VS pre-emp Non-trans mV Pre-emph dB */ 655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 665 }; 666 667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 668 /* HDMI Preset VS Pre-emph */ 669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 679 }; 680 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 682 /* NT mV Trans mV db */ 683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 693 }; 694 695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 696 /* NT mV Trans mV db */ 697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 707 }; 708 709 static const struct ddi_buf_trans * 710 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 711 { 712 if (dev_priv->vbt.edp.low_vswing) { 713 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 714 return bdw_ddi_translations_edp; 715 } else { 716 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 717 return bdw_ddi_translations_dp; 718 } 719 } 720 721 static const struct ddi_buf_trans * 722 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 723 { 724 if (IS_SKL_ULX(dev_priv)) { 725 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 726 return skl_y_ddi_translations_dp; 727 } else if (IS_SKL_ULT(dev_priv)) { 728 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 729 return skl_u_ddi_translations_dp; 730 } else { 731 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 732 return skl_ddi_translations_dp; 733 } 734 } 735 736 static const struct ddi_buf_trans * 737 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 738 { 739 if (IS_KBL_ULX(dev_priv) || 740 IS_CFL_ULX(dev_priv) || 741 IS_CML_ULX(dev_priv)) { 742 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 743 return kbl_y_ddi_translations_dp; 744 } else if (IS_KBL_ULT(dev_priv) || 745 IS_CFL_ULT(dev_priv) || 746 IS_CML_ULT(dev_priv)) { 747 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 748 return kbl_u_ddi_translations_dp; 749 } else { 750 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 751 return kbl_ddi_translations_dp; 752 } 753 } 754 755 static const struct ddi_buf_trans * 756 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 757 { 758 if (dev_priv->vbt.edp.low_vswing) { 759 if (IS_SKL_ULX(dev_priv) || 760 IS_KBL_ULX(dev_priv) || 761 IS_CFL_ULX(dev_priv) || 762 IS_CML_ULX(dev_priv)) { 763 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 764 return skl_y_ddi_translations_edp; 765 } else if (IS_SKL_ULT(dev_priv) || 766 IS_KBL_ULT(dev_priv) || 767 IS_CFL_ULT(dev_priv) || 768 IS_CML_ULT(dev_priv)) { 769 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 770 return skl_u_ddi_translations_edp; 771 } else { 772 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 773 return skl_ddi_translations_edp; 774 } 775 } 776 777 if (IS_KABYLAKE(dev_priv) || 778 IS_COFFEELAKE(dev_priv) || 779 IS_COMETLAKE(dev_priv)) 780 return kbl_get_buf_trans_dp(dev_priv, n_entries); 781 else 782 return skl_get_buf_trans_dp(dev_priv, n_entries); 783 } 784 785 static const struct ddi_buf_trans * 786 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 787 { 788 if (IS_SKL_ULX(dev_priv) || 789 IS_KBL_ULX(dev_priv) || 790 IS_CFL_ULX(dev_priv) || 791 IS_CML_ULX(dev_priv)) { 792 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 793 return skl_y_ddi_translations_hdmi; 794 } else { 795 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 796 return skl_ddi_translations_hdmi; 797 } 798 } 799 800 static int skl_buf_trans_num_entries(enum port port, int n_entries) 801 { 802 /* Only DDIA and DDIE can select the 10th register with DP */ 803 if (port == PORT_A || port == PORT_E) 804 return min(n_entries, 10); 805 else 806 return min(n_entries, 9); 807 } 808 809 static const struct ddi_buf_trans * 810 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 811 enum port port, int *n_entries) 812 { 813 if (IS_KABYLAKE(dev_priv) || 814 IS_COFFEELAKE(dev_priv) || 815 IS_COMETLAKE(dev_priv)) { 816 const struct ddi_buf_trans *ddi_translations = 817 kbl_get_buf_trans_dp(dev_priv, n_entries); 818 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 819 return ddi_translations; 820 } else if (IS_SKYLAKE(dev_priv)) { 821 const struct ddi_buf_trans *ddi_translations = 822 skl_get_buf_trans_dp(dev_priv, n_entries); 823 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 824 return ddi_translations; 825 } else if (IS_BROADWELL(dev_priv)) { 826 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 827 return bdw_ddi_translations_dp; 828 } else if (IS_HASWELL(dev_priv)) { 829 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 830 return hsw_ddi_translations_dp; 831 } 832 833 *n_entries = 0; 834 return NULL; 835 } 836 837 static const struct ddi_buf_trans * 838 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 839 enum port port, int *n_entries) 840 { 841 if (IS_GEN9_BC(dev_priv)) { 842 const struct ddi_buf_trans *ddi_translations = 843 skl_get_buf_trans_edp(dev_priv, n_entries); 844 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 845 return ddi_translations; 846 } else if (IS_BROADWELL(dev_priv)) { 847 return bdw_get_buf_trans_edp(dev_priv, n_entries); 848 } else if (IS_HASWELL(dev_priv)) { 849 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 850 return hsw_ddi_translations_dp; 851 } 852 853 *n_entries = 0; 854 return NULL; 855 } 856 857 static const struct ddi_buf_trans * 858 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 859 int *n_entries) 860 { 861 if (IS_BROADWELL(dev_priv)) { 862 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 863 return bdw_ddi_translations_fdi; 864 } else if (IS_HASWELL(dev_priv)) { 865 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 866 return hsw_ddi_translations_fdi; 867 } 868 869 *n_entries = 0; 870 return NULL; 871 } 872 873 static const struct ddi_buf_trans * 874 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 875 int *n_entries) 876 { 877 if (IS_GEN9_BC(dev_priv)) { 878 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 879 } else if (IS_BROADWELL(dev_priv)) { 880 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 881 return bdw_ddi_translations_hdmi; 882 } else if (IS_HASWELL(dev_priv)) { 883 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 884 return hsw_ddi_translations_hdmi; 885 } 886 887 *n_entries = 0; 888 return NULL; 889 } 890 891 static const struct bxt_ddi_buf_trans * 892 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 893 { 894 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 895 return bxt_ddi_translations_dp; 896 } 897 898 static const struct bxt_ddi_buf_trans * 899 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 900 { 901 if (dev_priv->vbt.edp.low_vswing) { 902 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 903 return bxt_ddi_translations_edp; 904 } 905 906 return bxt_get_buf_trans_dp(dev_priv, n_entries); 907 } 908 909 static const struct bxt_ddi_buf_trans * 910 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 911 { 912 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 913 return bxt_ddi_translations_hdmi; 914 } 915 916 static const struct cnl_ddi_buf_trans * 917 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 918 { 919 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 920 921 if (voltage == VOLTAGE_INFO_0_85V) { 922 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 923 return cnl_ddi_translations_hdmi_0_85V; 924 } else if (voltage == VOLTAGE_INFO_0_95V) { 925 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 926 return cnl_ddi_translations_hdmi_0_95V; 927 } else if (voltage == VOLTAGE_INFO_1_05V) { 928 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 929 return cnl_ddi_translations_hdmi_1_05V; 930 } else { 931 *n_entries = 1; /* shut up gcc */ 932 MISSING_CASE(voltage); 933 } 934 return NULL; 935 } 936 937 static const struct cnl_ddi_buf_trans * 938 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 939 { 940 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 941 942 if (voltage == VOLTAGE_INFO_0_85V) { 943 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 944 return cnl_ddi_translations_dp_0_85V; 945 } else if (voltage == VOLTAGE_INFO_0_95V) { 946 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 947 return cnl_ddi_translations_dp_0_95V; 948 } else if (voltage == VOLTAGE_INFO_1_05V) { 949 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 950 return cnl_ddi_translations_dp_1_05V; 951 } else { 952 *n_entries = 1; /* shut up gcc */ 953 MISSING_CASE(voltage); 954 } 955 return NULL; 956 } 957 958 static const struct cnl_ddi_buf_trans * 959 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 960 { 961 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 962 963 if (dev_priv->vbt.edp.low_vswing) { 964 if (voltage == VOLTAGE_INFO_0_85V) { 965 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 966 return cnl_ddi_translations_edp_0_85V; 967 } else if (voltage == VOLTAGE_INFO_0_95V) { 968 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 969 return cnl_ddi_translations_edp_0_95V; 970 } else if (voltage == VOLTAGE_INFO_1_05V) { 971 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 972 return cnl_ddi_translations_edp_1_05V; 973 } else { 974 *n_entries = 1; /* shut up gcc */ 975 MISSING_CASE(voltage); 976 } 977 return NULL; 978 } else { 979 return cnl_get_buf_trans_dp(dev_priv, n_entries); 980 } 981 } 982 983 static const struct cnl_ddi_buf_trans * 984 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 985 int *n_entries) 986 { 987 if (type == INTEL_OUTPUT_HDMI) { 988 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 989 return icl_combo_phy_ddi_translations_hdmi; 990 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 991 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 992 return icl_combo_phy_ddi_translations_edp_hbr3; 993 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 994 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 995 return icl_combo_phy_ddi_translations_edp_hbr2; 996 } 997 998 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 999 return icl_combo_phy_ddi_translations_dp_hbr2; 1000 } 1001 1002 static const struct icl_mg_phy_ddi_buf_trans * 1003 icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1004 int *n_entries) 1005 { 1006 if (type == INTEL_OUTPUT_HDMI) { 1007 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1008 return icl_mg_phy_ddi_translations_hdmi; 1009 } else if (rate > 270000) { 1010 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1011 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1012 } 1013 1014 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1015 return icl_mg_phy_ddi_translations_rbr_hbr; 1016 } 1017 1018 static const struct cnl_ddi_buf_trans * 1019 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1020 int *n_entries) 1021 { 1022 if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) { 1023 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1024 return ehl_combo_phy_ddi_translations_dp; 1025 } 1026 1027 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 1028 } 1029 1030 static const struct cnl_ddi_buf_trans * 1031 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1032 int *n_entries) 1033 { 1034 if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { 1035 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 1036 } else if (rate > 270000) { 1037 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1038 return tgl_combo_phy_ddi_translations_dp_hbr2; 1039 } 1040 1041 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1042 return tgl_combo_phy_ddi_translations_dp_hbr; 1043 } 1044 1045 static const struct tgl_dkl_phy_ddi_buf_trans * 1046 tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1047 int *n_entries) 1048 { 1049 if (type == INTEL_OUTPUT_HDMI) { 1050 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1051 return tgl_dkl_phy_hdmi_ddi_trans; 1052 } else if (rate > 270000) { 1053 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1054 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1055 } 1056 1057 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1058 return tgl_dkl_phy_dp_ddi_trans; 1059 } 1060 1061 static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 1062 { 1063 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1064 int n_entries, level, default_entry; 1065 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1066 1067 if (INTEL_GEN(dev_priv) >= 12) { 1068 if (intel_phy_is_combo(dev_priv, phy)) 1069 tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 1070 0, &n_entries); 1071 else 1072 tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, 1073 &n_entries); 1074 default_entry = n_entries - 1; 1075 } else if (INTEL_GEN(dev_priv) == 11) { 1076 if (intel_phy_is_combo(dev_priv, phy)) 1077 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 1078 0, &n_entries); 1079 else 1080 icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, 1081 &n_entries); 1082 default_entry = n_entries - 1; 1083 } else if (IS_CANNONLAKE(dev_priv)) { 1084 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 1085 default_entry = n_entries - 1; 1086 } else if (IS_GEN9_LP(dev_priv)) { 1087 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 1088 default_entry = n_entries - 1; 1089 } else if (IS_GEN9_BC(dev_priv)) { 1090 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1091 default_entry = 8; 1092 } else if (IS_BROADWELL(dev_priv)) { 1093 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1094 default_entry = 7; 1095 } else if (IS_HASWELL(dev_priv)) { 1096 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1097 default_entry = 6; 1098 } else { 1099 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1100 return 0; 1101 } 1102 1103 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1104 return 0; 1105 1106 level = intel_bios_hdmi_level_shift(encoder); 1107 if (level < 0) 1108 level = default_entry; 1109 1110 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1111 level = n_entries - 1; 1112 1113 return level; 1114 } 1115 1116 /* 1117 * Starting with Haswell, DDI port buffers must be programmed with correct 1118 * values in advance. This function programs the correct values for 1119 * DP/eDP/FDI use cases. 1120 */ 1121 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1122 const struct intel_crtc_state *crtc_state) 1123 { 1124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1125 u32 iboost_bit = 0; 1126 int i, n_entries; 1127 enum port port = encoder->port; 1128 const struct ddi_buf_trans *ddi_translations; 1129 1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1131 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1132 &n_entries); 1133 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1134 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 1135 &n_entries); 1136 else 1137 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 1138 &n_entries); 1139 1140 /* If we're boosting the current, set bit 31 of trans1 */ 1141 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1142 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1143 1144 for (i = 0; i < n_entries; i++) { 1145 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1146 ddi_translations[i].trans1 | iboost_bit); 1147 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1148 ddi_translations[i].trans2); 1149 } 1150 } 1151 1152 /* 1153 * Starting with Haswell, DDI port buffers must be programmed with correct 1154 * values in advance. This function programs the correct values for 1155 * HDMI/DVI use cases. 1156 */ 1157 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1158 int level) 1159 { 1160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1161 u32 iboost_bit = 0; 1162 int n_entries; 1163 enum port port = encoder->port; 1164 const struct ddi_buf_trans *ddi_translations; 1165 1166 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1167 1168 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1169 return; 1170 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1171 level = n_entries - 1; 1172 1173 /* If we're boosting the current, set bit 31 of trans1 */ 1174 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1175 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1176 1177 /* Entry 9 is for HDMI: */ 1178 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1179 ddi_translations[level].trans1 | iboost_bit); 1180 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1181 ddi_translations[level].trans2); 1182 } 1183 1184 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1185 enum port port) 1186 { 1187 i915_reg_t reg = DDI_BUF_CTL(port); 1188 int i; 1189 1190 for (i = 0; i < 16; i++) { 1191 udelay(1); 1192 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) 1193 return; 1194 } 1195 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", 1196 port_name(port)); 1197 } 1198 1199 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1200 { 1201 switch (pll->info->id) { 1202 case DPLL_ID_WRPLL1: 1203 return PORT_CLK_SEL_WRPLL1; 1204 case DPLL_ID_WRPLL2: 1205 return PORT_CLK_SEL_WRPLL2; 1206 case DPLL_ID_SPLL: 1207 return PORT_CLK_SEL_SPLL; 1208 case DPLL_ID_LCPLL_810: 1209 return PORT_CLK_SEL_LCPLL_810; 1210 case DPLL_ID_LCPLL_1350: 1211 return PORT_CLK_SEL_LCPLL_1350; 1212 case DPLL_ID_LCPLL_2700: 1213 return PORT_CLK_SEL_LCPLL_2700; 1214 default: 1215 MISSING_CASE(pll->info->id); 1216 return PORT_CLK_SEL_NONE; 1217 } 1218 } 1219 1220 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1221 const struct intel_crtc_state *crtc_state) 1222 { 1223 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1224 int clock = crtc_state->port_clock; 1225 const enum intel_dpll_id id = pll->info->id; 1226 1227 switch (id) { 1228 default: 1229 /* 1230 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1231 * here, so do warn if this get passed in 1232 */ 1233 MISSING_CASE(id); 1234 return DDI_CLK_SEL_NONE; 1235 case DPLL_ID_ICL_TBTPLL: 1236 switch (clock) { 1237 case 162000: 1238 return DDI_CLK_SEL_TBT_162; 1239 case 270000: 1240 return DDI_CLK_SEL_TBT_270; 1241 case 540000: 1242 return DDI_CLK_SEL_TBT_540; 1243 case 810000: 1244 return DDI_CLK_SEL_TBT_810; 1245 default: 1246 MISSING_CASE(clock); 1247 return DDI_CLK_SEL_NONE; 1248 } 1249 case DPLL_ID_ICL_MGPLL1: 1250 case DPLL_ID_ICL_MGPLL2: 1251 case DPLL_ID_ICL_MGPLL3: 1252 case DPLL_ID_ICL_MGPLL4: 1253 case DPLL_ID_TGL_MGPLL5: 1254 case DPLL_ID_TGL_MGPLL6: 1255 return DDI_CLK_SEL_MG; 1256 } 1257 } 1258 1259 /* Starting with Haswell, different DDI ports can work in FDI mode for 1260 * connection to the PCH-located connectors. For this, it is necessary to train 1261 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1262 * 1263 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1264 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1265 * DDI A (which is used for eDP) 1266 */ 1267 1268 void hsw_fdi_link_train(struct intel_encoder *encoder, 1269 const struct intel_crtc_state *crtc_state) 1270 { 1271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1272 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1273 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1274 1275 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1276 1277 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1278 * mode set "sequence for CRT port" document: 1279 * - TP1 to TP2 time with the default value 1280 * - FDI delay to 90h 1281 * 1282 * WaFDIAutoLinkSetTimingOverrride:hsw 1283 */ 1284 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1285 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1286 1287 /* Enable the PCH Receiver FDI PLL */ 1288 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1289 FDI_RX_PLL_ENABLE | 1290 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1291 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1292 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1293 udelay(220); 1294 1295 /* Switch from Rawclk to PCDclk */ 1296 rx_ctl_val |= FDI_PCDCLK; 1297 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1298 1299 /* Configure Port Clock Select */ 1300 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1301 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1302 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1303 1304 /* Start the training iterating through available voltages and emphasis, 1305 * testing each value twice. */ 1306 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1307 /* Configure DP_TP_CTL with auto-training */ 1308 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1309 DP_TP_CTL_FDI_AUTOTRAIN | 1310 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1311 DP_TP_CTL_LINK_TRAIN_PAT1 | 1312 DP_TP_CTL_ENABLE); 1313 1314 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1315 * DDI E does not support port reversal, the functionality is 1316 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1317 * port reversal bit */ 1318 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1319 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1320 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1321 1322 udelay(600); 1323 1324 /* Program PCH FDI Receiver TU */ 1325 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1326 1327 /* Enable PCH FDI Receiver with auto-training */ 1328 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1329 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1330 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1331 1332 /* Wait for FDI receiver lane calibration */ 1333 udelay(30); 1334 1335 /* Unset FDI_RX_MISC pwrdn lanes */ 1336 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1337 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1338 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1339 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1340 1341 /* Wait for FDI auto training time */ 1342 udelay(5); 1343 1344 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1345 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1346 drm_dbg_kms(&dev_priv->drm, 1347 "FDI link training done on step %d\n", i); 1348 break; 1349 } 1350 1351 /* 1352 * Leave things enabled even if we failed to train FDI. 1353 * Results in less fireworks from the state checker. 1354 */ 1355 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1356 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1357 break; 1358 } 1359 1360 rx_ctl_val &= ~FDI_RX_ENABLE; 1361 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1362 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1363 1364 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1365 temp &= ~DDI_BUF_CTL_ENABLE; 1366 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1367 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1368 1369 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1370 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1371 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1372 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1373 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1374 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1375 1376 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1377 1378 /* Reset FDI_RX_MISC pwrdn lanes */ 1379 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1380 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1381 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1382 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1383 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1384 } 1385 1386 /* Enable normal pixel sending for FDI */ 1387 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1388 DP_TP_CTL_FDI_AUTOTRAIN | 1389 DP_TP_CTL_LINK_TRAIN_NORMAL | 1390 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1391 DP_TP_CTL_ENABLE); 1392 } 1393 1394 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1395 { 1396 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1397 struct intel_digital_port *intel_dig_port = 1398 enc_to_dig_port(encoder); 1399 1400 intel_dp->DP = intel_dig_port->saved_port_bits | 1401 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1402 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1403 } 1404 1405 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1406 enum port port) 1407 { 1408 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1409 1410 switch (val) { 1411 case DDI_CLK_SEL_NONE: 1412 return 0; 1413 case DDI_CLK_SEL_TBT_162: 1414 return 162000; 1415 case DDI_CLK_SEL_TBT_270: 1416 return 270000; 1417 case DDI_CLK_SEL_TBT_540: 1418 return 540000; 1419 case DDI_CLK_SEL_TBT_810: 1420 return 810000; 1421 default: 1422 MISSING_CASE(val); 1423 return 0; 1424 } 1425 } 1426 1427 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1428 { 1429 int dotclock; 1430 1431 if (pipe_config->has_pch_encoder) 1432 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1433 &pipe_config->fdi_m_n); 1434 else if (intel_crtc_has_dp_encoder(pipe_config)) 1435 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1436 &pipe_config->dp_m_n); 1437 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1438 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1439 else 1440 dotclock = pipe_config->port_clock; 1441 1442 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1443 !intel_crtc_has_dp_encoder(pipe_config)) 1444 dotclock *= 2; 1445 1446 if (pipe_config->pixel_multiplier) 1447 dotclock /= pipe_config->pixel_multiplier; 1448 1449 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1450 } 1451 1452 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1453 struct intel_crtc_state *pipe_config) 1454 { 1455 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1456 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1457 1458 if (intel_phy_is_tc(dev_priv, phy) && 1459 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1460 DPLL_ID_ICL_TBTPLL) 1461 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1462 encoder->port); 1463 else 1464 pipe_config->port_clock = 1465 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1466 1467 ddi_dotclock_get(pipe_config); 1468 } 1469 1470 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1471 const struct drm_connector_state *conn_state) 1472 { 1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1475 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1476 u32 temp; 1477 1478 if (!intel_crtc_has_dp_encoder(crtc_state)) 1479 return; 1480 1481 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1482 1483 temp = DP_MSA_MISC_SYNC_CLOCK; 1484 1485 switch (crtc_state->pipe_bpp) { 1486 case 18: 1487 temp |= DP_MSA_MISC_6_BPC; 1488 break; 1489 case 24: 1490 temp |= DP_MSA_MISC_8_BPC; 1491 break; 1492 case 30: 1493 temp |= DP_MSA_MISC_10_BPC; 1494 break; 1495 case 36: 1496 temp |= DP_MSA_MISC_12_BPC; 1497 break; 1498 default: 1499 MISSING_CASE(crtc_state->pipe_bpp); 1500 break; 1501 } 1502 1503 /* nonsense combination */ 1504 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1505 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1506 1507 if (crtc_state->limited_color_range) 1508 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1509 1510 /* 1511 * As per DP 1.2 spec section 2.3.4.3 while sending 1512 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1513 * colorspace information. 1514 */ 1515 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1516 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1517 1518 /* 1519 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1520 * of Color Encoding Format and Content Color Gamut] while sending 1521 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1522 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1523 */ 1524 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1525 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1526 1527 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1528 } 1529 1530 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1531 { 1532 if (master_transcoder == TRANSCODER_EDP) 1533 return 0; 1534 else 1535 return master_transcoder + 1; 1536 } 1537 1538 /* 1539 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1540 * 1541 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1542 * intel_ddi_config_transcoder_func(). 1543 */ 1544 static u32 1545 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1546 const struct intel_crtc_state *crtc_state) 1547 { 1548 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1550 enum pipe pipe = crtc->pipe; 1551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1552 enum port port = encoder->port; 1553 u32 temp; 1554 1555 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1556 temp = TRANS_DDI_FUNC_ENABLE; 1557 if (INTEL_GEN(dev_priv) >= 12) 1558 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1559 else 1560 temp |= TRANS_DDI_SELECT_PORT(port); 1561 1562 switch (crtc_state->pipe_bpp) { 1563 case 18: 1564 temp |= TRANS_DDI_BPC_6; 1565 break; 1566 case 24: 1567 temp |= TRANS_DDI_BPC_8; 1568 break; 1569 case 30: 1570 temp |= TRANS_DDI_BPC_10; 1571 break; 1572 case 36: 1573 temp |= TRANS_DDI_BPC_12; 1574 break; 1575 default: 1576 BUG(); 1577 } 1578 1579 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1580 temp |= TRANS_DDI_PVSYNC; 1581 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1582 temp |= TRANS_DDI_PHSYNC; 1583 1584 if (cpu_transcoder == TRANSCODER_EDP) { 1585 switch (pipe) { 1586 case PIPE_A: 1587 /* On Haswell, can only use the always-on power well for 1588 * eDP when not using the panel fitter, and when not 1589 * using motion blur mitigation (which we don't 1590 * support). */ 1591 if (crtc_state->pch_pfit.force_thru) 1592 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1593 else 1594 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1595 break; 1596 case PIPE_B: 1597 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1598 break; 1599 case PIPE_C: 1600 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1601 break; 1602 default: 1603 BUG(); 1604 break; 1605 } 1606 } 1607 1608 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1609 if (crtc_state->has_hdmi_sink) 1610 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1611 else 1612 temp |= TRANS_DDI_MODE_SELECT_DVI; 1613 1614 if (crtc_state->hdmi_scrambling) 1615 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1616 if (crtc_state->hdmi_high_tmds_clock_ratio) 1617 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1618 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1619 temp |= TRANS_DDI_MODE_SELECT_FDI; 1620 temp |= (crtc_state->fdi_lanes - 1) << 1; 1621 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1622 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1623 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1624 1625 if (INTEL_GEN(dev_priv) >= 12) { 1626 enum transcoder master; 1627 1628 master = crtc_state->mst_master_transcoder; 1629 drm_WARN_ON(&dev_priv->drm, 1630 master == INVALID_TRANSCODER); 1631 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1632 } 1633 } else { 1634 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1635 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1636 } 1637 1638 if (IS_GEN_RANGE(dev_priv, 8, 10) && 1639 crtc_state->master_transcoder != INVALID_TRANSCODER) { 1640 u8 master_select = 1641 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 1642 1643 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 1644 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 1645 } 1646 1647 return temp; 1648 } 1649 1650 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 1651 const struct intel_crtc_state *crtc_state) 1652 { 1653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1655 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1656 u32 ctl; 1657 1658 if (INTEL_GEN(dev_priv) >= 11) { 1659 enum transcoder master_transcoder = crtc_state->master_transcoder; 1660 u32 ctl2 = 0; 1661 1662 if (master_transcoder != INVALID_TRANSCODER) { 1663 u8 master_select = 1664 bdw_trans_port_sync_master_select(master_transcoder); 1665 1666 ctl2 |= PORT_SYNC_MODE_ENABLE | 1667 PORT_SYNC_MODE_MASTER_SELECT(master_select); 1668 } 1669 1670 intel_de_write(dev_priv, 1671 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 1672 } 1673 1674 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1675 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1676 ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1677 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1678 } 1679 1680 /* 1681 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1682 * bit. 1683 */ 1684 static void 1685 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 1686 const struct intel_crtc_state *crtc_state) 1687 { 1688 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1689 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1690 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1691 u32 ctl; 1692 1693 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1694 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1695 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1696 } 1697 1698 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1699 { 1700 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1701 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1702 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1703 u32 ctl; 1704 1705 if (INTEL_GEN(dev_priv) >= 11) 1706 intel_de_write(dev_priv, 1707 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 1708 1709 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1710 1711 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1712 1713 if (IS_GEN_RANGE(dev_priv, 8, 10)) 1714 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 1715 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 1716 1717 if (INTEL_GEN(dev_priv) >= 12) { 1718 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1719 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 1720 TRANS_DDI_MODE_SELECT_MASK); 1721 } 1722 } else { 1723 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1724 } 1725 1726 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1727 1728 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1729 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1730 drm_dbg_kms(&dev_priv->drm, 1731 "Quirk Increase DDI disabled time\n"); 1732 /* Quirk time at 100ms for reliable operation */ 1733 msleep(100); 1734 } 1735 } 1736 1737 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1738 bool enable) 1739 { 1740 struct drm_device *dev = intel_encoder->base.dev; 1741 struct drm_i915_private *dev_priv = to_i915(dev); 1742 intel_wakeref_t wakeref; 1743 enum pipe pipe = 0; 1744 int ret = 0; 1745 u32 tmp; 1746 1747 wakeref = intel_display_power_get_if_enabled(dev_priv, 1748 intel_encoder->power_domain); 1749 if (drm_WARN_ON(dev, !wakeref)) 1750 return -ENXIO; 1751 1752 if (drm_WARN_ON(dev, 1753 !intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1754 ret = -EIO; 1755 goto out; 1756 } 1757 1758 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); 1759 if (enable) 1760 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1761 else 1762 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1763 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); 1764 out: 1765 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1766 return ret; 1767 } 1768 1769 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1770 { 1771 struct drm_device *dev = intel_connector->base.dev; 1772 struct drm_i915_private *dev_priv = to_i915(dev); 1773 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1774 int type = intel_connector->base.connector_type; 1775 enum port port = encoder->port; 1776 enum transcoder cpu_transcoder; 1777 intel_wakeref_t wakeref; 1778 enum pipe pipe = 0; 1779 u32 tmp; 1780 bool ret; 1781 1782 wakeref = intel_display_power_get_if_enabled(dev_priv, 1783 encoder->power_domain); 1784 if (!wakeref) 1785 return false; 1786 1787 if (!encoder->get_hw_state(encoder, &pipe)) { 1788 ret = false; 1789 goto out; 1790 } 1791 1792 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 1793 cpu_transcoder = TRANSCODER_EDP; 1794 else 1795 cpu_transcoder = (enum transcoder) pipe; 1796 1797 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1798 1799 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1800 case TRANS_DDI_MODE_SELECT_HDMI: 1801 case TRANS_DDI_MODE_SELECT_DVI: 1802 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1803 break; 1804 1805 case TRANS_DDI_MODE_SELECT_DP_SST: 1806 ret = type == DRM_MODE_CONNECTOR_eDP || 1807 type == DRM_MODE_CONNECTOR_DisplayPort; 1808 break; 1809 1810 case TRANS_DDI_MODE_SELECT_DP_MST: 1811 /* if the transcoder is in MST state then 1812 * connector isn't connected */ 1813 ret = false; 1814 break; 1815 1816 case TRANS_DDI_MODE_SELECT_FDI: 1817 ret = type == DRM_MODE_CONNECTOR_VGA; 1818 break; 1819 1820 default: 1821 ret = false; 1822 break; 1823 } 1824 1825 out: 1826 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1827 1828 return ret; 1829 } 1830 1831 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1832 u8 *pipe_mask, bool *is_dp_mst) 1833 { 1834 struct drm_device *dev = encoder->base.dev; 1835 struct drm_i915_private *dev_priv = to_i915(dev); 1836 enum port port = encoder->port; 1837 intel_wakeref_t wakeref; 1838 enum pipe p; 1839 u32 tmp; 1840 u8 mst_pipe_mask; 1841 1842 *pipe_mask = 0; 1843 *is_dp_mst = false; 1844 1845 wakeref = intel_display_power_get_if_enabled(dev_priv, 1846 encoder->power_domain); 1847 if (!wakeref) 1848 return; 1849 1850 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1851 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1852 goto out; 1853 1854 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 1855 tmp = intel_de_read(dev_priv, 1856 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1857 1858 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1859 default: 1860 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1861 /* fallthrough */ 1862 case TRANS_DDI_EDP_INPUT_A_ON: 1863 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1864 *pipe_mask = BIT(PIPE_A); 1865 break; 1866 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1867 *pipe_mask = BIT(PIPE_B); 1868 break; 1869 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1870 *pipe_mask = BIT(PIPE_C); 1871 break; 1872 } 1873 1874 goto out; 1875 } 1876 1877 mst_pipe_mask = 0; 1878 for_each_pipe(dev_priv, p) { 1879 enum transcoder cpu_transcoder = (enum transcoder)p; 1880 unsigned int port_mask, ddi_select; 1881 intel_wakeref_t trans_wakeref; 1882 1883 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 1884 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 1885 if (!trans_wakeref) 1886 continue; 1887 1888 if (INTEL_GEN(dev_priv) >= 12) { 1889 port_mask = TGL_TRANS_DDI_PORT_MASK; 1890 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 1891 } else { 1892 port_mask = TRANS_DDI_PORT_MASK; 1893 ddi_select = TRANS_DDI_SELECT_PORT(port); 1894 } 1895 1896 tmp = intel_de_read(dev_priv, 1897 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1898 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 1899 trans_wakeref); 1900 1901 if ((tmp & port_mask) != ddi_select) 1902 continue; 1903 1904 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1905 TRANS_DDI_MODE_SELECT_DP_MST) 1906 mst_pipe_mask |= BIT(p); 1907 1908 *pipe_mask |= BIT(p); 1909 } 1910 1911 if (!*pipe_mask) 1912 drm_dbg_kms(&dev_priv->drm, 1913 "No pipe for [ENCODER:%d:%s] found\n", 1914 encoder->base.base.id, encoder->base.name); 1915 1916 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 1917 drm_dbg_kms(&dev_priv->drm, 1918 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 1919 encoder->base.base.id, encoder->base.name, 1920 *pipe_mask); 1921 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 1922 } 1923 1924 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 1925 drm_dbg_kms(&dev_priv->drm, 1926 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 1927 encoder->base.base.id, encoder->base.name, 1928 *pipe_mask, mst_pipe_mask); 1929 else 1930 *is_dp_mst = mst_pipe_mask; 1931 1932 out: 1933 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 1934 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 1935 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 1936 BXT_PHY_LANE_POWERDOWN_ACK | 1937 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 1938 drm_err(&dev_priv->drm, 1939 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 1940 encoder->base.base.id, encoder->base.name, tmp); 1941 } 1942 1943 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1944 } 1945 1946 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1947 enum pipe *pipe) 1948 { 1949 u8 pipe_mask; 1950 bool is_mst; 1951 1952 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1953 1954 if (is_mst || !pipe_mask) 1955 return false; 1956 1957 *pipe = ffs(pipe_mask) - 1; 1958 1959 return true; 1960 } 1961 1962 static enum intel_display_power_domain 1963 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 1964 { 1965 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 1966 * DC states enabled at the same time, while for driver initiated AUX 1967 * transfers we need the same AUX IOs to be powered but with DC states 1968 * disabled. Accordingly use the AUX power domain here which leaves DC 1969 * states enabled. 1970 * However, for non-A AUX ports the corresponding non-EDP transcoders 1971 * would have already enabled power well 2 and DC_OFF. This means we can 1972 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 1973 * specific AUX_IO reference without powering up any extra wells. 1974 * Note that PSR is enabled only on Port A even though this function 1975 * returns the correct domain for other ports too. 1976 */ 1977 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 1978 intel_aux_power_domain(dig_port); 1979 } 1980 1981 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1982 struct intel_crtc_state *crtc_state) 1983 { 1984 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1985 struct intel_digital_port *dig_port; 1986 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1987 1988 /* 1989 * TODO: Add support for MST encoders. Atm, the following should never 1990 * happen since fake-MST encoders don't set their get_power_domains() 1991 * hook. 1992 */ 1993 if (drm_WARN_ON(&dev_priv->drm, 1994 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1995 return; 1996 1997 dig_port = enc_to_dig_port(encoder); 1998 1999 if (!intel_phy_is_tc(dev_priv, phy) || 2000 dig_port->tc_mode != TC_PORT_TBT_ALT) 2001 intel_display_power_get(dev_priv, 2002 dig_port->ddi_io_power_domain); 2003 2004 /* 2005 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2006 * ports. 2007 */ 2008 if (intel_crtc_has_dp_encoder(crtc_state) || 2009 intel_phy_is_tc(dev_priv, phy)) 2010 intel_display_power_get(dev_priv, 2011 intel_ddi_main_link_aux_domain(dig_port)); 2012 2013 /* 2014 * VDSC power is needed when DSC is enabled 2015 */ 2016 if (crtc_state->dsc.compression_enable) 2017 intel_display_power_get(dev_priv, 2018 intel_dsc_power_domain(crtc_state)); 2019 } 2020 2021 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 2022 const struct intel_crtc_state *crtc_state) 2023 { 2024 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2025 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2026 enum port port = encoder->port; 2027 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2028 2029 if (cpu_transcoder != TRANSCODER_EDP) { 2030 if (INTEL_GEN(dev_priv) >= 12) 2031 intel_de_write(dev_priv, 2032 TRANS_CLK_SEL(cpu_transcoder), 2033 TGL_TRANS_CLK_SEL_PORT(port)); 2034 else 2035 intel_de_write(dev_priv, 2036 TRANS_CLK_SEL(cpu_transcoder), 2037 TRANS_CLK_SEL_PORT(port)); 2038 } 2039 } 2040 2041 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2042 { 2043 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2045 2046 if (cpu_transcoder != TRANSCODER_EDP) { 2047 if (INTEL_GEN(dev_priv) >= 12) 2048 intel_de_write(dev_priv, 2049 TRANS_CLK_SEL(cpu_transcoder), 2050 TGL_TRANS_CLK_SEL_DISABLED); 2051 else 2052 intel_de_write(dev_priv, 2053 TRANS_CLK_SEL(cpu_transcoder), 2054 TRANS_CLK_SEL_DISABLED); 2055 } 2056 } 2057 2058 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2059 enum port port, u8 iboost) 2060 { 2061 u32 tmp; 2062 2063 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2064 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2065 if (iboost) 2066 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2067 else 2068 tmp |= BALANCE_LEG_DISABLE(port); 2069 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2070 } 2071 2072 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2073 int level, enum intel_output_type type) 2074 { 2075 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2077 enum port port = encoder->port; 2078 u8 iboost; 2079 2080 if (type == INTEL_OUTPUT_HDMI) 2081 iboost = intel_bios_hdmi_boost_level(encoder); 2082 else 2083 iboost = intel_bios_dp_boost_level(encoder); 2084 2085 if (iboost == 0) { 2086 const struct ddi_buf_trans *ddi_translations; 2087 int n_entries; 2088 2089 if (type == INTEL_OUTPUT_HDMI) 2090 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2091 else if (type == INTEL_OUTPUT_EDP) 2092 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2093 else 2094 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2095 2096 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2097 return; 2098 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2099 level = n_entries - 1; 2100 2101 iboost = ddi_translations[level].i_boost; 2102 } 2103 2104 /* Make sure that the requested I_boost is valid */ 2105 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2106 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2107 return; 2108 } 2109 2110 _skl_ddi_set_iboost(dev_priv, port, iboost); 2111 2112 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2113 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2114 } 2115 2116 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2117 int level, enum intel_output_type type) 2118 { 2119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2120 const struct bxt_ddi_buf_trans *ddi_translations; 2121 enum port port = encoder->port; 2122 int n_entries; 2123 2124 if (type == INTEL_OUTPUT_HDMI) 2125 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2126 else if (type == INTEL_OUTPUT_EDP) 2127 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2128 else 2129 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2130 2131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2132 return; 2133 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2134 level = n_entries - 1; 2135 2136 bxt_ddi_phy_set_signal_level(dev_priv, port, 2137 ddi_translations[level].margin, 2138 ddi_translations[level].scale, 2139 ddi_translations[level].enable, 2140 ddi_translations[level].deemphasis); 2141 } 2142 2143 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) 2144 { 2145 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2146 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2147 enum port port = encoder->port; 2148 enum phy phy = intel_port_to_phy(dev_priv, port); 2149 int n_entries; 2150 2151 if (INTEL_GEN(dev_priv) >= 12) { 2152 if (intel_phy_is_combo(dev_priv, phy)) 2153 tgl_get_combo_buf_trans(dev_priv, encoder->type, 2154 intel_dp->link_rate, &n_entries); 2155 else 2156 tgl_get_dkl_buf_trans(dev_priv, encoder->type, 2157 intel_dp->link_rate, &n_entries); 2158 } else if (INTEL_GEN(dev_priv) == 11) { 2159 if (IS_ELKHARTLAKE(dev_priv)) 2160 ehl_get_combo_buf_trans(dev_priv, encoder->type, 2161 intel_dp->link_rate, &n_entries); 2162 else if (intel_phy_is_combo(dev_priv, phy)) 2163 icl_get_combo_buf_trans(dev_priv, encoder->type, 2164 intel_dp->link_rate, &n_entries); 2165 else 2166 icl_get_mg_buf_trans(dev_priv, encoder->type, 2167 intel_dp->link_rate, &n_entries); 2168 } else if (IS_CANNONLAKE(dev_priv)) { 2169 if (encoder->type == INTEL_OUTPUT_EDP) 2170 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2171 else 2172 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2173 } else if (IS_GEN9_LP(dev_priv)) { 2174 if (encoder->type == INTEL_OUTPUT_EDP) 2175 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2176 else 2177 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2178 } else { 2179 if (encoder->type == INTEL_OUTPUT_EDP) 2180 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2181 else 2182 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2183 } 2184 2185 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2186 n_entries = 1; 2187 if (drm_WARN_ON(&dev_priv->drm, 2188 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2189 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2190 2191 return index_to_dp_signal_levels[n_entries - 1] & 2192 DP_TRAIN_VOLTAGE_SWING_MASK; 2193 } 2194 2195 /* 2196 * We assume that the full set of pre-emphasis values can be 2197 * used on all DDI platforms. Should that change we need to 2198 * rethink this code. 2199 */ 2200 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 2201 { 2202 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2203 } 2204 2205 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2206 int level, enum intel_output_type type) 2207 { 2208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2209 const struct cnl_ddi_buf_trans *ddi_translations; 2210 enum port port = encoder->port; 2211 int n_entries, ln; 2212 u32 val; 2213 2214 if (type == INTEL_OUTPUT_HDMI) 2215 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2216 else if (type == INTEL_OUTPUT_EDP) 2217 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2218 else 2219 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2220 2221 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2222 return; 2223 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2224 level = n_entries - 1; 2225 2226 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2227 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2228 val &= ~SCALING_MODE_SEL_MASK; 2229 val |= SCALING_MODE_SEL(2); 2230 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2231 2232 /* Program PORT_TX_DW2 */ 2233 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2234 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2235 RCOMP_SCALAR_MASK); 2236 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2237 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2238 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2239 val |= RCOMP_SCALAR(0x98); 2240 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2241 2242 /* Program PORT_TX_DW4 */ 2243 /* We cannot write to GRP. It would overrite individual loadgen */ 2244 for (ln = 0; ln < 4; ln++) { 2245 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2246 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2247 CURSOR_COEFF_MASK); 2248 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2249 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2250 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2251 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2252 } 2253 2254 /* Program PORT_TX_DW5 */ 2255 /* All DW5 values are fixed for every table entry */ 2256 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2257 val &= ~RTERM_SELECT_MASK; 2258 val |= RTERM_SELECT(6); 2259 val |= TAP3_DISABLE; 2260 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2261 2262 /* Program PORT_TX_DW7 */ 2263 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2264 val &= ~N_SCALAR_MASK; 2265 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2266 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2267 } 2268 2269 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2270 int level, enum intel_output_type type) 2271 { 2272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2273 enum port port = encoder->port; 2274 int width, rate, ln; 2275 u32 val; 2276 2277 if (type == INTEL_OUTPUT_HDMI) { 2278 width = 4; 2279 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2280 } else { 2281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2282 2283 width = intel_dp->lane_count; 2284 rate = intel_dp->link_rate; 2285 } 2286 2287 /* 2288 * 1. If port type is eDP or DP, 2289 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2290 * else clear to 0b. 2291 */ 2292 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2293 if (type != INTEL_OUTPUT_HDMI) 2294 val |= COMMON_KEEPER_EN; 2295 else 2296 val &= ~COMMON_KEEPER_EN; 2297 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2298 2299 /* 2. Program loadgen select */ 2300 /* 2301 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2302 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2303 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2304 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2305 */ 2306 for (ln = 0; ln <= 3; ln++) { 2307 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2308 val &= ~LOADGEN_SELECT; 2309 2310 if ((rate <= 600000 && width == 4 && ln >= 1) || 2311 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2312 val |= LOADGEN_SELECT; 2313 } 2314 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2315 } 2316 2317 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2318 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2319 val |= SUS_CLOCK_CONFIG; 2320 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2321 2322 /* 4. Clear training enable to change swing values */ 2323 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2324 val &= ~TX_TRAINING_EN; 2325 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2326 2327 /* 5. Program swing and de-emphasis */ 2328 cnl_ddi_vswing_program(encoder, level, type); 2329 2330 /* 6. Set training enable to trigger update */ 2331 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2332 val |= TX_TRAINING_EN; 2333 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2334 } 2335 2336 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2337 u32 level, enum phy phy, int type, 2338 int rate) 2339 { 2340 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2341 u32 n_entries, val; 2342 int ln; 2343 2344 if (INTEL_GEN(dev_priv) >= 12) 2345 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, 2346 &n_entries); 2347 else if (IS_ELKHARTLAKE(dev_priv)) 2348 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, 2349 &n_entries); 2350 else 2351 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2352 &n_entries); 2353 if (!ddi_translations) 2354 return; 2355 2356 if (level >= n_entries) { 2357 drm_dbg_kms(&dev_priv->drm, 2358 "DDI translation not found for level %d. Using %d instead.", 2359 level, n_entries - 1); 2360 level = n_entries - 1; 2361 } 2362 2363 /* Set PORT_TX_DW5 */ 2364 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2365 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2366 TAP2_DISABLE | TAP3_DISABLE); 2367 val |= SCALING_MODE_SEL(0x2); 2368 val |= RTERM_SELECT(0x6); 2369 val |= TAP3_DISABLE; 2370 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2371 2372 /* Program PORT_TX_DW2 */ 2373 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2374 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2375 RCOMP_SCALAR_MASK); 2376 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2377 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2378 /* Program Rcomp scalar for every table entry */ 2379 val |= RCOMP_SCALAR(0x98); 2380 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2381 2382 /* Program PORT_TX_DW4 */ 2383 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2384 for (ln = 0; ln <= 3; ln++) { 2385 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2386 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2387 CURSOR_COEFF_MASK); 2388 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2389 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2390 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2391 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2392 } 2393 2394 /* Program PORT_TX_DW7 */ 2395 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2396 val &= ~N_SCALAR_MASK; 2397 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2398 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2399 } 2400 2401 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2402 u32 level, 2403 enum intel_output_type type) 2404 { 2405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2406 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2407 int width = 0; 2408 int rate = 0; 2409 u32 val; 2410 int ln = 0; 2411 2412 if (type == INTEL_OUTPUT_HDMI) { 2413 width = 4; 2414 /* Rate is always < than 6GHz for HDMI */ 2415 } else { 2416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2417 2418 width = intel_dp->lane_count; 2419 rate = intel_dp->link_rate; 2420 } 2421 2422 /* 2423 * 1. If port type is eDP or DP, 2424 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2425 * else clear to 0b. 2426 */ 2427 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2428 if (type == INTEL_OUTPUT_HDMI) 2429 val &= ~COMMON_KEEPER_EN; 2430 else 2431 val |= COMMON_KEEPER_EN; 2432 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2433 2434 /* 2. Program loadgen select */ 2435 /* 2436 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2437 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2438 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2439 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2440 */ 2441 for (ln = 0; ln <= 3; ln++) { 2442 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2443 val &= ~LOADGEN_SELECT; 2444 2445 if ((rate <= 600000 && width == 4 && ln >= 1) || 2446 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2447 val |= LOADGEN_SELECT; 2448 } 2449 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2450 } 2451 2452 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2453 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2454 val |= SUS_CLOCK_CONFIG; 2455 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2456 2457 /* 4. Clear training enable to change swing values */ 2458 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2459 val &= ~TX_TRAINING_EN; 2460 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2461 2462 /* 5. Program swing and de-emphasis */ 2463 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2464 2465 /* 6. Set training enable to trigger update */ 2466 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2467 val |= TX_TRAINING_EN; 2468 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2469 } 2470 2471 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2472 int link_clock, u32 level, 2473 enum intel_output_type type) 2474 { 2475 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2476 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2477 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2478 u32 n_entries, val; 2479 int ln, rate = 0; 2480 2481 if (type != INTEL_OUTPUT_HDMI) { 2482 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2483 2484 rate = intel_dp->link_rate; 2485 } 2486 2487 ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate, 2488 &n_entries); 2489 /* The table does not have values for level 3 and level 9. */ 2490 if (level >= n_entries || level == 3 || level == 9) { 2491 drm_dbg_kms(&dev_priv->drm, 2492 "DDI translation not found for level %d. Using %d instead.", 2493 level, n_entries - 2); 2494 level = n_entries - 2; 2495 } 2496 2497 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2498 for (ln = 0; ln < 2; ln++) { 2499 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2500 val &= ~CRI_USE_FS32; 2501 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2502 2503 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2504 val &= ~CRI_USE_FS32; 2505 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2506 } 2507 2508 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2509 for (ln = 0; ln < 2; ln++) { 2510 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2511 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2512 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2513 ddi_translations[level].cri_txdeemph_override_17_12); 2514 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2515 2516 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2517 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2518 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2519 ddi_translations[level].cri_txdeemph_override_17_12); 2520 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2521 } 2522 2523 /* Program MG_TX_DRVCTRL with values from vswing table */ 2524 for (ln = 0; ln < 2; ln++) { 2525 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2526 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2527 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2528 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2529 ddi_translations[level].cri_txdeemph_override_5_0) | 2530 CRI_TXDEEMPH_OVERRIDE_11_6( 2531 ddi_translations[level].cri_txdeemph_override_11_6) | 2532 CRI_TXDEEMPH_OVERRIDE_EN; 2533 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2534 2535 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2536 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2537 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2538 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2539 ddi_translations[level].cri_txdeemph_override_5_0) | 2540 CRI_TXDEEMPH_OVERRIDE_11_6( 2541 ddi_translations[level].cri_txdeemph_override_11_6) | 2542 CRI_TXDEEMPH_OVERRIDE_EN; 2543 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2544 2545 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2546 } 2547 2548 /* 2549 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2550 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2551 * values from table for which TX1 and TX2 enabled. 2552 */ 2553 for (ln = 0; ln < 2; ln++) { 2554 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2555 if (link_clock < 300000) 2556 val |= CFG_LOW_RATE_LKREN_EN; 2557 else 2558 val &= ~CFG_LOW_RATE_LKREN_EN; 2559 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2560 } 2561 2562 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2563 for (ln = 0; ln < 2; ln++) { 2564 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2565 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2566 if (link_clock <= 500000) { 2567 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2568 } else { 2569 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2570 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2571 } 2572 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2573 2574 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2575 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2576 if (link_clock <= 500000) { 2577 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2578 } else { 2579 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2580 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2581 } 2582 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2583 } 2584 2585 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2586 for (ln = 0; ln < 2; ln++) { 2587 val = intel_de_read(dev_priv, 2588 MG_TX1_PISO_READLOAD(ln, tc_port)); 2589 val |= CRI_CALCINIT; 2590 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2591 val); 2592 2593 val = intel_de_read(dev_priv, 2594 MG_TX2_PISO_READLOAD(ln, tc_port)); 2595 val |= CRI_CALCINIT; 2596 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2597 val); 2598 } 2599 } 2600 2601 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2602 int link_clock, 2603 u32 level, 2604 enum intel_output_type type) 2605 { 2606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2607 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2608 2609 if (intel_phy_is_combo(dev_priv, phy)) 2610 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2611 else 2612 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level, 2613 type); 2614 } 2615 2616 static void 2617 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2618 u32 level, enum intel_output_type type) 2619 { 2620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2621 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2622 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2623 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2624 int rate = 0; 2625 2626 if (type == INTEL_OUTPUT_HDMI) { 2627 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2628 2629 rate = intel_dp->link_rate; 2630 } 2631 2632 ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate, 2633 &n_entries); 2634 2635 if (level >= n_entries) 2636 level = n_entries - 1; 2637 2638 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2639 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2640 DKL_TX_VSWING_CONTROL_MASK); 2641 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2642 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2643 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2644 2645 for (ln = 0; ln < 2; ln++) { 2646 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2647 HIP_INDEX_VAL(tc_port, ln)); 2648 2649 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2650 2651 /* All the registers are RMW */ 2652 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2653 val &= ~dpcnt_mask; 2654 val |= dpcnt_val; 2655 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2656 2657 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2658 val &= ~dpcnt_mask; 2659 val |= dpcnt_val; 2660 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2661 2662 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2663 val &= ~DKL_TX_DP20BITMODE; 2664 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2665 } 2666 } 2667 2668 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2669 int link_clock, 2670 u32 level, 2671 enum intel_output_type type) 2672 { 2673 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2674 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2675 2676 if (intel_phy_is_combo(dev_priv, phy)) 2677 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2678 else 2679 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); 2680 } 2681 2682 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) 2683 { 2684 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2685 int i; 2686 2687 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2688 if (index_to_dp_signal_levels[i] == signal_levels) 2689 return i; 2690 } 2691 2692 drm_WARN(&i915->drm, 1, 2693 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2694 signal_levels); 2695 2696 return 0; 2697 } 2698 2699 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2700 { 2701 u8 train_set = intel_dp->train_set[0]; 2702 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2703 DP_TRAIN_PRE_EMPHASIS_MASK); 2704 2705 return translate_signal_level(intel_dp, signal_levels); 2706 } 2707 2708 static void 2709 tgl_set_signal_levels(struct intel_dp *intel_dp) 2710 { 2711 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2712 int level = intel_ddi_dp_level(intel_dp); 2713 2714 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2715 level, encoder->type); 2716 } 2717 2718 static void 2719 icl_set_signal_levels(struct intel_dp *intel_dp) 2720 { 2721 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2722 int level = intel_ddi_dp_level(intel_dp); 2723 2724 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2725 level, encoder->type); 2726 } 2727 2728 static void 2729 cnl_set_signal_levels(struct intel_dp *intel_dp) 2730 { 2731 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2732 int level = intel_ddi_dp_level(intel_dp); 2733 2734 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2735 } 2736 2737 static void 2738 bxt_set_signal_levels(struct intel_dp *intel_dp) 2739 { 2740 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2741 int level = intel_ddi_dp_level(intel_dp); 2742 2743 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2744 } 2745 2746 static void 2747 hsw_set_signal_levels(struct intel_dp *intel_dp) 2748 { 2749 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2750 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2751 int level = intel_ddi_dp_level(intel_dp); 2752 enum port port = encoder->port; 2753 u32 signal_levels; 2754 2755 signal_levels = DDI_BUF_TRANS_SELECT(level); 2756 2757 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 2758 signal_levels); 2759 2760 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 2761 intel_dp->DP |= signal_levels; 2762 2763 if (IS_GEN9_BC(dev_priv)) 2764 skl_ddi_set_iboost(encoder, level, encoder->type); 2765 2766 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 2767 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 2768 } 2769 2770 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2771 enum phy phy) 2772 { 2773 if (intel_phy_is_combo(dev_priv, phy)) { 2774 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2775 } else if (intel_phy_is_tc(dev_priv, phy)) { 2776 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2777 (enum port)phy); 2778 2779 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2780 } 2781 2782 return 0; 2783 } 2784 2785 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2786 const struct intel_crtc_state *crtc_state) 2787 { 2788 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2789 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2790 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2791 u32 val; 2792 2793 mutex_lock(&dev_priv->dpll.lock); 2794 2795 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2796 drm_WARN_ON(&dev_priv->drm, 2797 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2798 2799 if (intel_phy_is_combo(dev_priv, phy)) { 2800 /* 2801 * Even though this register references DDIs, note that we 2802 * want to pass the PHY rather than the port (DDI). For 2803 * ICL, port=phy in all cases so it doesn't matter, but for 2804 * EHL the bspec notes the following: 2805 * 2806 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2807 * Clock Select chooses the PLL for both DDIA and DDID and 2808 * drives port A in all cases." 2809 */ 2810 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2811 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2812 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2813 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 2814 } 2815 2816 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2817 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2818 2819 mutex_unlock(&dev_priv->dpll.lock); 2820 } 2821 2822 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2823 { 2824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2825 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2826 u32 val; 2827 2828 mutex_lock(&dev_priv->dpll.lock); 2829 2830 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2831 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2832 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2833 2834 mutex_unlock(&dev_priv->dpll.lock); 2835 } 2836 2837 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 2838 u32 port_mask, bool ddi_clk_needed) 2839 { 2840 enum port port; 2841 u32 val; 2842 2843 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2844 for_each_port_masked(port, port_mask) { 2845 enum phy phy = intel_port_to_phy(dev_priv, port); 2846 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 2847 phy); 2848 2849 if (ddi_clk_needed == !ddi_clk_off) 2850 continue; 2851 2852 /* 2853 * Punt on the case now where clock is gated, but it would 2854 * be needed by the port. Something else is really broken then. 2855 */ 2856 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 2857 continue; 2858 2859 drm_notice(&dev_priv->drm, 2860 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2861 phy_name(phy)); 2862 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2863 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2864 } 2865 } 2866 2867 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2868 { 2869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2870 u32 port_mask; 2871 bool ddi_clk_needed; 2872 2873 /* 2874 * In case of DP MST, we sanitize the primary encoder only, not the 2875 * virtual ones. 2876 */ 2877 if (encoder->type == INTEL_OUTPUT_DP_MST) 2878 return; 2879 2880 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2881 u8 pipe_mask; 2882 bool is_mst; 2883 2884 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2885 /* 2886 * In the unlikely case that BIOS enables DP in MST mode, just 2887 * warn since our MST HW readout is incomplete. 2888 */ 2889 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 2890 return; 2891 } 2892 2893 port_mask = BIT(encoder->port); 2894 ddi_clk_needed = encoder->base.crtc; 2895 2896 if (encoder->type == INTEL_OUTPUT_DSI) { 2897 struct intel_encoder *other_encoder; 2898 2899 port_mask = intel_dsi_encoder_ports(encoder); 2900 /* 2901 * Sanity check that we haven't incorrectly registered another 2902 * encoder using any of the ports of this DSI encoder. 2903 */ 2904 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 2905 if (other_encoder == encoder) 2906 continue; 2907 2908 if (drm_WARN_ON(&dev_priv->drm, 2909 port_mask & BIT(other_encoder->port))) 2910 return; 2911 } 2912 /* 2913 * For DSI we keep the ddi clocks gated 2914 * except during enable/disable sequence. 2915 */ 2916 ddi_clk_needed = false; 2917 } 2918 2919 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 2920 } 2921 2922 static void intel_ddi_clk_select(struct intel_encoder *encoder, 2923 const struct intel_crtc_state *crtc_state) 2924 { 2925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2926 enum port port = encoder->port; 2927 enum phy phy = intel_port_to_phy(dev_priv, port); 2928 u32 val; 2929 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2930 2931 if (drm_WARN_ON(&dev_priv->drm, !pll)) 2932 return; 2933 2934 mutex_lock(&dev_priv->dpll.lock); 2935 2936 if (INTEL_GEN(dev_priv) >= 11) { 2937 if (!intel_phy_is_combo(dev_priv, phy)) 2938 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2939 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 2940 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 2941 /* 2942 * MG does not exist but the programming is required 2943 * to ungate DDIC and DDID 2944 */ 2945 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2946 DDI_CLK_SEL_MG); 2947 } else if (IS_CANNONLAKE(dev_priv)) { 2948 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 2949 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2950 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 2951 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 2952 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2953 2954 /* 2955 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 2956 * This step and the step before must be done with separate 2957 * register writes. 2958 */ 2959 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2960 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 2961 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2962 } else if (IS_GEN9_BC(dev_priv)) { 2963 /* DDI -> PLL mapping */ 2964 val = intel_de_read(dev_priv, DPLL_CTRL2); 2965 2966 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2967 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2968 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2969 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2970 2971 intel_de_write(dev_priv, DPLL_CTRL2, val); 2972 2973 } else if (INTEL_GEN(dev_priv) < 9) { 2974 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2975 hsw_pll_to_ddi_pll_sel(pll)); 2976 } 2977 2978 mutex_unlock(&dev_priv->dpll.lock); 2979 } 2980 2981 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 2982 { 2983 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2984 enum port port = encoder->port; 2985 enum phy phy = intel_port_to_phy(dev_priv, port); 2986 2987 if (INTEL_GEN(dev_priv) >= 11) { 2988 if (!intel_phy_is_combo(dev_priv, phy) || 2989 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 2990 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2991 DDI_CLK_SEL_NONE); 2992 } else if (IS_CANNONLAKE(dev_priv)) { 2993 intel_de_write(dev_priv, DPCLKA_CFGCR0, 2994 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2995 } else if (IS_GEN9_BC(dev_priv)) { 2996 intel_de_write(dev_priv, DPLL_CTRL2, 2997 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 2998 } else if (INTEL_GEN(dev_priv) < 9) { 2999 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3000 PORT_CLK_SEL_NONE); 3001 } 3002 } 3003 3004 static void 3005 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 3006 const struct intel_crtc_state *crtc_state) 3007 { 3008 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3009 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 3010 u32 ln0, ln1, pin_assignment; 3011 u8 width; 3012 3013 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3014 return; 3015 3016 if (INTEL_GEN(dev_priv) >= 12) { 3017 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3018 HIP_INDEX_VAL(tc_port, 0x0)); 3019 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3020 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3021 HIP_INDEX_VAL(tc_port, 0x1)); 3022 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3023 } else { 3024 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3025 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3026 } 3027 3028 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3029 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3030 3031 /* DPPATC */ 3032 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 3033 width = crtc_state->lane_count; 3034 3035 switch (pin_assignment) { 3036 case 0x0: 3037 drm_WARN_ON(&dev_priv->drm, 3038 intel_dig_port->tc_mode != TC_PORT_LEGACY); 3039 if (width == 1) { 3040 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3041 } else { 3042 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3043 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3044 } 3045 break; 3046 case 0x1: 3047 if (width == 4) { 3048 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3049 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3050 } 3051 break; 3052 case 0x2: 3053 if (width == 2) { 3054 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3055 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3056 } 3057 break; 3058 case 0x3: 3059 case 0x5: 3060 if (width == 1) { 3061 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3062 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3063 } else { 3064 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3065 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3066 } 3067 break; 3068 case 0x4: 3069 case 0x6: 3070 if (width == 1) { 3071 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3072 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3073 } else { 3074 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3075 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3076 } 3077 break; 3078 default: 3079 MISSING_CASE(pin_assignment); 3080 } 3081 3082 if (INTEL_GEN(dev_priv) >= 12) { 3083 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3084 HIP_INDEX_VAL(tc_port, 0x0)); 3085 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3086 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3087 HIP_INDEX_VAL(tc_port, 0x1)); 3088 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3089 } else { 3090 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3091 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3092 } 3093 } 3094 3095 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3096 const struct intel_crtc_state *crtc_state) 3097 { 3098 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3099 3100 if (!crtc_state->fec_enable) 3101 return; 3102 3103 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3104 drm_dbg_kms(&i915->drm, 3105 "Failed to set FEC_READY in the sink\n"); 3106 } 3107 3108 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3109 const struct intel_crtc_state *crtc_state) 3110 { 3111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3112 struct intel_dp *intel_dp; 3113 u32 val; 3114 3115 if (!crtc_state->fec_enable) 3116 return; 3117 3118 intel_dp = enc_to_intel_dp(encoder); 3119 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3120 val |= DP_TP_CTL_FEC_ENABLE; 3121 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3122 3123 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3124 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3125 drm_err(&dev_priv->drm, 3126 "Timed out waiting for FEC Enable Status\n"); 3127 } 3128 3129 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3130 const struct intel_crtc_state *crtc_state) 3131 { 3132 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3133 struct intel_dp *intel_dp; 3134 u32 val; 3135 3136 if (!crtc_state->fec_enable) 3137 return; 3138 3139 intel_dp = enc_to_intel_dp(encoder); 3140 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3141 val &= ~DP_TP_CTL_FEC_ENABLE; 3142 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3143 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3144 } 3145 3146 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3147 struct intel_encoder *encoder, 3148 const struct intel_crtc_state *crtc_state, 3149 const struct drm_connector_state *conn_state) 3150 { 3151 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3153 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3154 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3155 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3156 int level = intel_ddi_dp_level(intel_dp); 3157 enum transcoder transcoder = crtc_state->cpu_transcoder; 3158 3159 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3160 crtc_state->lane_count, is_mst); 3161 3162 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3163 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3164 3165 /* 3166 * 1. Enable Power Wells 3167 * 3168 * This was handled at the beginning of intel_atomic_commit_tail(), 3169 * before we called down into this function. 3170 */ 3171 3172 /* 2. Enable Panel Power if PPS is required */ 3173 intel_edp_panel_on(intel_dp); 3174 3175 /* 3176 * 3. For non-TBT Type-C ports, set FIA lane count 3177 * (DFLEXDPSP.DPX4TXLATC) 3178 * 3179 * This was done before tgl_ddi_pre_enable_dp by 3180 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3181 */ 3182 3183 /* 3184 * 4. Enable the port PLL. 3185 * 3186 * The PLL enabling itself was already done before this function by 3187 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3188 * configure the PLL to port mapping here. 3189 */ 3190 intel_ddi_clk_select(encoder, crtc_state); 3191 3192 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3193 if (!intel_phy_is_tc(dev_priv, phy) || 3194 dig_port->tc_mode != TC_PORT_TBT_ALT) 3195 intel_display_power_get(dev_priv, 3196 dig_port->ddi_io_power_domain); 3197 3198 /* 6. Program DP_MODE */ 3199 icl_program_mg_dp_mode(dig_port, crtc_state); 3200 3201 /* 3202 * 7. The rest of the below are substeps under the bspec's "Enable and 3203 * Train Display Port" step. Note that steps that are specific to 3204 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3205 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3206 * us when active_mst_links==0, so any steps designated for "single 3207 * stream or multi-stream master transcoder" can just be performed 3208 * unconditionally here. 3209 */ 3210 3211 /* 3212 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3213 * Transcoder. 3214 */ 3215 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3216 3217 /* 3218 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3219 * Transport Select 3220 */ 3221 intel_ddi_config_transcoder_func(encoder, crtc_state); 3222 3223 /* 3224 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3225 * selected 3226 * 3227 * This will be handled by the intel_dp_start_link_train() farther 3228 * down this function. 3229 */ 3230 3231 /* 7.e Configure voltage swing and related IO settings */ 3232 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3233 encoder->type); 3234 3235 /* 3236 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3237 * the used lanes of the DDI. 3238 */ 3239 if (intel_phy_is_combo(dev_priv, phy)) { 3240 bool lane_reversal = 3241 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3242 3243 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3244 crtc_state->lane_count, 3245 lane_reversal); 3246 } 3247 3248 /* 3249 * 7.g Configure and enable DDI_BUF_CTL 3250 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3251 * after 500 us. 3252 * 3253 * We only configure what the register value will be here. Actual 3254 * enabling happens during link training farther down. 3255 */ 3256 intel_ddi_init_dp_buf_reg(encoder); 3257 3258 if (!is_mst) 3259 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3260 3261 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3262 /* 3263 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3264 * in the FEC_CONFIGURATION register to 1 before initiating link 3265 * training 3266 */ 3267 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3268 3269 /* 3270 * 7.i Follow DisplayPort specification training sequence (see notes for 3271 * failure handling) 3272 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3273 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3274 * (timeout after 800 us) 3275 */ 3276 intel_dp_start_link_train(intel_dp); 3277 3278 /* 7.k Set DP_TP_CTL link training to Normal */ 3279 if (!is_trans_port_sync_mode(crtc_state)) 3280 intel_dp_stop_link_train(intel_dp); 3281 3282 /* 7.l Configure and enable FEC if needed */ 3283 intel_ddi_enable_fec(encoder, crtc_state); 3284 intel_dsc_enable(encoder, crtc_state); 3285 } 3286 3287 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3288 struct intel_encoder *encoder, 3289 const struct intel_crtc_state *crtc_state, 3290 const struct drm_connector_state *conn_state) 3291 { 3292 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3293 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3294 enum port port = encoder->port; 3295 enum phy phy = intel_port_to_phy(dev_priv, port); 3296 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3297 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3298 int level = intel_ddi_dp_level(intel_dp); 3299 3300 if (INTEL_GEN(dev_priv) < 11) 3301 drm_WARN_ON(&dev_priv->drm, 3302 is_mst && (port == PORT_A || port == PORT_E)); 3303 else 3304 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3305 3306 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3307 crtc_state->lane_count, is_mst); 3308 3309 intel_edp_panel_on(intel_dp); 3310 3311 intel_ddi_clk_select(encoder, crtc_state); 3312 3313 if (!intel_phy_is_tc(dev_priv, phy) || 3314 dig_port->tc_mode != TC_PORT_TBT_ALT) 3315 intel_display_power_get(dev_priv, 3316 dig_port->ddi_io_power_domain); 3317 3318 icl_program_mg_dp_mode(dig_port, crtc_state); 3319 3320 if (INTEL_GEN(dev_priv) >= 11) 3321 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3322 level, encoder->type); 3323 else if (IS_CANNONLAKE(dev_priv)) 3324 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3325 else if (IS_GEN9_LP(dev_priv)) 3326 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3327 else 3328 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3329 3330 if (intel_phy_is_combo(dev_priv, phy)) { 3331 bool lane_reversal = 3332 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3333 3334 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3335 crtc_state->lane_count, 3336 lane_reversal); 3337 } 3338 3339 intel_ddi_init_dp_buf_reg(encoder); 3340 if (!is_mst) 3341 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3342 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3343 true); 3344 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3345 intel_dp_start_link_train(intel_dp); 3346 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3347 !is_trans_port_sync_mode(crtc_state)) 3348 intel_dp_stop_link_train(intel_dp); 3349 3350 intel_ddi_enable_fec(encoder, crtc_state); 3351 3352 if (!is_mst) 3353 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3354 3355 intel_dsc_enable(encoder, crtc_state); 3356 } 3357 3358 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3359 struct intel_encoder *encoder, 3360 const struct intel_crtc_state *crtc_state, 3361 const struct drm_connector_state *conn_state) 3362 { 3363 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3364 3365 if (INTEL_GEN(dev_priv) >= 12) 3366 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3367 else 3368 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3369 3370 /* MST will call a setting of MSA after an allocating of Virtual Channel 3371 * from MST encoder pre_enable callback. 3372 */ 3373 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3374 intel_ddi_set_dp_msa(crtc_state, conn_state); 3375 3376 intel_dp_set_m_n(crtc_state, M1_N1); 3377 } 3378 } 3379 3380 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3381 struct intel_encoder *encoder, 3382 const struct intel_crtc_state *crtc_state, 3383 const struct drm_connector_state *conn_state) 3384 { 3385 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3386 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3388 int level = intel_ddi_hdmi_level(encoder); 3389 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3390 3391 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3392 intel_ddi_clk_select(encoder, crtc_state); 3393 3394 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3395 3396 icl_program_mg_dp_mode(dig_port, crtc_state); 3397 3398 if (INTEL_GEN(dev_priv) >= 12) 3399 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3400 level, INTEL_OUTPUT_HDMI); 3401 else if (INTEL_GEN(dev_priv) == 11) 3402 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3403 level, INTEL_OUTPUT_HDMI); 3404 else if (IS_CANNONLAKE(dev_priv)) 3405 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3406 else if (IS_GEN9_LP(dev_priv)) 3407 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3408 else 3409 intel_prepare_hdmi_ddi_buffers(encoder, level); 3410 3411 if (IS_GEN9_BC(dev_priv)) 3412 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3413 3414 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3415 3416 intel_dig_port->set_infoframes(encoder, 3417 crtc_state->has_infoframe, 3418 crtc_state, conn_state); 3419 } 3420 3421 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3422 struct intel_encoder *encoder, 3423 const struct intel_crtc_state *crtc_state, 3424 const struct drm_connector_state *conn_state) 3425 { 3426 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3427 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3428 enum pipe pipe = crtc->pipe; 3429 3430 /* 3431 * When called from DP MST code: 3432 * - conn_state will be NULL 3433 * - encoder will be the main encoder (ie. mst->primary) 3434 * - the main connector associated with this port 3435 * won't be active or linked to a crtc 3436 * - crtc_state will be the state of the first stream to 3437 * be activated on this port, and it may not be the same 3438 * stream that will be deactivated last, but each stream 3439 * should have a state that is identical when it comes to 3440 * the DP link parameteres 3441 */ 3442 3443 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3444 3445 if (INTEL_GEN(dev_priv) >= 11) 3446 icl_map_plls_to_ports(encoder, crtc_state); 3447 3448 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3449 3450 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3451 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3452 conn_state); 3453 } else { 3454 struct intel_lspcon *lspcon = 3455 enc_to_intel_lspcon(encoder); 3456 3457 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3458 conn_state); 3459 if (lspcon->active) { 3460 struct intel_digital_port *dig_port = 3461 enc_to_dig_port(encoder); 3462 3463 dig_port->set_infoframes(encoder, 3464 crtc_state->has_infoframe, 3465 crtc_state, conn_state); 3466 } 3467 } 3468 } 3469 3470 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3471 const struct intel_crtc_state *crtc_state) 3472 { 3473 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3474 enum port port = encoder->port; 3475 bool wait = false; 3476 u32 val; 3477 3478 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3479 if (val & DDI_BUF_CTL_ENABLE) { 3480 val &= ~DDI_BUF_CTL_ENABLE; 3481 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3482 wait = true; 3483 } 3484 3485 if (intel_crtc_has_dp_encoder(crtc_state)) { 3486 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3487 3488 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3489 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3490 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3491 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3492 } 3493 3494 /* Disable FEC in DP Sink */ 3495 intel_ddi_disable_fec_state(encoder, crtc_state); 3496 3497 if (wait) 3498 intel_wait_ddi_buf_idle(dev_priv, port); 3499 } 3500 3501 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3502 struct intel_encoder *encoder, 3503 const struct intel_crtc_state *old_crtc_state, 3504 const struct drm_connector_state *old_conn_state) 3505 { 3506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3507 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3508 struct intel_dp *intel_dp = &dig_port->dp; 3509 bool is_mst = intel_crtc_has_type(old_crtc_state, 3510 INTEL_OUTPUT_DP_MST); 3511 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3512 3513 if (!is_mst) 3514 intel_dp_set_infoframes(encoder, false, 3515 old_crtc_state, old_conn_state); 3516 3517 /* 3518 * Power down sink before disabling the port, otherwise we end 3519 * up getting interrupts from the sink on detecting link loss. 3520 */ 3521 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3522 3523 if (INTEL_GEN(dev_priv) >= 12) { 3524 if (is_mst) { 3525 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3526 u32 val; 3527 3528 val = intel_de_read(dev_priv, 3529 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3530 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3531 TRANS_DDI_MODE_SELECT_MASK); 3532 intel_de_write(dev_priv, 3533 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3534 val); 3535 } 3536 } else { 3537 if (!is_mst) 3538 intel_ddi_disable_pipe_clock(old_crtc_state); 3539 } 3540 3541 intel_disable_ddi_buf(encoder, old_crtc_state); 3542 3543 /* 3544 * From TGL spec: "If single stream or multi-stream master transcoder: 3545 * Configure Transcoder Clock select to direct no clock to the 3546 * transcoder" 3547 */ 3548 if (INTEL_GEN(dev_priv) >= 12) 3549 intel_ddi_disable_pipe_clock(old_crtc_state); 3550 3551 intel_edp_panel_vdd_on(intel_dp); 3552 intel_edp_panel_off(intel_dp); 3553 3554 if (!intel_phy_is_tc(dev_priv, phy) || 3555 dig_port->tc_mode != TC_PORT_TBT_ALT) 3556 intel_display_power_put_unchecked(dev_priv, 3557 dig_port->ddi_io_power_domain); 3558 3559 intel_ddi_clk_disable(encoder); 3560 } 3561 3562 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3563 struct intel_encoder *encoder, 3564 const struct intel_crtc_state *old_crtc_state, 3565 const struct drm_connector_state *old_conn_state) 3566 { 3567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3568 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3569 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3570 3571 dig_port->set_infoframes(encoder, false, 3572 old_crtc_state, old_conn_state); 3573 3574 intel_ddi_disable_pipe_clock(old_crtc_state); 3575 3576 intel_disable_ddi_buf(encoder, old_crtc_state); 3577 3578 intel_display_power_put_unchecked(dev_priv, 3579 dig_port->ddi_io_power_domain); 3580 3581 intel_ddi_clk_disable(encoder); 3582 3583 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3584 } 3585 3586 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3587 struct intel_encoder *encoder, 3588 const struct intel_crtc_state *old_crtc_state, 3589 const struct drm_connector_state *old_conn_state) 3590 { 3591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3592 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3593 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3594 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3595 3596 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3597 intel_crtc_vblank_off(old_crtc_state); 3598 3599 intel_disable_pipe(old_crtc_state); 3600 3601 intel_ddi_disable_transcoder_func(old_crtc_state); 3602 3603 intel_dsc_disable(old_crtc_state); 3604 3605 if (INTEL_GEN(dev_priv) >= 9) 3606 skl_scaler_disable(old_crtc_state); 3607 else 3608 ilk_pfit_disable(old_crtc_state); 3609 } 3610 3611 /* 3612 * When called from DP MST code: 3613 * - old_conn_state will be NULL 3614 * - encoder will be the main encoder (ie. mst->primary) 3615 * - the main connector associated with this port 3616 * won't be active or linked to a crtc 3617 * - old_crtc_state will be the state of the last stream to 3618 * be deactivated on this port, and it may not be the same 3619 * stream that was activated last, but each stream 3620 * should have a state that is identical when it comes to 3621 * the DP link parameteres 3622 */ 3623 3624 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3625 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3626 old_conn_state); 3627 else 3628 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3629 old_conn_state); 3630 3631 if (INTEL_GEN(dev_priv) >= 11) 3632 icl_unmap_plls_to_ports(encoder); 3633 3634 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3635 intel_display_power_put_unchecked(dev_priv, 3636 intel_ddi_main_link_aux_domain(dig_port)); 3637 3638 if (is_tc_port) 3639 intel_tc_port_put_link(dig_port); 3640 } 3641 3642 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3643 struct intel_encoder *encoder, 3644 const struct intel_crtc_state *old_crtc_state, 3645 const struct drm_connector_state *old_conn_state) 3646 { 3647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3648 u32 val; 3649 3650 /* 3651 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3652 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3653 * step 13 is the correct place for it. Step 18 is where it was 3654 * originally before the BUN. 3655 */ 3656 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3657 val &= ~FDI_RX_ENABLE; 3658 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3659 3660 intel_disable_ddi_buf(encoder, old_crtc_state); 3661 intel_ddi_clk_disable(encoder); 3662 3663 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3664 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3665 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3666 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3667 3668 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3669 val &= ~FDI_PCDCLK; 3670 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3671 3672 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3673 val &= ~FDI_RX_PLL_ENABLE; 3674 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3675 } 3676 3677 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3678 struct intel_encoder *encoder, 3679 const struct intel_crtc_state *crtc_state) 3680 { 3681 const struct drm_connector_state *conn_state; 3682 struct drm_connector *conn; 3683 int i; 3684 3685 if (!crtc_state->sync_mode_slaves_mask) 3686 return; 3687 3688 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3689 struct intel_encoder *slave_encoder = 3690 to_intel_encoder(conn_state->best_encoder); 3691 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3692 const struct intel_crtc_state *slave_crtc_state; 3693 3694 if (!slave_crtc) 3695 continue; 3696 3697 slave_crtc_state = 3698 intel_atomic_get_new_crtc_state(state, slave_crtc); 3699 3700 if (slave_crtc_state->master_transcoder != 3701 crtc_state->cpu_transcoder) 3702 continue; 3703 3704 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder)); 3705 } 3706 3707 usleep_range(200, 400); 3708 3709 intel_dp_stop_link_train(enc_to_intel_dp(encoder)); 3710 } 3711 3712 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3713 struct intel_encoder *encoder, 3714 const struct intel_crtc_state *crtc_state, 3715 const struct drm_connector_state *conn_state) 3716 { 3717 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3718 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3719 enum port port = encoder->port; 3720 3721 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3722 intel_dp_stop_link_train(intel_dp); 3723 3724 intel_edp_backlight_on(crtc_state, conn_state); 3725 intel_psr_enable(intel_dp, crtc_state, conn_state); 3726 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3727 intel_edp_drrs_enable(intel_dp, crtc_state); 3728 3729 if (crtc_state->has_audio) 3730 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3731 3732 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3733 } 3734 3735 static i915_reg_t 3736 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3737 enum port port) 3738 { 3739 static const enum transcoder trans[] = { 3740 [PORT_A] = TRANSCODER_EDP, 3741 [PORT_B] = TRANSCODER_A, 3742 [PORT_C] = TRANSCODER_B, 3743 [PORT_D] = TRANSCODER_C, 3744 [PORT_E] = TRANSCODER_A, 3745 }; 3746 3747 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3748 3749 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3750 port = PORT_A; 3751 3752 return CHICKEN_TRANS(trans[port]); 3753 } 3754 3755 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3756 struct intel_encoder *encoder, 3757 const struct intel_crtc_state *crtc_state, 3758 const struct drm_connector_state *conn_state) 3759 { 3760 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3761 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3762 struct drm_connector *connector = conn_state->connector; 3763 enum port port = encoder->port; 3764 3765 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3766 crtc_state->hdmi_high_tmds_clock_ratio, 3767 crtc_state->hdmi_scrambling)) 3768 drm_dbg_kms(&dev_priv->drm, 3769 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3770 connector->base.id, connector->name); 3771 3772 /* Display WA #1143: skl,kbl,cfl */ 3773 if (IS_GEN9_BC(dev_priv)) { 3774 /* 3775 * For some reason these chicken bits have been 3776 * stuffed into a transcoder register, event though 3777 * the bits affect a specific DDI port rather than 3778 * a specific transcoder. 3779 */ 3780 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3781 u32 val; 3782 3783 val = intel_de_read(dev_priv, reg); 3784 3785 if (port == PORT_E) 3786 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3787 DDIE_TRAINING_OVERRIDE_VALUE; 3788 else 3789 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3790 DDI_TRAINING_OVERRIDE_VALUE; 3791 3792 intel_de_write(dev_priv, reg, val); 3793 intel_de_posting_read(dev_priv, reg); 3794 3795 udelay(1); 3796 3797 if (port == PORT_E) 3798 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3799 DDIE_TRAINING_OVERRIDE_VALUE); 3800 else 3801 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3802 DDI_TRAINING_OVERRIDE_VALUE); 3803 3804 intel_de_write(dev_priv, reg, val); 3805 } 3806 3807 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3808 * are ignored so nothing special needs to be done besides 3809 * enabling the port. 3810 */ 3811 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3812 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3813 3814 if (crtc_state->has_audio) 3815 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3816 } 3817 3818 static void intel_enable_ddi(struct intel_atomic_state *state, 3819 struct intel_encoder *encoder, 3820 const struct intel_crtc_state *crtc_state, 3821 const struct drm_connector_state *conn_state) 3822 { 3823 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3824 3825 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3826 3827 intel_enable_pipe(crtc_state); 3828 3829 intel_crtc_vblank_on(crtc_state); 3830 3831 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3832 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3833 else 3834 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3835 3836 /* Enable hdcp if it's desired */ 3837 if (conn_state->content_protection == 3838 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3839 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3840 crtc_state->cpu_transcoder, 3841 (u8)conn_state->hdcp_content_type); 3842 } 3843 3844 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3845 struct intel_encoder *encoder, 3846 const struct intel_crtc_state *old_crtc_state, 3847 const struct drm_connector_state *old_conn_state) 3848 { 3849 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3850 3851 intel_dp->link_trained = false; 3852 3853 if (old_crtc_state->has_audio) 3854 intel_audio_codec_disable(encoder, 3855 old_crtc_state, old_conn_state); 3856 3857 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3858 intel_psr_disable(intel_dp, old_crtc_state); 3859 intel_edp_backlight_off(old_conn_state); 3860 /* Disable the decompression in DP Sink */ 3861 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3862 false); 3863 } 3864 3865 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3866 struct intel_encoder *encoder, 3867 const struct intel_crtc_state *old_crtc_state, 3868 const struct drm_connector_state *old_conn_state) 3869 { 3870 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3871 struct drm_connector *connector = old_conn_state->connector; 3872 3873 if (old_crtc_state->has_audio) 3874 intel_audio_codec_disable(encoder, 3875 old_crtc_state, old_conn_state); 3876 3877 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3878 false, false)) 3879 drm_dbg_kms(&i915->drm, 3880 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3881 connector->base.id, connector->name); 3882 } 3883 3884 static void intel_disable_ddi(struct intel_atomic_state *state, 3885 struct intel_encoder *encoder, 3886 const struct intel_crtc_state *old_crtc_state, 3887 const struct drm_connector_state *old_conn_state) 3888 { 3889 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3890 3891 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3892 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3893 old_conn_state); 3894 else 3895 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3896 old_conn_state); 3897 } 3898 3899 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3900 struct intel_encoder *encoder, 3901 const struct intel_crtc_state *crtc_state, 3902 const struct drm_connector_state *conn_state) 3903 { 3904 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3905 3906 intel_ddi_set_dp_msa(crtc_state, conn_state); 3907 3908 intel_psr_update(intel_dp, crtc_state, conn_state); 3909 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3910 intel_edp_drrs_enable(intel_dp, crtc_state); 3911 3912 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3913 } 3914 3915 static void intel_ddi_update_pipe(struct intel_atomic_state *state, 3916 struct intel_encoder *encoder, 3917 const struct intel_crtc_state *crtc_state, 3918 const struct drm_connector_state *conn_state) 3919 { 3920 3921 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3922 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3923 conn_state); 3924 3925 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3926 } 3927 3928 static void 3929 intel_ddi_update_prepare(struct intel_atomic_state *state, 3930 struct intel_encoder *encoder, 3931 struct intel_crtc *crtc) 3932 { 3933 struct intel_crtc_state *crtc_state = 3934 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3935 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3936 3937 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3938 3939 intel_tc_port_get_link(enc_to_dig_port(encoder), 3940 required_lanes); 3941 if (crtc_state && crtc_state->hw.active) 3942 intel_update_active_dpll(state, crtc, encoder); 3943 } 3944 3945 static void 3946 intel_ddi_update_complete(struct intel_atomic_state *state, 3947 struct intel_encoder *encoder, 3948 struct intel_crtc *crtc) 3949 { 3950 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3951 } 3952 3953 static void 3954 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3955 struct intel_encoder *encoder, 3956 const struct intel_crtc_state *crtc_state, 3957 const struct drm_connector_state *conn_state) 3958 { 3959 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3960 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3961 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3962 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3963 3964 if (is_tc_port) 3965 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3966 3967 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3968 intel_display_power_get(dev_priv, 3969 intel_ddi_main_link_aux_domain(dig_port)); 3970 3971 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3972 /* 3973 * Program the lane count for static/dynamic connections on 3974 * Type-C ports. Skip this step for TBT. 3975 */ 3976 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3977 else if (IS_GEN9_LP(dev_priv)) 3978 bxt_ddi_phy_set_lane_optim_mask(encoder, 3979 crtc_state->lane_lat_optim_mask); 3980 } 3981 3982 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3983 { 3984 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3985 struct drm_i915_private *dev_priv = 3986 to_i915(intel_dig_port->base.base.dev); 3987 enum port port = intel_dig_port->base.port; 3988 u32 dp_tp_ctl, ddi_buf_ctl; 3989 bool wait = false; 3990 3991 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3992 3993 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3994 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3995 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3996 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3997 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3998 wait = true; 3999 } 4000 4001 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4002 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4003 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4004 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4005 4006 if (wait) 4007 intel_wait_ddi_buf_idle(dev_priv, port); 4008 } 4009 4010 dp_tp_ctl = DP_TP_CTL_ENABLE | 4011 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4012 if (intel_dp->link_mst) 4013 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4014 else { 4015 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4016 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4017 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4018 } 4019 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4020 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4021 4022 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4023 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4024 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4025 4026 udelay(600); 4027 } 4028 4029 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 4030 u8 dp_train_pat) 4031 { 4032 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4033 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); 4034 enum port port = dp_to_dig_port(intel_dp)->base.port; 4035 u32 temp; 4036 4037 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4038 4039 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 4040 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 4041 else 4042 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 4043 4044 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4045 switch (dp_train_pat & train_pat_mask) { 4046 case DP_TRAINING_PATTERN_DISABLE: 4047 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4048 break; 4049 case DP_TRAINING_PATTERN_1: 4050 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4051 break; 4052 case DP_TRAINING_PATTERN_2: 4053 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4054 break; 4055 case DP_TRAINING_PATTERN_3: 4056 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4057 break; 4058 case DP_TRAINING_PATTERN_4: 4059 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4060 break; 4061 } 4062 4063 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); 4064 4065 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4066 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4067 } 4068 4069 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp) 4070 { 4071 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4073 enum port port = encoder->port; 4074 u32 val; 4075 4076 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4077 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4078 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4079 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 4080 4081 /* 4082 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4083 * reason we need to set idle transmission mode is to work around a HW 4084 * issue where we enable the pipe while not in idle link-training mode. 4085 * In this case there is requirement to wait for a minimum number of 4086 * idle patterns to be sent. 4087 */ 4088 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4089 return; 4090 4091 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 4092 DP_TP_STATUS_IDLE_DONE, 1)) 4093 drm_err(&dev_priv->drm, 4094 "Timed out waiting for DP idle patterns\n"); 4095 } 4096 4097 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4098 enum transcoder cpu_transcoder) 4099 { 4100 if (cpu_transcoder == TRANSCODER_EDP) 4101 return false; 4102 4103 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4104 return false; 4105 4106 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4107 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4108 } 4109 4110 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4111 struct intel_crtc_state *crtc_state) 4112 { 4113 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4114 crtc_state->min_voltage_level = 2; 4115 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 4116 crtc_state->min_voltage_level = 3; 4117 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4118 crtc_state->min_voltage_level = 1; 4119 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4120 crtc_state->min_voltage_level = 2; 4121 } 4122 4123 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4124 enum transcoder cpu_transcoder) 4125 { 4126 u32 master_select; 4127 4128 if (INTEL_GEN(dev_priv) >= 11) { 4129 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4130 4131 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4132 return INVALID_TRANSCODER; 4133 4134 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4135 } else { 4136 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4137 4138 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4139 return INVALID_TRANSCODER; 4140 4141 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4142 } 4143 4144 if (master_select == 0) 4145 return TRANSCODER_EDP; 4146 else 4147 return master_select - 1; 4148 } 4149 4150 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4151 { 4152 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4153 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4154 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4155 enum transcoder cpu_transcoder; 4156 4157 crtc_state->master_transcoder = 4158 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4159 4160 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4161 enum intel_display_power_domain power_domain; 4162 intel_wakeref_t trans_wakeref; 4163 4164 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4165 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4166 power_domain); 4167 4168 if (!trans_wakeref) 4169 continue; 4170 4171 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4172 crtc_state->cpu_transcoder) 4173 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4174 4175 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4176 } 4177 4178 drm_WARN_ON(&dev_priv->drm, 4179 crtc_state->master_transcoder != INVALID_TRANSCODER && 4180 crtc_state->sync_mode_slaves_mask); 4181 } 4182 4183 void intel_ddi_get_config(struct intel_encoder *encoder, 4184 struct intel_crtc_state *pipe_config) 4185 { 4186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4187 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4188 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4189 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4190 u32 temp, flags = 0; 4191 4192 /* XXX: DSI transcoder paranoia */ 4193 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4194 return; 4195 4196 if (INTEL_GEN(dev_priv) >= 12) { 4197 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); 4198 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); 4199 } 4200 4201 intel_dsc_get_config(encoder, pipe_config); 4202 4203 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4204 if (temp & TRANS_DDI_PHSYNC) 4205 flags |= DRM_MODE_FLAG_PHSYNC; 4206 else 4207 flags |= DRM_MODE_FLAG_NHSYNC; 4208 if (temp & TRANS_DDI_PVSYNC) 4209 flags |= DRM_MODE_FLAG_PVSYNC; 4210 else 4211 flags |= DRM_MODE_FLAG_NVSYNC; 4212 4213 pipe_config->hw.adjusted_mode.flags |= flags; 4214 4215 switch (temp & TRANS_DDI_BPC_MASK) { 4216 case TRANS_DDI_BPC_6: 4217 pipe_config->pipe_bpp = 18; 4218 break; 4219 case TRANS_DDI_BPC_8: 4220 pipe_config->pipe_bpp = 24; 4221 break; 4222 case TRANS_DDI_BPC_10: 4223 pipe_config->pipe_bpp = 30; 4224 break; 4225 case TRANS_DDI_BPC_12: 4226 pipe_config->pipe_bpp = 36; 4227 break; 4228 default: 4229 break; 4230 } 4231 4232 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4233 case TRANS_DDI_MODE_SELECT_HDMI: 4234 pipe_config->has_hdmi_sink = true; 4235 4236 pipe_config->infoframes.enable |= 4237 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4238 4239 if (pipe_config->infoframes.enable) 4240 pipe_config->has_infoframe = true; 4241 4242 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4243 pipe_config->hdmi_scrambling = true; 4244 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4245 pipe_config->hdmi_high_tmds_clock_ratio = true; 4246 /* fall through */ 4247 case TRANS_DDI_MODE_SELECT_DVI: 4248 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4249 pipe_config->lane_count = 4; 4250 break; 4251 case TRANS_DDI_MODE_SELECT_FDI: 4252 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4253 break; 4254 case TRANS_DDI_MODE_SELECT_DP_SST: 4255 if (encoder->type == INTEL_OUTPUT_EDP) 4256 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4257 else 4258 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4259 pipe_config->lane_count = 4260 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4261 intel_dp_get_m_n(intel_crtc, pipe_config); 4262 4263 if (INTEL_GEN(dev_priv) >= 11) { 4264 i915_reg_t dp_tp_ctl; 4265 4266 if (IS_GEN(dev_priv, 11)) 4267 dp_tp_ctl = DP_TP_CTL(encoder->port); 4268 else 4269 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4270 4271 pipe_config->fec_enable = 4272 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4273 4274 drm_dbg_kms(&dev_priv->drm, 4275 "[ENCODER:%d:%s] Fec status: %u\n", 4276 encoder->base.base.id, encoder->base.name, 4277 pipe_config->fec_enable); 4278 } 4279 4280 pipe_config->infoframes.enable |= 4281 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4282 4283 break; 4284 case TRANS_DDI_MODE_SELECT_DP_MST: 4285 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4286 pipe_config->lane_count = 4287 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4288 4289 if (INTEL_GEN(dev_priv) >= 12) 4290 pipe_config->mst_master_transcoder = 4291 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4292 4293 intel_dp_get_m_n(intel_crtc, pipe_config); 4294 4295 pipe_config->infoframes.enable |= 4296 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4297 break; 4298 default: 4299 break; 4300 } 4301 4302 pipe_config->has_audio = 4303 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4304 4305 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4306 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4307 /* 4308 * This is a big fat ugly hack. 4309 * 4310 * Some machines in UEFI boot mode provide us a VBT that has 18 4311 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4312 * unknown we fail to light up. Yet the same BIOS boots up with 4313 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4314 * max, not what it tells us to use. 4315 * 4316 * Note: This will still be broken if the eDP panel is not lit 4317 * up by the BIOS, and thus we can't get the mode at module 4318 * load. 4319 */ 4320 drm_dbg_kms(&dev_priv->drm, 4321 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4322 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4323 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4324 } 4325 4326 intel_ddi_clock_get(encoder, pipe_config); 4327 4328 if (IS_GEN9_LP(dev_priv)) 4329 pipe_config->lane_lat_optim_mask = 4330 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4331 4332 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4333 4334 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4335 4336 intel_read_infoframe(encoder, pipe_config, 4337 HDMI_INFOFRAME_TYPE_AVI, 4338 &pipe_config->infoframes.avi); 4339 intel_read_infoframe(encoder, pipe_config, 4340 HDMI_INFOFRAME_TYPE_SPD, 4341 &pipe_config->infoframes.spd); 4342 intel_read_infoframe(encoder, pipe_config, 4343 HDMI_INFOFRAME_TYPE_VENDOR, 4344 &pipe_config->infoframes.hdmi); 4345 intel_read_infoframe(encoder, pipe_config, 4346 HDMI_INFOFRAME_TYPE_DRM, 4347 &pipe_config->infoframes.drm); 4348 4349 if (INTEL_GEN(dev_priv) >= 8) 4350 bdw_get_trans_port_sync_config(pipe_config); 4351 4352 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4353 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4354 } 4355 4356 static enum intel_output_type 4357 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4358 struct intel_crtc_state *crtc_state, 4359 struct drm_connector_state *conn_state) 4360 { 4361 switch (conn_state->connector->connector_type) { 4362 case DRM_MODE_CONNECTOR_HDMIA: 4363 return INTEL_OUTPUT_HDMI; 4364 case DRM_MODE_CONNECTOR_eDP: 4365 return INTEL_OUTPUT_EDP; 4366 case DRM_MODE_CONNECTOR_DisplayPort: 4367 return INTEL_OUTPUT_DP; 4368 default: 4369 MISSING_CASE(conn_state->connector->connector_type); 4370 return INTEL_OUTPUT_UNUSED; 4371 } 4372 } 4373 4374 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4375 struct intel_crtc_state *pipe_config, 4376 struct drm_connector_state *conn_state) 4377 { 4378 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4380 enum port port = encoder->port; 4381 int ret; 4382 4383 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4384 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4385 4386 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4387 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4388 } else { 4389 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4390 } 4391 4392 if (ret) 4393 return ret; 4394 4395 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4396 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4397 pipe_config->pch_pfit.force_thru = 4398 pipe_config->pch_pfit.enabled || 4399 pipe_config->crc_enabled; 4400 4401 if (IS_GEN9_LP(dev_priv)) 4402 pipe_config->lane_lat_optim_mask = 4403 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4404 4405 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4406 4407 return 0; 4408 } 4409 4410 static bool mode_equal(const struct drm_display_mode *mode1, 4411 const struct drm_display_mode *mode2) 4412 { 4413 return drm_mode_match(mode1, mode2, 4414 DRM_MODE_MATCH_TIMINGS | 4415 DRM_MODE_MATCH_FLAGS | 4416 DRM_MODE_MATCH_3D_FLAGS) && 4417 mode1->clock == mode2->clock; /* we want an exact match */ 4418 } 4419 4420 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4421 const struct intel_link_m_n *m_n_2) 4422 { 4423 return m_n_1->tu == m_n_2->tu && 4424 m_n_1->gmch_m == m_n_2->gmch_m && 4425 m_n_1->gmch_n == m_n_2->gmch_n && 4426 m_n_1->link_m == m_n_2->link_m && 4427 m_n_1->link_n == m_n_2->link_n; 4428 } 4429 4430 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4431 const struct intel_crtc_state *crtc_state2) 4432 { 4433 return crtc_state1->hw.active && crtc_state2->hw.active && 4434 crtc_state1->output_types == crtc_state2->output_types && 4435 crtc_state1->output_format == crtc_state2->output_format && 4436 crtc_state1->lane_count == crtc_state2->lane_count && 4437 crtc_state1->port_clock == crtc_state2->port_clock && 4438 mode_equal(&crtc_state1->hw.adjusted_mode, 4439 &crtc_state2->hw.adjusted_mode) && 4440 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4441 } 4442 4443 static u8 4444 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4445 int tile_group_id) 4446 { 4447 struct drm_connector *connector; 4448 const struct drm_connector_state *conn_state; 4449 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4450 struct intel_atomic_state *state = 4451 to_intel_atomic_state(ref_crtc_state->uapi.state); 4452 u8 transcoders = 0; 4453 int i; 4454 4455 /* 4456 * We don't enable port sync on BDW due to missing w/as and 4457 * due to not having adjusted the modeset sequence appropriately. 4458 */ 4459 if (INTEL_GEN(dev_priv) < 9) 4460 return 0; 4461 4462 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4463 return 0; 4464 4465 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4466 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4467 const struct intel_crtc_state *crtc_state; 4468 4469 if (!crtc) 4470 continue; 4471 4472 if (!connector->has_tile || 4473 connector->tile_group->id != 4474 tile_group_id) 4475 continue; 4476 crtc_state = intel_atomic_get_new_crtc_state(state, 4477 crtc); 4478 if (!crtcs_port_sync_compatible(ref_crtc_state, 4479 crtc_state)) 4480 continue; 4481 transcoders |= BIT(crtc_state->cpu_transcoder); 4482 } 4483 4484 return transcoders; 4485 } 4486 4487 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4488 struct intel_crtc_state *crtc_state, 4489 struct drm_connector_state *conn_state) 4490 { 4491 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4492 struct drm_connector *connector = conn_state->connector; 4493 u8 port_sync_transcoders = 0; 4494 4495 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4496 encoder->base.base.id, encoder->base.name, 4497 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4498 4499 if (connector->has_tile) 4500 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4501 connector->tile_group->id); 4502 4503 /* 4504 * EDP Transcoders cannot be ensalved 4505 * make them a master always when present 4506 */ 4507 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4508 crtc_state->master_transcoder = TRANSCODER_EDP; 4509 else 4510 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4511 4512 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4513 crtc_state->master_transcoder = INVALID_TRANSCODER; 4514 crtc_state->sync_mode_slaves_mask = 4515 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4516 } 4517 4518 return 0; 4519 } 4520 4521 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4522 { 4523 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4524 4525 intel_dp_encoder_flush_work(encoder); 4526 4527 drm_encoder_cleanup(encoder); 4528 kfree(dig_port); 4529 } 4530 4531 static const struct drm_encoder_funcs intel_ddi_funcs = { 4532 .reset = intel_dp_encoder_reset, 4533 .destroy = intel_ddi_encoder_destroy, 4534 }; 4535 4536 static struct intel_connector * 4537 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4538 { 4539 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 4540 struct intel_connector *connector; 4541 enum port port = intel_dig_port->base.port; 4542 4543 connector = intel_connector_alloc(); 4544 if (!connector) 4545 return NULL; 4546 4547 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4548 intel_dig_port->dp.prepare_link_retrain = 4549 intel_ddi_prepare_link_retrain; 4550 intel_dig_port->dp.set_link_train = intel_ddi_set_link_train; 4551 intel_dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4552 4553 if (INTEL_GEN(dev_priv) >= 12) 4554 intel_dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4555 else if (INTEL_GEN(dev_priv) >= 11) 4556 intel_dig_port->dp.set_signal_levels = icl_set_signal_levels; 4557 else if (IS_CANNONLAKE(dev_priv)) 4558 intel_dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4559 else if (IS_GEN9_LP(dev_priv)) 4560 intel_dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4561 else 4562 intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4563 4564 intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4565 intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4566 4567 if (INTEL_GEN(dev_priv) < 12) { 4568 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); 4569 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); 4570 } 4571 4572 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4573 kfree(connector); 4574 return NULL; 4575 } 4576 4577 return connector; 4578 } 4579 4580 static int modeset_pipe(struct drm_crtc *crtc, 4581 struct drm_modeset_acquire_ctx *ctx) 4582 { 4583 struct drm_atomic_state *state; 4584 struct drm_crtc_state *crtc_state; 4585 int ret; 4586 4587 state = drm_atomic_state_alloc(crtc->dev); 4588 if (!state) 4589 return -ENOMEM; 4590 4591 state->acquire_ctx = ctx; 4592 4593 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4594 if (IS_ERR(crtc_state)) { 4595 ret = PTR_ERR(crtc_state); 4596 goto out; 4597 } 4598 4599 crtc_state->connectors_changed = true; 4600 4601 ret = drm_atomic_commit(state); 4602 out: 4603 drm_atomic_state_put(state); 4604 4605 return ret; 4606 } 4607 4608 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4609 struct drm_modeset_acquire_ctx *ctx) 4610 { 4611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4612 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4613 struct intel_connector *connector = hdmi->attached_connector; 4614 struct i2c_adapter *adapter = 4615 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4616 struct drm_connector_state *conn_state; 4617 struct intel_crtc_state *crtc_state; 4618 struct intel_crtc *crtc; 4619 u8 config; 4620 int ret; 4621 4622 if (!connector || connector->base.status != connector_status_connected) 4623 return 0; 4624 4625 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4626 ctx); 4627 if (ret) 4628 return ret; 4629 4630 conn_state = connector->base.state; 4631 4632 crtc = to_intel_crtc(conn_state->crtc); 4633 if (!crtc) 4634 return 0; 4635 4636 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4637 if (ret) 4638 return ret; 4639 4640 crtc_state = to_intel_crtc_state(crtc->base.state); 4641 4642 drm_WARN_ON(&dev_priv->drm, 4643 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4644 4645 if (!crtc_state->hw.active) 4646 return 0; 4647 4648 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4649 !crtc_state->hdmi_scrambling) 4650 return 0; 4651 4652 if (conn_state->commit && 4653 !try_wait_for_completion(&conn_state->commit->hw_done)) 4654 return 0; 4655 4656 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4657 if (ret < 0) { 4658 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4659 ret); 4660 return 0; 4661 } 4662 4663 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4664 crtc_state->hdmi_high_tmds_clock_ratio && 4665 !!(config & SCDC_SCRAMBLING_ENABLE) == 4666 crtc_state->hdmi_scrambling) 4667 return 0; 4668 4669 /* 4670 * HDMI 2.0 says that one should not send scrambled data 4671 * prior to configuring the sink scrambling, and that 4672 * TMDS clock/data transmission should be suspended when 4673 * changing the TMDS clock rate in the sink. So let's 4674 * just do a full modeset here, even though some sinks 4675 * would be perfectly happy if were to just reconfigure 4676 * the SCDC settings on the fly. 4677 */ 4678 return modeset_pipe(&crtc->base, ctx); 4679 } 4680 4681 static enum intel_hotplug_state 4682 intel_ddi_hotplug(struct intel_encoder *encoder, 4683 struct intel_connector *connector) 4684 { 4685 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4686 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4687 enum phy phy = intel_port_to_phy(i915, encoder->port); 4688 bool is_tc = intel_phy_is_tc(i915, phy); 4689 struct drm_modeset_acquire_ctx ctx; 4690 enum intel_hotplug_state state; 4691 int ret; 4692 4693 state = intel_encoder_hotplug(encoder, connector); 4694 4695 drm_modeset_acquire_init(&ctx, 0); 4696 4697 for (;;) { 4698 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4699 ret = intel_hdmi_reset_link(encoder, &ctx); 4700 else 4701 ret = intel_dp_retrain_link(encoder, &ctx); 4702 4703 if (ret == -EDEADLK) { 4704 drm_modeset_backoff(&ctx); 4705 continue; 4706 } 4707 4708 break; 4709 } 4710 4711 drm_modeset_drop_locks(&ctx); 4712 drm_modeset_acquire_fini(&ctx); 4713 drm_WARN(encoder->base.dev, ret, 4714 "Acquiring modeset locks failed with %i\n", ret); 4715 4716 /* 4717 * Unpowered type-c dongles can take some time to boot and be 4718 * responsible, so here giving some time to those dongles to power up 4719 * and then retrying the probe. 4720 * 4721 * On many platforms the HDMI live state signal is known to be 4722 * unreliable, so we can't use it to detect if a sink is connected or 4723 * not. Instead we detect if it's connected based on whether we can 4724 * read the EDID or not. That in turn has a problem during disconnect, 4725 * since the HPD interrupt may be raised before the DDC lines get 4726 * disconnected (due to how the required length of DDC vs. HPD 4727 * connector pins are specified) and so we'll still be able to get a 4728 * valid EDID. To solve this schedule another detection cycle if this 4729 * time around we didn't detect any change in the sink's connection 4730 * status. 4731 * 4732 * Type-c connectors which get their HPD signal deasserted then 4733 * reasserted, without unplugging/replugging the sink from the 4734 * connector, introduce a delay until the AUX channel communication 4735 * becomes functional. Retry the detection for 5 seconds on type-c 4736 * connectors to account for this delay. 4737 */ 4738 if (state == INTEL_HOTPLUG_UNCHANGED && 4739 connector->hotplug_retries < (is_tc ? 5 : 1) && 4740 !dig_port->dp.is_mst) 4741 state = INTEL_HOTPLUG_RETRY; 4742 4743 return state; 4744 } 4745 4746 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4747 { 4748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4749 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4750 4751 return intel_de_read(dev_priv, SDEISR) & bit; 4752 } 4753 4754 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4755 { 4756 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4757 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4758 4759 return intel_de_read(dev_priv, DEISR) & bit; 4760 } 4761 4762 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4763 { 4764 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4765 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4766 4767 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4768 } 4769 4770 static struct intel_connector * 4771 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4772 { 4773 struct intel_connector *connector; 4774 enum port port = intel_dig_port->base.port; 4775 4776 connector = intel_connector_alloc(); 4777 if (!connector) 4778 return NULL; 4779 4780 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4781 intel_hdmi_init_connector(intel_dig_port, connector); 4782 4783 return connector; 4784 } 4785 4786 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4787 { 4788 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4789 4790 if (dport->base.port != PORT_A) 4791 return false; 4792 4793 if (dport->saved_port_bits & DDI_A_4_LANES) 4794 return false; 4795 4796 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4797 * supported configuration 4798 */ 4799 if (IS_GEN9_LP(dev_priv)) 4800 return true; 4801 4802 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4803 * one who does also have a full A/E split called 4804 * DDI_F what makes DDI_E useless. However for this 4805 * case let's trust VBT info. 4806 */ 4807 if (IS_CANNONLAKE(dev_priv) && 4808 !intel_bios_is_port_present(dev_priv, PORT_E)) 4809 return true; 4810 4811 return false; 4812 } 4813 4814 static int 4815 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4816 { 4817 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4818 enum port port = intel_dport->base.port; 4819 int max_lanes = 4; 4820 4821 if (INTEL_GEN(dev_priv) >= 11) 4822 return max_lanes; 4823 4824 if (port == PORT_A || port == PORT_E) { 4825 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4826 max_lanes = port == PORT_A ? 4 : 0; 4827 else 4828 /* Both A and E share 2 lanes */ 4829 max_lanes = 2; 4830 } 4831 4832 /* 4833 * Some BIOS might fail to set this bit on port A if eDP 4834 * wasn't lit up at boot. Force this bit set when needed 4835 * so we use the proper lane count for our calculations. 4836 */ 4837 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4838 drm_dbg_kms(&dev_priv->drm, 4839 "Forcing DDI_A_4_LANES for port A\n"); 4840 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4841 max_lanes = 4; 4842 } 4843 4844 return max_lanes; 4845 } 4846 4847 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4848 { 4849 struct intel_digital_port *intel_dig_port; 4850 struct intel_encoder *encoder; 4851 bool init_hdmi, init_dp, init_lspcon = false; 4852 enum phy phy = intel_port_to_phy(dev_priv, port); 4853 4854 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 4855 intel_bios_port_supports_hdmi(dev_priv, port); 4856 init_dp = intel_bios_port_supports_dp(dev_priv, port); 4857 4858 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4859 /* 4860 * Lspcon device needs to be driven with DP connector 4861 * with special detection sequence. So make sure DP 4862 * is initialized before lspcon. 4863 */ 4864 init_dp = true; 4865 init_lspcon = true; 4866 init_hdmi = false; 4867 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4868 port_name(port)); 4869 } 4870 4871 if (!init_dp && !init_hdmi) { 4872 drm_dbg_kms(&dev_priv->drm, 4873 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4874 port_name(port)); 4875 return; 4876 } 4877 4878 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4879 if (!intel_dig_port) 4880 return; 4881 4882 encoder = &intel_dig_port->base; 4883 4884 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4885 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4886 4887 encoder->hotplug = intel_ddi_hotplug; 4888 encoder->compute_output_type = intel_ddi_compute_output_type; 4889 encoder->compute_config = intel_ddi_compute_config; 4890 encoder->compute_config_late = intel_ddi_compute_config_late; 4891 encoder->enable = intel_enable_ddi; 4892 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4893 encoder->pre_enable = intel_ddi_pre_enable; 4894 encoder->disable = intel_disable_ddi; 4895 encoder->post_disable = intel_ddi_post_disable; 4896 encoder->update_pipe = intel_ddi_update_pipe; 4897 encoder->get_hw_state = intel_ddi_get_hw_state; 4898 encoder->get_config = intel_ddi_get_config; 4899 encoder->suspend = intel_dp_encoder_suspend; 4900 encoder->get_power_domains = intel_ddi_get_power_domains; 4901 4902 encoder->type = INTEL_OUTPUT_DDI; 4903 encoder->power_domain = intel_port_to_power_domain(port); 4904 encoder->port = port; 4905 encoder->cloneable = 0; 4906 encoder->pipe_mask = ~0; 4907 4908 if (INTEL_GEN(dev_priv) >= 11) 4909 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4910 DDI_BUF_CTL(port)) & 4911 DDI_BUF_PORT_REVERSAL; 4912 else 4913 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4914 DDI_BUF_CTL(port)) & 4915 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4916 4917 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4918 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4919 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4920 4921 if (intel_phy_is_tc(dev_priv, phy)) { 4922 bool is_legacy = 4923 !intel_bios_port_supports_typec_usb(dev_priv, port) && 4924 !intel_bios_port_supports_tbt(dev_priv, port); 4925 4926 intel_tc_port_init(intel_dig_port, is_legacy); 4927 4928 encoder->update_prepare = intel_ddi_update_prepare; 4929 encoder->update_complete = intel_ddi_update_complete; 4930 } 4931 4932 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4933 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4934 port - PORT_A; 4935 4936 if (init_dp) { 4937 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4938 goto err; 4939 4940 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4941 } 4942 4943 /* In theory we don't need the encoder->type check, but leave it just in 4944 * case we have some really bad VBTs... */ 4945 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4946 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4947 goto err; 4948 } 4949 4950 if (init_lspcon) { 4951 if (lspcon_init(intel_dig_port)) 4952 /* TODO: handle hdmi info frame part */ 4953 drm_dbg_kms(&dev_priv->drm, 4954 "LSPCON init success on port %c\n", 4955 port_name(port)); 4956 else 4957 /* 4958 * LSPCON init faied, but DP init was success, so 4959 * lets try to drive as DP++ port. 4960 */ 4961 drm_err(&dev_priv->drm, 4962 "LSPCON init failed on port %c\n", 4963 port_name(port)); 4964 } 4965 4966 if (INTEL_GEN(dev_priv) >= 11) { 4967 if (intel_phy_is_tc(dev_priv, phy)) 4968 intel_dig_port->connected = intel_tc_port_connected; 4969 else 4970 intel_dig_port->connected = lpt_digital_port_connected; 4971 } else if (INTEL_GEN(dev_priv) >= 8) { 4972 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 4973 intel_dig_port->connected = bdw_digital_port_connected; 4974 else 4975 intel_dig_port->connected = lpt_digital_port_connected; 4976 } else { 4977 if (port == PORT_A) 4978 intel_dig_port->connected = hsw_digital_port_connected; 4979 else 4980 intel_dig_port->connected = lpt_digital_port_connected; 4981 } 4982 4983 intel_infoframe_init(intel_dig_port); 4984 4985 return; 4986 4987 err: 4988 drm_encoder_cleanup(&encoder->base); 4989 kfree(intel_dig_port); 4990 } 4991