1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 37 #include "icl_dsi.h" 38 #include "intel_alpm.h" 39 #include "intel_audio.h" 40 #include "intel_audio_regs.h" 41 #include "intel_backlight.h" 42 #include "intel_combo_phy.h" 43 #include "intel_combo_phy_regs.h" 44 #include "intel_connector.h" 45 #include "intel_crtc.h" 46 #include "intel_cx0_phy.h" 47 #include "intel_cx0_phy_regs.h" 48 #include "intel_ddi.h" 49 #include "intel_ddi_buf_trans.h" 50 #include "intel_de.h" 51 #include "intel_display_power.h" 52 #include "intel_display_regs.h" 53 #include "intel_display_types.h" 54 #include "intel_display_utils.h" 55 #include "intel_display_wa.h" 56 #include "intel_dkl_phy.h" 57 #include "intel_dkl_phy_regs.h" 58 #include "intel_dp.h" 59 #include "intel_dp_aux.h" 60 #include "intel_dp_link_training.h" 61 #include "intel_dp_mst.h" 62 #include "intel_dp_test.h" 63 #include "intel_dp_tunnel.h" 64 #include "intel_dpio_phy.h" 65 #include "intel_dsi.h" 66 #include "intel_encoder.h" 67 #include "intel_fdi.h" 68 #include "intel_fifo_underrun.h" 69 #include "intel_gmbus.h" 70 #include "intel_hdcp.h" 71 #include "intel_hdmi.h" 72 #include "intel_hotplug.h" 73 #include "intel_hti.h" 74 #include "intel_lspcon.h" 75 #include "intel_lt_phy.h" 76 #include "intel_mg_phy_regs.h" 77 #include "intel_modeset_lock.h" 78 #include "intel_panel.h" 79 #include "intel_pfit.h" 80 #include "intel_pps.h" 81 #include "intel_psr.h" 82 #include "intel_quirks.h" 83 #include "intel_snps_phy.h" 84 #include "intel_step.h" 85 #include "intel_tc.h" 86 #include "intel_vdsc.h" 87 #include "intel_vdsc_regs.h" 88 #include "intel_vrr.h" 89 #include "skl_scaler.h" 90 #include "skl_universal_plane.h" 91 92 struct intel_dpll; 93 94 static const u8 index_to_dp_signal_levels[] = { 95 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 98 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 99 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 100 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 101 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 102 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 103 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 104 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 105 }; 106 107 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 108 const struct intel_ddi_buf_trans *trans) 109 { 110 int level; 111 112 level = intel_bios_hdmi_level_shift(encoder->devdata); 113 if (level < 0) 114 level = trans->hdmi_default_entry; 115 116 return level; 117 } 118 119 static bool has_buf_trans_select(struct intel_display *display) 120 { 121 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 122 } 123 124 static bool has_iboost(struct intel_display *display) 125 { 126 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 127 } 128 129 /* 130 * Starting with Haswell, DDI port buffers must be programmed with correct 131 * values in advance. This function programs the correct values for 132 * DP/eDP/FDI use cases. 133 */ 134 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 135 const struct intel_crtc_state *crtc_state) 136 { 137 struct intel_display *display = to_intel_display(encoder); 138 u32 iboost_bit = 0; 139 int i, n_entries; 140 enum port port = encoder->port; 141 const struct intel_ddi_buf_trans *trans; 142 143 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 144 if (drm_WARN_ON_ONCE(display->drm, !trans)) 145 return; 146 147 /* If we're boosting the current, set bit 31 of trans1 */ 148 if (has_iboost(display) && 149 intel_bios_dp_boost_level(encoder->devdata)) 150 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 151 152 for (i = 0; i < n_entries; i++) { 153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 154 trans->entries[i].hsw.trans1 | iboost_bit); 155 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 156 trans->entries[i].hsw.trans2); 157 } 158 } 159 160 /* 161 * Starting with Haswell, DDI port buffers must be programmed with correct 162 * values in advance. This function programs the correct values for 163 * HDMI/DVI use cases. 164 */ 165 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 166 const struct intel_crtc_state *crtc_state) 167 { 168 struct intel_display *display = to_intel_display(encoder); 169 int level = intel_ddi_level(encoder, crtc_state, 0); 170 u32 iboost_bit = 0; 171 int n_entries; 172 enum port port = encoder->port; 173 const struct intel_ddi_buf_trans *trans; 174 175 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 176 if (drm_WARN_ON_ONCE(display->drm, !trans)) 177 return; 178 179 /* If we're boosting the current, set bit 31 of trans1 */ 180 if (has_iboost(display) && 181 intel_bios_hdmi_boost_level(encoder->devdata)) 182 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 183 184 /* Entry 9 is for HDMI: */ 185 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 186 trans->entries[level].hsw.trans1 | iboost_bit); 187 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 188 trans->entries[level].hsw.trans2); 189 } 190 191 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 192 { 193 if (DISPLAY_VER(display) >= 14) 194 return XELPDP_PORT_BUF_CTL1(display, port); 195 else 196 return DDI_BUF_CTL(port); 197 } 198 199 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 200 { 201 /* 202 * Bspec's platform specific timeouts: 203 * MTL+ : 100 us 204 * BXT : fixed 16 us 205 * HSW-ADL: 8 us 206 * 207 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 208 */ 209 if (display->platform.broxton) { 210 udelay(16); 211 return; 212 } 213 214 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 215 if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port), 216 DDI_BUF_IS_IDLE, 10)) 217 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 218 port_name(port)); 219 } 220 221 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 222 { 223 struct intel_display *display = to_intel_display(encoder); 224 enum port port = encoder->port; 225 226 /* 227 * Bspec's platform specific timeouts: 228 * MTL+ : 10000 us 229 * DG2 : 1200 us 230 * TGL-ADL combo PHY: 1000 us 231 * TGL-ADL TypeC PHY: 3000 us 232 * HSW-ICL : fixed 518 us 233 */ 234 if (DISPLAY_VER(display) < 10) { 235 usleep_range(518, 1000); 236 return; 237 } 238 239 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 240 if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port), 241 DDI_BUF_IS_IDLE, 10)) 242 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_dpll *pll = crtc_state->intel_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static int dp_phy_lane_stagger_delay(int port_clock) 332 { 333 /* 334 * Return the number of symbol clocks delay used to stagger the 335 * assertion/desassertion of the port lane enables. The target delay 336 * time is 100 ns or greater, return the number of symbols specific to 337 * the provided port_clock (aka link clock) corresponding to this delay 338 * time, i.e. so that 339 * 340 * number_of_symbols * duration_of_one_symbol >= 100 ns 341 * 342 * The delay must be applied only on TypeC DP outputs, for everything else 343 * the delay must be set to 0. 344 * 345 * Return the number of link symbols per 100 ns: 346 * port_clock (10 kHz) -> bits / 100 us 347 * / symbol_size -> symbols / 100 us 348 * / 1000 -> symbols / 100 ns 349 */ 350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 351 } 352 353 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state) 355 { 356 struct intel_display *display = to_intel_display(encoder); 357 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 358 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 359 360 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 362 DDI_BUF_TRANS_SELECT(0); 363 364 if (dig_port->lane_reversal) 365 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 366 if (dig_port->ddi_a_4_lanes) 367 intel_dp->DP |= DDI_A_4_LANES; 368 369 if (DISPLAY_VER(display) >= 14) { 370 if (intel_dp_is_uhbr(crtc_state)) 371 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 372 else 373 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 374 } 375 376 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 378 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 379 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 380 } 381 382 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 384 385 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 386 } 387 } 388 389 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 390 { 391 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 392 393 switch (val) { 394 case DDI_CLK_SEL_NONE: 395 return 0; 396 case DDI_CLK_SEL_TBT_162: 397 return 162000; 398 case DDI_CLK_SEL_TBT_270: 399 return 270000; 400 case DDI_CLK_SEL_TBT_540: 401 return 540000; 402 case DDI_CLK_SEL_TBT_810: 403 return 810000; 404 default: 405 MISSING_CASE(val); 406 return 0; 407 } 408 } 409 410 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 411 { 412 /* CRT dotclock is determined via other means */ 413 if (pipe_config->has_pch_encoder) 414 return; 415 416 pipe_config->hw.adjusted_mode.crtc_clock = 417 intel_crtc_dotclock(pipe_config); 418 } 419 420 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 421 const struct drm_connector_state *conn_state) 422 { 423 struct intel_display *display = to_intel_display(crtc_state); 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 u32 temp; 426 427 if (!intel_crtc_has_dp_encoder(crtc_state)) 428 return; 429 430 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 431 432 temp = DP_MSA_MISC_SYNC_CLOCK; 433 434 switch (crtc_state->pipe_bpp) { 435 case 18: 436 temp |= DP_MSA_MISC_6_BPC; 437 break; 438 case 24: 439 temp |= DP_MSA_MISC_8_BPC; 440 break; 441 case 30: 442 temp |= DP_MSA_MISC_10_BPC; 443 break; 444 case 36: 445 temp |= DP_MSA_MISC_12_BPC; 446 break; 447 default: 448 MISSING_CASE(crtc_state->pipe_bpp); 449 break; 450 } 451 452 /* nonsense combination */ 453 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 454 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 455 456 if (crtc_state->limited_color_range) 457 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 458 459 /* 460 * As per DP 1.2 spec section 2.3.4.3 while sending 461 * YCBCR 444 signals we should program MSA MISC1/0 fields with 462 * colorspace information. 463 */ 464 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 465 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 466 467 /* 468 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 469 * of Color Encoding Format and Content Color Gamut] while sending 470 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 471 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 472 */ 473 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 474 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 475 476 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 477 temp); 478 } 479 480 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 481 { 482 if (master_transcoder == TRANSCODER_EDP) 483 return 0; 484 else 485 return master_transcoder + 1; 486 } 487 488 static void 489 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 490 bool enable) 491 { 492 struct intel_display *display = to_intel_display(crtc_state); 493 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 494 u32 val = 0; 495 496 if (!HAS_DP20(display)) 497 return; 498 499 if (enable && intel_dp_is_uhbr(crtc_state)) 500 val = TRANS_DP2_128B132B_CHANNEL_CODING; 501 502 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 503 } 504 505 /* 506 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 507 * 508 * Only intended to be used by intel_ddi_enable_transcoder_func() and 509 * intel_ddi_config_transcoder_func(). 510 */ 511 static u32 512 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 513 const struct intel_crtc_state *crtc_state) 514 { 515 struct intel_display *display = to_intel_display(crtc_state); 516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 517 enum pipe pipe = crtc->pipe; 518 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 519 enum port port = encoder->port; 520 u32 temp; 521 522 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 523 temp = TRANS_DDI_FUNC_ENABLE; 524 if (DISPLAY_VER(display) >= 12) 525 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 526 else 527 temp |= TRANS_DDI_SELECT_PORT(port); 528 529 switch (crtc_state->pipe_bpp) { 530 default: 531 MISSING_CASE(crtc_state->pipe_bpp); 532 fallthrough; 533 case 18: 534 temp |= TRANS_DDI_BPC_6; 535 break; 536 case 24: 537 temp |= TRANS_DDI_BPC_8; 538 break; 539 case 30: 540 temp |= TRANS_DDI_BPC_10; 541 break; 542 case 36: 543 temp |= TRANS_DDI_BPC_12; 544 break; 545 } 546 547 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 548 temp |= TRANS_DDI_PVSYNC; 549 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 550 temp |= TRANS_DDI_PHSYNC; 551 552 if (cpu_transcoder == TRANSCODER_EDP) { 553 switch (pipe) { 554 default: 555 MISSING_CASE(pipe); 556 fallthrough; 557 case PIPE_A: 558 /* On Haswell, can only use the always-on power well for 559 * eDP when not using the panel fitter, and when not 560 * using motion blur mitigation (which we don't 561 * support). */ 562 if (crtc_state->pch_pfit.force_thru) 563 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 564 else 565 temp |= TRANS_DDI_EDP_INPUT_A_ON; 566 break; 567 case PIPE_B: 568 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 569 break; 570 case PIPE_C: 571 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 572 break; 573 } 574 } 575 576 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 577 if (crtc_state->has_hdmi_sink) 578 temp |= TRANS_DDI_MODE_SELECT_HDMI; 579 else 580 temp |= TRANS_DDI_MODE_SELECT_DVI; 581 582 if (crtc_state->hdmi_scrambling) 583 temp |= TRANS_DDI_HDMI_SCRAMBLING; 584 if (crtc_state->hdmi_high_tmds_clock_ratio) 585 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 586 if (DISPLAY_VER(display) >= 14) 587 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 588 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 589 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 590 temp |= (crtc_state->fdi_lanes - 1) << 1; 591 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 592 intel_dp_is_uhbr(crtc_state)) { 593 if (intel_dp_is_uhbr(crtc_state)) 594 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 595 else 596 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 597 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 598 599 if (DISPLAY_VER(display) >= 12) { 600 enum transcoder master; 601 602 master = crtc_state->mst_master_transcoder; 603 if (drm_WARN_ON(display->drm, 604 master == INVALID_TRANSCODER)) 605 master = TRANSCODER_A; 606 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 607 } 608 } else { 609 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 610 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 611 } 612 613 if (IS_DISPLAY_VER(display, 8, 10) && 614 crtc_state->master_transcoder != INVALID_TRANSCODER) { 615 u8 master_select = 616 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 617 618 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 619 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 620 } 621 622 return temp; 623 } 624 625 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 626 const struct intel_crtc_state *crtc_state) 627 { 628 struct intel_display *display = to_intel_display(crtc_state); 629 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 630 631 if (DISPLAY_VER(display) >= 11) { 632 enum transcoder master_transcoder = crtc_state->master_transcoder; 633 u32 ctl2 = 0; 634 635 if (master_transcoder != INVALID_TRANSCODER) { 636 u8 master_select = 637 bdw_trans_port_sync_master_select(master_transcoder); 638 639 ctl2 |= PORT_SYNC_MODE_ENABLE | 640 PORT_SYNC_MODE_MASTER_SELECT(master_select); 641 } 642 643 intel_de_write(display, 644 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 645 ctl2); 646 } 647 648 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 649 intel_ddi_transcoder_func_reg_val_get(encoder, 650 crtc_state)); 651 } 652 653 /* 654 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 655 * bit for the DDI function and enables the DP2 configuration. Called for all 656 * transcoder types. 657 */ 658 void 659 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 660 const struct intel_crtc_state *crtc_state) 661 { 662 struct intel_display *display = to_intel_display(crtc_state); 663 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 664 u32 ctl; 665 666 intel_ddi_config_transcoder_dp2(crtc_state, true); 667 668 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 669 ctl &= ~TRANS_DDI_FUNC_ENABLE; 670 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 671 ctl); 672 } 673 674 /* 675 * Disable the DDI function and port syncing. 676 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 677 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 678 * transcoders these are done later in intel_ddi_post_disable_dp(). 679 */ 680 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 681 { 682 struct intel_display *display = to_intel_display(crtc_state); 683 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 684 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 685 u32 ctl; 686 687 if (DISPLAY_VER(display) >= 11) 688 intel_de_write(display, 689 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 690 0); 691 692 ctl = intel_de_read(display, 693 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 694 695 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 696 697 ctl &= ~TRANS_DDI_FUNC_ENABLE; 698 699 if (IS_DISPLAY_VER(display, 8, 10)) 700 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 701 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 702 703 if (DISPLAY_VER(display) >= 12) { 704 if (!intel_dp_mst_is_master_trans(crtc_state)) { 705 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 706 TRANS_DDI_MODE_SELECT_MASK); 707 } 708 } else { 709 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 710 } 711 712 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 713 ctl); 714 715 if (intel_dp_mst_is_slave_trans(crtc_state)) 716 intel_ddi_config_transcoder_dp2(crtc_state, false); 717 718 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 719 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 720 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 721 /* Quirk time at 100ms for reliable operation */ 722 msleep(100); 723 } 724 } 725 726 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 727 enum transcoder cpu_transcoder, 728 bool enable, u32 hdcp_mask) 729 { 730 struct intel_display *display = to_intel_display(intel_encoder); 731 struct ref_tracker *wakeref; 732 int ret = 0; 733 734 wakeref = intel_display_power_get_if_enabled(display, 735 intel_encoder->power_domain); 736 if (drm_WARN_ON(display->drm, !wakeref)) 737 return -ENXIO; 738 739 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 740 hdcp_mask, enable ? hdcp_mask : 0); 741 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 742 return ret; 743 } 744 745 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 746 { 747 struct intel_display *display = to_intel_display(intel_connector); 748 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 749 int type = intel_connector->base.connector_type; 750 enum port port = encoder->port; 751 enum transcoder cpu_transcoder; 752 struct ref_tracker *wakeref; 753 enum pipe pipe = 0; 754 u32 ddi_mode; 755 bool ret; 756 757 wakeref = intel_display_power_get_if_enabled(display, 758 encoder->power_domain); 759 if (!wakeref) 760 return false; 761 762 /* Note: This returns false for DP MST primary encoders. */ 763 if (!encoder->get_hw_state(encoder, &pipe)) { 764 ret = false; 765 goto out; 766 } 767 768 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 769 cpu_transcoder = TRANSCODER_EDP; 770 else 771 cpu_transcoder = (enum transcoder) pipe; 772 773 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 774 TRANS_DDI_MODE_SELECT_MASK; 775 776 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 777 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 778 ret = type == DRM_MODE_CONNECTOR_HDMIA; 779 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 780 ret = type == DRM_MODE_CONNECTOR_VGA; 781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 782 ret = type == DRM_MODE_CONNECTOR_eDP || 783 type == DRM_MODE_CONNECTOR_DisplayPort; 784 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 785 /* 786 * encoder->get_hw_state() should have bailed out on MST. This 787 * must be SST and non-eDP. 788 */ 789 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 790 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 791 /* encoder->get_hw_state() should have bailed out on MST. */ 792 ret = false; 793 } else { 794 ret = false; 795 } 796 797 out: 798 intel_display_power_put(display, encoder->power_domain, wakeref); 799 800 return ret; 801 } 802 803 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 804 u8 *pipe_mask, bool *is_dp_mst) 805 { 806 struct intel_display *display = to_intel_display(encoder); 807 enum port port = encoder->port; 808 struct ref_tracker *wakeref; 809 enum pipe p; 810 u32 tmp; 811 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 812 813 *pipe_mask = 0; 814 *is_dp_mst = false; 815 816 wakeref = intel_display_power_get_if_enabled(display, 817 encoder->power_domain); 818 if (!wakeref) 819 return; 820 821 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 822 if (!(tmp & DDI_BUF_CTL_ENABLE)) 823 goto out; 824 825 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 826 tmp = intel_de_read(display, 827 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 828 829 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 830 default: 831 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 832 fallthrough; 833 case TRANS_DDI_EDP_INPUT_A_ON: 834 case TRANS_DDI_EDP_INPUT_A_ONOFF: 835 *pipe_mask = BIT(PIPE_A); 836 break; 837 case TRANS_DDI_EDP_INPUT_B_ONOFF: 838 *pipe_mask = BIT(PIPE_B); 839 break; 840 case TRANS_DDI_EDP_INPUT_C_ONOFF: 841 *pipe_mask = BIT(PIPE_C); 842 break; 843 } 844 845 goto out; 846 } 847 848 for_each_pipe(display, p) { 849 enum transcoder cpu_transcoder = (enum transcoder)p; 850 u32 port_mask, ddi_select, ddi_mode; 851 struct ref_tracker *trans_wakeref; 852 853 trans_wakeref = intel_display_power_get_if_enabled(display, 854 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 855 if (!trans_wakeref) 856 continue; 857 858 if (DISPLAY_VER(display) >= 12) { 859 port_mask = TGL_TRANS_DDI_PORT_MASK; 860 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 861 } else { 862 port_mask = TRANS_DDI_PORT_MASK; 863 ddi_select = TRANS_DDI_SELECT_PORT(port); 864 } 865 866 tmp = intel_de_read(display, 867 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 868 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 869 trans_wakeref); 870 871 if ((tmp & port_mask) != ddi_select) 872 continue; 873 874 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 875 876 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 877 mst_pipe_mask |= BIT(p); 878 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 879 dp128b132b_pipe_mask |= BIT(p); 880 881 *pipe_mask |= BIT(p); 882 } 883 884 if (!*pipe_mask) 885 drm_dbg_kms(display->drm, 886 "No pipe for [ENCODER:%d:%s] found\n", 887 encoder->base.base.id, encoder->base.name); 888 889 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 890 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 891 892 /* 893 * If we don't have 8b/10b MST, but have more than one 894 * transcoder in 128b/132b mode, we know it must be 128b/132b 895 * MST. 896 * 897 * Otherwise, we fall back to checking the current MST 898 * state. It's not accurate for hardware takeover at probe, but 899 * we don't expect MST to have been enabled at that point, and 900 * can assume it's SST. 901 */ 902 if (hweight8(dp128b132b_pipe_mask) > 1 || 903 intel_dp_mst_active_streams(intel_dp)) 904 mst_pipe_mask = dp128b132b_pipe_mask; 905 } 906 907 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 908 drm_dbg_kms(display->drm, 909 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 910 encoder->base.base.id, encoder->base.name, 911 *pipe_mask); 912 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 913 } 914 915 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 916 drm_dbg_kms(display->drm, 917 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 918 encoder->base.base.id, encoder->base.name, 919 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 920 else 921 *is_dp_mst = mst_pipe_mask; 922 923 out: 924 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 925 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 926 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 927 BXT_PHY_LANE_POWERDOWN_ACK | 928 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 929 drm_err(display->drm, 930 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 931 encoder->base.base.id, encoder->base.name, tmp); 932 } 933 934 intel_display_power_put(display, encoder->power_domain, wakeref); 935 } 936 937 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 938 enum pipe *pipe) 939 { 940 u8 pipe_mask; 941 bool is_mst; 942 943 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 944 945 if (is_mst || !pipe_mask) 946 return false; 947 948 *pipe = ffs(pipe_mask) - 1; 949 950 return true; 951 } 952 953 static enum intel_display_power_domain 954 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 955 const struct intel_crtc_state *crtc_state) 956 { 957 struct intel_display *display = to_intel_display(dig_port); 958 959 /* 960 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 961 * DC states enabled at the same time, while for driver initiated AUX 962 * transfers we need the same AUX IOs to be powered but with DC states 963 * disabled. Accordingly use the AUX_IO_<port> power domain here which 964 * leaves DC states enabled. 965 * 966 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 967 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 968 * well, so we can acquire a wider AUX_<port> power domain reference 969 * instead of a specific AUX_IO_<port> reference without powering up any 970 * extra wells. 971 */ 972 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 973 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 974 else if (DISPLAY_VER(display) < 14 && 975 (intel_crtc_has_dp_encoder(crtc_state) || 976 intel_encoder_is_tc(&dig_port->base))) 977 return intel_aux_power_domain(dig_port); 978 else 979 return POWER_DOMAIN_INVALID; 980 } 981 982 static void 983 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 984 const struct intel_crtc_state *crtc_state) 985 { 986 struct intel_display *display = to_intel_display(dig_port); 987 enum intel_display_power_domain domain = 988 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 989 990 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 991 992 if (domain == POWER_DOMAIN_INVALID) 993 return; 994 995 dig_port->aux_wakeref = intel_display_power_get(display, domain); 996 } 997 998 static void 999 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 1000 const struct intel_crtc_state *crtc_state) 1001 { 1002 struct intel_display *display = to_intel_display(dig_port); 1003 enum intel_display_power_domain domain = 1004 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1005 struct ref_tracker *wf; 1006 1007 wf = fetch_and_zero(&dig_port->aux_wakeref); 1008 if (!wf) 1009 return; 1010 1011 intel_display_power_put(display, domain, wf); 1012 } 1013 1014 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1015 struct intel_crtc_state *crtc_state) 1016 { 1017 struct intel_display *display = to_intel_display(encoder); 1018 struct intel_digital_port *dig_port; 1019 1020 /* 1021 * TODO: Add support for MST encoders. Atm, the following should never 1022 * happen since fake-MST encoders don't set their get_power_domains() 1023 * hook. 1024 */ 1025 if (drm_WARN_ON(display->drm, 1026 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1027 return; 1028 1029 dig_port = enc_to_dig_port(encoder); 1030 1031 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1032 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1033 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1034 dig_port->ddi_io_power_domain); 1035 } 1036 1037 main_link_aux_power_domain_get(dig_port, crtc_state); 1038 } 1039 1040 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state) 1042 { 1043 struct intel_display *display = to_intel_display(crtc_state); 1044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1045 enum phy phy = intel_encoder_to_phy(encoder); 1046 u32 val; 1047 1048 if (cpu_transcoder == TRANSCODER_EDP) 1049 return; 1050 1051 if (DISPLAY_VER(display) >= 13) 1052 val = TGL_TRANS_CLK_SEL_PORT(phy); 1053 else if (DISPLAY_VER(display) >= 12) 1054 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1055 else 1056 val = TRANS_CLK_SEL_PORT(encoder->port); 1057 1058 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1059 } 1060 1061 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1062 { 1063 struct intel_display *display = to_intel_display(crtc_state); 1064 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1065 u32 val; 1066 1067 if (cpu_transcoder == TRANSCODER_EDP) 1068 return; 1069 1070 if (DISPLAY_VER(display) >= 12) 1071 val = TGL_TRANS_CLK_SEL_DISABLED; 1072 else 1073 val = TRANS_CLK_SEL_DISABLED; 1074 1075 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1076 } 1077 1078 static void _skl_ddi_set_iboost(struct intel_display *display, 1079 enum port port, u8 iboost) 1080 { 1081 u32 tmp; 1082 1083 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1084 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1085 if (iboost) 1086 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1087 else 1088 tmp |= BALANCE_LEG_DISABLE(port); 1089 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1090 } 1091 1092 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1093 const struct intel_crtc_state *crtc_state, 1094 int level) 1095 { 1096 struct intel_display *display = to_intel_display(encoder); 1097 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1098 u8 iboost; 1099 1100 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1101 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1102 else 1103 iboost = intel_bios_dp_boost_level(encoder->devdata); 1104 1105 if (iboost == 0) { 1106 const struct intel_ddi_buf_trans *trans; 1107 int n_entries; 1108 1109 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1110 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1111 return; 1112 1113 iboost = trans->entries[level].hsw.i_boost; 1114 } 1115 1116 /* Make sure that the requested I_boost is valid */ 1117 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1118 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1119 return; 1120 } 1121 1122 _skl_ddi_set_iboost(display, encoder->port, iboost); 1123 1124 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1125 _skl_ddi_set_iboost(display, PORT_E, iboost); 1126 } 1127 1128 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1129 const struct intel_crtc_state *crtc_state) 1130 { 1131 struct intel_display *display = to_intel_display(intel_dp); 1132 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1133 int n_entries; 1134 1135 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1136 1137 if (drm_WARN_ON(display->drm, n_entries < 1)) 1138 n_entries = 1; 1139 if (drm_WARN_ON(display->drm, 1140 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1141 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1142 1143 return index_to_dp_signal_levels[n_entries - 1] & 1144 DP_TRAIN_VOLTAGE_SWING_MASK; 1145 } 1146 1147 /* 1148 * We assume that the full set of pre-emphasis values can be 1149 * used on all DDI platforms. Should that change we need to 1150 * rethink this code. 1151 */ 1152 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1153 { 1154 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1155 } 1156 1157 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1158 int lane) 1159 { 1160 if (crtc_state->port_clock > 600000) 1161 return 0; 1162 1163 if (crtc_state->lane_count == 4) 1164 return lane >= 1 ? LOADGEN_SELECT : 0; 1165 else 1166 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1167 } 1168 1169 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1170 const struct intel_crtc_state *crtc_state) 1171 { 1172 struct intel_display *display = to_intel_display(encoder); 1173 const struct intel_ddi_buf_trans *trans; 1174 enum phy phy = intel_encoder_to_phy(encoder); 1175 int n_entries, ln; 1176 u32 val; 1177 1178 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1179 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1180 return; 1181 1182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1183 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1184 1185 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1186 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1187 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1188 intel_dp->hobl_active ? val : 0); 1189 } 1190 1191 /* Set PORT_TX_DW5 */ 1192 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1193 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1194 COEFF_POLARITY | CURSOR_PROGRAM | 1195 TAP2_DISABLE | TAP3_DISABLE); 1196 val |= SCALING_MODE_SEL(0x2); 1197 val |= RTERM_SELECT(0x6); 1198 val |= TAP3_DISABLE; 1199 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1200 1201 /* Program PORT_TX_DW2 */ 1202 for (ln = 0; ln < 4; ln++) { 1203 int level = intel_ddi_level(encoder, crtc_state, ln); 1204 1205 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1206 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1207 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1208 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1209 RCOMP_SCALAR(0x98)); 1210 } 1211 1212 /* Program PORT_TX_DW4 */ 1213 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1214 for (ln = 0; ln < 4; ln++) { 1215 int level = intel_ddi_level(encoder, crtc_state, ln); 1216 1217 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1218 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1219 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1220 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1221 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1222 } 1223 1224 /* Program PORT_TX_DW7 */ 1225 for (ln = 0; ln < 4; ln++) { 1226 int level = intel_ddi_level(encoder, crtc_state, ln); 1227 1228 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1229 N_SCALAR_MASK, 1230 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1231 } 1232 } 1233 1234 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1235 const struct intel_crtc_state *crtc_state) 1236 { 1237 struct intel_display *display = to_intel_display(encoder); 1238 enum phy phy = intel_encoder_to_phy(encoder); 1239 u32 val; 1240 int ln; 1241 1242 /* 1243 * 1. If port type is eDP or DP, 1244 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1245 * else clear to 0b. 1246 */ 1247 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1248 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1249 val &= ~COMMON_KEEPER_EN; 1250 else 1251 val |= COMMON_KEEPER_EN; 1252 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1253 1254 /* 2. Program loadgen select */ 1255 /* 1256 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1257 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1258 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1259 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1260 */ 1261 for (ln = 0; ln < 4; ln++) { 1262 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1263 LOADGEN_SELECT, 1264 icl_combo_phy_loadgen_select(crtc_state, ln)); 1265 } 1266 1267 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1268 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1269 0, SUS_CLOCK_CONFIG); 1270 1271 /* 4. Clear training enable to change swing values */ 1272 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1273 val &= ~TX_TRAINING_EN; 1274 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1275 1276 /* 5. Program swing and de-emphasis */ 1277 icl_ddi_combo_vswing_program(encoder, crtc_state); 1278 1279 /* 6. Set training enable to trigger update */ 1280 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1281 val |= TX_TRAINING_EN; 1282 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1283 } 1284 1285 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1286 const struct intel_crtc_state *crtc_state) 1287 { 1288 struct intel_display *display = to_intel_display(encoder); 1289 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1290 const struct intel_ddi_buf_trans *trans; 1291 int n_entries, ln; 1292 1293 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1294 return; 1295 1296 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1297 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1298 return; 1299 1300 for (ln = 0; ln < 2; ln++) { 1301 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1302 CRI_USE_FS32, 0); 1303 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1304 CRI_USE_FS32, 0); 1305 } 1306 1307 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1308 for (ln = 0; ln < 2; ln++) { 1309 int level; 1310 1311 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1312 1313 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1314 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1315 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1316 1317 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1318 1319 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1320 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1321 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1322 } 1323 1324 /* Program MG_TX_DRVCTRL with values from vswing table */ 1325 for (ln = 0; ln < 2; ln++) { 1326 int level; 1327 1328 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1329 1330 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1331 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1332 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1333 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1334 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1335 CRI_TXDEEMPH_OVERRIDE_EN); 1336 1337 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1338 1339 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1340 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1341 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1342 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1343 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1344 CRI_TXDEEMPH_OVERRIDE_EN); 1345 1346 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1347 } 1348 1349 /* 1350 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1351 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1352 * values from table for which TX1 and TX2 enabled. 1353 */ 1354 for (ln = 0; ln < 2; ln++) { 1355 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1356 CFG_LOW_RATE_LKREN_EN, 1357 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1358 } 1359 1360 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1361 for (ln = 0; ln < 2; ln++) { 1362 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1363 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1364 CFG_AMI_CK_DIV_OVERRIDE_EN, 1365 crtc_state->port_clock > 500000 ? 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1367 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1368 1369 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1370 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1371 CFG_AMI_CK_DIV_OVERRIDE_EN, 1372 crtc_state->port_clock > 500000 ? 1373 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1374 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1375 } 1376 1377 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1378 for (ln = 0; ln < 2; ln++) { 1379 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1380 0, CRI_CALCINIT); 1381 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1382 0, CRI_CALCINIT); 1383 } 1384 } 1385 1386 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1387 const struct intel_crtc_state *crtc_state) 1388 { 1389 struct intel_display *display = to_intel_display(encoder); 1390 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1391 const struct intel_ddi_buf_trans *trans; 1392 int n_entries, ln; 1393 1394 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1395 return; 1396 1397 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1398 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1399 return; 1400 1401 for (ln = 0; ln < 2; ln++) { 1402 int level; 1403 1404 /* Wa_16011342517:adl-p */ 1405 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011342517)) { 1406 if ((intel_encoder_is_hdmi(encoder) && 1407 crtc_state->port_clock == 594000) || 1408 (intel_encoder_is_dp(encoder) && 1409 crtc_state->port_clock == 162000)) { 1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1411 LOADGEN_SHARING_PMD_DISABLE, 1); 1412 } else { 1413 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1414 LOADGEN_SHARING_PMD_DISABLE, 0); 1415 } 1416 } 1417 1418 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1419 1420 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1421 1422 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1423 DKL_TX_PRESHOOT_COEFF_MASK | 1424 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1425 DKL_TX_VSWING_CONTROL_MASK, 1426 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1427 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1428 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1429 1430 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1431 1432 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1433 DKL_TX_PRESHOOT_COEFF_MASK | 1434 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1435 DKL_TX_VSWING_CONTROL_MASK, 1436 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1437 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1438 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1439 1440 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1441 DKL_TX_DP20BITMODE, 0); 1442 1443 if (display->platform.alderlake_p) { 1444 u32 val; 1445 1446 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1447 if (ln == 0) { 1448 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1449 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1450 } else { 1451 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1452 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1453 } 1454 } else { 1455 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1456 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1457 } 1458 1459 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1460 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1461 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1462 val); 1463 } 1464 } 1465 } 1466 1467 static int translate_signal_level(struct intel_dp *intel_dp, 1468 u8 signal_levels) 1469 { 1470 struct intel_display *display = to_intel_display(intel_dp); 1471 const u8 *signal_array; 1472 size_t array_size; 1473 int i; 1474 1475 signal_array = index_to_dp_signal_levels; 1476 array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1477 1478 for (i = 0; i < array_size; i++) { 1479 if (signal_array[i] == signal_levels) 1480 return i; 1481 } 1482 1483 drm_WARN(display->drm, 1, 1484 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1485 signal_levels); 1486 1487 return 0; 1488 } 1489 1490 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1491 const struct intel_crtc_state *crtc_state, 1492 int lane) 1493 { 1494 u8 train_set = intel_dp->train_set[lane]; 1495 1496 if (intel_dp_is_uhbr(crtc_state)) { 1497 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1498 } else { 1499 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1500 DP_TRAIN_PRE_EMPHASIS_MASK); 1501 1502 return translate_signal_level(intel_dp, signal_levels); 1503 } 1504 } 1505 1506 int intel_ddi_level(struct intel_encoder *encoder, 1507 const struct intel_crtc_state *crtc_state, 1508 int lane) 1509 { 1510 struct intel_display *display = to_intel_display(encoder); 1511 const struct intel_ddi_buf_trans *trans; 1512 int level, n_entries; 1513 1514 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1515 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1516 return 0; 1517 1518 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1519 level = intel_ddi_hdmi_level(encoder, trans); 1520 else 1521 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1522 lane); 1523 1524 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1525 level = n_entries - 1; 1526 1527 return level; 1528 } 1529 1530 static void 1531 hsw_set_signal_levels(struct intel_encoder *encoder, 1532 const struct intel_crtc_state *crtc_state) 1533 { 1534 struct intel_display *display = to_intel_display(encoder); 1535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1536 int level = intel_ddi_level(encoder, crtc_state, 0); 1537 enum port port = encoder->port; 1538 u32 signal_levels; 1539 1540 if (has_iboost(display)) 1541 skl_ddi_set_iboost(encoder, crtc_state, level); 1542 1543 /* HDMI ignores the rest */ 1544 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1545 return; 1546 1547 signal_levels = DDI_BUF_TRANS_SELECT(level); 1548 1549 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1550 signal_levels); 1551 1552 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1553 intel_dp->DP |= signal_levels; 1554 1555 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1556 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1557 } 1558 1559 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1560 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1561 { 1562 mutex_lock(&display->dpll.lock); 1563 1564 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1565 1566 /* 1567 * "This step and the step before must be 1568 * done with separate register writes." 1569 */ 1570 intel_de_rmw(display, reg, clk_off, 0); 1571 1572 mutex_unlock(&display->dpll.lock); 1573 } 1574 1575 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1576 u32 clk_off) 1577 { 1578 mutex_lock(&display->dpll.lock); 1579 1580 intel_de_rmw(display, reg, 0, clk_off); 1581 1582 mutex_unlock(&display->dpll.lock); 1583 } 1584 1585 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1586 u32 clk_off) 1587 { 1588 return !(intel_de_read(display, reg) & clk_off); 1589 } 1590 1591 static struct intel_dpll * 1592 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1593 u32 clk_sel_mask, u32 clk_sel_shift) 1594 { 1595 enum intel_dpll_id id; 1596 1597 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1598 1599 return intel_get_dpll_by_id(display, id); 1600 } 1601 1602 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1603 const struct intel_crtc_state *crtc_state) 1604 { 1605 struct intel_display *display = to_intel_display(encoder); 1606 const struct intel_dpll *pll = crtc_state->intel_dpll; 1607 enum phy phy = intel_encoder_to_phy(encoder); 1608 1609 if (drm_WARN_ON(display->drm, !pll)) 1610 return; 1611 1612 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1613 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1614 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1615 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1616 } 1617 1618 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1619 { 1620 struct intel_display *display = to_intel_display(encoder); 1621 enum phy phy = intel_encoder_to_phy(encoder); 1622 1623 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1624 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1625 } 1626 1627 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1628 { 1629 struct intel_display *display = to_intel_display(encoder); 1630 enum phy phy = intel_encoder_to_phy(encoder); 1631 1632 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1633 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1634 } 1635 1636 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1637 { 1638 struct intel_display *display = to_intel_display(encoder); 1639 enum phy phy = intel_encoder_to_phy(encoder); 1640 1641 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1642 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1643 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1644 } 1645 1646 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1647 const struct intel_crtc_state *crtc_state) 1648 { 1649 struct intel_display *display = to_intel_display(encoder); 1650 const struct intel_dpll *pll = crtc_state->intel_dpll; 1651 enum phy phy = intel_encoder_to_phy(encoder); 1652 1653 if (drm_WARN_ON(display->drm, !pll)) 1654 return; 1655 1656 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1657 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1658 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1659 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1660 } 1661 1662 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1663 { 1664 struct intel_display *display = to_intel_display(encoder); 1665 enum phy phy = intel_encoder_to_phy(encoder); 1666 1667 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1668 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1669 } 1670 1671 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1672 { 1673 struct intel_display *display = to_intel_display(encoder); 1674 enum phy phy = intel_encoder_to_phy(encoder); 1675 1676 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1677 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1678 } 1679 1680 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1681 { 1682 struct intel_display *display = to_intel_display(encoder); 1683 enum phy phy = intel_encoder_to_phy(encoder); 1684 1685 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1686 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1687 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1688 } 1689 1690 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1691 const struct intel_crtc_state *crtc_state) 1692 { 1693 struct intel_display *display = to_intel_display(encoder); 1694 const struct intel_dpll *pll = crtc_state->intel_dpll; 1695 enum phy phy = intel_encoder_to_phy(encoder); 1696 1697 if (drm_WARN_ON(display->drm, !pll)) 1698 return; 1699 1700 /* 1701 * If we fail this, something went very wrong: first 2 PLLs should be 1702 * used by first 2 phys and last 2 PLLs by last phys 1703 */ 1704 if (drm_WARN_ON(display->drm, 1705 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1706 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1707 return; 1708 1709 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1710 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1711 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1712 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1713 } 1714 1715 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1716 { 1717 struct intel_display *display = to_intel_display(encoder); 1718 enum phy phy = intel_encoder_to_phy(encoder); 1719 1720 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1721 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1722 } 1723 1724 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1725 { 1726 struct intel_display *display = to_intel_display(encoder); 1727 enum phy phy = intel_encoder_to_phy(encoder); 1728 1729 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1730 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1731 } 1732 1733 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1734 { 1735 struct intel_display *display = to_intel_display(encoder); 1736 enum phy phy = intel_encoder_to_phy(encoder); 1737 enum intel_dpll_id id; 1738 u32 val; 1739 1740 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1741 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1742 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1743 id = val; 1744 1745 /* 1746 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1747 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1748 * bit for phy C and D. 1749 */ 1750 if (phy >= PHY_C) 1751 id += DPLL_ID_DG1_DPLL2; 1752 1753 return intel_get_dpll_by_id(display, id); 1754 } 1755 1756 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1757 const struct intel_crtc_state *crtc_state) 1758 { 1759 struct intel_display *display = to_intel_display(encoder); 1760 const struct intel_dpll *pll = crtc_state->intel_dpll; 1761 enum phy phy = intel_encoder_to_phy(encoder); 1762 1763 if (drm_WARN_ON(display->drm, !pll)) 1764 return; 1765 1766 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1767 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1768 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1769 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1770 } 1771 1772 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1773 { 1774 struct intel_display *display = to_intel_display(encoder); 1775 enum phy phy = intel_encoder_to_phy(encoder); 1776 1777 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1778 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1779 } 1780 1781 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1782 { 1783 struct intel_display *display = to_intel_display(encoder); 1784 enum phy phy = intel_encoder_to_phy(encoder); 1785 1786 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1787 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1788 } 1789 1790 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1791 { 1792 struct intel_display *display = to_intel_display(encoder); 1793 enum phy phy = intel_encoder_to_phy(encoder); 1794 1795 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1796 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1797 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1798 } 1799 1800 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1801 const struct intel_crtc_state *crtc_state) 1802 { 1803 struct intel_display *display = to_intel_display(encoder); 1804 const struct intel_dpll *pll = crtc_state->intel_dpll; 1805 enum port port = encoder->port; 1806 1807 if (drm_WARN_ON(display->drm, !pll)) 1808 return; 1809 1810 /* 1811 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1812 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1813 */ 1814 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1815 1816 icl_ddi_combo_enable_clock(encoder, crtc_state); 1817 } 1818 1819 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1820 { 1821 struct intel_display *display = to_intel_display(encoder); 1822 enum port port = encoder->port; 1823 1824 icl_ddi_combo_disable_clock(encoder); 1825 1826 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1827 } 1828 1829 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1830 { 1831 struct intel_display *display = to_intel_display(encoder); 1832 enum port port = encoder->port; 1833 u32 tmp; 1834 1835 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1836 1837 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1838 return false; 1839 1840 return icl_ddi_combo_is_clock_enabled(encoder); 1841 } 1842 1843 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1844 const struct intel_crtc_state *crtc_state) 1845 { 1846 struct intel_display *display = to_intel_display(encoder); 1847 const struct intel_dpll *pll = crtc_state->intel_dpll; 1848 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1849 enum port port = encoder->port; 1850 1851 if (drm_WARN_ON(display->drm, !pll)) 1852 return; 1853 1854 intel_de_write(display, DDI_CLK_SEL(port), 1855 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1856 1857 mutex_lock(&display->dpll.lock); 1858 1859 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1860 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1861 1862 mutex_unlock(&display->dpll.lock); 1863 } 1864 1865 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1866 { 1867 struct intel_display *display = to_intel_display(encoder); 1868 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1869 enum port port = encoder->port; 1870 1871 mutex_lock(&display->dpll.lock); 1872 1873 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1874 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1875 1876 mutex_unlock(&display->dpll.lock); 1877 1878 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1879 } 1880 1881 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1882 { 1883 struct intel_display *display = to_intel_display(encoder); 1884 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1885 enum port port = encoder->port; 1886 u32 tmp; 1887 1888 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1889 1890 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1891 return false; 1892 1893 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1894 1895 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1896 } 1897 1898 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1899 { 1900 struct intel_display *display = to_intel_display(encoder); 1901 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1902 enum port port = encoder->port; 1903 enum intel_dpll_id id; 1904 u32 tmp; 1905 1906 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1907 1908 switch (tmp & DDI_CLK_SEL_MASK) { 1909 case DDI_CLK_SEL_TBT_162: 1910 case DDI_CLK_SEL_TBT_270: 1911 case DDI_CLK_SEL_TBT_540: 1912 case DDI_CLK_SEL_TBT_810: 1913 id = DPLL_ID_ICL_TBTPLL; 1914 break; 1915 case DDI_CLK_SEL_MG: 1916 id = icl_tc_port_to_pll_id(tc_port); 1917 break; 1918 default: 1919 MISSING_CASE(tmp); 1920 fallthrough; 1921 case DDI_CLK_SEL_NONE: 1922 return NULL; 1923 } 1924 1925 return intel_get_dpll_by_id(display, id); 1926 } 1927 1928 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1929 { 1930 struct intel_display *display = to_intel_display(encoder->base.dev); 1931 enum intel_dpll_id id; 1932 1933 switch (encoder->port) { 1934 case PORT_A: 1935 id = DPLL_ID_SKL_DPLL0; 1936 break; 1937 case PORT_B: 1938 id = DPLL_ID_SKL_DPLL1; 1939 break; 1940 case PORT_C: 1941 id = DPLL_ID_SKL_DPLL2; 1942 break; 1943 default: 1944 MISSING_CASE(encoder->port); 1945 return NULL; 1946 } 1947 1948 return intel_get_dpll_by_id(display, id); 1949 } 1950 1951 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1952 const struct intel_crtc_state *crtc_state) 1953 { 1954 struct intel_display *display = to_intel_display(encoder); 1955 const struct intel_dpll *pll = crtc_state->intel_dpll; 1956 enum port port = encoder->port; 1957 1958 if (drm_WARN_ON(display->drm, !pll)) 1959 return; 1960 1961 mutex_lock(&display->dpll.lock); 1962 1963 intel_de_rmw(display, DPLL_CTRL2, 1964 DPLL_CTRL2_DDI_CLK_OFF(port) | 1965 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1966 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1967 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1968 1969 mutex_unlock(&display->dpll.lock); 1970 } 1971 1972 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1973 { 1974 struct intel_display *display = to_intel_display(encoder); 1975 enum port port = encoder->port; 1976 1977 mutex_lock(&display->dpll.lock); 1978 1979 intel_de_rmw(display, DPLL_CTRL2, 1980 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1981 1982 mutex_unlock(&display->dpll.lock); 1983 } 1984 1985 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1986 { 1987 struct intel_display *display = to_intel_display(encoder); 1988 enum port port = encoder->port; 1989 1990 /* 1991 * FIXME Not sure if the override affects both 1992 * the PLL selection and the CLK_OFF bit. 1993 */ 1994 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1995 } 1996 1997 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1998 { 1999 struct intel_display *display = to_intel_display(encoder); 2000 enum port port = encoder->port; 2001 enum intel_dpll_id id; 2002 u32 tmp; 2003 2004 tmp = intel_de_read(display, DPLL_CTRL2); 2005 2006 /* 2007 * FIXME Not sure if the override affects both 2008 * the PLL selection and the CLK_OFF bit. 2009 */ 2010 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2011 return NULL; 2012 2013 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2014 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2015 2016 return intel_get_dpll_by_id(display, id); 2017 } 2018 2019 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2020 const struct intel_crtc_state *crtc_state) 2021 { 2022 struct intel_display *display = to_intel_display(encoder); 2023 const struct intel_dpll *pll = crtc_state->intel_dpll; 2024 enum port port = encoder->port; 2025 2026 if (drm_WARN_ON(display->drm, !pll)) 2027 return; 2028 2029 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2030 } 2031 2032 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2033 { 2034 struct intel_display *display = to_intel_display(encoder); 2035 enum port port = encoder->port; 2036 2037 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2038 } 2039 2040 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2041 { 2042 struct intel_display *display = to_intel_display(encoder); 2043 enum port port = encoder->port; 2044 2045 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2046 } 2047 2048 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2049 { 2050 struct intel_display *display = to_intel_display(encoder); 2051 enum port port = encoder->port; 2052 enum intel_dpll_id id; 2053 u32 tmp; 2054 2055 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2056 2057 switch (tmp & PORT_CLK_SEL_MASK) { 2058 case PORT_CLK_SEL_WRPLL1: 2059 id = DPLL_ID_WRPLL1; 2060 break; 2061 case PORT_CLK_SEL_WRPLL2: 2062 id = DPLL_ID_WRPLL2; 2063 break; 2064 case PORT_CLK_SEL_SPLL: 2065 id = DPLL_ID_SPLL; 2066 break; 2067 case PORT_CLK_SEL_LCPLL_810: 2068 id = DPLL_ID_LCPLL_810; 2069 break; 2070 case PORT_CLK_SEL_LCPLL_1350: 2071 id = DPLL_ID_LCPLL_1350; 2072 break; 2073 case PORT_CLK_SEL_LCPLL_2700: 2074 id = DPLL_ID_LCPLL_2700; 2075 break; 2076 default: 2077 MISSING_CASE(tmp); 2078 fallthrough; 2079 case PORT_CLK_SEL_NONE: 2080 return NULL; 2081 } 2082 2083 return intel_get_dpll_by_id(display, id); 2084 } 2085 2086 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2087 const struct intel_crtc_state *crtc_state) 2088 { 2089 if (encoder->enable_clock) 2090 encoder->enable_clock(encoder, crtc_state); 2091 } 2092 2093 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2094 { 2095 if (encoder->disable_clock) 2096 encoder->disable_clock(encoder); 2097 } 2098 2099 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2100 { 2101 struct intel_display *display = to_intel_display(encoder); 2102 u32 port_mask; 2103 bool ddi_clk_needed; 2104 2105 /* 2106 * In case of DP MST, we sanitize the primary encoder only, not the 2107 * virtual ones. 2108 */ 2109 if (encoder->type == INTEL_OUTPUT_DP_MST) 2110 return; 2111 2112 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2113 u8 pipe_mask; 2114 bool is_mst; 2115 2116 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2117 /* 2118 * In the unlikely case that BIOS enables DP in MST mode, just 2119 * warn since our MST HW readout is incomplete. 2120 */ 2121 if (drm_WARN_ON(display->drm, is_mst)) 2122 return; 2123 } 2124 2125 port_mask = BIT(encoder->port); 2126 ddi_clk_needed = encoder->base.crtc; 2127 2128 if (encoder->type == INTEL_OUTPUT_DSI) { 2129 struct intel_encoder *other_encoder; 2130 2131 port_mask = intel_dsi_encoder_ports(encoder); 2132 /* 2133 * Sanity check that we haven't incorrectly registered another 2134 * encoder using any of the ports of this DSI encoder. 2135 */ 2136 for_each_intel_encoder(display->drm, other_encoder) { 2137 if (other_encoder == encoder) 2138 continue; 2139 2140 if (drm_WARN_ON(display->drm, 2141 port_mask & BIT(other_encoder->port))) 2142 return; 2143 } 2144 /* 2145 * For DSI we keep the ddi clocks gated 2146 * except during enable/disable sequence. 2147 */ 2148 ddi_clk_needed = false; 2149 } 2150 2151 if (ddi_clk_needed || !encoder->is_clock_enabled || 2152 !encoder->is_clock_enabled(encoder)) 2153 return; 2154 2155 drm_dbg_kms(display->drm, 2156 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2157 encoder->base.base.id, encoder->base.name); 2158 2159 encoder->disable_clock(encoder); 2160 } 2161 2162 static void 2163 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2164 enum tc_port tc_port, u32 ln0, u32 ln1) 2165 { 2166 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2167 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2168 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2169 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2170 } 2171 2172 static void 2173 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2174 const struct intel_crtc_state *crtc_state) 2175 { 2176 struct intel_display *display = to_intel_display(crtc_state); 2177 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2178 enum intel_tc_pin_assignment pin_assignment; 2179 u32 ln0, ln1; 2180 u8 width; 2181 2182 if (DISPLAY_VER(display) >= 14) 2183 return; 2184 2185 if (!intel_encoder_is_tc(&dig_port->base) || 2186 intel_tc_port_in_tbt_alt_mode(dig_port)) 2187 return; 2188 2189 if (DISPLAY_VER(display) >= 12) { 2190 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2191 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2192 } else { 2193 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2194 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2195 } 2196 2197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2198 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2199 2200 /* DPPATC */ 2201 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2202 width = crtc_state->lane_count; 2203 2204 switch (pin_assignment) { 2205 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2206 drm_WARN_ON(display->drm, 2207 !intel_tc_port_in_legacy_mode(dig_port)); 2208 if (width == 1) { 2209 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2210 } else { 2211 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2212 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2213 } 2214 break; 2215 case INTEL_TC_PIN_ASSIGNMENT_A: 2216 if (width == 4) { 2217 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2218 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2219 } 2220 break; 2221 case INTEL_TC_PIN_ASSIGNMENT_B: 2222 if (width == 2) { 2223 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2224 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2225 } 2226 break; 2227 case INTEL_TC_PIN_ASSIGNMENT_C: 2228 case INTEL_TC_PIN_ASSIGNMENT_E: 2229 if (width == 1) { 2230 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2231 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2232 } else { 2233 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2234 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2235 } 2236 break; 2237 case INTEL_TC_PIN_ASSIGNMENT_D: 2238 case INTEL_TC_PIN_ASSIGNMENT_F: 2239 if (width == 1) { 2240 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2241 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2242 } else { 2243 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2244 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2245 } 2246 break; 2247 default: 2248 MISSING_CASE(pin_assignment); 2249 } 2250 2251 if (DISPLAY_VER(display) >= 12) { 2252 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2253 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2254 /* WA_14018221282 */ 2255 if (IS_DISPLAY_VER(display, 12, 13)) 2256 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2257 2258 } else { 2259 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2260 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2261 } 2262 } 2263 2264 static enum transcoder 2265 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2266 { 2267 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2268 return crtc_state->mst_master_transcoder; 2269 else 2270 return crtc_state->cpu_transcoder; 2271 } 2272 2273 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2274 const struct intel_crtc_state *crtc_state) 2275 { 2276 struct intel_display *display = to_intel_display(encoder); 2277 2278 if (DISPLAY_VER(display) >= 12) 2279 return TGL_DP_TP_CTL(display, 2280 tgl_dp_tp_transcoder(crtc_state)); 2281 else 2282 return DP_TP_CTL(encoder->port); 2283 } 2284 2285 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2286 const struct intel_crtc_state *crtc_state) 2287 { 2288 struct intel_display *display = to_intel_display(encoder); 2289 2290 if (DISPLAY_VER(display) >= 12) 2291 return TGL_DP_TP_STATUS(display, 2292 tgl_dp_tp_transcoder(crtc_state)); 2293 else 2294 return DP_TP_STATUS(encoder->port); 2295 } 2296 2297 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2298 const struct intel_crtc_state *crtc_state) 2299 { 2300 struct intel_display *display = to_intel_display(encoder); 2301 2302 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2303 DP_TP_STATUS_ACT_SENT); 2304 } 2305 2306 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2307 const struct intel_crtc_state *crtc_state) 2308 { 2309 struct intel_display *display = to_intel_display(encoder); 2310 2311 if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2312 DP_TP_STATUS_ACT_SENT, 1)) 2313 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2314 } 2315 2316 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2317 const struct intel_crtc_state *crtc_state, 2318 bool enable) 2319 { 2320 struct intel_display *display = to_intel_display(intel_dp); 2321 2322 if (!crtc_state->vrr.enable) 2323 return; 2324 2325 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2326 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2327 drm_dbg_kms(display->drm, 2328 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2329 str_enable_disable(enable)); 2330 } 2331 2332 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2333 const struct intel_crtc_state *crtc_state, 2334 bool enable) 2335 { 2336 struct intel_display *display = to_intel_display(intel_dp); 2337 2338 if (!crtc_state->fec_enable) 2339 return; 2340 2341 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2342 enable ? DP_FEC_READY : 0) <= 0) 2343 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2344 str_enabled_disabled(enable)); 2345 2346 if (enable && 2347 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2348 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2349 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2350 } 2351 2352 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2353 { 2354 struct intel_display *display = to_intel_display(aux->drm_dev); 2355 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2356 u8 status = 0; 2357 int ret, err; 2358 2359 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2360 err || (status & mask), 2361 10 * 1000, 200 * 1000, false); 2362 2363 /* Either can be non-zero, but not both */ 2364 ret = ret ?: err; 2365 if (ret) { 2366 drm_dbg_kms(display->drm, 2367 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2368 str_enabled_disabled(enabled), ret, status); 2369 return ret; 2370 } 2371 2372 return 0; 2373 } 2374 2375 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2376 const struct intel_crtc_state *crtc_state, 2377 bool enabled) 2378 { 2379 struct intel_display *display = to_intel_display(encoder); 2380 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2381 int ret; 2382 2383 if (!crtc_state->fec_enable) 2384 return 0; 2385 2386 if (enabled) 2387 ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2388 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2389 else 2390 ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state), 2391 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2392 2393 if (ret) { 2394 drm_err(display->drm, 2395 "Timeout waiting for FEC live state to get %s\n", 2396 str_enabled_disabled(enabled)); 2397 return ret; 2398 } 2399 /* 2400 * At least the Synoptics MST hub doesn't set the detected flag for 2401 * FEC decoding disabling so skip waiting for that. 2402 */ 2403 if (enabled) { 2404 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2405 if (ret) 2406 return ret; 2407 } 2408 2409 return 0; 2410 } 2411 2412 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2413 const struct intel_crtc_state *crtc_state) 2414 { 2415 struct intel_display *display = to_intel_display(encoder); 2416 int i; 2417 int ret; 2418 2419 if (!crtc_state->fec_enable) 2420 return; 2421 2422 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2423 0, DP_TP_CTL_FEC_ENABLE); 2424 2425 if (DISPLAY_VER(display) < 30) 2426 return; 2427 2428 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2429 if (!ret) 2430 return; 2431 2432 for (i = 0; i < 3; i++) { 2433 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2434 2435 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2436 DP_TP_CTL_FEC_ENABLE, 0); 2437 2438 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2439 if (ret) 2440 continue; 2441 2442 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2443 0, DP_TP_CTL_FEC_ENABLE); 2444 2445 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2446 if (!ret) 2447 return; 2448 } 2449 2450 drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); 2451 } 2452 2453 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2454 const struct intel_crtc_state *crtc_state) 2455 { 2456 struct intel_display *display = to_intel_display(encoder); 2457 2458 if (!crtc_state->fec_enable) 2459 return; 2460 2461 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2462 DP_TP_CTL_FEC_ENABLE, 0); 2463 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2464 } 2465 2466 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2467 const struct intel_crtc_state *crtc_state) 2468 { 2469 struct intel_display *display = to_intel_display(encoder); 2470 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2471 2472 if (intel_encoder_is_combo(encoder)) { 2473 enum phy phy = intel_encoder_to_phy(encoder); 2474 2475 intel_combo_phy_power_up_lanes(display, phy, false, 2476 crtc_state->lane_count, 2477 dig_port->lane_reversal); 2478 } 2479 } 2480 2481 /* 2482 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2483 * platforms. 2484 */ 2485 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2486 { 2487 if (DISPLAY_VER(display) > 20) 2488 return ~0; 2489 else if (display->platform.alderlake_p) 2490 return BIT(PIPE_A) | BIT(PIPE_B); 2491 else 2492 return BIT(PIPE_A); 2493 } 2494 2495 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2496 struct intel_crtc_state *pipe_config) 2497 { 2498 struct intel_display *display = to_intel_display(pipe_config); 2499 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2500 enum pipe pipe = crtc->pipe; 2501 u32 dss1; 2502 2503 if (!HAS_MSO(display)) 2504 return; 2505 2506 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2507 2508 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2509 if (!pipe_config->splitter.enable) 2510 return; 2511 2512 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2513 pipe_config->splitter.enable = false; 2514 return; 2515 } 2516 2517 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2518 default: 2519 drm_WARN(display->drm, true, 2520 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2521 fallthrough; 2522 case SPLITTER_CONFIGURATION_2_SEGMENT: 2523 pipe_config->splitter.link_count = 2; 2524 break; 2525 case SPLITTER_CONFIGURATION_4_SEGMENT: 2526 pipe_config->splitter.link_count = 4; 2527 break; 2528 } 2529 2530 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2531 } 2532 2533 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2534 { 2535 struct intel_display *display = to_intel_display(crtc_state); 2536 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2537 enum pipe pipe = crtc->pipe; 2538 u32 dss1 = 0; 2539 2540 if (!HAS_MSO(display)) 2541 return; 2542 2543 if (crtc_state->splitter.enable) { 2544 dss1 |= SPLITTER_ENABLE; 2545 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2546 if (crtc_state->splitter.link_count == 2) 2547 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2548 else 2549 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2550 } 2551 2552 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2553 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2554 OVERLAP_PIXELS_MASK, dss1); 2555 } 2556 2557 static void 2558 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2559 { 2560 struct intel_display *display = to_intel_display(encoder); 2561 enum port port = encoder->port; 2562 i915_reg_t reg; 2563 u32 set_bits, wait_bits; 2564 int ret; 2565 2566 if (DISPLAY_VER(display) < 14) 2567 return; 2568 2569 if (DISPLAY_VER(display) >= 20) { 2570 reg = DDI_BUF_CTL(port); 2571 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2572 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2573 } else { 2574 reg = XELPDP_PORT_BUF_CTL1(display, port); 2575 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2576 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2577 } 2578 2579 intel_de_rmw(display, reg, 0, set_bits); 2580 2581 ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100); 2582 if (ret) { 2583 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2584 port_name(port)); 2585 } 2586 } 2587 2588 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2589 const struct intel_crtc_state *crtc_state) 2590 { 2591 struct intel_display *display = to_intel_display(encoder); 2592 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2593 enum port port = encoder->port; 2594 u32 val = 0; 2595 2596 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2597 2598 if (intel_dp_is_uhbr(crtc_state)) 2599 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2600 else 2601 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2602 2603 if (dig_port->lane_reversal) 2604 val |= XELPDP_PORT_REVERSAL; 2605 2606 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2607 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2608 val); 2609 } 2610 2611 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2612 { 2613 struct intel_display *display = to_intel_display(encoder); 2614 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2615 u32 val; 2616 2617 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2618 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2619 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2620 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2621 } 2622 2623 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2624 struct intel_encoder *encoder, 2625 const struct intel_crtc_state *crtc_state, 2626 const struct drm_connector_state *conn_state) 2627 { 2628 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2629 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2630 bool transparent_mode; 2631 int ret; 2632 2633 intel_dp_set_link_params(intel_dp, 2634 crtc_state->port_clock, 2635 crtc_state->lane_count); 2636 2637 /* 2638 * We only configure what the register value will be here. Actual 2639 * enabling happens during link training farther down. 2640 */ 2641 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2642 2643 /* 2644 * 1. Enable Power Wells 2645 * 2646 * This was handled at the beginning of intel_atomic_commit_tail(), 2647 * before we called down into this function. 2648 */ 2649 2650 /* 2. PMdemand was already set */ 2651 2652 /* 3. Select Thunderbolt */ 2653 mtl_port_buf_ctl_io_selection(encoder); 2654 2655 /* 4. Enable Panel Power if PPS is required */ 2656 intel_pps_on(intel_dp); 2657 2658 /* 5. Enable the port PLL */ 2659 intel_ddi_enable_clock(encoder, crtc_state); 2660 2661 /* 2662 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2663 * Transcoder. 2664 */ 2665 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2666 2667 /* 2668 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2669 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2670 * Transport Select 2671 */ 2672 intel_ddi_config_transcoder_func(encoder, crtc_state); 2673 2674 /* 2675 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2676 */ 2677 intel_ddi_mso_configure(crtc_state); 2678 2679 if (!is_mst) 2680 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2681 2682 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2683 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2684 2685 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2686 if (!is_mst) 2687 intel_dp_sink_enable_decompression(state, 2688 to_intel_connector(conn_state->connector), 2689 crtc_state); 2690 2691 /* 2692 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2693 * in the FEC_CONFIGURATION register to 1 before initiating link 2694 * training 2695 */ 2696 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2697 2698 intel_dp_check_frl_training(intel_dp); 2699 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2700 2701 /* 2702 * 6. The rest of the below are substeps under the bspec's "Enable and 2703 * Train Display Port" step. Note that steps that are specific to 2704 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2705 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2706 * us when active_mst_links==0, so any steps designated for "single 2707 * stream or multi-stream master transcoder" can just be performed 2708 * unconditionally here. 2709 * 2710 * mtl_ddi_prepare_link_retrain() that is called by 2711 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2712 * 6.i and 6.j 2713 * 2714 * 6.k Follow DisplayPort specification training sequence (see notes for 2715 * failure handling) 2716 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2717 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2718 * (timeout after 800 us) 2719 */ 2720 intel_dp_start_link_train(state, intel_dp, crtc_state); 2721 2722 /* 6.n Set DP_TP_CTL link training to Normal */ 2723 if (!is_trans_port_sync_mode(crtc_state)) 2724 intel_dp_stop_link_train(intel_dp, crtc_state); 2725 2726 /* 6.o Configure and enable FEC if needed */ 2727 intel_ddi_enable_fec(encoder, crtc_state); 2728 2729 /* 7.a 128b/132b SST. */ 2730 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2731 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2732 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2733 if (ret < 0) 2734 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2735 } 2736 2737 if (!is_mst) 2738 intel_dsc_dp_pps_write(encoder, crtc_state); 2739 } 2740 2741 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2742 struct intel_encoder *encoder, 2743 const struct intel_crtc_state *crtc_state, 2744 const struct drm_connector_state *conn_state) 2745 { 2746 struct intel_display *display = to_intel_display(encoder); 2747 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2748 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2749 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2750 int ret; 2751 2752 intel_dp_set_link_params(intel_dp, 2753 crtc_state->port_clock, 2754 crtc_state->lane_count); 2755 2756 /* 2757 * We only configure what the register value will be here. Actual 2758 * enabling happens during link training farther down. 2759 */ 2760 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2761 2762 /* 2763 * 1. Enable Power Wells 2764 * 2765 * This was handled at the beginning of intel_atomic_commit_tail(), 2766 * before we called down into this function. 2767 */ 2768 2769 /* 2. Enable Panel Power if PPS is required */ 2770 intel_pps_on(intel_dp); 2771 2772 /* 2773 * 3. For non-TBT Type-C ports, set FIA lane count 2774 * (DFLEXDPSP.DPX4TXLATC) 2775 * 2776 * This was done before tgl_ddi_pre_enable_dp by 2777 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2778 */ 2779 2780 /* 2781 * 4. Enable the port PLL. 2782 * 2783 * The PLL enabling itself was already done before this function by 2784 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2785 * configure the PLL to port mapping here. 2786 */ 2787 intel_ddi_enable_clock(encoder, crtc_state); 2788 2789 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2790 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2791 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2792 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2793 dig_port->ddi_io_power_domain); 2794 } 2795 2796 /* 6. Program DP_MODE */ 2797 icl_program_mg_dp_mode(dig_port, crtc_state); 2798 2799 /* 2800 * 7. The rest of the below are substeps under the bspec's "Enable and 2801 * Train Display Port" step. Note that steps that are specific to 2802 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2803 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2804 * us when active_mst_links==0, so any steps designated for "single 2805 * stream or multi-stream master transcoder" can just be performed 2806 * unconditionally here. 2807 */ 2808 2809 /* 2810 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2811 * Transcoder. 2812 */ 2813 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2814 2815 /* 2816 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2817 * Transport Select 2818 */ 2819 intel_ddi_config_transcoder_func(encoder, crtc_state); 2820 2821 /* 2822 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2823 * selected 2824 * 2825 * This will be handled by the intel_dp_start_link_train() farther 2826 * down this function. 2827 */ 2828 2829 /* 7.e Configure voltage swing and related IO settings */ 2830 encoder->set_signal_levels(encoder, crtc_state); 2831 2832 /* 2833 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2834 * the used lanes of the DDI. 2835 */ 2836 intel_ddi_power_up_lanes(encoder, crtc_state); 2837 2838 /* 2839 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2840 */ 2841 intel_ddi_mso_configure(crtc_state); 2842 2843 if (!is_mst) 2844 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2845 2846 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2847 if (!is_mst) 2848 intel_dp_sink_enable_decompression(state, 2849 to_intel_connector(conn_state->connector), 2850 crtc_state); 2851 /* 2852 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2853 * in the FEC_CONFIGURATION register to 1 before initiating link 2854 * training 2855 */ 2856 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2857 2858 intel_dp_check_frl_training(intel_dp); 2859 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2860 2861 /* 2862 * 7.i Follow DisplayPort specification training sequence (see notes for 2863 * failure handling) 2864 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2865 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2866 * (timeout after 800 us) 2867 */ 2868 intel_dp_start_link_train(state, intel_dp, crtc_state); 2869 2870 /* 7.k Set DP_TP_CTL link training to Normal */ 2871 if (!is_trans_port_sync_mode(crtc_state)) 2872 intel_dp_stop_link_train(intel_dp, crtc_state); 2873 2874 /* 7.l Configure and enable FEC if needed */ 2875 intel_ddi_enable_fec(encoder, crtc_state); 2876 2877 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2878 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2879 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2880 if (ret < 0) 2881 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2882 } 2883 2884 if (!is_mst) 2885 intel_dsc_dp_pps_write(encoder, crtc_state); 2886 } 2887 2888 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2889 struct intel_encoder *encoder, 2890 const struct intel_crtc_state *crtc_state, 2891 const struct drm_connector_state *conn_state) 2892 { 2893 struct intel_display *display = to_intel_display(encoder); 2894 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2895 enum port port = encoder->port; 2896 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2897 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2898 2899 if (DISPLAY_VER(display) < 11) 2900 drm_WARN_ON(display->drm, 2901 is_mst && (port == PORT_A || port == PORT_E)); 2902 else 2903 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2904 2905 intel_dp_set_link_params(intel_dp, 2906 crtc_state->port_clock, 2907 crtc_state->lane_count); 2908 2909 /* 2910 * We only configure what the register value will be here. Actual 2911 * enabling happens during link training farther down. 2912 */ 2913 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2914 2915 intel_pps_on(intel_dp); 2916 2917 intel_ddi_enable_clock(encoder, crtc_state); 2918 2919 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2920 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2921 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2922 dig_port->ddi_io_power_domain); 2923 } 2924 2925 icl_program_mg_dp_mode(dig_port, crtc_state); 2926 2927 if (has_buf_trans_select(display)) 2928 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2929 2930 encoder->set_signal_levels(encoder, crtc_state); 2931 2932 intel_ddi_power_up_lanes(encoder, crtc_state); 2933 2934 if (!is_mst) 2935 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2936 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2937 if (!is_mst) 2938 intel_dp_sink_enable_decompression(state, 2939 to_intel_connector(conn_state->connector), 2940 crtc_state); 2941 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2942 intel_dp_start_link_train(state, intel_dp, crtc_state); 2943 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2944 !is_trans_port_sync_mode(crtc_state)) 2945 intel_dp_stop_link_train(intel_dp, crtc_state); 2946 2947 intel_ddi_enable_fec(encoder, crtc_state); 2948 2949 if (!is_mst) { 2950 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2951 intel_dsc_dp_pps_write(encoder, crtc_state); 2952 } 2953 } 2954 2955 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2956 struct intel_encoder *encoder, 2957 const struct intel_crtc_state *crtc_state, 2958 const struct drm_connector_state *conn_state) 2959 { 2960 struct intel_display *display = to_intel_display(encoder); 2961 2962 if (HAS_DP20(display)) 2963 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2964 crtc_state); 2965 2966 /* Panel replay has to be enabled in sink dpcd before link training. */ 2967 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2968 2969 if (DISPLAY_VER(display) >= 14) 2970 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2971 else if (DISPLAY_VER(display) >= 12) 2972 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2973 else 2974 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2975 2976 /* MST will call a setting of MSA after an allocating of Virtual Channel 2977 * from MST encoder pre_enable callback. 2978 */ 2979 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2980 intel_ddi_set_dp_msa(crtc_state, conn_state); 2981 } 2982 2983 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2984 struct intel_encoder *encoder, 2985 const struct intel_crtc_state *crtc_state, 2986 const struct drm_connector_state *conn_state) 2987 { 2988 struct intel_display *display = to_intel_display(encoder); 2989 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2990 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2991 2992 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2993 intel_ddi_enable_clock(encoder, crtc_state); 2994 2995 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2996 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2997 dig_port->ddi_io_power_domain); 2998 2999 icl_program_mg_dp_mode(dig_port, crtc_state); 3000 3001 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3002 3003 dig_port->set_infoframes(encoder, 3004 crtc_state->has_infoframe, 3005 crtc_state, conn_state); 3006 } 3007 3008 /* 3009 * Note: Also called from the ->pre_enable of the first active MST stream 3010 * encoder on its primary encoder. 3011 * 3012 * When called from DP MST code: 3013 * 3014 * - conn_state will be NULL 3015 * 3016 * - encoder will be the primary encoder (i.e. mst->primary) 3017 * 3018 * - the main connector associated with this port won't be active or linked to a 3019 * crtc 3020 * 3021 * - crtc_state will be the state of the first stream to be activated on this 3022 * port, and it may not be the same stream that will be deactivated last, but 3023 * each stream should have a state that is identical when it comes to the DP 3024 * link parameters. 3025 */ 3026 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3027 struct intel_encoder *encoder, 3028 const struct intel_crtc_state *crtc_state, 3029 const struct drm_connector_state *conn_state) 3030 { 3031 struct intel_display *display = to_intel_display(state); 3032 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3033 enum pipe pipe = crtc->pipe; 3034 3035 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3036 3037 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3038 3039 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3040 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3041 conn_state); 3042 } else { 3043 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3044 3045 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3046 conn_state); 3047 3048 /* FIXME precompute everything properly */ 3049 /* FIXME how do we turn infoframes off again? */ 3050 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3051 dig_port->set_infoframes(encoder, 3052 crtc_state->has_infoframe, 3053 crtc_state, conn_state); 3054 } 3055 } 3056 3057 static void 3058 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3059 { 3060 struct intel_display *display = to_intel_display(encoder); 3061 enum port port = encoder->port; 3062 i915_reg_t reg; 3063 u32 clr_bits, wait_bits; 3064 int ret; 3065 3066 if (DISPLAY_VER(display) < 14) 3067 return; 3068 3069 if (DISPLAY_VER(display) >= 20) { 3070 reg = DDI_BUF_CTL(port); 3071 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3072 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3073 } else { 3074 reg = XELPDP_PORT_BUF_CTL1(display, port); 3075 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3076 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3077 } 3078 3079 intel_de_rmw(display, reg, clr_bits, 0); 3080 3081 ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100); 3082 if (ret) 3083 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3084 port_name(port)); 3085 } 3086 3087 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3088 { 3089 struct intel_display *display = to_intel_display(encoder); 3090 enum port port = encoder->port; 3091 3092 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3093 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3094 3095 intel_wait_ddi_buf_active(encoder); 3096 } 3097 3098 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3099 const struct intel_crtc_state *crtc_state) 3100 { 3101 struct intel_display *display = to_intel_display(encoder); 3102 enum port port = encoder->port; 3103 3104 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3105 3106 if (DISPLAY_VER(display) >= 14) 3107 intel_wait_ddi_buf_idle(display, port); 3108 3109 mtl_ddi_disable_d2d(encoder); 3110 3111 if (intel_crtc_has_dp_encoder(crtc_state)) { 3112 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3113 DP_TP_CTL_ENABLE, 0); 3114 } 3115 3116 intel_ddi_disable_fec(encoder, crtc_state); 3117 3118 if (DISPLAY_VER(display) < 14) 3119 intel_wait_ddi_buf_idle(display, port); 3120 3121 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3122 } 3123 3124 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3125 struct intel_encoder *encoder, 3126 const struct intel_crtc_state *old_crtc_state, 3127 const struct drm_connector_state *old_conn_state) 3128 { 3129 struct intel_display *display = to_intel_display(encoder); 3130 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3131 struct intel_dp *intel_dp = &dig_port->dp; 3132 struct ref_tracker *wakeref; 3133 bool is_mst = intel_crtc_has_type(old_crtc_state, 3134 INTEL_OUTPUT_DP_MST); 3135 3136 if (!is_mst) 3137 intel_dp_set_infoframes(encoder, false, 3138 old_crtc_state, old_conn_state); 3139 3140 /* 3141 * Power down sink before disabling the port, otherwise we end 3142 * up getting interrupts from the sink on detecting link loss. 3143 */ 3144 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3145 3146 if (DISPLAY_VER(display) >= 12) { 3147 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3148 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3149 3150 intel_de_rmw(display, 3151 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3152 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3153 0); 3154 } 3155 } else { 3156 if (!is_mst) 3157 intel_ddi_disable_transcoder_clock(old_crtc_state); 3158 } 3159 3160 intel_ddi_buf_disable(encoder, old_crtc_state); 3161 3162 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3163 3164 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3165 3166 /* 3167 * From TGL spec: "If single stream or multi-stream master transcoder: 3168 * Configure Transcoder Clock select to direct no clock to the 3169 * transcoder" 3170 */ 3171 if (DISPLAY_VER(display) >= 12) 3172 intel_ddi_disable_transcoder_clock(old_crtc_state); 3173 3174 intel_pps_vdd_on(intel_dp); 3175 intel_pps_off(intel_dp); 3176 3177 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3178 3179 if (wakeref) 3180 intel_display_power_put(display, 3181 dig_port->ddi_io_power_domain, 3182 wakeref); 3183 3184 intel_ddi_disable_clock(encoder); 3185 3186 /* De-select Thunderbolt */ 3187 if (DISPLAY_VER(display) >= 14) 3188 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3189 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3190 } 3191 3192 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3193 struct intel_encoder *encoder, 3194 const struct intel_crtc_state *old_crtc_state, 3195 const struct drm_connector_state *old_conn_state) 3196 { 3197 struct intel_display *display = to_intel_display(encoder); 3198 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3199 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3200 struct ref_tracker *wakeref; 3201 3202 dig_port->set_infoframes(encoder, false, 3203 old_crtc_state, old_conn_state); 3204 3205 if (DISPLAY_VER(display) < 12) 3206 intel_ddi_disable_transcoder_clock(old_crtc_state); 3207 3208 intel_ddi_buf_disable(encoder, old_crtc_state); 3209 3210 if (DISPLAY_VER(display) >= 12) 3211 intel_ddi_disable_transcoder_clock(old_crtc_state); 3212 3213 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3214 if (wakeref) 3215 intel_display_power_put(display, 3216 dig_port->ddi_io_power_domain, 3217 wakeref); 3218 3219 intel_ddi_disable_clock(encoder); 3220 3221 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3222 } 3223 3224 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3225 struct intel_encoder *encoder, 3226 const struct intel_crtc_state *old_crtc_state, 3227 const struct drm_connector_state *old_conn_state) 3228 { 3229 struct intel_display *display = to_intel_display(encoder); 3230 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3231 struct intel_crtc *pipe_crtc; 3232 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3233 int i; 3234 3235 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3236 const struct intel_crtc_state *old_pipe_crtc_state = 3237 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3238 3239 intel_crtc_vblank_off(old_pipe_crtc_state); 3240 } 3241 3242 intel_disable_transcoder(old_crtc_state); 3243 3244 /* 128b/132b SST */ 3245 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3246 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3247 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3248 3249 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3250 3251 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3252 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3253 3254 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3255 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3256 } 3257 3258 intel_vrr_transcoder_disable(old_crtc_state); 3259 3260 intel_ddi_disable_transcoder_func(old_crtc_state); 3261 3262 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3263 const struct intel_crtc_state *old_pipe_crtc_state = 3264 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3265 3266 intel_dsc_disable(old_pipe_crtc_state); 3267 3268 if (DISPLAY_VER(display) >= 9) 3269 skl_scaler_disable(old_pipe_crtc_state); 3270 else 3271 ilk_pfit_disable(old_pipe_crtc_state); 3272 } 3273 } 3274 3275 /* 3276 * Note: Also called from the ->post_disable of the last active MST stream 3277 * encoder on its primary encoder. See also the comment for 3278 * intel_ddi_pre_enable(). 3279 */ 3280 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3281 struct intel_encoder *encoder, 3282 const struct intel_crtc_state *old_crtc_state, 3283 const struct drm_connector_state *old_conn_state) 3284 { 3285 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3286 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3287 old_conn_state); 3288 3289 /* 3290 * When called from DP MST code: 3291 * - old_conn_state will be NULL 3292 * - encoder will be the main encoder (ie. mst->primary) 3293 * - the main connector associated with this port 3294 * won't be active or linked to a crtc 3295 * - old_crtc_state will be the state of the last stream to 3296 * be deactivated on this port, and it may not be the same 3297 * stream that was activated last, but each stream 3298 * should have a state that is identical when it comes to 3299 * the DP link parameters 3300 */ 3301 3302 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3303 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3304 old_conn_state); 3305 else 3306 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3307 old_conn_state); 3308 } 3309 3310 /* 3311 * Note: Also called from the ->post_pll_disable of the last active MST stream 3312 * encoder on its primary encoder. See also the comment for 3313 * intel_ddi_pre_enable(). 3314 */ 3315 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3316 struct intel_encoder *encoder, 3317 const struct intel_crtc_state *old_crtc_state, 3318 const struct drm_connector_state *old_conn_state) 3319 { 3320 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3321 3322 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3323 3324 if (intel_encoder_is_tc(encoder)) 3325 intel_tc_port_put_link(dig_port); 3326 } 3327 3328 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3329 struct intel_encoder *encoder, 3330 const struct intel_crtc_state *crtc_state) 3331 { 3332 const struct drm_connector_state *conn_state; 3333 struct drm_connector *conn; 3334 int i; 3335 3336 if (!crtc_state->sync_mode_slaves_mask) 3337 return; 3338 3339 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3340 struct intel_encoder *slave_encoder = 3341 to_intel_encoder(conn_state->best_encoder); 3342 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3343 const struct intel_crtc_state *slave_crtc_state; 3344 3345 if (!slave_crtc) 3346 continue; 3347 3348 slave_crtc_state = 3349 intel_atomic_get_new_crtc_state(state, slave_crtc); 3350 3351 if (slave_crtc_state->master_transcoder != 3352 crtc_state->cpu_transcoder) 3353 continue; 3354 3355 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3356 slave_crtc_state); 3357 } 3358 3359 usleep_range(200, 400); 3360 3361 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3362 crtc_state); 3363 } 3364 3365 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3366 struct intel_encoder *encoder, 3367 const struct intel_crtc_state *crtc_state, 3368 const struct drm_connector_state *conn_state) 3369 { 3370 struct intel_display *display = to_intel_display(encoder); 3371 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3372 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3373 enum port port = encoder->port; 3374 3375 if (port == PORT_A && DISPLAY_VER(display) < 9) 3376 intel_dp_stop_link_train(intel_dp, crtc_state); 3377 3378 drm_connector_update_privacy_screen(conn_state); 3379 intel_edp_backlight_on(crtc_state, conn_state); 3380 3381 intel_panel_prepare(crtc_state, conn_state); 3382 3383 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3384 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3385 3386 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3387 } 3388 3389 static i915_reg_t 3390 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3391 { 3392 static const enum transcoder trans[] = { 3393 [PORT_A] = TRANSCODER_EDP, 3394 [PORT_B] = TRANSCODER_A, 3395 [PORT_C] = TRANSCODER_B, 3396 [PORT_D] = TRANSCODER_C, 3397 [PORT_E] = TRANSCODER_A, 3398 }; 3399 3400 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3401 3402 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3403 port = PORT_A; 3404 3405 return CHICKEN_TRANS(display, trans[port]); 3406 } 3407 3408 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3409 struct intel_encoder *encoder, 3410 const struct intel_crtc_state *crtc_state, 3411 const struct drm_connector_state *conn_state) 3412 { 3413 struct intel_display *display = to_intel_display(encoder); 3414 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3415 struct drm_connector *connector = conn_state->connector; 3416 enum port port = encoder->port; 3417 u32 buf_ctl = 0; 3418 3419 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3420 crtc_state->hdmi_high_tmds_clock_ratio, 3421 crtc_state->hdmi_scrambling)) 3422 drm_dbg_kms(display->drm, 3423 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3424 connector->base.id, connector->name); 3425 3426 if (has_buf_trans_select(display)) 3427 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3428 3429 /* e. Enable D2D Link for C10/C20 Phy */ 3430 mtl_ddi_enable_d2d(encoder); 3431 3432 encoder->set_signal_levels(encoder, crtc_state); 3433 3434 /* Display WA #1143: skl,kbl,cfl */ 3435 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3436 /* 3437 * For some reason these chicken bits have been 3438 * stuffed into a transcoder register, event though 3439 * the bits affect a specific DDI port rather than 3440 * a specific transcoder. 3441 */ 3442 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3443 u32 val; 3444 3445 val = intel_de_read(display, reg); 3446 3447 if (port == PORT_E) 3448 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3449 DDIE_TRAINING_OVERRIDE_VALUE; 3450 else 3451 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3452 DDI_TRAINING_OVERRIDE_VALUE; 3453 3454 intel_de_write(display, reg, val); 3455 intel_de_posting_read(display, reg); 3456 3457 udelay(1); 3458 3459 if (port == PORT_E) 3460 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3461 DDIE_TRAINING_OVERRIDE_VALUE); 3462 else 3463 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3464 DDI_TRAINING_OVERRIDE_VALUE); 3465 3466 intel_de_write(display, reg, val); 3467 } 3468 3469 intel_ddi_power_up_lanes(encoder, crtc_state); 3470 3471 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3472 * are ignored so nothing special needs to be done besides 3473 * enabling the port. 3474 * 3475 * On ADL_P the PHY link rate and lane count must be programmed but 3476 * these are both 0 for HDMI. 3477 * 3478 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3479 * is filled with lane count, already set in the crtc_state. 3480 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3481 */ 3482 if (dig_port->lane_reversal) 3483 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3484 if (dig_port->ddi_a_4_lanes) 3485 buf_ctl |= DDI_A_4_LANES; 3486 3487 if (DISPLAY_VER(display) >= 14) { 3488 u32 port_buf = 0; 3489 3490 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3491 3492 if (dig_port->lane_reversal) 3493 port_buf |= XELPDP_PORT_REVERSAL; 3494 3495 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3496 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3497 3498 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3499 3500 if (DISPLAY_VER(display) >= 20) 3501 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3502 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3503 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3504 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3505 } 3506 3507 intel_ddi_buf_enable(encoder, buf_ctl); 3508 } 3509 3510 static void intel_ddi_enable(struct intel_atomic_state *state, 3511 struct intel_encoder *encoder, 3512 const struct intel_crtc_state *crtc_state, 3513 const struct drm_connector_state *conn_state) 3514 { 3515 struct intel_display *display = to_intel_display(encoder); 3516 struct intel_crtc *pipe_crtc; 3517 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3518 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3519 int i; 3520 3521 /* 128b/132b SST */ 3522 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3523 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3524 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3525 3526 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3527 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3528 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3529 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3530 } 3531 3532 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3533 3534 intel_vrr_transcoder_enable(crtc_state); 3535 3536 /* 128b/132b SST */ 3537 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3538 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3539 3540 intel_ddi_clear_act_sent(encoder, crtc_state); 3541 3542 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3543 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3544 3545 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3546 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3547 } 3548 3549 intel_enable_transcoder(crtc_state); 3550 3551 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3552 3553 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3554 const struct intel_crtc_state *pipe_crtc_state = 3555 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3556 3557 intel_crtc_vblank_on(pipe_crtc_state); 3558 } 3559 3560 if (is_hdmi) 3561 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3562 else 3563 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3564 3565 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3566 3567 } 3568 3569 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3570 struct intel_encoder *encoder, 3571 const struct intel_crtc_state *old_crtc_state, 3572 const struct drm_connector_state *old_conn_state) 3573 { 3574 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3575 struct intel_connector *connector = 3576 to_intel_connector(old_conn_state->connector); 3577 3578 intel_dp->link.active = false; 3579 3580 intel_panel_unprepare(old_conn_state); 3581 intel_psr_disable(intel_dp, old_crtc_state); 3582 intel_alpm_disable(intel_dp); 3583 intel_edp_backlight_off(old_conn_state); 3584 /* Disable the decompression in DP Sink */ 3585 intel_dp_sink_disable_decompression(state, 3586 connector, old_crtc_state); 3587 /* Disable Ignore_MSA bit in DP Sink */ 3588 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3589 false); 3590 } 3591 3592 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3593 struct intel_encoder *encoder, 3594 const struct intel_crtc_state *old_crtc_state, 3595 const struct drm_connector_state *old_conn_state) 3596 { 3597 struct intel_display *display = to_intel_display(encoder); 3598 struct drm_connector *connector = old_conn_state->connector; 3599 3600 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3601 false, false)) 3602 drm_dbg_kms(display->drm, 3603 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3604 connector->base.id, connector->name); 3605 } 3606 3607 static void intel_ddi_disable(struct intel_atomic_state *state, 3608 struct intel_encoder *encoder, 3609 const struct intel_crtc_state *old_crtc_state, 3610 const struct drm_connector_state *old_conn_state) 3611 { 3612 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3613 3614 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3615 3616 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3617 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3618 old_conn_state); 3619 else 3620 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3621 old_conn_state); 3622 } 3623 3624 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3625 struct intel_encoder *encoder, 3626 const struct intel_crtc_state *crtc_state, 3627 const struct drm_connector_state *conn_state) 3628 { 3629 intel_ddi_set_dp_msa(crtc_state, conn_state); 3630 3631 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3632 3633 intel_backlight_update(state, encoder, crtc_state, conn_state); 3634 drm_connector_update_privacy_screen(conn_state); 3635 } 3636 3637 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3638 const struct intel_crtc_state *crtc_state, 3639 const struct drm_connector_state *conn_state) 3640 { 3641 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3642 } 3643 3644 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3645 struct intel_encoder *encoder, 3646 const struct intel_crtc_state *crtc_state, 3647 const struct drm_connector_state *conn_state) 3648 { 3649 3650 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3651 !intel_encoder_is_mst(encoder)) 3652 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3653 conn_state); 3654 3655 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3656 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3657 conn_state); 3658 3659 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3660 } 3661 3662 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3663 struct intel_encoder *encoder, 3664 struct intel_crtc *crtc) 3665 { 3666 struct intel_display *display = to_intel_display(encoder); 3667 const struct intel_crtc_state *crtc_state = 3668 intel_atomic_get_new_crtc_state(state, crtc); 3669 struct intel_crtc *pipe_crtc; 3670 3671 /* FIXME: Add NVL+ and DG2 pll_mgr */ 3672 if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) 3673 return; 3674 3675 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3676 intel_crtc_joined_pipe_mask(crtc_state)) 3677 intel_dpll_update_active(state, pipe_crtc, encoder); 3678 } 3679 3680 /* 3681 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3682 * encoder on its primary encoder. See also the comment for 3683 * intel_ddi_pre_enable(). 3684 */ 3685 static void 3686 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3687 struct intel_encoder *encoder, 3688 const struct intel_crtc_state *crtc_state, 3689 const struct drm_connector_state *conn_state) 3690 { 3691 struct intel_display *display = to_intel_display(encoder); 3692 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3693 bool is_tc_port = intel_encoder_is_tc(encoder); 3694 3695 if (is_tc_port) { 3696 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3697 3698 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3699 intel_ddi_update_active_dpll(state, encoder, crtc); 3700 } 3701 3702 main_link_aux_power_domain_get(dig_port, crtc_state); 3703 3704 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3705 /* 3706 * Program the lane count for static/dynamic connections on 3707 * Type-C ports. Skip this step for TBT. 3708 */ 3709 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3710 else if (display->platform.geminilake || display->platform.broxton) 3711 bxt_dpio_phy_set_lane_optim_mask(encoder, 3712 crtc_state->lane_lat_optim_mask); 3713 } 3714 3715 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3716 { 3717 struct intel_display *display = to_intel_display(encoder); 3718 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3719 int ln; 3720 3721 for (ln = 0; ln < 2; ln++) 3722 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3723 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3724 } 3725 3726 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3727 const struct intel_crtc_state *crtc_state) 3728 { 3729 struct intel_display *display = to_intel_display(crtc_state); 3730 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3731 struct intel_encoder *encoder = &dig_port->base; 3732 u32 dp_tp_ctl; 3733 3734 /* 3735 * TODO: To train with only a different voltage swing entry is not 3736 * necessary disable and enable port 3737 */ 3738 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3739 3740 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3741 3742 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3743 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3744 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3745 intel_dp_is_uhbr(crtc_state)) { 3746 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3747 } else { 3748 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3749 if (crtc_state->enhanced_framing) 3750 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3751 } 3752 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3753 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3754 3755 /* 6.f Enable D2D Link */ 3756 mtl_ddi_enable_d2d(encoder); 3757 3758 /* 6.g Configure voltage swing and related IO settings */ 3759 encoder->set_signal_levels(encoder, crtc_state); 3760 3761 /* 6.h Configure PORT_BUF_CTL1 */ 3762 mtl_port_buf_ctl_program(encoder, crtc_state); 3763 3764 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3765 if (DISPLAY_VER(display) >= 20) 3766 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3767 3768 intel_ddi_buf_enable(encoder, intel_dp->DP); 3769 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3770 3771 /* 3772 * 6.k If AUX-Less ALPM is going to be enabled: 3773 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3774 */ 3775 intel_alpm_port_configure(intel_dp, crtc_state); 3776 3777 /* 3778 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3779 * register 3780 */ 3781 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3782 } 3783 3784 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3785 const struct intel_crtc_state *crtc_state) 3786 { 3787 struct intel_display *display = to_intel_display(intel_dp); 3788 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3789 struct intel_encoder *encoder = &dig_port->base; 3790 u32 dp_tp_ctl; 3791 3792 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3793 3794 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3795 3796 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3797 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3798 intel_dp_is_uhbr(crtc_state)) { 3799 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3800 } else { 3801 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3802 if (crtc_state->enhanced_framing) 3803 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3804 } 3805 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3806 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3807 3808 if (display->platform.alderlake_p && 3809 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3810 adlp_tbt_to_dp_alt_switch_wa(encoder); 3811 3812 intel_ddi_buf_enable(encoder, intel_dp->DP); 3813 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3814 } 3815 3816 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3817 const struct intel_crtc_state *crtc_state, 3818 u8 dp_train_pat) 3819 { 3820 struct intel_display *display = to_intel_display(intel_dp); 3821 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3822 u32 temp; 3823 3824 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3825 3826 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3827 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3828 case DP_TRAINING_PATTERN_DISABLE: 3829 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3830 break; 3831 case DP_TRAINING_PATTERN_1: 3832 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3833 break; 3834 case DP_TRAINING_PATTERN_2: 3835 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3836 break; 3837 case DP_TRAINING_PATTERN_3: 3838 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3839 break; 3840 case DP_TRAINING_PATTERN_4: 3841 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3842 break; 3843 } 3844 3845 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3846 } 3847 3848 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3849 const struct intel_crtc_state *crtc_state) 3850 { 3851 struct intel_display *display = to_intel_display(intel_dp); 3852 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3853 enum port port = encoder->port; 3854 3855 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3856 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3857 3858 /* 3859 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3860 * reason we need to set idle transmission mode is to work around a HW 3861 * issue where we enable the pipe while not in idle link-training mode. 3862 * In this case there is requirement to wait for a minimum number of 3863 * idle patterns to be sent. 3864 */ 3865 if (port == PORT_A && DISPLAY_VER(display) < 12) 3866 return; 3867 3868 if (intel_de_wait_for_set_ms(display, 3869 dp_tp_status_reg(encoder, crtc_state), 3870 DP_TP_STATUS_IDLE_DONE, 2)) 3871 drm_err(display->drm, 3872 "Timed out waiting for DP idle patterns\n"); 3873 } 3874 3875 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3876 enum transcoder cpu_transcoder) 3877 { 3878 if (cpu_transcoder == TRANSCODER_EDP) 3879 return false; 3880 3881 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3882 return false; 3883 3884 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3885 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3886 } 3887 3888 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3889 { 3890 if (crtc_state->port_clock > 594000) 3891 return 2; 3892 else 3893 return 0; 3894 } 3895 3896 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3897 { 3898 if (crtc_state->port_clock > 594000) 3899 return 3; 3900 else 3901 return 0; 3902 } 3903 3904 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3905 { 3906 if (crtc_state->port_clock > 594000) 3907 return 1; 3908 else 3909 return 0; 3910 } 3911 3912 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3913 { 3914 struct intel_display *display = to_intel_display(crtc_state); 3915 3916 if (DISPLAY_VER(display) >= 14) 3917 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3918 else if (DISPLAY_VER(display) >= 12) 3919 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3920 else if (display->platform.jasperlake || display->platform.elkhartlake) 3921 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3922 else if (DISPLAY_VER(display) >= 11) 3923 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3924 } 3925 3926 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3927 enum transcoder cpu_transcoder) 3928 { 3929 u32 master_select; 3930 3931 if (DISPLAY_VER(display) >= 11) { 3932 u32 ctl2 = intel_de_read(display, 3933 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3934 3935 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3936 return INVALID_TRANSCODER; 3937 3938 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3939 } else { 3940 u32 ctl = intel_de_read(display, 3941 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3942 3943 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3944 return INVALID_TRANSCODER; 3945 3946 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3947 } 3948 3949 if (master_select == 0) 3950 return TRANSCODER_EDP; 3951 else 3952 return master_select - 1; 3953 } 3954 3955 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3956 { 3957 struct intel_display *display = to_intel_display(crtc_state); 3958 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3959 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3960 enum transcoder cpu_transcoder; 3961 3962 crtc_state->master_transcoder = 3963 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3964 3965 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3966 enum intel_display_power_domain power_domain; 3967 struct ref_tracker *trans_wakeref; 3968 3969 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3970 trans_wakeref = intel_display_power_get_if_enabled(display, 3971 power_domain); 3972 3973 if (!trans_wakeref) 3974 continue; 3975 3976 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3977 crtc_state->cpu_transcoder) 3978 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3979 3980 intel_display_power_put(display, power_domain, trans_wakeref); 3981 } 3982 3983 drm_WARN_ON(display->drm, 3984 crtc_state->master_transcoder != INVALID_TRANSCODER && 3985 crtc_state->sync_mode_slaves_mask); 3986 } 3987 3988 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3989 struct intel_crtc_state *crtc_state, 3990 u32 ddi_func_ctl) 3991 { 3992 struct intel_display *display = to_intel_display(encoder); 3993 3994 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3995 if (DISPLAY_VER(display) >= 14) 3996 crtc_state->lane_count = 3997 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3998 else 3999 crtc_state->lane_count = 4; 4000 } 4001 4002 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4003 struct intel_crtc_state *crtc_state, 4004 u32 ddi_func_ctl) 4005 { 4006 crtc_state->has_hdmi_sink = true; 4007 4008 crtc_state->infoframes.enable |= 4009 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4010 4011 if (crtc_state->infoframes.enable) 4012 crtc_state->has_infoframe = true; 4013 4014 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4015 crtc_state->hdmi_scrambling = true; 4016 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4017 crtc_state->hdmi_high_tmds_clock_ratio = true; 4018 4019 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4020 } 4021 4022 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4023 struct intel_crtc_state *crtc_state, 4024 u32 ddi_func_ctl) 4025 { 4026 struct intel_display *display = to_intel_display(encoder); 4027 4028 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4029 crtc_state->enhanced_framing = 4030 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4031 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4032 } 4033 4034 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4035 struct intel_crtc_state *crtc_state, 4036 u32 ddi_func_ctl) 4037 { 4038 struct intel_display *display = to_intel_display(encoder); 4039 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4040 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4041 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4042 4043 if (encoder->type == INTEL_OUTPUT_EDP) 4044 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4045 else 4046 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4047 crtc_state->lane_count = 4048 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4049 4050 if (DISPLAY_VER(display) >= 12 && 4051 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4052 crtc_state->mst_master_transcoder = 4053 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4054 4055 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4056 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4057 4058 crtc_state->enhanced_framing = 4059 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4060 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4061 4062 if (DISPLAY_VER(display) >= 11) 4063 crtc_state->fec_enable = 4064 intel_de_read(display, 4065 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4066 4067 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4068 crtc_state->infoframes.enable |= 4069 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4070 else 4071 crtc_state->infoframes.enable |= 4072 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4073 } 4074 4075 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4076 struct intel_crtc_state *crtc_state, 4077 u32 ddi_func_ctl) 4078 { 4079 struct intel_display *display = to_intel_display(encoder); 4080 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4081 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4082 4083 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4084 crtc_state->lane_count = 4085 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4086 4087 if (DISPLAY_VER(display) >= 12) 4088 crtc_state->mst_master_transcoder = 4089 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4090 4091 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4092 4093 if (DISPLAY_VER(display) >= 11) 4094 crtc_state->fec_enable = 4095 intel_de_read(display, 4096 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4097 4098 crtc_state->infoframes.enable |= 4099 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4100 } 4101 4102 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4103 struct intel_crtc_state *pipe_config) 4104 { 4105 struct intel_display *display = to_intel_display(encoder); 4106 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4107 u32 ddi_func_ctl, ddi_mode, flags = 0; 4108 4109 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4110 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4111 flags |= DRM_MODE_FLAG_PHSYNC; 4112 else 4113 flags |= DRM_MODE_FLAG_NHSYNC; 4114 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4115 flags |= DRM_MODE_FLAG_PVSYNC; 4116 else 4117 flags |= DRM_MODE_FLAG_NVSYNC; 4118 4119 pipe_config->hw.adjusted_mode.flags |= flags; 4120 4121 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4122 case TRANS_DDI_BPC_6: 4123 pipe_config->pipe_bpp = 18; 4124 break; 4125 case TRANS_DDI_BPC_8: 4126 pipe_config->pipe_bpp = 24; 4127 break; 4128 case TRANS_DDI_BPC_10: 4129 pipe_config->pipe_bpp = 30; 4130 break; 4131 case TRANS_DDI_BPC_12: 4132 pipe_config->pipe_bpp = 36; 4133 break; 4134 default: 4135 break; 4136 } 4137 4138 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4139 4140 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4141 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4142 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4143 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4144 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4145 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4146 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4147 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4148 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4149 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4150 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4151 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4152 4153 /* 4154 * If this is true, we know we're being called from mst stream 4155 * encoder's ->get_config(). 4156 */ 4157 if (intel_dp_mst_active_streams(intel_dp)) 4158 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4159 else 4160 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4161 } 4162 } 4163 4164 /* 4165 * Note: Also called from the ->get_config of the MST stream encoders on their 4166 * primary encoder, via the platform specific hooks here. See also the comment 4167 * for intel_ddi_pre_enable(). 4168 */ 4169 static void intel_ddi_get_config(struct intel_encoder *encoder, 4170 struct intel_crtc_state *pipe_config) 4171 { 4172 struct intel_display *display = to_intel_display(encoder); 4173 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4174 4175 /* XXX: DSI transcoder paranoia */ 4176 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4177 return; 4178 4179 intel_ddi_read_func_ctl(encoder, pipe_config); 4180 4181 intel_ddi_mso_get_config(encoder, pipe_config); 4182 4183 pipe_config->has_audio = 4184 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4185 4186 if (encoder->type == INTEL_OUTPUT_EDP) 4187 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4188 4189 ddi_dotclock_get(pipe_config); 4190 4191 if (display->platform.geminilake || display->platform.broxton) 4192 pipe_config->lane_lat_optim_mask = 4193 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4194 4195 intel_ddi_compute_min_voltage_level(pipe_config); 4196 4197 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4198 4199 intel_read_infoframe(encoder, pipe_config, 4200 HDMI_INFOFRAME_TYPE_AVI, 4201 &pipe_config->infoframes.avi); 4202 intel_read_infoframe(encoder, pipe_config, 4203 HDMI_INFOFRAME_TYPE_SPD, 4204 &pipe_config->infoframes.spd); 4205 intel_read_infoframe(encoder, pipe_config, 4206 HDMI_INFOFRAME_TYPE_VENDOR, 4207 &pipe_config->infoframes.hdmi); 4208 intel_read_infoframe(encoder, pipe_config, 4209 HDMI_INFOFRAME_TYPE_DRM, 4210 &pipe_config->infoframes.drm); 4211 4212 if (DISPLAY_VER(display) >= 8) 4213 bdw_get_trans_port_sync_config(pipe_config); 4214 4215 intel_psr_get_config(encoder, pipe_config); 4216 4217 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4218 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4219 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4220 4221 intel_audio_codec_get_config(encoder, pipe_config); 4222 } 4223 4224 void intel_ddi_get_clock(struct intel_encoder *encoder, 4225 struct intel_crtc_state *crtc_state, 4226 struct intel_dpll *pll) 4227 { 4228 struct intel_display *display = to_intel_display(encoder); 4229 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4230 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4231 bool pll_active; 4232 4233 if (drm_WARN_ON(display->drm, !pll)) 4234 return; 4235 4236 port_dpll->pll = pll; 4237 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4238 drm_WARN_ON(display->drm, !pll_active); 4239 4240 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4241 4242 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4243 &crtc_state->dpll_hw_state); 4244 } 4245 4246 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4247 { 4248 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4249 } 4250 4251 static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, 4252 struct intel_crtc_state *crtc_state, 4253 enum icl_port_dpll_id port_dpll_id, 4254 enum intel_dpll_id pll_id) 4255 { 4256 struct intel_display *display = to_intel_display(encoder); 4257 struct icl_port_dpll *port_dpll; 4258 struct intel_dpll *pll; 4259 bool pll_active; 4260 4261 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4262 pll = intel_get_dpll_by_id(display, pll_id); 4263 4264 if (drm_WARN_ON(display->drm, !pll)) 4265 return; 4266 4267 port_dpll->pll = pll; 4268 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4269 drm_WARN_ON(display->drm, !pll_active); 4270 4271 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4272 4273 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4274 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4275 else 4276 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4277 &crtc_state->dpll_hw_state); 4278 4279 intel_ddi_get_config(encoder, crtc_state); 4280 } 4281 4282 /* 4283 * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4284 * C20 PHY PLL in the cases of: 4285 * - BMG port A/B 4286 * - PTL port B eDP over TypeC PHY 4287 */ 4288 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4289 struct intel_crtc_state *crtc_state) 4290 { 4291 struct intel_display *display = to_intel_display(encoder); 4292 4293 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4294 mtl_port_to_pll_id(display, encoder->port)); 4295 } 4296 4297 static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, 4298 struct intel_crtc_state *crtc_state) 4299 { 4300 struct intel_display *display = to_intel_display(encoder); 4301 4302 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4303 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4304 DPLL_ID_ICL_TBTPLL); 4305 else 4306 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, 4307 mtl_port_to_pll_id(display, encoder->port)); 4308 } 4309 4310 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4311 struct intel_crtc_state *crtc_state) 4312 { 4313 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4314 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4315 4316 intel_ddi_get_config(encoder, crtc_state); 4317 } 4318 4319 static void adls_ddi_get_config(struct intel_encoder *encoder, 4320 struct intel_crtc_state *crtc_state) 4321 { 4322 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4323 intel_ddi_get_config(encoder, crtc_state); 4324 } 4325 4326 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4327 struct intel_crtc_state *crtc_state) 4328 { 4329 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4330 intel_ddi_get_config(encoder, crtc_state); 4331 } 4332 4333 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4334 struct intel_crtc_state *crtc_state) 4335 { 4336 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4337 intel_ddi_get_config(encoder, crtc_state); 4338 } 4339 4340 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4341 struct intel_crtc_state *crtc_state) 4342 { 4343 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4344 intel_ddi_get_config(encoder, crtc_state); 4345 } 4346 4347 static enum icl_port_dpll_id 4348 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4349 const struct intel_crtc_state *crtc_state) 4350 { 4351 struct intel_display *display = to_intel_display(encoder); 4352 const struct intel_dpll *pll = crtc_state->intel_dpll; 4353 4354 if (drm_WARN_ON(display->drm, !pll)) 4355 return ICL_PORT_DPLL_DEFAULT; 4356 4357 if (icl_ddi_tc_pll_is_tbt(pll)) 4358 return ICL_PORT_DPLL_DEFAULT; 4359 else 4360 return ICL_PORT_DPLL_MG_PHY; 4361 } 4362 4363 enum icl_port_dpll_id 4364 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4365 const struct intel_crtc_state *crtc_state) 4366 { 4367 if (!encoder->port_pll_type) 4368 return ICL_PORT_DPLL_DEFAULT; 4369 4370 return encoder->port_pll_type(encoder, crtc_state); 4371 } 4372 4373 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4374 struct intel_crtc_state *crtc_state, 4375 struct intel_dpll *pll) 4376 { 4377 struct intel_display *display = to_intel_display(encoder); 4378 enum icl_port_dpll_id port_dpll_id; 4379 struct icl_port_dpll *port_dpll; 4380 bool pll_active; 4381 4382 if (drm_WARN_ON(display->drm, !pll)) 4383 return; 4384 4385 if (icl_ddi_tc_pll_is_tbt(pll)) 4386 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4387 else 4388 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4389 4390 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4391 4392 port_dpll->pll = pll; 4393 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4394 drm_WARN_ON(display->drm, !pll_active); 4395 4396 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4397 4398 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4399 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4400 else 4401 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4402 &crtc_state->dpll_hw_state); 4403 } 4404 4405 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4406 struct intel_crtc_state *crtc_state) 4407 { 4408 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4409 intel_ddi_get_config(encoder, crtc_state); 4410 } 4411 4412 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4413 struct intel_crtc_state *crtc_state) 4414 { 4415 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4416 intel_ddi_get_config(encoder, crtc_state); 4417 } 4418 4419 static void skl_ddi_get_config(struct intel_encoder *encoder, 4420 struct intel_crtc_state *crtc_state) 4421 { 4422 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4423 intel_ddi_get_config(encoder, crtc_state); 4424 } 4425 4426 void hsw_ddi_get_config(struct intel_encoder *encoder, 4427 struct intel_crtc_state *crtc_state) 4428 { 4429 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4430 intel_ddi_get_config(encoder, crtc_state); 4431 } 4432 4433 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4434 const struct intel_crtc_state *crtc_state) 4435 { 4436 if (intel_encoder_is_tc(encoder)) 4437 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4438 crtc_state); 4439 4440 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4441 (!crtc_state && intel_encoder_is_dp(encoder))) 4442 intel_dp_sync_state(encoder, crtc_state); 4443 } 4444 4445 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4446 struct intel_crtc_state *crtc_state) 4447 { 4448 struct intel_display *display = to_intel_display(encoder); 4449 bool fastset = true; 4450 4451 if (intel_encoder_is_tc(encoder)) { 4452 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4453 encoder->base.base.id, encoder->base.name); 4454 crtc_state->uapi.mode_changed = true; 4455 fastset = false; 4456 } 4457 4458 if (intel_crtc_has_dp_encoder(crtc_state) && 4459 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4460 fastset = false; 4461 4462 return fastset; 4463 } 4464 4465 static enum intel_output_type 4466 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4467 struct intel_crtc_state *crtc_state, 4468 struct drm_connector_state *conn_state) 4469 { 4470 switch (conn_state->connector->connector_type) { 4471 case DRM_MODE_CONNECTOR_HDMIA: 4472 return INTEL_OUTPUT_HDMI; 4473 case DRM_MODE_CONNECTOR_eDP: 4474 return INTEL_OUTPUT_EDP; 4475 case DRM_MODE_CONNECTOR_DisplayPort: 4476 return INTEL_OUTPUT_DP; 4477 default: 4478 MISSING_CASE(conn_state->connector->connector_type); 4479 return INTEL_OUTPUT_UNUSED; 4480 } 4481 } 4482 4483 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4484 struct intel_crtc_state *pipe_config, 4485 struct drm_connector_state *conn_state) 4486 { 4487 struct intel_display *display = to_intel_display(encoder); 4488 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4489 enum port port = encoder->port; 4490 int ret; 4491 4492 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4493 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4494 4495 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4496 pipe_config->has_hdmi_sink = 4497 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4498 4499 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4500 } else { 4501 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4502 } 4503 4504 if (ret) 4505 return ret; 4506 4507 if (display->platform.haswell && crtc->pipe == PIPE_A && 4508 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4509 pipe_config->pch_pfit.force_thru = 4510 pipe_config->pch_pfit.enabled || 4511 pipe_config->crc_enabled; 4512 4513 if (display->platform.geminilake || display->platform.broxton) 4514 pipe_config->lane_lat_optim_mask = 4515 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4516 4517 intel_ddi_compute_min_voltage_level(pipe_config); 4518 4519 return 0; 4520 } 4521 4522 static bool mode_equal(const struct drm_display_mode *mode1, 4523 const struct drm_display_mode *mode2) 4524 { 4525 return drm_mode_match(mode1, mode2, 4526 DRM_MODE_MATCH_TIMINGS | 4527 DRM_MODE_MATCH_FLAGS | 4528 DRM_MODE_MATCH_3D_FLAGS) && 4529 mode1->clock == mode2->clock; /* we want an exact match */ 4530 } 4531 4532 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4533 const struct intel_link_m_n *m_n_2) 4534 { 4535 return m_n_1->tu == m_n_2->tu && 4536 m_n_1->data_m == m_n_2->data_m && 4537 m_n_1->data_n == m_n_2->data_n && 4538 m_n_1->link_m == m_n_2->link_m && 4539 m_n_1->link_n == m_n_2->link_n; 4540 } 4541 4542 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4543 const struct intel_crtc_state *crtc_state2) 4544 { 4545 /* 4546 * FIXME the modeset sequence is currently wrong and 4547 * can't deal with joiner + port sync at the same time. 4548 */ 4549 return crtc_state1->hw.active && crtc_state2->hw.active && 4550 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4551 crtc_state1->output_types == crtc_state2->output_types && 4552 crtc_state1->output_format == crtc_state2->output_format && 4553 crtc_state1->lane_count == crtc_state2->lane_count && 4554 crtc_state1->port_clock == crtc_state2->port_clock && 4555 mode_equal(&crtc_state1->hw.adjusted_mode, 4556 &crtc_state2->hw.adjusted_mode) && 4557 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4558 } 4559 4560 static u8 4561 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4562 int tile_group_id) 4563 { 4564 struct intel_display *display = to_intel_display(ref_crtc_state); 4565 struct drm_connector *connector; 4566 const struct drm_connector_state *conn_state; 4567 struct intel_atomic_state *state = 4568 to_intel_atomic_state(ref_crtc_state->uapi.state); 4569 u8 transcoders = 0; 4570 int i; 4571 4572 /* 4573 * We don't enable port sync on BDW due to missing w/as and 4574 * due to not having adjusted the modeset sequence appropriately. 4575 * From, xe3lpd onwards we have defeatured this with reference to 4576 * Wa_16024710867 4577 */ 4578 if (!IS_DISPLAY_VER(display, 9, 20)) 4579 return 0; 4580 4581 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4582 return 0; 4583 4584 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4585 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4586 const struct intel_crtc_state *crtc_state; 4587 4588 if (!crtc) 4589 continue; 4590 4591 if (!connector->has_tile || 4592 connector->tile_group->id != 4593 tile_group_id) 4594 continue; 4595 crtc_state = intel_atomic_get_new_crtc_state(state, 4596 crtc); 4597 if (!crtcs_port_sync_compatible(ref_crtc_state, 4598 crtc_state)) 4599 continue; 4600 transcoders |= BIT(crtc_state->cpu_transcoder); 4601 } 4602 4603 return transcoders; 4604 } 4605 4606 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4607 struct intel_crtc_state *crtc_state, 4608 struct drm_connector_state *conn_state) 4609 { 4610 struct intel_display *display = to_intel_display(encoder); 4611 struct drm_connector *connector = conn_state->connector; 4612 u8 port_sync_transcoders = 0; 4613 int ret = 0; 4614 4615 if (intel_crtc_has_dp_encoder(crtc_state)) 4616 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); 4617 4618 if (ret) 4619 return ret; 4620 4621 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4622 encoder->base.base.id, encoder->base.name, 4623 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4624 4625 if (connector->has_tile) 4626 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4627 connector->tile_group->id); 4628 4629 /* 4630 * EDP Transcoders cannot be ensalved 4631 * make them a master always when present 4632 */ 4633 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4634 crtc_state->master_transcoder = TRANSCODER_EDP; 4635 else 4636 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4637 4638 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4639 crtc_state->master_transcoder = INVALID_TRANSCODER; 4640 crtc_state->sync_mode_slaves_mask = 4641 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4642 } 4643 4644 return 0; 4645 } 4646 4647 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4648 { 4649 struct intel_display *display = to_intel_display(encoder->dev); 4650 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4651 4652 intel_dp_encoder_flush_work(encoder); 4653 if (intel_encoder_is_tc(&dig_port->base)) 4654 intel_tc_port_cleanup(dig_port); 4655 intel_display_power_flush_work(display); 4656 4657 drm_encoder_cleanup(encoder); 4658 kfree(dig_port->hdcp.port_data.streams); 4659 kfree(dig_port); 4660 } 4661 4662 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4663 { 4664 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4665 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4666 4667 intel_dp->reset_link_params = true; 4668 intel_dp_invalidate_source_oui(intel_dp); 4669 4670 intel_pps_encoder_reset(intel_dp); 4671 4672 if (intel_encoder_is_tc(&dig_port->base)) 4673 intel_tc_port_init_mode(dig_port); 4674 } 4675 4676 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4677 { 4678 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4679 4680 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4681 4682 return 0; 4683 } 4684 4685 static const struct drm_encoder_funcs intel_ddi_funcs = { 4686 .reset = intel_ddi_encoder_reset, 4687 .destroy = intel_ddi_encoder_destroy, 4688 .late_register = intel_ddi_encoder_late_register, 4689 }; 4690 4691 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4692 { 4693 struct intel_display *display = to_intel_display(dig_port); 4694 struct intel_connector *connector; 4695 enum port port = dig_port->base.port; 4696 4697 connector = intel_connector_alloc(); 4698 if (!connector) 4699 return -ENOMEM; 4700 4701 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4702 if (DISPLAY_VER(display) >= 14) 4703 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4704 else 4705 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4706 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4707 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4708 4709 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4710 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4711 4712 if (!intel_dp_init_connector(dig_port, connector)) { 4713 kfree(connector); 4714 return -EINVAL; 4715 } 4716 4717 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4718 struct drm_privacy_screen *privacy_screen; 4719 4720 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4721 if (!IS_ERR(privacy_screen)) { 4722 drm_connector_attach_privacy_screen_provider(&connector->base, 4723 privacy_screen); 4724 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4725 drm_warn(display->drm, "Error getting privacy-screen\n"); 4726 } 4727 } 4728 4729 return 0; 4730 } 4731 4732 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4733 struct drm_modeset_acquire_ctx *ctx) 4734 { 4735 struct intel_display *display = to_intel_display(encoder); 4736 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4737 struct intel_connector *connector = hdmi->attached_connector; 4738 struct i2c_adapter *ddc = connector->base.ddc; 4739 struct drm_connector_state *conn_state; 4740 struct intel_crtc_state *crtc_state; 4741 struct intel_crtc *crtc; 4742 u8 config; 4743 int ret; 4744 4745 if (connector->base.status != connector_status_connected) 4746 return 0; 4747 4748 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4749 ctx); 4750 if (ret) 4751 return ret; 4752 4753 conn_state = connector->base.state; 4754 4755 crtc = to_intel_crtc(conn_state->crtc); 4756 if (!crtc) 4757 return 0; 4758 4759 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4760 if (ret) 4761 return ret; 4762 4763 crtc_state = to_intel_crtc_state(crtc->base.state); 4764 4765 drm_WARN_ON(display->drm, 4766 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4767 4768 if (!crtc_state->hw.active) 4769 return 0; 4770 4771 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4772 !crtc_state->hdmi_scrambling) 4773 return 0; 4774 4775 if (conn_state->commit && 4776 !try_wait_for_completion(&conn_state->commit->hw_done)) 4777 return 0; 4778 4779 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4780 if (ret < 0) { 4781 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4782 connector->base.base.id, connector->base.name, ret); 4783 return 0; 4784 } 4785 4786 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4787 crtc_state->hdmi_high_tmds_clock_ratio && 4788 !!(config & SCDC_SCRAMBLING_ENABLE) == 4789 crtc_state->hdmi_scrambling) 4790 return 0; 4791 4792 /* 4793 * HDMI 2.0 says that one should not send scrambled data 4794 * prior to configuring the sink scrambling, and that 4795 * TMDS clock/data transmission should be suspended when 4796 * changing the TMDS clock rate in the sink. So let's 4797 * just do a full modeset here, even though some sinks 4798 * would be perfectly happy if were to just reconfigure 4799 * the SCDC settings on the fly. 4800 */ 4801 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4802 } 4803 4804 static void intel_ddi_link_check(struct intel_encoder *encoder) 4805 { 4806 struct intel_display *display = to_intel_display(encoder); 4807 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4808 4809 /* TODO: Move checking the HDMI link state here as well. */ 4810 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4811 4812 intel_dp_link_check(encoder); 4813 } 4814 4815 static enum intel_hotplug_state 4816 intel_ddi_hotplug(struct intel_encoder *encoder, 4817 struct intel_connector *connector) 4818 { 4819 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4820 struct intel_dp *intel_dp = &dig_port->dp; 4821 bool is_tc = intel_encoder_is_tc(encoder); 4822 struct drm_modeset_acquire_ctx ctx; 4823 enum intel_hotplug_state state; 4824 int ret; 4825 4826 if (intel_dp_test_phy(intel_dp)) 4827 return INTEL_HOTPLUG_UNCHANGED; 4828 4829 state = intel_encoder_hotplug(encoder, connector); 4830 4831 if (!intel_tc_port_link_reset(dig_port)) { 4832 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4833 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4834 ret = intel_hdmi_reset_link(encoder, &ctx); 4835 drm_WARN_ON(encoder->base.dev, ret); 4836 } else { 4837 intel_dp_check_link_state(intel_dp); 4838 } 4839 } 4840 4841 /* 4842 * Unpowered type-c dongles can take some time to boot and be 4843 * responsible, so here giving some time to those dongles to power up 4844 * and then retrying the probe. 4845 * 4846 * On many platforms the HDMI live state signal is known to be 4847 * unreliable, so we can't use it to detect if a sink is connected or 4848 * not. Instead we detect if it's connected based on whether we can 4849 * read the EDID or not. That in turn has a problem during disconnect, 4850 * since the HPD interrupt may be raised before the DDC lines get 4851 * disconnected (due to how the required length of DDC vs. HPD 4852 * connector pins are specified) and so we'll still be able to get a 4853 * valid EDID. To solve this schedule another detection cycle if this 4854 * time around we didn't detect any change in the sink's connection 4855 * status. 4856 * 4857 * Type-c connectors which get their HPD signal deasserted then 4858 * reasserted, without unplugging/replugging the sink from the 4859 * connector, introduce a delay until the AUX channel communication 4860 * becomes functional. Retry the detection for 5 seconds on type-c 4861 * connectors to account for this delay. 4862 */ 4863 if (state == INTEL_HOTPLUG_UNCHANGED && 4864 connector->hotplug_retries < (is_tc ? 5 : 1) && 4865 !dig_port->dp.is_mst) 4866 state = INTEL_HOTPLUG_RETRY; 4867 4868 return state; 4869 } 4870 4871 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4872 { 4873 struct intel_display *display = to_intel_display(encoder); 4874 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4875 4876 return intel_de_read(display, SDEISR) & bit; 4877 } 4878 4879 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4880 { 4881 struct intel_display *display = to_intel_display(encoder); 4882 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4883 4884 return intel_de_read(display, DEISR) & bit; 4885 } 4886 4887 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4888 { 4889 struct intel_display *display = to_intel_display(encoder); 4890 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4891 4892 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4893 } 4894 4895 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4896 { 4897 struct intel_connector *connector; 4898 enum port port = dig_port->base.port; 4899 4900 connector = intel_connector_alloc(); 4901 if (!connector) 4902 return -ENOMEM; 4903 4904 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4905 4906 if (!intel_hdmi_init_connector(dig_port, connector)) { 4907 /* 4908 * HDMI connector init failures may just mean conflicting DDC 4909 * pins or not having enough lanes. Handle them gracefully, but 4910 * don't fail the entire DDI init. 4911 */ 4912 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4913 kfree(connector); 4914 } 4915 4916 return 0; 4917 } 4918 4919 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4920 { 4921 struct intel_display *display = to_intel_display(dig_port); 4922 4923 if (dig_port->base.port != PORT_A) 4924 return false; 4925 4926 if (dig_port->ddi_a_4_lanes) 4927 return false; 4928 4929 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4930 * supported configuration 4931 */ 4932 if (display->platform.geminilake || display->platform.broxton) 4933 return true; 4934 4935 return false; 4936 } 4937 4938 static int 4939 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4940 { 4941 struct intel_display *display = to_intel_display(dig_port); 4942 enum port port = dig_port->base.port; 4943 int max_lanes = 4; 4944 4945 if (DISPLAY_VER(display) >= 11) 4946 return max_lanes; 4947 4948 if (port == PORT_A || port == PORT_E) { 4949 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4950 max_lanes = port == PORT_A ? 4 : 0; 4951 else 4952 /* Both A and E share 2 lanes */ 4953 max_lanes = 2; 4954 } 4955 4956 /* 4957 * Some BIOS might fail to set this bit on port A if eDP 4958 * wasn't lit up at boot. Force this bit set when needed 4959 * so we use the proper lane count for our calculations. 4960 */ 4961 if (intel_ddi_a_force_4_lanes(dig_port)) { 4962 drm_dbg_kms(display->drm, 4963 "Forcing DDI_A_4_LANES for port A\n"); 4964 dig_port->ddi_a_4_lanes = true; 4965 max_lanes = 4; 4966 } 4967 4968 return max_lanes; 4969 } 4970 4971 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4972 { 4973 if (port >= PORT_D_XELPD) 4974 return HPD_PORT_D + port - PORT_D_XELPD; 4975 else if (port >= PORT_TC1) 4976 return HPD_PORT_TC1 + port - PORT_TC1; 4977 else 4978 return HPD_PORT_A + port - PORT_A; 4979 } 4980 4981 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4982 { 4983 if (port >= PORT_TC1) 4984 return HPD_PORT_C + port - PORT_TC1; 4985 else 4986 return HPD_PORT_A + port - PORT_A; 4987 } 4988 4989 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4990 { 4991 if (port >= PORT_TC1) 4992 return HPD_PORT_TC1 + port - PORT_TC1; 4993 else 4994 return HPD_PORT_A + port - PORT_A; 4995 } 4996 4997 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4998 { 4999 if (HAS_PCH_TGP(display)) 5000 return tgl_hpd_pin(display, port); 5001 5002 if (port >= PORT_TC1) 5003 return HPD_PORT_C + port - PORT_TC1; 5004 else 5005 return HPD_PORT_A + port - PORT_A; 5006 } 5007 5008 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 5009 { 5010 if (port >= PORT_C) 5011 return HPD_PORT_TC1 + port - PORT_C; 5012 else 5013 return HPD_PORT_A + port - PORT_A; 5014 } 5015 5016 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 5017 { 5018 if (port == PORT_D) 5019 return HPD_PORT_A; 5020 5021 if (HAS_PCH_TGP(display)) 5022 return icl_hpd_pin(display, port); 5023 5024 return HPD_PORT_A + port - PORT_A; 5025 } 5026 5027 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 5028 { 5029 if (HAS_PCH_TGP(display)) 5030 return icl_hpd_pin(display, port); 5031 5032 return HPD_PORT_A + port - PORT_A; 5033 } 5034 5035 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 5036 { 5037 if (DISPLAY_VER(display) >= 12) 5038 return port >= PORT_TC1; 5039 else if (DISPLAY_VER(display) >= 11) 5040 return port >= PORT_C; 5041 else 5042 return false; 5043 } 5044 5045 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5046 { 5047 intel_dp_encoder_suspend(encoder); 5048 } 5049 5050 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5051 { 5052 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5053 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5054 5055 /* 5056 * TODO: Move this to intel_dp_encoder_suspend(), 5057 * once modeset locking around that is removed. 5058 */ 5059 intel_encoder_link_check_flush_work(encoder); 5060 intel_tc_port_suspend(dig_port); 5061 } 5062 5063 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5064 { 5065 if (intel_encoder_is_dp(encoder)) 5066 intel_dp_encoder_shutdown(encoder); 5067 if (intel_encoder_is_hdmi(encoder)) 5068 intel_hdmi_encoder_shutdown(encoder); 5069 } 5070 5071 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5072 { 5073 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5074 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5075 5076 intel_tc_port_cleanup(dig_port); 5077 } 5078 5079 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5080 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5081 5082 static bool port_strap_detected(struct intel_display *display, enum port port) 5083 { 5084 /* straps not used on skl+ */ 5085 if (DISPLAY_VER(display) >= 9) 5086 return true; 5087 5088 switch (port) { 5089 case PORT_A: 5090 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5091 case PORT_B: 5092 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5093 case PORT_C: 5094 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5095 case PORT_D: 5096 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5097 case PORT_E: 5098 return true; /* no strap for DDI-E */ 5099 default: 5100 MISSING_CASE(port); 5101 return false; 5102 } 5103 } 5104 5105 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5106 { 5107 return init_dp || intel_encoder_is_tc(encoder); 5108 } 5109 5110 static bool assert_has_icl_dsi(struct intel_display *display) 5111 { 5112 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5113 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5114 "Platform does not support DSI\n"); 5115 } 5116 5117 static bool port_in_use(struct intel_display *display, enum port port) 5118 { 5119 struct intel_encoder *encoder; 5120 5121 for_each_intel_encoder(display->drm, encoder) { 5122 /* FIXME what about second port for dual link DSI? */ 5123 if (encoder->port == port) 5124 return true; 5125 } 5126 5127 return false; 5128 } 5129 5130 static const char *intel_ddi_encoder_name(struct intel_display *display, 5131 enum port port, enum phy phy, 5132 struct seq_buf *s) 5133 { 5134 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5135 seq_buf_printf(s, "DDI %c/PHY %c", 5136 port_name(port - PORT_D_XELPD + PORT_D), 5137 phy_name(phy)); 5138 } else if (DISPLAY_VER(display) >= 12) { 5139 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5140 5141 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5142 port >= PORT_TC1 ? "TC" : "", 5143 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5144 tc_port != TC_PORT_NONE ? "TC" : "", 5145 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5146 } else if (DISPLAY_VER(display) >= 11) { 5147 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5148 5149 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5150 port_name(port), 5151 port >= PORT_C ? " (TC)" : "", 5152 tc_port != TC_PORT_NONE ? "TC" : "", 5153 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5154 } else { 5155 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5156 } 5157 5158 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5159 5160 return seq_buf_str(s); 5161 } 5162 5163 void intel_ddi_init(struct intel_display *display, 5164 const struct intel_bios_encoder_data *devdata) 5165 { 5166 struct intel_digital_port *dig_port; 5167 struct intel_encoder *encoder; 5168 DECLARE_SEQ_BUF(encoder_name, 20); 5169 bool init_hdmi, init_dp; 5170 enum port port; 5171 enum phy phy; 5172 u32 ddi_buf_ctl; 5173 5174 port = intel_bios_encoder_port(devdata); 5175 if (port == PORT_NONE) 5176 return; 5177 5178 if (!port_strap_detected(display, port)) { 5179 drm_dbg_kms(display->drm, 5180 "Port %c strap not detected\n", port_name(port)); 5181 return; 5182 } 5183 5184 if (!assert_port_valid(display, port)) 5185 return; 5186 5187 if (port_in_use(display, port)) { 5188 drm_dbg_kms(display->drm, 5189 "Port %c already claimed\n", port_name(port)); 5190 return; 5191 } 5192 5193 if (intel_bios_encoder_supports_dsi(devdata)) { 5194 /* BXT/GLK handled elsewhere, for now at least */ 5195 if (!assert_has_icl_dsi(display)) 5196 return; 5197 5198 icl_dsi_init(display, devdata); 5199 return; 5200 } 5201 5202 phy = intel_port_to_phy(display, port); 5203 5204 /* 5205 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5206 * have taken over some of the PHYs and made them unavailable to the 5207 * driver. In that case we should skip initializing the corresponding 5208 * outputs. 5209 */ 5210 if (intel_hti_uses_phy(display, phy)) { 5211 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5212 port_name(port), phy_name(phy)); 5213 return; 5214 } 5215 5216 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5217 intel_bios_encoder_supports_hdmi(devdata); 5218 init_dp = intel_bios_encoder_supports_dp(devdata); 5219 5220 if (intel_bios_encoder_is_lspcon(devdata)) { 5221 /* 5222 * Lspcon device needs to be driven with DP connector 5223 * with special detection sequence. So make sure DP 5224 * is initialized before lspcon. 5225 */ 5226 init_dp = true; 5227 init_hdmi = false; 5228 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5229 port_name(port)); 5230 } 5231 5232 if (!init_dp && !init_hdmi) { 5233 drm_dbg_kms(display->drm, 5234 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5235 port_name(port)); 5236 return; 5237 } 5238 5239 if (intel_phy_is_snps(display, phy) && 5240 display->snps.phy_failed_calibration & BIT(phy)) { 5241 drm_dbg_kms(display->drm, 5242 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5243 phy_name(phy)); 5244 } 5245 5246 dig_port = intel_dig_port_alloc(); 5247 if (!dig_port) 5248 return; 5249 5250 encoder = &dig_port->base; 5251 encoder->devdata = devdata; 5252 5253 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5254 DRM_MODE_ENCODER_TMDS, "%s", 5255 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5256 5257 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5258 5259 encoder->hotplug = intel_ddi_hotplug; 5260 encoder->compute_output_type = intel_ddi_compute_output_type; 5261 encoder->compute_config = intel_ddi_compute_config; 5262 encoder->compute_config_late = intel_ddi_compute_config_late; 5263 encoder->enable = intel_ddi_enable; 5264 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5265 encoder->pre_enable = intel_ddi_pre_enable; 5266 encoder->disable = intel_ddi_disable; 5267 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5268 encoder->post_disable = intel_ddi_post_disable; 5269 encoder->update_pipe = intel_ddi_update_pipe; 5270 encoder->audio_enable = intel_audio_codec_enable; 5271 encoder->audio_disable = intel_audio_codec_disable; 5272 encoder->get_hw_state = intel_ddi_get_hw_state; 5273 encoder->sync_state = intel_ddi_sync_state; 5274 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5275 encoder->suspend = intel_ddi_encoder_suspend; 5276 encoder->shutdown = intel_ddi_encoder_shutdown; 5277 encoder->get_power_domains = intel_ddi_get_power_domains; 5278 5279 encoder->type = INTEL_OUTPUT_DDI; 5280 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5281 encoder->port = port; 5282 encoder->cloneable = 0; 5283 encoder->pipe_mask = ~0; 5284 5285 if (HAS_LT_PHY(display)) { 5286 encoder->enable_clock = intel_mtl_pll_enable_clock; 5287 encoder->disable_clock = intel_mtl_pll_disable_clock; 5288 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5289 if (intel_encoder_is_tc(encoder)) 5290 encoder->get_config = mtl_ddi_tc_phy_get_config; 5291 else 5292 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5293 } else if (DISPLAY_VER(display) >= 14) { 5294 encoder->enable_clock = intel_mtl_pll_enable_clock; 5295 encoder->disable_clock = intel_mtl_pll_disable_clock; 5296 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5297 if (intel_encoder_is_tc(encoder)) 5298 encoder->get_config = mtl_ddi_tc_phy_get_config; 5299 else 5300 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5301 } else if (display->platform.dg2) { 5302 encoder->enable_clock = intel_mpllb_enable; 5303 encoder->disable_clock = intel_mpllb_disable; 5304 encoder->get_config = dg2_ddi_get_config; 5305 } else if (display->platform.alderlake_s) { 5306 encoder->enable_clock = adls_ddi_enable_clock; 5307 encoder->disable_clock = adls_ddi_disable_clock; 5308 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5309 encoder->get_config = adls_ddi_get_config; 5310 } else if (display->platform.rocketlake) { 5311 encoder->enable_clock = rkl_ddi_enable_clock; 5312 encoder->disable_clock = rkl_ddi_disable_clock; 5313 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5314 encoder->get_config = rkl_ddi_get_config; 5315 } else if (display->platform.dg1) { 5316 encoder->enable_clock = dg1_ddi_enable_clock; 5317 encoder->disable_clock = dg1_ddi_disable_clock; 5318 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5319 encoder->get_config = dg1_ddi_get_config; 5320 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5321 if (intel_ddi_is_tc(display, port)) { 5322 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5323 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5324 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5325 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5326 encoder->get_config = icl_ddi_combo_get_config; 5327 } else { 5328 encoder->enable_clock = icl_ddi_combo_enable_clock; 5329 encoder->disable_clock = icl_ddi_combo_disable_clock; 5330 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5331 encoder->get_config = icl_ddi_combo_get_config; 5332 } 5333 } else if (DISPLAY_VER(display) >= 11) { 5334 if (intel_ddi_is_tc(display, port)) { 5335 encoder->enable_clock = icl_ddi_tc_enable_clock; 5336 encoder->disable_clock = icl_ddi_tc_disable_clock; 5337 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5338 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5339 encoder->get_config = icl_ddi_tc_get_config; 5340 } else { 5341 encoder->enable_clock = icl_ddi_combo_enable_clock; 5342 encoder->disable_clock = icl_ddi_combo_disable_clock; 5343 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5344 encoder->get_config = icl_ddi_combo_get_config; 5345 } 5346 } else if (display->platform.geminilake || display->platform.broxton) { 5347 /* BXT/GLK have fixed PLL->port mapping */ 5348 encoder->get_config = bxt_ddi_get_config; 5349 } else if (DISPLAY_VER(display) == 9) { 5350 encoder->enable_clock = skl_ddi_enable_clock; 5351 encoder->disable_clock = skl_ddi_disable_clock; 5352 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5353 encoder->get_config = skl_ddi_get_config; 5354 } else if (display->platform.broadwell || display->platform.haswell) { 5355 encoder->enable_clock = hsw_ddi_enable_clock; 5356 encoder->disable_clock = hsw_ddi_disable_clock; 5357 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5358 encoder->get_config = hsw_ddi_get_config; 5359 } 5360 5361 if (HAS_LT_PHY(display)) { 5362 encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5363 } else if (DISPLAY_VER(display) >= 14) { 5364 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5365 } else if (display->platform.dg2) { 5366 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5367 } else if (DISPLAY_VER(display) >= 12) { 5368 if (intel_encoder_is_combo(encoder)) 5369 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5370 else 5371 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5372 } else if (DISPLAY_VER(display) >= 11) { 5373 if (intel_encoder_is_combo(encoder)) 5374 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5375 else 5376 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5377 } else if (display->platform.geminilake || display->platform.broxton) { 5378 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5379 } else { 5380 encoder->set_signal_levels = hsw_set_signal_levels; 5381 } 5382 5383 intel_ddi_buf_trans_init(encoder); 5384 5385 if (DISPLAY_VER(display) >= 13) 5386 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5387 else if (display->platform.dg1) 5388 encoder->hpd_pin = dg1_hpd_pin(display, port); 5389 else if (display->platform.rocketlake) 5390 encoder->hpd_pin = rkl_hpd_pin(display, port); 5391 else if (DISPLAY_VER(display) >= 12) 5392 encoder->hpd_pin = tgl_hpd_pin(display, port); 5393 else if (display->platform.jasperlake || display->platform.elkhartlake) 5394 encoder->hpd_pin = ehl_hpd_pin(display, port); 5395 else if (DISPLAY_VER(display) == 11) 5396 encoder->hpd_pin = icl_hpd_pin(display, port); 5397 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5398 encoder->hpd_pin = skl_hpd_pin(display, port); 5399 else 5400 encoder->hpd_pin = intel_hpd_pin_default(port); 5401 5402 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5403 5404 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5405 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5406 5407 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5408 5409 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5410 5411 if (need_aux_ch(encoder, init_dp)) { 5412 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5413 if (dig_port->aux_ch == AUX_CH_NONE) 5414 goto err; 5415 } 5416 5417 /* 5418 * FIXME: We currently need to store dedicated_external because devdata 5419 * does not live long enough for when intel_encoder_is_tc() is called on 5420 * the unbind path. This needs to be fixed by making sure that the VBT 5421 * data is kept long enough, so that 5422 * intel_bios_encoder_is_dedicated_external() can be called directly 5423 * from intel_encoder_is_tc(). 5424 */ 5425 if (intel_bios_encoder_is_dedicated_external(devdata)) 5426 dig_port->dedicated_external = true; 5427 5428 if (intel_encoder_is_tc(encoder)) { 5429 bool is_legacy = 5430 !intel_bios_encoder_supports_typec_usb(devdata) && 5431 !intel_bios_encoder_supports_tbt(devdata); 5432 5433 if (!is_legacy && init_hdmi) { 5434 is_legacy = !init_dp; 5435 5436 drm_dbg_kms(display->drm, 5437 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5438 port_name(port), 5439 str_yes_no(init_dp), 5440 is_legacy ? "legacy" : "non-legacy"); 5441 } 5442 5443 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5444 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5445 5446 dig_port->lock = intel_tc_port_lock; 5447 dig_port->unlock = intel_tc_port_unlock; 5448 5449 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5450 goto err; 5451 } 5452 5453 drm_WARN_ON(display->drm, port > PORT_I); 5454 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5455 5456 if (DISPLAY_VER(display) >= 11) { 5457 if (intel_encoder_is_tc(encoder)) 5458 dig_port->connected = intel_tc_port_connected; 5459 else 5460 dig_port->connected = lpt_digital_port_connected; 5461 } else if (display->platform.geminilake || display->platform.broxton) { 5462 dig_port->connected = bdw_digital_port_connected; 5463 } else if (DISPLAY_VER(display) == 9) { 5464 dig_port->connected = lpt_digital_port_connected; 5465 } else if (display->platform.broadwell) { 5466 if (port == PORT_A) 5467 dig_port->connected = bdw_digital_port_connected; 5468 else 5469 dig_port->connected = lpt_digital_port_connected; 5470 } else if (display->platform.haswell) { 5471 if (port == PORT_A) 5472 dig_port->connected = hsw_digital_port_connected; 5473 else 5474 dig_port->connected = lpt_digital_port_connected; 5475 } 5476 5477 intel_infoframe_init(dig_port); 5478 5479 if (init_dp) { 5480 if (intel_ddi_init_dp_connector(dig_port)) 5481 goto err; 5482 5483 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5484 5485 if (dig_port->dp.mso_link_count) 5486 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5487 } 5488 5489 /* 5490 * In theory we don't need the encoder->type check, 5491 * but leave it just in case we have some really bad VBTs... 5492 */ 5493 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5494 if (intel_ddi_init_hdmi_connector(dig_port)) 5495 goto err; 5496 } 5497 5498 return; 5499 5500 err: 5501 drm_encoder_cleanup(&encoder->base); 5502 kfree(dig_port); 5503 } 5504