1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 #include <drm/intel/step.h> 37 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_display_utils.h" 56 #include "intel_display_wa.h" 57 #include "intel_dkl_phy.h" 58 #include "intel_dkl_phy_regs.h" 59 #include "intel_dp.h" 60 #include "intel_dp_aux.h" 61 #include "intel_dp_link_training.h" 62 #include "intel_dp_mst.h" 63 #include "intel_dp_test.h" 64 #include "intel_dp_tunnel.h" 65 #include "intel_dpio_phy.h" 66 #include "intel_dsi.h" 67 #include "intel_encoder.h" 68 #include "intel_fdi.h" 69 #include "intel_fifo_underrun.h" 70 #include "intel_gmbus.h" 71 #include "intel_hdcp.h" 72 #include "intel_hdmi.h" 73 #include "intel_hotplug.h" 74 #include "intel_hti.h" 75 #include "intel_lspcon.h" 76 #include "intel_lt_phy.h" 77 #include "intel_mg_phy_regs.h" 78 #include "intel_modeset_lock.h" 79 #include "intel_panel.h" 80 #include "intel_pfit.h" 81 #include "intel_pps.h" 82 #include "intel_psr.h" 83 #include "intel_quirks.h" 84 #include "intel_snps_phy.h" 85 #include "intel_tc.h" 86 #include "intel_vdsc.h" 87 #include "intel_vdsc_regs.h" 88 #include "intel_vrr.h" 89 #include "skl_scaler.h" 90 #include "skl_universal_plane.h" 91 92 struct intel_dpll; 93 94 static const u8 index_to_dp_signal_levels[] = { 95 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 98 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 99 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 100 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 101 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 102 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 103 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 104 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 105 }; 106 107 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 108 const struct intel_ddi_buf_trans *trans) 109 { 110 int level; 111 112 level = intel_bios_hdmi_level_shift(encoder->devdata); 113 if (level < 0) 114 level = trans->hdmi_default_entry; 115 116 return level; 117 } 118 119 static bool has_buf_trans_select(struct intel_display *display) 120 { 121 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 122 } 123 124 static bool has_iboost(struct intel_display *display) 125 { 126 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 127 } 128 129 /* 130 * Starting with Haswell, DDI port buffers must be programmed with correct 131 * values in advance. This function programs the correct values for 132 * DP/eDP/FDI use cases. 133 */ 134 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 135 const struct intel_crtc_state *crtc_state) 136 { 137 struct intel_display *display = to_intel_display(encoder); 138 u32 iboost_bit = 0; 139 int i, n_entries; 140 enum port port = encoder->port; 141 const struct intel_ddi_buf_trans *trans; 142 143 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 144 if (drm_WARN_ON_ONCE(display->drm, !trans)) 145 return; 146 147 /* If we're boosting the current, set bit 31 of trans1 */ 148 if (has_iboost(display) && 149 intel_bios_dp_boost_level(encoder->devdata)) 150 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 151 152 for (i = 0; i < n_entries; i++) { 153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 154 trans->entries[i].hsw.trans1 | iboost_bit); 155 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 156 trans->entries[i].hsw.trans2); 157 } 158 } 159 160 /* 161 * Starting with Haswell, DDI port buffers must be programmed with correct 162 * values in advance. This function programs the correct values for 163 * HDMI/DVI use cases. 164 */ 165 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 166 const struct intel_crtc_state *crtc_state) 167 { 168 struct intel_display *display = to_intel_display(encoder); 169 int level = intel_ddi_level(encoder, crtc_state, 0); 170 u32 iboost_bit = 0; 171 int n_entries; 172 enum port port = encoder->port; 173 const struct intel_ddi_buf_trans *trans; 174 175 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 176 if (drm_WARN_ON_ONCE(display->drm, !trans)) 177 return; 178 179 /* If we're boosting the current, set bit 31 of trans1 */ 180 if (has_iboost(display) && 181 intel_bios_hdmi_boost_level(encoder->devdata)) 182 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 183 184 /* Entry 9 is for HDMI: */ 185 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 186 trans->entries[level].hsw.trans1 | iboost_bit); 187 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 188 trans->entries[level].hsw.trans2); 189 } 190 191 static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 192 { 193 if (DISPLAY_VER(display) >= 14) 194 return XELPDP_PORT_BUF_CTL1(display, port); 195 else 196 return DDI_BUF_CTL(port); 197 } 198 199 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 200 { 201 /* 202 * Bspec's platform specific timeouts: 203 * MTL+ : 100 us 204 * BXT : fixed 16 us 205 * HSW-ADL: 8 us 206 * 207 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 208 */ 209 if (display->platform.broxton) { 210 udelay(16); 211 return; 212 } 213 214 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 215 if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port), 216 DDI_BUF_IS_IDLE, 10)) 217 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 218 port_name(port)); 219 } 220 221 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 222 { 223 struct intel_display *display = to_intel_display(encoder); 224 enum port port = encoder->port; 225 226 /* 227 * Bspec's platform specific timeouts: 228 * MTL+ : 10000 us 229 * DG2 : 1200 us 230 * TGL-ADL combo PHY: 1000 us 231 * TGL-ADL TypeC PHY: 3000 us 232 * HSW-ICL : fixed 518 us 233 */ 234 if (DISPLAY_VER(display) < 10) { 235 usleep_range(518, 1000); 236 return; 237 } 238 239 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 240 if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port), 241 DDI_BUF_IS_IDLE, 10)) 242 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_dpll *pll = crtc_state->intel_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static int dp_phy_lane_stagger_delay(int port_clock) 332 { 333 /* 334 * Return the number of symbol clocks delay used to stagger the 335 * assertion/desassertion of the port lane enables. The target delay 336 * time is 100 ns or greater, return the number of symbols specific to 337 * the provided port_clock (aka link clock) corresponding to this delay 338 * time, i.e. so that 339 * 340 * number_of_symbols * duration_of_one_symbol >= 100 ns 341 * 342 * The delay must be applied only on TypeC DP outputs, for everything else 343 * the delay must be set to 0. 344 * 345 * Return the number of link symbols per 100 ns: 346 * port_clock (10 kHz) -> bits / 100 us 347 * / symbol_size -> symbols / 100 us 348 * / 1000 -> symbols / 100 ns 349 */ 350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 351 } 352 353 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state) 355 { 356 struct intel_display *display = to_intel_display(encoder); 357 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 358 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 359 360 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 362 DDI_BUF_TRANS_SELECT(0); 363 364 if (dig_port->lane_reversal) 365 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 366 if (dig_port->ddi_a_4_lanes) 367 intel_dp->DP |= DDI_A_4_LANES; 368 369 if (DISPLAY_VER(display) >= 14) { 370 if (intel_dp_is_uhbr(crtc_state)) 371 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 372 else 373 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 374 } 375 376 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 378 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 379 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 380 } 381 382 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 384 385 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 386 } 387 } 388 389 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 390 { 391 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 392 393 switch (val) { 394 case DDI_CLK_SEL_NONE: 395 return 0; 396 case DDI_CLK_SEL_TBT_162: 397 return 162000; 398 case DDI_CLK_SEL_TBT_270: 399 return 270000; 400 case DDI_CLK_SEL_TBT_540: 401 return 540000; 402 case DDI_CLK_SEL_TBT_810: 403 return 810000; 404 default: 405 MISSING_CASE(val); 406 return 0; 407 } 408 } 409 410 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 411 { 412 /* CRT dotclock is determined via other means */ 413 if (pipe_config->has_pch_encoder) 414 return; 415 416 pipe_config->hw.adjusted_mode.crtc_clock = 417 intel_crtc_dotclock(pipe_config); 418 } 419 420 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 421 const struct drm_connector_state *conn_state) 422 { 423 struct intel_display *display = to_intel_display(crtc_state); 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 u32 temp; 426 427 if (!intel_crtc_has_dp_encoder(crtc_state)) 428 return; 429 430 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 431 432 temp = DP_MSA_MISC_SYNC_CLOCK; 433 434 switch (crtc_state->pipe_bpp) { 435 case 18: 436 temp |= DP_MSA_MISC_6_BPC; 437 break; 438 case 24: 439 temp |= DP_MSA_MISC_8_BPC; 440 break; 441 case 30: 442 temp |= DP_MSA_MISC_10_BPC; 443 break; 444 case 36: 445 temp |= DP_MSA_MISC_12_BPC; 446 break; 447 default: 448 MISSING_CASE(crtc_state->pipe_bpp); 449 break; 450 } 451 452 /* nonsense combination */ 453 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 454 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 455 456 if (crtc_state->limited_color_range) 457 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 458 459 /* 460 * As per DP 1.2 spec section 2.3.4.3 while sending 461 * YCBCR 444 signals we should program MSA MISC1/0 fields with 462 * colorspace information. 463 */ 464 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 465 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 466 467 /* 468 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 469 * of Color Encoding Format and Content Color Gamut] while sending 470 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 471 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 472 * Only set the delegation bit when the content needs it and 473 * the sink advertises support. 474 */ 475 if (intel_dp_needs_vsc_colorimetry(crtc_state, conn_state)) 476 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 477 478 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 479 temp); 480 } 481 482 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 483 { 484 if (master_transcoder == TRANSCODER_EDP) 485 return 0; 486 else 487 return master_transcoder + 1; 488 } 489 490 static void 491 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 492 bool enable) 493 { 494 struct intel_display *display = to_intel_display(crtc_state); 495 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 496 u32 val = 0; 497 498 if (!HAS_DP20(display)) 499 return; 500 501 if (enable && intel_dp_is_uhbr(crtc_state)) 502 val = TRANS_DP2_128B132B_CHANNEL_CODING; 503 504 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 505 } 506 507 /* 508 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 509 * 510 * Only intended to be used by intel_ddi_enable_transcoder_func() and 511 * intel_ddi_config_transcoder_func(). 512 */ 513 static u32 514 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 515 const struct intel_crtc_state *crtc_state) 516 { 517 struct intel_display *display = to_intel_display(crtc_state); 518 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 519 enum pipe pipe = crtc->pipe; 520 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 521 enum port port = encoder->port; 522 u32 temp; 523 524 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 525 temp = TRANS_DDI_FUNC_ENABLE; 526 if (DISPLAY_VER(display) >= 12) 527 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 528 else 529 temp |= TRANS_DDI_SELECT_PORT(port); 530 531 switch (crtc_state->pipe_bpp) { 532 default: 533 MISSING_CASE(crtc_state->pipe_bpp); 534 fallthrough; 535 case 18: 536 temp |= TRANS_DDI_BPC_6; 537 break; 538 case 24: 539 temp |= TRANS_DDI_BPC_8; 540 break; 541 case 30: 542 temp |= TRANS_DDI_BPC_10; 543 break; 544 case 36: 545 temp |= TRANS_DDI_BPC_12; 546 break; 547 } 548 549 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 550 temp |= TRANS_DDI_PVSYNC; 551 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 552 temp |= TRANS_DDI_PHSYNC; 553 554 if (cpu_transcoder == TRANSCODER_EDP) { 555 switch (pipe) { 556 default: 557 MISSING_CASE(pipe); 558 fallthrough; 559 case PIPE_A: 560 /* On Haswell, can only use the always-on power well for 561 * eDP when not using the panel fitter, and when not 562 * using motion blur mitigation (which we don't 563 * support). */ 564 if (crtc_state->pch_pfit.force_thru) 565 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 566 else 567 temp |= TRANS_DDI_EDP_INPUT_A_ON; 568 break; 569 case PIPE_B: 570 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 571 break; 572 case PIPE_C: 573 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 574 break; 575 } 576 } 577 578 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 579 if (crtc_state->has_hdmi_sink) 580 temp |= TRANS_DDI_MODE_SELECT_HDMI; 581 else 582 temp |= TRANS_DDI_MODE_SELECT_DVI; 583 584 if (crtc_state->hdmi_scrambling) 585 temp |= TRANS_DDI_HDMI_SCRAMBLING; 586 if (crtc_state->hdmi_high_tmds_clock_ratio) 587 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 588 if (DISPLAY_VER(display) >= 14) 589 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 590 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 591 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 592 temp |= (crtc_state->fdi_lanes - 1) << 1; 593 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 594 intel_dp_is_uhbr(crtc_state)) { 595 if (intel_dp_is_uhbr(crtc_state)) 596 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 597 else 598 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 599 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 600 601 if (DISPLAY_VER(display) >= 12) { 602 enum transcoder master; 603 604 master = crtc_state->mst_master_transcoder; 605 if (drm_WARN_ON(display->drm, 606 master == INVALID_TRANSCODER)) 607 master = TRANSCODER_A; 608 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 609 } 610 } else { 611 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 612 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 613 } 614 615 if (IS_DISPLAY_VER(display, 8, 10) && 616 crtc_state->master_transcoder != INVALID_TRANSCODER) { 617 u8 master_select = 618 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 619 620 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 621 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 622 } 623 624 return temp; 625 } 626 627 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 628 const struct intel_crtc_state *crtc_state) 629 { 630 struct intel_display *display = to_intel_display(crtc_state); 631 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 632 633 if (DISPLAY_VER(display) >= 11) { 634 enum transcoder master_transcoder = crtc_state->master_transcoder; 635 u32 ctl2 = 0; 636 637 if (master_transcoder != INVALID_TRANSCODER) { 638 u8 master_select = 639 bdw_trans_port_sync_master_select(master_transcoder); 640 641 ctl2 |= PORT_SYNC_MODE_ENABLE | 642 PORT_SYNC_MODE_MASTER_SELECT(master_select); 643 } 644 645 intel_de_write(display, 646 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 647 ctl2); 648 } 649 650 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 651 intel_ddi_transcoder_func_reg_val_get(encoder, 652 crtc_state)); 653 } 654 655 /* 656 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 657 * bit for the DDI function and enables the DP2 configuration. Called for all 658 * transcoder types. 659 */ 660 void 661 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 662 const struct intel_crtc_state *crtc_state) 663 { 664 struct intel_display *display = to_intel_display(crtc_state); 665 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 666 u32 ctl; 667 668 intel_ddi_config_transcoder_dp2(crtc_state, true); 669 670 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 671 ctl &= ~TRANS_DDI_FUNC_ENABLE; 672 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 673 ctl); 674 } 675 676 /* 677 * Disable the DDI function and port syncing. 678 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 679 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 680 * transcoders these are done later in intel_ddi_post_disable_dp(). 681 */ 682 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 683 { 684 struct intel_display *display = to_intel_display(crtc_state); 685 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 686 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 687 u32 ctl; 688 689 if (DISPLAY_VER(display) >= 11) 690 intel_de_write(display, 691 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 692 0); 693 694 ctl = intel_de_read(display, 695 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 696 697 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 698 699 ctl &= ~TRANS_DDI_FUNC_ENABLE; 700 701 if (IS_DISPLAY_VER(display, 8, 10)) 702 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 703 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 704 705 if (DISPLAY_VER(display) >= 12) { 706 if (!intel_dp_mst_is_master_trans(crtc_state)) { 707 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 708 TRANS_DDI_MODE_SELECT_MASK); 709 } 710 } else { 711 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 712 } 713 714 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 715 ctl); 716 717 if (intel_dp_mst_is_slave_trans(crtc_state)) 718 intel_ddi_config_transcoder_dp2(crtc_state, false); 719 720 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 721 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 722 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 723 /* Quirk time at 100ms for reliable operation */ 724 msleep(100); 725 } 726 } 727 728 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 729 enum transcoder cpu_transcoder, 730 bool enable, u32 hdcp_mask) 731 { 732 struct intel_display *display = to_intel_display(intel_encoder); 733 struct ref_tracker *wakeref; 734 int ret = 0; 735 736 wakeref = intel_display_power_get_if_enabled(display, 737 intel_encoder->power_domain); 738 if (drm_WARN_ON(display->drm, !wakeref)) 739 return -ENXIO; 740 741 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 742 hdcp_mask, enable ? hdcp_mask : 0); 743 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 744 return ret; 745 } 746 747 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 748 { 749 struct intel_display *display = to_intel_display(intel_connector); 750 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 751 int type = intel_connector->base.connector_type; 752 enum port port = encoder->port; 753 enum transcoder cpu_transcoder; 754 struct ref_tracker *wakeref; 755 enum pipe pipe = 0; 756 u32 ddi_mode; 757 bool ret; 758 759 wakeref = intel_display_power_get_if_enabled(display, 760 encoder->power_domain); 761 if (!wakeref) 762 return false; 763 764 /* Note: This returns false for DP MST primary encoders. */ 765 if (!encoder->get_hw_state(encoder, &pipe)) { 766 ret = false; 767 goto out; 768 } 769 770 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 771 cpu_transcoder = TRANSCODER_EDP; 772 else 773 cpu_transcoder = (enum transcoder) pipe; 774 775 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 776 TRANS_DDI_MODE_SELECT_MASK; 777 778 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 779 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 780 ret = type == DRM_MODE_CONNECTOR_HDMIA; 781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 782 ret = type == DRM_MODE_CONNECTOR_VGA; 783 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 784 ret = type == DRM_MODE_CONNECTOR_eDP || 785 type == DRM_MODE_CONNECTOR_DisplayPort; 786 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 787 /* 788 * encoder->get_hw_state() should have bailed out on MST. This 789 * must be SST and non-eDP. 790 */ 791 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 792 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 793 /* encoder->get_hw_state() should have bailed out on MST. */ 794 ret = false; 795 } else { 796 ret = false; 797 } 798 799 out: 800 intel_display_power_put(display, encoder->power_domain, wakeref); 801 802 return ret; 803 } 804 805 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 806 u8 *pipe_mask, bool *is_dp_mst) 807 { 808 struct intel_display *display = to_intel_display(encoder); 809 enum port port = encoder->port; 810 struct ref_tracker *wakeref; 811 enum pipe p; 812 u32 tmp; 813 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 814 815 *pipe_mask = 0; 816 *is_dp_mst = false; 817 818 wakeref = intel_display_power_get_if_enabled(display, 819 encoder->power_domain); 820 if (!wakeref) 821 return; 822 823 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 824 if (!(tmp & DDI_BUF_CTL_ENABLE)) 825 goto out; 826 827 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 828 tmp = intel_de_read(display, 829 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 830 831 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 832 default: 833 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 834 fallthrough; 835 case TRANS_DDI_EDP_INPUT_A_ON: 836 case TRANS_DDI_EDP_INPUT_A_ONOFF: 837 *pipe_mask = BIT(PIPE_A); 838 break; 839 case TRANS_DDI_EDP_INPUT_B_ONOFF: 840 *pipe_mask = BIT(PIPE_B); 841 break; 842 case TRANS_DDI_EDP_INPUT_C_ONOFF: 843 *pipe_mask = BIT(PIPE_C); 844 break; 845 } 846 847 goto out; 848 } 849 850 for_each_pipe(display, p) { 851 enum transcoder cpu_transcoder = (enum transcoder)p; 852 u32 port_mask, ddi_select, ddi_mode; 853 struct ref_tracker *trans_wakeref; 854 855 trans_wakeref = intel_display_power_get_if_enabled(display, 856 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 857 if (!trans_wakeref) 858 continue; 859 860 if (DISPLAY_VER(display) >= 12) { 861 port_mask = TGL_TRANS_DDI_PORT_MASK; 862 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 863 } else { 864 port_mask = TRANS_DDI_PORT_MASK; 865 ddi_select = TRANS_DDI_SELECT_PORT(port); 866 } 867 868 tmp = intel_de_read(display, 869 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 870 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 871 trans_wakeref); 872 873 if ((tmp & port_mask) != ddi_select) 874 continue; 875 876 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 877 878 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 879 mst_pipe_mask |= BIT(p); 880 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 881 dp128b132b_pipe_mask |= BIT(p); 882 883 *pipe_mask |= BIT(p); 884 } 885 886 if (!*pipe_mask) 887 drm_dbg_kms(display->drm, 888 "No pipe for [ENCODER:%d:%s] found\n", 889 encoder->base.base.id, encoder->base.name); 890 891 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 892 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 893 894 /* 895 * If we don't have 8b/10b MST, but have more than one 896 * transcoder in 128b/132b mode, we know it must be 128b/132b 897 * MST. 898 * 899 * Otherwise, we fall back to checking the current MST 900 * state. It's not accurate for hardware takeover at probe, but 901 * we don't expect MST to have been enabled at that point, and 902 * can assume it's SST. 903 */ 904 if (hweight8(dp128b132b_pipe_mask) > 1 || 905 intel_dp_mst_active_streams(intel_dp)) 906 mst_pipe_mask = dp128b132b_pipe_mask; 907 } 908 909 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 910 drm_dbg_kms(display->drm, 911 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 912 encoder->base.base.id, encoder->base.name, 913 *pipe_mask); 914 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 915 } 916 917 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 918 drm_dbg_kms(display->drm, 919 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 920 encoder->base.base.id, encoder->base.name, 921 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 922 else 923 *is_dp_mst = mst_pipe_mask; 924 925 out: 926 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 927 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 928 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 929 BXT_PHY_LANE_POWERDOWN_ACK | 930 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 931 drm_err(display->drm, 932 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 933 encoder->base.base.id, encoder->base.name, tmp); 934 } 935 936 intel_display_power_put(display, encoder->power_domain, wakeref); 937 } 938 939 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 940 enum pipe *pipe) 941 { 942 u8 pipe_mask; 943 bool is_mst; 944 945 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 946 947 if (is_mst || !pipe_mask) 948 return false; 949 950 *pipe = ffs(pipe_mask) - 1; 951 952 return true; 953 } 954 955 static enum intel_display_power_domain 956 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 957 const struct intel_crtc_state *crtc_state) 958 { 959 struct intel_display *display = to_intel_display(dig_port); 960 961 /* 962 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 963 * DC states enabled at the same time, while for driver initiated AUX 964 * transfers we need the same AUX IOs to be powered but with DC states 965 * disabled. Accordingly use the AUX_IO_<port> power domain here which 966 * leaves DC states enabled. 967 * 968 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 969 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 970 * well, so we can acquire a wider AUX_<port> power domain reference 971 * instead of a specific AUX_IO_<port> reference without powering up any 972 * extra wells. 973 */ 974 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 975 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 976 else if (DISPLAY_VER(display) < 14 && 977 (intel_crtc_has_dp_encoder(crtc_state) || 978 intel_encoder_is_tc(&dig_port->base))) 979 return intel_aux_power_domain(dig_port); 980 else 981 return POWER_DOMAIN_INVALID; 982 } 983 984 static void 985 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 986 const struct intel_crtc_state *crtc_state) 987 { 988 struct intel_display *display = to_intel_display(dig_port); 989 enum intel_display_power_domain domain = 990 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 991 992 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 993 994 if (domain == POWER_DOMAIN_INVALID) 995 return; 996 997 dig_port->aux_wakeref = intel_display_power_get(display, domain); 998 } 999 1000 static void 1001 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 1002 const struct intel_crtc_state *crtc_state) 1003 { 1004 struct intel_display *display = to_intel_display(dig_port); 1005 enum intel_display_power_domain domain = 1006 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1007 struct ref_tracker *wf; 1008 1009 wf = fetch_and_zero(&dig_port->aux_wakeref); 1010 if (!wf) 1011 return; 1012 1013 intel_display_power_put(display, domain, wf); 1014 } 1015 1016 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1017 struct intel_crtc_state *crtc_state) 1018 { 1019 struct intel_display *display = to_intel_display(encoder); 1020 struct intel_digital_port *dig_port; 1021 1022 /* 1023 * TODO: Add support for MST encoders. Atm, the following should never 1024 * happen since fake-MST encoders don't set their get_power_domains() 1025 * hook. 1026 */ 1027 if (drm_WARN_ON(display->drm, 1028 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1029 return; 1030 1031 dig_port = enc_to_dig_port(encoder); 1032 1033 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1034 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1035 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1036 dig_port->ddi_io_power_domain); 1037 } 1038 1039 main_link_aux_power_domain_get(dig_port, crtc_state); 1040 } 1041 1042 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1043 const struct intel_crtc_state *crtc_state) 1044 { 1045 struct intel_display *display = to_intel_display(crtc_state); 1046 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1047 enum phy phy = intel_encoder_to_phy(encoder); 1048 u32 val; 1049 1050 if (cpu_transcoder == TRANSCODER_EDP) 1051 return; 1052 1053 if (DISPLAY_VER(display) >= 13) 1054 val = TGL_TRANS_CLK_SEL_PORT(phy); 1055 else if (DISPLAY_VER(display) >= 12) 1056 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1057 else 1058 val = TRANS_CLK_SEL_PORT(encoder->port); 1059 1060 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1061 } 1062 1063 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1064 { 1065 struct intel_display *display = to_intel_display(crtc_state); 1066 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1067 u32 val; 1068 1069 if (cpu_transcoder == TRANSCODER_EDP) 1070 return; 1071 1072 if (DISPLAY_VER(display) >= 12) 1073 val = TGL_TRANS_CLK_SEL_DISABLED; 1074 else 1075 val = TRANS_CLK_SEL_DISABLED; 1076 1077 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1078 } 1079 1080 static void _skl_ddi_set_iboost(struct intel_display *display, 1081 enum port port, u8 iboost) 1082 { 1083 u32 tmp; 1084 1085 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1086 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1087 if (iboost) 1088 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1089 else 1090 tmp |= BALANCE_LEG_DISABLE(port); 1091 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1092 } 1093 1094 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1095 const struct intel_crtc_state *crtc_state, 1096 int level) 1097 { 1098 struct intel_display *display = to_intel_display(encoder); 1099 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1100 u8 iboost; 1101 1102 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1103 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1104 else 1105 iboost = intel_bios_dp_boost_level(encoder->devdata); 1106 1107 if (iboost == 0) { 1108 const struct intel_ddi_buf_trans *trans; 1109 int n_entries; 1110 1111 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1112 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1113 return; 1114 1115 iboost = trans->entries[level].hsw.i_boost; 1116 } 1117 1118 /* Make sure that the requested I_boost is valid */ 1119 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1120 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1121 return; 1122 } 1123 1124 _skl_ddi_set_iboost(display, encoder->port, iboost); 1125 1126 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1127 _skl_ddi_set_iboost(display, PORT_E, iboost); 1128 } 1129 1130 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1131 const struct intel_crtc_state *crtc_state) 1132 { 1133 struct intel_display *display = to_intel_display(intel_dp); 1134 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1135 int n_entries; 1136 1137 intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1138 1139 if (drm_WARN_ON(display->drm, n_entries < 1)) 1140 n_entries = 1; 1141 if (drm_WARN_ON(display->drm, 1142 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1143 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1144 1145 return index_to_dp_signal_levels[n_entries - 1] & 1146 DP_TRAIN_VOLTAGE_SWING_MASK; 1147 } 1148 1149 /* 1150 * We assume that the full set of pre-emphasis values can be 1151 * used on all DDI platforms. Should that change we need to 1152 * rethink this code. 1153 */ 1154 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1155 { 1156 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1157 } 1158 1159 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1160 int lane) 1161 { 1162 if (crtc_state->port_clock > 600000) 1163 return 0; 1164 1165 if (crtc_state->lane_count == 4) 1166 return lane >= 1 ? LOADGEN_SELECT : 0; 1167 else 1168 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1169 } 1170 1171 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1172 const struct intel_crtc_state *crtc_state) 1173 { 1174 struct intel_display *display = to_intel_display(encoder); 1175 const struct intel_ddi_buf_trans *trans; 1176 enum phy phy = intel_encoder_to_phy(encoder); 1177 int n_entries, ln; 1178 u32 val; 1179 1180 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1181 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1182 return; 1183 1184 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1185 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1186 1187 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1188 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1189 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1190 intel_dp->hobl_active ? val : 0); 1191 } 1192 1193 /* Set PORT_TX_DW5 */ 1194 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1195 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1196 COEFF_POLARITY | CURSOR_PROGRAM | 1197 TAP2_DISABLE | TAP3_DISABLE); 1198 val |= SCALING_MODE_SEL(0x2); 1199 val |= RTERM_SELECT(0x6); 1200 val |= TAP3_DISABLE; 1201 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1202 1203 /* Program PORT_TX_DW2 */ 1204 for (ln = 0; ln < 4; ln++) { 1205 int level = intel_ddi_level(encoder, crtc_state, ln); 1206 1207 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1208 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1209 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1210 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1211 RCOMP_SCALAR(0x98)); 1212 } 1213 1214 /* Program PORT_TX_DW4 */ 1215 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1216 for (ln = 0; ln < 4; ln++) { 1217 int level = intel_ddi_level(encoder, crtc_state, ln); 1218 1219 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1220 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1221 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1222 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1223 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1224 } 1225 1226 /* Program PORT_TX_DW7 */ 1227 for (ln = 0; ln < 4; ln++) { 1228 int level = intel_ddi_level(encoder, crtc_state, ln); 1229 1230 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1231 N_SCALAR_MASK, 1232 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1233 } 1234 } 1235 1236 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1237 const struct intel_crtc_state *crtc_state) 1238 { 1239 struct intel_display *display = to_intel_display(encoder); 1240 enum phy phy = intel_encoder_to_phy(encoder); 1241 u32 val; 1242 int ln; 1243 1244 /* 1245 * 1. If port type is eDP or DP, 1246 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1247 * else clear to 0b. 1248 */ 1249 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1250 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1251 val &= ~COMMON_KEEPER_EN; 1252 else 1253 val |= COMMON_KEEPER_EN; 1254 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1255 1256 /* 2. Program loadgen select */ 1257 /* 1258 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1259 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1260 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1261 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1262 */ 1263 for (ln = 0; ln < 4; ln++) { 1264 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1265 LOADGEN_SELECT, 1266 icl_combo_phy_loadgen_select(crtc_state, ln)); 1267 } 1268 1269 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1270 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1271 0, SUS_CLOCK_CONFIG); 1272 1273 /* 4. Clear training enable to change swing values */ 1274 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1275 val &= ~TX_TRAINING_EN; 1276 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1277 1278 /* 5. Program swing and de-emphasis */ 1279 icl_ddi_combo_vswing_program(encoder, crtc_state); 1280 1281 /* 6. Set training enable to trigger update */ 1282 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1283 val |= TX_TRAINING_EN; 1284 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1285 } 1286 1287 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1288 const struct intel_crtc_state *crtc_state) 1289 { 1290 struct intel_display *display = to_intel_display(encoder); 1291 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1292 const struct intel_ddi_buf_trans *trans; 1293 int n_entries, ln; 1294 1295 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1296 return; 1297 1298 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1299 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1300 return; 1301 1302 for (ln = 0; ln < 2; ln++) { 1303 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1304 CRI_USE_FS32, 0); 1305 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1306 CRI_USE_FS32, 0); 1307 } 1308 1309 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1310 for (ln = 0; ln < 2; ln++) { 1311 int level; 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1314 1315 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1316 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1317 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1318 1319 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1320 1321 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1322 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1323 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1324 } 1325 1326 /* Program MG_TX_DRVCTRL with values from vswing table */ 1327 for (ln = 0; ln < 2; ln++) { 1328 int level; 1329 1330 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1331 1332 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1333 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1334 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1335 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1336 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1337 CRI_TXDEEMPH_OVERRIDE_EN); 1338 1339 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1340 1341 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1342 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1343 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1344 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1345 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1346 CRI_TXDEEMPH_OVERRIDE_EN); 1347 1348 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1349 } 1350 1351 /* 1352 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1353 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1354 * values from table for which TX1 and TX2 enabled. 1355 */ 1356 for (ln = 0; ln < 2; ln++) { 1357 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1358 CFG_LOW_RATE_LKREN_EN, 1359 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1360 } 1361 1362 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1363 for (ln = 0; ln < 2; ln++) { 1364 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1365 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1366 CFG_AMI_CK_DIV_OVERRIDE_EN, 1367 crtc_state->port_clock > 500000 ? 1368 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1369 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1370 1371 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1372 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1373 CFG_AMI_CK_DIV_OVERRIDE_EN, 1374 crtc_state->port_clock > 500000 ? 1375 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1376 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1377 } 1378 1379 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1380 for (ln = 0; ln < 2; ln++) { 1381 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1382 0, CRI_CALCINIT); 1383 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1384 0, CRI_CALCINIT); 1385 } 1386 } 1387 1388 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1389 const struct intel_crtc_state *crtc_state) 1390 { 1391 struct intel_display *display = to_intel_display(encoder); 1392 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1393 const struct intel_ddi_buf_trans *trans; 1394 int n_entries, ln; 1395 1396 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1397 return; 1398 1399 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1400 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1401 return; 1402 1403 for (ln = 0; ln < 2; ln++) { 1404 int level; 1405 1406 /* Wa_16011342517:adl-p */ 1407 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011342517)) { 1408 if ((intel_encoder_is_hdmi(encoder) && 1409 crtc_state->port_clock == 594000) || 1410 (intel_encoder_is_dp(encoder) && 1411 crtc_state->port_clock == 162000)) { 1412 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1413 LOADGEN_SHARING_PMD_DISABLE, 1); 1414 } else { 1415 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1416 LOADGEN_SHARING_PMD_DISABLE, 0); 1417 } 1418 } 1419 1420 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1421 1422 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1423 1424 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1425 DKL_TX_PRESHOOT_COEFF_MASK | 1426 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1427 DKL_TX_VSWING_CONTROL_MASK, 1428 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1429 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1430 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1431 1432 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1433 1434 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1435 DKL_TX_PRESHOOT_COEFF_MASK | 1436 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1437 DKL_TX_VSWING_CONTROL_MASK, 1438 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1439 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1440 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1441 1442 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1443 DKL_TX_DP20BITMODE, 0); 1444 1445 if (display->platform.alderlake_p) { 1446 u32 val; 1447 1448 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1449 if (ln == 0) { 1450 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1451 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1452 } else { 1453 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1454 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1455 } 1456 } else { 1457 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1458 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1459 } 1460 1461 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1462 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1463 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1464 val); 1465 } 1466 } 1467 } 1468 1469 static int translate_signal_level(struct intel_dp *intel_dp, 1470 u8 signal_levels) 1471 { 1472 struct intel_display *display = to_intel_display(intel_dp); 1473 const u8 *signal_array; 1474 size_t array_size; 1475 int i; 1476 1477 signal_array = index_to_dp_signal_levels; 1478 array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1479 1480 for (i = 0; i < array_size; i++) { 1481 if (signal_array[i] == signal_levels) 1482 return i; 1483 } 1484 1485 drm_WARN(display->drm, 1, 1486 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1487 signal_levels); 1488 1489 return 0; 1490 } 1491 1492 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1493 const struct intel_crtc_state *crtc_state, 1494 int lane) 1495 { 1496 u8 train_set = intel_dp->train_set[lane]; 1497 1498 if (intel_dp_is_uhbr(crtc_state)) { 1499 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1500 } else { 1501 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1502 DP_TRAIN_PRE_EMPHASIS_MASK); 1503 1504 return translate_signal_level(intel_dp, signal_levels); 1505 } 1506 } 1507 1508 int intel_ddi_level(struct intel_encoder *encoder, 1509 const struct intel_crtc_state *crtc_state, 1510 int lane) 1511 { 1512 struct intel_display *display = to_intel_display(encoder); 1513 const struct intel_ddi_buf_trans *trans; 1514 int level, n_entries; 1515 1516 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1517 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1518 return 0; 1519 1520 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1521 level = intel_ddi_hdmi_level(encoder, trans); 1522 else 1523 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1524 lane); 1525 1526 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1527 level = n_entries - 1; 1528 1529 return level; 1530 } 1531 1532 static void 1533 hsw_set_signal_levels(struct intel_encoder *encoder, 1534 const struct intel_crtc_state *crtc_state) 1535 { 1536 struct intel_display *display = to_intel_display(encoder); 1537 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1538 int level = intel_ddi_level(encoder, crtc_state, 0); 1539 enum port port = encoder->port; 1540 u32 signal_levels; 1541 1542 if (has_iboost(display)) 1543 skl_ddi_set_iboost(encoder, crtc_state, level); 1544 1545 /* HDMI ignores the rest */ 1546 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1547 return; 1548 1549 signal_levels = DDI_BUF_TRANS_SELECT(level); 1550 1551 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1552 signal_levels); 1553 1554 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1555 intel_dp->DP |= signal_levels; 1556 1557 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1558 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1559 } 1560 1561 static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg, 1562 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1563 { 1564 mutex_lock(&display->dpll.lock); 1565 1566 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1567 1568 /* 1569 * "This step and the step before must be 1570 * done with separate register writes." 1571 */ 1572 intel_de_rmw(display, reg, clk_off, 0); 1573 1574 mutex_unlock(&display->dpll.lock); 1575 } 1576 1577 static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg, 1578 u32 clk_off) 1579 { 1580 mutex_lock(&display->dpll.lock); 1581 1582 intel_de_rmw(display, reg, 0, clk_off); 1583 1584 mutex_unlock(&display->dpll.lock); 1585 } 1586 1587 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg, 1588 u32 clk_off) 1589 { 1590 return !(intel_de_read(display, reg) & clk_off); 1591 } 1592 1593 static struct intel_dpll * 1594 _icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg, 1595 u32 clk_sel_mask, u32 clk_sel_shift) 1596 { 1597 enum intel_dpll_id id; 1598 1599 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1600 1601 return intel_get_dpll_by_id(display, id); 1602 } 1603 1604 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1605 const struct intel_crtc_state *crtc_state) 1606 { 1607 struct intel_display *display = to_intel_display(encoder); 1608 const struct intel_dpll *pll = crtc_state->intel_dpll; 1609 enum phy phy = intel_encoder_to_phy(encoder); 1610 1611 if (drm_WARN_ON(display->drm, !pll)) 1612 return; 1613 1614 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1615 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1616 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1617 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1618 } 1619 1620 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1621 { 1622 struct intel_display *display = to_intel_display(encoder); 1623 enum phy phy = intel_encoder_to_phy(encoder); 1624 1625 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1626 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1627 } 1628 1629 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1630 { 1631 struct intel_display *display = to_intel_display(encoder); 1632 enum phy phy = intel_encoder_to_phy(encoder); 1633 1634 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1635 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1636 } 1637 1638 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1639 { 1640 struct intel_display *display = to_intel_display(encoder); 1641 enum phy phy = intel_encoder_to_phy(encoder); 1642 1643 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1644 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1645 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1646 } 1647 1648 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1649 const struct intel_crtc_state *crtc_state) 1650 { 1651 struct intel_display *display = to_intel_display(encoder); 1652 const struct intel_dpll *pll = crtc_state->intel_dpll; 1653 enum phy phy = intel_encoder_to_phy(encoder); 1654 1655 if (drm_WARN_ON(display->drm, !pll)) 1656 return; 1657 1658 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1659 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1661 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1662 } 1663 1664 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1665 { 1666 struct intel_display *display = to_intel_display(encoder); 1667 enum phy phy = intel_encoder_to_phy(encoder); 1668 1669 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1670 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1671 } 1672 1673 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1674 { 1675 struct intel_display *display = to_intel_display(encoder); 1676 enum phy phy = intel_encoder_to_phy(encoder); 1677 1678 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1679 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1680 } 1681 1682 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1683 { 1684 struct intel_display *display = to_intel_display(encoder); 1685 enum phy phy = intel_encoder_to_phy(encoder); 1686 1687 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1688 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1689 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1690 } 1691 1692 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1693 const struct intel_crtc_state *crtc_state) 1694 { 1695 struct intel_display *display = to_intel_display(encoder); 1696 const struct intel_dpll *pll = crtc_state->intel_dpll; 1697 enum phy phy = intel_encoder_to_phy(encoder); 1698 1699 if (drm_WARN_ON(display->drm, !pll)) 1700 return; 1701 1702 /* 1703 * If we fail this, something went very wrong: first 2 PLLs should be 1704 * used by first 2 phys and last 2 PLLs by last phys 1705 */ 1706 if (drm_WARN_ON(display->drm, 1707 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1708 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1709 return; 1710 1711 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1712 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1713 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1714 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1715 } 1716 1717 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1718 { 1719 struct intel_display *display = to_intel_display(encoder); 1720 enum phy phy = intel_encoder_to_phy(encoder); 1721 1722 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1723 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1724 } 1725 1726 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1727 { 1728 struct intel_display *display = to_intel_display(encoder); 1729 enum phy phy = intel_encoder_to_phy(encoder); 1730 1731 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1732 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1733 } 1734 1735 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1736 { 1737 struct intel_display *display = to_intel_display(encoder); 1738 enum phy phy = intel_encoder_to_phy(encoder); 1739 enum intel_dpll_id id; 1740 u32 val; 1741 1742 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1743 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1744 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1745 id = val; 1746 1747 /* 1748 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1749 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1750 * bit for phy C and D. 1751 */ 1752 if (phy >= PHY_C) 1753 id += DPLL_ID_DG1_DPLL2; 1754 1755 return intel_get_dpll_by_id(display, id); 1756 } 1757 1758 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1759 const struct intel_crtc_state *crtc_state) 1760 { 1761 struct intel_display *display = to_intel_display(encoder); 1762 const struct intel_dpll *pll = crtc_state->intel_dpll; 1763 enum phy phy = intel_encoder_to_phy(encoder); 1764 1765 if (drm_WARN_ON(display->drm, !pll)) 1766 return; 1767 1768 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1769 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1771 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1772 } 1773 1774 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1775 { 1776 struct intel_display *display = to_intel_display(encoder); 1777 enum phy phy = intel_encoder_to_phy(encoder); 1778 1779 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1780 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1781 } 1782 1783 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1784 { 1785 struct intel_display *display = to_intel_display(encoder); 1786 enum phy phy = intel_encoder_to_phy(encoder); 1787 1788 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1789 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1790 } 1791 1792 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1793 { 1794 struct intel_display *display = to_intel_display(encoder); 1795 enum phy phy = intel_encoder_to_phy(encoder); 1796 1797 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1798 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1799 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1800 } 1801 1802 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1803 const struct intel_crtc_state *crtc_state) 1804 { 1805 struct intel_display *display = to_intel_display(encoder); 1806 const struct intel_dpll *pll = crtc_state->intel_dpll; 1807 enum port port = encoder->port; 1808 1809 if (drm_WARN_ON(display->drm, !pll)) 1810 return; 1811 1812 /* 1813 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1814 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1815 */ 1816 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1817 1818 icl_ddi_combo_enable_clock(encoder, crtc_state); 1819 } 1820 1821 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1822 { 1823 struct intel_display *display = to_intel_display(encoder); 1824 enum port port = encoder->port; 1825 1826 icl_ddi_combo_disable_clock(encoder); 1827 1828 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1829 } 1830 1831 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1832 { 1833 struct intel_display *display = to_intel_display(encoder); 1834 enum port port = encoder->port; 1835 u32 tmp; 1836 1837 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1838 1839 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1840 return false; 1841 1842 return icl_ddi_combo_is_clock_enabled(encoder); 1843 } 1844 1845 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1846 const struct intel_crtc_state *crtc_state) 1847 { 1848 struct intel_display *display = to_intel_display(encoder); 1849 const struct intel_dpll *pll = crtc_state->intel_dpll; 1850 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1851 enum port port = encoder->port; 1852 1853 if (drm_WARN_ON(display->drm, !pll)) 1854 return; 1855 1856 intel_de_write(display, DDI_CLK_SEL(port), 1857 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1858 1859 mutex_lock(&display->dpll.lock); 1860 1861 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1862 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1863 1864 mutex_unlock(&display->dpll.lock); 1865 } 1866 1867 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1868 { 1869 struct intel_display *display = to_intel_display(encoder); 1870 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1871 enum port port = encoder->port; 1872 1873 mutex_lock(&display->dpll.lock); 1874 1875 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1876 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1877 1878 mutex_unlock(&display->dpll.lock); 1879 1880 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1881 } 1882 1883 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1884 { 1885 struct intel_display *display = to_intel_display(encoder); 1886 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1887 enum port port = encoder->port; 1888 u32 tmp; 1889 1890 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1891 1892 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1893 return false; 1894 1895 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1896 1897 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1898 } 1899 1900 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1901 { 1902 struct intel_display *display = to_intel_display(encoder); 1903 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1904 enum port port = encoder->port; 1905 enum intel_dpll_id id; 1906 u32 tmp; 1907 1908 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1909 1910 switch (tmp & DDI_CLK_SEL_MASK) { 1911 case DDI_CLK_SEL_TBT_162: 1912 case DDI_CLK_SEL_TBT_270: 1913 case DDI_CLK_SEL_TBT_540: 1914 case DDI_CLK_SEL_TBT_810: 1915 id = DPLL_ID_ICL_TBTPLL; 1916 break; 1917 case DDI_CLK_SEL_MG: 1918 id = icl_tc_port_to_pll_id(tc_port); 1919 break; 1920 default: 1921 MISSING_CASE(tmp); 1922 fallthrough; 1923 case DDI_CLK_SEL_NONE: 1924 return NULL; 1925 } 1926 1927 return intel_get_dpll_by_id(display, id); 1928 } 1929 1930 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1931 { 1932 struct intel_display *display = to_intel_display(encoder->base.dev); 1933 enum intel_dpll_id id; 1934 1935 switch (encoder->port) { 1936 case PORT_A: 1937 id = DPLL_ID_SKL_DPLL0; 1938 break; 1939 case PORT_B: 1940 id = DPLL_ID_SKL_DPLL1; 1941 break; 1942 case PORT_C: 1943 id = DPLL_ID_SKL_DPLL2; 1944 break; 1945 default: 1946 MISSING_CASE(encoder->port); 1947 return NULL; 1948 } 1949 1950 return intel_get_dpll_by_id(display, id); 1951 } 1952 1953 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1954 const struct intel_crtc_state *crtc_state) 1955 { 1956 struct intel_display *display = to_intel_display(encoder); 1957 const struct intel_dpll *pll = crtc_state->intel_dpll; 1958 enum port port = encoder->port; 1959 1960 if (drm_WARN_ON(display->drm, !pll)) 1961 return; 1962 1963 mutex_lock(&display->dpll.lock); 1964 1965 intel_de_rmw(display, DPLL_CTRL2, 1966 DPLL_CTRL2_DDI_CLK_OFF(port) | 1967 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1968 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1969 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1970 1971 mutex_unlock(&display->dpll.lock); 1972 } 1973 1974 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1975 { 1976 struct intel_display *display = to_intel_display(encoder); 1977 enum port port = encoder->port; 1978 1979 mutex_lock(&display->dpll.lock); 1980 1981 intel_de_rmw(display, DPLL_CTRL2, 1982 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1983 1984 mutex_unlock(&display->dpll.lock); 1985 } 1986 1987 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1988 { 1989 struct intel_display *display = to_intel_display(encoder); 1990 enum port port = encoder->port; 1991 1992 /* 1993 * FIXME Not sure if the override affects both 1994 * the PLL selection and the CLK_OFF bit. 1995 */ 1996 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1997 } 1998 1999 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 2000 { 2001 struct intel_display *display = to_intel_display(encoder); 2002 enum port port = encoder->port; 2003 enum intel_dpll_id id; 2004 u32 tmp; 2005 2006 tmp = intel_de_read(display, DPLL_CTRL2); 2007 2008 /* 2009 * FIXME Not sure if the override affects both 2010 * the PLL selection and the CLK_OFF bit. 2011 */ 2012 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2013 return NULL; 2014 2015 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2016 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2017 2018 return intel_get_dpll_by_id(display, id); 2019 } 2020 2021 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2022 const struct intel_crtc_state *crtc_state) 2023 { 2024 struct intel_display *display = to_intel_display(encoder); 2025 const struct intel_dpll *pll = crtc_state->intel_dpll; 2026 enum port port = encoder->port; 2027 2028 if (drm_WARN_ON(display->drm, !pll)) 2029 return; 2030 2031 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2032 } 2033 2034 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2035 { 2036 struct intel_display *display = to_intel_display(encoder); 2037 enum port port = encoder->port; 2038 2039 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2040 } 2041 2042 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2043 { 2044 struct intel_display *display = to_intel_display(encoder); 2045 enum port port = encoder->port; 2046 2047 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2048 } 2049 2050 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2051 { 2052 struct intel_display *display = to_intel_display(encoder); 2053 enum port port = encoder->port; 2054 enum intel_dpll_id id; 2055 u32 tmp; 2056 2057 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2058 2059 switch (tmp & PORT_CLK_SEL_MASK) { 2060 case PORT_CLK_SEL_WRPLL1: 2061 id = DPLL_ID_WRPLL1; 2062 break; 2063 case PORT_CLK_SEL_WRPLL2: 2064 id = DPLL_ID_WRPLL2; 2065 break; 2066 case PORT_CLK_SEL_SPLL: 2067 id = DPLL_ID_SPLL; 2068 break; 2069 case PORT_CLK_SEL_LCPLL_810: 2070 id = DPLL_ID_LCPLL_810; 2071 break; 2072 case PORT_CLK_SEL_LCPLL_1350: 2073 id = DPLL_ID_LCPLL_1350; 2074 break; 2075 case PORT_CLK_SEL_LCPLL_2700: 2076 id = DPLL_ID_LCPLL_2700; 2077 break; 2078 default: 2079 MISSING_CASE(tmp); 2080 fallthrough; 2081 case PORT_CLK_SEL_NONE: 2082 return NULL; 2083 } 2084 2085 return intel_get_dpll_by_id(display, id); 2086 } 2087 2088 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2089 const struct intel_crtc_state *crtc_state) 2090 { 2091 if (encoder->enable_clock) 2092 encoder->enable_clock(encoder, crtc_state); 2093 } 2094 2095 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2096 { 2097 if (encoder->disable_clock) 2098 encoder->disable_clock(encoder); 2099 } 2100 2101 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2102 { 2103 struct intel_display *display = to_intel_display(encoder); 2104 u32 port_mask; 2105 bool ddi_clk_needed; 2106 2107 /* 2108 * In case of DP MST, we sanitize the primary encoder only, not the 2109 * virtual ones. 2110 */ 2111 if (encoder->type == INTEL_OUTPUT_DP_MST) 2112 return; 2113 2114 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2115 u8 pipe_mask; 2116 bool is_mst; 2117 2118 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2119 /* 2120 * In the unlikely case that BIOS enables DP in MST mode, just 2121 * warn since our MST HW readout is incomplete. 2122 */ 2123 if (drm_WARN_ON(display->drm, is_mst)) 2124 return; 2125 } 2126 2127 port_mask = BIT(encoder->port); 2128 ddi_clk_needed = encoder->base.crtc; 2129 2130 if (encoder->type == INTEL_OUTPUT_DSI) { 2131 struct intel_encoder *other_encoder; 2132 2133 port_mask = intel_dsi_encoder_ports(encoder); 2134 /* 2135 * Sanity check that we haven't incorrectly registered another 2136 * encoder using any of the ports of this DSI encoder. 2137 */ 2138 for_each_intel_encoder(display->drm, other_encoder) { 2139 if (other_encoder == encoder) 2140 continue; 2141 2142 if (drm_WARN_ON(display->drm, 2143 port_mask & BIT(other_encoder->port))) 2144 return; 2145 } 2146 /* 2147 * For DSI we keep the ddi clocks gated 2148 * except during enable/disable sequence. 2149 */ 2150 ddi_clk_needed = false; 2151 } 2152 2153 if (ddi_clk_needed || !encoder->is_clock_enabled || 2154 !encoder->is_clock_enabled(encoder)) 2155 return; 2156 2157 drm_dbg_kms(display->drm, 2158 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2159 encoder->base.base.id, encoder->base.name); 2160 2161 encoder->disable_clock(encoder); 2162 } 2163 2164 static void 2165 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2166 enum tc_port tc_port, u32 ln0, u32 ln1) 2167 { 2168 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2169 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2170 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2171 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2172 } 2173 2174 static void 2175 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2176 const struct intel_crtc_state *crtc_state) 2177 { 2178 struct intel_display *display = to_intel_display(crtc_state); 2179 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2180 enum intel_tc_pin_assignment pin_assignment; 2181 u32 ln0, ln1; 2182 u8 width; 2183 2184 if (DISPLAY_VER(display) >= 14) 2185 return; 2186 2187 if (!intel_encoder_is_tc(&dig_port->base) || 2188 intel_tc_port_in_tbt_alt_mode(dig_port)) 2189 return; 2190 2191 if (DISPLAY_VER(display) >= 12) { 2192 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2193 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2194 } else { 2195 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2196 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2197 } 2198 2199 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2200 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2201 2202 /* DPPATC */ 2203 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2204 width = crtc_state->lane_count; 2205 2206 switch (pin_assignment) { 2207 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2208 drm_WARN_ON(display->drm, 2209 !intel_tc_port_in_legacy_mode(dig_port)); 2210 if (width == 1) { 2211 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2212 } else { 2213 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2214 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2215 } 2216 break; 2217 case INTEL_TC_PIN_ASSIGNMENT_A: 2218 if (width == 4) { 2219 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2220 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2221 } 2222 break; 2223 case INTEL_TC_PIN_ASSIGNMENT_B: 2224 if (width == 2) { 2225 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2227 } 2228 break; 2229 case INTEL_TC_PIN_ASSIGNMENT_C: 2230 case INTEL_TC_PIN_ASSIGNMENT_E: 2231 if (width == 1) { 2232 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2233 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2234 } else { 2235 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2236 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2237 } 2238 break; 2239 case INTEL_TC_PIN_ASSIGNMENT_D: 2240 case INTEL_TC_PIN_ASSIGNMENT_F: 2241 if (width == 1) { 2242 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2243 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2244 } else { 2245 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2246 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2247 } 2248 break; 2249 default: 2250 MISSING_CASE(pin_assignment); 2251 } 2252 2253 if (DISPLAY_VER(display) >= 12) { 2254 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2255 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2256 /* WA_14018221282 */ 2257 if (IS_DISPLAY_VER(display, 12, 13)) 2258 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2259 2260 } else { 2261 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2262 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2263 } 2264 } 2265 2266 static enum transcoder 2267 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2268 { 2269 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2270 return crtc_state->mst_master_transcoder; 2271 else 2272 return crtc_state->cpu_transcoder; 2273 } 2274 2275 intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2276 const struct intel_crtc_state *crtc_state) 2277 { 2278 struct intel_display *display = to_intel_display(encoder); 2279 2280 if (DISPLAY_VER(display) >= 12) 2281 return TGL_DP_TP_CTL(display, 2282 tgl_dp_tp_transcoder(crtc_state)); 2283 else 2284 return DP_TP_CTL(encoder->port); 2285 } 2286 2287 static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2288 const struct intel_crtc_state *crtc_state) 2289 { 2290 struct intel_display *display = to_intel_display(encoder); 2291 2292 if (DISPLAY_VER(display) >= 12) 2293 return TGL_DP_TP_STATUS(display, 2294 tgl_dp_tp_transcoder(crtc_state)); 2295 else 2296 return DP_TP_STATUS(encoder->port); 2297 } 2298 2299 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2300 const struct intel_crtc_state *crtc_state) 2301 { 2302 struct intel_display *display = to_intel_display(encoder); 2303 2304 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2305 DP_TP_STATUS_ACT_SENT); 2306 } 2307 2308 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2309 const struct intel_crtc_state *crtc_state) 2310 { 2311 struct intel_display *display = to_intel_display(encoder); 2312 2313 if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2314 DP_TP_STATUS_ACT_SENT, 1)) 2315 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2316 } 2317 2318 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2319 const struct intel_crtc_state *crtc_state, 2320 bool enable) 2321 { 2322 struct intel_display *display = to_intel_display(intel_dp); 2323 2324 if (!crtc_state->vrr.enable) 2325 return; 2326 2327 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2328 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2329 drm_dbg_kms(display->drm, 2330 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2331 str_enable_disable(enable)); 2332 } 2333 2334 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2335 const struct intel_crtc_state *crtc_state, 2336 bool enable) 2337 { 2338 struct intel_display *display = to_intel_display(intel_dp); 2339 2340 if (!crtc_state->fec_enable) 2341 return; 2342 2343 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2344 enable ? DP_FEC_READY : 0) <= 0) 2345 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2346 str_enabled_disabled(enable)); 2347 2348 if (enable && 2349 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2350 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2351 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2352 } 2353 2354 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2355 { 2356 struct intel_display *display = to_intel_display(aux->drm_dev); 2357 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2358 u8 status = 0; 2359 int ret, err; 2360 2361 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2362 err || (status & mask), 2363 10 * 1000, 200 * 1000, false); 2364 2365 /* Either can be non-zero, but not both */ 2366 ret = ret ?: err; 2367 if (ret) { 2368 drm_dbg_kms(display->drm, 2369 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2370 str_enabled_disabled(enabled), ret, status); 2371 return ret; 2372 } 2373 2374 return 0; 2375 } 2376 2377 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2378 const struct intel_crtc_state *crtc_state, 2379 bool enabled) 2380 { 2381 struct intel_display *display = to_intel_display(encoder); 2382 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2383 int ret; 2384 2385 if (!crtc_state->fec_enable) 2386 return 0; 2387 2388 if (enabled) 2389 ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2390 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2391 else 2392 ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state), 2393 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2394 2395 if (ret) { 2396 drm_err(display->drm, 2397 "Timeout waiting for FEC live state to get %s\n", 2398 str_enabled_disabled(enabled)); 2399 return ret; 2400 } 2401 /* 2402 * At least the Synoptics MST hub doesn't set the detected flag for 2403 * FEC decoding disabling so skip waiting for that. 2404 */ 2405 if (enabled) { 2406 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2407 if (ret) 2408 return ret; 2409 } 2410 2411 return 0; 2412 } 2413 2414 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2415 const struct intel_crtc_state *crtc_state) 2416 { 2417 struct intel_display *display = to_intel_display(encoder); 2418 int i; 2419 int ret; 2420 2421 if (!crtc_state->fec_enable) 2422 return; 2423 2424 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2425 0, DP_TP_CTL_FEC_ENABLE); 2426 2427 if (DISPLAY_VER(display) < 30) 2428 return; 2429 2430 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2431 if (!ret) 2432 return; 2433 2434 for (i = 0; i < 3; i++) { 2435 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2436 2437 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2438 DP_TP_CTL_FEC_ENABLE, 0); 2439 2440 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2441 if (ret) 2442 continue; 2443 2444 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2445 0, DP_TP_CTL_FEC_ENABLE); 2446 2447 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2448 if (!ret) 2449 return; 2450 } 2451 2452 drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); 2453 } 2454 2455 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2456 const struct intel_crtc_state *crtc_state) 2457 { 2458 struct intel_display *display = to_intel_display(encoder); 2459 2460 if (!crtc_state->fec_enable) 2461 return; 2462 2463 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2464 DP_TP_CTL_FEC_ENABLE, 0); 2465 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2466 } 2467 2468 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2469 const struct intel_crtc_state *crtc_state) 2470 { 2471 struct intel_display *display = to_intel_display(encoder); 2472 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2473 2474 if (intel_encoder_is_combo(encoder)) { 2475 enum phy phy = intel_encoder_to_phy(encoder); 2476 2477 intel_combo_phy_power_up_lanes(display, phy, false, 2478 crtc_state->lane_count, 2479 dig_port->lane_reversal); 2480 } 2481 } 2482 2483 /* 2484 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2485 * platforms. 2486 */ 2487 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2488 { 2489 if (DISPLAY_VER(display) > 20) 2490 return ~0; 2491 else if (display->platform.alderlake_p) 2492 return BIT(PIPE_A) | BIT(PIPE_B); 2493 else 2494 return BIT(PIPE_A); 2495 } 2496 2497 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2498 struct intel_crtc_state *pipe_config) 2499 { 2500 struct intel_display *display = to_intel_display(pipe_config); 2501 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2502 enum pipe pipe = crtc->pipe; 2503 u32 dss1; 2504 2505 if (!HAS_MSO(display)) 2506 return; 2507 2508 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2509 2510 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2511 if (!pipe_config->splitter.enable) 2512 return; 2513 2514 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2515 pipe_config->splitter.enable = false; 2516 return; 2517 } 2518 2519 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2520 default: 2521 drm_WARN(display->drm, true, 2522 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2523 fallthrough; 2524 case SPLITTER_CONFIGURATION_2_SEGMENT: 2525 pipe_config->splitter.link_count = 2; 2526 break; 2527 case SPLITTER_CONFIGURATION_4_SEGMENT: 2528 pipe_config->splitter.link_count = 4; 2529 break; 2530 } 2531 2532 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2533 } 2534 2535 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2536 { 2537 struct intel_display *display = to_intel_display(crtc_state); 2538 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2539 enum pipe pipe = crtc->pipe; 2540 u32 dss1 = 0; 2541 2542 if (!HAS_MSO(display)) 2543 return; 2544 2545 if (crtc_state->splitter.enable) { 2546 dss1 |= SPLITTER_ENABLE; 2547 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2548 if (crtc_state->splitter.link_count == 2) 2549 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2550 else 2551 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2552 } 2553 2554 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2555 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2556 OVERLAP_PIXELS_MASK, dss1); 2557 } 2558 2559 static void 2560 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2561 { 2562 struct intel_display *display = to_intel_display(encoder); 2563 enum port port = encoder->port; 2564 intel_reg_t reg; 2565 u32 set_bits, wait_bits; 2566 int ret; 2567 2568 if (DISPLAY_VER(display) < 14) 2569 return; 2570 2571 if (DISPLAY_VER(display) >= 20) { 2572 reg = DDI_BUF_CTL(port); 2573 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2574 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2575 } else { 2576 reg = XELPDP_PORT_BUF_CTL1(display, port); 2577 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2578 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2579 } 2580 2581 intel_de_rmw(display, reg, 0, set_bits); 2582 2583 ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100); 2584 if (ret) { 2585 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2586 port_name(port)); 2587 } 2588 } 2589 2590 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2591 const struct intel_crtc_state *crtc_state) 2592 { 2593 struct intel_display *display = to_intel_display(encoder); 2594 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2595 enum port port = encoder->port; 2596 u32 val = 0; 2597 2598 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2599 2600 if (intel_dp_is_uhbr(crtc_state)) 2601 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2602 else 2603 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2604 2605 if (dig_port->lane_reversal) 2606 val |= XELPDP_PORT_REVERSAL; 2607 2608 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2609 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2610 val); 2611 } 2612 2613 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2614 { 2615 struct intel_display *display = to_intel_display(encoder); 2616 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2617 u32 val; 2618 2619 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2620 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2621 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2622 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2623 } 2624 2625 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2626 struct intel_encoder *encoder, 2627 const struct intel_crtc_state *crtc_state, 2628 const struct drm_connector_state *conn_state) 2629 { 2630 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2631 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2632 bool transparent_mode; 2633 int ret; 2634 2635 intel_dp_set_link_params(intel_dp, 2636 crtc_state->port_clock, 2637 crtc_state->lane_count); 2638 2639 /* 2640 * We only configure what the register value will be here. Actual 2641 * enabling happens during link training farther down. 2642 */ 2643 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2644 2645 /* 2646 * 1. Enable Power Wells 2647 * 2648 * This was handled at the beginning of intel_atomic_commit_tail(), 2649 * before we called down into this function. 2650 */ 2651 2652 /* 2. PMdemand was already set */ 2653 2654 /* 3. Select Thunderbolt */ 2655 mtl_port_buf_ctl_io_selection(encoder); 2656 2657 /* 5. Enable the port PLL */ 2658 intel_ddi_enable_clock(encoder, crtc_state); 2659 2660 /* 2661 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2662 * Transcoder. 2663 */ 2664 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2665 2666 /* 2667 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2668 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2669 * Transport Select 2670 */ 2671 intel_ddi_config_transcoder_func(encoder, crtc_state); 2672 2673 /* 2674 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2675 */ 2676 intel_ddi_mso_configure(crtc_state); 2677 2678 if (!is_mst) 2679 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2680 2681 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2682 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2683 2684 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2685 if (!is_mst) 2686 intel_dp_sink_enable_decompression(state, 2687 to_intel_connector(conn_state->connector), 2688 crtc_state); 2689 2690 /* 2691 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2692 * in the FEC_CONFIGURATION register to 1 before initiating link 2693 * training 2694 */ 2695 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2696 2697 intel_dp_check_frl_training(intel_dp); 2698 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2699 2700 /* 2701 * 6. The rest of the below are substeps under the bspec's "Enable and 2702 * Train Display Port" step. Note that steps that are specific to 2703 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2704 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2705 * us when active_mst_links==0, so any steps designated for "single 2706 * stream or multi-stream master transcoder" can just be performed 2707 * unconditionally here. 2708 * 2709 * mtl_ddi_prepare_link_retrain() that is called by 2710 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2711 * 6.i and 6.j 2712 * 2713 * 6.k Follow DisplayPort specification training sequence (see notes for 2714 * failure handling) 2715 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2716 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2717 * (timeout after 800 us) 2718 */ 2719 intel_dp_start_link_train(state, intel_dp, crtc_state); 2720 2721 /* 6.n Set DP_TP_CTL link training to Normal */ 2722 if (!is_trans_port_sync_mode(crtc_state)) 2723 intel_dp_stop_link_train(intel_dp, crtc_state); 2724 2725 /* 6.o Configure and enable FEC if needed */ 2726 intel_ddi_enable_fec(encoder, crtc_state); 2727 2728 /* 7.a 128b/132b SST. */ 2729 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2730 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2731 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2732 if (ret < 0) 2733 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2734 } 2735 2736 if (!is_mst) 2737 intel_dsc_dp_pps_write(encoder, crtc_state); 2738 } 2739 2740 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2741 struct intel_encoder *encoder, 2742 const struct intel_crtc_state *crtc_state, 2743 const struct drm_connector_state *conn_state) 2744 { 2745 struct intel_display *display = to_intel_display(encoder); 2746 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2747 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2748 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2749 int ret; 2750 2751 intel_dp_set_link_params(intel_dp, 2752 crtc_state->port_clock, 2753 crtc_state->lane_count); 2754 2755 /* 2756 * We only configure what the register value will be here. Actual 2757 * enabling happens during link training farther down. 2758 */ 2759 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2760 2761 /* 2762 * 1. Enable Power Wells 2763 * 2764 * This was handled at the beginning of intel_atomic_commit_tail(), 2765 * before we called down into this function. 2766 */ 2767 2768 /* 2. Enable Panel Power if PPS is required */ 2769 intel_pps_on(intel_dp); 2770 2771 /* 2772 * 3. For non-TBT Type-C ports, set FIA lane count 2773 * (DFLEXDPSP.DPX4TXLATC) 2774 * 2775 * This was done before tgl_ddi_pre_enable_dp by 2776 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2777 */ 2778 2779 /* 2780 * 4. Enable the port PLL. 2781 * 2782 * The PLL enabling itself was already done before this function by 2783 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2784 * configure the PLL to port mapping here. 2785 */ 2786 intel_ddi_enable_clock(encoder, crtc_state); 2787 2788 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2789 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2790 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2791 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2792 dig_port->ddi_io_power_domain); 2793 } 2794 2795 /* 6. Program DP_MODE */ 2796 icl_program_mg_dp_mode(dig_port, crtc_state); 2797 2798 /* 2799 * 7. The rest of the below are substeps under the bspec's "Enable and 2800 * Train Display Port" step. Note that steps that are specific to 2801 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2802 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2803 * us when active_mst_links==0, so any steps designated for "single 2804 * stream or multi-stream master transcoder" can just be performed 2805 * unconditionally here. 2806 */ 2807 2808 /* 2809 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2810 * Transcoder. 2811 */ 2812 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2813 2814 /* 2815 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2816 * Transport Select 2817 */ 2818 intel_ddi_config_transcoder_func(encoder, crtc_state); 2819 2820 /* 2821 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2822 * selected 2823 * 2824 * This will be handled by the intel_dp_start_link_train() farther 2825 * down this function. 2826 */ 2827 2828 /* 7.e Configure voltage swing and related IO settings */ 2829 encoder->set_signal_levels(encoder, crtc_state); 2830 2831 /* 2832 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2833 * the used lanes of the DDI. 2834 */ 2835 intel_ddi_power_up_lanes(encoder, crtc_state); 2836 2837 /* 2838 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2839 */ 2840 intel_ddi_mso_configure(crtc_state); 2841 2842 if (!is_mst) 2843 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2844 2845 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2846 if (!is_mst) 2847 intel_dp_sink_enable_decompression(state, 2848 to_intel_connector(conn_state->connector), 2849 crtc_state); 2850 /* 2851 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2852 * in the FEC_CONFIGURATION register to 1 before initiating link 2853 * training 2854 */ 2855 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2856 2857 intel_dp_check_frl_training(intel_dp); 2858 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2859 2860 /* 2861 * 7.i Follow DisplayPort specification training sequence (see notes for 2862 * failure handling) 2863 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2864 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2865 * (timeout after 800 us) 2866 */ 2867 intel_dp_start_link_train(state, intel_dp, crtc_state); 2868 2869 /* 7.k Set DP_TP_CTL link training to Normal */ 2870 if (!is_trans_port_sync_mode(crtc_state)) 2871 intel_dp_stop_link_train(intel_dp, crtc_state); 2872 2873 /* 7.l Configure and enable FEC if needed */ 2874 intel_ddi_enable_fec(encoder, crtc_state); 2875 2876 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2877 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2878 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2879 if (ret < 0) 2880 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2881 } 2882 2883 if (!is_mst) 2884 intel_dsc_dp_pps_write(encoder, crtc_state); 2885 } 2886 2887 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2888 struct intel_encoder *encoder, 2889 const struct intel_crtc_state *crtc_state, 2890 const struct drm_connector_state *conn_state) 2891 { 2892 struct intel_display *display = to_intel_display(encoder); 2893 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2894 enum port port = encoder->port; 2895 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2896 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2897 2898 if (DISPLAY_VER(display) < 11) 2899 drm_WARN_ON(display->drm, 2900 is_mst && (port == PORT_A || port == PORT_E)); 2901 else 2902 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2903 2904 intel_dp_set_link_params(intel_dp, 2905 crtc_state->port_clock, 2906 crtc_state->lane_count); 2907 2908 /* 2909 * We only configure what the register value will be here. Actual 2910 * enabling happens during link training farther down. 2911 */ 2912 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2913 2914 intel_pps_on(intel_dp); 2915 2916 intel_ddi_enable_clock(encoder, crtc_state); 2917 2918 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2919 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2920 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2921 dig_port->ddi_io_power_domain); 2922 } 2923 2924 icl_program_mg_dp_mode(dig_port, crtc_state); 2925 2926 if (has_buf_trans_select(display)) 2927 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2928 2929 encoder->set_signal_levels(encoder, crtc_state); 2930 2931 intel_ddi_power_up_lanes(encoder, crtc_state); 2932 2933 if (!is_mst) 2934 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2935 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2936 if (!is_mst) 2937 intel_dp_sink_enable_decompression(state, 2938 to_intel_connector(conn_state->connector), 2939 crtc_state); 2940 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2941 intel_dp_start_link_train(state, intel_dp, crtc_state); 2942 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2943 !is_trans_port_sync_mode(crtc_state)) 2944 intel_dp_stop_link_train(intel_dp, crtc_state); 2945 2946 intel_ddi_enable_fec(encoder, crtc_state); 2947 2948 if (!is_mst) { 2949 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2950 intel_dsc_dp_pps_write(encoder, crtc_state); 2951 } 2952 } 2953 2954 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2955 struct intel_encoder *encoder, 2956 const struct intel_crtc_state *crtc_state, 2957 const struct drm_connector_state *conn_state) 2958 { 2959 struct intel_display *display = to_intel_display(encoder); 2960 2961 if (HAS_DP20(display)) 2962 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2963 crtc_state); 2964 2965 /* Panel replay has to be enabled in sink dpcd before link training. */ 2966 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2967 2968 if (DISPLAY_VER(display) >= 14) 2969 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2970 else if (DISPLAY_VER(display) >= 12) 2971 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2972 else 2973 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2974 2975 /* MST will call a setting of MSA after an allocating of Virtual Channel 2976 * from MST encoder pre_enable callback. 2977 */ 2978 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2979 intel_ddi_set_dp_msa(crtc_state, conn_state); 2980 } 2981 2982 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2983 struct intel_encoder *encoder, 2984 const struct intel_crtc_state *crtc_state, 2985 const struct drm_connector_state *conn_state) 2986 { 2987 struct intel_display *display = to_intel_display(encoder); 2988 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2989 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2990 2991 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2992 intel_ddi_enable_clock(encoder, crtc_state); 2993 2994 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2995 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2996 dig_port->ddi_io_power_domain); 2997 2998 icl_program_mg_dp_mode(dig_port, crtc_state); 2999 3000 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3001 3002 dig_port->set_infoframes(encoder, 3003 crtc_state->has_infoframe, 3004 crtc_state, conn_state); 3005 } 3006 3007 /* 3008 * Note: Also called from the ->pre_enable of the first active MST stream 3009 * encoder on its primary encoder. 3010 * 3011 * When called from DP MST code: 3012 * 3013 * - conn_state will be NULL 3014 * 3015 * - encoder will be the primary encoder (i.e. mst->primary) 3016 * 3017 * - the main connector associated with this port won't be active or linked to a 3018 * crtc 3019 * 3020 * - crtc_state will be the state of the first stream to be activated on this 3021 * port, and it may not be the same stream that will be deactivated last, but 3022 * each stream should have a state that is identical when it comes to the DP 3023 * link parameters. 3024 */ 3025 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3026 struct intel_encoder *encoder, 3027 const struct intel_crtc_state *crtc_state, 3028 const struct drm_connector_state *conn_state) 3029 { 3030 struct intel_display *display = to_intel_display(state); 3031 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3032 enum pipe pipe = crtc->pipe; 3033 3034 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3035 3036 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3037 3038 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3039 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3040 conn_state); 3041 } else { 3042 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3043 3044 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3045 conn_state); 3046 3047 /* FIXME precompute everything properly */ 3048 /* FIXME how do we turn infoframes off again? */ 3049 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3050 dig_port->set_infoframes(encoder, 3051 crtc_state->has_infoframe, 3052 crtc_state, conn_state); 3053 } 3054 } 3055 3056 static void 3057 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3058 { 3059 struct intel_display *display = to_intel_display(encoder); 3060 enum port port = encoder->port; 3061 intel_reg_t reg; 3062 u32 clr_bits, wait_bits; 3063 int ret; 3064 3065 if (DISPLAY_VER(display) < 14) 3066 return; 3067 3068 if (DISPLAY_VER(display) >= 20) { 3069 reg = DDI_BUF_CTL(port); 3070 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3071 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3072 } else { 3073 reg = XELPDP_PORT_BUF_CTL1(display, port); 3074 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3075 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3076 } 3077 3078 intel_de_rmw(display, reg, clr_bits, 0); 3079 3080 ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100); 3081 if (ret) 3082 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3083 port_name(port)); 3084 } 3085 3086 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3087 { 3088 struct intel_display *display = to_intel_display(encoder); 3089 enum port port = encoder->port; 3090 3091 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3092 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3093 3094 intel_wait_ddi_buf_active(encoder); 3095 } 3096 3097 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3098 const struct intel_crtc_state *crtc_state) 3099 { 3100 struct intel_display *display = to_intel_display(encoder); 3101 enum port port = encoder->port; 3102 3103 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3104 3105 if (DISPLAY_VER(display) >= 14) 3106 intel_wait_ddi_buf_idle(display, port); 3107 3108 mtl_ddi_disable_d2d(encoder); 3109 3110 if (intel_crtc_has_dp_encoder(crtc_state)) { 3111 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3112 DP_TP_CTL_ENABLE, 0); 3113 } 3114 3115 intel_ddi_disable_fec(encoder, crtc_state); 3116 3117 if (DISPLAY_VER(display) < 14) 3118 intel_wait_ddi_buf_idle(display, port); 3119 3120 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3121 } 3122 3123 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3124 struct intel_encoder *encoder, 3125 const struct intel_crtc_state *old_crtc_state, 3126 const struct drm_connector_state *old_conn_state) 3127 { 3128 struct intel_display *display = to_intel_display(encoder); 3129 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3130 struct intel_dp *intel_dp = &dig_port->dp; 3131 struct ref_tracker *wakeref; 3132 bool is_mst = intel_crtc_has_type(old_crtc_state, 3133 INTEL_OUTPUT_DP_MST); 3134 3135 if (!is_mst) 3136 intel_dp_set_infoframes(encoder, false, 3137 old_crtc_state, old_conn_state); 3138 3139 /* 3140 * Power down sink before disabling the port, otherwise we end 3141 * up getting interrupts from the sink on detecting link loss. 3142 */ 3143 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3144 3145 if (DISPLAY_VER(display) >= 12) { 3146 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3147 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3148 3149 intel_de_rmw(display, 3150 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3151 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3152 0); 3153 } 3154 } else { 3155 if (!is_mst) 3156 intel_ddi_disable_transcoder_clock(old_crtc_state); 3157 } 3158 3159 intel_ddi_buf_disable(encoder, old_crtc_state); 3160 3161 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3162 3163 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3164 3165 /* 3166 * From TGL spec: "If single stream or multi-stream master transcoder: 3167 * Configure Transcoder Clock select to direct no clock to the 3168 * transcoder" 3169 */ 3170 if (DISPLAY_VER(display) >= 12) 3171 intel_ddi_disable_transcoder_clock(old_crtc_state); 3172 3173 intel_pps_vdd_on(intel_dp); 3174 intel_pps_off(intel_dp); 3175 3176 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3177 3178 if (wakeref) 3179 intel_display_power_put(display, 3180 dig_port->ddi_io_power_domain, 3181 wakeref); 3182 3183 intel_ddi_disable_clock(encoder); 3184 3185 /* De-select Thunderbolt */ 3186 if (DISPLAY_VER(display) >= 14) 3187 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3188 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3189 } 3190 3191 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3192 struct intel_encoder *encoder, 3193 const struct intel_crtc_state *old_crtc_state, 3194 const struct drm_connector_state *old_conn_state) 3195 { 3196 struct intel_display *display = to_intel_display(encoder); 3197 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3198 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3199 struct ref_tracker *wakeref; 3200 3201 dig_port->set_infoframes(encoder, false, 3202 old_crtc_state, old_conn_state); 3203 3204 if (DISPLAY_VER(display) < 12) 3205 intel_ddi_disable_transcoder_clock(old_crtc_state); 3206 3207 intel_ddi_buf_disable(encoder, old_crtc_state); 3208 3209 if (DISPLAY_VER(display) >= 12) 3210 intel_ddi_disable_transcoder_clock(old_crtc_state); 3211 3212 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3213 if (wakeref) 3214 intel_display_power_put(display, 3215 dig_port->ddi_io_power_domain, 3216 wakeref); 3217 3218 intel_ddi_disable_clock(encoder); 3219 3220 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3221 } 3222 3223 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3224 struct intel_encoder *encoder, 3225 const struct intel_crtc_state *old_crtc_state, 3226 const struct drm_connector_state *old_conn_state) 3227 { 3228 struct intel_display *display = to_intel_display(encoder); 3229 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3230 struct intel_crtc *pipe_crtc; 3231 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3232 3233 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 3234 const struct intel_crtc_state *old_pipe_crtc_state = 3235 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3236 3237 intel_crtc_vblank_off(old_pipe_crtc_state); 3238 } 3239 3240 intel_disable_transcoder(old_crtc_state); 3241 3242 /* 128b/132b SST */ 3243 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3244 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3245 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3246 3247 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3248 3249 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3250 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3251 3252 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3253 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3254 } 3255 3256 intel_vrr_transcoder_disable(old_crtc_state); 3257 3258 intel_ddi_disable_transcoder_func(old_crtc_state); 3259 3260 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 3261 const struct intel_crtc_state *old_pipe_crtc_state = 3262 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3263 3264 intel_dsc_disable(old_pipe_crtc_state); 3265 3266 if (DISPLAY_VER(display) >= 9) 3267 skl_scaler_disable(old_pipe_crtc_state); 3268 else 3269 ilk_pfit_disable(old_pipe_crtc_state); 3270 } 3271 } 3272 3273 /* 3274 * Note: Also called from the ->post_disable of the last active MST stream 3275 * encoder on its primary encoder. See also the comment for 3276 * intel_ddi_pre_enable(). 3277 */ 3278 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3279 struct intel_encoder *encoder, 3280 const struct intel_crtc_state *old_crtc_state, 3281 const struct drm_connector_state *old_conn_state) 3282 { 3283 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3284 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3285 old_conn_state); 3286 3287 /* 3288 * When called from DP MST code: 3289 * - old_conn_state will be NULL 3290 * - encoder will be the main encoder (ie. mst->primary) 3291 * - the main connector associated with this port 3292 * won't be active or linked to a crtc 3293 * - old_crtc_state will be the state of the last stream to 3294 * be deactivated on this port, and it may not be the same 3295 * stream that was activated last, but each stream 3296 * should have a state that is identical when it comes to 3297 * the DP link parameters 3298 */ 3299 3300 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3301 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3302 old_conn_state); 3303 else 3304 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3305 old_conn_state); 3306 } 3307 3308 /* 3309 * Note: Also called from the ->post_pll_disable of the last active MST stream 3310 * encoder on its primary encoder. See also the comment for 3311 * intel_ddi_pre_enable(). 3312 */ 3313 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3314 struct intel_encoder *encoder, 3315 const struct intel_crtc_state *old_crtc_state, 3316 const struct drm_connector_state *old_conn_state) 3317 { 3318 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3319 3320 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3321 3322 if (intel_encoder_is_tc(encoder)) 3323 intel_tc_port_put_link(dig_port); 3324 } 3325 3326 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3327 struct intel_encoder *encoder, 3328 const struct intel_crtc_state *crtc_state) 3329 { 3330 const struct drm_connector_state *conn_state; 3331 struct drm_connector *conn; 3332 int i; 3333 3334 if (!crtc_state->sync_mode_slaves_mask) 3335 return; 3336 3337 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3338 struct intel_encoder *slave_encoder = 3339 to_intel_encoder(conn_state->best_encoder); 3340 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3341 const struct intel_crtc_state *slave_crtc_state; 3342 3343 if (!slave_crtc) 3344 continue; 3345 3346 slave_crtc_state = 3347 intel_atomic_get_new_crtc_state(state, slave_crtc); 3348 3349 if (slave_crtc_state->master_transcoder != 3350 crtc_state->cpu_transcoder) 3351 continue; 3352 3353 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3354 slave_crtc_state); 3355 } 3356 3357 usleep_range(200, 400); 3358 3359 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3360 crtc_state); 3361 } 3362 3363 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3364 struct intel_encoder *encoder, 3365 const struct intel_crtc_state *crtc_state, 3366 const struct drm_connector_state *conn_state) 3367 { 3368 struct intel_display *display = to_intel_display(encoder); 3369 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3370 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3371 enum port port = encoder->port; 3372 3373 if (port == PORT_A && DISPLAY_VER(display) < 9) 3374 intel_dp_stop_link_train(intel_dp, crtc_state); 3375 3376 drm_connector_update_privacy_screen(conn_state); 3377 intel_edp_backlight_on(crtc_state, conn_state); 3378 3379 intel_panel_prepare(crtc_state, conn_state); 3380 3381 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3382 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3383 3384 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3385 } 3386 3387 static intel_reg_t 3388 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3389 { 3390 static const enum transcoder trans[] = { 3391 [PORT_A] = TRANSCODER_EDP, 3392 [PORT_B] = TRANSCODER_A, 3393 [PORT_C] = TRANSCODER_B, 3394 [PORT_D] = TRANSCODER_C, 3395 [PORT_E] = TRANSCODER_A, 3396 }; 3397 3398 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3399 3400 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3401 port = PORT_A; 3402 3403 return CHICKEN_TRANS(display, trans[port]); 3404 } 3405 3406 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3407 struct intel_encoder *encoder, 3408 const struct intel_crtc_state *crtc_state, 3409 const struct drm_connector_state *conn_state) 3410 { 3411 struct intel_display *display = to_intel_display(encoder); 3412 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3413 struct drm_connector *connector = conn_state->connector; 3414 enum port port = encoder->port; 3415 u32 buf_ctl = 0; 3416 3417 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3418 crtc_state->hdmi_high_tmds_clock_ratio, 3419 crtc_state->hdmi_scrambling)) 3420 drm_dbg_kms(display->drm, 3421 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3422 connector->base.id, connector->name); 3423 3424 if (has_buf_trans_select(display)) 3425 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3426 3427 /* e. Enable D2D Link for C10/C20 Phy */ 3428 mtl_ddi_enable_d2d(encoder); 3429 3430 encoder->set_signal_levels(encoder, crtc_state); 3431 3432 /* Display WA #1143: skl,kbl,cfl */ 3433 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3434 /* 3435 * For some reason these chicken bits have been 3436 * stuffed into a transcoder register, event though 3437 * the bits affect a specific DDI port rather than 3438 * a specific transcoder. 3439 */ 3440 intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3441 u32 val; 3442 3443 val = intel_de_read(display, reg); 3444 3445 if (port == PORT_E) 3446 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3447 DDIE_TRAINING_OVERRIDE_VALUE; 3448 else 3449 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3450 DDI_TRAINING_OVERRIDE_VALUE; 3451 3452 intel_de_write(display, reg, val); 3453 intel_de_posting_read(display, reg); 3454 3455 udelay(1); 3456 3457 if (port == PORT_E) 3458 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3459 DDIE_TRAINING_OVERRIDE_VALUE); 3460 else 3461 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3462 DDI_TRAINING_OVERRIDE_VALUE); 3463 3464 intel_de_write(display, reg, val); 3465 } 3466 3467 intel_ddi_power_up_lanes(encoder, crtc_state); 3468 3469 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3470 * are ignored so nothing special needs to be done besides 3471 * enabling the port. 3472 * 3473 * On ADL_P the PHY link rate and lane count must be programmed but 3474 * these are both 0 for HDMI. 3475 * 3476 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3477 * is filled with lane count, already set in the crtc_state. 3478 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3479 */ 3480 if (dig_port->lane_reversal) 3481 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3482 if (dig_port->ddi_a_4_lanes) 3483 buf_ctl |= DDI_A_4_LANES; 3484 3485 if (DISPLAY_VER(display) >= 14) { 3486 u32 port_buf = 0; 3487 3488 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3489 3490 if (dig_port->lane_reversal) 3491 port_buf |= XELPDP_PORT_REVERSAL; 3492 3493 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3494 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3495 3496 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3497 3498 if (DISPLAY_VER(display) >= 20) 3499 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3500 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3501 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3502 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3503 } 3504 3505 intel_ddi_buf_enable(encoder, buf_ctl); 3506 3507 intel_hdmi_poll_for_scrambling_enable(crtc_state, connector); 3508 } 3509 3510 static void intel_ddi_enable(struct intel_atomic_state *state, 3511 struct intel_encoder *encoder, 3512 const struct intel_crtc_state *crtc_state, 3513 const struct drm_connector_state *conn_state) 3514 { 3515 struct intel_display *display = to_intel_display(encoder); 3516 struct intel_crtc *pipe_crtc; 3517 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3518 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3519 3520 /* 128b/132b SST */ 3521 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3522 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3523 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3524 3525 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3526 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3527 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3528 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3529 } 3530 3531 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3532 3533 intel_vrr_transcoder_enable(crtc_state); 3534 3535 /* 128b/132b SST */ 3536 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3537 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3538 3539 intel_ddi_clear_act_sent(encoder, crtc_state); 3540 3541 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3542 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3543 3544 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3545 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3546 } 3547 3548 intel_enable_transcoder(crtc_state); 3549 3550 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3551 3552 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) { 3553 const struct intel_crtc_state *pipe_crtc_state = 3554 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3555 3556 intel_crtc_vblank_on(pipe_crtc_state); 3557 } 3558 3559 if (is_hdmi) 3560 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3561 else 3562 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3563 3564 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3565 3566 } 3567 3568 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3569 struct intel_encoder *encoder, 3570 const struct intel_crtc_state *old_crtc_state, 3571 const struct drm_connector_state *old_conn_state) 3572 { 3573 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3574 struct intel_connector *connector = 3575 to_intel_connector(old_conn_state->connector); 3576 3577 intel_dp->link.active = false; 3578 3579 intel_panel_unprepare(old_conn_state); 3580 intel_psr_disable(intel_dp, old_crtc_state); 3581 intel_alpm_disable(intel_dp); 3582 intel_edp_backlight_off(old_conn_state); 3583 /* Disable the decompression in DP Sink */ 3584 intel_dp_sink_disable_decompression(state, 3585 connector, old_crtc_state); 3586 /* Disable Ignore_MSA bit in DP Sink */ 3587 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3588 false); 3589 } 3590 3591 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3592 struct intel_encoder *encoder, 3593 const struct intel_crtc_state *old_crtc_state, 3594 const struct drm_connector_state *old_conn_state) 3595 { 3596 struct intel_display *display = to_intel_display(encoder); 3597 struct drm_connector *connector = old_conn_state->connector; 3598 3599 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3600 false, false)) 3601 drm_dbg_kms(display->drm, 3602 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3603 connector->base.id, connector->name); 3604 } 3605 3606 static void intel_ddi_disable(struct intel_atomic_state *state, 3607 struct intel_encoder *encoder, 3608 const struct intel_crtc_state *old_crtc_state, 3609 const struct drm_connector_state *old_conn_state) 3610 { 3611 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3612 3613 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3614 3615 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3616 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3617 old_conn_state); 3618 else 3619 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3620 old_conn_state); 3621 } 3622 3623 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3624 struct intel_encoder *encoder, 3625 const struct intel_crtc_state *crtc_state, 3626 const struct drm_connector_state *conn_state) 3627 { 3628 intel_ddi_set_dp_msa(crtc_state, conn_state); 3629 3630 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3631 3632 intel_backlight_update(state, encoder, crtc_state, conn_state); 3633 drm_connector_update_privacy_screen(conn_state); 3634 } 3635 3636 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3637 const struct intel_crtc_state *crtc_state, 3638 const struct drm_connector_state *conn_state) 3639 { 3640 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3641 } 3642 3643 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3644 struct intel_encoder *encoder, 3645 const struct intel_crtc_state *crtc_state, 3646 const struct drm_connector_state *conn_state) 3647 { 3648 3649 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3650 !intel_encoder_is_mst(encoder)) 3651 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3652 conn_state); 3653 3654 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3655 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3656 conn_state); 3657 3658 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3659 } 3660 3661 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3662 struct intel_encoder *encoder, 3663 struct intel_crtc *crtc) 3664 { 3665 struct intel_display *display = to_intel_display(encoder); 3666 const struct intel_crtc_state *crtc_state = 3667 intel_atomic_get_new_crtc_state(state, crtc); 3668 struct intel_crtc *pipe_crtc; 3669 3670 /* FIXME: Add NVL+ and DG2 pll_mgr */ 3671 if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) 3672 return; 3673 3674 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 3675 intel_crtc_joined_pipe_mask(crtc_state)) 3676 intel_dpll_update_active(state, pipe_crtc, encoder); 3677 } 3678 3679 /* 3680 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3681 * encoder on its primary encoder. See also the comment for 3682 * intel_ddi_pre_enable(). 3683 */ 3684 static void 3685 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3686 struct intel_encoder *encoder, 3687 const struct intel_crtc_state *crtc_state, 3688 const struct drm_connector_state *conn_state) 3689 { 3690 struct intel_display *display = to_intel_display(encoder); 3691 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3692 bool is_tc_port = intel_encoder_is_tc(encoder); 3693 3694 if (is_tc_port) { 3695 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3696 3697 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3698 intel_ddi_update_active_dpll(state, encoder, crtc); 3699 } 3700 3701 main_link_aux_power_domain_get(dig_port, crtc_state); 3702 3703 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3704 /* 3705 * Program the lane count for static/dynamic connections on 3706 * Type-C ports. Skip this step for TBT. 3707 */ 3708 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3709 else if (display->platform.geminilake || display->platform.broxton) 3710 bxt_dpio_phy_set_lane_optim_mask(encoder, 3711 crtc_state->lane_lat_optim_mask); 3712 3713 /* 3714 * There is no direct connection between the PLL and PPS, however 3715 * enabling PPS before PLL is required to avoid PLL/DDI BUF timeouts 3716 * during system resume. Do that matching the Bspec order as well. 3717 */ 3718 if (DISPLAY_VER(display) >= 14) 3719 intel_pps_on(&dig_port->dp); 3720 } 3721 3722 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3723 { 3724 struct intel_display *display = to_intel_display(encoder); 3725 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3726 int ln; 3727 3728 for (ln = 0; ln < 2; ln++) 3729 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3730 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3731 } 3732 3733 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3734 const struct intel_crtc_state *crtc_state) 3735 { 3736 struct intel_display *display = to_intel_display(crtc_state); 3737 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3738 struct intel_encoder *encoder = &dig_port->base; 3739 u32 dp_tp_ctl; 3740 3741 /* 3742 * TODO: To train with only a different voltage swing entry is not 3743 * necessary disable and enable port 3744 */ 3745 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3746 3747 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3748 3749 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3750 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3751 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3752 intel_dp_is_uhbr(crtc_state)) { 3753 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3754 } else { 3755 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3756 if (crtc_state->enhanced_framing) 3757 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3758 } 3759 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3760 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3761 3762 /* 6.f Enable D2D Link */ 3763 mtl_ddi_enable_d2d(encoder); 3764 3765 /* 6.g Configure voltage swing and related IO settings */ 3766 encoder->set_signal_levels(encoder, crtc_state); 3767 3768 /* 6.h Configure PORT_BUF_CTL1 */ 3769 mtl_port_buf_ctl_program(encoder, crtc_state); 3770 3771 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3772 if (DISPLAY_VER(display) >= 20) 3773 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3774 3775 intel_ddi_buf_enable(encoder, intel_dp->DP); 3776 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3777 3778 /* 3779 * 6.k If AUX-Less ALPM is going to be enabled: 3780 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3781 */ 3782 intel_alpm_port_configure(intel_dp, crtc_state); 3783 3784 /* 3785 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3786 * register 3787 */ 3788 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3789 } 3790 3791 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3792 const struct intel_crtc_state *crtc_state) 3793 { 3794 struct intel_display *display = to_intel_display(intel_dp); 3795 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3796 struct intel_encoder *encoder = &dig_port->base; 3797 u32 dp_tp_ctl; 3798 3799 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3800 3801 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3802 3803 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3804 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3805 intel_dp_is_uhbr(crtc_state)) { 3806 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3807 } else { 3808 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3809 if (crtc_state->enhanced_framing) 3810 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3811 } 3812 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3813 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3814 3815 if (display->platform.alderlake_p && 3816 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3817 adlp_tbt_to_dp_alt_switch_wa(encoder); 3818 3819 intel_ddi_buf_enable(encoder, intel_dp->DP); 3820 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3821 } 3822 3823 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3824 const struct intel_crtc_state *crtc_state, 3825 u8 dp_train_pat) 3826 { 3827 struct intel_display *display = to_intel_display(intel_dp); 3828 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3829 u32 temp; 3830 3831 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3832 3833 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3834 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3835 case DP_TRAINING_PATTERN_DISABLE: 3836 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3837 break; 3838 case DP_TRAINING_PATTERN_1: 3839 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3840 break; 3841 case DP_TRAINING_PATTERN_2: 3842 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3843 break; 3844 case DP_TRAINING_PATTERN_3: 3845 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3846 break; 3847 case DP_TRAINING_PATTERN_4: 3848 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3849 break; 3850 } 3851 3852 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3853 } 3854 3855 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3856 const struct intel_crtc_state *crtc_state) 3857 { 3858 struct intel_display *display = to_intel_display(intel_dp); 3859 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3860 enum port port = encoder->port; 3861 3862 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3863 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3864 3865 /* 3866 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3867 * reason we need to set idle transmission mode is to work around a HW 3868 * issue where we enable the pipe while not in idle link-training mode. 3869 * In this case there is requirement to wait for a minimum number of 3870 * idle patterns to be sent. 3871 */ 3872 if (port == PORT_A && DISPLAY_VER(display) < 12) 3873 return; 3874 3875 if (intel_de_wait_for_set_ms(display, 3876 dp_tp_status_reg(encoder, crtc_state), 3877 DP_TP_STATUS_IDLE_DONE, 2)) 3878 drm_err(display->drm, 3879 "Timed out waiting for DP idle patterns\n"); 3880 } 3881 3882 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3883 enum transcoder cpu_transcoder) 3884 { 3885 if (cpu_transcoder == TRANSCODER_EDP) 3886 return false; 3887 3888 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3889 return false; 3890 3891 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3892 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3893 } 3894 3895 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3896 { 3897 if (crtc_state->port_clock > 594000) 3898 return 2; 3899 else 3900 return 0; 3901 } 3902 3903 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3904 { 3905 if (crtc_state->port_clock > 594000) 3906 return 3; 3907 else 3908 return 0; 3909 } 3910 3911 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3912 { 3913 if (crtc_state->port_clock > 594000) 3914 return 1; 3915 else 3916 return 0; 3917 } 3918 3919 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3920 { 3921 struct intel_display *display = to_intel_display(crtc_state); 3922 3923 if (DISPLAY_VER(display) >= 14) 3924 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3925 else if (DISPLAY_VER(display) >= 12) 3926 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3927 else if (display->platform.jasperlake || display->platform.elkhartlake) 3928 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3929 else if (DISPLAY_VER(display) >= 11) 3930 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3931 } 3932 3933 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3934 enum transcoder cpu_transcoder) 3935 { 3936 u32 master_select; 3937 3938 if (DISPLAY_VER(display) >= 11) { 3939 u32 ctl2 = intel_de_read(display, 3940 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3941 3942 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3943 return INVALID_TRANSCODER; 3944 3945 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3946 } else { 3947 u32 ctl = intel_de_read(display, 3948 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3949 3950 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3951 return INVALID_TRANSCODER; 3952 3953 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3954 } 3955 3956 if (master_select == 0) 3957 return TRANSCODER_EDP; 3958 else 3959 return master_select - 1; 3960 } 3961 3962 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3963 { 3964 struct intel_display *display = to_intel_display(crtc_state); 3965 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3966 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3967 enum transcoder cpu_transcoder; 3968 3969 crtc_state->master_transcoder = 3970 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3971 3972 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3973 enum intel_display_power_domain power_domain; 3974 struct ref_tracker *trans_wakeref; 3975 3976 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3977 trans_wakeref = intel_display_power_get_if_enabled(display, 3978 power_domain); 3979 3980 if (!trans_wakeref) 3981 continue; 3982 3983 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3984 crtc_state->cpu_transcoder) 3985 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3986 3987 intel_display_power_put(display, power_domain, trans_wakeref); 3988 } 3989 3990 drm_WARN_ON(display->drm, 3991 crtc_state->master_transcoder != INVALID_TRANSCODER && 3992 crtc_state->sync_mode_slaves_mask); 3993 } 3994 3995 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3996 struct intel_crtc_state *crtc_state, 3997 u32 ddi_func_ctl) 3998 { 3999 struct intel_display *display = to_intel_display(encoder); 4000 4001 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 4002 if (DISPLAY_VER(display) >= 14) 4003 crtc_state->lane_count = 4004 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4005 else 4006 crtc_state->lane_count = 4; 4007 } 4008 4009 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4010 struct intel_crtc_state *crtc_state, 4011 u32 ddi_func_ctl) 4012 { 4013 crtc_state->has_hdmi_sink = true; 4014 4015 crtc_state->infoframes.enable |= 4016 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4017 4018 if (crtc_state->infoframes.enable) 4019 crtc_state->has_infoframe = true; 4020 4021 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4022 crtc_state->hdmi_scrambling = true; 4023 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4024 crtc_state->hdmi_high_tmds_clock_ratio = true; 4025 4026 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4027 } 4028 4029 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4030 struct intel_crtc_state *crtc_state, 4031 u32 ddi_func_ctl) 4032 { 4033 struct intel_display *display = to_intel_display(encoder); 4034 4035 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4036 crtc_state->enhanced_framing = 4037 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4038 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4039 } 4040 4041 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4042 struct intel_crtc_state *crtc_state, 4043 u32 ddi_func_ctl) 4044 { 4045 struct intel_display *display = to_intel_display(encoder); 4046 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4047 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4048 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4049 4050 if (encoder->type == INTEL_OUTPUT_EDP) 4051 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4052 else 4053 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4054 crtc_state->lane_count = 4055 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4056 4057 if (DISPLAY_VER(display) >= 12 && 4058 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4059 crtc_state->mst_master_transcoder = 4060 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4061 4062 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4063 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4064 4065 crtc_state->enhanced_framing = 4066 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4067 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4068 4069 if (DISPLAY_VER(display) >= 11) 4070 crtc_state->fec_enable = 4071 intel_de_read(display, 4072 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4073 4074 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4075 crtc_state->infoframes.enable |= 4076 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4077 else 4078 crtc_state->infoframes.enable |= 4079 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4080 } 4081 4082 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4083 struct intel_crtc_state *crtc_state, 4084 u32 ddi_func_ctl) 4085 { 4086 struct intel_display *display = to_intel_display(encoder); 4087 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4088 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4089 4090 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4091 crtc_state->lane_count = 4092 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4093 4094 if (DISPLAY_VER(display) >= 12) 4095 crtc_state->mst_master_transcoder = 4096 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4097 4098 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4099 4100 if (DISPLAY_VER(display) >= 11) 4101 crtc_state->fec_enable = 4102 intel_de_read(display, 4103 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4104 4105 crtc_state->infoframes.enable |= 4106 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4107 } 4108 4109 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4110 struct intel_crtc_state *pipe_config) 4111 { 4112 struct intel_display *display = to_intel_display(encoder); 4113 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4114 u32 ddi_func_ctl, ddi_mode, flags = 0; 4115 4116 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4117 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4118 flags |= DRM_MODE_FLAG_PHSYNC; 4119 else 4120 flags |= DRM_MODE_FLAG_NHSYNC; 4121 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4122 flags |= DRM_MODE_FLAG_PVSYNC; 4123 else 4124 flags |= DRM_MODE_FLAG_NVSYNC; 4125 4126 pipe_config->hw.adjusted_mode.flags |= flags; 4127 4128 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4129 case TRANS_DDI_BPC_6: 4130 pipe_config->pipe_bpp = 18; 4131 break; 4132 case TRANS_DDI_BPC_8: 4133 pipe_config->pipe_bpp = 24; 4134 break; 4135 case TRANS_DDI_BPC_10: 4136 pipe_config->pipe_bpp = 30; 4137 break; 4138 case TRANS_DDI_BPC_12: 4139 pipe_config->pipe_bpp = 36; 4140 break; 4141 default: 4142 break; 4143 } 4144 4145 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4146 4147 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4148 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4150 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4152 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4153 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4154 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4155 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4156 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4157 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4158 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4159 4160 /* 4161 * If this is true, we know we're being called from mst stream 4162 * encoder's ->get_config(). 4163 */ 4164 if (intel_dp_mst_active_streams(intel_dp)) 4165 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4166 else 4167 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4168 } 4169 } 4170 4171 /* 4172 * Note: Also called from the ->get_config of the MST stream encoders on their 4173 * primary encoder, via the platform specific hooks here. See also the comment 4174 * for intel_ddi_pre_enable(). 4175 */ 4176 static void intel_ddi_get_config(struct intel_encoder *encoder, 4177 struct intel_crtc_state *pipe_config) 4178 { 4179 struct intel_display *display = to_intel_display(encoder); 4180 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4181 4182 /* XXX: DSI transcoder paranoia */ 4183 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4184 return; 4185 4186 intel_ddi_read_func_ctl(encoder, pipe_config); 4187 4188 intel_ddi_mso_get_config(encoder, pipe_config); 4189 4190 pipe_config->has_audio = 4191 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4192 4193 if (encoder->type == INTEL_OUTPUT_EDP) 4194 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4195 4196 ddi_dotclock_get(pipe_config); 4197 4198 if (display->platform.geminilake || display->platform.broxton) 4199 pipe_config->lane_lat_optim_mask = 4200 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4201 4202 intel_ddi_compute_min_voltage_level(pipe_config); 4203 4204 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4205 4206 intel_read_infoframe(encoder, pipe_config, 4207 HDMI_INFOFRAME_TYPE_AVI, 4208 &pipe_config->infoframes.avi); 4209 intel_read_infoframe(encoder, pipe_config, 4210 HDMI_INFOFRAME_TYPE_SPD, 4211 &pipe_config->infoframes.spd); 4212 intel_read_infoframe(encoder, pipe_config, 4213 HDMI_INFOFRAME_TYPE_VENDOR, 4214 &pipe_config->infoframes.hdmi); 4215 intel_read_infoframe(encoder, pipe_config, 4216 HDMI_INFOFRAME_TYPE_DRM, 4217 &pipe_config->infoframes.drm); 4218 4219 if (DISPLAY_VER(display) >= 8) 4220 bdw_get_trans_port_sync_config(pipe_config); 4221 4222 intel_psr_get_config(encoder, pipe_config); 4223 4224 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4225 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4226 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4227 4228 intel_audio_codec_get_config(encoder, pipe_config); 4229 } 4230 4231 void intel_ddi_get_clock(struct intel_encoder *encoder, 4232 struct intel_crtc_state *crtc_state, 4233 struct intel_dpll *pll) 4234 { 4235 struct intel_display *display = to_intel_display(encoder); 4236 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4237 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4238 bool pll_active; 4239 4240 if (drm_WARN_ON(display->drm, !pll)) 4241 return; 4242 4243 port_dpll->pll = pll; 4244 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4245 drm_WARN_ON(display->drm, !pll_active); 4246 4247 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4248 4249 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4250 &crtc_state->dpll_hw_state); 4251 } 4252 4253 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4254 { 4255 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4256 } 4257 4258 static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, 4259 struct intel_crtc_state *crtc_state, 4260 enum icl_port_dpll_id port_dpll_id, 4261 enum intel_dpll_id pll_id) 4262 { 4263 struct intel_display *display = to_intel_display(encoder); 4264 struct icl_port_dpll *port_dpll; 4265 struct intel_dpll *pll; 4266 bool pll_active; 4267 4268 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4269 pll = intel_get_dpll_by_id(display, pll_id); 4270 4271 if (drm_WARN_ON(display->drm, !pll)) 4272 return; 4273 4274 port_dpll->pll = pll; 4275 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4276 drm_WARN_ON(display->drm, !pll_active); 4277 4278 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4279 4280 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4281 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4282 else 4283 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4284 &crtc_state->dpll_hw_state); 4285 4286 intel_ddi_get_config(encoder, crtc_state); 4287 } 4288 4289 /* 4290 * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4291 * C20 PHY PLL in the cases of: 4292 * - BMG port A/B 4293 * - PTL port B eDP over TypeC PHY 4294 */ 4295 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4296 struct intel_crtc_state *crtc_state) 4297 { 4298 struct intel_display *display = to_intel_display(encoder); 4299 4300 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4301 mtl_port_to_pll_id(display, encoder->port)); 4302 } 4303 4304 static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, 4305 struct intel_crtc_state *crtc_state) 4306 { 4307 struct intel_display *display = to_intel_display(encoder); 4308 4309 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4310 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4311 DPLL_ID_ICL_TBTPLL); 4312 else 4313 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, 4314 mtl_port_to_pll_id(display, encoder->port)); 4315 } 4316 4317 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4318 struct intel_crtc_state *crtc_state) 4319 { 4320 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4321 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4322 4323 intel_ddi_get_config(encoder, crtc_state); 4324 } 4325 4326 static void adls_ddi_get_config(struct intel_encoder *encoder, 4327 struct intel_crtc_state *crtc_state) 4328 { 4329 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4330 intel_ddi_get_config(encoder, crtc_state); 4331 } 4332 4333 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4334 struct intel_crtc_state *crtc_state) 4335 { 4336 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4337 intel_ddi_get_config(encoder, crtc_state); 4338 } 4339 4340 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4341 struct intel_crtc_state *crtc_state) 4342 { 4343 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4344 intel_ddi_get_config(encoder, crtc_state); 4345 } 4346 4347 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4348 struct intel_crtc_state *crtc_state) 4349 { 4350 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4351 intel_ddi_get_config(encoder, crtc_state); 4352 } 4353 4354 static enum icl_port_dpll_id 4355 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4356 const struct intel_crtc_state *crtc_state) 4357 { 4358 struct intel_display *display = to_intel_display(encoder); 4359 const struct intel_dpll *pll = crtc_state->intel_dpll; 4360 4361 if (drm_WARN_ON(display->drm, !pll)) 4362 return ICL_PORT_DPLL_DEFAULT; 4363 4364 if (icl_ddi_tc_pll_is_tbt(pll)) 4365 return ICL_PORT_DPLL_DEFAULT; 4366 else 4367 return ICL_PORT_DPLL_MG_PHY; 4368 } 4369 4370 enum icl_port_dpll_id 4371 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4372 const struct intel_crtc_state *crtc_state) 4373 { 4374 if (!encoder->port_pll_type) 4375 return ICL_PORT_DPLL_DEFAULT; 4376 4377 return encoder->port_pll_type(encoder, crtc_state); 4378 } 4379 4380 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4381 struct intel_crtc_state *crtc_state, 4382 struct intel_dpll *pll) 4383 { 4384 struct intel_display *display = to_intel_display(encoder); 4385 enum icl_port_dpll_id port_dpll_id; 4386 struct icl_port_dpll *port_dpll; 4387 bool pll_active; 4388 4389 if (drm_WARN_ON(display->drm, !pll)) 4390 return; 4391 4392 if (icl_ddi_tc_pll_is_tbt(pll)) 4393 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4394 else 4395 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4396 4397 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4398 4399 port_dpll->pll = pll; 4400 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4401 drm_WARN_ON(display->drm, !pll_active); 4402 4403 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4404 4405 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4406 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4407 else 4408 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4409 &crtc_state->dpll_hw_state); 4410 } 4411 4412 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4413 struct intel_crtc_state *crtc_state) 4414 { 4415 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4416 intel_ddi_get_config(encoder, crtc_state); 4417 } 4418 4419 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4420 struct intel_crtc_state *crtc_state) 4421 { 4422 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4423 intel_ddi_get_config(encoder, crtc_state); 4424 } 4425 4426 static void skl_ddi_get_config(struct intel_encoder *encoder, 4427 struct intel_crtc_state *crtc_state) 4428 { 4429 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4430 intel_ddi_get_config(encoder, crtc_state); 4431 } 4432 4433 void hsw_ddi_get_config(struct intel_encoder *encoder, 4434 struct intel_crtc_state *crtc_state) 4435 { 4436 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4437 intel_ddi_get_config(encoder, crtc_state); 4438 } 4439 4440 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4441 const struct intel_crtc_state *crtc_state) 4442 { 4443 if (intel_encoder_is_tc(encoder)) 4444 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4445 crtc_state); 4446 4447 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4448 (!crtc_state && intel_encoder_is_dp(encoder))) 4449 intel_dp_sync_state(encoder, crtc_state); 4450 } 4451 4452 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4453 struct intel_crtc_state *crtc_state) 4454 { 4455 struct intel_display *display = to_intel_display(encoder); 4456 bool fastset = true; 4457 4458 if (intel_encoder_is_tc(encoder)) { 4459 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4460 encoder->base.base.id, encoder->base.name); 4461 crtc_state->uapi.mode_changed = true; 4462 fastset = false; 4463 } 4464 4465 if (intel_crtc_has_dp_encoder(crtc_state) && 4466 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4467 fastset = false; 4468 4469 return fastset; 4470 } 4471 4472 static enum intel_output_type 4473 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4474 struct intel_crtc_state *crtc_state, 4475 struct drm_connector_state *conn_state) 4476 { 4477 switch (conn_state->connector->connector_type) { 4478 case DRM_MODE_CONNECTOR_HDMIA: 4479 return INTEL_OUTPUT_HDMI; 4480 case DRM_MODE_CONNECTOR_eDP: 4481 return INTEL_OUTPUT_EDP; 4482 case DRM_MODE_CONNECTOR_DisplayPort: 4483 return INTEL_OUTPUT_DP; 4484 default: 4485 MISSING_CASE(conn_state->connector->connector_type); 4486 return INTEL_OUTPUT_UNUSED; 4487 } 4488 } 4489 4490 static int intel_ddi_compute_config(struct intel_atomic_state *state, 4491 struct intel_encoder *encoder, 4492 struct intel_crtc_state *pipe_config, 4493 struct drm_connector_state *conn_state) 4494 { 4495 struct intel_display *display = to_intel_display(encoder); 4496 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4497 enum port port = encoder->port; 4498 int ret; 4499 4500 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4501 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4502 4503 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4504 pipe_config->has_hdmi_sink = 4505 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4506 4507 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4508 } else { 4509 ret = intel_dp_compute_config(state, encoder, pipe_config, conn_state); 4510 } 4511 4512 if (ret) 4513 return ret; 4514 4515 if (display->platform.haswell && crtc->pipe == PIPE_A && 4516 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4517 pipe_config->pch_pfit.force_thru = 4518 pipe_config->pch_pfit.enabled || 4519 pipe_config->crc_enabled; 4520 4521 if (display->platform.geminilake || display->platform.broxton) 4522 pipe_config->lane_lat_optim_mask = 4523 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4524 4525 intel_ddi_compute_min_voltage_level(pipe_config); 4526 4527 return 0; 4528 } 4529 4530 static bool mode_equal(const struct drm_display_mode *mode1, 4531 const struct drm_display_mode *mode2) 4532 { 4533 return drm_mode_match(mode1, mode2, 4534 DRM_MODE_MATCH_TIMINGS | 4535 DRM_MODE_MATCH_FLAGS | 4536 DRM_MODE_MATCH_3D_FLAGS) && 4537 mode1->clock == mode2->clock; /* we want an exact match */ 4538 } 4539 4540 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4541 const struct intel_link_m_n *m_n_2) 4542 { 4543 return m_n_1->tu == m_n_2->tu && 4544 m_n_1->data_m == m_n_2->data_m && 4545 m_n_1->data_n == m_n_2->data_n && 4546 m_n_1->link_m == m_n_2->link_m && 4547 m_n_1->link_n == m_n_2->link_n; 4548 } 4549 4550 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4551 const struct intel_crtc_state *crtc_state2) 4552 { 4553 /* 4554 * FIXME the modeset sequence is currently wrong and 4555 * can't deal with joiner + port sync at the same time. 4556 */ 4557 return crtc_state1->hw.active && crtc_state2->hw.active && 4558 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4559 crtc_state1->output_types == crtc_state2->output_types && 4560 crtc_state1->output_format == crtc_state2->output_format && 4561 crtc_state1->lane_count == crtc_state2->lane_count && 4562 crtc_state1->port_clock == crtc_state2->port_clock && 4563 mode_equal(&crtc_state1->hw.adjusted_mode, 4564 &crtc_state2->hw.adjusted_mode) && 4565 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4566 } 4567 4568 static u16 4569 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4570 int tile_group_id) 4571 { 4572 struct intel_display *display = to_intel_display(ref_crtc_state); 4573 struct drm_connector *connector; 4574 const struct drm_connector_state *conn_state; 4575 struct intel_atomic_state *state = 4576 to_intel_atomic_state(ref_crtc_state->uapi.state); 4577 u16 transcoders = 0; 4578 int i; 4579 4580 /* 4581 * We don't enable port sync on BDW due to missing w/as and 4582 * due to not having adjusted the modeset sequence appropriately. 4583 * From, xe3lpd onwards we have defeatured this with reference to 4584 * Wa_16024710867 4585 */ 4586 if (!IS_DISPLAY_VER(display, 9, 20)) 4587 return 0; 4588 4589 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4590 return 0; 4591 4592 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4593 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4594 const struct intel_crtc_state *crtc_state; 4595 4596 if (!crtc) 4597 continue; 4598 4599 if (!connector->has_tile || 4600 connector->tile_group->id != 4601 tile_group_id) 4602 continue; 4603 crtc_state = intel_atomic_get_new_crtc_state(state, 4604 crtc); 4605 if (!crtcs_port_sync_compatible(ref_crtc_state, 4606 crtc_state)) 4607 continue; 4608 transcoders |= BIT(crtc_state->cpu_transcoder); 4609 } 4610 4611 return transcoders; 4612 } 4613 4614 static int intel_ddi_compute_config_late(struct intel_atomic_state *state, 4615 struct intel_encoder *encoder, 4616 struct intel_crtc_state *crtc_state, 4617 struct drm_connector_state *conn_state) 4618 { 4619 struct intel_display *display = to_intel_display(encoder); 4620 struct drm_connector *connector = conn_state->connector; 4621 u16 port_sync_transcoders = 0; 4622 int ret = 0; 4623 4624 if (intel_crtc_has_dp_encoder(crtc_state)) 4625 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); 4626 4627 if (ret) 4628 return ret; 4629 4630 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4631 encoder->base.base.id, encoder->base.name, 4632 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4633 4634 if (connector->has_tile) 4635 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4636 connector->tile_group->id); 4637 4638 /* 4639 * EDP Transcoders cannot be ensalved 4640 * make them a master always when present 4641 */ 4642 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4643 crtc_state->master_transcoder = TRANSCODER_EDP; 4644 else 4645 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4646 4647 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4648 crtc_state->master_transcoder = INVALID_TRANSCODER; 4649 crtc_state->sync_mode_slaves_mask = 4650 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4651 } 4652 4653 return 0; 4654 } 4655 4656 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4657 { 4658 struct intel_display *display = to_intel_display(encoder->dev); 4659 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4660 4661 intel_dp_encoder_flush_work(encoder); 4662 if (intel_encoder_is_tc(&dig_port->base)) 4663 intel_tc_port_cleanup(dig_port); 4664 intel_display_power_flush_work(display); 4665 4666 drm_encoder_cleanup(encoder); 4667 kfree(dig_port->hdcp.port_data.streams); 4668 intel_dp_link_cleanup(&dig_port->dp); 4669 kfree(dig_port); 4670 } 4671 4672 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4673 { 4674 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4675 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4676 4677 intel_dp->reset_link_params = true; 4678 intel_dp_invalidate_source_oui(intel_dp); 4679 4680 intel_pps_encoder_reset(intel_dp); 4681 4682 if (intel_encoder_is_tc(&dig_port->base)) 4683 intel_tc_port_init_mode(dig_port); 4684 } 4685 4686 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4687 { 4688 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4689 4690 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4691 4692 return 0; 4693 } 4694 4695 static const struct drm_encoder_funcs intel_ddi_funcs = { 4696 .reset = intel_ddi_encoder_reset, 4697 .destroy = intel_ddi_encoder_destroy, 4698 .late_register = intel_ddi_encoder_late_register, 4699 }; 4700 4701 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4702 { 4703 struct intel_display *display = to_intel_display(dig_port); 4704 struct intel_connector *connector; 4705 enum port port = dig_port->base.port; 4706 int err; 4707 4708 connector = intel_connector_alloc(); 4709 if (!connector) 4710 return -ENOMEM; 4711 4712 err = intel_dp_link_init(&dig_port->dp); 4713 if (err) 4714 goto err_dp_init; 4715 4716 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4717 if (DISPLAY_VER(display) >= 14) 4718 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4719 else 4720 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4721 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4722 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4723 4724 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4725 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4726 4727 if (!intel_dp_init_connector(dig_port, connector)) { 4728 err = -EINVAL; 4729 4730 goto err_init_connector; 4731 } 4732 4733 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4734 struct drm_privacy_screen *privacy_screen; 4735 4736 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4737 if (!IS_ERR(privacy_screen)) { 4738 drm_connector_attach_privacy_screen_provider(&connector->base, 4739 privacy_screen); 4740 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4741 drm_warn(display->drm, "Error getting privacy-screen\n"); 4742 } 4743 } 4744 4745 return 0; 4746 4747 err_init_connector: 4748 intel_dp_link_cleanup(&dig_port->dp); 4749 err_dp_init: 4750 kfree(connector); 4751 4752 return err; 4753 } 4754 4755 static void intel_ddi_cleanup_dp_connector(struct intel_digital_port *dig_port) 4756 { 4757 struct intel_dp *intel_dp = &dig_port->dp; 4758 struct intel_connector *connector = intel_dp->attached_connector; 4759 4760 intel_dp_cleanup_connector(dig_port, connector); 4761 intel_dp_link_cleanup(intel_dp); 4762 kfree(connector); 4763 } 4764 4765 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4766 struct drm_modeset_acquire_ctx *ctx) 4767 { 4768 struct intel_display *display = to_intel_display(encoder); 4769 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4770 struct intel_connector *connector = hdmi->attached_connector; 4771 struct i2c_adapter *ddc = connector->base.ddc; 4772 struct drm_connector_state *conn_state; 4773 struct intel_crtc_state *crtc_state; 4774 struct intel_crtc *crtc; 4775 u8 config; 4776 int ret; 4777 4778 if (connector->base.status != connector_status_connected) 4779 return 0; 4780 4781 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4782 ctx); 4783 if (ret) 4784 return ret; 4785 4786 conn_state = connector->base.state; 4787 4788 crtc = to_intel_crtc(conn_state->crtc); 4789 if (!crtc) 4790 return 0; 4791 4792 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4793 if (ret) 4794 return ret; 4795 4796 crtc_state = to_intel_crtc_state(crtc->base.state); 4797 4798 drm_WARN_ON(display->drm, 4799 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4800 4801 if (!crtc_state->hw.active) 4802 return 0; 4803 4804 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4805 !crtc_state->hdmi_scrambling) 4806 return 0; 4807 4808 if (conn_state->commit && 4809 !try_wait_for_completion(&conn_state->commit->hw_done)) 4810 return 0; 4811 4812 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4813 if (ret < 0) { 4814 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4815 connector->base.base.id, connector->base.name, ret); 4816 return 0; 4817 } 4818 4819 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4820 crtc_state->hdmi_high_tmds_clock_ratio && 4821 !!(config & SCDC_SCRAMBLING_ENABLE) == 4822 crtc_state->hdmi_scrambling) 4823 return 0; 4824 4825 /* 4826 * HDMI 2.0 says that one should not send scrambled data 4827 * prior to configuring the sink scrambling, and that 4828 * TMDS clock/data transmission should be suspended when 4829 * changing the TMDS clock rate in the sink. So let's 4830 * just do a full modeset here, even though some sinks 4831 * would be perfectly happy if were to just reconfigure 4832 * the SCDC settings on the fly. 4833 */ 4834 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4835 } 4836 4837 static void intel_ddi_link_check(struct intel_encoder *encoder) 4838 { 4839 struct intel_display *display = to_intel_display(encoder); 4840 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4841 4842 /* TODO: Move checking the HDMI link state here as well. */ 4843 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4844 4845 intel_dp_link_check(encoder); 4846 } 4847 4848 static enum intel_hotplug_state 4849 intel_ddi_hotplug(struct intel_encoder *encoder, 4850 struct intel_connector *connector) 4851 { 4852 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4853 struct intel_dp *intel_dp = &dig_port->dp; 4854 bool is_tc = intel_encoder_is_tc(encoder); 4855 struct drm_modeset_acquire_ctx ctx; 4856 enum intel_hotplug_state state; 4857 int ret; 4858 4859 if (intel_dp_test_phy(intel_dp)) 4860 return INTEL_HOTPLUG_UNCHANGED; 4861 4862 state = intel_encoder_hotplug(encoder, connector); 4863 4864 if (!intel_tc_port_link_reset(dig_port)) { 4865 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4866 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4867 ret = intel_hdmi_reset_link(encoder, &ctx); 4868 drm_WARN_ON(encoder->base.dev, ret); 4869 } else { 4870 intel_dp_check_link_state(intel_dp); 4871 } 4872 } 4873 4874 /* 4875 * Unpowered type-c dongles can take some time to boot and be 4876 * responsible, so here giving some time to those dongles to power up 4877 * and then retrying the probe. 4878 * 4879 * On many platforms the HDMI live state signal is known to be 4880 * unreliable, so we can't use it to detect if a sink is connected or 4881 * not. Instead we detect if it's connected based on whether we can 4882 * read the EDID or not. That in turn has a problem during disconnect, 4883 * since the HPD interrupt may be raised before the DDC lines get 4884 * disconnected (due to how the required length of DDC vs. HPD 4885 * connector pins are specified) and so we'll still be able to get a 4886 * valid EDID. To solve this schedule another detection cycle if this 4887 * time around we didn't detect any change in the sink's connection 4888 * status. 4889 * 4890 * Type-c connectors which get their HPD signal deasserted then 4891 * reasserted, without unplugging/replugging the sink from the 4892 * connector, introduce a delay until the AUX channel communication 4893 * becomes functional. Retry the detection for 5 seconds on type-c 4894 * connectors to account for this delay. 4895 */ 4896 if (state == INTEL_HOTPLUG_UNCHANGED && 4897 connector->hotplug_retries < (is_tc ? 5 : 1) && 4898 !dig_port->dp.is_mst) 4899 state = INTEL_HOTPLUG_RETRY; 4900 4901 return state; 4902 } 4903 4904 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4905 { 4906 struct intel_display *display = to_intel_display(encoder); 4907 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4908 4909 return intel_de_read(display, SDEISR) & bit; 4910 } 4911 4912 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4913 { 4914 struct intel_display *display = to_intel_display(encoder); 4915 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4916 4917 return intel_de_read(display, DEISR) & bit; 4918 } 4919 4920 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4921 { 4922 struct intel_display *display = to_intel_display(encoder); 4923 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4924 4925 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4926 } 4927 4928 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4929 { 4930 struct intel_connector *connector; 4931 enum port port = dig_port->base.port; 4932 4933 connector = intel_connector_alloc(); 4934 if (!connector) 4935 return -ENOMEM; 4936 4937 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4938 4939 if (!intel_hdmi_init_connector(dig_port, connector)) { 4940 /* 4941 * HDMI connector init failures may just mean conflicting DDC 4942 * pins or not having enough lanes. Handle them gracefully, but 4943 * don't fail the entire DDI init. 4944 */ 4945 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4946 kfree(connector); 4947 } 4948 4949 return 0; 4950 } 4951 4952 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4953 { 4954 struct intel_display *display = to_intel_display(dig_port); 4955 4956 if (dig_port->base.port != PORT_A) 4957 return false; 4958 4959 if (dig_port->ddi_a_4_lanes) 4960 return false; 4961 4962 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4963 * supported configuration 4964 */ 4965 if (display->platform.geminilake || display->platform.broxton) 4966 return true; 4967 4968 return false; 4969 } 4970 4971 static int 4972 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4973 { 4974 struct intel_display *display = to_intel_display(dig_port); 4975 enum port port = dig_port->base.port; 4976 int max_lanes = 4; 4977 4978 if (DISPLAY_VER(display) >= 11) 4979 return max_lanes; 4980 4981 if (port == PORT_A || port == PORT_E) { 4982 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4983 max_lanes = port == PORT_A ? 4 : 0; 4984 else 4985 /* Both A and E share 2 lanes */ 4986 max_lanes = 2; 4987 } 4988 4989 /* 4990 * Some BIOS might fail to set this bit on port A if eDP 4991 * wasn't lit up at boot. Force this bit set when needed 4992 * so we use the proper lane count for our calculations. 4993 */ 4994 if (intel_ddi_a_force_4_lanes(dig_port)) { 4995 drm_dbg_kms(display->drm, 4996 "Forcing DDI_A_4_LANES for port A\n"); 4997 dig_port->ddi_a_4_lanes = true; 4998 max_lanes = 4; 4999 } 5000 5001 return max_lanes; 5002 } 5003 5004 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 5005 { 5006 if (port >= PORT_D_XELPD) 5007 return HPD_PORT_D + port - PORT_D_XELPD; 5008 else if (port >= PORT_TC1) 5009 return HPD_PORT_TC1 + port - PORT_TC1; 5010 else 5011 return HPD_PORT_A + port - PORT_A; 5012 } 5013 5014 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 5015 { 5016 if (port >= PORT_TC1) 5017 return HPD_PORT_C + port - PORT_TC1; 5018 else 5019 return HPD_PORT_A + port - PORT_A; 5020 } 5021 5022 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 5023 { 5024 if (port >= PORT_TC1) 5025 return HPD_PORT_TC1 + port - PORT_TC1; 5026 else 5027 return HPD_PORT_A + port - PORT_A; 5028 } 5029 5030 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 5031 { 5032 if (HAS_PCH_TGP(display)) 5033 return tgl_hpd_pin(display, port); 5034 5035 if (port >= PORT_TC1) 5036 return HPD_PORT_C + port - PORT_TC1; 5037 else 5038 return HPD_PORT_A + port - PORT_A; 5039 } 5040 5041 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 5042 { 5043 if (port >= PORT_C) 5044 return HPD_PORT_TC1 + port - PORT_C; 5045 else 5046 return HPD_PORT_A + port - PORT_A; 5047 } 5048 5049 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 5050 { 5051 if (port == PORT_D) 5052 return HPD_PORT_A; 5053 5054 if (HAS_PCH_TGP(display)) 5055 return icl_hpd_pin(display, port); 5056 5057 return HPD_PORT_A + port - PORT_A; 5058 } 5059 5060 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 5061 { 5062 if (HAS_PCH_TGP(display)) 5063 return icl_hpd_pin(display, port); 5064 5065 return HPD_PORT_A + port - PORT_A; 5066 } 5067 5068 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 5069 { 5070 if (DISPLAY_VER(display) >= 12) 5071 return port >= PORT_TC1; 5072 else if (DISPLAY_VER(display) >= 11) 5073 return port >= PORT_C; 5074 else 5075 return false; 5076 } 5077 5078 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5079 { 5080 intel_dp_encoder_suspend(encoder); 5081 } 5082 5083 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5084 { 5085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5086 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5087 5088 /* 5089 * TODO: Move this to intel_dp_encoder_suspend(), 5090 * once modeset locking around that is removed. 5091 */ 5092 intel_encoder_link_check_flush_work(encoder); 5093 intel_tc_port_suspend(dig_port); 5094 } 5095 5096 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5097 { 5098 if (intel_encoder_is_dp(encoder)) 5099 intel_dp_encoder_shutdown(encoder); 5100 if (intel_encoder_is_hdmi(encoder)) 5101 intel_hdmi_encoder_shutdown(encoder); 5102 } 5103 5104 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5105 { 5106 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5107 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5108 5109 intel_tc_port_cleanup(dig_port); 5110 } 5111 5112 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5113 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5114 5115 static bool port_strap_detected(struct intel_display *display, enum port port) 5116 { 5117 /* straps not used on skl+ */ 5118 if (DISPLAY_VER(display) >= 9) 5119 return true; 5120 5121 switch (port) { 5122 case PORT_A: 5123 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5124 case PORT_B: 5125 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5126 case PORT_C: 5127 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5128 case PORT_D: 5129 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5130 case PORT_E: 5131 return true; /* no strap for DDI-E */ 5132 default: 5133 MISSING_CASE(port); 5134 return false; 5135 } 5136 } 5137 5138 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5139 { 5140 return init_dp || intel_encoder_is_tc(encoder); 5141 } 5142 5143 static bool assert_has_icl_dsi(struct intel_display *display) 5144 { 5145 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5146 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5147 "Platform does not support DSI\n"); 5148 } 5149 5150 static bool port_in_use(struct intel_display *display, enum port port) 5151 { 5152 struct intel_encoder *encoder; 5153 5154 for_each_intel_encoder(display->drm, encoder) { 5155 /* FIXME what about second port for dual link DSI? */ 5156 if (encoder->port == port) 5157 return true; 5158 } 5159 5160 return false; 5161 } 5162 5163 static const char *intel_ddi_encoder_name(struct intel_display *display, 5164 enum port port, enum phy phy, 5165 struct seq_buf *s) 5166 { 5167 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5168 seq_buf_printf(s, "DDI %c/PHY %c", 5169 port_name(port - PORT_D_XELPD + PORT_D), 5170 phy_name(phy)); 5171 } else if (DISPLAY_VER(display) >= 12) { 5172 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5173 5174 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5175 port >= PORT_TC1 ? "TC" : "", 5176 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5177 tc_port != TC_PORT_NONE ? "TC" : "", 5178 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5179 } else if (DISPLAY_VER(display) >= 11) { 5180 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5181 5182 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5183 port_name(port), 5184 port >= PORT_C ? " (TC)" : "", 5185 tc_port != TC_PORT_NONE ? "TC" : "", 5186 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5187 } else { 5188 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5189 } 5190 5191 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5192 5193 return seq_buf_str(s); 5194 } 5195 5196 void intel_ddi_init(struct intel_display *display, 5197 const struct intel_bios_encoder_data *devdata) 5198 { 5199 struct intel_digital_port *dig_port; 5200 struct intel_encoder *encoder; 5201 DECLARE_SEQ_BUF(encoder_name, 20); 5202 bool init_hdmi, init_dp; 5203 enum port port; 5204 enum phy phy; 5205 u32 ddi_buf_ctl; 5206 5207 port = intel_bios_encoder_port(devdata); 5208 if (port == PORT_NONE) 5209 return; 5210 5211 if (!port_strap_detected(display, port)) { 5212 drm_dbg_kms(display->drm, 5213 "Port %c strap not detected\n", port_name(port)); 5214 return; 5215 } 5216 5217 if (!assert_port_valid(display, port)) 5218 return; 5219 5220 if (port_in_use(display, port)) { 5221 drm_dbg_kms(display->drm, 5222 "Port %c already claimed\n", port_name(port)); 5223 return; 5224 } 5225 5226 if (intel_bios_encoder_supports_dsi(devdata)) { 5227 /* BXT/GLK handled elsewhere, for now at least */ 5228 if (!assert_has_icl_dsi(display)) 5229 return; 5230 5231 icl_dsi_init(display, devdata); 5232 return; 5233 } 5234 5235 phy = intel_port_to_phy(display, port); 5236 5237 /* 5238 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5239 * have taken over some of the PHYs and made them unavailable to the 5240 * driver. In that case we should skip initializing the corresponding 5241 * outputs. 5242 */ 5243 if (intel_hti_uses_phy(display, phy)) { 5244 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5245 port_name(port), phy_name(phy)); 5246 return; 5247 } 5248 5249 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5250 intel_bios_encoder_supports_hdmi(devdata); 5251 init_dp = intel_bios_encoder_supports_dp(devdata); 5252 5253 if (intel_bios_encoder_is_lspcon(devdata)) { 5254 /* 5255 * Lspcon device needs to be driven with DP connector 5256 * with special detection sequence. So make sure DP 5257 * is initialized before lspcon. 5258 */ 5259 init_dp = true; 5260 init_hdmi = false; 5261 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5262 port_name(port)); 5263 } 5264 5265 if (!init_dp && !init_hdmi) { 5266 drm_dbg_kms(display->drm, 5267 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5268 port_name(port)); 5269 return; 5270 } 5271 5272 if (intel_phy_is_snps(display, phy) && 5273 display->snps.phy_failed_calibration & BIT(phy)) { 5274 drm_dbg_kms(display->drm, 5275 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5276 phy_name(phy)); 5277 } 5278 5279 dig_port = intel_dig_port_alloc(); 5280 if (!dig_port) 5281 return; 5282 5283 encoder = &dig_port->base; 5284 encoder->devdata = devdata; 5285 5286 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5287 DRM_MODE_ENCODER_TMDS, "%s", 5288 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5289 5290 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5291 5292 encoder->hotplug = intel_ddi_hotplug; 5293 encoder->compute_output_type = intel_ddi_compute_output_type; 5294 encoder->compute_config = intel_ddi_compute_config; 5295 encoder->compute_config_late = intel_ddi_compute_config_late; 5296 encoder->enable = intel_ddi_enable; 5297 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5298 encoder->pre_enable = intel_ddi_pre_enable; 5299 encoder->disable = intel_ddi_disable; 5300 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5301 encoder->post_disable = intel_ddi_post_disable; 5302 encoder->update_pipe = intel_ddi_update_pipe; 5303 encoder->audio_enable = intel_audio_codec_enable; 5304 encoder->audio_disable = intel_audio_codec_disable; 5305 encoder->get_hw_state = intel_ddi_get_hw_state; 5306 encoder->sync_state = intel_ddi_sync_state; 5307 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5308 encoder->suspend = intel_ddi_encoder_suspend; 5309 encoder->shutdown = intel_ddi_encoder_shutdown; 5310 encoder->get_power_domains = intel_ddi_get_power_domains; 5311 5312 encoder->type = INTEL_OUTPUT_DDI; 5313 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5314 encoder->port = port; 5315 encoder->cloneable = 0; 5316 encoder->pipe_mask = ~0; 5317 5318 if (HAS_LT_PHY(display)) { 5319 encoder->enable_clock = intel_mtl_pll_enable_clock; 5320 encoder->disable_clock = intel_mtl_pll_disable_clock; 5321 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5322 if (intel_encoder_is_tc(encoder)) 5323 encoder->get_config = mtl_ddi_tc_phy_get_config; 5324 else 5325 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5326 } else if (DISPLAY_VER(display) >= 14) { 5327 encoder->enable_clock = intel_mtl_pll_enable_clock; 5328 encoder->disable_clock = intel_mtl_pll_disable_clock; 5329 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5330 if (intel_encoder_is_tc(encoder)) 5331 encoder->get_config = mtl_ddi_tc_phy_get_config; 5332 else 5333 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5334 } else if (display->platform.dg2) { 5335 encoder->enable_clock = intel_mpllb_enable; 5336 encoder->disable_clock = intel_mpllb_disable; 5337 encoder->get_config = dg2_ddi_get_config; 5338 } else if (display->platform.alderlake_s) { 5339 encoder->enable_clock = adls_ddi_enable_clock; 5340 encoder->disable_clock = adls_ddi_disable_clock; 5341 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5342 encoder->get_config = adls_ddi_get_config; 5343 } else if (display->platform.rocketlake) { 5344 encoder->enable_clock = rkl_ddi_enable_clock; 5345 encoder->disable_clock = rkl_ddi_disable_clock; 5346 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5347 encoder->get_config = rkl_ddi_get_config; 5348 } else if (display->platform.dg1) { 5349 encoder->enable_clock = dg1_ddi_enable_clock; 5350 encoder->disable_clock = dg1_ddi_disable_clock; 5351 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5352 encoder->get_config = dg1_ddi_get_config; 5353 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5354 if (intel_ddi_is_tc(display, port)) { 5355 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5356 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5357 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5358 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5359 encoder->get_config = icl_ddi_combo_get_config; 5360 } else { 5361 encoder->enable_clock = icl_ddi_combo_enable_clock; 5362 encoder->disable_clock = icl_ddi_combo_disable_clock; 5363 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5364 encoder->get_config = icl_ddi_combo_get_config; 5365 } 5366 } else if (DISPLAY_VER(display) >= 11) { 5367 if (intel_ddi_is_tc(display, port)) { 5368 encoder->enable_clock = icl_ddi_tc_enable_clock; 5369 encoder->disable_clock = icl_ddi_tc_disable_clock; 5370 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5371 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5372 encoder->get_config = icl_ddi_tc_get_config; 5373 } else { 5374 encoder->enable_clock = icl_ddi_combo_enable_clock; 5375 encoder->disable_clock = icl_ddi_combo_disable_clock; 5376 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5377 encoder->get_config = icl_ddi_combo_get_config; 5378 } 5379 } else if (display->platform.geminilake || display->platform.broxton) { 5380 /* BXT/GLK have fixed PLL->port mapping */ 5381 encoder->get_config = bxt_ddi_get_config; 5382 } else if (DISPLAY_VER(display) == 9) { 5383 encoder->enable_clock = skl_ddi_enable_clock; 5384 encoder->disable_clock = skl_ddi_disable_clock; 5385 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5386 encoder->get_config = skl_ddi_get_config; 5387 } else if (display->platform.broadwell || display->platform.haswell) { 5388 encoder->enable_clock = hsw_ddi_enable_clock; 5389 encoder->disable_clock = hsw_ddi_disable_clock; 5390 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5391 encoder->get_config = hsw_ddi_get_config; 5392 } 5393 5394 if (HAS_LT_PHY(display)) { 5395 encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5396 } else if (DISPLAY_VER(display) >= 14) { 5397 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5398 } else if (display->platform.dg2) { 5399 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5400 } else if (DISPLAY_VER(display) >= 12) { 5401 if (intel_encoder_is_combo(encoder)) 5402 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5403 else 5404 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5405 } else if (DISPLAY_VER(display) >= 11) { 5406 if (intel_encoder_is_combo(encoder)) 5407 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5408 else 5409 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5410 } else if (display->platform.geminilake || display->platform.broxton) { 5411 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5412 } else { 5413 encoder->set_signal_levels = hsw_set_signal_levels; 5414 } 5415 5416 intel_ddi_buf_trans_init(encoder); 5417 5418 if (DISPLAY_VER(display) >= 13) 5419 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5420 else if (display->platform.dg1) 5421 encoder->hpd_pin = dg1_hpd_pin(display, port); 5422 else if (display->platform.rocketlake) 5423 encoder->hpd_pin = rkl_hpd_pin(display, port); 5424 else if (DISPLAY_VER(display) >= 12) 5425 encoder->hpd_pin = tgl_hpd_pin(display, port); 5426 else if (display->platform.jasperlake || display->platform.elkhartlake) 5427 encoder->hpd_pin = ehl_hpd_pin(display, port); 5428 else if (DISPLAY_VER(display) == 11) 5429 encoder->hpd_pin = icl_hpd_pin(display, port); 5430 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5431 encoder->hpd_pin = skl_hpd_pin(display, port); 5432 else 5433 encoder->hpd_pin = intel_hpd_pin_default(port); 5434 5435 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5436 5437 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5438 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5439 5440 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5441 5442 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5443 5444 if (need_aux_ch(encoder, init_dp)) { 5445 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5446 if (dig_port->aux_ch == AUX_CH_NONE) 5447 goto err_aux_ch_init; 5448 } 5449 5450 /* 5451 * FIXME: We currently need to store dedicated_external because devdata 5452 * does not live long enough for when intel_encoder_is_tc() is called on 5453 * the unbind path. This needs to be fixed by making sure that the VBT 5454 * data is kept long enough, so that 5455 * intel_bios_encoder_is_dedicated_external() can be called directly 5456 * from intel_encoder_is_tc(). 5457 */ 5458 if (intel_bios_encoder_is_dedicated_external(devdata)) 5459 dig_port->dedicated_external = true; 5460 5461 if (intel_encoder_is_tc(encoder)) { 5462 bool is_legacy = 5463 !intel_bios_encoder_supports_typec_usb(devdata) && 5464 !intel_bios_encoder_supports_tbt(devdata); 5465 5466 if (!is_legacy && init_hdmi) { 5467 is_legacy = !init_dp; 5468 5469 drm_dbg_kms(display->drm, 5470 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5471 port_name(port), 5472 str_yes_no(init_dp), 5473 is_legacy ? "legacy" : "non-legacy"); 5474 } 5475 5476 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5477 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5478 5479 dig_port->lock = intel_tc_port_lock; 5480 dig_port->unlock = intel_tc_port_unlock; 5481 5482 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5483 goto err_aux_ch_init; 5484 } 5485 5486 drm_WARN_ON(display->drm, port > PORT_I); 5487 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5488 5489 if (DISPLAY_VER(display) >= 11) { 5490 if (intel_encoder_is_tc(encoder)) 5491 dig_port->connected = intel_tc_port_connected; 5492 else 5493 dig_port->connected = lpt_digital_port_connected; 5494 } else if (display->platform.geminilake || display->platform.broxton) { 5495 dig_port->connected = bdw_digital_port_connected; 5496 } else if (DISPLAY_VER(display) == 9) { 5497 dig_port->connected = lpt_digital_port_connected; 5498 } else if (display->platform.broadwell) { 5499 if (port == PORT_A) 5500 dig_port->connected = bdw_digital_port_connected; 5501 else 5502 dig_port->connected = lpt_digital_port_connected; 5503 } else if (display->platform.haswell) { 5504 if (port == PORT_A) 5505 dig_port->connected = hsw_digital_port_connected; 5506 else 5507 dig_port->connected = lpt_digital_port_connected; 5508 } 5509 5510 intel_infoframe_init(dig_port); 5511 5512 if (init_dp) { 5513 if (intel_ddi_init_dp_connector(dig_port)) 5514 goto err_dp_connector_init; 5515 5516 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5517 5518 if (dig_port->dp.mso_link_count) 5519 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5520 } 5521 5522 /* 5523 * In theory we don't need the encoder->type check, 5524 * but leave it just in case we have some really bad VBTs... 5525 */ 5526 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5527 if (intel_ddi_init_hdmi_connector(dig_port)) 5528 goto err_hdmi_connector_init; 5529 } 5530 5531 return; 5532 5533 err_hdmi_connector_init: 5534 if (init_dp) 5535 intel_ddi_cleanup_dp_connector(dig_port); 5536 err_dp_connector_init: 5537 if (intel_encoder_is_tc(encoder)) 5538 intel_tc_port_cleanup(dig_port); 5539 err_aux_ch_init: 5540 drm_encoder_cleanup(&encoder->base); 5541 kfree(dig_port); 5542 } 5543