1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dp_tunnel.h" 58 #include "intel_dpio_phy.h" 59 #include "intel_dsi.h" 60 #include "intel_fdi.h" 61 #include "intel_fifo_underrun.h" 62 #include "intel_gmbus.h" 63 #include "intel_hdcp.h" 64 #include "intel_hdmi.h" 65 #include "intel_hotplug.h" 66 #include "intel_hti.h" 67 #include "intel_lspcon.h" 68 #include "intel_mg_phy_regs.h" 69 #include "intel_modeset_lock.h" 70 #include "intel_pps.h" 71 #include "intel_psr.h" 72 #include "intel_quirks.h" 73 #include "intel_snps_phy.h" 74 #include "intel_tc.h" 75 #include "intel_vdsc.h" 76 #include "intel_vdsc_regs.h" 77 #include "skl_scaler.h" 78 #include "skl_universal_plane.h" 79 80 static const u8 index_to_dp_signal_levels[] = { 81 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 82 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 83 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 84 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 85 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 86 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 87 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 88 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 91 }; 92 93 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 94 const struct intel_ddi_buf_trans *trans) 95 { 96 int level; 97 98 level = intel_bios_hdmi_level_shift(encoder->devdata); 99 if (level < 0) 100 level = trans->hdmi_default_entry; 101 102 return level; 103 } 104 105 static bool has_buf_trans_select(struct drm_i915_private *i915) 106 { 107 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 108 } 109 110 static bool has_iboost(struct drm_i915_private *i915) 111 { 112 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 113 } 114 115 /* 116 * Starting with Haswell, DDI port buffers must be programmed with correct 117 * values in advance. This function programs the correct values for 118 * DP/eDP/FDI use cases. 119 */ 120 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 121 const struct intel_crtc_state *crtc_state) 122 { 123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 124 u32 iboost_bit = 0; 125 int i, n_entries; 126 enum port port = encoder->port; 127 const struct intel_ddi_buf_trans *trans; 128 129 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 130 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 131 return; 132 133 /* If we're boosting the current, set bit 31 of trans1 */ 134 if (has_iboost(dev_priv) && 135 intel_bios_dp_boost_level(encoder->devdata)) 136 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 137 138 for (i = 0; i < n_entries; i++) { 139 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 140 trans->entries[i].hsw.trans1 | iboost_bit); 141 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 142 trans->entries[i].hsw.trans2); 143 } 144 } 145 146 /* 147 * Starting with Haswell, DDI port buffers must be programmed with correct 148 * values in advance. This function programs the correct values for 149 * HDMI/DVI use cases. 150 */ 151 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 152 const struct intel_crtc_state *crtc_state) 153 { 154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 155 int level = intel_ddi_level(encoder, crtc_state, 0); 156 u32 iboost_bit = 0; 157 int n_entries; 158 enum port port = encoder->port; 159 const struct intel_ddi_buf_trans *trans; 160 161 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 162 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 163 return; 164 165 /* If we're boosting the current, set bit 31 of trans1 */ 166 if (has_iboost(dev_priv) && 167 intel_bios_hdmi_boost_level(encoder->devdata)) 168 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 169 170 /* Entry 9 is for HDMI: */ 171 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 172 trans->entries[level].hsw.trans1 | iboost_bit); 173 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 174 trans->entries[level].hsw.trans2); 175 } 176 177 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 178 { 179 int ret; 180 181 /* FIXME: find out why Bspec's 100us timeout is too short */ 182 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 183 XELPDP_PORT_BUF_PHY_IDLE), 10000); 184 if (ret) 185 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 186 port_name(port)); 187 } 188 189 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 190 enum port port) 191 { 192 if (IS_BROXTON(dev_priv)) { 193 udelay(16); 194 return; 195 } 196 197 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 198 DDI_BUF_IS_IDLE), 8)) 199 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 200 port_name(port)); 201 } 202 203 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 204 { 205 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 206 enum port port = encoder->port; 207 int timeout_us; 208 int ret; 209 210 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 211 if (DISPLAY_VER(dev_priv) < 10) { 212 usleep_range(518, 1000); 213 return; 214 } 215 216 if (DISPLAY_VER(dev_priv) >= 14) { 217 timeout_us = 10000; 218 } else if (IS_DG2(dev_priv)) { 219 timeout_us = 1200; 220 } else if (DISPLAY_VER(dev_priv) >= 12) { 221 if (intel_encoder_is_tc(encoder)) 222 timeout_us = 3000; 223 else 224 timeout_us = 1000; 225 } else { 226 timeout_us = 500; 227 } 228 229 if (DISPLAY_VER(dev_priv) >= 14) 230 ret = _wait_for(!(intel_de_read(dev_priv, 231 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 232 XELPDP_PORT_BUF_PHY_IDLE), 233 timeout_us, 10, 10); 234 else 235 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 236 timeout_us, 10, 10); 237 238 if (ret) 239 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 240 port_name(port)); 241 } 242 243 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 244 { 245 switch (pll->info->id) { 246 case DPLL_ID_WRPLL1: 247 return PORT_CLK_SEL_WRPLL1; 248 case DPLL_ID_WRPLL2: 249 return PORT_CLK_SEL_WRPLL2; 250 case DPLL_ID_SPLL: 251 return PORT_CLK_SEL_SPLL; 252 case DPLL_ID_LCPLL_810: 253 return PORT_CLK_SEL_LCPLL_810; 254 case DPLL_ID_LCPLL_1350: 255 return PORT_CLK_SEL_LCPLL_1350; 256 case DPLL_ID_LCPLL_2700: 257 return PORT_CLK_SEL_LCPLL_2700; 258 default: 259 MISSING_CASE(pll->info->id); 260 return PORT_CLK_SEL_NONE; 261 } 262 } 263 264 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 265 const struct intel_crtc_state *crtc_state) 266 { 267 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 268 int clock = crtc_state->port_clock; 269 const enum intel_dpll_id id = pll->info->id; 270 271 switch (id) { 272 default: 273 /* 274 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 275 * here, so do warn if this get passed in 276 */ 277 MISSING_CASE(id); 278 return DDI_CLK_SEL_NONE; 279 case DPLL_ID_ICL_TBTPLL: 280 switch (clock) { 281 case 162000: 282 return DDI_CLK_SEL_TBT_162; 283 case 270000: 284 return DDI_CLK_SEL_TBT_270; 285 case 540000: 286 return DDI_CLK_SEL_TBT_540; 287 case 810000: 288 return DDI_CLK_SEL_TBT_810; 289 default: 290 MISSING_CASE(clock); 291 return DDI_CLK_SEL_NONE; 292 } 293 case DPLL_ID_ICL_MGPLL1: 294 case DPLL_ID_ICL_MGPLL2: 295 case DPLL_ID_ICL_MGPLL3: 296 case DPLL_ID_ICL_MGPLL4: 297 case DPLL_ID_TGL_MGPLL5: 298 case DPLL_ID_TGL_MGPLL6: 299 return DDI_CLK_SEL_MG; 300 } 301 } 302 303 static u32 ddi_buf_phy_link_rate(int port_clock) 304 { 305 switch (port_clock) { 306 case 162000: 307 return DDI_BUF_PHY_LINK_RATE(0); 308 case 216000: 309 return DDI_BUF_PHY_LINK_RATE(4); 310 case 243000: 311 return DDI_BUF_PHY_LINK_RATE(5); 312 case 270000: 313 return DDI_BUF_PHY_LINK_RATE(1); 314 case 324000: 315 return DDI_BUF_PHY_LINK_RATE(6); 316 case 432000: 317 return DDI_BUF_PHY_LINK_RATE(7); 318 case 540000: 319 return DDI_BUF_PHY_LINK_RATE(2); 320 case 810000: 321 return DDI_BUF_PHY_LINK_RATE(3); 322 default: 323 MISSING_CASE(port_clock); 324 return DDI_BUF_PHY_LINK_RATE(0); 325 } 326 } 327 328 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 329 const struct intel_crtc_state *crtc_state) 330 { 331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 332 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 333 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 334 335 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 336 intel_dp->DP = dig_port->saved_port_bits | 337 DDI_PORT_WIDTH(crtc_state->lane_count) | 338 DDI_BUF_TRANS_SELECT(0); 339 340 if (DISPLAY_VER(i915) >= 14) { 341 if (intel_dp_is_uhbr(crtc_state)) 342 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 343 else 344 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 345 } 346 347 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 348 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 349 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 350 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 351 } 352 } 353 354 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 355 enum port port) 356 { 357 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 358 359 switch (val) { 360 case DDI_CLK_SEL_NONE: 361 return 0; 362 case DDI_CLK_SEL_TBT_162: 363 return 162000; 364 case DDI_CLK_SEL_TBT_270: 365 return 270000; 366 case DDI_CLK_SEL_TBT_540: 367 return 540000; 368 case DDI_CLK_SEL_TBT_810: 369 return 810000; 370 default: 371 MISSING_CASE(val); 372 return 0; 373 } 374 } 375 376 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 377 { 378 /* CRT dotclock is determined via other means */ 379 if (pipe_config->has_pch_encoder) 380 return; 381 382 pipe_config->hw.adjusted_mode.crtc_clock = 383 intel_crtc_dotclock(pipe_config); 384 } 385 386 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 387 const struct drm_connector_state *conn_state) 388 { 389 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 392 u32 temp; 393 394 if (!intel_crtc_has_dp_encoder(crtc_state)) 395 return; 396 397 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 398 399 temp = DP_MSA_MISC_SYNC_CLOCK; 400 401 switch (crtc_state->pipe_bpp) { 402 case 18: 403 temp |= DP_MSA_MISC_6_BPC; 404 break; 405 case 24: 406 temp |= DP_MSA_MISC_8_BPC; 407 break; 408 case 30: 409 temp |= DP_MSA_MISC_10_BPC; 410 break; 411 case 36: 412 temp |= DP_MSA_MISC_12_BPC; 413 break; 414 default: 415 MISSING_CASE(crtc_state->pipe_bpp); 416 break; 417 } 418 419 /* nonsense combination */ 420 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 421 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 422 423 if (crtc_state->limited_color_range) 424 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 425 426 /* 427 * As per DP 1.2 spec section 2.3.4.3 while sending 428 * YCBCR 444 signals we should program MSA MISC1/0 fields with 429 * colorspace information. 430 */ 431 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 432 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 433 434 /* 435 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 436 * of Color Encoding Format and Content Color Gamut] while sending 437 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 438 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 439 */ 440 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 441 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 442 443 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 444 } 445 446 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 447 { 448 if (master_transcoder == TRANSCODER_EDP) 449 return 0; 450 else 451 return master_transcoder + 1; 452 } 453 454 static void 455 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 456 const struct intel_crtc_state *crtc_state) 457 { 458 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 460 u32 val = 0; 461 462 if (intel_dp_is_uhbr(crtc_state)) 463 val = TRANS_DP2_128B132B_CHANNEL_CODING; 464 465 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 466 } 467 468 /* 469 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 470 * 471 * Only intended to be used by intel_ddi_enable_transcoder_func() and 472 * intel_ddi_config_transcoder_func(). 473 */ 474 static u32 475 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 476 const struct intel_crtc_state *crtc_state) 477 { 478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 480 enum pipe pipe = crtc->pipe; 481 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 482 enum port port = encoder->port; 483 u32 temp; 484 485 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 486 temp = TRANS_DDI_FUNC_ENABLE; 487 if (DISPLAY_VER(dev_priv) >= 12) 488 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 489 else 490 temp |= TRANS_DDI_SELECT_PORT(port); 491 492 switch (crtc_state->pipe_bpp) { 493 default: 494 MISSING_CASE(crtc_state->pipe_bpp); 495 fallthrough; 496 case 18: 497 temp |= TRANS_DDI_BPC_6; 498 break; 499 case 24: 500 temp |= TRANS_DDI_BPC_8; 501 break; 502 case 30: 503 temp |= TRANS_DDI_BPC_10; 504 break; 505 case 36: 506 temp |= TRANS_DDI_BPC_12; 507 break; 508 } 509 510 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 511 temp |= TRANS_DDI_PVSYNC; 512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 513 temp |= TRANS_DDI_PHSYNC; 514 515 if (cpu_transcoder == TRANSCODER_EDP) { 516 switch (pipe) { 517 default: 518 MISSING_CASE(pipe); 519 fallthrough; 520 case PIPE_A: 521 /* On Haswell, can only use the always-on power well for 522 * eDP when not using the panel fitter, and when not 523 * using motion blur mitigation (which we don't 524 * support). */ 525 if (crtc_state->pch_pfit.force_thru) 526 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 527 else 528 temp |= TRANS_DDI_EDP_INPUT_A_ON; 529 break; 530 case PIPE_B: 531 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 532 break; 533 case PIPE_C: 534 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 535 break; 536 } 537 } 538 539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 540 if (crtc_state->has_hdmi_sink) 541 temp |= TRANS_DDI_MODE_SELECT_HDMI; 542 else 543 temp |= TRANS_DDI_MODE_SELECT_DVI; 544 545 if (crtc_state->hdmi_scrambling) 546 temp |= TRANS_DDI_HDMI_SCRAMBLING; 547 if (crtc_state->hdmi_high_tmds_clock_ratio) 548 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 549 if (DISPLAY_VER(dev_priv) >= 14) 550 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 551 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 552 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 553 temp |= (crtc_state->fdi_lanes - 1) << 1; 554 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 555 if (intel_dp_is_uhbr(crtc_state)) 556 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 557 else 558 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 559 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 560 561 if (DISPLAY_VER(dev_priv) >= 12) { 562 enum transcoder master; 563 564 master = crtc_state->mst_master_transcoder; 565 drm_WARN_ON(&dev_priv->drm, 566 master == INVALID_TRANSCODER); 567 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 568 } 569 } else { 570 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 } 573 574 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 575 crtc_state->master_transcoder != INVALID_TRANSCODER) { 576 u8 master_select = 577 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 578 579 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 580 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 581 } 582 583 return temp; 584 } 585 586 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 587 const struct intel_crtc_state *crtc_state) 588 { 589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 592 593 if (DISPLAY_VER(dev_priv) >= 11) { 594 enum transcoder master_transcoder = crtc_state->master_transcoder; 595 u32 ctl2 = 0; 596 597 if (master_transcoder != INVALID_TRANSCODER) { 598 u8 master_select = 599 bdw_trans_port_sync_master_select(master_transcoder); 600 601 ctl2 |= PORT_SYNC_MODE_ENABLE | 602 PORT_SYNC_MODE_MASTER_SELECT(master_select); 603 } 604 605 intel_de_write(dev_priv, 606 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 607 } 608 609 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 610 intel_ddi_transcoder_func_reg_val_get(encoder, 611 crtc_state)); 612 } 613 614 /* 615 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 616 * bit. 617 */ 618 static void 619 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 620 const struct intel_crtc_state *crtc_state) 621 { 622 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 624 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 625 u32 ctl; 626 627 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 628 ctl &= ~TRANS_DDI_FUNC_ENABLE; 629 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 630 } 631 632 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 633 { 634 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 636 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 637 u32 ctl; 638 639 if (DISPLAY_VER(dev_priv) >= 11) 640 intel_de_write(dev_priv, 641 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 642 643 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 644 645 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 646 647 ctl &= ~TRANS_DDI_FUNC_ENABLE; 648 649 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 650 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 651 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 652 653 if (DISPLAY_VER(dev_priv) >= 12) { 654 if (!intel_dp_mst_is_master_trans(crtc_state)) { 655 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 656 TRANS_DDI_MODE_SELECT_MASK); 657 } 658 } else { 659 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 660 } 661 662 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 663 664 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 665 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 666 drm_dbg_kms(&dev_priv->drm, 667 "Quirk Increase DDI disabled time\n"); 668 /* Quirk time at 100ms for reliable operation */ 669 msleep(100); 670 } 671 } 672 673 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 674 enum transcoder cpu_transcoder, 675 bool enable, u32 hdcp_mask) 676 { 677 struct drm_device *dev = intel_encoder->base.dev; 678 struct drm_i915_private *dev_priv = to_i915(dev); 679 intel_wakeref_t wakeref; 680 int ret = 0; 681 682 wakeref = intel_display_power_get_if_enabled(dev_priv, 683 intel_encoder->power_domain); 684 if (drm_WARN_ON(dev, !wakeref)) 685 return -ENXIO; 686 687 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 688 hdcp_mask, enable ? hdcp_mask : 0); 689 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 690 return ret; 691 } 692 693 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 694 { 695 struct drm_device *dev = intel_connector->base.dev; 696 struct drm_i915_private *dev_priv = to_i915(dev); 697 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 698 int type = intel_connector->base.connector_type; 699 enum port port = encoder->port; 700 enum transcoder cpu_transcoder; 701 intel_wakeref_t wakeref; 702 enum pipe pipe = 0; 703 u32 tmp; 704 bool ret; 705 706 wakeref = intel_display_power_get_if_enabled(dev_priv, 707 encoder->power_domain); 708 if (!wakeref) 709 return false; 710 711 if (!encoder->get_hw_state(encoder, &pipe)) { 712 ret = false; 713 goto out; 714 } 715 716 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 717 cpu_transcoder = TRANSCODER_EDP; 718 else 719 cpu_transcoder = (enum transcoder) pipe; 720 721 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 722 723 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 724 case TRANS_DDI_MODE_SELECT_HDMI: 725 case TRANS_DDI_MODE_SELECT_DVI: 726 ret = type == DRM_MODE_CONNECTOR_HDMIA; 727 break; 728 729 case TRANS_DDI_MODE_SELECT_DP_SST: 730 ret = type == DRM_MODE_CONNECTOR_eDP || 731 type == DRM_MODE_CONNECTOR_DisplayPort; 732 break; 733 734 case TRANS_DDI_MODE_SELECT_DP_MST: 735 /* if the transcoder is in MST state then 736 * connector isn't connected */ 737 ret = false; 738 break; 739 740 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 741 if (HAS_DP20(dev_priv)) 742 /* 128b/132b */ 743 ret = false; 744 else 745 /* FDI */ 746 ret = type == DRM_MODE_CONNECTOR_VGA; 747 break; 748 749 default: 750 ret = false; 751 break; 752 } 753 754 out: 755 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 756 757 return ret; 758 } 759 760 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 761 u8 *pipe_mask, bool *is_dp_mst) 762 { 763 struct drm_device *dev = encoder->base.dev; 764 struct drm_i915_private *dev_priv = to_i915(dev); 765 enum port port = encoder->port; 766 intel_wakeref_t wakeref; 767 enum pipe p; 768 u32 tmp; 769 u8 mst_pipe_mask; 770 771 *pipe_mask = 0; 772 *is_dp_mst = false; 773 774 wakeref = intel_display_power_get_if_enabled(dev_priv, 775 encoder->power_domain); 776 if (!wakeref) 777 return; 778 779 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 780 if (!(tmp & DDI_BUF_CTL_ENABLE)) 781 goto out; 782 783 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 784 tmp = intel_de_read(dev_priv, 785 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 786 787 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 788 default: 789 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 790 fallthrough; 791 case TRANS_DDI_EDP_INPUT_A_ON: 792 case TRANS_DDI_EDP_INPUT_A_ONOFF: 793 *pipe_mask = BIT(PIPE_A); 794 break; 795 case TRANS_DDI_EDP_INPUT_B_ONOFF: 796 *pipe_mask = BIT(PIPE_B); 797 break; 798 case TRANS_DDI_EDP_INPUT_C_ONOFF: 799 *pipe_mask = BIT(PIPE_C); 800 break; 801 } 802 803 goto out; 804 } 805 806 mst_pipe_mask = 0; 807 for_each_pipe(dev_priv, p) { 808 enum transcoder cpu_transcoder = (enum transcoder)p; 809 unsigned int port_mask, ddi_select; 810 intel_wakeref_t trans_wakeref; 811 812 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 813 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 814 if (!trans_wakeref) 815 continue; 816 817 if (DISPLAY_VER(dev_priv) >= 12) { 818 port_mask = TGL_TRANS_DDI_PORT_MASK; 819 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 820 } else { 821 port_mask = TRANS_DDI_PORT_MASK; 822 ddi_select = TRANS_DDI_SELECT_PORT(port); 823 } 824 825 tmp = intel_de_read(dev_priv, 826 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 827 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 828 trans_wakeref); 829 830 if ((tmp & port_mask) != ddi_select) 831 continue; 832 833 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 834 (HAS_DP20(dev_priv) && 835 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 836 mst_pipe_mask |= BIT(p); 837 838 *pipe_mask |= BIT(p); 839 } 840 841 if (!*pipe_mask) 842 drm_dbg_kms(&dev_priv->drm, 843 "No pipe for [ENCODER:%d:%s] found\n", 844 encoder->base.base.id, encoder->base.name); 845 846 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 847 drm_dbg_kms(&dev_priv->drm, 848 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 849 encoder->base.base.id, encoder->base.name, 850 *pipe_mask); 851 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 852 } 853 854 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 855 drm_dbg_kms(&dev_priv->drm, 856 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 857 encoder->base.base.id, encoder->base.name, 858 *pipe_mask, mst_pipe_mask); 859 else 860 *is_dp_mst = mst_pipe_mask; 861 862 out: 863 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 864 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 865 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 866 BXT_PHY_LANE_POWERDOWN_ACK | 867 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 868 drm_err(&dev_priv->drm, 869 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 870 encoder->base.base.id, encoder->base.name, tmp); 871 } 872 873 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 874 } 875 876 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 877 enum pipe *pipe) 878 { 879 u8 pipe_mask; 880 bool is_mst; 881 882 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 883 884 if (is_mst || !pipe_mask) 885 return false; 886 887 *pipe = ffs(pipe_mask) - 1; 888 889 return true; 890 } 891 892 static enum intel_display_power_domain 893 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 894 const struct intel_crtc_state *crtc_state) 895 { 896 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 897 898 /* 899 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 900 * DC states enabled at the same time, while for driver initiated AUX 901 * transfers we need the same AUX IOs to be powered but with DC states 902 * disabled. Accordingly use the AUX_IO_<port> power domain here which 903 * leaves DC states enabled. 904 * 905 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 906 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 907 * well, so we can acquire a wider AUX_<port> power domain reference 908 * instead of a specific AUX_IO_<port> reference without powering up any 909 * extra wells. 910 */ 911 if (intel_encoder_can_psr(&dig_port->base)) 912 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 913 else if (DISPLAY_VER(i915) < 14 && 914 (intel_crtc_has_dp_encoder(crtc_state) || 915 intel_encoder_is_tc(&dig_port->base))) 916 return intel_aux_power_domain(dig_port); 917 else 918 return POWER_DOMAIN_INVALID; 919 } 920 921 static void 922 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 923 const struct intel_crtc_state *crtc_state) 924 { 925 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 926 enum intel_display_power_domain domain = 927 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 928 929 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 930 931 if (domain == POWER_DOMAIN_INVALID) 932 return; 933 934 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 935 } 936 937 static void 938 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 939 const struct intel_crtc_state *crtc_state) 940 { 941 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 942 enum intel_display_power_domain domain = 943 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 944 intel_wakeref_t wf; 945 946 wf = fetch_and_zero(&dig_port->aux_wakeref); 947 if (!wf) 948 return; 949 950 intel_display_power_put(i915, domain, wf); 951 } 952 953 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 954 struct intel_crtc_state *crtc_state) 955 { 956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 957 struct intel_digital_port *dig_port; 958 959 /* 960 * TODO: Add support for MST encoders. Atm, the following should never 961 * happen since fake-MST encoders don't set their get_power_domains() 962 * hook. 963 */ 964 if (drm_WARN_ON(&dev_priv->drm, 965 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 966 return; 967 968 dig_port = enc_to_dig_port(encoder); 969 970 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 971 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 972 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 973 dig_port->ddi_io_power_domain); 974 } 975 976 main_link_aux_power_domain_get(dig_port, crtc_state); 977 } 978 979 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 980 const struct intel_crtc_state *crtc_state) 981 { 982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 983 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 984 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 985 enum phy phy = intel_encoder_to_phy(encoder); 986 u32 val; 987 988 if (cpu_transcoder == TRANSCODER_EDP) 989 return; 990 991 if (DISPLAY_VER(dev_priv) >= 13) 992 val = TGL_TRANS_CLK_SEL_PORT(phy); 993 else if (DISPLAY_VER(dev_priv) >= 12) 994 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 995 else 996 val = TRANS_CLK_SEL_PORT(encoder->port); 997 998 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 999 } 1000 1001 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1002 { 1003 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1004 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1005 u32 val; 1006 1007 if (cpu_transcoder == TRANSCODER_EDP) 1008 return; 1009 1010 if (DISPLAY_VER(dev_priv) >= 12) 1011 val = TGL_TRANS_CLK_SEL_DISABLED; 1012 else 1013 val = TRANS_CLK_SEL_DISABLED; 1014 1015 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1016 } 1017 1018 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1019 enum port port, u8 iboost) 1020 { 1021 u32 tmp; 1022 1023 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1024 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1025 if (iboost) 1026 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1027 else 1028 tmp |= BALANCE_LEG_DISABLE(port); 1029 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1030 } 1031 1032 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1033 const struct intel_crtc_state *crtc_state, 1034 int level) 1035 { 1036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1038 u8 iboost; 1039 1040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1041 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1042 else 1043 iboost = intel_bios_dp_boost_level(encoder->devdata); 1044 1045 if (iboost == 0) { 1046 const struct intel_ddi_buf_trans *trans; 1047 int n_entries; 1048 1049 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1050 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1051 return; 1052 1053 iboost = trans->entries[level].hsw.i_boost; 1054 } 1055 1056 /* Make sure that the requested I_boost is valid */ 1057 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1058 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1059 return; 1060 } 1061 1062 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1063 1064 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1065 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1066 } 1067 1068 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1069 const struct intel_crtc_state *crtc_state) 1070 { 1071 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1073 int n_entries; 1074 1075 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1076 1077 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1078 n_entries = 1; 1079 if (drm_WARN_ON(&dev_priv->drm, 1080 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1081 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1082 1083 return index_to_dp_signal_levels[n_entries - 1] & 1084 DP_TRAIN_VOLTAGE_SWING_MASK; 1085 } 1086 1087 /* 1088 * We assume that the full set of pre-emphasis values can be 1089 * used on all DDI platforms. Should that change we need to 1090 * rethink this code. 1091 */ 1092 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1093 { 1094 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1095 } 1096 1097 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1098 int lane) 1099 { 1100 if (crtc_state->port_clock > 600000) 1101 return 0; 1102 1103 if (crtc_state->lane_count == 4) 1104 return lane >= 1 ? LOADGEN_SELECT : 0; 1105 else 1106 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1107 } 1108 1109 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1110 const struct intel_crtc_state *crtc_state) 1111 { 1112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1113 const struct intel_ddi_buf_trans *trans; 1114 enum phy phy = intel_encoder_to_phy(encoder); 1115 int n_entries, ln; 1116 u32 val; 1117 1118 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1119 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1120 return; 1121 1122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1123 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1124 1125 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1126 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1127 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1128 intel_dp->hobl_active ? val : 0); 1129 } 1130 1131 /* Set PORT_TX_DW5 */ 1132 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1133 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1134 TAP2_DISABLE | TAP3_DISABLE); 1135 val |= SCALING_MODE_SEL(0x2); 1136 val |= RTERM_SELECT(0x6); 1137 val |= TAP3_DISABLE; 1138 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1139 1140 /* Program PORT_TX_DW2 */ 1141 for (ln = 0; ln < 4; ln++) { 1142 int level = intel_ddi_level(encoder, crtc_state, ln); 1143 1144 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1145 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1146 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1147 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1148 RCOMP_SCALAR(0x98)); 1149 } 1150 1151 /* Program PORT_TX_DW4 */ 1152 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1153 for (ln = 0; ln < 4; ln++) { 1154 int level = intel_ddi_level(encoder, crtc_state, ln); 1155 1156 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1157 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1158 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1159 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1160 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1161 } 1162 1163 /* Program PORT_TX_DW7 */ 1164 for (ln = 0; ln < 4; ln++) { 1165 int level = intel_ddi_level(encoder, crtc_state, ln); 1166 1167 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1168 N_SCALAR_MASK, 1169 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1170 } 1171 } 1172 1173 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1174 const struct intel_crtc_state *crtc_state) 1175 { 1176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1177 enum phy phy = intel_encoder_to_phy(encoder); 1178 u32 val; 1179 int ln; 1180 1181 /* 1182 * 1. If port type is eDP or DP, 1183 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1184 * else clear to 0b. 1185 */ 1186 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1187 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1188 val &= ~COMMON_KEEPER_EN; 1189 else 1190 val |= COMMON_KEEPER_EN; 1191 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1192 1193 /* 2. Program loadgen select */ 1194 /* 1195 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1196 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1197 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1198 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1199 */ 1200 for (ln = 0; ln < 4; ln++) { 1201 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1202 LOADGEN_SELECT, 1203 icl_combo_phy_loadgen_select(crtc_state, ln)); 1204 } 1205 1206 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1207 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1208 0, SUS_CLOCK_CONFIG); 1209 1210 /* 4. Clear training enable to change swing values */ 1211 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1212 val &= ~TX_TRAINING_EN; 1213 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1214 1215 /* 5. Program swing and de-emphasis */ 1216 icl_ddi_combo_vswing_program(encoder, crtc_state); 1217 1218 /* 6. Set training enable to trigger update */ 1219 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1220 val |= TX_TRAINING_EN; 1221 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1222 } 1223 1224 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1225 const struct intel_crtc_state *crtc_state) 1226 { 1227 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1228 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1229 const struct intel_ddi_buf_trans *trans; 1230 int n_entries, ln; 1231 1232 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1233 return; 1234 1235 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1236 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1237 return; 1238 1239 for (ln = 0; ln < 2; ln++) { 1240 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1241 CRI_USE_FS32, 0); 1242 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1243 CRI_USE_FS32, 0); 1244 } 1245 1246 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1247 for (ln = 0; ln < 2; ln++) { 1248 int level; 1249 1250 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1251 1252 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1253 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1254 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1255 1256 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1257 1258 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1259 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1260 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1261 } 1262 1263 /* Program MG_TX_DRVCTRL with values from vswing table */ 1264 for (ln = 0; ln < 2; ln++) { 1265 int level; 1266 1267 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1268 1269 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1270 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1271 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1272 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1273 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1274 CRI_TXDEEMPH_OVERRIDE_EN); 1275 1276 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1277 1278 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1279 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1280 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1281 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1282 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1283 CRI_TXDEEMPH_OVERRIDE_EN); 1284 1285 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1286 } 1287 1288 /* 1289 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1290 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1291 * values from table for which TX1 and TX2 enabled. 1292 */ 1293 for (ln = 0; ln < 2; ln++) { 1294 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1295 CFG_LOW_RATE_LKREN_EN, 1296 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1297 } 1298 1299 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1300 for (ln = 0; ln < 2; ln++) { 1301 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1302 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1303 CFG_AMI_CK_DIV_OVERRIDE_EN, 1304 crtc_state->port_clock > 500000 ? 1305 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1306 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1307 1308 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1309 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1310 CFG_AMI_CK_DIV_OVERRIDE_EN, 1311 crtc_state->port_clock > 500000 ? 1312 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1313 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1314 } 1315 1316 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1317 for (ln = 0; ln < 2; ln++) { 1318 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1319 0, CRI_CALCINIT); 1320 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1321 0, CRI_CALCINIT); 1322 } 1323 } 1324 1325 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state) 1327 { 1328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1329 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1330 const struct intel_ddi_buf_trans *trans; 1331 int n_entries, ln; 1332 1333 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1334 return; 1335 1336 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1337 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1338 return; 1339 1340 for (ln = 0; ln < 2; ln++) { 1341 int level; 1342 1343 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1344 1345 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1346 1347 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1348 DKL_TX_PRESHOOT_COEFF_MASK | 1349 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1350 DKL_TX_VSWING_CONTROL_MASK, 1351 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1352 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1353 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1354 1355 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1356 1357 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1358 DKL_TX_PRESHOOT_COEFF_MASK | 1359 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1360 DKL_TX_VSWING_CONTROL_MASK, 1361 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1362 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1363 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1364 1365 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1366 DKL_TX_DP20BITMODE, 0); 1367 1368 if (IS_ALDERLAKE_P(dev_priv)) { 1369 u32 val; 1370 1371 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1372 if (ln == 0) { 1373 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1374 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1375 } else { 1376 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1377 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1378 } 1379 } else { 1380 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1381 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1382 } 1383 1384 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1385 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1386 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1387 val); 1388 } 1389 } 1390 } 1391 1392 static int translate_signal_level(struct intel_dp *intel_dp, 1393 u8 signal_levels) 1394 { 1395 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1396 int i; 1397 1398 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1399 if (index_to_dp_signal_levels[i] == signal_levels) 1400 return i; 1401 } 1402 1403 drm_WARN(&i915->drm, 1, 1404 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1405 signal_levels); 1406 1407 return 0; 1408 } 1409 1410 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1411 const struct intel_crtc_state *crtc_state, 1412 int lane) 1413 { 1414 u8 train_set = intel_dp->train_set[lane]; 1415 1416 if (intel_dp_is_uhbr(crtc_state)) { 1417 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1418 } else { 1419 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1420 DP_TRAIN_PRE_EMPHASIS_MASK); 1421 1422 return translate_signal_level(intel_dp, signal_levels); 1423 } 1424 } 1425 1426 int intel_ddi_level(struct intel_encoder *encoder, 1427 const struct intel_crtc_state *crtc_state, 1428 int lane) 1429 { 1430 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1431 const struct intel_ddi_buf_trans *trans; 1432 int level, n_entries; 1433 1434 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1435 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1436 return 0; 1437 1438 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1439 level = intel_ddi_hdmi_level(encoder, trans); 1440 else 1441 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1442 lane); 1443 1444 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1445 level = n_entries - 1; 1446 1447 return level; 1448 } 1449 1450 static void 1451 hsw_set_signal_levels(struct intel_encoder *encoder, 1452 const struct intel_crtc_state *crtc_state) 1453 { 1454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1456 int level = intel_ddi_level(encoder, crtc_state, 0); 1457 enum port port = encoder->port; 1458 u32 signal_levels; 1459 1460 if (has_iboost(dev_priv)) 1461 skl_ddi_set_iboost(encoder, crtc_state, level); 1462 1463 /* HDMI ignores the rest */ 1464 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1465 return; 1466 1467 signal_levels = DDI_BUF_TRANS_SELECT(level); 1468 1469 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1470 signal_levels); 1471 1472 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1473 intel_dp->DP |= signal_levels; 1474 1475 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1476 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1477 } 1478 1479 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1480 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1481 { 1482 mutex_lock(&i915->display.dpll.lock); 1483 1484 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1485 1486 /* 1487 * "This step and the step before must be 1488 * done with separate register writes." 1489 */ 1490 intel_de_rmw(i915, reg, clk_off, 0); 1491 1492 mutex_unlock(&i915->display.dpll.lock); 1493 } 1494 1495 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1496 u32 clk_off) 1497 { 1498 mutex_lock(&i915->display.dpll.lock); 1499 1500 intel_de_rmw(i915, reg, 0, clk_off); 1501 1502 mutex_unlock(&i915->display.dpll.lock); 1503 } 1504 1505 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1506 u32 clk_off) 1507 { 1508 return !(intel_de_read(i915, reg) & clk_off); 1509 } 1510 1511 static struct intel_shared_dpll * 1512 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1513 u32 clk_sel_mask, u32 clk_sel_shift) 1514 { 1515 enum intel_dpll_id id; 1516 1517 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1518 1519 return intel_get_shared_dpll_by_id(i915, id); 1520 } 1521 1522 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1523 const struct intel_crtc_state *crtc_state) 1524 { 1525 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1526 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1527 enum phy phy = intel_encoder_to_phy(encoder); 1528 1529 if (drm_WARN_ON(&i915->drm, !pll)) 1530 return; 1531 1532 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1533 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1534 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1535 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1536 } 1537 1538 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1539 { 1540 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1541 enum phy phy = intel_encoder_to_phy(encoder); 1542 1543 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1544 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1545 } 1546 1547 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1548 { 1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1550 enum phy phy = intel_encoder_to_phy(encoder); 1551 1552 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1553 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1554 } 1555 1556 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1557 { 1558 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1559 enum phy phy = intel_encoder_to_phy(encoder); 1560 1561 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1562 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1563 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1564 } 1565 1566 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1567 const struct intel_crtc_state *crtc_state) 1568 { 1569 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1570 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1571 enum phy phy = intel_encoder_to_phy(encoder); 1572 1573 if (drm_WARN_ON(&i915->drm, !pll)) 1574 return; 1575 1576 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1578 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1579 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1580 } 1581 1582 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1583 { 1584 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1585 enum phy phy = intel_encoder_to_phy(encoder); 1586 1587 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1588 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1589 } 1590 1591 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1592 { 1593 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1594 enum phy phy = intel_encoder_to_phy(encoder); 1595 1596 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1597 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1598 } 1599 1600 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1601 { 1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1603 enum phy phy = intel_encoder_to_phy(encoder); 1604 1605 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1606 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1607 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1608 } 1609 1610 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1611 const struct intel_crtc_state *crtc_state) 1612 { 1613 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1614 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1615 enum phy phy = intel_encoder_to_phy(encoder); 1616 1617 if (drm_WARN_ON(&i915->drm, !pll)) 1618 return; 1619 1620 /* 1621 * If we fail this, something went very wrong: first 2 PLLs should be 1622 * used by first 2 phys and last 2 PLLs by last phys 1623 */ 1624 if (drm_WARN_ON(&i915->drm, 1625 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1626 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1627 return; 1628 1629 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1630 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1631 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1632 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1633 } 1634 1635 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1636 { 1637 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1638 enum phy phy = intel_encoder_to_phy(encoder); 1639 1640 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1641 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1642 } 1643 1644 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1645 { 1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1647 enum phy phy = intel_encoder_to_phy(encoder); 1648 1649 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1650 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1651 } 1652 1653 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1654 { 1655 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 enum intel_dpll_id id; 1658 u32 val; 1659 1660 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1661 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1662 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1663 id = val; 1664 1665 /* 1666 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1667 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1668 * bit for phy C and D. 1669 */ 1670 if (phy >= PHY_C) 1671 id += DPLL_ID_DG1_DPLL2; 1672 1673 return intel_get_shared_dpll_by_id(i915, id); 1674 } 1675 1676 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1677 const struct intel_crtc_state *crtc_state) 1678 { 1679 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1680 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1681 enum phy phy = intel_encoder_to_phy(encoder); 1682 1683 if (drm_WARN_ON(&i915->drm, !pll)) 1684 return; 1685 1686 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1688 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1689 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1690 } 1691 1692 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 enum phy phy = intel_encoder_to_phy(encoder); 1696 1697 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1698 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1699 } 1700 1701 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1702 { 1703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1704 enum phy phy = intel_encoder_to_phy(encoder); 1705 1706 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1707 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1708 } 1709 1710 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1711 { 1712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1713 enum phy phy = intel_encoder_to_phy(encoder); 1714 1715 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1716 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1717 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1718 } 1719 1720 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1721 const struct intel_crtc_state *crtc_state) 1722 { 1723 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1724 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1725 enum port port = encoder->port; 1726 1727 if (drm_WARN_ON(&i915->drm, !pll)) 1728 return; 1729 1730 /* 1731 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1732 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1733 */ 1734 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1735 1736 icl_ddi_combo_enable_clock(encoder, crtc_state); 1737 } 1738 1739 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1740 { 1741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1742 enum port port = encoder->port; 1743 1744 icl_ddi_combo_disable_clock(encoder); 1745 1746 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1747 } 1748 1749 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1750 { 1751 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1752 enum port port = encoder->port; 1753 u32 tmp; 1754 1755 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1756 1757 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1758 return false; 1759 1760 return icl_ddi_combo_is_clock_enabled(encoder); 1761 } 1762 1763 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1764 const struct intel_crtc_state *crtc_state) 1765 { 1766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1767 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1768 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1769 enum port port = encoder->port; 1770 1771 if (drm_WARN_ON(&i915->drm, !pll)) 1772 return; 1773 1774 intel_de_write(i915, DDI_CLK_SEL(port), 1775 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1776 1777 mutex_lock(&i915->display.dpll.lock); 1778 1779 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1780 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1781 1782 mutex_unlock(&i915->display.dpll.lock); 1783 } 1784 1785 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1786 { 1787 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1788 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1789 enum port port = encoder->port; 1790 1791 mutex_lock(&i915->display.dpll.lock); 1792 1793 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1794 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1795 1796 mutex_unlock(&i915->display.dpll.lock); 1797 1798 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1799 } 1800 1801 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1802 { 1803 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1804 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1805 enum port port = encoder->port; 1806 u32 tmp; 1807 1808 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1809 1810 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1811 return false; 1812 1813 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1814 1815 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1816 } 1817 1818 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1819 { 1820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1821 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1822 enum port port = encoder->port; 1823 enum intel_dpll_id id; 1824 u32 tmp; 1825 1826 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1827 1828 switch (tmp & DDI_CLK_SEL_MASK) { 1829 case DDI_CLK_SEL_TBT_162: 1830 case DDI_CLK_SEL_TBT_270: 1831 case DDI_CLK_SEL_TBT_540: 1832 case DDI_CLK_SEL_TBT_810: 1833 id = DPLL_ID_ICL_TBTPLL; 1834 break; 1835 case DDI_CLK_SEL_MG: 1836 id = icl_tc_port_to_pll_id(tc_port); 1837 break; 1838 default: 1839 MISSING_CASE(tmp); 1840 fallthrough; 1841 case DDI_CLK_SEL_NONE: 1842 return NULL; 1843 } 1844 1845 return intel_get_shared_dpll_by_id(i915, id); 1846 } 1847 1848 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1849 { 1850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1851 enum intel_dpll_id id; 1852 1853 switch (encoder->port) { 1854 case PORT_A: 1855 id = DPLL_ID_SKL_DPLL0; 1856 break; 1857 case PORT_B: 1858 id = DPLL_ID_SKL_DPLL1; 1859 break; 1860 case PORT_C: 1861 id = DPLL_ID_SKL_DPLL2; 1862 break; 1863 default: 1864 MISSING_CASE(encoder->port); 1865 return NULL; 1866 } 1867 1868 return intel_get_shared_dpll_by_id(i915, id); 1869 } 1870 1871 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1872 const struct intel_crtc_state *crtc_state) 1873 { 1874 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1875 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1876 enum port port = encoder->port; 1877 1878 if (drm_WARN_ON(&i915->drm, !pll)) 1879 return; 1880 1881 mutex_lock(&i915->display.dpll.lock); 1882 1883 intel_de_rmw(i915, DPLL_CTRL2, 1884 DPLL_CTRL2_DDI_CLK_OFF(port) | 1885 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1886 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1887 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1888 1889 mutex_unlock(&i915->display.dpll.lock); 1890 } 1891 1892 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1893 { 1894 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1895 enum port port = encoder->port; 1896 1897 mutex_lock(&i915->display.dpll.lock); 1898 1899 intel_de_rmw(i915, DPLL_CTRL2, 1900 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1901 1902 mutex_unlock(&i915->display.dpll.lock); 1903 } 1904 1905 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1906 { 1907 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1908 enum port port = encoder->port; 1909 1910 /* 1911 * FIXME Not sure if the override affects both 1912 * the PLL selection and the CLK_OFF bit. 1913 */ 1914 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1915 } 1916 1917 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1918 { 1919 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1920 enum port port = encoder->port; 1921 enum intel_dpll_id id; 1922 u32 tmp; 1923 1924 tmp = intel_de_read(i915, DPLL_CTRL2); 1925 1926 /* 1927 * FIXME Not sure if the override affects both 1928 * the PLL selection and the CLK_OFF bit. 1929 */ 1930 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1931 return NULL; 1932 1933 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1934 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1935 1936 return intel_get_shared_dpll_by_id(i915, id); 1937 } 1938 1939 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1940 const struct intel_crtc_state *crtc_state) 1941 { 1942 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1943 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1944 enum port port = encoder->port; 1945 1946 if (drm_WARN_ON(&i915->drm, !pll)) 1947 return; 1948 1949 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1950 } 1951 1952 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1953 { 1954 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1955 enum port port = encoder->port; 1956 1957 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1958 } 1959 1960 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1961 { 1962 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1963 enum port port = encoder->port; 1964 1965 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1966 } 1967 1968 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 enum port port = encoder->port; 1972 enum intel_dpll_id id; 1973 u32 tmp; 1974 1975 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1976 1977 switch (tmp & PORT_CLK_SEL_MASK) { 1978 case PORT_CLK_SEL_WRPLL1: 1979 id = DPLL_ID_WRPLL1; 1980 break; 1981 case PORT_CLK_SEL_WRPLL2: 1982 id = DPLL_ID_WRPLL2; 1983 break; 1984 case PORT_CLK_SEL_SPLL: 1985 id = DPLL_ID_SPLL; 1986 break; 1987 case PORT_CLK_SEL_LCPLL_810: 1988 id = DPLL_ID_LCPLL_810; 1989 break; 1990 case PORT_CLK_SEL_LCPLL_1350: 1991 id = DPLL_ID_LCPLL_1350; 1992 break; 1993 case PORT_CLK_SEL_LCPLL_2700: 1994 id = DPLL_ID_LCPLL_2700; 1995 break; 1996 default: 1997 MISSING_CASE(tmp); 1998 fallthrough; 1999 case PORT_CLK_SEL_NONE: 2000 return NULL; 2001 } 2002 2003 return intel_get_shared_dpll_by_id(i915, id); 2004 } 2005 2006 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2007 const struct intel_crtc_state *crtc_state) 2008 { 2009 if (encoder->enable_clock) 2010 encoder->enable_clock(encoder, crtc_state); 2011 } 2012 2013 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2014 { 2015 if (encoder->disable_clock) 2016 encoder->disable_clock(encoder); 2017 } 2018 2019 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2020 { 2021 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2022 u32 port_mask; 2023 bool ddi_clk_needed; 2024 2025 /* 2026 * In case of DP MST, we sanitize the primary encoder only, not the 2027 * virtual ones. 2028 */ 2029 if (encoder->type == INTEL_OUTPUT_DP_MST) 2030 return; 2031 2032 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2033 u8 pipe_mask; 2034 bool is_mst; 2035 2036 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2037 /* 2038 * In the unlikely case that BIOS enables DP in MST mode, just 2039 * warn since our MST HW readout is incomplete. 2040 */ 2041 if (drm_WARN_ON(&i915->drm, is_mst)) 2042 return; 2043 } 2044 2045 port_mask = BIT(encoder->port); 2046 ddi_clk_needed = encoder->base.crtc; 2047 2048 if (encoder->type == INTEL_OUTPUT_DSI) { 2049 struct intel_encoder *other_encoder; 2050 2051 port_mask = intel_dsi_encoder_ports(encoder); 2052 /* 2053 * Sanity check that we haven't incorrectly registered another 2054 * encoder using any of the ports of this DSI encoder. 2055 */ 2056 for_each_intel_encoder(&i915->drm, other_encoder) { 2057 if (other_encoder == encoder) 2058 continue; 2059 2060 if (drm_WARN_ON(&i915->drm, 2061 port_mask & BIT(other_encoder->port))) 2062 return; 2063 } 2064 /* 2065 * For DSI we keep the ddi clocks gated 2066 * except during enable/disable sequence. 2067 */ 2068 ddi_clk_needed = false; 2069 } 2070 2071 if (ddi_clk_needed || !encoder->is_clock_enabled || 2072 !encoder->is_clock_enabled(encoder)) 2073 return; 2074 2075 drm_notice(&i915->drm, 2076 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2077 encoder->base.base.id, encoder->base.name); 2078 2079 encoder->disable_clock(encoder); 2080 } 2081 2082 static void 2083 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2084 const struct intel_crtc_state *crtc_state) 2085 { 2086 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2087 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2088 u32 ln0, ln1, pin_assignment; 2089 u8 width; 2090 2091 if (!intel_encoder_is_tc(&dig_port->base) || 2092 intel_tc_port_in_tbt_alt_mode(dig_port)) 2093 return; 2094 2095 if (DISPLAY_VER(dev_priv) >= 12) { 2096 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2097 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2098 } else { 2099 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2100 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2101 } 2102 2103 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2104 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2105 2106 /* DPPATC */ 2107 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2108 width = crtc_state->lane_count; 2109 2110 switch (pin_assignment) { 2111 case 0x0: 2112 drm_WARN_ON(&dev_priv->drm, 2113 !intel_tc_port_in_legacy_mode(dig_port)); 2114 if (width == 1) { 2115 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2116 } else { 2117 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2118 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2119 } 2120 break; 2121 case 0x1: 2122 if (width == 4) { 2123 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2124 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2125 } 2126 break; 2127 case 0x2: 2128 if (width == 2) { 2129 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2130 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2131 } 2132 break; 2133 case 0x3: 2134 case 0x5: 2135 if (width == 1) { 2136 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2137 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2138 } else { 2139 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2140 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2141 } 2142 break; 2143 case 0x4: 2144 case 0x6: 2145 if (width == 1) { 2146 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2147 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2148 } else { 2149 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2150 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2151 } 2152 break; 2153 default: 2154 MISSING_CASE(pin_assignment); 2155 } 2156 2157 if (DISPLAY_VER(dev_priv) >= 12) { 2158 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2159 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2160 } else { 2161 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2162 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2163 } 2164 } 2165 2166 static enum transcoder 2167 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2168 { 2169 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2170 return crtc_state->mst_master_transcoder; 2171 else 2172 return crtc_state->cpu_transcoder; 2173 } 2174 2175 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2176 const struct intel_crtc_state *crtc_state) 2177 { 2178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2179 2180 if (DISPLAY_VER(dev_priv) >= 12) 2181 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2182 else 2183 return DP_TP_CTL(encoder->port); 2184 } 2185 2186 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2187 const struct intel_crtc_state *crtc_state) 2188 { 2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2190 2191 if (DISPLAY_VER(dev_priv) >= 12) 2192 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2193 else 2194 return DP_TP_STATUS(encoder->port); 2195 } 2196 2197 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2198 const struct intel_crtc_state *crtc_state, 2199 bool enable) 2200 { 2201 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2202 2203 if (!crtc_state->vrr.enable) 2204 return; 2205 2206 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2207 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2208 drm_dbg_kms(&i915->drm, 2209 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2210 str_enable_disable(enable)); 2211 } 2212 2213 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2214 const struct intel_crtc_state *crtc_state, 2215 bool enable) 2216 { 2217 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2218 2219 if (!crtc_state->fec_enable) 2220 return; 2221 2222 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2223 enable ? DP_FEC_READY : 0) <= 0) 2224 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2225 enable ? "enabled" : "disabled"); 2226 2227 if (enable && 2228 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2229 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2230 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2231 } 2232 2233 static int read_fec_detected_status(struct drm_dp_aux *aux) 2234 { 2235 int ret; 2236 u8 status; 2237 2238 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2239 if (ret < 0) 2240 return ret; 2241 2242 return status; 2243 } 2244 2245 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2246 { 2247 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2248 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2249 int status; 2250 int err; 2251 2252 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2253 status & mask || status < 0, 2254 10000, 200000); 2255 2256 if (!err && status >= 0) 2257 return; 2258 2259 if (err == -ETIMEDOUT) 2260 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2261 str_enabled_disabled(enabled)); 2262 else 2263 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2264 } 2265 2266 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2267 const struct intel_crtc_state *crtc_state, 2268 bool enabled) 2269 { 2270 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2271 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2272 int ret; 2273 2274 if (!crtc_state->fec_enable) 2275 return; 2276 2277 if (enabled) 2278 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2279 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2280 else 2281 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2282 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2283 2284 if (ret) 2285 drm_err(&i915->drm, 2286 "Timeout waiting for FEC live state to get %s\n", 2287 str_enabled_disabled(enabled)); 2288 2289 /* 2290 * At least the Synoptics MST hub doesn't set the detected flag for 2291 * FEC decoding disabling so skip waiting for that. 2292 */ 2293 if (enabled) 2294 wait_for_fec_detected(&intel_dp->aux, enabled); 2295 } 2296 2297 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2298 const struct intel_crtc_state *crtc_state) 2299 { 2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2301 2302 if (!crtc_state->fec_enable) 2303 return; 2304 2305 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2306 0, DP_TP_CTL_FEC_ENABLE); 2307 } 2308 2309 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2310 const struct intel_crtc_state *crtc_state) 2311 { 2312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2313 2314 if (!crtc_state->fec_enable) 2315 return; 2316 2317 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2318 DP_TP_CTL_FEC_ENABLE, 0); 2319 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2320 } 2321 2322 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2323 const struct intel_crtc_state *crtc_state) 2324 { 2325 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2326 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2327 2328 if (intel_encoder_is_combo(encoder)) { 2329 enum phy phy = intel_encoder_to_phy(encoder); 2330 bool lane_reversal = 2331 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2332 2333 intel_combo_phy_power_up_lanes(i915, phy, false, 2334 crtc_state->lane_count, 2335 lane_reversal); 2336 } 2337 } 2338 2339 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2340 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2341 { 2342 if (IS_ALDERLAKE_P(i915)) 2343 return BIT(PIPE_A) | BIT(PIPE_B); 2344 else 2345 return BIT(PIPE_A); 2346 } 2347 2348 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2349 struct intel_crtc_state *pipe_config) 2350 { 2351 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2352 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2353 enum pipe pipe = crtc->pipe; 2354 u32 dss1; 2355 2356 if (!HAS_MSO(i915)) 2357 return; 2358 2359 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2360 2361 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2362 if (!pipe_config->splitter.enable) 2363 return; 2364 2365 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2366 pipe_config->splitter.enable = false; 2367 return; 2368 } 2369 2370 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2371 default: 2372 drm_WARN(&i915->drm, true, 2373 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2374 fallthrough; 2375 case SPLITTER_CONFIGURATION_2_SEGMENT: 2376 pipe_config->splitter.link_count = 2; 2377 break; 2378 case SPLITTER_CONFIGURATION_4_SEGMENT: 2379 pipe_config->splitter.link_count = 4; 2380 break; 2381 } 2382 2383 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2384 } 2385 2386 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2387 { 2388 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2389 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2390 enum pipe pipe = crtc->pipe; 2391 u32 dss1 = 0; 2392 2393 if (!HAS_MSO(i915)) 2394 return; 2395 2396 if (crtc_state->splitter.enable) { 2397 dss1 |= SPLITTER_ENABLE; 2398 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2399 if (crtc_state->splitter.link_count == 2) 2400 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2401 else 2402 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2403 } 2404 2405 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2406 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2407 OVERLAP_PIXELS_MASK, dss1); 2408 } 2409 2410 static u8 mtl_get_port_width(u8 lane_count) 2411 { 2412 switch (lane_count) { 2413 case 1: 2414 return 0; 2415 case 2: 2416 return 1; 2417 case 3: 2418 return 4; 2419 case 4: 2420 return 3; 2421 default: 2422 MISSING_CASE(lane_count); 2423 return 4; 2424 } 2425 } 2426 2427 static void 2428 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2429 { 2430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2431 enum port port = encoder->port; 2432 i915_reg_t reg; 2433 u32 set_bits, wait_bits; 2434 2435 if (DISPLAY_VER(dev_priv) >= 20) { 2436 reg = DDI_BUF_CTL(port); 2437 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2438 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2439 } else { 2440 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2441 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2442 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2443 } 2444 2445 intel_de_rmw(dev_priv, reg, 0, set_bits); 2446 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2447 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2448 port_name(port)); 2449 } 2450 } 2451 2452 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2453 const struct intel_crtc_state *crtc_state) 2454 { 2455 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2456 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2457 enum port port = encoder->port; 2458 u32 val; 2459 2460 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2461 val &= ~XELPDP_PORT_WIDTH_MASK; 2462 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2463 2464 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2465 if (intel_dp_is_uhbr(crtc_state)) 2466 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2467 else 2468 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2469 2470 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2471 val |= XELPDP_PORT_REVERSAL; 2472 2473 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2474 } 2475 2476 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2477 { 2478 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2479 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2480 u32 val; 2481 2482 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2483 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2484 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2485 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2486 } 2487 2488 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2489 struct intel_encoder *encoder, 2490 const struct intel_crtc_state *crtc_state, 2491 const struct drm_connector_state *conn_state) 2492 { 2493 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2494 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2495 2496 intel_dp_set_link_params(intel_dp, 2497 crtc_state->port_clock, 2498 crtc_state->lane_count); 2499 2500 /* 2501 * We only configure what the register value will be here. Actual 2502 * enabling happens during link training farther down. 2503 */ 2504 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2505 2506 /* 2507 * 1. Enable Power Wells 2508 * 2509 * This was handled at the beginning of intel_atomic_commit_tail(), 2510 * before we called down into this function. 2511 */ 2512 2513 /* 2. PMdemand was already set */ 2514 2515 /* 3. Select Thunderbolt */ 2516 mtl_port_buf_ctl_io_selection(encoder); 2517 2518 /* 4. Enable Panel Power if PPS is required */ 2519 intel_pps_on(intel_dp); 2520 2521 /* 5. Enable the port PLL */ 2522 intel_ddi_enable_clock(encoder, crtc_state); 2523 2524 /* 2525 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2526 * Transcoder. 2527 */ 2528 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2529 2530 /* 2531 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2532 */ 2533 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2534 2535 /* 2536 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2537 * Transport Select 2538 */ 2539 intel_ddi_config_transcoder_func(encoder, crtc_state); 2540 2541 /* 2542 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2543 */ 2544 intel_ddi_mso_configure(crtc_state); 2545 2546 if (!is_mst) 2547 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2548 2549 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2550 if (!is_mst) 2551 intel_dp_sink_enable_decompression(state, 2552 to_intel_connector(conn_state->connector), 2553 crtc_state); 2554 2555 /* 2556 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2557 * in the FEC_CONFIGURATION register to 1 before initiating link 2558 * training 2559 */ 2560 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2561 2562 intel_dp_check_frl_training(intel_dp); 2563 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2564 2565 /* 2566 * 6. The rest of the below are substeps under the bspec's "Enable and 2567 * Train Display Port" step. Note that steps that are specific to 2568 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2569 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2570 * us when active_mst_links==0, so any steps designated for "single 2571 * stream or multi-stream master transcoder" can just be performed 2572 * unconditionally here. 2573 * 2574 * mtl_ddi_prepare_link_retrain() that is called by 2575 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2576 * 6.i and 6.j 2577 * 2578 * 6.k Follow DisplayPort specification training sequence (see notes for 2579 * failure handling) 2580 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2581 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2582 * (timeout after 800 us) 2583 */ 2584 intel_dp_start_link_train(intel_dp, crtc_state); 2585 2586 /* 6.n Set DP_TP_CTL link training to Normal */ 2587 if (!is_trans_port_sync_mode(crtc_state)) 2588 intel_dp_stop_link_train(intel_dp, crtc_state); 2589 2590 /* 6.o Configure and enable FEC if needed */ 2591 intel_ddi_enable_fec(encoder, crtc_state); 2592 2593 if (!is_mst) 2594 intel_dsc_dp_pps_write(encoder, crtc_state); 2595 } 2596 2597 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2598 struct intel_encoder *encoder, 2599 const struct intel_crtc_state *crtc_state, 2600 const struct drm_connector_state *conn_state) 2601 { 2602 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2603 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2604 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2605 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2606 2607 intel_dp_set_link_params(intel_dp, 2608 crtc_state->port_clock, 2609 crtc_state->lane_count); 2610 2611 /* 2612 * We only configure what the register value will be here. Actual 2613 * enabling happens during link training farther down. 2614 */ 2615 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2616 2617 /* 2618 * 1. Enable Power Wells 2619 * 2620 * This was handled at the beginning of intel_atomic_commit_tail(), 2621 * before we called down into this function. 2622 */ 2623 2624 /* 2. Enable Panel Power if PPS is required */ 2625 intel_pps_on(intel_dp); 2626 2627 /* 2628 * 3. For non-TBT Type-C ports, set FIA lane count 2629 * (DFLEXDPSP.DPX4TXLATC) 2630 * 2631 * This was done before tgl_ddi_pre_enable_dp by 2632 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2633 */ 2634 2635 /* 2636 * 4. Enable the port PLL. 2637 * 2638 * The PLL enabling itself was already done before this function by 2639 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2640 * configure the PLL to port mapping here. 2641 */ 2642 intel_ddi_enable_clock(encoder, crtc_state); 2643 2644 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2645 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2646 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2647 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2648 dig_port->ddi_io_power_domain); 2649 } 2650 2651 /* 6. Program DP_MODE */ 2652 icl_program_mg_dp_mode(dig_port, crtc_state); 2653 2654 /* 2655 * 7. The rest of the below are substeps under the bspec's "Enable and 2656 * Train Display Port" step. Note that steps that are specific to 2657 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2658 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2659 * us when active_mst_links==0, so any steps designated for "single 2660 * stream or multi-stream master transcoder" can just be performed 2661 * unconditionally here. 2662 */ 2663 2664 /* 2665 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2666 * Transcoder. 2667 */ 2668 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2669 2670 if (HAS_DP20(dev_priv)) 2671 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2672 2673 /* 2674 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2675 * Transport Select 2676 */ 2677 intel_ddi_config_transcoder_func(encoder, crtc_state); 2678 2679 /* 2680 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2681 * selected 2682 * 2683 * This will be handled by the intel_dp_start_link_train() farther 2684 * down this function. 2685 */ 2686 2687 /* 7.e Configure voltage swing and related IO settings */ 2688 encoder->set_signal_levels(encoder, crtc_state); 2689 2690 /* 2691 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2692 * the used lanes of the DDI. 2693 */ 2694 intel_ddi_power_up_lanes(encoder, crtc_state); 2695 2696 /* 2697 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2698 */ 2699 intel_ddi_mso_configure(crtc_state); 2700 2701 if (!is_mst) 2702 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2703 2704 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2705 if (!is_mst) 2706 intel_dp_sink_enable_decompression(state, 2707 to_intel_connector(conn_state->connector), 2708 crtc_state); 2709 /* 2710 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2711 * in the FEC_CONFIGURATION register to 1 before initiating link 2712 * training 2713 */ 2714 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2715 2716 intel_dp_check_frl_training(intel_dp); 2717 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2718 2719 /* 2720 * 7.i Follow DisplayPort specification training sequence (see notes for 2721 * failure handling) 2722 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2723 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2724 * (timeout after 800 us) 2725 */ 2726 intel_dp_start_link_train(intel_dp, crtc_state); 2727 2728 /* 7.k Set DP_TP_CTL link training to Normal */ 2729 if (!is_trans_port_sync_mode(crtc_state)) 2730 intel_dp_stop_link_train(intel_dp, crtc_state); 2731 2732 /* 7.l Configure and enable FEC if needed */ 2733 intel_ddi_enable_fec(encoder, crtc_state); 2734 2735 if (!is_mst) 2736 intel_dsc_dp_pps_write(encoder, crtc_state); 2737 } 2738 2739 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2740 struct intel_encoder *encoder, 2741 const struct intel_crtc_state *crtc_state, 2742 const struct drm_connector_state *conn_state) 2743 { 2744 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2745 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2746 enum port port = encoder->port; 2747 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2748 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2749 2750 if (DISPLAY_VER(dev_priv) < 11) 2751 drm_WARN_ON(&dev_priv->drm, 2752 is_mst && (port == PORT_A || port == PORT_E)); 2753 else 2754 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2755 2756 intel_dp_set_link_params(intel_dp, 2757 crtc_state->port_clock, 2758 crtc_state->lane_count); 2759 2760 /* 2761 * We only configure what the register value will be here. Actual 2762 * enabling happens during link training farther down. 2763 */ 2764 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2765 2766 intel_pps_on(intel_dp); 2767 2768 intel_ddi_enable_clock(encoder, crtc_state); 2769 2770 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2771 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2772 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2773 dig_port->ddi_io_power_domain); 2774 } 2775 2776 icl_program_mg_dp_mode(dig_port, crtc_state); 2777 2778 if (has_buf_trans_select(dev_priv)) 2779 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2780 2781 encoder->set_signal_levels(encoder, crtc_state); 2782 2783 intel_ddi_power_up_lanes(encoder, crtc_state); 2784 2785 if (!is_mst) 2786 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2787 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2788 if (!is_mst) 2789 intel_dp_sink_enable_decompression(state, 2790 to_intel_connector(conn_state->connector), 2791 crtc_state); 2792 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2793 intel_dp_start_link_train(intel_dp, crtc_state); 2794 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2795 !is_trans_port_sync_mode(crtc_state)) 2796 intel_dp_stop_link_train(intel_dp, crtc_state); 2797 2798 intel_ddi_enable_fec(encoder, crtc_state); 2799 2800 if (!is_mst) { 2801 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2802 intel_dsc_dp_pps_write(encoder, crtc_state); 2803 } 2804 } 2805 2806 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2807 struct intel_encoder *encoder, 2808 const struct intel_crtc_state *crtc_state, 2809 const struct drm_connector_state *conn_state) 2810 { 2811 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2812 2813 if (HAS_DP20(dev_priv)) 2814 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2815 crtc_state); 2816 2817 /* Panel replay has to be enabled in sink dpcd before link training. */ 2818 if (crtc_state->has_panel_replay) 2819 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2820 2821 if (DISPLAY_VER(dev_priv) >= 14) 2822 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2823 else if (DISPLAY_VER(dev_priv) >= 12) 2824 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2825 else 2826 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2827 2828 /* MST will call a setting of MSA after an allocating of Virtual Channel 2829 * from MST encoder pre_enable callback. 2830 */ 2831 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2832 intel_ddi_set_dp_msa(crtc_state, conn_state); 2833 } 2834 2835 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2836 struct intel_encoder *encoder, 2837 const struct intel_crtc_state *crtc_state, 2838 const struct drm_connector_state *conn_state) 2839 { 2840 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2841 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2843 2844 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2845 intel_ddi_enable_clock(encoder, crtc_state); 2846 2847 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2848 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2849 dig_port->ddi_io_power_domain); 2850 2851 icl_program_mg_dp_mode(dig_port, crtc_state); 2852 2853 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2854 2855 dig_port->set_infoframes(encoder, 2856 crtc_state->has_infoframe, 2857 crtc_state, conn_state); 2858 } 2859 2860 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2861 struct intel_encoder *encoder, 2862 const struct intel_crtc_state *crtc_state, 2863 const struct drm_connector_state *conn_state) 2864 { 2865 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2866 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2867 enum pipe pipe = crtc->pipe; 2868 2869 /* 2870 * When called from DP MST code: 2871 * - conn_state will be NULL 2872 * - encoder will be the main encoder (ie. mst->primary) 2873 * - the main connector associated with this port 2874 * won't be active or linked to a crtc 2875 * - crtc_state will be the state of the first stream to 2876 * be activated on this port, and it may not be the same 2877 * stream that will be deactivated last, but each stream 2878 * should have a state that is identical when it comes to 2879 * the DP link parameteres 2880 */ 2881 2882 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2883 2884 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2885 2886 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2887 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2888 conn_state); 2889 } else { 2890 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2891 2892 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2893 conn_state); 2894 2895 /* FIXME precompute everything properly */ 2896 /* FIXME how do we turn infoframes off again? */ 2897 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2898 dig_port->set_infoframes(encoder, 2899 crtc_state->has_infoframe, 2900 crtc_state, conn_state); 2901 } 2902 } 2903 2904 static void 2905 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2906 { 2907 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2908 enum port port = encoder->port; 2909 i915_reg_t reg; 2910 u32 clr_bits, wait_bits; 2911 2912 if (DISPLAY_VER(dev_priv) >= 20) { 2913 reg = DDI_BUF_CTL(port); 2914 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2915 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2916 } else { 2917 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2918 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2919 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2920 } 2921 2922 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2923 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2924 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2925 port_name(port)); 2926 } 2927 2928 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2929 const struct intel_crtc_state *crtc_state) 2930 { 2931 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2932 enum port port = encoder->port; 2933 u32 val; 2934 2935 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2936 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2937 if (val & DDI_BUF_CTL_ENABLE) { 2938 val &= ~DDI_BUF_CTL_ENABLE; 2939 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2940 2941 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2942 mtl_wait_ddi_buf_idle(dev_priv, port); 2943 } 2944 2945 /* 3.d Disable D2D Link */ 2946 mtl_ddi_disable_d2d_link(encoder); 2947 2948 /* 3.e Disable DP_TP_CTL */ 2949 if (intel_crtc_has_dp_encoder(crtc_state)) { 2950 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2951 DP_TP_CTL_ENABLE, 0); 2952 } 2953 } 2954 2955 static void disable_ddi_buf(struct intel_encoder *encoder, 2956 const struct intel_crtc_state *crtc_state) 2957 { 2958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2959 enum port port = encoder->port; 2960 bool wait = false; 2961 u32 val; 2962 2963 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2964 if (val & DDI_BUF_CTL_ENABLE) { 2965 val &= ~DDI_BUF_CTL_ENABLE; 2966 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2967 wait = true; 2968 } 2969 2970 if (intel_crtc_has_dp_encoder(crtc_state)) 2971 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2972 DP_TP_CTL_ENABLE, 0); 2973 2974 intel_ddi_disable_fec(encoder, crtc_state); 2975 2976 if (wait) 2977 intel_wait_ddi_buf_idle(dev_priv, port); 2978 } 2979 2980 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2981 const struct intel_crtc_state *crtc_state) 2982 { 2983 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2984 2985 if (DISPLAY_VER(dev_priv) >= 14) { 2986 mtl_disable_ddi_buf(encoder, crtc_state); 2987 2988 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2989 intel_ddi_disable_fec(encoder, crtc_state); 2990 } else { 2991 disable_ddi_buf(encoder, crtc_state); 2992 } 2993 2994 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2995 } 2996 2997 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2998 struct intel_encoder *encoder, 2999 const struct intel_crtc_state *old_crtc_state, 3000 const struct drm_connector_state *old_conn_state) 3001 { 3002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3003 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3004 struct intel_dp *intel_dp = &dig_port->dp; 3005 intel_wakeref_t wakeref; 3006 bool is_mst = intel_crtc_has_type(old_crtc_state, 3007 INTEL_OUTPUT_DP_MST); 3008 3009 if (!is_mst) 3010 intel_dp_set_infoframes(encoder, false, 3011 old_crtc_state, old_conn_state); 3012 3013 /* 3014 * Power down sink before disabling the port, otherwise we end 3015 * up getting interrupts from the sink on detecting link loss. 3016 */ 3017 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3018 3019 if (DISPLAY_VER(dev_priv) >= 12) { 3020 if (is_mst) { 3021 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3022 3023 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 3024 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3025 0); 3026 } 3027 } else { 3028 if (!is_mst) 3029 intel_ddi_disable_transcoder_clock(old_crtc_state); 3030 } 3031 3032 intel_disable_ddi_buf(encoder, old_crtc_state); 3033 3034 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3035 3036 /* 3037 * From TGL spec: "If single stream or multi-stream master transcoder: 3038 * Configure Transcoder Clock select to direct no clock to the 3039 * transcoder" 3040 */ 3041 if (DISPLAY_VER(dev_priv) >= 12) 3042 intel_ddi_disable_transcoder_clock(old_crtc_state); 3043 3044 intel_pps_vdd_on(intel_dp); 3045 intel_pps_off(intel_dp); 3046 3047 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3048 3049 if (wakeref) 3050 intel_display_power_put(dev_priv, 3051 dig_port->ddi_io_power_domain, 3052 wakeref); 3053 3054 intel_ddi_disable_clock(encoder); 3055 3056 /* De-select Thunderbolt */ 3057 if (DISPLAY_VER(dev_priv) >= 14) 3058 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3059 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3060 } 3061 3062 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3063 struct intel_encoder *encoder, 3064 const struct intel_crtc_state *old_crtc_state, 3065 const struct drm_connector_state *old_conn_state) 3066 { 3067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3068 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3069 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3070 intel_wakeref_t wakeref; 3071 3072 dig_port->set_infoframes(encoder, false, 3073 old_crtc_state, old_conn_state); 3074 3075 if (DISPLAY_VER(dev_priv) < 12) 3076 intel_ddi_disable_transcoder_clock(old_crtc_state); 3077 3078 intel_disable_ddi_buf(encoder, old_crtc_state); 3079 3080 if (DISPLAY_VER(dev_priv) >= 12) 3081 intel_ddi_disable_transcoder_clock(old_crtc_state); 3082 3083 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3084 if (wakeref) 3085 intel_display_power_put(dev_priv, 3086 dig_port->ddi_io_power_domain, 3087 wakeref); 3088 3089 intel_ddi_disable_clock(encoder); 3090 3091 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3092 } 3093 3094 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3095 struct intel_encoder *encoder, 3096 const struct intel_crtc_state *old_crtc_state, 3097 const struct drm_connector_state *old_conn_state) 3098 { 3099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3100 struct intel_crtc *pipe_crtc; 3101 3102 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3103 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3104 const struct intel_crtc_state *old_pipe_crtc_state = 3105 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3106 3107 intel_crtc_vblank_off(old_pipe_crtc_state); 3108 } 3109 3110 intel_disable_transcoder(old_crtc_state); 3111 3112 intel_ddi_disable_transcoder_func(old_crtc_state); 3113 3114 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3115 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3116 const struct intel_crtc_state *old_pipe_crtc_state = 3117 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3118 3119 intel_dsc_disable(old_pipe_crtc_state); 3120 3121 if (DISPLAY_VER(dev_priv) >= 9) 3122 skl_scaler_disable(old_pipe_crtc_state); 3123 else 3124 ilk_pfit_disable(old_pipe_crtc_state); 3125 } 3126 } 3127 3128 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3129 struct intel_encoder *encoder, 3130 const struct intel_crtc_state *old_crtc_state, 3131 const struct drm_connector_state *old_conn_state) 3132 { 3133 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3134 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3135 old_conn_state); 3136 3137 /* 3138 * When called from DP MST code: 3139 * - old_conn_state will be NULL 3140 * - encoder will be the main encoder (ie. mst->primary) 3141 * - the main connector associated with this port 3142 * won't be active or linked to a crtc 3143 * - old_crtc_state will be the state of the last stream to 3144 * be deactivated on this port, and it may not be the same 3145 * stream that was activated last, but each stream 3146 * should have a state that is identical when it comes to 3147 * the DP link parameteres 3148 */ 3149 3150 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3151 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3152 old_conn_state); 3153 else 3154 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3155 old_conn_state); 3156 } 3157 3158 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3159 struct intel_encoder *encoder, 3160 const struct intel_crtc_state *old_crtc_state, 3161 const struct drm_connector_state *old_conn_state) 3162 { 3163 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3164 3165 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3166 3167 if (intel_encoder_is_tc(encoder)) 3168 intel_tc_port_put_link(dig_port); 3169 } 3170 3171 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3172 struct intel_encoder *encoder, 3173 const struct intel_crtc_state *crtc_state) 3174 { 3175 const struct drm_connector_state *conn_state; 3176 struct drm_connector *conn; 3177 int i; 3178 3179 if (!crtc_state->sync_mode_slaves_mask) 3180 return; 3181 3182 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3183 struct intel_encoder *slave_encoder = 3184 to_intel_encoder(conn_state->best_encoder); 3185 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3186 const struct intel_crtc_state *slave_crtc_state; 3187 3188 if (!slave_crtc) 3189 continue; 3190 3191 slave_crtc_state = 3192 intel_atomic_get_new_crtc_state(state, slave_crtc); 3193 3194 if (slave_crtc_state->master_transcoder != 3195 crtc_state->cpu_transcoder) 3196 continue; 3197 3198 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3199 slave_crtc_state); 3200 } 3201 3202 usleep_range(200, 400); 3203 3204 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3205 crtc_state); 3206 } 3207 3208 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3209 struct intel_encoder *encoder, 3210 const struct intel_crtc_state *crtc_state, 3211 const struct drm_connector_state *conn_state) 3212 { 3213 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3214 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3215 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3216 enum port port = encoder->port; 3217 3218 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3219 intel_dp_stop_link_train(intel_dp, crtc_state); 3220 3221 drm_connector_update_privacy_screen(conn_state); 3222 intel_edp_backlight_on(crtc_state, conn_state); 3223 3224 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3225 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3226 3227 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3228 } 3229 3230 /* FIXME bad home for this function */ 3231 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3232 enum transcoder cpu_transcoder) 3233 { 3234 return DISPLAY_VER(i915) >= 14 ? 3235 MTL_CHICKEN_TRANS(cpu_transcoder) : 3236 CHICKEN_TRANS(cpu_transcoder); 3237 } 3238 3239 static i915_reg_t 3240 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3241 enum port port) 3242 { 3243 static const enum transcoder trans[] = { 3244 [PORT_A] = TRANSCODER_EDP, 3245 [PORT_B] = TRANSCODER_A, 3246 [PORT_C] = TRANSCODER_B, 3247 [PORT_D] = TRANSCODER_C, 3248 [PORT_E] = TRANSCODER_A, 3249 }; 3250 3251 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3252 3253 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3254 port = PORT_A; 3255 3256 return CHICKEN_TRANS(trans[port]); 3257 } 3258 3259 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3260 struct intel_encoder *encoder, 3261 const struct intel_crtc_state *crtc_state, 3262 const struct drm_connector_state *conn_state) 3263 { 3264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3265 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3266 struct drm_connector *connector = conn_state->connector; 3267 enum port port = encoder->port; 3268 u32 buf_ctl; 3269 3270 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3271 crtc_state->hdmi_high_tmds_clock_ratio, 3272 crtc_state->hdmi_scrambling)) 3273 drm_dbg_kms(&dev_priv->drm, 3274 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3275 connector->base.id, connector->name); 3276 3277 if (has_buf_trans_select(dev_priv)) 3278 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3279 3280 /* e. Enable D2D Link for C10/C20 Phy */ 3281 if (DISPLAY_VER(dev_priv) >= 14) 3282 mtl_ddi_enable_d2d(encoder); 3283 3284 encoder->set_signal_levels(encoder, crtc_state); 3285 3286 /* Display WA #1143: skl,kbl,cfl */ 3287 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3288 /* 3289 * For some reason these chicken bits have been 3290 * stuffed into a transcoder register, event though 3291 * the bits affect a specific DDI port rather than 3292 * a specific transcoder. 3293 */ 3294 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3295 u32 val; 3296 3297 val = intel_de_read(dev_priv, reg); 3298 3299 if (port == PORT_E) 3300 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3301 DDIE_TRAINING_OVERRIDE_VALUE; 3302 else 3303 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3304 DDI_TRAINING_OVERRIDE_VALUE; 3305 3306 intel_de_write(dev_priv, reg, val); 3307 intel_de_posting_read(dev_priv, reg); 3308 3309 udelay(1); 3310 3311 if (port == PORT_E) 3312 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3313 DDIE_TRAINING_OVERRIDE_VALUE); 3314 else 3315 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3316 DDI_TRAINING_OVERRIDE_VALUE); 3317 3318 intel_de_write(dev_priv, reg, val); 3319 } 3320 3321 intel_ddi_power_up_lanes(encoder, crtc_state); 3322 3323 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3324 * are ignored so nothing special needs to be done besides 3325 * enabling the port. 3326 * 3327 * On ADL_P the PHY link rate and lane count must be programmed but 3328 * these are both 0 for HDMI. 3329 * 3330 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3331 * is filled with lane count, already set in the crtc_state. 3332 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3333 */ 3334 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3335 if (DISPLAY_VER(dev_priv) >= 14) { 3336 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3337 u32 port_buf = 0; 3338 3339 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3340 3341 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3342 port_buf |= XELPDP_PORT_REVERSAL; 3343 3344 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3345 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3346 3347 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3348 3349 if (DISPLAY_VER(dev_priv) >= 20) 3350 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3351 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3352 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3353 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3354 } 3355 3356 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3357 3358 intel_wait_ddi_buf_active(encoder); 3359 } 3360 3361 static void intel_enable_ddi(struct intel_atomic_state *state, 3362 struct intel_encoder *encoder, 3363 const struct intel_crtc_state *crtc_state, 3364 const struct drm_connector_state *conn_state) 3365 { 3366 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3367 struct intel_crtc *pipe_crtc; 3368 3369 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3370 3371 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3372 intel_audio_sdp_split_update(crtc_state); 3373 3374 intel_enable_transcoder(crtc_state); 3375 3376 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3377 3378 for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, 3379 intel_crtc_joined_pipe_mask(crtc_state)) { 3380 const struct intel_crtc_state *pipe_crtc_state = 3381 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3382 3383 intel_crtc_vblank_on(pipe_crtc_state); 3384 } 3385 3386 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3387 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3388 else 3389 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3390 3391 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3392 3393 } 3394 3395 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3396 struct intel_encoder *encoder, 3397 const struct intel_crtc_state *old_crtc_state, 3398 const struct drm_connector_state *old_conn_state) 3399 { 3400 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3401 struct intel_connector *connector = 3402 to_intel_connector(old_conn_state->connector); 3403 3404 intel_dp->link_trained = false; 3405 3406 intel_psr_disable(intel_dp, old_crtc_state); 3407 intel_edp_backlight_off(old_conn_state); 3408 /* Disable the decompression in DP Sink */ 3409 intel_dp_sink_disable_decompression(state, 3410 connector, old_crtc_state); 3411 /* Disable Ignore_MSA bit in DP Sink */ 3412 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3413 false); 3414 } 3415 3416 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3417 struct intel_encoder *encoder, 3418 const struct intel_crtc_state *old_crtc_state, 3419 const struct drm_connector_state *old_conn_state) 3420 { 3421 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3422 struct drm_connector *connector = old_conn_state->connector; 3423 3424 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3425 false, false)) 3426 drm_dbg_kms(&i915->drm, 3427 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3428 connector->base.id, connector->name); 3429 } 3430 3431 static void intel_disable_ddi(struct intel_atomic_state *state, 3432 struct intel_encoder *encoder, 3433 const struct intel_crtc_state *old_crtc_state, 3434 const struct drm_connector_state *old_conn_state) 3435 { 3436 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3437 3438 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3439 3440 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3441 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3442 old_conn_state); 3443 else 3444 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3445 old_conn_state); 3446 } 3447 3448 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3449 struct intel_encoder *encoder, 3450 const struct intel_crtc_state *crtc_state, 3451 const struct drm_connector_state *conn_state) 3452 { 3453 intel_ddi_set_dp_msa(crtc_state, conn_state); 3454 3455 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3456 3457 intel_backlight_update(state, encoder, crtc_state, conn_state); 3458 drm_connector_update_privacy_screen(conn_state); 3459 } 3460 3461 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3462 struct intel_encoder *encoder, 3463 const struct intel_crtc_state *crtc_state, 3464 const struct drm_connector_state *conn_state) 3465 { 3466 3467 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3468 !intel_encoder_is_mst(encoder)) 3469 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3470 conn_state); 3471 3472 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3473 } 3474 3475 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3476 struct intel_encoder *encoder, 3477 struct intel_crtc *crtc) 3478 { 3479 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3480 const struct intel_crtc_state *crtc_state = 3481 intel_atomic_get_new_crtc_state(state, crtc); 3482 struct intel_crtc *pipe_crtc; 3483 3484 /* FIXME: Add MTL pll_mgr */ 3485 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3486 return; 3487 3488 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3489 intel_crtc_joined_pipe_mask(crtc_state)) 3490 intel_update_active_dpll(state, pipe_crtc, encoder); 3491 } 3492 3493 static void 3494 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3495 struct intel_encoder *encoder, 3496 const struct intel_crtc_state *crtc_state, 3497 const struct drm_connector_state *conn_state) 3498 { 3499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3500 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3501 bool is_tc_port = intel_encoder_is_tc(encoder); 3502 3503 if (is_tc_port) { 3504 struct intel_crtc *master_crtc = 3505 to_intel_crtc(crtc_state->uapi.crtc); 3506 3507 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3508 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3509 } 3510 3511 main_link_aux_power_domain_get(dig_port, crtc_state); 3512 3513 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3514 /* 3515 * Program the lane count for static/dynamic connections on 3516 * Type-C ports. Skip this step for TBT. 3517 */ 3518 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3519 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3520 bxt_ddi_phy_set_lane_optim_mask(encoder, 3521 crtc_state->lane_lat_optim_mask); 3522 } 3523 3524 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3525 { 3526 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3527 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3528 int ln; 3529 3530 for (ln = 0; ln < 2; ln++) 3531 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3532 } 3533 3534 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3535 const struct intel_crtc_state *crtc_state) 3536 { 3537 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3538 struct intel_encoder *encoder = &dig_port->base; 3539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3540 enum port port = encoder->port; 3541 u32 dp_tp_ctl; 3542 3543 /* 3544 * TODO: To train with only a different voltage swing entry is not 3545 * necessary disable and enable port 3546 */ 3547 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3548 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3549 mtl_disable_ddi_buf(encoder, crtc_state); 3550 3551 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3552 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3553 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3554 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3555 } else { 3556 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3557 if (crtc_state->enhanced_framing) 3558 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3559 } 3560 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3561 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3562 3563 /* 6.f Enable D2D Link */ 3564 mtl_ddi_enable_d2d(encoder); 3565 3566 /* 6.g Configure voltage swing and related IO settings */ 3567 encoder->set_signal_levels(encoder, crtc_state); 3568 3569 /* 6.h Configure PORT_BUF_CTL1 */ 3570 mtl_port_buf_ctl_program(encoder, crtc_state); 3571 3572 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3573 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3574 if (DISPLAY_VER(dev_priv) >= 20) 3575 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3576 3577 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3578 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3579 3580 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3581 intel_wait_ddi_buf_active(encoder); 3582 } 3583 3584 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3585 const struct intel_crtc_state *crtc_state) 3586 { 3587 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3588 struct intel_encoder *encoder = &dig_port->base; 3589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3590 enum port port = encoder->port; 3591 u32 dp_tp_ctl, ddi_buf_ctl; 3592 bool wait = false; 3593 3594 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3595 3596 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3597 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3598 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3599 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3600 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3601 wait = true; 3602 } 3603 3604 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3605 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3606 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3607 3608 if (wait) 3609 intel_wait_ddi_buf_idle(dev_priv, port); 3610 } 3611 3612 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3613 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3614 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3615 } else { 3616 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3617 if (crtc_state->enhanced_framing) 3618 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3619 } 3620 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3621 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3622 3623 if (IS_ALDERLAKE_P(dev_priv) && 3624 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3625 adlp_tbt_to_dp_alt_switch_wa(encoder); 3626 3627 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3628 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3629 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3630 3631 intel_wait_ddi_buf_active(encoder); 3632 } 3633 3634 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3635 const struct intel_crtc_state *crtc_state, 3636 u8 dp_train_pat) 3637 { 3638 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3640 u32 temp; 3641 3642 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3643 3644 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3645 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3646 case DP_TRAINING_PATTERN_DISABLE: 3647 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3648 break; 3649 case DP_TRAINING_PATTERN_1: 3650 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3651 break; 3652 case DP_TRAINING_PATTERN_2: 3653 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3654 break; 3655 case DP_TRAINING_PATTERN_3: 3656 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3657 break; 3658 case DP_TRAINING_PATTERN_4: 3659 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3660 break; 3661 } 3662 3663 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3664 } 3665 3666 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3667 const struct intel_crtc_state *crtc_state) 3668 { 3669 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3670 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3671 enum port port = encoder->port; 3672 3673 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3674 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3675 3676 /* 3677 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3678 * reason we need to set idle transmission mode is to work around a HW 3679 * issue where we enable the pipe while not in idle link-training mode. 3680 * In this case there is requirement to wait for a minimum number of 3681 * idle patterns to be sent. 3682 */ 3683 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3684 return; 3685 3686 if (intel_de_wait_for_set(dev_priv, 3687 dp_tp_status_reg(encoder, crtc_state), 3688 DP_TP_STATUS_IDLE_DONE, 2)) 3689 drm_err(&dev_priv->drm, 3690 "Timed out waiting for DP idle patterns\n"); 3691 } 3692 3693 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3694 enum transcoder cpu_transcoder) 3695 { 3696 if (cpu_transcoder == TRANSCODER_EDP) 3697 return false; 3698 3699 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3700 return false; 3701 3702 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3703 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3704 } 3705 3706 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3707 { 3708 if (crtc_state->port_clock > 594000) 3709 return 2; 3710 else 3711 return 0; 3712 } 3713 3714 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3715 { 3716 if (crtc_state->port_clock > 594000) 3717 return 3; 3718 else 3719 return 0; 3720 } 3721 3722 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3723 { 3724 if (crtc_state->port_clock > 594000) 3725 return 1; 3726 else 3727 return 0; 3728 } 3729 3730 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3731 { 3732 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3733 3734 if (DISPLAY_VER(dev_priv) >= 14) 3735 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3736 else if (DISPLAY_VER(dev_priv) >= 12) 3737 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3738 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3739 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3740 else if (DISPLAY_VER(dev_priv) >= 11) 3741 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3742 } 3743 3744 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3745 enum transcoder cpu_transcoder) 3746 { 3747 u32 master_select; 3748 3749 if (DISPLAY_VER(dev_priv) >= 11) { 3750 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3751 3752 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3753 return INVALID_TRANSCODER; 3754 3755 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3756 } else { 3757 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3758 3759 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3760 return INVALID_TRANSCODER; 3761 3762 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3763 } 3764 3765 if (master_select == 0) 3766 return TRANSCODER_EDP; 3767 else 3768 return master_select - 1; 3769 } 3770 3771 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3772 { 3773 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3774 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3775 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3776 enum transcoder cpu_transcoder; 3777 3778 crtc_state->master_transcoder = 3779 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3780 3781 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3782 enum intel_display_power_domain power_domain; 3783 intel_wakeref_t trans_wakeref; 3784 3785 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3786 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3787 power_domain); 3788 3789 if (!trans_wakeref) 3790 continue; 3791 3792 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3793 crtc_state->cpu_transcoder) 3794 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3795 3796 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3797 } 3798 3799 drm_WARN_ON(&dev_priv->drm, 3800 crtc_state->master_transcoder != INVALID_TRANSCODER && 3801 crtc_state->sync_mode_slaves_mask); 3802 } 3803 3804 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3805 struct intel_crtc_state *pipe_config) 3806 { 3807 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3808 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3809 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3810 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3811 u32 temp, flags = 0; 3812 3813 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3814 if (temp & TRANS_DDI_PHSYNC) 3815 flags |= DRM_MODE_FLAG_PHSYNC; 3816 else 3817 flags |= DRM_MODE_FLAG_NHSYNC; 3818 if (temp & TRANS_DDI_PVSYNC) 3819 flags |= DRM_MODE_FLAG_PVSYNC; 3820 else 3821 flags |= DRM_MODE_FLAG_NVSYNC; 3822 3823 pipe_config->hw.adjusted_mode.flags |= flags; 3824 3825 switch (temp & TRANS_DDI_BPC_MASK) { 3826 case TRANS_DDI_BPC_6: 3827 pipe_config->pipe_bpp = 18; 3828 break; 3829 case TRANS_DDI_BPC_8: 3830 pipe_config->pipe_bpp = 24; 3831 break; 3832 case TRANS_DDI_BPC_10: 3833 pipe_config->pipe_bpp = 30; 3834 break; 3835 case TRANS_DDI_BPC_12: 3836 pipe_config->pipe_bpp = 36; 3837 break; 3838 default: 3839 break; 3840 } 3841 3842 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3843 case TRANS_DDI_MODE_SELECT_HDMI: 3844 pipe_config->has_hdmi_sink = true; 3845 3846 pipe_config->infoframes.enable |= 3847 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3848 3849 if (pipe_config->infoframes.enable) 3850 pipe_config->has_infoframe = true; 3851 3852 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3853 pipe_config->hdmi_scrambling = true; 3854 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3855 pipe_config->hdmi_high_tmds_clock_ratio = true; 3856 fallthrough; 3857 case TRANS_DDI_MODE_SELECT_DVI: 3858 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3859 if (DISPLAY_VER(dev_priv) >= 14) 3860 pipe_config->lane_count = 3861 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3862 else 3863 pipe_config->lane_count = 4; 3864 break; 3865 case TRANS_DDI_MODE_SELECT_DP_SST: 3866 if (encoder->type == INTEL_OUTPUT_EDP) 3867 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3868 else 3869 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3870 pipe_config->lane_count = 3871 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3872 3873 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3874 &pipe_config->dp_m_n); 3875 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3876 &pipe_config->dp_m2_n2); 3877 3878 pipe_config->enhanced_framing = 3879 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3880 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3881 3882 if (DISPLAY_VER(dev_priv) >= 11) 3883 pipe_config->fec_enable = 3884 intel_de_read(dev_priv, 3885 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3886 3887 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3888 pipe_config->infoframes.enable |= 3889 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3890 else 3891 pipe_config->infoframes.enable |= 3892 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3893 break; 3894 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3895 if (!HAS_DP20(dev_priv)) { 3896 /* FDI */ 3897 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3898 pipe_config->enhanced_framing = 3899 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3900 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3901 break; 3902 } 3903 fallthrough; /* 128b/132b */ 3904 case TRANS_DDI_MODE_SELECT_DP_MST: 3905 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3906 pipe_config->lane_count = 3907 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3908 3909 if (DISPLAY_VER(dev_priv) >= 12) 3910 pipe_config->mst_master_transcoder = 3911 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3912 3913 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3914 &pipe_config->dp_m_n); 3915 3916 if (DISPLAY_VER(dev_priv) >= 11) 3917 pipe_config->fec_enable = 3918 intel_de_read(dev_priv, 3919 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3920 3921 pipe_config->infoframes.enable |= 3922 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3923 break; 3924 default: 3925 break; 3926 } 3927 } 3928 3929 static void intel_ddi_get_config(struct intel_encoder *encoder, 3930 struct intel_crtc_state *pipe_config) 3931 { 3932 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3933 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3934 3935 /* XXX: DSI transcoder paranoia */ 3936 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3937 return; 3938 3939 intel_ddi_read_func_ctl(encoder, pipe_config); 3940 3941 intel_ddi_mso_get_config(encoder, pipe_config); 3942 3943 pipe_config->has_audio = 3944 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3945 3946 if (encoder->type == INTEL_OUTPUT_EDP) 3947 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3948 3949 ddi_dotclock_get(pipe_config); 3950 3951 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3952 pipe_config->lane_lat_optim_mask = 3953 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3954 3955 intel_ddi_compute_min_voltage_level(pipe_config); 3956 3957 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3958 3959 intel_read_infoframe(encoder, pipe_config, 3960 HDMI_INFOFRAME_TYPE_AVI, 3961 &pipe_config->infoframes.avi); 3962 intel_read_infoframe(encoder, pipe_config, 3963 HDMI_INFOFRAME_TYPE_SPD, 3964 &pipe_config->infoframes.spd); 3965 intel_read_infoframe(encoder, pipe_config, 3966 HDMI_INFOFRAME_TYPE_VENDOR, 3967 &pipe_config->infoframes.hdmi); 3968 intel_read_infoframe(encoder, pipe_config, 3969 HDMI_INFOFRAME_TYPE_DRM, 3970 &pipe_config->infoframes.drm); 3971 3972 if (DISPLAY_VER(dev_priv) >= 8) 3973 bdw_get_trans_port_sync_config(pipe_config); 3974 3975 intel_psr_get_config(encoder, pipe_config); 3976 3977 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3978 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3979 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 3980 3981 intel_audio_codec_get_config(encoder, pipe_config); 3982 } 3983 3984 void intel_ddi_get_clock(struct intel_encoder *encoder, 3985 struct intel_crtc_state *crtc_state, 3986 struct intel_shared_dpll *pll) 3987 { 3988 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3989 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3990 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3991 bool pll_active; 3992 3993 if (drm_WARN_ON(&i915->drm, !pll)) 3994 return; 3995 3996 port_dpll->pll = pll; 3997 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3998 drm_WARN_ON(&i915->drm, !pll_active); 3999 4000 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4001 4002 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4003 &crtc_state->dpll_hw_state); 4004 } 4005 4006 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4007 struct intel_crtc_state *crtc_state) 4008 { 4009 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4010 4011 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 4012 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4013 } else { 4014 intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state); 4015 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state); 4016 } 4017 4018 intel_ddi_get_config(encoder, crtc_state); 4019 } 4020 4021 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4022 struct intel_crtc_state *crtc_state) 4023 { 4024 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 4025 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 4026 4027 intel_ddi_get_config(encoder, crtc_state); 4028 } 4029 4030 static void adls_ddi_get_config(struct intel_encoder *encoder, 4031 struct intel_crtc_state *crtc_state) 4032 { 4033 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4034 intel_ddi_get_config(encoder, crtc_state); 4035 } 4036 4037 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4038 struct intel_crtc_state *crtc_state) 4039 { 4040 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4041 intel_ddi_get_config(encoder, crtc_state); 4042 } 4043 4044 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4045 struct intel_crtc_state *crtc_state) 4046 { 4047 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4048 intel_ddi_get_config(encoder, crtc_state); 4049 } 4050 4051 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4052 struct intel_crtc_state *crtc_state) 4053 { 4054 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4055 intel_ddi_get_config(encoder, crtc_state); 4056 } 4057 4058 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4059 { 4060 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4061 } 4062 4063 static enum icl_port_dpll_id 4064 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4065 const struct intel_crtc_state *crtc_state) 4066 { 4067 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4068 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4069 4070 if (drm_WARN_ON(&i915->drm, !pll)) 4071 return ICL_PORT_DPLL_DEFAULT; 4072 4073 if (icl_ddi_tc_pll_is_tbt(pll)) 4074 return ICL_PORT_DPLL_DEFAULT; 4075 else 4076 return ICL_PORT_DPLL_MG_PHY; 4077 } 4078 4079 enum icl_port_dpll_id 4080 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4081 const struct intel_crtc_state *crtc_state) 4082 { 4083 if (!encoder->port_pll_type) 4084 return ICL_PORT_DPLL_DEFAULT; 4085 4086 return encoder->port_pll_type(encoder, crtc_state); 4087 } 4088 4089 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4090 struct intel_crtc_state *crtc_state, 4091 struct intel_shared_dpll *pll) 4092 { 4093 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4094 enum icl_port_dpll_id port_dpll_id; 4095 struct icl_port_dpll *port_dpll; 4096 bool pll_active; 4097 4098 if (drm_WARN_ON(&i915->drm, !pll)) 4099 return; 4100 4101 if (icl_ddi_tc_pll_is_tbt(pll)) 4102 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4103 else 4104 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4105 4106 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4107 4108 port_dpll->pll = pll; 4109 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4110 drm_WARN_ON(&i915->drm, !pll_active); 4111 4112 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4113 4114 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4115 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4116 else 4117 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4118 &crtc_state->dpll_hw_state); 4119 } 4120 4121 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4122 struct intel_crtc_state *crtc_state) 4123 { 4124 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4125 intel_ddi_get_config(encoder, crtc_state); 4126 } 4127 4128 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4129 struct intel_crtc_state *crtc_state) 4130 { 4131 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4132 intel_ddi_get_config(encoder, crtc_state); 4133 } 4134 4135 static void skl_ddi_get_config(struct intel_encoder *encoder, 4136 struct intel_crtc_state *crtc_state) 4137 { 4138 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4139 intel_ddi_get_config(encoder, crtc_state); 4140 } 4141 4142 void hsw_ddi_get_config(struct intel_encoder *encoder, 4143 struct intel_crtc_state *crtc_state) 4144 { 4145 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4146 intel_ddi_get_config(encoder, crtc_state); 4147 } 4148 4149 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4150 const struct intel_crtc_state *crtc_state) 4151 { 4152 if (intel_encoder_is_tc(encoder)) 4153 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4154 crtc_state); 4155 4156 if (intel_encoder_is_dp(encoder)) 4157 intel_dp_sync_state(encoder, crtc_state); 4158 } 4159 4160 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4161 struct intel_crtc_state *crtc_state) 4162 { 4163 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4164 bool fastset = true; 4165 4166 if (intel_encoder_is_tc(encoder)) { 4167 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4168 encoder->base.base.id, encoder->base.name); 4169 crtc_state->uapi.mode_changed = true; 4170 fastset = false; 4171 } 4172 4173 if (intel_crtc_has_dp_encoder(crtc_state) && 4174 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4175 fastset = false; 4176 4177 return fastset; 4178 } 4179 4180 static enum intel_output_type 4181 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4182 struct intel_crtc_state *crtc_state, 4183 struct drm_connector_state *conn_state) 4184 { 4185 switch (conn_state->connector->connector_type) { 4186 case DRM_MODE_CONNECTOR_HDMIA: 4187 return INTEL_OUTPUT_HDMI; 4188 case DRM_MODE_CONNECTOR_eDP: 4189 return INTEL_OUTPUT_EDP; 4190 case DRM_MODE_CONNECTOR_DisplayPort: 4191 return INTEL_OUTPUT_DP; 4192 default: 4193 MISSING_CASE(conn_state->connector->connector_type); 4194 return INTEL_OUTPUT_UNUSED; 4195 } 4196 } 4197 4198 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4199 struct intel_crtc_state *pipe_config, 4200 struct drm_connector_state *conn_state) 4201 { 4202 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4204 enum port port = encoder->port; 4205 int ret; 4206 4207 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4208 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4209 4210 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4211 pipe_config->has_hdmi_sink = 4212 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4213 4214 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4215 } else { 4216 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4217 } 4218 4219 if (ret) 4220 return ret; 4221 4222 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4223 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4224 pipe_config->pch_pfit.force_thru = 4225 pipe_config->pch_pfit.enabled || 4226 pipe_config->crc_enabled; 4227 4228 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4229 pipe_config->lane_lat_optim_mask = 4230 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4231 4232 intel_ddi_compute_min_voltage_level(pipe_config); 4233 4234 return 0; 4235 } 4236 4237 static bool mode_equal(const struct drm_display_mode *mode1, 4238 const struct drm_display_mode *mode2) 4239 { 4240 return drm_mode_match(mode1, mode2, 4241 DRM_MODE_MATCH_TIMINGS | 4242 DRM_MODE_MATCH_FLAGS | 4243 DRM_MODE_MATCH_3D_FLAGS) && 4244 mode1->clock == mode2->clock; /* we want an exact match */ 4245 } 4246 4247 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4248 const struct intel_link_m_n *m_n_2) 4249 { 4250 return m_n_1->tu == m_n_2->tu && 4251 m_n_1->data_m == m_n_2->data_m && 4252 m_n_1->data_n == m_n_2->data_n && 4253 m_n_1->link_m == m_n_2->link_m && 4254 m_n_1->link_n == m_n_2->link_n; 4255 } 4256 4257 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4258 const struct intel_crtc_state *crtc_state2) 4259 { 4260 /* 4261 * FIXME the modeset sequence is currently wrong and 4262 * can't deal with bigjoiner + port sync at the same time. 4263 */ 4264 return crtc_state1->hw.active && crtc_state2->hw.active && 4265 !crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes && 4266 crtc_state1->output_types == crtc_state2->output_types && 4267 crtc_state1->output_format == crtc_state2->output_format && 4268 crtc_state1->lane_count == crtc_state2->lane_count && 4269 crtc_state1->port_clock == crtc_state2->port_clock && 4270 mode_equal(&crtc_state1->hw.adjusted_mode, 4271 &crtc_state2->hw.adjusted_mode) && 4272 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4273 } 4274 4275 static u8 4276 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4277 int tile_group_id) 4278 { 4279 struct drm_connector *connector; 4280 const struct drm_connector_state *conn_state; 4281 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4282 struct intel_atomic_state *state = 4283 to_intel_atomic_state(ref_crtc_state->uapi.state); 4284 u8 transcoders = 0; 4285 int i; 4286 4287 /* 4288 * We don't enable port sync on BDW due to missing w/as and 4289 * due to not having adjusted the modeset sequence appropriately. 4290 */ 4291 if (DISPLAY_VER(dev_priv) < 9) 4292 return 0; 4293 4294 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4295 return 0; 4296 4297 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4298 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4299 const struct intel_crtc_state *crtc_state; 4300 4301 if (!crtc) 4302 continue; 4303 4304 if (!connector->has_tile || 4305 connector->tile_group->id != 4306 tile_group_id) 4307 continue; 4308 crtc_state = intel_atomic_get_new_crtc_state(state, 4309 crtc); 4310 if (!crtcs_port_sync_compatible(ref_crtc_state, 4311 crtc_state)) 4312 continue; 4313 transcoders |= BIT(crtc_state->cpu_transcoder); 4314 } 4315 4316 return transcoders; 4317 } 4318 4319 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4320 struct intel_crtc_state *crtc_state, 4321 struct drm_connector_state *conn_state) 4322 { 4323 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4324 struct drm_connector *connector = conn_state->connector; 4325 u8 port_sync_transcoders = 0; 4326 4327 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4328 encoder->base.base.id, encoder->base.name, 4329 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4330 4331 if (connector->has_tile) 4332 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4333 connector->tile_group->id); 4334 4335 /* 4336 * EDP Transcoders cannot be ensalved 4337 * make them a master always when present 4338 */ 4339 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4340 crtc_state->master_transcoder = TRANSCODER_EDP; 4341 else 4342 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4343 4344 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4345 crtc_state->master_transcoder = INVALID_TRANSCODER; 4346 crtc_state->sync_mode_slaves_mask = 4347 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4348 } 4349 4350 return 0; 4351 } 4352 4353 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4354 { 4355 struct drm_i915_private *i915 = to_i915(encoder->dev); 4356 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4357 4358 intel_dp_encoder_flush_work(encoder); 4359 if (intel_encoder_is_tc(&dig_port->base)) 4360 intel_tc_port_cleanup(dig_port); 4361 intel_display_power_flush_work(i915); 4362 4363 drm_encoder_cleanup(encoder); 4364 kfree(dig_port->hdcp_port_data.streams); 4365 kfree(dig_port); 4366 } 4367 4368 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4369 { 4370 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4371 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4372 4373 intel_dp->reset_link_params = true; 4374 4375 intel_pps_encoder_reset(intel_dp); 4376 4377 if (intel_encoder_is_tc(&dig_port->base)) 4378 intel_tc_port_init_mode(dig_port); 4379 } 4380 4381 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4382 { 4383 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4384 4385 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4386 4387 return 0; 4388 } 4389 4390 static const struct drm_encoder_funcs intel_ddi_funcs = { 4391 .reset = intel_ddi_encoder_reset, 4392 .destroy = intel_ddi_encoder_destroy, 4393 .late_register = intel_ddi_encoder_late_register, 4394 }; 4395 4396 static struct intel_connector * 4397 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4398 { 4399 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4400 struct intel_connector *connector; 4401 enum port port = dig_port->base.port; 4402 4403 connector = intel_connector_alloc(); 4404 if (!connector) 4405 return NULL; 4406 4407 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4408 if (DISPLAY_VER(i915) >= 14) 4409 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4410 else 4411 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4412 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4413 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4414 4415 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4416 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4417 4418 if (!intel_dp_init_connector(dig_port, connector)) { 4419 kfree(connector); 4420 return NULL; 4421 } 4422 4423 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4424 struct drm_device *dev = dig_port->base.base.dev; 4425 struct drm_privacy_screen *privacy_screen; 4426 4427 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4428 if (!IS_ERR(privacy_screen)) { 4429 drm_connector_attach_privacy_screen_provider(&connector->base, 4430 privacy_screen); 4431 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4432 drm_warn(dev, "Error getting privacy-screen\n"); 4433 } 4434 } 4435 4436 return connector; 4437 } 4438 4439 static int modeset_pipe(struct drm_crtc *crtc, 4440 struct drm_modeset_acquire_ctx *ctx) 4441 { 4442 struct drm_atomic_state *state; 4443 struct drm_crtc_state *crtc_state; 4444 int ret; 4445 4446 state = drm_atomic_state_alloc(crtc->dev); 4447 if (!state) 4448 return -ENOMEM; 4449 4450 state->acquire_ctx = ctx; 4451 to_intel_atomic_state(state)->internal = true; 4452 4453 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4454 if (IS_ERR(crtc_state)) { 4455 ret = PTR_ERR(crtc_state); 4456 goto out; 4457 } 4458 4459 crtc_state->connectors_changed = true; 4460 4461 ret = drm_atomic_commit(state); 4462 out: 4463 drm_atomic_state_put(state); 4464 4465 return ret; 4466 } 4467 4468 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4469 struct drm_modeset_acquire_ctx *ctx) 4470 { 4471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4472 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4473 struct intel_connector *connector = hdmi->attached_connector; 4474 struct i2c_adapter *ddc = connector->base.ddc; 4475 struct drm_connector_state *conn_state; 4476 struct intel_crtc_state *crtc_state; 4477 struct intel_crtc *crtc; 4478 u8 config; 4479 int ret; 4480 4481 if (connector->base.status != connector_status_connected) 4482 return 0; 4483 4484 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4485 ctx); 4486 if (ret) 4487 return ret; 4488 4489 conn_state = connector->base.state; 4490 4491 crtc = to_intel_crtc(conn_state->crtc); 4492 if (!crtc) 4493 return 0; 4494 4495 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4496 if (ret) 4497 return ret; 4498 4499 crtc_state = to_intel_crtc_state(crtc->base.state); 4500 4501 drm_WARN_ON(&dev_priv->drm, 4502 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4503 4504 if (!crtc_state->hw.active) 4505 return 0; 4506 4507 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4508 !crtc_state->hdmi_scrambling) 4509 return 0; 4510 4511 if (conn_state->commit && 4512 !try_wait_for_completion(&conn_state->commit->hw_done)) 4513 return 0; 4514 4515 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4516 if (ret < 0) { 4517 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4518 connector->base.base.id, connector->base.name, ret); 4519 return 0; 4520 } 4521 4522 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4523 crtc_state->hdmi_high_tmds_clock_ratio && 4524 !!(config & SCDC_SCRAMBLING_ENABLE) == 4525 crtc_state->hdmi_scrambling) 4526 return 0; 4527 4528 /* 4529 * HDMI 2.0 says that one should not send scrambled data 4530 * prior to configuring the sink scrambling, and that 4531 * TMDS clock/data transmission should be suspended when 4532 * changing the TMDS clock rate in the sink. So let's 4533 * just do a full modeset here, even though some sinks 4534 * would be perfectly happy if were to just reconfigure 4535 * the SCDC settings on the fly. 4536 */ 4537 return modeset_pipe(&crtc->base, ctx); 4538 } 4539 4540 static enum intel_hotplug_state 4541 intel_ddi_hotplug(struct intel_encoder *encoder, 4542 struct intel_connector *connector) 4543 { 4544 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4545 struct intel_dp *intel_dp = &dig_port->dp; 4546 bool is_tc = intel_encoder_is_tc(encoder); 4547 struct drm_modeset_acquire_ctx ctx; 4548 enum intel_hotplug_state state; 4549 int ret; 4550 4551 if (intel_dp->compliance.test_active && 4552 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4553 intel_dp_phy_test(encoder); 4554 /* just do the PHY test and nothing else */ 4555 return INTEL_HOTPLUG_UNCHANGED; 4556 } 4557 4558 state = intel_encoder_hotplug(encoder, connector); 4559 4560 if (!intel_tc_port_link_reset(dig_port)) { 4561 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4562 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4563 ret = intel_hdmi_reset_link(encoder, &ctx); 4564 else 4565 ret = intel_dp_retrain_link(encoder, &ctx); 4566 } 4567 4568 drm_WARN_ON(encoder->base.dev, ret); 4569 } 4570 4571 /* 4572 * Unpowered type-c dongles can take some time to boot and be 4573 * responsible, so here giving some time to those dongles to power up 4574 * and then retrying the probe. 4575 * 4576 * On many platforms the HDMI live state signal is known to be 4577 * unreliable, so we can't use it to detect if a sink is connected or 4578 * not. Instead we detect if it's connected based on whether we can 4579 * read the EDID or not. That in turn has a problem during disconnect, 4580 * since the HPD interrupt may be raised before the DDC lines get 4581 * disconnected (due to how the required length of DDC vs. HPD 4582 * connector pins are specified) and so we'll still be able to get a 4583 * valid EDID. To solve this schedule another detection cycle if this 4584 * time around we didn't detect any change in the sink's connection 4585 * status. 4586 * 4587 * Type-c connectors which get their HPD signal deasserted then 4588 * reasserted, without unplugging/replugging the sink from the 4589 * connector, introduce a delay until the AUX channel communication 4590 * becomes functional. Retry the detection for 5 seconds on type-c 4591 * connectors to account for this delay. 4592 */ 4593 if (state == INTEL_HOTPLUG_UNCHANGED && 4594 connector->hotplug_retries < (is_tc ? 5 : 1) && 4595 !dig_port->dp.is_mst) 4596 state = INTEL_HOTPLUG_RETRY; 4597 4598 return state; 4599 } 4600 4601 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4602 { 4603 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4604 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4605 4606 return intel_de_read(dev_priv, SDEISR) & bit; 4607 } 4608 4609 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4610 { 4611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4612 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4613 4614 return intel_de_read(dev_priv, DEISR) & bit; 4615 } 4616 4617 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4618 { 4619 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4620 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4621 4622 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4623 } 4624 4625 static struct intel_connector * 4626 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4627 { 4628 struct intel_connector *connector; 4629 enum port port = dig_port->base.port; 4630 4631 connector = intel_connector_alloc(); 4632 if (!connector) 4633 return NULL; 4634 4635 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4636 intel_hdmi_init_connector(dig_port, connector); 4637 4638 return connector; 4639 } 4640 4641 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4642 { 4643 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4644 4645 if (dig_port->base.port != PORT_A) 4646 return false; 4647 4648 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4649 return false; 4650 4651 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4652 * supported configuration 4653 */ 4654 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4655 return true; 4656 4657 return false; 4658 } 4659 4660 static int 4661 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4662 { 4663 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4664 enum port port = dig_port->base.port; 4665 int max_lanes = 4; 4666 4667 if (DISPLAY_VER(dev_priv) >= 11) 4668 return max_lanes; 4669 4670 if (port == PORT_A || port == PORT_E) { 4671 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4672 max_lanes = port == PORT_A ? 4 : 0; 4673 else 4674 /* Both A and E share 2 lanes */ 4675 max_lanes = 2; 4676 } 4677 4678 /* 4679 * Some BIOS might fail to set this bit on port A if eDP 4680 * wasn't lit up at boot. Force this bit set when needed 4681 * so we use the proper lane count for our calculations. 4682 */ 4683 if (intel_ddi_a_force_4_lanes(dig_port)) { 4684 drm_dbg_kms(&dev_priv->drm, 4685 "Forcing DDI_A_4_LANES for port A\n"); 4686 dig_port->saved_port_bits |= DDI_A_4_LANES; 4687 max_lanes = 4; 4688 } 4689 4690 return max_lanes; 4691 } 4692 4693 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4694 enum port port) 4695 { 4696 if (port >= PORT_D_XELPD) 4697 return HPD_PORT_D + port - PORT_D_XELPD; 4698 else if (port >= PORT_TC1) 4699 return HPD_PORT_TC1 + port - PORT_TC1; 4700 else 4701 return HPD_PORT_A + port - PORT_A; 4702 } 4703 4704 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4705 enum port port) 4706 { 4707 if (port >= PORT_TC1) 4708 return HPD_PORT_C + port - PORT_TC1; 4709 else 4710 return HPD_PORT_A + port - PORT_A; 4711 } 4712 4713 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4714 enum port port) 4715 { 4716 if (port >= PORT_TC1) 4717 return HPD_PORT_TC1 + port - PORT_TC1; 4718 else 4719 return HPD_PORT_A + port - PORT_A; 4720 } 4721 4722 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4723 enum port port) 4724 { 4725 if (HAS_PCH_TGP(dev_priv)) 4726 return tgl_hpd_pin(dev_priv, port); 4727 4728 if (port >= PORT_TC1) 4729 return HPD_PORT_C + port - PORT_TC1; 4730 else 4731 return HPD_PORT_A + port - PORT_A; 4732 } 4733 4734 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4735 enum port port) 4736 { 4737 if (port >= PORT_C) 4738 return HPD_PORT_TC1 + port - PORT_C; 4739 else 4740 return HPD_PORT_A + port - PORT_A; 4741 } 4742 4743 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4744 enum port port) 4745 { 4746 if (port == PORT_D) 4747 return HPD_PORT_A; 4748 4749 if (HAS_PCH_TGP(dev_priv)) 4750 return icl_hpd_pin(dev_priv, port); 4751 4752 return HPD_PORT_A + port - PORT_A; 4753 } 4754 4755 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4756 { 4757 if (HAS_PCH_TGP(dev_priv)) 4758 return icl_hpd_pin(dev_priv, port); 4759 4760 return HPD_PORT_A + port - PORT_A; 4761 } 4762 4763 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4764 { 4765 if (DISPLAY_VER(i915) >= 12) 4766 return port >= PORT_TC1; 4767 else if (DISPLAY_VER(i915) >= 11) 4768 return port >= PORT_C; 4769 else 4770 return false; 4771 } 4772 4773 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4774 { 4775 intel_dp_encoder_suspend(encoder); 4776 } 4777 4778 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4779 { 4780 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4781 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4782 4783 intel_tc_port_suspend(dig_port); 4784 } 4785 4786 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4787 { 4788 intel_dp_encoder_shutdown(encoder); 4789 intel_hdmi_encoder_shutdown(encoder); 4790 } 4791 4792 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4793 { 4794 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4795 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4796 4797 intel_tc_port_cleanup(dig_port); 4798 } 4799 4800 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4801 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4802 4803 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4804 { 4805 /* straps not used on skl+ */ 4806 if (DISPLAY_VER(i915) >= 9) 4807 return true; 4808 4809 switch (port) { 4810 case PORT_A: 4811 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4812 case PORT_B: 4813 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4814 case PORT_C: 4815 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4816 case PORT_D: 4817 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4818 case PORT_E: 4819 return true; /* no strap for DDI-E */ 4820 default: 4821 MISSING_CASE(port); 4822 return false; 4823 } 4824 } 4825 4826 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4827 { 4828 return init_dp || intel_encoder_is_tc(encoder); 4829 } 4830 4831 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4832 { 4833 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4834 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4835 "Platform does not support DSI\n"); 4836 } 4837 4838 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4839 { 4840 struct intel_encoder *encoder; 4841 4842 for_each_intel_encoder(&i915->drm, encoder) { 4843 /* FIXME what about second port for dual link DSI? */ 4844 if (encoder->port == port) 4845 return true; 4846 } 4847 4848 return false; 4849 } 4850 4851 void intel_ddi_init(struct drm_i915_private *dev_priv, 4852 const struct intel_bios_encoder_data *devdata) 4853 { 4854 struct intel_digital_port *dig_port; 4855 struct intel_encoder *encoder; 4856 bool init_hdmi, init_dp; 4857 enum port port; 4858 enum phy phy; 4859 4860 port = intel_bios_encoder_port(devdata); 4861 if (port == PORT_NONE) 4862 return; 4863 4864 if (!port_strap_detected(dev_priv, port)) { 4865 drm_dbg_kms(&dev_priv->drm, 4866 "Port %c strap not detected\n", port_name(port)); 4867 return; 4868 } 4869 4870 if (!assert_port_valid(dev_priv, port)) 4871 return; 4872 4873 if (port_in_use(dev_priv, port)) { 4874 drm_dbg_kms(&dev_priv->drm, 4875 "Port %c already claimed\n", port_name(port)); 4876 return; 4877 } 4878 4879 if (intel_bios_encoder_supports_dsi(devdata)) { 4880 /* BXT/GLK handled elsewhere, for now at least */ 4881 if (!assert_has_icl_dsi(dev_priv)) 4882 return; 4883 4884 icl_dsi_init(dev_priv, devdata); 4885 return; 4886 } 4887 4888 phy = intel_port_to_phy(dev_priv, port); 4889 4890 /* 4891 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4892 * have taken over some of the PHYs and made them unavailable to the 4893 * driver. In that case we should skip initializing the corresponding 4894 * outputs. 4895 */ 4896 if (intel_hti_uses_phy(dev_priv, phy)) { 4897 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4898 port_name(port), phy_name(phy)); 4899 return; 4900 } 4901 4902 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4903 intel_bios_encoder_supports_hdmi(devdata); 4904 init_dp = intel_bios_encoder_supports_dp(devdata); 4905 4906 if (intel_bios_encoder_is_lspcon(devdata)) { 4907 /* 4908 * Lspcon device needs to be driven with DP connector 4909 * with special detection sequence. So make sure DP 4910 * is initialized before lspcon. 4911 */ 4912 init_dp = true; 4913 init_hdmi = false; 4914 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4915 port_name(port)); 4916 } 4917 4918 if (!init_dp && !init_hdmi) { 4919 drm_dbg_kms(&dev_priv->drm, 4920 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4921 port_name(port)); 4922 return; 4923 } 4924 4925 if (intel_phy_is_snps(dev_priv, phy) && 4926 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4927 drm_dbg_kms(&dev_priv->drm, 4928 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4929 phy_name(phy)); 4930 } 4931 4932 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4933 if (!dig_port) 4934 return; 4935 4936 dig_port->aux_ch = AUX_CH_NONE; 4937 4938 encoder = &dig_port->base; 4939 encoder->devdata = devdata; 4940 4941 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4942 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4943 DRM_MODE_ENCODER_TMDS, 4944 "DDI %c/PHY %c", 4945 port_name(port - PORT_D_XELPD + PORT_D), 4946 phy_name(phy)); 4947 } else if (DISPLAY_VER(dev_priv) >= 12) { 4948 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4949 4950 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4951 DRM_MODE_ENCODER_TMDS, 4952 "DDI %s%c/PHY %s%c", 4953 port >= PORT_TC1 ? "TC" : "", 4954 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4955 tc_port != TC_PORT_NONE ? "TC" : "", 4956 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4957 } else if (DISPLAY_VER(dev_priv) >= 11) { 4958 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4959 4960 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4961 DRM_MODE_ENCODER_TMDS, 4962 "DDI %c%s/PHY %s%c", 4963 port_name(port), 4964 port >= PORT_C ? " (TC)" : "", 4965 tc_port != TC_PORT_NONE ? "TC" : "", 4966 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4967 } else { 4968 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4969 DRM_MODE_ENCODER_TMDS, 4970 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4971 } 4972 4973 mutex_init(&dig_port->hdcp_mutex); 4974 dig_port->num_hdcp_streams = 0; 4975 4976 encoder->hotplug = intel_ddi_hotplug; 4977 encoder->compute_output_type = intel_ddi_compute_output_type; 4978 encoder->compute_config = intel_ddi_compute_config; 4979 encoder->compute_config_late = intel_ddi_compute_config_late; 4980 encoder->enable = intel_enable_ddi; 4981 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4982 encoder->pre_enable = intel_ddi_pre_enable; 4983 encoder->disable = intel_disable_ddi; 4984 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4985 encoder->post_disable = intel_ddi_post_disable; 4986 encoder->update_pipe = intel_ddi_update_pipe; 4987 encoder->audio_enable = intel_audio_codec_enable; 4988 encoder->audio_disable = intel_audio_codec_disable; 4989 encoder->get_hw_state = intel_ddi_get_hw_state; 4990 encoder->sync_state = intel_ddi_sync_state; 4991 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4992 encoder->suspend = intel_ddi_encoder_suspend; 4993 encoder->shutdown = intel_ddi_encoder_shutdown; 4994 encoder->get_power_domains = intel_ddi_get_power_domains; 4995 4996 encoder->type = INTEL_OUTPUT_DDI; 4997 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4998 encoder->port = port; 4999 encoder->cloneable = 0; 5000 encoder->pipe_mask = ~0; 5001 5002 if (DISPLAY_VER(dev_priv) >= 14) { 5003 encoder->enable_clock = intel_mtl_pll_enable; 5004 encoder->disable_clock = intel_mtl_pll_disable; 5005 encoder->port_pll_type = intel_mtl_port_pll_type; 5006 encoder->get_config = mtl_ddi_get_config; 5007 } else if (IS_DG2(dev_priv)) { 5008 encoder->enable_clock = intel_mpllb_enable; 5009 encoder->disable_clock = intel_mpllb_disable; 5010 encoder->get_config = dg2_ddi_get_config; 5011 } else if (IS_ALDERLAKE_S(dev_priv)) { 5012 encoder->enable_clock = adls_ddi_enable_clock; 5013 encoder->disable_clock = adls_ddi_disable_clock; 5014 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5015 encoder->get_config = adls_ddi_get_config; 5016 } else if (IS_ROCKETLAKE(dev_priv)) { 5017 encoder->enable_clock = rkl_ddi_enable_clock; 5018 encoder->disable_clock = rkl_ddi_disable_clock; 5019 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5020 encoder->get_config = rkl_ddi_get_config; 5021 } else if (IS_DG1(dev_priv)) { 5022 encoder->enable_clock = dg1_ddi_enable_clock; 5023 encoder->disable_clock = dg1_ddi_disable_clock; 5024 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5025 encoder->get_config = dg1_ddi_get_config; 5026 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5027 if (intel_ddi_is_tc(dev_priv, port)) { 5028 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5029 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5030 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5031 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5032 encoder->get_config = icl_ddi_combo_get_config; 5033 } else { 5034 encoder->enable_clock = icl_ddi_combo_enable_clock; 5035 encoder->disable_clock = icl_ddi_combo_disable_clock; 5036 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5037 encoder->get_config = icl_ddi_combo_get_config; 5038 } 5039 } else if (DISPLAY_VER(dev_priv) >= 11) { 5040 if (intel_ddi_is_tc(dev_priv, port)) { 5041 encoder->enable_clock = icl_ddi_tc_enable_clock; 5042 encoder->disable_clock = icl_ddi_tc_disable_clock; 5043 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5044 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5045 encoder->get_config = icl_ddi_tc_get_config; 5046 } else { 5047 encoder->enable_clock = icl_ddi_combo_enable_clock; 5048 encoder->disable_clock = icl_ddi_combo_disable_clock; 5049 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5050 encoder->get_config = icl_ddi_combo_get_config; 5051 } 5052 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5053 /* BXT/GLK have fixed PLL->port mapping */ 5054 encoder->get_config = bxt_ddi_get_config; 5055 } else if (DISPLAY_VER(dev_priv) == 9) { 5056 encoder->enable_clock = skl_ddi_enable_clock; 5057 encoder->disable_clock = skl_ddi_disable_clock; 5058 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5059 encoder->get_config = skl_ddi_get_config; 5060 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5061 encoder->enable_clock = hsw_ddi_enable_clock; 5062 encoder->disable_clock = hsw_ddi_disable_clock; 5063 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5064 encoder->get_config = hsw_ddi_get_config; 5065 } 5066 5067 if (DISPLAY_VER(dev_priv) >= 14) { 5068 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5069 } else if (IS_DG2(dev_priv)) { 5070 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5071 } else if (DISPLAY_VER(dev_priv) >= 12) { 5072 if (intel_encoder_is_combo(encoder)) 5073 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5074 else 5075 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5076 } else if (DISPLAY_VER(dev_priv) >= 11) { 5077 if (intel_encoder_is_combo(encoder)) 5078 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5079 else 5080 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5081 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5082 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 5083 } else { 5084 encoder->set_signal_levels = hsw_set_signal_levels; 5085 } 5086 5087 intel_ddi_buf_trans_init(encoder); 5088 5089 if (DISPLAY_VER(dev_priv) >= 13) 5090 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5091 else if (IS_DG1(dev_priv)) 5092 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5093 else if (IS_ROCKETLAKE(dev_priv)) 5094 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5095 else if (DISPLAY_VER(dev_priv) >= 12) 5096 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5097 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5098 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5099 else if (DISPLAY_VER(dev_priv) == 11) 5100 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5101 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5102 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5103 else 5104 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5105 5106 if (DISPLAY_VER(dev_priv) >= 11) 5107 dig_port->saved_port_bits = 5108 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5109 & DDI_BUF_PORT_REVERSAL; 5110 else 5111 dig_port->saved_port_bits = 5112 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5113 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5114 5115 if (intel_bios_encoder_lane_reversal(devdata)) 5116 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5117 5118 dig_port->dp.output_reg = INVALID_MMIO_REG; 5119 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5120 5121 if (need_aux_ch(encoder, init_dp)) { 5122 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5123 if (dig_port->aux_ch == AUX_CH_NONE) 5124 goto err; 5125 } 5126 5127 if (intel_encoder_is_tc(encoder)) { 5128 bool is_legacy = 5129 !intel_bios_encoder_supports_typec_usb(devdata) && 5130 !intel_bios_encoder_supports_tbt(devdata); 5131 5132 if (!is_legacy && init_hdmi) { 5133 is_legacy = !init_dp; 5134 5135 drm_dbg_kms(&dev_priv->drm, 5136 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5137 port_name(port), 5138 str_yes_no(init_dp), 5139 is_legacy ? "legacy" : "non-legacy"); 5140 } 5141 5142 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5143 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5144 5145 dig_port->lock = intel_tc_port_lock; 5146 dig_port->unlock = intel_tc_port_unlock; 5147 5148 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5149 goto err; 5150 } 5151 5152 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5153 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5154 5155 if (DISPLAY_VER(dev_priv) >= 11) { 5156 if (intel_encoder_is_tc(encoder)) 5157 dig_port->connected = intel_tc_port_connected; 5158 else 5159 dig_port->connected = lpt_digital_port_connected; 5160 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5161 dig_port->connected = bdw_digital_port_connected; 5162 } else if (DISPLAY_VER(dev_priv) == 9) { 5163 dig_port->connected = lpt_digital_port_connected; 5164 } else if (IS_BROADWELL(dev_priv)) { 5165 if (port == PORT_A) 5166 dig_port->connected = bdw_digital_port_connected; 5167 else 5168 dig_port->connected = lpt_digital_port_connected; 5169 } else if (IS_HASWELL(dev_priv)) { 5170 if (port == PORT_A) 5171 dig_port->connected = hsw_digital_port_connected; 5172 else 5173 dig_port->connected = lpt_digital_port_connected; 5174 } 5175 5176 intel_infoframe_init(dig_port); 5177 5178 if (init_dp) { 5179 if (!intel_ddi_init_dp_connector(dig_port)) 5180 goto err; 5181 5182 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5183 5184 if (dig_port->dp.mso_link_count) 5185 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5186 } 5187 5188 /* 5189 * In theory we don't need the encoder->type check, 5190 * but leave it just in case we have some really bad VBTs... 5191 */ 5192 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5193 if (!intel_ddi_init_hdmi_connector(dig_port)) 5194 goto err; 5195 } 5196 5197 return; 5198 5199 err: 5200 drm_encoder_cleanup(&encoder->base); 5201 kfree(dig_port); 5202 } 5203