1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_privacy_screen_consumer.h> 35 36 #include "i915_reg.h" 37 #include "i915_utils.h" 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_dkl_phy.h" 56 #include "intel_dkl_phy_regs.h" 57 #include "intel_dp.h" 58 #include "intel_dp_aux.h" 59 #include "intel_dp_link_training.h" 60 #include "intel_dp_mst.h" 61 #include "intel_dp_test.h" 62 #include "intel_dp_tunnel.h" 63 #include "intel_dpio_phy.h" 64 #include "intel_dsi.h" 65 #include "intel_encoder.h" 66 #include "intel_fdi.h" 67 #include "intel_fifo_underrun.h" 68 #include "intel_gmbus.h" 69 #include "intel_hdcp.h" 70 #include "intel_hdmi.h" 71 #include "intel_hotplug.h" 72 #include "intel_hti.h" 73 #include "intel_lspcon.h" 74 #include "intel_mg_phy_regs.h" 75 #include "intel_modeset_lock.h" 76 #include "intel_panel.h" 77 #include "intel_pfit.h" 78 #include "intel_pps.h" 79 #include "intel_psr.h" 80 #include "intel_quirks.h" 81 #include "intel_snps_phy.h" 82 #include "intel_step.h" 83 #include "intel_tc.h" 84 #include "intel_vdsc.h" 85 #include "intel_vdsc_regs.h" 86 #include "intel_vrr.h" 87 #include "skl_scaler.h" 88 #include "skl_universal_plane.h" 89 90 static const u8 index_to_dp_signal_levels[] = { 91 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 94 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 95 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 98 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 99 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 100 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 101 }; 102 103 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 104 const struct intel_ddi_buf_trans *trans) 105 { 106 int level; 107 108 level = intel_bios_hdmi_level_shift(encoder->devdata); 109 if (level < 0) 110 level = trans->hdmi_default_entry; 111 112 return level; 113 } 114 115 static bool has_buf_trans_select(struct intel_display *display) 116 { 117 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 118 } 119 120 static bool has_iboost(struct intel_display *display) 121 { 122 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 123 } 124 125 /* 126 * Starting with Haswell, DDI port buffers must be programmed with correct 127 * values in advance. This function programs the correct values for 128 * DP/eDP/FDI use cases. 129 */ 130 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 131 const struct intel_crtc_state *crtc_state) 132 { 133 struct intel_display *display = to_intel_display(encoder); 134 u32 iboost_bit = 0; 135 int i, n_entries; 136 enum port port = encoder->port; 137 const struct intel_ddi_buf_trans *trans; 138 139 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 140 if (drm_WARN_ON_ONCE(display->drm, !trans)) 141 return; 142 143 /* If we're boosting the current, set bit 31 of trans1 */ 144 if (has_iboost(display) && 145 intel_bios_dp_boost_level(encoder->devdata)) 146 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 147 148 for (i = 0; i < n_entries; i++) { 149 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 150 trans->entries[i].hsw.trans1 | iboost_bit); 151 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 152 trans->entries[i].hsw.trans2); 153 } 154 } 155 156 /* 157 * Starting with Haswell, DDI port buffers must be programmed with correct 158 * values in advance. This function programs the correct values for 159 * HDMI/DVI use cases. 160 */ 161 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 162 const struct intel_crtc_state *crtc_state) 163 { 164 struct intel_display *display = to_intel_display(encoder); 165 int level = intel_ddi_level(encoder, crtc_state, 0); 166 u32 iboost_bit = 0; 167 int n_entries; 168 enum port port = encoder->port; 169 const struct intel_ddi_buf_trans *trans; 170 171 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 172 if (drm_WARN_ON_ONCE(display->drm, !trans)) 173 return; 174 175 /* If we're boosting the current, set bit 31 of trans1 */ 176 if (has_iboost(display) && 177 intel_bios_hdmi_boost_level(encoder->devdata)) 178 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 179 180 /* Entry 9 is for HDMI: */ 181 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 182 trans->entries[level].hsw.trans1 | iboost_bit); 183 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 184 trans->entries[level].hsw.trans2); 185 } 186 187 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 188 { 189 if (DISPLAY_VER(display) >= 14) 190 return XELPDP_PORT_BUF_CTL1(display, port); 191 else 192 return DDI_BUF_CTL(port); 193 } 194 195 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 196 { 197 /* 198 * Bspec's platform specific timeouts: 199 * MTL+ : 100 us 200 * BXT : fixed 16 us 201 * HSW-ADL: 8 us 202 * 203 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 204 */ 205 if (display->platform.broxton) { 206 udelay(16); 207 return; 208 } 209 210 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 211 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 212 DDI_BUF_IS_IDLE, 10)) 213 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 214 port_name(port)); 215 } 216 217 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 218 { 219 struct intel_display *display = to_intel_display(encoder); 220 enum port port = encoder->port; 221 222 /* 223 * Bspec's platform specific timeouts: 224 * MTL+ : 10000 us 225 * DG2 : 1200 us 226 * TGL-ADL combo PHY: 1000 us 227 * TGL-ADL TypeC PHY: 3000 us 228 * HSW-ICL : fixed 518 us 229 */ 230 if (DISPLAY_VER(display) < 10) { 231 usleep_range(518, 1000); 232 return; 233 } 234 235 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 236 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 237 DDI_BUF_IS_IDLE, 10)) 238 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 239 port_name(port)); 240 } 241 242 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 243 { 244 switch (pll->info->id) { 245 case DPLL_ID_WRPLL1: 246 return PORT_CLK_SEL_WRPLL1; 247 case DPLL_ID_WRPLL2: 248 return PORT_CLK_SEL_WRPLL2; 249 case DPLL_ID_SPLL: 250 return PORT_CLK_SEL_SPLL; 251 case DPLL_ID_LCPLL_810: 252 return PORT_CLK_SEL_LCPLL_810; 253 case DPLL_ID_LCPLL_1350: 254 return PORT_CLK_SEL_LCPLL_1350; 255 case DPLL_ID_LCPLL_2700: 256 return PORT_CLK_SEL_LCPLL_2700; 257 default: 258 MISSING_CASE(pll->info->id); 259 return PORT_CLK_SEL_NONE; 260 } 261 } 262 263 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 264 const struct intel_crtc_state *crtc_state) 265 { 266 const struct intel_dpll *pll = crtc_state->intel_dpll; 267 int clock = crtc_state->port_clock; 268 const enum intel_dpll_id id = pll->info->id; 269 270 switch (id) { 271 default: 272 /* 273 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 274 * here, so do warn if this get passed in 275 */ 276 MISSING_CASE(id); 277 return DDI_CLK_SEL_NONE; 278 case DPLL_ID_ICL_TBTPLL: 279 switch (clock) { 280 case 162000: 281 return DDI_CLK_SEL_TBT_162; 282 case 270000: 283 return DDI_CLK_SEL_TBT_270; 284 case 540000: 285 return DDI_CLK_SEL_TBT_540; 286 case 810000: 287 return DDI_CLK_SEL_TBT_810; 288 default: 289 MISSING_CASE(clock); 290 return DDI_CLK_SEL_NONE; 291 } 292 case DPLL_ID_ICL_MGPLL1: 293 case DPLL_ID_ICL_MGPLL2: 294 case DPLL_ID_ICL_MGPLL3: 295 case DPLL_ID_ICL_MGPLL4: 296 case DPLL_ID_TGL_MGPLL5: 297 case DPLL_ID_TGL_MGPLL6: 298 return DDI_CLK_SEL_MG; 299 } 300 } 301 302 static u32 ddi_buf_phy_link_rate(int port_clock) 303 { 304 switch (port_clock) { 305 case 162000: 306 return DDI_BUF_PHY_LINK_RATE(0); 307 case 216000: 308 return DDI_BUF_PHY_LINK_RATE(4); 309 case 243000: 310 return DDI_BUF_PHY_LINK_RATE(5); 311 case 270000: 312 return DDI_BUF_PHY_LINK_RATE(1); 313 case 324000: 314 return DDI_BUF_PHY_LINK_RATE(6); 315 case 432000: 316 return DDI_BUF_PHY_LINK_RATE(7); 317 case 540000: 318 return DDI_BUF_PHY_LINK_RATE(2); 319 case 810000: 320 return DDI_BUF_PHY_LINK_RATE(3); 321 default: 322 MISSING_CASE(port_clock); 323 return DDI_BUF_PHY_LINK_RATE(0); 324 } 325 } 326 327 static int dp_phy_lane_stagger_delay(int port_clock) 328 { 329 /* 330 * Return the number of symbol clocks delay used to stagger the 331 * assertion/desassertion of the port lane enables. The target delay 332 * time is 100 ns or greater, return the number of symbols specific to 333 * the provided port_clock (aka link clock) corresponding to this delay 334 * time, i.e. so that 335 * 336 * number_of_symbols * duration_of_one_symbol >= 100 ns 337 * 338 * The delay must be applied only on TypeC DP outputs, for everything else 339 * the delay must be set to 0. 340 * 341 * Return the number of link symbols per 100 ns: 342 * port_clock (10 kHz) -> bits / 100 us 343 * / symbol_size -> symbols / 100 us 344 * / 1000 -> symbols / 100 ns 345 */ 346 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 347 } 348 349 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 350 const struct intel_crtc_state *crtc_state) 351 { 352 struct intel_display *display = to_intel_display(encoder); 353 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 354 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 355 356 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 357 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 358 DDI_BUF_TRANS_SELECT(0); 359 360 if (dig_port->lane_reversal) 361 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 362 if (dig_port->ddi_a_4_lanes) 363 intel_dp->DP |= DDI_A_4_LANES; 364 365 if (DISPLAY_VER(display) >= 14) { 366 if (intel_dp_is_uhbr(crtc_state)) 367 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 368 else 369 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 370 } 371 372 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 373 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 374 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 375 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 376 } 377 378 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 379 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 380 381 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 382 } 383 } 384 385 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 386 { 387 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 388 389 switch (val) { 390 case DDI_CLK_SEL_NONE: 391 return 0; 392 case DDI_CLK_SEL_TBT_162: 393 return 162000; 394 case DDI_CLK_SEL_TBT_270: 395 return 270000; 396 case DDI_CLK_SEL_TBT_540: 397 return 540000; 398 case DDI_CLK_SEL_TBT_810: 399 return 810000; 400 default: 401 MISSING_CASE(val); 402 return 0; 403 } 404 } 405 406 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 407 { 408 /* CRT dotclock is determined via other means */ 409 if (pipe_config->has_pch_encoder) 410 return; 411 412 pipe_config->hw.adjusted_mode.crtc_clock = 413 intel_crtc_dotclock(pipe_config); 414 } 415 416 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 417 const struct drm_connector_state *conn_state) 418 { 419 struct intel_display *display = to_intel_display(crtc_state); 420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 421 u32 temp; 422 423 if (!intel_crtc_has_dp_encoder(crtc_state)) 424 return; 425 426 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 427 428 temp = DP_MSA_MISC_SYNC_CLOCK; 429 430 switch (crtc_state->pipe_bpp) { 431 case 18: 432 temp |= DP_MSA_MISC_6_BPC; 433 break; 434 case 24: 435 temp |= DP_MSA_MISC_8_BPC; 436 break; 437 case 30: 438 temp |= DP_MSA_MISC_10_BPC; 439 break; 440 case 36: 441 temp |= DP_MSA_MISC_12_BPC; 442 break; 443 default: 444 MISSING_CASE(crtc_state->pipe_bpp); 445 break; 446 } 447 448 /* nonsense combination */ 449 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 450 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 451 452 if (crtc_state->limited_color_range) 453 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 454 455 /* 456 * As per DP 1.2 spec section 2.3.4.3 while sending 457 * YCBCR 444 signals we should program MSA MISC1/0 fields with 458 * colorspace information. 459 */ 460 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 461 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 462 463 /* 464 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 465 * of Color Encoding Format and Content Color Gamut] while sending 466 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 467 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 468 */ 469 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 470 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 471 472 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 473 temp); 474 } 475 476 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 477 { 478 if (master_transcoder == TRANSCODER_EDP) 479 return 0; 480 else 481 return master_transcoder + 1; 482 } 483 484 static void 485 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 486 bool enable) 487 { 488 struct intel_display *display = to_intel_display(crtc_state); 489 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 490 u32 val = 0; 491 492 if (!HAS_DP20(display)) 493 return; 494 495 if (enable && intel_dp_is_uhbr(crtc_state)) 496 val = TRANS_DP2_128B132B_CHANNEL_CODING; 497 498 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 499 } 500 501 /* 502 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 503 * 504 * Only intended to be used by intel_ddi_enable_transcoder_func() and 505 * intel_ddi_config_transcoder_func(). 506 */ 507 static u32 508 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 509 const struct intel_crtc_state *crtc_state) 510 { 511 struct intel_display *display = to_intel_display(crtc_state); 512 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 513 enum pipe pipe = crtc->pipe; 514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 515 enum port port = encoder->port; 516 u32 temp; 517 518 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 519 temp = TRANS_DDI_FUNC_ENABLE; 520 if (DISPLAY_VER(display) >= 12) 521 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 522 else 523 temp |= TRANS_DDI_SELECT_PORT(port); 524 525 switch (crtc_state->pipe_bpp) { 526 default: 527 MISSING_CASE(crtc_state->pipe_bpp); 528 fallthrough; 529 case 18: 530 temp |= TRANS_DDI_BPC_6; 531 break; 532 case 24: 533 temp |= TRANS_DDI_BPC_8; 534 break; 535 case 30: 536 temp |= TRANS_DDI_BPC_10; 537 break; 538 case 36: 539 temp |= TRANS_DDI_BPC_12; 540 break; 541 } 542 543 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 544 temp |= TRANS_DDI_PVSYNC; 545 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 546 temp |= TRANS_DDI_PHSYNC; 547 548 if (cpu_transcoder == TRANSCODER_EDP) { 549 switch (pipe) { 550 default: 551 MISSING_CASE(pipe); 552 fallthrough; 553 case PIPE_A: 554 /* On Haswell, can only use the always-on power well for 555 * eDP when not using the panel fitter, and when not 556 * using motion blur mitigation (which we don't 557 * support). */ 558 if (crtc_state->pch_pfit.force_thru) 559 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 560 else 561 temp |= TRANS_DDI_EDP_INPUT_A_ON; 562 break; 563 case PIPE_B: 564 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 565 break; 566 case PIPE_C: 567 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 568 break; 569 } 570 } 571 572 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 573 if (crtc_state->has_hdmi_sink) 574 temp |= TRANS_DDI_MODE_SELECT_HDMI; 575 else 576 temp |= TRANS_DDI_MODE_SELECT_DVI; 577 578 if (crtc_state->hdmi_scrambling) 579 temp |= TRANS_DDI_HDMI_SCRAMBLING; 580 if (crtc_state->hdmi_high_tmds_clock_ratio) 581 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 582 if (DISPLAY_VER(display) >= 14) 583 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 584 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 585 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 586 temp |= (crtc_state->fdi_lanes - 1) << 1; 587 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 588 intel_dp_is_uhbr(crtc_state)) { 589 if (intel_dp_is_uhbr(crtc_state)) 590 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 591 else 592 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 593 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 594 595 if (DISPLAY_VER(display) >= 12) { 596 enum transcoder master; 597 598 master = crtc_state->mst_master_transcoder; 599 drm_WARN_ON(display->drm, 600 master == INVALID_TRANSCODER); 601 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 602 } 603 } else { 604 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 605 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 606 } 607 608 if (IS_DISPLAY_VER(display, 8, 10) && 609 crtc_state->master_transcoder != INVALID_TRANSCODER) { 610 u8 master_select = 611 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 612 613 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 614 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 615 } 616 617 return temp; 618 } 619 620 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 621 const struct intel_crtc_state *crtc_state) 622 { 623 struct intel_display *display = to_intel_display(crtc_state); 624 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 625 626 if (DISPLAY_VER(display) >= 11) { 627 enum transcoder master_transcoder = crtc_state->master_transcoder; 628 u32 ctl2 = 0; 629 630 if (master_transcoder != INVALID_TRANSCODER) { 631 u8 master_select = 632 bdw_trans_port_sync_master_select(master_transcoder); 633 634 ctl2 |= PORT_SYNC_MODE_ENABLE | 635 PORT_SYNC_MODE_MASTER_SELECT(master_select); 636 } 637 638 intel_de_write(display, 639 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 640 ctl2); 641 } 642 643 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 644 intel_ddi_transcoder_func_reg_val_get(encoder, 645 crtc_state)); 646 } 647 648 /* 649 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 650 * bit for the DDI function and enables the DP2 configuration. Called for all 651 * transcoder types. 652 */ 653 void 654 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 655 const struct intel_crtc_state *crtc_state) 656 { 657 struct intel_display *display = to_intel_display(crtc_state); 658 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 659 u32 ctl; 660 661 intel_ddi_config_transcoder_dp2(crtc_state, true); 662 663 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 664 ctl &= ~TRANS_DDI_FUNC_ENABLE; 665 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 666 ctl); 667 } 668 669 /* 670 * Disable the DDI function and port syncing. 671 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 672 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 673 * transcoders these are done later in intel_ddi_post_disable_dp(). 674 */ 675 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 676 { 677 struct intel_display *display = to_intel_display(crtc_state); 678 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 679 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 680 u32 ctl; 681 682 if (DISPLAY_VER(display) >= 11) 683 intel_de_write(display, 684 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 685 0); 686 687 ctl = intel_de_read(display, 688 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 689 690 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 691 692 ctl &= ~TRANS_DDI_FUNC_ENABLE; 693 694 if (IS_DISPLAY_VER(display, 8, 10)) 695 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 696 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 697 698 if (DISPLAY_VER(display) >= 12) { 699 if (!intel_dp_mst_is_master_trans(crtc_state)) { 700 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 701 TRANS_DDI_MODE_SELECT_MASK); 702 } 703 } else { 704 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 705 } 706 707 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 708 ctl); 709 710 if (intel_dp_mst_is_slave_trans(crtc_state)) 711 intel_ddi_config_transcoder_dp2(crtc_state, false); 712 713 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 714 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 715 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 716 /* Quirk time at 100ms for reliable operation */ 717 msleep(100); 718 } 719 } 720 721 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 722 enum transcoder cpu_transcoder, 723 bool enable, u32 hdcp_mask) 724 { 725 struct intel_display *display = to_intel_display(intel_encoder); 726 intel_wakeref_t wakeref; 727 int ret = 0; 728 729 wakeref = intel_display_power_get_if_enabled(display, 730 intel_encoder->power_domain); 731 if (drm_WARN_ON(display->drm, !wakeref)) 732 return -ENXIO; 733 734 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 735 hdcp_mask, enable ? hdcp_mask : 0); 736 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 737 return ret; 738 } 739 740 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 741 { 742 struct intel_display *display = to_intel_display(intel_connector); 743 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 744 int type = intel_connector->base.connector_type; 745 enum port port = encoder->port; 746 enum transcoder cpu_transcoder; 747 intel_wakeref_t wakeref; 748 enum pipe pipe = 0; 749 u32 ddi_mode; 750 bool ret; 751 752 wakeref = intel_display_power_get_if_enabled(display, 753 encoder->power_domain); 754 if (!wakeref) 755 return false; 756 757 /* Note: This returns false for DP MST primary encoders. */ 758 if (!encoder->get_hw_state(encoder, &pipe)) { 759 ret = false; 760 goto out; 761 } 762 763 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 764 cpu_transcoder = TRANSCODER_EDP; 765 else 766 cpu_transcoder = (enum transcoder) pipe; 767 768 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 769 TRANS_DDI_MODE_SELECT_MASK; 770 771 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 772 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 773 ret = type == DRM_MODE_CONNECTOR_HDMIA; 774 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 775 ret = type == DRM_MODE_CONNECTOR_VGA; 776 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 777 ret = type == DRM_MODE_CONNECTOR_eDP || 778 type == DRM_MODE_CONNECTOR_DisplayPort; 779 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 780 /* 781 * encoder->get_hw_state() should have bailed out on MST. This 782 * must be SST and non-eDP. 783 */ 784 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 785 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 786 /* encoder->get_hw_state() should have bailed out on MST. */ 787 ret = false; 788 } else { 789 ret = false; 790 } 791 792 out: 793 intel_display_power_put(display, encoder->power_domain, wakeref); 794 795 return ret; 796 } 797 798 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 799 u8 *pipe_mask, bool *is_dp_mst) 800 { 801 struct intel_display *display = to_intel_display(encoder); 802 enum port port = encoder->port; 803 intel_wakeref_t wakeref; 804 enum pipe p; 805 u32 tmp; 806 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 807 808 *pipe_mask = 0; 809 *is_dp_mst = false; 810 811 wakeref = intel_display_power_get_if_enabled(display, 812 encoder->power_domain); 813 if (!wakeref) 814 return; 815 816 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 817 if (!(tmp & DDI_BUF_CTL_ENABLE)) 818 goto out; 819 820 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 821 tmp = intel_de_read(display, 822 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 823 824 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 825 default: 826 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 827 fallthrough; 828 case TRANS_DDI_EDP_INPUT_A_ON: 829 case TRANS_DDI_EDP_INPUT_A_ONOFF: 830 *pipe_mask = BIT(PIPE_A); 831 break; 832 case TRANS_DDI_EDP_INPUT_B_ONOFF: 833 *pipe_mask = BIT(PIPE_B); 834 break; 835 case TRANS_DDI_EDP_INPUT_C_ONOFF: 836 *pipe_mask = BIT(PIPE_C); 837 break; 838 } 839 840 goto out; 841 } 842 843 for_each_pipe(display, p) { 844 enum transcoder cpu_transcoder = (enum transcoder)p; 845 u32 port_mask, ddi_select, ddi_mode; 846 intel_wakeref_t trans_wakeref; 847 848 trans_wakeref = intel_display_power_get_if_enabled(display, 849 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 850 if (!trans_wakeref) 851 continue; 852 853 if (DISPLAY_VER(display) >= 12) { 854 port_mask = TGL_TRANS_DDI_PORT_MASK; 855 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 856 } else { 857 port_mask = TRANS_DDI_PORT_MASK; 858 ddi_select = TRANS_DDI_SELECT_PORT(port); 859 } 860 861 tmp = intel_de_read(display, 862 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 863 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 864 trans_wakeref); 865 866 if ((tmp & port_mask) != ddi_select) 867 continue; 868 869 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 870 871 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 872 mst_pipe_mask |= BIT(p); 873 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 874 dp128b132b_pipe_mask |= BIT(p); 875 876 *pipe_mask |= BIT(p); 877 } 878 879 if (!*pipe_mask) 880 drm_dbg_kms(display->drm, 881 "No pipe for [ENCODER:%d:%s] found\n", 882 encoder->base.base.id, encoder->base.name); 883 884 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 885 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 886 887 /* 888 * If we don't have 8b/10b MST, but have more than one 889 * transcoder in 128b/132b mode, we know it must be 128b/132b 890 * MST. 891 * 892 * Otherwise, we fall back to checking the current MST 893 * state. It's not accurate for hardware takeover at probe, but 894 * we don't expect MST to have been enabled at that point, and 895 * can assume it's SST. 896 */ 897 if (hweight8(dp128b132b_pipe_mask) > 1 || 898 intel_dp_mst_active_streams(intel_dp)) 899 mst_pipe_mask = dp128b132b_pipe_mask; 900 } 901 902 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 903 drm_dbg_kms(display->drm, 904 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 905 encoder->base.base.id, encoder->base.name, 906 *pipe_mask); 907 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 908 } 909 910 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 911 drm_dbg_kms(display->drm, 912 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 913 encoder->base.base.id, encoder->base.name, 914 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 915 else 916 *is_dp_mst = mst_pipe_mask; 917 918 out: 919 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 920 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 921 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 922 BXT_PHY_LANE_POWERDOWN_ACK | 923 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 924 drm_err(display->drm, 925 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 926 encoder->base.base.id, encoder->base.name, tmp); 927 } 928 929 intel_display_power_put(display, encoder->power_domain, wakeref); 930 } 931 932 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 933 enum pipe *pipe) 934 { 935 u8 pipe_mask; 936 bool is_mst; 937 938 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 939 940 if (is_mst || !pipe_mask) 941 return false; 942 943 *pipe = ffs(pipe_mask) - 1; 944 945 return true; 946 } 947 948 static enum intel_display_power_domain 949 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 950 const struct intel_crtc_state *crtc_state) 951 { 952 struct intel_display *display = to_intel_display(dig_port); 953 954 /* 955 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 956 * DC states enabled at the same time, while for driver initiated AUX 957 * transfers we need the same AUX IOs to be powered but with DC states 958 * disabled. Accordingly use the AUX_IO_<port> power domain here which 959 * leaves DC states enabled. 960 * 961 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 962 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 963 * well, so we can acquire a wider AUX_<port> power domain reference 964 * instead of a specific AUX_IO_<port> reference without powering up any 965 * extra wells. 966 */ 967 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 968 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 969 else if (DISPLAY_VER(display) < 14 && 970 (intel_crtc_has_dp_encoder(crtc_state) || 971 intel_encoder_is_tc(&dig_port->base))) 972 return intel_aux_power_domain(dig_port); 973 else 974 return POWER_DOMAIN_INVALID; 975 } 976 977 static void 978 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 979 const struct intel_crtc_state *crtc_state) 980 { 981 struct intel_display *display = to_intel_display(dig_port); 982 enum intel_display_power_domain domain = 983 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 984 985 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 986 987 if (domain == POWER_DOMAIN_INVALID) 988 return; 989 990 dig_port->aux_wakeref = intel_display_power_get(display, domain); 991 } 992 993 static void 994 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 995 const struct intel_crtc_state *crtc_state) 996 { 997 struct intel_display *display = to_intel_display(dig_port); 998 enum intel_display_power_domain domain = 999 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1000 intel_wakeref_t wf; 1001 1002 wf = fetch_and_zero(&dig_port->aux_wakeref); 1003 if (!wf) 1004 return; 1005 1006 intel_display_power_put(display, domain, wf); 1007 } 1008 1009 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1010 struct intel_crtc_state *crtc_state) 1011 { 1012 struct intel_display *display = to_intel_display(encoder); 1013 struct intel_digital_port *dig_port; 1014 1015 /* 1016 * TODO: Add support for MST encoders. Atm, the following should never 1017 * happen since fake-MST encoders don't set their get_power_domains() 1018 * hook. 1019 */ 1020 if (drm_WARN_ON(display->drm, 1021 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1022 return; 1023 1024 dig_port = enc_to_dig_port(encoder); 1025 1026 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1027 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1028 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1029 dig_port->ddi_io_power_domain); 1030 } 1031 1032 main_link_aux_power_domain_get(dig_port, crtc_state); 1033 } 1034 1035 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1036 const struct intel_crtc_state *crtc_state) 1037 { 1038 struct intel_display *display = to_intel_display(crtc_state); 1039 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1040 enum phy phy = intel_encoder_to_phy(encoder); 1041 u32 val; 1042 1043 if (cpu_transcoder == TRANSCODER_EDP) 1044 return; 1045 1046 if (DISPLAY_VER(display) >= 13) 1047 val = TGL_TRANS_CLK_SEL_PORT(phy); 1048 else if (DISPLAY_VER(display) >= 12) 1049 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1050 else 1051 val = TRANS_CLK_SEL_PORT(encoder->port); 1052 1053 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1054 } 1055 1056 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1057 { 1058 struct intel_display *display = to_intel_display(crtc_state); 1059 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1060 u32 val; 1061 1062 if (cpu_transcoder == TRANSCODER_EDP) 1063 return; 1064 1065 if (DISPLAY_VER(display) >= 12) 1066 val = TGL_TRANS_CLK_SEL_DISABLED; 1067 else 1068 val = TRANS_CLK_SEL_DISABLED; 1069 1070 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1071 } 1072 1073 static void _skl_ddi_set_iboost(struct intel_display *display, 1074 enum port port, u8 iboost) 1075 { 1076 u32 tmp; 1077 1078 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1079 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1080 if (iboost) 1081 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1082 else 1083 tmp |= BALANCE_LEG_DISABLE(port); 1084 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1085 } 1086 1087 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1088 const struct intel_crtc_state *crtc_state, 1089 int level) 1090 { 1091 struct intel_display *display = to_intel_display(encoder); 1092 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1093 u8 iboost; 1094 1095 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1096 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1097 else 1098 iboost = intel_bios_dp_boost_level(encoder->devdata); 1099 1100 if (iboost == 0) { 1101 const struct intel_ddi_buf_trans *trans; 1102 int n_entries; 1103 1104 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1105 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1106 return; 1107 1108 iboost = trans->entries[level].hsw.i_boost; 1109 } 1110 1111 /* Make sure that the requested I_boost is valid */ 1112 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1113 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1114 return; 1115 } 1116 1117 _skl_ddi_set_iboost(display, encoder->port, iboost); 1118 1119 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1120 _skl_ddi_set_iboost(display, PORT_E, iboost); 1121 } 1122 1123 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1124 const struct intel_crtc_state *crtc_state) 1125 { 1126 struct intel_display *display = to_intel_display(intel_dp); 1127 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1128 int n_entries; 1129 1130 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1131 1132 if (drm_WARN_ON(display->drm, n_entries < 1)) 1133 n_entries = 1; 1134 if (drm_WARN_ON(display->drm, 1135 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1136 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1137 1138 return index_to_dp_signal_levels[n_entries - 1] & 1139 DP_TRAIN_VOLTAGE_SWING_MASK; 1140 } 1141 1142 /* 1143 * We assume that the full set of pre-emphasis values can be 1144 * used on all DDI platforms. Should that change we need to 1145 * rethink this code. 1146 */ 1147 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1148 { 1149 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1150 } 1151 1152 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1153 int lane) 1154 { 1155 if (crtc_state->port_clock > 600000) 1156 return 0; 1157 1158 if (crtc_state->lane_count == 4) 1159 return lane >= 1 ? LOADGEN_SELECT : 0; 1160 else 1161 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1162 } 1163 1164 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1165 const struct intel_crtc_state *crtc_state) 1166 { 1167 struct intel_display *display = to_intel_display(encoder); 1168 const struct intel_ddi_buf_trans *trans; 1169 enum phy phy = intel_encoder_to_phy(encoder); 1170 int n_entries, ln; 1171 u32 val; 1172 1173 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1174 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1175 return; 1176 1177 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1178 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1179 1180 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1181 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1182 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1183 intel_dp->hobl_active ? val : 0); 1184 } 1185 1186 /* Set PORT_TX_DW5 */ 1187 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1188 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1189 COEFF_POLARITY | CURSOR_PROGRAM | 1190 TAP2_DISABLE | TAP3_DISABLE); 1191 val |= SCALING_MODE_SEL(0x2); 1192 val |= RTERM_SELECT(0x6); 1193 val |= TAP3_DISABLE; 1194 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1195 1196 /* Program PORT_TX_DW2 */ 1197 for (ln = 0; ln < 4; ln++) { 1198 int level = intel_ddi_level(encoder, crtc_state, ln); 1199 1200 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1201 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1202 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1203 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1204 RCOMP_SCALAR(0x98)); 1205 } 1206 1207 /* Program PORT_TX_DW4 */ 1208 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1209 for (ln = 0; ln < 4; ln++) { 1210 int level = intel_ddi_level(encoder, crtc_state, ln); 1211 1212 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1213 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1214 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1215 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1216 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1217 } 1218 1219 /* Program PORT_TX_DW7 */ 1220 for (ln = 0; ln < 4; ln++) { 1221 int level = intel_ddi_level(encoder, crtc_state, ln); 1222 1223 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1224 N_SCALAR_MASK, 1225 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1226 } 1227 } 1228 1229 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1230 const struct intel_crtc_state *crtc_state) 1231 { 1232 struct intel_display *display = to_intel_display(encoder); 1233 enum phy phy = intel_encoder_to_phy(encoder); 1234 u32 val; 1235 int ln; 1236 1237 /* 1238 * 1. If port type is eDP or DP, 1239 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1240 * else clear to 0b. 1241 */ 1242 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1243 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1244 val &= ~COMMON_KEEPER_EN; 1245 else 1246 val |= COMMON_KEEPER_EN; 1247 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1248 1249 /* 2. Program loadgen select */ 1250 /* 1251 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1252 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1253 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1254 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1255 */ 1256 for (ln = 0; ln < 4; ln++) { 1257 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1258 LOADGEN_SELECT, 1259 icl_combo_phy_loadgen_select(crtc_state, ln)); 1260 } 1261 1262 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1263 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1264 0, SUS_CLOCK_CONFIG); 1265 1266 /* 4. Clear training enable to change swing values */ 1267 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1268 val &= ~TX_TRAINING_EN; 1269 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1270 1271 /* 5. Program swing and de-emphasis */ 1272 icl_ddi_combo_vswing_program(encoder, crtc_state); 1273 1274 /* 6. Set training enable to trigger update */ 1275 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1276 val |= TX_TRAINING_EN; 1277 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1278 } 1279 1280 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1281 const struct intel_crtc_state *crtc_state) 1282 { 1283 struct intel_display *display = to_intel_display(encoder); 1284 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1285 const struct intel_ddi_buf_trans *trans; 1286 int n_entries, ln; 1287 1288 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1289 return; 1290 1291 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1292 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1293 return; 1294 1295 for (ln = 0; ln < 2; ln++) { 1296 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1297 CRI_USE_FS32, 0); 1298 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1299 CRI_USE_FS32, 0); 1300 } 1301 1302 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1303 for (ln = 0; ln < 2; ln++) { 1304 int level; 1305 1306 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1307 1308 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1309 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1310 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1311 1312 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1313 1314 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1315 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1316 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1317 } 1318 1319 /* Program MG_TX_DRVCTRL with values from vswing table */ 1320 for (ln = 0; ln < 2; ln++) { 1321 int level; 1322 1323 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1324 1325 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1326 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1327 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1328 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1329 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1330 CRI_TXDEEMPH_OVERRIDE_EN); 1331 1332 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1333 1334 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1335 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1336 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1337 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1338 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1339 CRI_TXDEEMPH_OVERRIDE_EN); 1340 1341 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1342 } 1343 1344 /* 1345 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1346 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1347 * values from table for which TX1 and TX2 enabled. 1348 */ 1349 for (ln = 0; ln < 2; ln++) { 1350 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1351 CFG_LOW_RATE_LKREN_EN, 1352 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1353 } 1354 1355 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1356 for (ln = 0; ln < 2; ln++) { 1357 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1358 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1359 CFG_AMI_CK_DIV_OVERRIDE_EN, 1360 crtc_state->port_clock > 500000 ? 1361 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1362 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1363 1364 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1365 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1366 CFG_AMI_CK_DIV_OVERRIDE_EN, 1367 crtc_state->port_clock > 500000 ? 1368 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1369 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1370 } 1371 1372 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1373 for (ln = 0; ln < 2; ln++) { 1374 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1375 0, CRI_CALCINIT); 1376 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1377 0, CRI_CALCINIT); 1378 } 1379 } 1380 1381 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1382 const struct intel_crtc_state *crtc_state) 1383 { 1384 struct intel_display *display = to_intel_display(encoder); 1385 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1386 const struct intel_ddi_buf_trans *trans; 1387 int n_entries, ln; 1388 1389 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1390 return; 1391 1392 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1393 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1394 return; 1395 1396 for (ln = 0; ln < 2; ln++) { 1397 int level; 1398 1399 /* Wa_16011342517:adl-p */ 1400 if (display->platform.alderlake_p && 1401 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) { 1402 if ((intel_encoder_is_hdmi(encoder) && 1403 crtc_state->port_clock == 594000) || 1404 (intel_encoder_is_dp(encoder) && 1405 crtc_state->port_clock == 162000)) { 1406 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1407 LOADGEN_SHARING_PMD_DISABLE, 1); 1408 } else { 1409 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1410 LOADGEN_SHARING_PMD_DISABLE, 0); 1411 } 1412 } 1413 1414 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1415 1416 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1417 1418 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1419 DKL_TX_PRESHOOT_COEFF_MASK | 1420 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1421 DKL_TX_VSWING_CONTROL_MASK, 1422 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1423 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1424 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1425 1426 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1427 1428 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1429 DKL_TX_PRESHOOT_COEFF_MASK | 1430 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1431 DKL_TX_VSWING_CONTROL_MASK, 1432 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1433 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1434 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1435 1436 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1437 DKL_TX_DP20BITMODE, 0); 1438 1439 if (display->platform.alderlake_p) { 1440 u32 val; 1441 1442 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1443 if (ln == 0) { 1444 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1445 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1446 } else { 1447 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1448 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1449 } 1450 } else { 1451 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1452 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1453 } 1454 1455 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1456 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1457 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1458 val); 1459 } 1460 } 1461 } 1462 1463 static int translate_signal_level(struct intel_dp *intel_dp, 1464 u8 signal_levels) 1465 { 1466 struct intel_display *display = to_intel_display(intel_dp); 1467 int i; 1468 1469 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1470 if (index_to_dp_signal_levels[i] == signal_levels) 1471 return i; 1472 } 1473 1474 drm_WARN(display->drm, 1, 1475 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1476 signal_levels); 1477 1478 return 0; 1479 } 1480 1481 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1482 const struct intel_crtc_state *crtc_state, 1483 int lane) 1484 { 1485 u8 train_set = intel_dp->train_set[lane]; 1486 1487 if (intel_dp_is_uhbr(crtc_state)) { 1488 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1489 } else { 1490 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1491 DP_TRAIN_PRE_EMPHASIS_MASK); 1492 1493 return translate_signal_level(intel_dp, signal_levels); 1494 } 1495 } 1496 1497 int intel_ddi_level(struct intel_encoder *encoder, 1498 const struct intel_crtc_state *crtc_state, 1499 int lane) 1500 { 1501 struct intel_display *display = to_intel_display(encoder); 1502 const struct intel_ddi_buf_trans *trans; 1503 int level, n_entries; 1504 1505 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1506 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1507 return 0; 1508 1509 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1510 level = intel_ddi_hdmi_level(encoder, trans); 1511 else 1512 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1513 lane); 1514 1515 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1516 level = n_entries - 1; 1517 1518 return level; 1519 } 1520 1521 static void 1522 hsw_set_signal_levels(struct intel_encoder *encoder, 1523 const struct intel_crtc_state *crtc_state) 1524 { 1525 struct intel_display *display = to_intel_display(encoder); 1526 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1527 int level = intel_ddi_level(encoder, crtc_state, 0); 1528 enum port port = encoder->port; 1529 u32 signal_levels; 1530 1531 if (has_iboost(display)) 1532 skl_ddi_set_iboost(encoder, crtc_state, level); 1533 1534 /* HDMI ignores the rest */ 1535 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1536 return; 1537 1538 signal_levels = DDI_BUF_TRANS_SELECT(level); 1539 1540 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1541 signal_levels); 1542 1543 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1544 intel_dp->DP |= signal_levels; 1545 1546 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1547 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1548 } 1549 1550 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1551 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1552 { 1553 mutex_lock(&display->dpll.lock); 1554 1555 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1556 1557 /* 1558 * "This step and the step before must be 1559 * done with separate register writes." 1560 */ 1561 intel_de_rmw(display, reg, clk_off, 0); 1562 1563 mutex_unlock(&display->dpll.lock); 1564 } 1565 1566 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1567 u32 clk_off) 1568 { 1569 mutex_lock(&display->dpll.lock); 1570 1571 intel_de_rmw(display, reg, 0, clk_off); 1572 1573 mutex_unlock(&display->dpll.lock); 1574 } 1575 1576 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1577 u32 clk_off) 1578 { 1579 return !(intel_de_read(display, reg) & clk_off); 1580 } 1581 1582 static struct intel_dpll * 1583 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1584 u32 clk_sel_mask, u32 clk_sel_shift) 1585 { 1586 enum intel_dpll_id id; 1587 1588 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1589 1590 return intel_get_dpll_by_id(display, id); 1591 } 1592 1593 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1594 const struct intel_crtc_state *crtc_state) 1595 { 1596 struct intel_display *display = to_intel_display(encoder); 1597 const struct intel_dpll *pll = crtc_state->intel_dpll; 1598 enum phy phy = intel_encoder_to_phy(encoder); 1599 1600 if (drm_WARN_ON(display->drm, !pll)) 1601 return; 1602 1603 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1604 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1605 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1606 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1607 } 1608 1609 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1610 { 1611 struct intel_display *display = to_intel_display(encoder); 1612 enum phy phy = intel_encoder_to_phy(encoder); 1613 1614 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1615 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1616 } 1617 1618 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1619 { 1620 struct intel_display *display = to_intel_display(encoder); 1621 enum phy phy = intel_encoder_to_phy(encoder); 1622 1623 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1624 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1625 } 1626 1627 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1628 { 1629 struct intel_display *display = to_intel_display(encoder); 1630 enum phy phy = intel_encoder_to_phy(encoder); 1631 1632 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1633 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1634 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1635 } 1636 1637 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1638 const struct intel_crtc_state *crtc_state) 1639 { 1640 struct intel_display *display = to_intel_display(encoder); 1641 const struct intel_dpll *pll = crtc_state->intel_dpll; 1642 enum phy phy = intel_encoder_to_phy(encoder); 1643 1644 if (drm_WARN_ON(display->drm, !pll)) 1645 return; 1646 1647 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1648 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1649 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1650 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1651 } 1652 1653 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1654 { 1655 struct intel_display *display = to_intel_display(encoder); 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 1658 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1659 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1660 } 1661 1662 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1663 { 1664 struct intel_display *display = to_intel_display(encoder); 1665 enum phy phy = intel_encoder_to_phy(encoder); 1666 1667 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1668 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1669 } 1670 1671 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1672 { 1673 struct intel_display *display = to_intel_display(encoder); 1674 enum phy phy = intel_encoder_to_phy(encoder); 1675 1676 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1677 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1678 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1679 } 1680 1681 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1682 const struct intel_crtc_state *crtc_state) 1683 { 1684 struct intel_display *display = to_intel_display(encoder); 1685 const struct intel_dpll *pll = crtc_state->intel_dpll; 1686 enum phy phy = intel_encoder_to_phy(encoder); 1687 1688 if (drm_WARN_ON(display->drm, !pll)) 1689 return; 1690 1691 /* 1692 * If we fail this, something went very wrong: first 2 PLLs should be 1693 * used by first 2 phys and last 2 PLLs by last phys 1694 */ 1695 if (drm_WARN_ON(display->drm, 1696 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1697 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1698 return; 1699 1700 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1701 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1702 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1703 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1704 } 1705 1706 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1707 { 1708 struct intel_display *display = to_intel_display(encoder); 1709 enum phy phy = intel_encoder_to_phy(encoder); 1710 1711 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1712 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1713 } 1714 1715 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1716 { 1717 struct intel_display *display = to_intel_display(encoder); 1718 enum phy phy = intel_encoder_to_phy(encoder); 1719 1720 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1721 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1722 } 1723 1724 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1725 { 1726 struct intel_display *display = to_intel_display(encoder); 1727 enum phy phy = intel_encoder_to_phy(encoder); 1728 enum intel_dpll_id id; 1729 u32 val; 1730 1731 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1732 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1733 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1734 id = val; 1735 1736 /* 1737 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1738 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1739 * bit for phy C and D. 1740 */ 1741 if (phy >= PHY_C) 1742 id += DPLL_ID_DG1_DPLL2; 1743 1744 return intel_get_dpll_by_id(display, id); 1745 } 1746 1747 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1748 const struct intel_crtc_state *crtc_state) 1749 { 1750 struct intel_display *display = to_intel_display(encoder); 1751 const struct intel_dpll *pll = crtc_state->intel_dpll; 1752 enum phy phy = intel_encoder_to_phy(encoder); 1753 1754 if (drm_WARN_ON(display->drm, !pll)) 1755 return; 1756 1757 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1758 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1759 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1760 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1761 } 1762 1763 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1764 { 1765 struct intel_display *display = to_intel_display(encoder); 1766 enum phy phy = intel_encoder_to_phy(encoder); 1767 1768 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1769 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1770 } 1771 1772 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1773 { 1774 struct intel_display *display = to_intel_display(encoder); 1775 enum phy phy = intel_encoder_to_phy(encoder); 1776 1777 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1778 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1779 } 1780 1781 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1782 { 1783 struct intel_display *display = to_intel_display(encoder); 1784 enum phy phy = intel_encoder_to_phy(encoder); 1785 1786 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1787 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1788 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1789 } 1790 1791 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1792 const struct intel_crtc_state *crtc_state) 1793 { 1794 struct intel_display *display = to_intel_display(encoder); 1795 const struct intel_dpll *pll = crtc_state->intel_dpll; 1796 enum port port = encoder->port; 1797 1798 if (drm_WARN_ON(display->drm, !pll)) 1799 return; 1800 1801 /* 1802 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1803 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1804 */ 1805 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1806 1807 icl_ddi_combo_enable_clock(encoder, crtc_state); 1808 } 1809 1810 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1811 { 1812 struct intel_display *display = to_intel_display(encoder); 1813 enum port port = encoder->port; 1814 1815 icl_ddi_combo_disable_clock(encoder); 1816 1817 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1818 } 1819 1820 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1821 { 1822 struct intel_display *display = to_intel_display(encoder); 1823 enum port port = encoder->port; 1824 u32 tmp; 1825 1826 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1827 1828 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1829 return false; 1830 1831 return icl_ddi_combo_is_clock_enabled(encoder); 1832 } 1833 1834 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1835 const struct intel_crtc_state *crtc_state) 1836 { 1837 struct intel_display *display = to_intel_display(encoder); 1838 const struct intel_dpll *pll = crtc_state->intel_dpll; 1839 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1840 enum port port = encoder->port; 1841 1842 if (drm_WARN_ON(display->drm, !pll)) 1843 return; 1844 1845 intel_de_write(display, DDI_CLK_SEL(port), 1846 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1847 1848 mutex_lock(&display->dpll.lock); 1849 1850 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1851 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1852 1853 mutex_unlock(&display->dpll.lock); 1854 } 1855 1856 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1857 { 1858 struct intel_display *display = to_intel_display(encoder); 1859 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1860 enum port port = encoder->port; 1861 1862 mutex_lock(&display->dpll.lock); 1863 1864 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1865 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1866 1867 mutex_unlock(&display->dpll.lock); 1868 1869 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1870 } 1871 1872 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1873 { 1874 struct intel_display *display = to_intel_display(encoder); 1875 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1876 enum port port = encoder->port; 1877 u32 tmp; 1878 1879 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1880 1881 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1882 return false; 1883 1884 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1885 1886 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1887 } 1888 1889 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1890 { 1891 struct intel_display *display = to_intel_display(encoder); 1892 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1893 enum port port = encoder->port; 1894 enum intel_dpll_id id; 1895 u32 tmp; 1896 1897 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1898 1899 switch (tmp & DDI_CLK_SEL_MASK) { 1900 case DDI_CLK_SEL_TBT_162: 1901 case DDI_CLK_SEL_TBT_270: 1902 case DDI_CLK_SEL_TBT_540: 1903 case DDI_CLK_SEL_TBT_810: 1904 id = DPLL_ID_ICL_TBTPLL; 1905 break; 1906 case DDI_CLK_SEL_MG: 1907 id = icl_tc_port_to_pll_id(tc_port); 1908 break; 1909 default: 1910 MISSING_CASE(tmp); 1911 fallthrough; 1912 case DDI_CLK_SEL_NONE: 1913 return NULL; 1914 } 1915 1916 return intel_get_dpll_by_id(display, id); 1917 } 1918 1919 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1920 { 1921 struct intel_display *display = to_intel_display(encoder->base.dev); 1922 enum intel_dpll_id id; 1923 1924 switch (encoder->port) { 1925 case PORT_A: 1926 id = DPLL_ID_SKL_DPLL0; 1927 break; 1928 case PORT_B: 1929 id = DPLL_ID_SKL_DPLL1; 1930 break; 1931 case PORT_C: 1932 id = DPLL_ID_SKL_DPLL2; 1933 break; 1934 default: 1935 MISSING_CASE(encoder->port); 1936 return NULL; 1937 } 1938 1939 return intel_get_dpll_by_id(display, id); 1940 } 1941 1942 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1943 const struct intel_crtc_state *crtc_state) 1944 { 1945 struct intel_display *display = to_intel_display(encoder); 1946 const struct intel_dpll *pll = crtc_state->intel_dpll; 1947 enum port port = encoder->port; 1948 1949 if (drm_WARN_ON(display->drm, !pll)) 1950 return; 1951 1952 mutex_lock(&display->dpll.lock); 1953 1954 intel_de_rmw(display, DPLL_CTRL2, 1955 DPLL_CTRL2_DDI_CLK_OFF(port) | 1956 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1957 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1958 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1959 1960 mutex_unlock(&display->dpll.lock); 1961 } 1962 1963 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1964 { 1965 struct intel_display *display = to_intel_display(encoder); 1966 enum port port = encoder->port; 1967 1968 mutex_lock(&display->dpll.lock); 1969 1970 intel_de_rmw(display, DPLL_CTRL2, 1971 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1972 1973 mutex_unlock(&display->dpll.lock); 1974 } 1975 1976 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1977 { 1978 struct intel_display *display = to_intel_display(encoder); 1979 enum port port = encoder->port; 1980 1981 /* 1982 * FIXME Not sure if the override affects both 1983 * the PLL selection and the CLK_OFF bit. 1984 */ 1985 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1986 } 1987 1988 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1989 { 1990 struct intel_display *display = to_intel_display(encoder); 1991 enum port port = encoder->port; 1992 enum intel_dpll_id id; 1993 u32 tmp; 1994 1995 tmp = intel_de_read(display, DPLL_CTRL2); 1996 1997 /* 1998 * FIXME Not sure if the override affects both 1999 * the PLL selection and the CLK_OFF bit. 2000 */ 2001 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2002 return NULL; 2003 2004 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2005 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2006 2007 return intel_get_dpll_by_id(display, id); 2008 } 2009 2010 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2011 const struct intel_crtc_state *crtc_state) 2012 { 2013 struct intel_display *display = to_intel_display(encoder); 2014 const struct intel_dpll *pll = crtc_state->intel_dpll; 2015 enum port port = encoder->port; 2016 2017 if (drm_WARN_ON(display->drm, !pll)) 2018 return; 2019 2020 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2021 } 2022 2023 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2024 { 2025 struct intel_display *display = to_intel_display(encoder); 2026 enum port port = encoder->port; 2027 2028 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2029 } 2030 2031 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2032 { 2033 struct intel_display *display = to_intel_display(encoder); 2034 enum port port = encoder->port; 2035 2036 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2037 } 2038 2039 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2040 { 2041 struct intel_display *display = to_intel_display(encoder); 2042 enum port port = encoder->port; 2043 enum intel_dpll_id id; 2044 u32 tmp; 2045 2046 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2047 2048 switch (tmp & PORT_CLK_SEL_MASK) { 2049 case PORT_CLK_SEL_WRPLL1: 2050 id = DPLL_ID_WRPLL1; 2051 break; 2052 case PORT_CLK_SEL_WRPLL2: 2053 id = DPLL_ID_WRPLL2; 2054 break; 2055 case PORT_CLK_SEL_SPLL: 2056 id = DPLL_ID_SPLL; 2057 break; 2058 case PORT_CLK_SEL_LCPLL_810: 2059 id = DPLL_ID_LCPLL_810; 2060 break; 2061 case PORT_CLK_SEL_LCPLL_1350: 2062 id = DPLL_ID_LCPLL_1350; 2063 break; 2064 case PORT_CLK_SEL_LCPLL_2700: 2065 id = DPLL_ID_LCPLL_2700; 2066 break; 2067 default: 2068 MISSING_CASE(tmp); 2069 fallthrough; 2070 case PORT_CLK_SEL_NONE: 2071 return NULL; 2072 } 2073 2074 return intel_get_dpll_by_id(display, id); 2075 } 2076 2077 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2078 const struct intel_crtc_state *crtc_state) 2079 { 2080 if (encoder->enable_clock) 2081 encoder->enable_clock(encoder, crtc_state); 2082 } 2083 2084 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2085 { 2086 if (encoder->disable_clock) 2087 encoder->disable_clock(encoder); 2088 } 2089 2090 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2091 { 2092 struct intel_display *display = to_intel_display(encoder); 2093 u32 port_mask; 2094 bool ddi_clk_needed; 2095 2096 /* 2097 * In case of DP MST, we sanitize the primary encoder only, not the 2098 * virtual ones. 2099 */ 2100 if (encoder->type == INTEL_OUTPUT_DP_MST) 2101 return; 2102 2103 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2104 u8 pipe_mask; 2105 bool is_mst; 2106 2107 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2108 /* 2109 * In the unlikely case that BIOS enables DP in MST mode, just 2110 * warn since our MST HW readout is incomplete. 2111 */ 2112 if (drm_WARN_ON(display->drm, is_mst)) 2113 return; 2114 } 2115 2116 port_mask = BIT(encoder->port); 2117 ddi_clk_needed = encoder->base.crtc; 2118 2119 if (encoder->type == INTEL_OUTPUT_DSI) { 2120 struct intel_encoder *other_encoder; 2121 2122 port_mask = intel_dsi_encoder_ports(encoder); 2123 /* 2124 * Sanity check that we haven't incorrectly registered another 2125 * encoder using any of the ports of this DSI encoder. 2126 */ 2127 for_each_intel_encoder(display->drm, other_encoder) { 2128 if (other_encoder == encoder) 2129 continue; 2130 2131 if (drm_WARN_ON(display->drm, 2132 port_mask & BIT(other_encoder->port))) 2133 return; 2134 } 2135 /* 2136 * For DSI we keep the ddi clocks gated 2137 * except during enable/disable sequence. 2138 */ 2139 ddi_clk_needed = false; 2140 } 2141 2142 if (ddi_clk_needed || !encoder->is_clock_enabled || 2143 !encoder->is_clock_enabled(encoder)) 2144 return; 2145 2146 drm_dbg_kms(display->drm, 2147 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2148 encoder->base.base.id, encoder->base.name); 2149 2150 encoder->disable_clock(encoder); 2151 } 2152 2153 static void 2154 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2155 enum tc_port tc_port, u32 ln0, u32 ln1) 2156 { 2157 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2158 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2159 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2160 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2161 } 2162 2163 static void 2164 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2165 const struct intel_crtc_state *crtc_state) 2166 { 2167 struct intel_display *display = to_intel_display(crtc_state); 2168 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2169 u32 ln0, ln1, pin_assignment; 2170 u8 width; 2171 2172 if (DISPLAY_VER(display) >= 14) 2173 return; 2174 2175 if (!intel_encoder_is_tc(&dig_port->base) || 2176 intel_tc_port_in_tbt_alt_mode(dig_port)) 2177 return; 2178 2179 if (DISPLAY_VER(display) >= 12) { 2180 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2181 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2182 } else { 2183 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2184 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2185 } 2186 2187 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2188 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2189 2190 /* DPPATC */ 2191 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2192 width = crtc_state->lane_count; 2193 2194 switch (pin_assignment) { 2195 case 0x0: 2196 drm_WARN_ON(display->drm, 2197 !intel_tc_port_in_legacy_mode(dig_port)); 2198 if (width == 1) { 2199 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2200 } else { 2201 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2202 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2203 } 2204 break; 2205 case 0x1: 2206 if (width == 4) { 2207 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2208 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2209 } 2210 break; 2211 case 0x2: 2212 if (width == 2) { 2213 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2214 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2215 } 2216 break; 2217 case 0x3: 2218 case 0x5: 2219 if (width == 1) { 2220 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2221 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2222 } else { 2223 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2224 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2225 } 2226 break; 2227 case 0x4: 2228 case 0x6: 2229 if (width == 1) { 2230 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2231 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2232 } else { 2233 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2234 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2235 } 2236 break; 2237 default: 2238 MISSING_CASE(pin_assignment); 2239 } 2240 2241 if (DISPLAY_VER(display) >= 12) { 2242 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2243 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2244 /* WA_14018221282 */ 2245 if (IS_DISPLAY_VER(display, 12, 13)) 2246 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2247 2248 } else { 2249 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2250 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2251 } 2252 } 2253 2254 static enum transcoder 2255 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2256 { 2257 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2258 return crtc_state->mst_master_transcoder; 2259 else 2260 return crtc_state->cpu_transcoder; 2261 } 2262 2263 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2264 const struct intel_crtc_state *crtc_state) 2265 { 2266 struct intel_display *display = to_intel_display(encoder); 2267 2268 if (DISPLAY_VER(display) >= 12) 2269 return TGL_DP_TP_CTL(display, 2270 tgl_dp_tp_transcoder(crtc_state)); 2271 else 2272 return DP_TP_CTL(encoder->port); 2273 } 2274 2275 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2276 const struct intel_crtc_state *crtc_state) 2277 { 2278 struct intel_display *display = to_intel_display(encoder); 2279 2280 if (DISPLAY_VER(display) >= 12) 2281 return TGL_DP_TP_STATUS(display, 2282 tgl_dp_tp_transcoder(crtc_state)); 2283 else 2284 return DP_TP_STATUS(encoder->port); 2285 } 2286 2287 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2288 const struct intel_crtc_state *crtc_state) 2289 { 2290 struct intel_display *display = to_intel_display(encoder); 2291 2292 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2293 DP_TP_STATUS_ACT_SENT); 2294 } 2295 2296 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2297 const struct intel_crtc_state *crtc_state) 2298 { 2299 struct intel_display *display = to_intel_display(encoder); 2300 2301 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2302 DP_TP_STATUS_ACT_SENT, 1)) 2303 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2304 } 2305 2306 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2307 const struct intel_crtc_state *crtc_state, 2308 bool enable) 2309 { 2310 struct intel_display *display = to_intel_display(intel_dp); 2311 2312 if (!crtc_state->vrr.enable) 2313 return; 2314 2315 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2316 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2317 drm_dbg_kms(display->drm, 2318 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2319 str_enable_disable(enable)); 2320 } 2321 2322 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2323 const struct intel_crtc_state *crtc_state, 2324 bool enable) 2325 { 2326 struct intel_display *display = to_intel_display(intel_dp); 2327 2328 if (!crtc_state->fec_enable) 2329 return; 2330 2331 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2332 enable ? DP_FEC_READY : 0) <= 0) 2333 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2334 str_enabled_disabled(enable)); 2335 2336 if (enable && 2337 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2338 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2339 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2340 } 2341 2342 static int read_fec_detected_status(struct drm_dp_aux *aux) 2343 { 2344 int ret; 2345 u8 status; 2346 2347 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2348 if (ret < 0) 2349 return ret; 2350 2351 return status; 2352 } 2353 2354 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2355 { 2356 struct intel_display *display = to_intel_display(aux->drm_dev); 2357 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2358 int status; 2359 int err; 2360 2361 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2362 status & mask || status < 0, 2363 10000, 200000); 2364 2365 if (err || status < 0) { 2366 drm_dbg_kms(display->drm, 2367 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2368 str_enabled_disabled(enabled), err, status); 2369 return err ? err : status; 2370 } 2371 2372 return 0; 2373 } 2374 2375 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2376 const struct intel_crtc_state *crtc_state, 2377 bool enabled) 2378 { 2379 struct intel_display *display = to_intel_display(encoder); 2380 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2381 int ret; 2382 2383 if (!crtc_state->fec_enable) 2384 return 0; 2385 2386 if (enabled) 2387 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2388 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2389 else 2390 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2391 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2392 2393 if (ret) { 2394 drm_err(display->drm, 2395 "Timeout waiting for FEC live state to get %s\n", 2396 str_enabled_disabled(enabled)); 2397 return ret; 2398 } 2399 /* 2400 * At least the Synoptics MST hub doesn't set the detected flag for 2401 * FEC decoding disabling so skip waiting for that. 2402 */ 2403 if (enabled) { 2404 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2405 if (ret) 2406 return ret; 2407 } 2408 2409 return 0; 2410 } 2411 2412 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2413 const struct intel_crtc_state *crtc_state) 2414 { 2415 struct intel_display *display = to_intel_display(encoder); 2416 int i; 2417 int ret; 2418 2419 if (!crtc_state->fec_enable) 2420 return; 2421 2422 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2423 0, DP_TP_CTL_FEC_ENABLE); 2424 2425 if (DISPLAY_VER(display) < 30) 2426 return; 2427 2428 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2429 if (!ret) 2430 return; 2431 2432 for (i = 0; i < 3; i++) { 2433 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2434 2435 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2436 DP_TP_CTL_FEC_ENABLE, 0); 2437 2438 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2439 if (ret) 2440 continue; 2441 2442 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2443 0, DP_TP_CTL_FEC_ENABLE); 2444 2445 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2446 if (!ret) 2447 return; 2448 } 2449 2450 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2451 } 2452 2453 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2454 const struct intel_crtc_state *crtc_state) 2455 { 2456 struct intel_display *display = to_intel_display(encoder); 2457 2458 if (!crtc_state->fec_enable) 2459 return; 2460 2461 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2462 DP_TP_CTL_FEC_ENABLE, 0); 2463 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2464 } 2465 2466 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2467 const struct intel_crtc_state *crtc_state) 2468 { 2469 struct intel_display *display = to_intel_display(encoder); 2470 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2471 2472 if (intel_encoder_is_combo(encoder)) { 2473 enum phy phy = intel_encoder_to_phy(encoder); 2474 2475 intel_combo_phy_power_up_lanes(display, phy, false, 2476 crtc_state->lane_count, 2477 dig_port->lane_reversal); 2478 } 2479 } 2480 2481 /* 2482 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2483 * platforms. 2484 */ 2485 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2486 { 2487 if (DISPLAY_VER(display) > 20) 2488 return ~0; 2489 else if (display->platform.alderlake_p) 2490 return BIT(PIPE_A) | BIT(PIPE_B); 2491 else 2492 return BIT(PIPE_A); 2493 } 2494 2495 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2496 struct intel_crtc_state *pipe_config) 2497 { 2498 struct intel_display *display = to_intel_display(pipe_config); 2499 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2500 enum pipe pipe = crtc->pipe; 2501 u32 dss1; 2502 2503 if (!HAS_MSO(display)) 2504 return; 2505 2506 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2507 2508 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2509 if (!pipe_config->splitter.enable) 2510 return; 2511 2512 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2513 pipe_config->splitter.enable = false; 2514 return; 2515 } 2516 2517 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2518 default: 2519 drm_WARN(display->drm, true, 2520 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2521 fallthrough; 2522 case SPLITTER_CONFIGURATION_2_SEGMENT: 2523 pipe_config->splitter.link_count = 2; 2524 break; 2525 case SPLITTER_CONFIGURATION_4_SEGMENT: 2526 pipe_config->splitter.link_count = 4; 2527 break; 2528 } 2529 2530 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2531 } 2532 2533 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2534 { 2535 struct intel_display *display = to_intel_display(crtc_state); 2536 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2537 enum pipe pipe = crtc->pipe; 2538 u32 dss1 = 0; 2539 2540 if (!HAS_MSO(display)) 2541 return; 2542 2543 if (crtc_state->splitter.enable) { 2544 dss1 |= SPLITTER_ENABLE; 2545 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2546 if (crtc_state->splitter.link_count == 2) 2547 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2548 else 2549 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2550 } 2551 2552 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2553 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2554 OVERLAP_PIXELS_MASK, dss1); 2555 } 2556 2557 static void 2558 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2559 { 2560 struct intel_display *display = to_intel_display(encoder); 2561 enum port port = encoder->port; 2562 i915_reg_t reg; 2563 u32 set_bits, wait_bits; 2564 2565 if (DISPLAY_VER(display) < 14) 2566 return; 2567 2568 if (DISPLAY_VER(display) >= 20) { 2569 reg = DDI_BUF_CTL(port); 2570 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2571 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2572 } else { 2573 reg = XELPDP_PORT_BUF_CTL1(display, port); 2574 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2575 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2576 } 2577 2578 intel_de_rmw(display, reg, 0, set_bits); 2579 if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { 2580 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2581 port_name(port)); 2582 } 2583 } 2584 2585 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2586 const struct intel_crtc_state *crtc_state) 2587 { 2588 struct intel_display *display = to_intel_display(encoder); 2589 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2590 enum port port = encoder->port; 2591 u32 val = 0; 2592 2593 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2594 2595 if (intel_dp_is_uhbr(crtc_state)) 2596 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2597 else 2598 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2599 2600 if (dig_port->lane_reversal) 2601 val |= XELPDP_PORT_REVERSAL; 2602 2603 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2604 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2605 val); 2606 } 2607 2608 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2609 { 2610 struct intel_display *display = to_intel_display(encoder); 2611 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2612 u32 val; 2613 2614 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2615 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2616 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2617 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2618 } 2619 2620 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2621 struct intel_encoder *encoder, 2622 const struct intel_crtc_state *crtc_state, 2623 const struct drm_connector_state *conn_state) 2624 { 2625 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2626 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2627 bool transparent_mode; 2628 int ret; 2629 2630 intel_dp_set_link_params(intel_dp, 2631 crtc_state->port_clock, 2632 crtc_state->lane_count); 2633 2634 /* 2635 * We only configure what the register value will be here. Actual 2636 * enabling happens during link training farther down. 2637 */ 2638 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2639 2640 /* 2641 * 1. Enable Power Wells 2642 * 2643 * This was handled at the beginning of intel_atomic_commit_tail(), 2644 * before we called down into this function. 2645 */ 2646 2647 /* 2. PMdemand was already set */ 2648 2649 /* 3. Select Thunderbolt */ 2650 mtl_port_buf_ctl_io_selection(encoder); 2651 2652 /* 4. Enable Panel Power if PPS is required */ 2653 intel_pps_on(intel_dp); 2654 2655 /* 5. Enable the port PLL */ 2656 intel_ddi_enable_clock(encoder, crtc_state); 2657 2658 /* 2659 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2660 * Transcoder. 2661 */ 2662 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2663 2664 /* 2665 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2666 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2667 * Transport Select 2668 */ 2669 intel_ddi_config_transcoder_func(encoder, crtc_state); 2670 2671 /* 2672 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2673 */ 2674 intel_ddi_mso_configure(crtc_state); 2675 2676 if (!is_mst) 2677 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2678 2679 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2680 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2681 2682 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2683 if (!is_mst) 2684 intel_dp_sink_enable_decompression(state, 2685 to_intel_connector(conn_state->connector), 2686 crtc_state); 2687 2688 /* 2689 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2690 * in the FEC_CONFIGURATION register to 1 before initiating link 2691 * training 2692 */ 2693 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2694 2695 intel_dp_check_frl_training(intel_dp); 2696 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2697 2698 /* 2699 * 6. The rest of the below are substeps under the bspec's "Enable and 2700 * Train Display Port" step. Note that steps that are specific to 2701 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2702 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2703 * us when active_mst_links==0, so any steps designated for "single 2704 * stream or multi-stream master transcoder" can just be performed 2705 * unconditionally here. 2706 * 2707 * mtl_ddi_prepare_link_retrain() that is called by 2708 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2709 * 6.i and 6.j 2710 * 2711 * 6.k Follow DisplayPort specification training sequence (see notes for 2712 * failure handling) 2713 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2714 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2715 * (timeout after 800 us) 2716 */ 2717 intel_dp_start_link_train(state, intel_dp, crtc_state); 2718 2719 /* 6.n Set DP_TP_CTL link training to Normal */ 2720 if (!is_trans_port_sync_mode(crtc_state)) 2721 intel_dp_stop_link_train(intel_dp, crtc_state); 2722 2723 /* 6.o Configure and enable FEC if needed */ 2724 intel_ddi_enable_fec(encoder, crtc_state); 2725 2726 /* 7.a 128b/132b SST. */ 2727 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2728 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2729 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2730 if (ret < 0) 2731 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2732 } 2733 2734 if (!is_mst) 2735 intel_dsc_dp_pps_write(encoder, crtc_state); 2736 } 2737 2738 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2739 struct intel_encoder *encoder, 2740 const struct intel_crtc_state *crtc_state, 2741 const struct drm_connector_state *conn_state) 2742 { 2743 struct intel_display *display = to_intel_display(encoder); 2744 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2745 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2746 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2747 int ret; 2748 2749 intel_dp_set_link_params(intel_dp, 2750 crtc_state->port_clock, 2751 crtc_state->lane_count); 2752 2753 /* 2754 * We only configure what the register value will be here. Actual 2755 * enabling happens during link training farther down. 2756 */ 2757 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2758 2759 /* 2760 * 1. Enable Power Wells 2761 * 2762 * This was handled at the beginning of intel_atomic_commit_tail(), 2763 * before we called down into this function. 2764 */ 2765 2766 /* 2. Enable Panel Power if PPS is required */ 2767 intel_pps_on(intel_dp); 2768 2769 /* 2770 * 3. For non-TBT Type-C ports, set FIA lane count 2771 * (DFLEXDPSP.DPX4TXLATC) 2772 * 2773 * This was done before tgl_ddi_pre_enable_dp by 2774 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2775 */ 2776 2777 /* 2778 * 4. Enable the port PLL. 2779 * 2780 * The PLL enabling itself was already done before this function by 2781 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2782 * configure the PLL to port mapping here. 2783 */ 2784 intel_ddi_enable_clock(encoder, crtc_state); 2785 2786 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2787 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2788 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2789 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2790 dig_port->ddi_io_power_domain); 2791 } 2792 2793 /* 6. Program DP_MODE */ 2794 icl_program_mg_dp_mode(dig_port, crtc_state); 2795 2796 /* 2797 * 7. The rest of the below are substeps under the bspec's "Enable and 2798 * Train Display Port" step. Note that steps that are specific to 2799 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2800 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2801 * us when active_mst_links==0, so any steps designated for "single 2802 * stream or multi-stream master transcoder" can just be performed 2803 * unconditionally here. 2804 */ 2805 2806 /* 2807 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2808 * Transcoder. 2809 */ 2810 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2811 2812 /* 2813 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2814 * Transport Select 2815 */ 2816 intel_ddi_config_transcoder_func(encoder, crtc_state); 2817 2818 /* 2819 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2820 * selected 2821 * 2822 * This will be handled by the intel_dp_start_link_train() farther 2823 * down this function. 2824 */ 2825 2826 /* 7.e Configure voltage swing and related IO settings */ 2827 encoder->set_signal_levels(encoder, crtc_state); 2828 2829 /* 2830 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2831 * the used lanes of the DDI. 2832 */ 2833 intel_ddi_power_up_lanes(encoder, crtc_state); 2834 2835 /* 2836 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2837 */ 2838 intel_ddi_mso_configure(crtc_state); 2839 2840 if (!is_mst) 2841 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2842 2843 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2844 if (!is_mst) 2845 intel_dp_sink_enable_decompression(state, 2846 to_intel_connector(conn_state->connector), 2847 crtc_state); 2848 /* 2849 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2850 * in the FEC_CONFIGURATION register to 1 before initiating link 2851 * training 2852 */ 2853 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2854 2855 intel_dp_check_frl_training(intel_dp); 2856 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2857 2858 /* 2859 * 7.i Follow DisplayPort specification training sequence (see notes for 2860 * failure handling) 2861 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2862 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2863 * (timeout after 800 us) 2864 */ 2865 intel_dp_start_link_train(state, intel_dp, crtc_state); 2866 2867 /* 7.k Set DP_TP_CTL link training to Normal */ 2868 if (!is_trans_port_sync_mode(crtc_state)) 2869 intel_dp_stop_link_train(intel_dp, crtc_state); 2870 2871 /* 7.l Configure and enable FEC if needed */ 2872 intel_ddi_enable_fec(encoder, crtc_state); 2873 2874 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2875 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2876 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2877 if (ret < 0) 2878 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2879 } 2880 2881 if (!is_mst) 2882 intel_dsc_dp_pps_write(encoder, crtc_state); 2883 } 2884 2885 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2886 struct intel_encoder *encoder, 2887 const struct intel_crtc_state *crtc_state, 2888 const struct drm_connector_state *conn_state) 2889 { 2890 struct intel_display *display = to_intel_display(encoder); 2891 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2892 enum port port = encoder->port; 2893 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2894 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2895 2896 if (DISPLAY_VER(display) < 11) 2897 drm_WARN_ON(display->drm, 2898 is_mst && (port == PORT_A || port == PORT_E)); 2899 else 2900 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2901 2902 intel_dp_set_link_params(intel_dp, 2903 crtc_state->port_clock, 2904 crtc_state->lane_count); 2905 2906 /* 2907 * We only configure what the register value will be here. Actual 2908 * enabling happens during link training farther down. 2909 */ 2910 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2911 2912 intel_pps_on(intel_dp); 2913 2914 intel_ddi_enable_clock(encoder, crtc_state); 2915 2916 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2917 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2918 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2919 dig_port->ddi_io_power_domain); 2920 } 2921 2922 icl_program_mg_dp_mode(dig_port, crtc_state); 2923 2924 if (has_buf_trans_select(display)) 2925 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2926 2927 encoder->set_signal_levels(encoder, crtc_state); 2928 2929 intel_ddi_power_up_lanes(encoder, crtc_state); 2930 2931 if (!is_mst) 2932 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2933 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2934 if (!is_mst) 2935 intel_dp_sink_enable_decompression(state, 2936 to_intel_connector(conn_state->connector), 2937 crtc_state); 2938 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2939 intel_dp_start_link_train(state, intel_dp, crtc_state); 2940 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2941 !is_trans_port_sync_mode(crtc_state)) 2942 intel_dp_stop_link_train(intel_dp, crtc_state); 2943 2944 intel_ddi_enable_fec(encoder, crtc_state); 2945 2946 if (!is_mst) { 2947 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2948 intel_dsc_dp_pps_write(encoder, crtc_state); 2949 } 2950 } 2951 2952 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2953 struct intel_encoder *encoder, 2954 const struct intel_crtc_state *crtc_state, 2955 const struct drm_connector_state *conn_state) 2956 { 2957 struct intel_display *display = to_intel_display(encoder); 2958 2959 if (HAS_DP20(display)) 2960 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2961 crtc_state); 2962 2963 /* Panel replay has to be enabled in sink dpcd before link training. */ 2964 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2965 2966 if (DISPLAY_VER(display) >= 14) 2967 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2968 else if (DISPLAY_VER(display) >= 12) 2969 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2970 else 2971 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2972 2973 /* MST will call a setting of MSA after an allocating of Virtual Channel 2974 * from MST encoder pre_enable callback. 2975 */ 2976 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2977 intel_ddi_set_dp_msa(crtc_state, conn_state); 2978 } 2979 2980 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2981 struct intel_encoder *encoder, 2982 const struct intel_crtc_state *crtc_state, 2983 const struct drm_connector_state *conn_state) 2984 { 2985 struct intel_display *display = to_intel_display(encoder); 2986 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2987 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2988 2989 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2990 intel_ddi_enable_clock(encoder, crtc_state); 2991 2992 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2993 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2994 dig_port->ddi_io_power_domain); 2995 2996 icl_program_mg_dp_mode(dig_port, crtc_state); 2997 2998 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2999 3000 dig_port->set_infoframes(encoder, 3001 crtc_state->has_infoframe, 3002 crtc_state, conn_state); 3003 } 3004 3005 /* 3006 * Note: Also called from the ->pre_enable of the first active MST stream 3007 * encoder on its primary encoder. 3008 * 3009 * When called from DP MST code: 3010 * 3011 * - conn_state will be NULL 3012 * 3013 * - encoder will be the primary encoder (i.e. mst->primary) 3014 * 3015 * - the main connector associated with this port won't be active or linked to a 3016 * crtc 3017 * 3018 * - crtc_state will be the state of the first stream to be activated on this 3019 * port, and it may not be the same stream that will be deactivated last, but 3020 * each stream should have a state that is identical when it comes to the DP 3021 * link parameters. 3022 */ 3023 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3024 struct intel_encoder *encoder, 3025 const struct intel_crtc_state *crtc_state, 3026 const struct drm_connector_state *conn_state) 3027 { 3028 struct intel_display *display = to_intel_display(state); 3029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3030 enum pipe pipe = crtc->pipe; 3031 3032 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3033 3034 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3035 3036 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3037 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3038 conn_state); 3039 } else { 3040 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3041 3042 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3043 conn_state); 3044 3045 /* FIXME precompute everything properly */ 3046 /* FIXME how do we turn infoframes off again? */ 3047 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3048 dig_port->set_infoframes(encoder, 3049 crtc_state->has_infoframe, 3050 crtc_state, conn_state); 3051 } 3052 } 3053 3054 static void 3055 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3056 { 3057 struct intel_display *display = to_intel_display(encoder); 3058 enum port port = encoder->port; 3059 i915_reg_t reg; 3060 u32 clr_bits, wait_bits; 3061 3062 if (DISPLAY_VER(display) < 14) 3063 return; 3064 3065 if (DISPLAY_VER(display) >= 20) { 3066 reg = DDI_BUF_CTL(port); 3067 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3068 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3069 } else { 3070 reg = XELPDP_PORT_BUF_CTL1(display, port); 3071 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3072 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3073 } 3074 3075 intel_de_rmw(display, reg, clr_bits, 0); 3076 if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) 3077 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3078 port_name(port)); 3079 } 3080 3081 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3082 { 3083 struct intel_display *display = to_intel_display(encoder); 3084 enum port port = encoder->port; 3085 3086 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3087 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3088 3089 intel_wait_ddi_buf_active(encoder); 3090 } 3091 3092 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3093 const struct intel_crtc_state *crtc_state) 3094 { 3095 struct intel_display *display = to_intel_display(encoder); 3096 enum port port = encoder->port; 3097 3098 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3099 3100 if (DISPLAY_VER(display) >= 14) 3101 intel_wait_ddi_buf_idle(display, port); 3102 3103 mtl_ddi_disable_d2d(encoder); 3104 3105 if (intel_crtc_has_dp_encoder(crtc_state)) { 3106 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3107 DP_TP_CTL_ENABLE, 0); 3108 } 3109 3110 intel_ddi_disable_fec(encoder, crtc_state); 3111 3112 if (DISPLAY_VER(display) < 14) 3113 intel_wait_ddi_buf_idle(display, port); 3114 3115 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3116 } 3117 3118 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3119 struct intel_encoder *encoder, 3120 const struct intel_crtc_state *old_crtc_state, 3121 const struct drm_connector_state *old_conn_state) 3122 { 3123 struct intel_display *display = to_intel_display(encoder); 3124 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3125 struct intel_dp *intel_dp = &dig_port->dp; 3126 intel_wakeref_t wakeref; 3127 bool is_mst = intel_crtc_has_type(old_crtc_state, 3128 INTEL_OUTPUT_DP_MST); 3129 3130 if (!is_mst) 3131 intel_dp_set_infoframes(encoder, false, 3132 old_crtc_state, old_conn_state); 3133 3134 /* 3135 * Power down sink before disabling the port, otherwise we end 3136 * up getting interrupts from the sink on detecting link loss. 3137 */ 3138 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3139 3140 if (DISPLAY_VER(display) >= 12) { 3141 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3142 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3143 3144 intel_de_rmw(display, 3145 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3146 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3147 0); 3148 } 3149 } else { 3150 if (!is_mst) 3151 intel_ddi_disable_transcoder_clock(old_crtc_state); 3152 } 3153 3154 intel_ddi_buf_disable(encoder, old_crtc_state); 3155 3156 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3157 3158 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3159 3160 /* 3161 * From TGL spec: "If single stream or multi-stream master transcoder: 3162 * Configure Transcoder Clock select to direct no clock to the 3163 * transcoder" 3164 */ 3165 if (DISPLAY_VER(display) >= 12) 3166 intel_ddi_disable_transcoder_clock(old_crtc_state); 3167 3168 intel_pps_vdd_on(intel_dp); 3169 intel_pps_off(intel_dp); 3170 3171 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3172 3173 if (wakeref) 3174 intel_display_power_put(display, 3175 dig_port->ddi_io_power_domain, 3176 wakeref); 3177 3178 intel_ddi_disable_clock(encoder); 3179 3180 /* De-select Thunderbolt */ 3181 if (DISPLAY_VER(display) >= 14) 3182 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3183 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3184 } 3185 3186 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3187 struct intel_encoder *encoder, 3188 const struct intel_crtc_state *old_crtc_state, 3189 const struct drm_connector_state *old_conn_state) 3190 { 3191 struct intel_display *display = to_intel_display(encoder); 3192 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3193 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3194 intel_wakeref_t wakeref; 3195 3196 dig_port->set_infoframes(encoder, false, 3197 old_crtc_state, old_conn_state); 3198 3199 if (DISPLAY_VER(display) < 12) 3200 intel_ddi_disable_transcoder_clock(old_crtc_state); 3201 3202 intel_ddi_buf_disable(encoder, old_crtc_state); 3203 3204 if (DISPLAY_VER(display) >= 12) 3205 intel_ddi_disable_transcoder_clock(old_crtc_state); 3206 3207 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3208 if (wakeref) 3209 intel_display_power_put(display, 3210 dig_port->ddi_io_power_domain, 3211 wakeref); 3212 3213 intel_ddi_disable_clock(encoder); 3214 3215 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3216 } 3217 3218 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3219 struct intel_encoder *encoder, 3220 const struct intel_crtc_state *old_crtc_state, 3221 const struct drm_connector_state *old_conn_state) 3222 { 3223 struct intel_display *display = to_intel_display(encoder); 3224 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3225 struct intel_crtc *pipe_crtc; 3226 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3227 int i; 3228 3229 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3230 const struct intel_crtc_state *old_pipe_crtc_state = 3231 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3232 3233 intel_crtc_vblank_off(old_pipe_crtc_state); 3234 } 3235 3236 intel_disable_transcoder(old_crtc_state); 3237 3238 /* 128b/132b SST */ 3239 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3240 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3241 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3242 3243 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3244 3245 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3246 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3247 3248 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3249 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3250 } 3251 3252 intel_vrr_transcoder_disable(old_crtc_state); 3253 3254 intel_ddi_disable_transcoder_func(old_crtc_state); 3255 3256 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3257 const struct intel_crtc_state *old_pipe_crtc_state = 3258 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3259 3260 intel_dsc_disable(old_pipe_crtc_state); 3261 3262 if (DISPLAY_VER(display) >= 9) 3263 skl_scaler_disable(old_pipe_crtc_state); 3264 else 3265 ilk_pfit_disable(old_pipe_crtc_state); 3266 } 3267 } 3268 3269 /* 3270 * Note: Also called from the ->post_disable of the last active MST stream 3271 * encoder on its primary encoder. See also the comment for 3272 * intel_ddi_pre_enable(). 3273 */ 3274 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3275 struct intel_encoder *encoder, 3276 const struct intel_crtc_state *old_crtc_state, 3277 const struct drm_connector_state *old_conn_state) 3278 { 3279 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3280 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3281 old_conn_state); 3282 3283 /* 3284 * When called from DP MST code: 3285 * - old_conn_state will be NULL 3286 * - encoder will be the main encoder (ie. mst->primary) 3287 * - the main connector associated with this port 3288 * won't be active or linked to a crtc 3289 * - old_crtc_state will be the state of the last stream to 3290 * be deactivated on this port, and it may not be the same 3291 * stream that was activated last, but each stream 3292 * should have a state that is identical when it comes to 3293 * the DP link parameters 3294 */ 3295 3296 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3297 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3298 old_conn_state); 3299 else 3300 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3301 old_conn_state); 3302 } 3303 3304 /* 3305 * Note: Also called from the ->post_pll_disable of the last active MST stream 3306 * encoder on its primary encoder. See also the comment for 3307 * intel_ddi_pre_enable(). 3308 */ 3309 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3310 struct intel_encoder *encoder, 3311 const struct intel_crtc_state *old_crtc_state, 3312 const struct drm_connector_state *old_conn_state) 3313 { 3314 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3315 3316 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3317 3318 if (intel_encoder_is_tc(encoder)) 3319 intel_tc_port_put_link(dig_port); 3320 } 3321 3322 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3323 struct intel_encoder *encoder, 3324 const struct intel_crtc_state *crtc_state) 3325 { 3326 const struct drm_connector_state *conn_state; 3327 struct drm_connector *conn; 3328 int i; 3329 3330 if (!crtc_state->sync_mode_slaves_mask) 3331 return; 3332 3333 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3334 struct intel_encoder *slave_encoder = 3335 to_intel_encoder(conn_state->best_encoder); 3336 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3337 const struct intel_crtc_state *slave_crtc_state; 3338 3339 if (!slave_crtc) 3340 continue; 3341 3342 slave_crtc_state = 3343 intel_atomic_get_new_crtc_state(state, slave_crtc); 3344 3345 if (slave_crtc_state->master_transcoder != 3346 crtc_state->cpu_transcoder) 3347 continue; 3348 3349 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3350 slave_crtc_state); 3351 } 3352 3353 usleep_range(200, 400); 3354 3355 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3356 crtc_state); 3357 } 3358 3359 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3360 struct intel_encoder *encoder, 3361 const struct intel_crtc_state *crtc_state, 3362 const struct drm_connector_state *conn_state) 3363 { 3364 struct intel_display *display = to_intel_display(encoder); 3365 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3366 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3367 enum port port = encoder->port; 3368 3369 if (port == PORT_A && DISPLAY_VER(display) < 9) 3370 intel_dp_stop_link_train(intel_dp, crtc_state); 3371 3372 drm_connector_update_privacy_screen(conn_state); 3373 intel_edp_backlight_on(crtc_state, conn_state); 3374 3375 intel_panel_prepare(crtc_state, conn_state); 3376 3377 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3378 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3379 3380 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3381 } 3382 3383 static i915_reg_t 3384 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3385 { 3386 static const enum transcoder trans[] = { 3387 [PORT_A] = TRANSCODER_EDP, 3388 [PORT_B] = TRANSCODER_A, 3389 [PORT_C] = TRANSCODER_B, 3390 [PORT_D] = TRANSCODER_C, 3391 [PORT_E] = TRANSCODER_A, 3392 }; 3393 3394 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3395 3396 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3397 port = PORT_A; 3398 3399 return CHICKEN_TRANS(display, trans[port]); 3400 } 3401 3402 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3403 struct intel_encoder *encoder, 3404 const struct intel_crtc_state *crtc_state, 3405 const struct drm_connector_state *conn_state) 3406 { 3407 struct intel_display *display = to_intel_display(encoder); 3408 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3409 struct drm_connector *connector = conn_state->connector; 3410 enum port port = encoder->port; 3411 u32 buf_ctl = 0; 3412 3413 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3414 crtc_state->hdmi_high_tmds_clock_ratio, 3415 crtc_state->hdmi_scrambling)) 3416 drm_dbg_kms(display->drm, 3417 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3418 connector->base.id, connector->name); 3419 3420 if (has_buf_trans_select(display)) 3421 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3422 3423 /* e. Enable D2D Link for C10/C20 Phy */ 3424 mtl_ddi_enable_d2d(encoder); 3425 3426 encoder->set_signal_levels(encoder, crtc_state); 3427 3428 /* Display WA #1143: skl,kbl,cfl */ 3429 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3430 /* 3431 * For some reason these chicken bits have been 3432 * stuffed into a transcoder register, event though 3433 * the bits affect a specific DDI port rather than 3434 * a specific transcoder. 3435 */ 3436 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3437 u32 val; 3438 3439 val = intel_de_read(display, reg); 3440 3441 if (port == PORT_E) 3442 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3443 DDIE_TRAINING_OVERRIDE_VALUE; 3444 else 3445 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3446 DDI_TRAINING_OVERRIDE_VALUE; 3447 3448 intel_de_write(display, reg, val); 3449 intel_de_posting_read(display, reg); 3450 3451 udelay(1); 3452 3453 if (port == PORT_E) 3454 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3455 DDIE_TRAINING_OVERRIDE_VALUE); 3456 else 3457 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3458 DDI_TRAINING_OVERRIDE_VALUE); 3459 3460 intel_de_write(display, reg, val); 3461 } 3462 3463 intel_ddi_power_up_lanes(encoder, crtc_state); 3464 3465 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3466 * are ignored so nothing special needs to be done besides 3467 * enabling the port. 3468 * 3469 * On ADL_P the PHY link rate and lane count must be programmed but 3470 * these are both 0 for HDMI. 3471 * 3472 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3473 * is filled with lane count, already set in the crtc_state. 3474 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3475 */ 3476 if (dig_port->lane_reversal) 3477 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3478 if (dig_port->ddi_a_4_lanes) 3479 buf_ctl |= DDI_A_4_LANES; 3480 3481 if (DISPLAY_VER(display) >= 14) { 3482 u32 port_buf = 0; 3483 3484 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3485 3486 if (dig_port->lane_reversal) 3487 port_buf |= XELPDP_PORT_REVERSAL; 3488 3489 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3490 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3491 3492 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3493 3494 if (DISPLAY_VER(display) >= 20) 3495 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3496 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3497 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3498 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3499 } 3500 3501 intel_ddi_buf_enable(encoder, buf_ctl); 3502 } 3503 3504 static void intel_ddi_enable(struct intel_atomic_state *state, 3505 struct intel_encoder *encoder, 3506 const struct intel_crtc_state *crtc_state, 3507 const struct drm_connector_state *conn_state) 3508 { 3509 struct intel_display *display = to_intel_display(encoder); 3510 struct intel_crtc *pipe_crtc; 3511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3512 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3513 int i; 3514 3515 /* 128b/132b SST */ 3516 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3517 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3518 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3519 3520 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3521 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3522 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3523 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3524 } 3525 3526 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3527 3528 intel_vrr_transcoder_enable(crtc_state); 3529 3530 /* 128b/132b SST */ 3531 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3532 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3533 3534 intel_ddi_clear_act_sent(encoder, crtc_state); 3535 3536 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3537 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3538 3539 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3540 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3541 } 3542 3543 intel_enable_transcoder(crtc_state); 3544 3545 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3546 3547 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3548 const struct intel_crtc_state *pipe_crtc_state = 3549 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3550 3551 intel_crtc_vblank_on(pipe_crtc_state); 3552 } 3553 3554 if (is_hdmi) 3555 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3556 else 3557 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3558 3559 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3560 3561 } 3562 3563 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3564 struct intel_encoder *encoder, 3565 const struct intel_crtc_state *old_crtc_state, 3566 const struct drm_connector_state *old_conn_state) 3567 { 3568 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3569 struct intel_connector *connector = 3570 to_intel_connector(old_conn_state->connector); 3571 3572 intel_dp->link.active = false; 3573 3574 intel_panel_unprepare(old_conn_state); 3575 intel_psr_disable(intel_dp, old_crtc_state); 3576 intel_alpm_disable(intel_dp); 3577 intel_edp_backlight_off(old_conn_state); 3578 /* Disable the decompression in DP Sink */ 3579 intel_dp_sink_disable_decompression(state, 3580 connector, old_crtc_state); 3581 /* Disable Ignore_MSA bit in DP Sink */ 3582 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3583 false); 3584 } 3585 3586 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3587 struct intel_encoder *encoder, 3588 const struct intel_crtc_state *old_crtc_state, 3589 const struct drm_connector_state *old_conn_state) 3590 { 3591 struct intel_display *display = to_intel_display(encoder); 3592 struct drm_connector *connector = old_conn_state->connector; 3593 3594 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3595 false, false)) 3596 drm_dbg_kms(display->drm, 3597 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3598 connector->base.id, connector->name); 3599 } 3600 3601 static void intel_ddi_disable(struct intel_atomic_state *state, 3602 struct intel_encoder *encoder, 3603 const struct intel_crtc_state *old_crtc_state, 3604 const struct drm_connector_state *old_conn_state) 3605 { 3606 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3607 3608 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3609 3610 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3611 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3612 old_conn_state); 3613 else 3614 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3615 old_conn_state); 3616 } 3617 3618 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3619 struct intel_encoder *encoder, 3620 const struct intel_crtc_state *crtc_state, 3621 const struct drm_connector_state *conn_state) 3622 { 3623 intel_ddi_set_dp_msa(crtc_state, conn_state); 3624 3625 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3626 3627 intel_backlight_update(state, encoder, crtc_state, conn_state); 3628 drm_connector_update_privacy_screen(conn_state); 3629 } 3630 3631 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3632 const struct intel_crtc_state *crtc_state, 3633 const struct drm_connector_state *conn_state) 3634 { 3635 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3636 } 3637 3638 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3639 struct intel_encoder *encoder, 3640 const struct intel_crtc_state *crtc_state, 3641 const struct drm_connector_state *conn_state) 3642 { 3643 3644 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3645 !intel_encoder_is_mst(encoder)) 3646 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3647 conn_state); 3648 3649 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3650 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3651 conn_state); 3652 3653 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3654 } 3655 3656 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3657 struct intel_encoder *encoder, 3658 struct intel_crtc *crtc) 3659 { 3660 struct intel_display *display = to_intel_display(encoder); 3661 const struct intel_crtc_state *crtc_state = 3662 intel_atomic_get_new_crtc_state(state, crtc); 3663 struct intel_crtc *pipe_crtc; 3664 3665 /* FIXME: Add MTL pll_mgr */ 3666 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3667 return; 3668 3669 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3670 intel_crtc_joined_pipe_mask(crtc_state)) 3671 intel_dpll_update_active(state, pipe_crtc, encoder); 3672 } 3673 3674 /* 3675 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3676 * encoder on its primary encoder. See also the comment for 3677 * intel_ddi_pre_enable(). 3678 */ 3679 static void 3680 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3681 struct intel_encoder *encoder, 3682 const struct intel_crtc_state *crtc_state, 3683 const struct drm_connector_state *conn_state) 3684 { 3685 struct intel_display *display = to_intel_display(encoder); 3686 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3687 bool is_tc_port = intel_encoder_is_tc(encoder); 3688 3689 if (is_tc_port) { 3690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3691 3692 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3693 intel_ddi_update_active_dpll(state, encoder, crtc); 3694 } 3695 3696 main_link_aux_power_domain_get(dig_port, crtc_state); 3697 3698 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3699 /* 3700 * Program the lane count for static/dynamic connections on 3701 * Type-C ports. Skip this step for TBT. 3702 */ 3703 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3704 else if (display->platform.geminilake || display->platform.broxton) 3705 bxt_dpio_phy_set_lane_optim_mask(encoder, 3706 crtc_state->lane_lat_optim_mask); 3707 } 3708 3709 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3710 { 3711 struct intel_display *display = to_intel_display(encoder); 3712 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3713 int ln; 3714 3715 for (ln = 0; ln < 2; ln++) 3716 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3717 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3718 } 3719 3720 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3721 const struct intel_crtc_state *crtc_state) 3722 { 3723 struct intel_display *display = to_intel_display(crtc_state); 3724 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3725 struct intel_encoder *encoder = &dig_port->base; 3726 u32 dp_tp_ctl; 3727 3728 /* 3729 * TODO: To train with only a different voltage swing entry is not 3730 * necessary disable and enable port 3731 */ 3732 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3733 3734 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3735 3736 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3737 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3738 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3739 intel_dp_is_uhbr(crtc_state)) { 3740 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3741 } else { 3742 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3743 if (crtc_state->enhanced_framing) 3744 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3745 } 3746 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3747 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3748 3749 /* 6.f Enable D2D Link */ 3750 mtl_ddi_enable_d2d(encoder); 3751 3752 /* 6.g Configure voltage swing and related IO settings */ 3753 encoder->set_signal_levels(encoder, crtc_state); 3754 3755 /* 6.h Configure PORT_BUF_CTL1 */ 3756 mtl_port_buf_ctl_program(encoder, crtc_state); 3757 3758 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3759 if (DISPLAY_VER(display) >= 20) 3760 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3761 3762 intel_ddi_buf_enable(encoder, intel_dp->DP); 3763 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3764 3765 /* 3766 * 6.k If AUX-Less ALPM is going to be enabled: 3767 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3768 */ 3769 intel_alpm_port_configure(intel_dp, crtc_state); 3770 3771 /* 3772 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3773 * register 3774 */ 3775 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3776 } 3777 3778 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3779 const struct intel_crtc_state *crtc_state) 3780 { 3781 struct intel_display *display = to_intel_display(intel_dp); 3782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3783 struct intel_encoder *encoder = &dig_port->base; 3784 u32 dp_tp_ctl; 3785 3786 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3787 3788 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3789 3790 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3791 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3792 intel_dp_is_uhbr(crtc_state)) { 3793 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3794 } else { 3795 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3796 if (crtc_state->enhanced_framing) 3797 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3798 } 3799 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3800 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3801 3802 if (display->platform.alderlake_p && 3803 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3804 adlp_tbt_to_dp_alt_switch_wa(encoder); 3805 3806 intel_ddi_buf_enable(encoder, intel_dp->DP); 3807 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3808 } 3809 3810 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3811 const struct intel_crtc_state *crtc_state, 3812 u8 dp_train_pat) 3813 { 3814 struct intel_display *display = to_intel_display(intel_dp); 3815 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3816 u32 temp; 3817 3818 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3819 3820 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3821 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3822 case DP_TRAINING_PATTERN_DISABLE: 3823 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3824 break; 3825 case DP_TRAINING_PATTERN_1: 3826 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3827 break; 3828 case DP_TRAINING_PATTERN_2: 3829 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3830 break; 3831 case DP_TRAINING_PATTERN_3: 3832 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3833 break; 3834 case DP_TRAINING_PATTERN_4: 3835 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3836 break; 3837 } 3838 3839 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3840 } 3841 3842 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3843 const struct intel_crtc_state *crtc_state) 3844 { 3845 struct intel_display *display = to_intel_display(intel_dp); 3846 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3847 enum port port = encoder->port; 3848 3849 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3850 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3851 3852 /* 3853 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3854 * reason we need to set idle transmission mode is to work around a HW 3855 * issue where we enable the pipe while not in idle link-training mode. 3856 * In this case there is requirement to wait for a minimum number of 3857 * idle patterns to be sent. 3858 */ 3859 if (port == PORT_A && DISPLAY_VER(display) < 12) 3860 return; 3861 3862 if (intel_de_wait_for_set(display, 3863 dp_tp_status_reg(encoder, crtc_state), 3864 DP_TP_STATUS_IDLE_DONE, 2)) 3865 drm_err(display->drm, 3866 "Timed out waiting for DP idle patterns\n"); 3867 } 3868 3869 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3870 enum transcoder cpu_transcoder) 3871 { 3872 if (cpu_transcoder == TRANSCODER_EDP) 3873 return false; 3874 3875 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3876 return false; 3877 3878 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3879 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3880 } 3881 3882 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3883 { 3884 if (crtc_state->port_clock > 594000) 3885 return 2; 3886 else 3887 return 0; 3888 } 3889 3890 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3891 { 3892 if (crtc_state->port_clock > 594000) 3893 return 3; 3894 else 3895 return 0; 3896 } 3897 3898 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3899 { 3900 if (crtc_state->port_clock > 594000) 3901 return 1; 3902 else 3903 return 0; 3904 } 3905 3906 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3907 { 3908 struct intel_display *display = to_intel_display(crtc_state); 3909 3910 if (DISPLAY_VER(display) >= 14) 3911 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3912 else if (DISPLAY_VER(display) >= 12) 3913 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3914 else if (display->platform.jasperlake || display->platform.elkhartlake) 3915 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3916 else if (DISPLAY_VER(display) >= 11) 3917 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3918 } 3919 3920 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3921 enum transcoder cpu_transcoder) 3922 { 3923 u32 master_select; 3924 3925 if (DISPLAY_VER(display) >= 11) { 3926 u32 ctl2 = intel_de_read(display, 3927 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3928 3929 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3930 return INVALID_TRANSCODER; 3931 3932 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3933 } else { 3934 u32 ctl = intel_de_read(display, 3935 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3936 3937 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3938 return INVALID_TRANSCODER; 3939 3940 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3941 } 3942 3943 if (master_select == 0) 3944 return TRANSCODER_EDP; 3945 else 3946 return master_select - 1; 3947 } 3948 3949 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3950 { 3951 struct intel_display *display = to_intel_display(crtc_state); 3952 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3953 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3954 enum transcoder cpu_transcoder; 3955 3956 crtc_state->master_transcoder = 3957 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3958 3959 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3960 enum intel_display_power_domain power_domain; 3961 intel_wakeref_t trans_wakeref; 3962 3963 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3964 trans_wakeref = intel_display_power_get_if_enabled(display, 3965 power_domain); 3966 3967 if (!trans_wakeref) 3968 continue; 3969 3970 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3971 crtc_state->cpu_transcoder) 3972 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3973 3974 intel_display_power_put(display, power_domain, trans_wakeref); 3975 } 3976 3977 drm_WARN_ON(display->drm, 3978 crtc_state->master_transcoder != INVALID_TRANSCODER && 3979 crtc_state->sync_mode_slaves_mask); 3980 } 3981 3982 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3983 struct intel_crtc_state *crtc_state, 3984 u32 ddi_func_ctl) 3985 { 3986 struct intel_display *display = to_intel_display(encoder); 3987 3988 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3989 if (DISPLAY_VER(display) >= 14) 3990 crtc_state->lane_count = 3991 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3992 else 3993 crtc_state->lane_count = 4; 3994 } 3995 3996 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3997 struct intel_crtc_state *crtc_state, 3998 u32 ddi_func_ctl) 3999 { 4000 crtc_state->has_hdmi_sink = true; 4001 4002 crtc_state->infoframes.enable |= 4003 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4004 4005 if (crtc_state->infoframes.enable) 4006 crtc_state->has_infoframe = true; 4007 4008 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4009 crtc_state->hdmi_scrambling = true; 4010 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4011 crtc_state->hdmi_high_tmds_clock_ratio = true; 4012 4013 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4014 } 4015 4016 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4017 struct intel_crtc_state *crtc_state, 4018 u32 ddi_func_ctl) 4019 { 4020 struct intel_display *display = to_intel_display(encoder); 4021 4022 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4023 crtc_state->enhanced_framing = 4024 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4025 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4026 } 4027 4028 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4029 struct intel_crtc_state *crtc_state, 4030 u32 ddi_func_ctl) 4031 { 4032 struct intel_display *display = to_intel_display(encoder); 4033 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4034 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4035 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4036 4037 if (encoder->type == INTEL_OUTPUT_EDP) 4038 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4039 else 4040 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4041 crtc_state->lane_count = 4042 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4043 4044 if (DISPLAY_VER(display) >= 12 && 4045 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4046 crtc_state->mst_master_transcoder = 4047 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4048 4049 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4050 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4051 4052 crtc_state->enhanced_framing = 4053 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4054 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4055 4056 if (DISPLAY_VER(display) >= 11) 4057 crtc_state->fec_enable = 4058 intel_de_read(display, 4059 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4060 4061 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4062 crtc_state->infoframes.enable |= 4063 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4064 else 4065 crtc_state->infoframes.enable |= 4066 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4067 } 4068 4069 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4070 struct intel_crtc_state *crtc_state, 4071 u32 ddi_func_ctl) 4072 { 4073 struct intel_display *display = to_intel_display(encoder); 4074 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4075 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4076 4077 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4078 crtc_state->lane_count = 4079 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4080 4081 if (DISPLAY_VER(display) >= 12) 4082 crtc_state->mst_master_transcoder = 4083 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4084 4085 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4086 4087 if (DISPLAY_VER(display) >= 11) 4088 crtc_state->fec_enable = 4089 intel_de_read(display, 4090 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4091 4092 crtc_state->infoframes.enable |= 4093 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4094 } 4095 4096 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4097 struct intel_crtc_state *pipe_config) 4098 { 4099 struct intel_display *display = to_intel_display(encoder); 4100 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4101 u32 ddi_func_ctl, ddi_mode, flags = 0; 4102 4103 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4104 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4105 flags |= DRM_MODE_FLAG_PHSYNC; 4106 else 4107 flags |= DRM_MODE_FLAG_NHSYNC; 4108 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4109 flags |= DRM_MODE_FLAG_PVSYNC; 4110 else 4111 flags |= DRM_MODE_FLAG_NVSYNC; 4112 4113 pipe_config->hw.adjusted_mode.flags |= flags; 4114 4115 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4116 case TRANS_DDI_BPC_6: 4117 pipe_config->pipe_bpp = 18; 4118 break; 4119 case TRANS_DDI_BPC_8: 4120 pipe_config->pipe_bpp = 24; 4121 break; 4122 case TRANS_DDI_BPC_10: 4123 pipe_config->pipe_bpp = 30; 4124 break; 4125 case TRANS_DDI_BPC_12: 4126 pipe_config->pipe_bpp = 36; 4127 break; 4128 default: 4129 break; 4130 } 4131 4132 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4133 4134 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4135 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4136 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4137 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4138 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4139 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4140 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4141 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4142 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4143 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4144 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4145 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4146 4147 /* 4148 * If this is true, we know we're being called from mst stream 4149 * encoder's ->get_config(). 4150 */ 4151 if (intel_dp_mst_active_streams(intel_dp)) 4152 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4153 else 4154 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4155 } 4156 } 4157 4158 /* 4159 * Note: Also called from the ->get_config of the MST stream encoders on their 4160 * primary encoder, via the platform specific hooks here. See also the comment 4161 * for intel_ddi_pre_enable(). 4162 */ 4163 static void intel_ddi_get_config(struct intel_encoder *encoder, 4164 struct intel_crtc_state *pipe_config) 4165 { 4166 struct intel_display *display = to_intel_display(encoder); 4167 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4168 4169 /* XXX: DSI transcoder paranoia */ 4170 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4171 return; 4172 4173 intel_ddi_read_func_ctl(encoder, pipe_config); 4174 4175 intel_ddi_mso_get_config(encoder, pipe_config); 4176 4177 pipe_config->has_audio = 4178 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4179 4180 if (encoder->type == INTEL_OUTPUT_EDP) 4181 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4182 4183 ddi_dotclock_get(pipe_config); 4184 4185 if (display->platform.geminilake || display->platform.broxton) 4186 pipe_config->lane_lat_optim_mask = 4187 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4188 4189 intel_ddi_compute_min_voltage_level(pipe_config); 4190 4191 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4192 4193 intel_read_infoframe(encoder, pipe_config, 4194 HDMI_INFOFRAME_TYPE_AVI, 4195 &pipe_config->infoframes.avi); 4196 intel_read_infoframe(encoder, pipe_config, 4197 HDMI_INFOFRAME_TYPE_SPD, 4198 &pipe_config->infoframes.spd); 4199 intel_read_infoframe(encoder, pipe_config, 4200 HDMI_INFOFRAME_TYPE_VENDOR, 4201 &pipe_config->infoframes.hdmi); 4202 intel_read_infoframe(encoder, pipe_config, 4203 HDMI_INFOFRAME_TYPE_DRM, 4204 &pipe_config->infoframes.drm); 4205 4206 if (DISPLAY_VER(display) >= 8) 4207 bdw_get_trans_port_sync_config(pipe_config); 4208 4209 intel_psr_get_config(encoder, pipe_config); 4210 4211 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4212 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4213 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4214 4215 intel_audio_codec_get_config(encoder, pipe_config); 4216 } 4217 4218 void intel_ddi_get_clock(struct intel_encoder *encoder, 4219 struct intel_crtc_state *crtc_state, 4220 struct intel_dpll *pll) 4221 { 4222 struct intel_display *display = to_intel_display(encoder); 4223 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4224 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4225 bool pll_active; 4226 4227 if (drm_WARN_ON(display->drm, !pll)) 4228 return; 4229 4230 port_dpll->pll = pll; 4231 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4232 drm_WARN_ON(display->drm, !pll_active); 4233 4234 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4235 4236 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4237 &crtc_state->dpll_hw_state); 4238 } 4239 4240 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4241 struct intel_crtc_state *crtc_state) 4242 { 4243 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4244 4245 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4246 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4247 else 4248 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4249 4250 intel_ddi_get_config(encoder, crtc_state); 4251 } 4252 4253 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4254 struct intel_crtc_state *crtc_state) 4255 { 4256 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4257 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4258 4259 intel_ddi_get_config(encoder, crtc_state); 4260 } 4261 4262 static void adls_ddi_get_config(struct intel_encoder *encoder, 4263 struct intel_crtc_state *crtc_state) 4264 { 4265 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4266 intel_ddi_get_config(encoder, crtc_state); 4267 } 4268 4269 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4270 struct intel_crtc_state *crtc_state) 4271 { 4272 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4273 intel_ddi_get_config(encoder, crtc_state); 4274 } 4275 4276 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4277 struct intel_crtc_state *crtc_state) 4278 { 4279 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4280 intel_ddi_get_config(encoder, crtc_state); 4281 } 4282 4283 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4284 struct intel_crtc_state *crtc_state) 4285 { 4286 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4287 intel_ddi_get_config(encoder, crtc_state); 4288 } 4289 4290 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4291 { 4292 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4293 } 4294 4295 static enum icl_port_dpll_id 4296 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4297 const struct intel_crtc_state *crtc_state) 4298 { 4299 struct intel_display *display = to_intel_display(encoder); 4300 const struct intel_dpll *pll = crtc_state->intel_dpll; 4301 4302 if (drm_WARN_ON(display->drm, !pll)) 4303 return ICL_PORT_DPLL_DEFAULT; 4304 4305 if (icl_ddi_tc_pll_is_tbt(pll)) 4306 return ICL_PORT_DPLL_DEFAULT; 4307 else 4308 return ICL_PORT_DPLL_MG_PHY; 4309 } 4310 4311 enum icl_port_dpll_id 4312 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4313 const struct intel_crtc_state *crtc_state) 4314 { 4315 if (!encoder->port_pll_type) 4316 return ICL_PORT_DPLL_DEFAULT; 4317 4318 return encoder->port_pll_type(encoder, crtc_state); 4319 } 4320 4321 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4322 struct intel_crtc_state *crtc_state, 4323 struct intel_dpll *pll) 4324 { 4325 struct intel_display *display = to_intel_display(encoder); 4326 enum icl_port_dpll_id port_dpll_id; 4327 struct icl_port_dpll *port_dpll; 4328 bool pll_active; 4329 4330 if (drm_WARN_ON(display->drm, !pll)) 4331 return; 4332 4333 if (icl_ddi_tc_pll_is_tbt(pll)) 4334 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4335 else 4336 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4337 4338 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4339 4340 port_dpll->pll = pll; 4341 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4342 drm_WARN_ON(display->drm, !pll_active); 4343 4344 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4345 4346 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4347 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4348 else 4349 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4350 &crtc_state->dpll_hw_state); 4351 } 4352 4353 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4354 struct intel_crtc_state *crtc_state) 4355 { 4356 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4357 intel_ddi_get_config(encoder, crtc_state); 4358 } 4359 4360 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4361 struct intel_crtc_state *crtc_state) 4362 { 4363 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4364 intel_ddi_get_config(encoder, crtc_state); 4365 } 4366 4367 static void skl_ddi_get_config(struct intel_encoder *encoder, 4368 struct intel_crtc_state *crtc_state) 4369 { 4370 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4371 intel_ddi_get_config(encoder, crtc_state); 4372 } 4373 4374 void hsw_ddi_get_config(struct intel_encoder *encoder, 4375 struct intel_crtc_state *crtc_state) 4376 { 4377 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4378 intel_ddi_get_config(encoder, crtc_state); 4379 } 4380 4381 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4382 const struct intel_crtc_state *crtc_state) 4383 { 4384 if (intel_encoder_is_tc(encoder)) 4385 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4386 crtc_state); 4387 4388 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4389 (!crtc_state && intel_encoder_is_dp(encoder))) 4390 intel_dp_sync_state(encoder, crtc_state); 4391 } 4392 4393 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4394 struct intel_crtc_state *crtc_state) 4395 { 4396 struct intel_display *display = to_intel_display(encoder); 4397 bool fastset = true; 4398 4399 if (intel_encoder_is_tc(encoder)) { 4400 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4401 encoder->base.base.id, encoder->base.name); 4402 crtc_state->uapi.mode_changed = true; 4403 fastset = false; 4404 } 4405 4406 if (intel_crtc_has_dp_encoder(crtc_state) && 4407 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4408 fastset = false; 4409 4410 return fastset; 4411 } 4412 4413 static enum intel_output_type 4414 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4415 struct intel_crtc_state *crtc_state, 4416 struct drm_connector_state *conn_state) 4417 { 4418 switch (conn_state->connector->connector_type) { 4419 case DRM_MODE_CONNECTOR_HDMIA: 4420 return INTEL_OUTPUT_HDMI; 4421 case DRM_MODE_CONNECTOR_eDP: 4422 return INTEL_OUTPUT_EDP; 4423 case DRM_MODE_CONNECTOR_DisplayPort: 4424 return INTEL_OUTPUT_DP; 4425 default: 4426 MISSING_CASE(conn_state->connector->connector_type); 4427 return INTEL_OUTPUT_UNUSED; 4428 } 4429 } 4430 4431 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4432 struct intel_crtc_state *pipe_config, 4433 struct drm_connector_state *conn_state) 4434 { 4435 struct intel_display *display = to_intel_display(encoder); 4436 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4437 enum port port = encoder->port; 4438 int ret; 4439 4440 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4441 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4442 4443 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4444 pipe_config->has_hdmi_sink = 4445 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4446 4447 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4448 } else { 4449 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4450 } 4451 4452 if (ret) 4453 return ret; 4454 4455 if (display->platform.haswell && crtc->pipe == PIPE_A && 4456 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4457 pipe_config->pch_pfit.force_thru = 4458 pipe_config->pch_pfit.enabled || 4459 pipe_config->crc_enabled; 4460 4461 if (display->platform.geminilake || display->platform.broxton) 4462 pipe_config->lane_lat_optim_mask = 4463 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4464 4465 intel_ddi_compute_min_voltage_level(pipe_config); 4466 4467 return 0; 4468 } 4469 4470 static bool mode_equal(const struct drm_display_mode *mode1, 4471 const struct drm_display_mode *mode2) 4472 { 4473 return drm_mode_match(mode1, mode2, 4474 DRM_MODE_MATCH_TIMINGS | 4475 DRM_MODE_MATCH_FLAGS | 4476 DRM_MODE_MATCH_3D_FLAGS) && 4477 mode1->clock == mode2->clock; /* we want an exact match */ 4478 } 4479 4480 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4481 const struct intel_link_m_n *m_n_2) 4482 { 4483 return m_n_1->tu == m_n_2->tu && 4484 m_n_1->data_m == m_n_2->data_m && 4485 m_n_1->data_n == m_n_2->data_n && 4486 m_n_1->link_m == m_n_2->link_m && 4487 m_n_1->link_n == m_n_2->link_n; 4488 } 4489 4490 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4491 const struct intel_crtc_state *crtc_state2) 4492 { 4493 /* 4494 * FIXME the modeset sequence is currently wrong and 4495 * can't deal with joiner + port sync at the same time. 4496 */ 4497 return crtc_state1->hw.active && crtc_state2->hw.active && 4498 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4499 crtc_state1->output_types == crtc_state2->output_types && 4500 crtc_state1->output_format == crtc_state2->output_format && 4501 crtc_state1->lane_count == crtc_state2->lane_count && 4502 crtc_state1->port_clock == crtc_state2->port_clock && 4503 mode_equal(&crtc_state1->hw.adjusted_mode, 4504 &crtc_state2->hw.adjusted_mode) && 4505 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4506 } 4507 4508 static u8 4509 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4510 int tile_group_id) 4511 { 4512 struct intel_display *display = to_intel_display(ref_crtc_state); 4513 struct drm_connector *connector; 4514 const struct drm_connector_state *conn_state; 4515 struct intel_atomic_state *state = 4516 to_intel_atomic_state(ref_crtc_state->uapi.state); 4517 u8 transcoders = 0; 4518 int i; 4519 4520 /* 4521 * We don't enable port sync on BDW due to missing w/as and 4522 * due to not having adjusted the modeset sequence appropriately. 4523 */ 4524 if (DISPLAY_VER(display) < 9) 4525 return 0; 4526 4527 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4528 return 0; 4529 4530 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4531 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4532 const struct intel_crtc_state *crtc_state; 4533 4534 if (!crtc) 4535 continue; 4536 4537 if (!connector->has_tile || 4538 connector->tile_group->id != 4539 tile_group_id) 4540 continue; 4541 crtc_state = intel_atomic_get_new_crtc_state(state, 4542 crtc); 4543 if (!crtcs_port_sync_compatible(ref_crtc_state, 4544 crtc_state)) 4545 continue; 4546 transcoders |= BIT(crtc_state->cpu_transcoder); 4547 } 4548 4549 return transcoders; 4550 } 4551 4552 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4553 struct intel_crtc_state *crtc_state, 4554 struct drm_connector_state *conn_state) 4555 { 4556 struct intel_display *display = to_intel_display(encoder); 4557 struct drm_connector *connector = conn_state->connector; 4558 u8 port_sync_transcoders = 0; 4559 4560 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4561 encoder->base.base.id, encoder->base.name, 4562 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4563 4564 if (connector->has_tile) 4565 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4566 connector->tile_group->id); 4567 4568 /* 4569 * EDP Transcoders cannot be ensalved 4570 * make them a master always when present 4571 */ 4572 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4573 crtc_state->master_transcoder = TRANSCODER_EDP; 4574 else 4575 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4576 4577 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4578 crtc_state->master_transcoder = INVALID_TRANSCODER; 4579 crtc_state->sync_mode_slaves_mask = 4580 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4581 } 4582 4583 return 0; 4584 } 4585 4586 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4587 { 4588 struct intel_display *display = to_intel_display(encoder->dev); 4589 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4590 4591 intel_dp_encoder_flush_work(encoder); 4592 if (intel_encoder_is_tc(&dig_port->base)) 4593 intel_tc_port_cleanup(dig_port); 4594 intel_display_power_flush_work(display); 4595 4596 drm_encoder_cleanup(encoder); 4597 kfree(dig_port->hdcp.port_data.streams); 4598 kfree(dig_port); 4599 } 4600 4601 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4602 { 4603 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4604 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4605 4606 intel_dp->reset_link_params = true; 4607 intel_dp_invalidate_source_oui(intel_dp); 4608 4609 intel_pps_encoder_reset(intel_dp); 4610 4611 if (intel_encoder_is_tc(&dig_port->base)) 4612 intel_tc_port_init_mode(dig_port); 4613 } 4614 4615 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4616 { 4617 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4618 4619 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4620 4621 return 0; 4622 } 4623 4624 static const struct drm_encoder_funcs intel_ddi_funcs = { 4625 .reset = intel_ddi_encoder_reset, 4626 .destroy = intel_ddi_encoder_destroy, 4627 .late_register = intel_ddi_encoder_late_register, 4628 }; 4629 4630 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4631 { 4632 struct intel_display *display = to_intel_display(dig_port); 4633 struct intel_connector *connector; 4634 enum port port = dig_port->base.port; 4635 4636 connector = intel_connector_alloc(); 4637 if (!connector) 4638 return -ENOMEM; 4639 4640 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4641 if (DISPLAY_VER(display) >= 14) 4642 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4643 else 4644 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4645 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4646 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4647 4648 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4649 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4650 4651 if (!intel_dp_init_connector(dig_port, connector)) { 4652 kfree(connector); 4653 return -EINVAL; 4654 } 4655 4656 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4657 struct drm_privacy_screen *privacy_screen; 4658 4659 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4660 if (!IS_ERR(privacy_screen)) { 4661 drm_connector_attach_privacy_screen_provider(&connector->base, 4662 privacy_screen); 4663 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4664 drm_warn(display->drm, "Error getting privacy-screen\n"); 4665 } 4666 } 4667 4668 return 0; 4669 } 4670 4671 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4672 struct drm_modeset_acquire_ctx *ctx) 4673 { 4674 struct intel_display *display = to_intel_display(encoder); 4675 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4676 struct intel_connector *connector = hdmi->attached_connector; 4677 struct i2c_adapter *ddc = connector->base.ddc; 4678 struct drm_connector_state *conn_state; 4679 struct intel_crtc_state *crtc_state; 4680 struct intel_crtc *crtc; 4681 u8 config; 4682 int ret; 4683 4684 if (connector->base.status != connector_status_connected) 4685 return 0; 4686 4687 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4688 ctx); 4689 if (ret) 4690 return ret; 4691 4692 conn_state = connector->base.state; 4693 4694 crtc = to_intel_crtc(conn_state->crtc); 4695 if (!crtc) 4696 return 0; 4697 4698 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4699 if (ret) 4700 return ret; 4701 4702 crtc_state = to_intel_crtc_state(crtc->base.state); 4703 4704 drm_WARN_ON(display->drm, 4705 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4706 4707 if (!crtc_state->hw.active) 4708 return 0; 4709 4710 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4711 !crtc_state->hdmi_scrambling) 4712 return 0; 4713 4714 if (conn_state->commit && 4715 !try_wait_for_completion(&conn_state->commit->hw_done)) 4716 return 0; 4717 4718 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4719 if (ret < 0) { 4720 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4721 connector->base.base.id, connector->base.name, ret); 4722 return 0; 4723 } 4724 4725 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4726 crtc_state->hdmi_high_tmds_clock_ratio && 4727 !!(config & SCDC_SCRAMBLING_ENABLE) == 4728 crtc_state->hdmi_scrambling) 4729 return 0; 4730 4731 /* 4732 * HDMI 2.0 says that one should not send scrambled data 4733 * prior to configuring the sink scrambling, and that 4734 * TMDS clock/data transmission should be suspended when 4735 * changing the TMDS clock rate in the sink. So let's 4736 * just do a full modeset here, even though some sinks 4737 * would be perfectly happy if were to just reconfigure 4738 * the SCDC settings on the fly. 4739 */ 4740 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4741 } 4742 4743 static void intel_ddi_link_check(struct intel_encoder *encoder) 4744 { 4745 struct intel_display *display = to_intel_display(encoder); 4746 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4747 4748 /* TODO: Move checking the HDMI link state here as well. */ 4749 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4750 4751 intel_dp_link_check(encoder); 4752 } 4753 4754 static enum intel_hotplug_state 4755 intel_ddi_hotplug(struct intel_encoder *encoder, 4756 struct intel_connector *connector) 4757 { 4758 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4759 struct intel_dp *intel_dp = &dig_port->dp; 4760 bool is_tc = intel_encoder_is_tc(encoder); 4761 struct drm_modeset_acquire_ctx ctx; 4762 enum intel_hotplug_state state; 4763 int ret; 4764 4765 if (intel_dp_test_phy(intel_dp)) 4766 return INTEL_HOTPLUG_UNCHANGED; 4767 4768 state = intel_encoder_hotplug(encoder, connector); 4769 4770 if (!intel_tc_port_link_reset(dig_port)) { 4771 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4772 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4773 ret = intel_hdmi_reset_link(encoder, &ctx); 4774 drm_WARN_ON(encoder->base.dev, ret); 4775 } else { 4776 intel_dp_check_link_state(intel_dp); 4777 } 4778 } 4779 4780 /* 4781 * Unpowered type-c dongles can take some time to boot and be 4782 * responsible, so here giving some time to those dongles to power up 4783 * and then retrying the probe. 4784 * 4785 * On many platforms the HDMI live state signal is known to be 4786 * unreliable, so we can't use it to detect if a sink is connected or 4787 * not. Instead we detect if it's connected based on whether we can 4788 * read the EDID or not. That in turn has a problem during disconnect, 4789 * since the HPD interrupt may be raised before the DDC lines get 4790 * disconnected (due to how the required length of DDC vs. HPD 4791 * connector pins are specified) and so we'll still be able to get a 4792 * valid EDID. To solve this schedule another detection cycle if this 4793 * time around we didn't detect any change in the sink's connection 4794 * status. 4795 * 4796 * Type-c connectors which get their HPD signal deasserted then 4797 * reasserted, without unplugging/replugging the sink from the 4798 * connector, introduce a delay until the AUX channel communication 4799 * becomes functional. Retry the detection for 5 seconds on type-c 4800 * connectors to account for this delay. 4801 */ 4802 if (state == INTEL_HOTPLUG_UNCHANGED && 4803 connector->hotplug_retries < (is_tc ? 5 : 1) && 4804 !dig_port->dp.is_mst) 4805 state = INTEL_HOTPLUG_RETRY; 4806 4807 return state; 4808 } 4809 4810 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4811 { 4812 struct intel_display *display = to_intel_display(encoder); 4813 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4814 4815 return intel_de_read(display, SDEISR) & bit; 4816 } 4817 4818 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4819 { 4820 struct intel_display *display = to_intel_display(encoder); 4821 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4822 4823 return intel_de_read(display, DEISR) & bit; 4824 } 4825 4826 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4827 { 4828 struct intel_display *display = to_intel_display(encoder); 4829 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4830 4831 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4832 } 4833 4834 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4835 { 4836 struct intel_connector *connector; 4837 enum port port = dig_port->base.port; 4838 4839 connector = intel_connector_alloc(); 4840 if (!connector) 4841 return -ENOMEM; 4842 4843 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4844 4845 if (!intel_hdmi_init_connector(dig_port, connector)) { 4846 /* 4847 * HDMI connector init failures may just mean conflicting DDC 4848 * pins or not having enough lanes. Handle them gracefully, but 4849 * don't fail the entire DDI init. 4850 */ 4851 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4852 kfree(connector); 4853 } 4854 4855 return 0; 4856 } 4857 4858 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4859 { 4860 struct intel_display *display = to_intel_display(dig_port); 4861 4862 if (dig_port->base.port != PORT_A) 4863 return false; 4864 4865 if (dig_port->ddi_a_4_lanes) 4866 return false; 4867 4868 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4869 * supported configuration 4870 */ 4871 if (display->platform.geminilake || display->platform.broxton) 4872 return true; 4873 4874 return false; 4875 } 4876 4877 static int 4878 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4879 { 4880 struct intel_display *display = to_intel_display(dig_port); 4881 enum port port = dig_port->base.port; 4882 int max_lanes = 4; 4883 4884 if (DISPLAY_VER(display) >= 11) 4885 return max_lanes; 4886 4887 if (port == PORT_A || port == PORT_E) { 4888 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4889 max_lanes = port == PORT_A ? 4 : 0; 4890 else 4891 /* Both A and E share 2 lanes */ 4892 max_lanes = 2; 4893 } 4894 4895 /* 4896 * Some BIOS might fail to set this bit on port A if eDP 4897 * wasn't lit up at boot. Force this bit set when needed 4898 * so we use the proper lane count for our calculations. 4899 */ 4900 if (intel_ddi_a_force_4_lanes(dig_port)) { 4901 drm_dbg_kms(display->drm, 4902 "Forcing DDI_A_4_LANES for port A\n"); 4903 dig_port->ddi_a_4_lanes = true; 4904 max_lanes = 4; 4905 } 4906 4907 return max_lanes; 4908 } 4909 4910 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4911 { 4912 if (port >= PORT_D_XELPD) 4913 return HPD_PORT_D + port - PORT_D_XELPD; 4914 else if (port >= PORT_TC1) 4915 return HPD_PORT_TC1 + port - PORT_TC1; 4916 else 4917 return HPD_PORT_A + port - PORT_A; 4918 } 4919 4920 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4921 { 4922 if (port >= PORT_TC1) 4923 return HPD_PORT_C + port - PORT_TC1; 4924 else 4925 return HPD_PORT_A + port - PORT_A; 4926 } 4927 4928 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4929 { 4930 if (port >= PORT_TC1) 4931 return HPD_PORT_TC1 + port - PORT_TC1; 4932 else 4933 return HPD_PORT_A + port - PORT_A; 4934 } 4935 4936 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4937 { 4938 if (HAS_PCH_TGP(display)) 4939 return tgl_hpd_pin(display, port); 4940 4941 if (port >= PORT_TC1) 4942 return HPD_PORT_C + port - PORT_TC1; 4943 else 4944 return HPD_PORT_A + port - PORT_A; 4945 } 4946 4947 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4948 { 4949 if (port >= PORT_C) 4950 return HPD_PORT_TC1 + port - PORT_C; 4951 else 4952 return HPD_PORT_A + port - PORT_A; 4953 } 4954 4955 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4956 { 4957 if (port == PORT_D) 4958 return HPD_PORT_A; 4959 4960 if (HAS_PCH_TGP(display)) 4961 return icl_hpd_pin(display, port); 4962 4963 return HPD_PORT_A + port - PORT_A; 4964 } 4965 4966 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4967 { 4968 if (HAS_PCH_TGP(display)) 4969 return icl_hpd_pin(display, port); 4970 4971 return HPD_PORT_A + port - PORT_A; 4972 } 4973 4974 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 4975 { 4976 if (DISPLAY_VER(display) >= 12) 4977 return port >= PORT_TC1; 4978 else if (DISPLAY_VER(display) >= 11) 4979 return port >= PORT_C; 4980 else 4981 return false; 4982 } 4983 4984 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4985 { 4986 intel_dp_encoder_suspend(encoder); 4987 } 4988 4989 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4990 { 4991 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4992 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4993 4994 /* 4995 * TODO: Move this to intel_dp_encoder_suspend(), 4996 * once modeset locking around that is removed. 4997 */ 4998 intel_encoder_link_check_flush_work(encoder); 4999 intel_tc_port_suspend(dig_port); 5000 } 5001 5002 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5003 { 5004 if (intel_encoder_is_dp(encoder)) 5005 intel_dp_encoder_shutdown(encoder); 5006 if (intel_encoder_is_hdmi(encoder)) 5007 intel_hdmi_encoder_shutdown(encoder); 5008 } 5009 5010 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5011 { 5012 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5013 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5014 5015 intel_tc_port_cleanup(dig_port); 5016 } 5017 5018 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5019 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5020 5021 static bool port_strap_detected(struct intel_display *display, enum port port) 5022 { 5023 /* straps not used on skl+ */ 5024 if (DISPLAY_VER(display) >= 9) 5025 return true; 5026 5027 switch (port) { 5028 case PORT_A: 5029 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5030 case PORT_B: 5031 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5032 case PORT_C: 5033 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5034 case PORT_D: 5035 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5036 case PORT_E: 5037 return true; /* no strap for DDI-E */ 5038 default: 5039 MISSING_CASE(port); 5040 return false; 5041 } 5042 } 5043 5044 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5045 { 5046 return init_dp || intel_encoder_is_tc(encoder); 5047 } 5048 5049 static bool assert_has_icl_dsi(struct intel_display *display) 5050 { 5051 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5052 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5053 "Platform does not support DSI\n"); 5054 } 5055 5056 static bool port_in_use(struct intel_display *display, enum port port) 5057 { 5058 struct intel_encoder *encoder; 5059 5060 for_each_intel_encoder(display->drm, encoder) { 5061 /* FIXME what about second port for dual link DSI? */ 5062 if (encoder->port == port) 5063 return true; 5064 } 5065 5066 return false; 5067 } 5068 5069 void intel_ddi_init(struct intel_display *display, 5070 const struct intel_bios_encoder_data *devdata) 5071 { 5072 struct intel_digital_port *dig_port; 5073 struct intel_encoder *encoder; 5074 bool init_hdmi, init_dp; 5075 enum port port; 5076 enum phy phy; 5077 u32 ddi_buf_ctl; 5078 5079 port = intel_bios_encoder_port(devdata); 5080 if (port == PORT_NONE) 5081 return; 5082 5083 if (!port_strap_detected(display, port)) { 5084 drm_dbg_kms(display->drm, 5085 "Port %c strap not detected\n", port_name(port)); 5086 return; 5087 } 5088 5089 if (!assert_port_valid(display, port)) 5090 return; 5091 5092 if (port_in_use(display, port)) { 5093 drm_dbg_kms(display->drm, 5094 "Port %c already claimed\n", port_name(port)); 5095 return; 5096 } 5097 5098 if (intel_bios_encoder_supports_dsi(devdata)) { 5099 /* BXT/GLK handled elsewhere, for now at least */ 5100 if (!assert_has_icl_dsi(display)) 5101 return; 5102 5103 icl_dsi_init(display, devdata); 5104 return; 5105 } 5106 5107 phy = intel_port_to_phy(display, port); 5108 5109 /* 5110 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5111 * have taken over some of the PHYs and made them unavailable to the 5112 * driver. In that case we should skip initializing the corresponding 5113 * outputs. 5114 */ 5115 if (intel_hti_uses_phy(display, phy)) { 5116 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5117 port_name(port), phy_name(phy)); 5118 return; 5119 } 5120 5121 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5122 intel_bios_encoder_supports_hdmi(devdata); 5123 init_dp = intel_bios_encoder_supports_dp(devdata); 5124 5125 if (intel_bios_encoder_is_lspcon(devdata)) { 5126 /* 5127 * Lspcon device needs to be driven with DP connector 5128 * with special detection sequence. So make sure DP 5129 * is initialized before lspcon. 5130 */ 5131 init_dp = true; 5132 init_hdmi = false; 5133 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5134 port_name(port)); 5135 } 5136 5137 if (!init_dp && !init_hdmi) { 5138 drm_dbg_kms(display->drm, 5139 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5140 port_name(port)); 5141 return; 5142 } 5143 5144 if (intel_phy_is_snps(display, phy) && 5145 display->snps.phy_failed_calibration & BIT(phy)) { 5146 drm_dbg_kms(display->drm, 5147 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5148 phy_name(phy)); 5149 } 5150 5151 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5152 if (!dig_port) 5153 return; 5154 5155 dig_port->aux_ch = AUX_CH_NONE; 5156 5157 encoder = &dig_port->base; 5158 encoder->devdata = devdata; 5159 5160 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5161 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5162 DRM_MODE_ENCODER_TMDS, 5163 "DDI %c/PHY %c", 5164 port_name(port - PORT_D_XELPD + PORT_D), 5165 phy_name(phy)); 5166 } else if (DISPLAY_VER(display) >= 12) { 5167 enum tc_port tc_port = intel_port_to_tc(display, port); 5168 5169 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5170 DRM_MODE_ENCODER_TMDS, 5171 "DDI %s%c/PHY %s%c", 5172 port >= PORT_TC1 ? "TC" : "", 5173 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5174 tc_port != TC_PORT_NONE ? "TC" : "", 5175 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5176 } else if (DISPLAY_VER(display) >= 11) { 5177 enum tc_port tc_port = intel_port_to_tc(display, port); 5178 5179 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5180 DRM_MODE_ENCODER_TMDS, 5181 "DDI %c%s/PHY %s%c", 5182 port_name(port), 5183 port >= PORT_C ? " (TC)" : "", 5184 tc_port != TC_PORT_NONE ? "TC" : "", 5185 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5186 } else { 5187 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5188 DRM_MODE_ENCODER_TMDS, 5189 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5190 } 5191 5192 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5193 5194 mutex_init(&dig_port->hdcp.mutex); 5195 dig_port->hdcp.num_streams = 0; 5196 5197 encoder->hotplug = intel_ddi_hotplug; 5198 encoder->compute_output_type = intel_ddi_compute_output_type; 5199 encoder->compute_config = intel_ddi_compute_config; 5200 encoder->compute_config_late = intel_ddi_compute_config_late; 5201 encoder->enable = intel_ddi_enable; 5202 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5203 encoder->pre_enable = intel_ddi_pre_enable; 5204 encoder->disable = intel_ddi_disable; 5205 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5206 encoder->post_disable = intel_ddi_post_disable; 5207 encoder->update_pipe = intel_ddi_update_pipe; 5208 encoder->audio_enable = intel_audio_codec_enable; 5209 encoder->audio_disable = intel_audio_codec_disable; 5210 encoder->get_hw_state = intel_ddi_get_hw_state; 5211 encoder->sync_state = intel_ddi_sync_state; 5212 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5213 encoder->suspend = intel_ddi_encoder_suspend; 5214 encoder->shutdown = intel_ddi_encoder_shutdown; 5215 encoder->get_power_domains = intel_ddi_get_power_domains; 5216 5217 encoder->type = INTEL_OUTPUT_DDI; 5218 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5219 encoder->port = port; 5220 encoder->cloneable = 0; 5221 encoder->pipe_mask = ~0; 5222 5223 if (DISPLAY_VER(display) >= 14) { 5224 encoder->enable_clock = intel_mtl_pll_enable; 5225 encoder->disable_clock = intel_mtl_pll_disable; 5226 encoder->port_pll_type = intel_mtl_port_pll_type; 5227 encoder->get_config = mtl_ddi_get_config; 5228 } else if (display->platform.dg2) { 5229 encoder->enable_clock = intel_mpllb_enable; 5230 encoder->disable_clock = intel_mpllb_disable; 5231 encoder->get_config = dg2_ddi_get_config; 5232 } else if (display->platform.alderlake_s) { 5233 encoder->enable_clock = adls_ddi_enable_clock; 5234 encoder->disable_clock = adls_ddi_disable_clock; 5235 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5236 encoder->get_config = adls_ddi_get_config; 5237 } else if (display->platform.rocketlake) { 5238 encoder->enable_clock = rkl_ddi_enable_clock; 5239 encoder->disable_clock = rkl_ddi_disable_clock; 5240 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5241 encoder->get_config = rkl_ddi_get_config; 5242 } else if (display->platform.dg1) { 5243 encoder->enable_clock = dg1_ddi_enable_clock; 5244 encoder->disable_clock = dg1_ddi_disable_clock; 5245 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5246 encoder->get_config = dg1_ddi_get_config; 5247 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5248 if (intel_ddi_is_tc(display, port)) { 5249 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5250 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5251 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5252 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5253 encoder->get_config = icl_ddi_combo_get_config; 5254 } else { 5255 encoder->enable_clock = icl_ddi_combo_enable_clock; 5256 encoder->disable_clock = icl_ddi_combo_disable_clock; 5257 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5258 encoder->get_config = icl_ddi_combo_get_config; 5259 } 5260 } else if (DISPLAY_VER(display) >= 11) { 5261 if (intel_ddi_is_tc(display, port)) { 5262 encoder->enable_clock = icl_ddi_tc_enable_clock; 5263 encoder->disable_clock = icl_ddi_tc_disable_clock; 5264 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5265 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5266 encoder->get_config = icl_ddi_tc_get_config; 5267 } else { 5268 encoder->enable_clock = icl_ddi_combo_enable_clock; 5269 encoder->disable_clock = icl_ddi_combo_disable_clock; 5270 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5271 encoder->get_config = icl_ddi_combo_get_config; 5272 } 5273 } else if (display->platform.geminilake || display->platform.broxton) { 5274 /* BXT/GLK have fixed PLL->port mapping */ 5275 encoder->get_config = bxt_ddi_get_config; 5276 } else if (DISPLAY_VER(display) == 9) { 5277 encoder->enable_clock = skl_ddi_enable_clock; 5278 encoder->disable_clock = skl_ddi_disable_clock; 5279 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5280 encoder->get_config = skl_ddi_get_config; 5281 } else if (display->platform.broadwell || display->platform.haswell) { 5282 encoder->enable_clock = hsw_ddi_enable_clock; 5283 encoder->disable_clock = hsw_ddi_disable_clock; 5284 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5285 encoder->get_config = hsw_ddi_get_config; 5286 } 5287 5288 if (DISPLAY_VER(display) >= 14) { 5289 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5290 } else if (display->platform.dg2) { 5291 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5292 } else if (DISPLAY_VER(display) >= 12) { 5293 if (intel_encoder_is_combo(encoder)) 5294 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5295 else 5296 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5297 } else if (DISPLAY_VER(display) >= 11) { 5298 if (intel_encoder_is_combo(encoder)) 5299 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5300 else 5301 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5302 } else if (display->platform.geminilake || display->platform.broxton) { 5303 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5304 } else { 5305 encoder->set_signal_levels = hsw_set_signal_levels; 5306 } 5307 5308 intel_ddi_buf_trans_init(encoder); 5309 5310 if (DISPLAY_VER(display) >= 13) 5311 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5312 else if (display->platform.dg1) 5313 encoder->hpd_pin = dg1_hpd_pin(display, port); 5314 else if (display->platform.rocketlake) 5315 encoder->hpd_pin = rkl_hpd_pin(display, port); 5316 else if (DISPLAY_VER(display) >= 12) 5317 encoder->hpd_pin = tgl_hpd_pin(display, port); 5318 else if (display->platform.jasperlake || display->platform.elkhartlake) 5319 encoder->hpd_pin = ehl_hpd_pin(display, port); 5320 else if (DISPLAY_VER(display) == 11) 5321 encoder->hpd_pin = icl_hpd_pin(display, port); 5322 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5323 encoder->hpd_pin = skl_hpd_pin(display, port); 5324 else 5325 encoder->hpd_pin = intel_hpd_pin_default(port); 5326 5327 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5328 5329 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5330 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5331 5332 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5333 5334 dig_port->dp.output_reg = INVALID_MMIO_REG; 5335 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5336 5337 if (need_aux_ch(encoder, init_dp)) { 5338 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5339 if (dig_port->aux_ch == AUX_CH_NONE) 5340 goto err; 5341 } 5342 5343 if (intel_encoder_is_tc(encoder)) { 5344 bool is_legacy = 5345 !intel_bios_encoder_supports_typec_usb(devdata) && 5346 !intel_bios_encoder_supports_tbt(devdata); 5347 5348 if (!is_legacy && init_hdmi) { 5349 is_legacy = !init_dp; 5350 5351 drm_dbg_kms(display->drm, 5352 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5353 port_name(port), 5354 str_yes_no(init_dp), 5355 is_legacy ? "legacy" : "non-legacy"); 5356 } 5357 5358 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5359 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5360 5361 dig_port->lock = intel_tc_port_lock; 5362 dig_port->unlock = intel_tc_port_unlock; 5363 5364 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5365 goto err; 5366 } 5367 5368 drm_WARN_ON(display->drm, port > PORT_I); 5369 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5370 5371 if (DISPLAY_VER(display) >= 11) { 5372 if (intel_encoder_is_tc(encoder)) 5373 dig_port->connected = intel_tc_port_connected; 5374 else 5375 dig_port->connected = lpt_digital_port_connected; 5376 } else if (display->platform.geminilake || display->platform.broxton) { 5377 dig_port->connected = bdw_digital_port_connected; 5378 } else if (DISPLAY_VER(display) == 9) { 5379 dig_port->connected = lpt_digital_port_connected; 5380 } else if (display->platform.broadwell) { 5381 if (port == PORT_A) 5382 dig_port->connected = bdw_digital_port_connected; 5383 else 5384 dig_port->connected = lpt_digital_port_connected; 5385 } else if (display->platform.haswell) { 5386 if (port == PORT_A) 5387 dig_port->connected = hsw_digital_port_connected; 5388 else 5389 dig_port->connected = lpt_digital_port_connected; 5390 } 5391 5392 intel_infoframe_init(dig_port); 5393 5394 if (init_dp) { 5395 if (intel_ddi_init_dp_connector(dig_port)) 5396 goto err; 5397 5398 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5399 5400 if (dig_port->dp.mso_link_count) 5401 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5402 } 5403 5404 /* 5405 * In theory we don't need the encoder->type check, 5406 * but leave it just in case we have some really bad VBTs... 5407 */ 5408 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5409 if (intel_ddi_init_hdmi_connector(dig_port)) 5410 goto err; 5411 } 5412 5413 return; 5414 5415 err: 5416 drm_encoder_cleanup(&encoder->base); 5417 kfree(dig_port); 5418 } 5419