1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_hbr2_hbr3[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_5_0; 587 u32 cri_txdeemph_override_11_6; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x0, 0x1B, 0x00 }, /* 0 0 */ 594 { 0x0, 0x23, 0x08 }, /* 0 1 */ 595 { 0x0, 0x2D, 0x12 }, /* 0 2 */ 596 { 0x0, 0x00, 0x00 }, /* 0 3 */ 597 { 0x0, 0x23, 0x00 }, /* 1 0 */ 598 { 0x0, 0x2B, 0x09 }, /* 1 1 */ 599 { 0x0, 0x2E, 0x11 }, /* 1 2 */ 600 { 0x0, 0x2F, 0x00 }, /* 2 0 */ 601 { 0x0, 0x33, 0x0C }, /* 2 1 */ 602 { 0x0, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 struct tgl_dkl_phy_ddi_buf_trans { 606 u32 dkl_vswing_control; 607 u32 dkl_preshoot_control; 608 u32 dkl_de_emphasis_control; 609 }; 610 611 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 612 /* VS pre-emp Non-trans mV Pre-emph dB */ 613 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 614 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ 615 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ 616 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 617 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 618 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ 619 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 620 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 621 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 622 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 623 }; 624 625 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 626 /* HDMI Preset VS Pre-emph */ 627 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 628 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 629 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 630 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 631 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 632 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 633 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 634 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 635 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 636 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 637 }; 638 639 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 640 /* NT mV Trans mV db */ 641 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 642 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 643 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 644 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 645 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 646 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 647 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 648 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 649 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 650 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 651 }; 652 653 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 654 /* NT mV Trans mV db */ 655 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 656 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 657 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 658 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 659 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 660 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 661 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 662 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 663 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 664 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 665 }; 666 667 static const struct ddi_buf_trans * 668 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 669 { 670 if (dev_priv->vbt.edp.low_vswing) { 671 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 672 return bdw_ddi_translations_edp; 673 } else { 674 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 675 return bdw_ddi_translations_dp; 676 } 677 } 678 679 static const struct ddi_buf_trans * 680 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 681 { 682 if (IS_SKL_ULX(dev_priv)) { 683 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 684 return skl_y_ddi_translations_dp; 685 } else if (IS_SKL_ULT(dev_priv)) { 686 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 687 return skl_u_ddi_translations_dp; 688 } else { 689 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 690 return skl_ddi_translations_dp; 691 } 692 } 693 694 static const struct ddi_buf_trans * 695 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 696 { 697 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 698 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 699 return kbl_y_ddi_translations_dp; 700 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 701 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 702 return kbl_u_ddi_translations_dp; 703 } else { 704 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 705 return kbl_ddi_translations_dp; 706 } 707 } 708 709 static const struct ddi_buf_trans * 710 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 711 { 712 if (dev_priv->vbt.edp.low_vswing) { 713 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 714 IS_CFL_ULX(dev_priv)) { 715 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 716 return skl_y_ddi_translations_edp; 717 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 718 IS_CFL_ULT(dev_priv)) { 719 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 720 return skl_u_ddi_translations_edp; 721 } else { 722 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 723 return skl_ddi_translations_edp; 724 } 725 } 726 727 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 728 return kbl_get_buf_trans_dp(dev_priv, n_entries); 729 else 730 return skl_get_buf_trans_dp(dev_priv, n_entries); 731 } 732 733 static const struct ddi_buf_trans * 734 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 735 { 736 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 737 IS_CFL_ULX(dev_priv)) { 738 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 739 return skl_y_ddi_translations_hdmi; 740 } else { 741 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 742 return skl_ddi_translations_hdmi; 743 } 744 } 745 746 static int skl_buf_trans_num_entries(enum port port, int n_entries) 747 { 748 /* Only DDIA and DDIE can select the 10th register with DP */ 749 if (port == PORT_A || port == PORT_E) 750 return min(n_entries, 10); 751 else 752 return min(n_entries, 9); 753 } 754 755 static const struct ddi_buf_trans * 756 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 757 enum port port, int *n_entries) 758 { 759 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 760 const struct ddi_buf_trans *ddi_translations = 761 kbl_get_buf_trans_dp(dev_priv, n_entries); 762 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 763 return ddi_translations; 764 } else if (IS_SKYLAKE(dev_priv)) { 765 const struct ddi_buf_trans *ddi_translations = 766 skl_get_buf_trans_dp(dev_priv, n_entries); 767 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 768 return ddi_translations; 769 } else if (IS_BROADWELL(dev_priv)) { 770 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 771 return bdw_ddi_translations_dp; 772 } else if (IS_HASWELL(dev_priv)) { 773 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 774 return hsw_ddi_translations_dp; 775 } 776 777 *n_entries = 0; 778 return NULL; 779 } 780 781 static const struct ddi_buf_trans * 782 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 783 enum port port, int *n_entries) 784 { 785 if (IS_GEN9_BC(dev_priv)) { 786 const struct ddi_buf_trans *ddi_translations = 787 skl_get_buf_trans_edp(dev_priv, n_entries); 788 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 789 return ddi_translations; 790 } else if (IS_BROADWELL(dev_priv)) { 791 return bdw_get_buf_trans_edp(dev_priv, n_entries); 792 } else if (IS_HASWELL(dev_priv)) { 793 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 794 return hsw_ddi_translations_dp; 795 } 796 797 *n_entries = 0; 798 return NULL; 799 } 800 801 static const struct ddi_buf_trans * 802 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 803 int *n_entries) 804 { 805 if (IS_BROADWELL(dev_priv)) { 806 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 807 return bdw_ddi_translations_fdi; 808 } else if (IS_HASWELL(dev_priv)) { 809 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 810 return hsw_ddi_translations_fdi; 811 } 812 813 *n_entries = 0; 814 return NULL; 815 } 816 817 static const struct ddi_buf_trans * 818 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 819 int *n_entries) 820 { 821 if (IS_GEN9_BC(dev_priv)) { 822 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 823 } else if (IS_BROADWELL(dev_priv)) { 824 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 825 return bdw_ddi_translations_hdmi; 826 } else if (IS_HASWELL(dev_priv)) { 827 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 828 return hsw_ddi_translations_hdmi; 829 } 830 831 *n_entries = 0; 832 return NULL; 833 } 834 835 static const struct bxt_ddi_buf_trans * 836 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 837 { 838 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 839 return bxt_ddi_translations_dp; 840 } 841 842 static const struct bxt_ddi_buf_trans * 843 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 844 { 845 if (dev_priv->vbt.edp.low_vswing) { 846 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 847 return bxt_ddi_translations_edp; 848 } 849 850 return bxt_get_buf_trans_dp(dev_priv, n_entries); 851 } 852 853 static const struct bxt_ddi_buf_trans * 854 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 855 { 856 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 857 return bxt_ddi_translations_hdmi; 858 } 859 860 static const struct cnl_ddi_buf_trans * 861 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 862 { 863 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 864 865 if (voltage == VOLTAGE_INFO_0_85V) { 866 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 867 return cnl_ddi_translations_hdmi_0_85V; 868 } else if (voltage == VOLTAGE_INFO_0_95V) { 869 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 870 return cnl_ddi_translations_hdmi_0_95V; 871 } else if (voltage == VOLTAGE_INFO_1_05V) { 872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 873 return cnl_ddi_translations_hdmi_1_05V; 874 } else { 875 *n_entries = 1; /* shut up gcc */ 876 MISSING_CASE(voltage); 877 } 878 return NULL; 879 } 880 881 static const struct cnl_ddi_buf_trans * 882 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 883 { 884 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 885 886 if (voltage == VOLTAGE_INFO_0_85V) { 887 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 888 return cnl_ddi_translations_dp_0_85V; 889 } else if (voltage == VOLTAGE_INFO_0_95V) { 890 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 891 return cnl_ddi_translations_dp_0_95V; 892 } else if (voltage == VOLTAGE_INFO_1_05V) { 893 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 894 return cnl_ddi_translations_dp_1_05V; 895 } else { 896 *n_entries = 1; /* shut up gcc */ 897 MISSING_CASE(voltage); 898 } 899 return NULL; 900 } 901 902 static const struct cnl_ddi_buf_trans * 903 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 904 { 905 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 906 907 if (dev_priv->vbt.edp.low_vswing) { 908 if (voltage == VOLTAGE_INFO_0_85V) { 909 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 910 return cnl_ddi_translations_edp_0_85V; 911 } else if (voltage == VOLTAGE_INFO_0_95V) { 912 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 913 return cnl_ddi_translations_edp_0_95V; 914 } else if (voltage == VOLTAGE_INFO_1_05V) { 915 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 916 return cnl_ddi_translations_edp_1_05V; 917 } else { 918 *n_entries = 1; /* shut up gcc */ 919 MISSING_CASE(voltage); 920 } 921 return NULL; 922 } else { 923 return cnl_get_buf_trans_dp(dev_priv, n_entries); 924 } 925 } 926 927 static const struct cnl_ddi_buf_trans * 928 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 929 int *n_entries) 930 { 931 if (type == INTEL_OUTPUT_HDMI) { 932 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 933 return icl_combo_phy_ddi_translations_hdmi; 934 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 935 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 936 return icl_combo_phy_ddi_translations_edp_hbr3; 937 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 938 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 939 return icl_combo_phy_ddi_translations_edp_hbr2; 940 } 941 942 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 943 return icl_combo_phy_ddi_translations_dp_hbr2; 944 } 945 946 static const struct cnl_ddi_buf_trans * 947 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 948 int *n_entries) 949 { 950 if (type == INTEL_OUTPUT_DP && rate > 270000) { 951 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3); 952 return ehl_combo_phy_ddi_translations_hbr2_hbr3; 953 } 954 955 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 956 } 957 958 static const struct cnl_ddi_buf_trans * 959 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 960 int *n_entries) 961 { 962 if (type != INTEL_OUTPUT_DP) { 963 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 964 } else if (rate > 270000) { 965 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 966 return tgl_combo_phy_ddi_translations_dp_hbr2; 967 } 968 969 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 970 return tgl_combo_phy_ddi_translations_dp_hbr; 971 } 972 973 static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 974 { 975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 976 int n_entries, level, default_entry; 977 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 978 979 if (INTEL_GEN(dev_priv) >= 12) { 980 if (intel_phy_is_combo(dev_priv, phy)) 981 tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 982 0, &n_entries); 983 else 984 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 985 default_entry = n_entries - 1; 986 } else if (INTEL_GEN(dev_priv) == 11) { 987 if (intel_phy_is_combo(dev_priv, phy)) 988 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 989 0, &n_entries); 990 else 991 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 992 default_entry = n_entries - 1; 993 } else if (IS_CANNONLAKE(dev_priv)) { 994 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 995 default_entry = n_entries - 1; 996 } else if (IS_GEN9_LP(dev_priv)) { 997 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 998 default_entry = n_entries - 1; 999 } else if (IS_GEN9_BC(dev_priv)) { 1000 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1001 default_entry = 8; 1002 } else if (IS_BROADWELL(dev_priv)) { 1003 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1004 default_entry = 7; 1005 } else if (IS_HASWELL(dev_priv)) { 1006 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1007 default_entry = 6; 1008 } else { 1009 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1010 return 0; 1011 } 1012 1013 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1014 return 0; 1015 1016 level = intel_bios_hdmi_level_shift(encoder); 1017 if (level < 0) 1018 level = default_entry; 1019 1020 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1021 level = n_entries - 1; 1022 1023 return level; 1024 } 1025 1026 /* 1027 * Starting with Haswell, DDI port buffers must be programmed with correct 1028 * values in advance. This function programs the correct values for 1029 * DP/eDP/FDI use cases. 1030 */ 1031 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1032 const struct intel_crtc_state *crtc_state) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1035 u32 iboost_bit = 0; 1036 int i, n_entries; 1037 enum port port = encoder->port; 1038 const struct ddi_buf_trans *ddi_translations; 1039 1040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1041 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1042 &n_entries); 1043 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1044 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 1045 &n_entries); 1046 else 1047 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 1048 &n_entries); 1049 1050 /* If we're boosting the current, set bit 31 of trans1 */ 1051 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1052 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1053 1054 for (i = 0; i < n_entries; i++) { 1055 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1056 ddi_translations[i].trans1 | iboost_bit); 1057 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1058 ddi_translations[i].trans2); 1059 } 1060 } 1061 1062 /* 1063 * Starting with Haswell, DDI port buffers must be programmed with correct 1064 * values in advance. This function programs the correct values for 1065 * HDMI/DVI use cases. 1066 */ 1067 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1068 int level) 1069 { 1070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1071 u32 iboost_bit = 0; 1072 int n_entries; 1073 enum port port = encoder->port; 1074 const struct ddi_buf_trans *ddi_translations; 1075 1076 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1077 1078 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1079 return; 1080 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1081 level = n_entries - 1; 1082 1083 /* If we're boosting the current, set bit 31 of trans1 */ 1084 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1085 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1086 1087 /* Entry 9 is for HDMI: */ 1088 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1089 ddi_translations[level].trans1 | iboost_bit); 1090 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1091 ddi_translations[level].trans2); 1092 } 1093 1094 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1095 enum port port) 1096 { 1097 i915_reg_t reg = DDI_BUF_CTL(port); 1098 int i; 1099 1100 for (i = 0; i < 16; i++) { 1101 udelay(1); 1102 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) 1103 return; 1104 } 1105 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 1106 } 1107 1108 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1109 { 1110 switch (pll->info->id) { 1111 case DPLL_ID_WRPLL1: 1112 return PORT_CLK_SEL_WRPLL1; 1113 case DPLL_ID_WRPLL2: 1114 return PORT_CLK_SEL_WRPLL2; 1115 case DPLL_ID_SPLL: 1116 return PORT_CLK_SEL_SPLL; 1117 case DPLL_ID_LCPLL_810: 1118 return PORT_CLK_SEL_LCPLL_810; 1119 case DPLL_ID_LCPLL_1350: 1120 return PORT_CLK_SEL_LCPLL_1350; 1121 case DPLL_ID_LCPLL_2700: 1122 return PORT_CLK_SEL_LCPLL_2700; 1123 default: 1124 MISSING_CASE(pll->info->id); 1125 return PORT_CLK_SEL_NONE; 1126 } 1127 } 1128 1129 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1130 const struct intel_crtc_state *crtc_state) 1131 { 1132 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1133 int clock = crtc_state->port_clock; 1134 const enum intel_dpll_id id = pll->info->id; 1135 1136 switch (id) { 1137 default: 1138 /* 1139 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1140 * here, so do warn if this get passed in 1141 */ 1142 MISSING_CASE(id); 1143 return DDI_CLK_SEL_NONE; 1144 case DPLL_ID_ICL_TBTPLL: 1145 switch (clock) { 1146 case 162000: 1147 return DDI_CLK_SEL_TBT_162; 1148 case 270000: 1149 return DDI_CLK_SEL_TBT_270; 1150 case 540000: 1151 return DDI_CLK_SEL_TBT_540; 1152 case 810000: 1153 return DDI_CLK_SEL_TBT_810; 1154 default: 1155 MISSING_CASE(clock); 1156 return DDI_CLK_SEL_NONE; 1157 } 1158 case DPLL_ID_ICL_MGPLL1: 1159 case DPLL_ID_ICL_MGPLL2: 1160 case DPLL_ID_ICL_MGPLL3: 1161 case DPLL_ID_ICL_MGPLL4: 1162 case DPLL_ID_TGL_MGPLL5: 1163 case DPLL_ID_TGL_MGPLL6: 1164 return DDI_CLK_SEL_MG; 1165 } 1166 } 1167 1168 /* Starting with Haswell, different DDI ports can work in FDI mode for 1169 * connection to the PCH-located connectors. For this, it is necessary to train 1170 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1171 * 1172 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1173 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1174 * DDI A (which is used for eDP) 1175 */ 1176 1177 void hsw_fdi_link_train(struct intel_encoder *encoder, 1178 const struct intel_crtc_state *crtc_state) 1179 { 1180 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1182 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1183 1184 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1185 1186 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1187 * mode set "sequence for CRT port" document: 1188 * - TP1 to TP2 time with the default value 1189 * - FDI delay to 90h 1190 * 1191 * WaFDIAutoLinkSetTimingOverrride:hsw 1192 */ 1193 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1194 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1195 1196 /* Enable the PCH Receiver FDI PLL */ 1197 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1198 FDI_RX_PLL_ENABLE | 1199 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1200 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1201 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1202 udelay(220); 1203 1204 /* Switch from Rawclk to PCDclk */ 1205 rx_ctl_val |= FDI_PCDCLK; 1206 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1207 1208 /* Configure Port Clock Select */ 1209 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1210 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1211 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1212 1213 /* Start the training iterating through available voltages and emphasis, 1214 * testing each value twice. */ 1215 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1216 /* Configure DP_TP_CTL with auto-training */ 1217 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1218 DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE); 1219 1220 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1221 * DDI E does not support port reversal, the functionality is 1222 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1223 * port reversal bit */ 1224 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1225 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1226 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1227 1228 udelay(600); 1229 1230 /* Program PCH FDI Receiver TU */ 1231 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1232 1233 /* Enable PCH FDI Receiver with auto-training */ 1234 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1235 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1236 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1237 1238 /* Wait for FDI receiver lane calibration */ 1239 udelay(30); 1240 1241 /* Unset FDI_RX_MISC pwrdn lanes */ 1242 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1243 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1244 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1245 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1246 1247 /* Wait for FDI auto training time */ 1248 udelay(5); 1249 1250 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1251 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1252 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 1253 break; 1254 } 1255 1256 /* 1257 * Leave things enabled even if we failed to train FDI. 1258 * Results in less fireworks from the state checker. 1259 */ 1260 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1261 DRM_ERROR("FDI link training failed!\n"); 1262 break; 1263 } 1264 1265 rx_ctl_val &= ~FDI_RX_ENABLE; 1266 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1267 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1268 1269 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1270 temp &= ~DDI_BUF_CTL_ENABLE; 1271 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1272 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1273 1274 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1275 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1276 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1277 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1278 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1279 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1280 1281 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1282 1283 /* Reset FDI_RX_MISC pwrdn lanes */ 1284 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1285 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1286 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1287 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1288 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1289 } 1290 1291 /* Enable normal pixel sending for FDI */ 1292 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1293 DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE); 1294 } 1295 1296 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1297 { 1298 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1299 struct intel_digital_port *intel_dig_port = 1300 enc_to_dig_port(encoder); 1301 1302 intel_dp->DP = intel_dig_port->saved_port_bits | 1303 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1304 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1305 } 1306 1307 static struct intel_encoder * 1308 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 1309 { 1310 struct drm_device *dev = crtc->base.dev; 1311 struct intel_encoder *encoder, *ret = NULL; 1312 int num_encoders = 0; 1313 1314 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1315 ret = encoder; 1316 num_encoders++; 1317 } 1318 1319 if (num_encoders != 1) 1320 drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n", 1321 num_encoders, 1322 pipe_name(crtc->pipe)); 1323 1324 BUG_ON(ret == NULL); 1325 return ret; 1326 } 1327 1328 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 1329 i915_reg_t reg) 1330 { 1331 int refclk; 1332 int n, p, r; 1333 u32 wrpll; 1334 1335 wrpll = intel_de_read(dev_priv, reg); 1336 switch (wrpll & WRPLL_REF_MASK) { 1337 case WRPLL_REF_SPECIAL_HSW: 1338 /* 1339 * muxed-SSC for BDW. 1340 * non-SSC for non-ULT HSW. Check FUSE_STRAP3 1341 * for the non-SSC reference frequency. 1342 */ 1343 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { 1344 if (intel_de_read(dev_priv, FUSE_STRAP3) & HSW_REF_CLK_SELECT) 1345 refclk = 24; 1346 else 1347 refclk = 135; 1348 break; 1349 } 1350 /* fall through */ 1351 case WRPLL_REF_PCH_SSC: 1352 /* 1353 * We could calculate spread here, but our checking 1354 * code only cares about 5% accuracy, and spread is a max of 1355 * 0.5% downspread. 1356 */ 1357 refclk = 135; 1358 break; 1359 case WRPLL_REF_LCPLL: 1360 refclk = 2700; 1361 break; 1362 default: 1363 MISSING_CASE(wrpll); 1364 return 0; 1365 } 1366 1367 r = wrpll & WRPLL_DIVIDER_REF_MASK; 1368 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 1369 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 1370 1371 /* Convert to KHz, p & r have a fixed point portion */ 1372 return (refclk * n * 100) / (p * r); 1373 } 1374 1375 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) 1376 { 1377 u32 p0, p1, p2, dco_freq; 1378 1379 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; 1380 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; 1381 1382 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) 1383 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 1384 else 1385 p1 = 1; 1386 1387 1388 switch (p0) { 1389 case DPLL_CFGCR2_PDIV_1: 1390 p0 = 1; 1391 break; 1392 case DPLL_CFGCR2_PDIV_2: 1393 p0 = 2; 1394 break; 1395 case DPLL_CFGCR2_PDIV_3: 1396 p0 = 3; 1397 break; 1398 case DPLL_CFGCR2_PDIV_7: 1399 p0 = 7; 1400 break; 1401 } 1402 1403 switch (p2) { 1404 case DPLL_CFGCR2_KDIV_5: 1405 p2 = 5; 1406 break; 1407 case DPLL_CFGCR2_KDIV_2: 1408 p2 = 2; 1409 break; 1410 case DPLL_CFGCR2_KDIV_3: 1411 p2 = 3; 1412 break; 1413 case DPLL_CFGCR2_KDIV_1: 1414 p2 = 1; 1415 break; 1416 } 1417 1418 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) 1419 * 24 * 1000; 1420 1421 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) 1422 * 24 * 1000) / 0x8000; 1423 1424 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1425 return 0; 1426 1427 return dco_freq / (p0 * p1 * p2 * 5); 1428 } 1429 1430 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, 1431 struct intel_dpll_hw_state *pll_state) 1432 { 1433 u32 p0, p1, p2, dco_freq, ref_clock; 1434 1435 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; 1436 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; 1437 1438 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) 1439 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> 1440 DPLL_CFGCR1_QDIV_RATIO_SHIFT; 1441 else 1442 p1 = 1; 1443 1444 1445 switch (p0) { 1446 case DPLL_CFGCR1_PDIV_2: 1447 p0 = 2; 1448 break; 1449 case DPLL_CFGCR1_PDIV_3: 1450 p0 = 3; 1451 break; 1452 case DPLL_CFGCR1_PDIV_5: 1453 p0 = 5; 1454 break; 1455 case DPLL_CFGCR1_PDIV_7: 1456 p0 = 7; 1457 break; 1458 } 1459 1460 switch (p2) { 1461 case DPLL_CFGCR1_KDIV_1: 1462 p2 = 1; 1463 break; 1464 case DPLL_CFGCR1_KDIV_2: 1465 p2 = 2; 1466 break; 1467 case DPLL_CFGCR1_KDIV_3: 1468 p2 = 3; 1469 break; 1470 } 1471 1472 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); 1473 1474 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) 1475 * ref_clock; 1476 1477 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> 1478 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; 1479 1480 if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0)) 1481 return 0; 1482 1483 return dco_freq / (p0 * p1 * p2 * 5); 1484 } 1485 1486 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1487 enum port port) 1488 { 1489 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1490 1491 switch (val) { 1492 case DDI_CLK_SEL_NONE: 1493 return 0; 1494 case DDI_CLK_SEL_TBT_162: 1495 return 162000; 1496 case DDI_CLK_SEL_TBT_270: 1497 return 270000; 1498 case DDI_CLK_SEL_TBT_540: 1499 return 540000; 1500 case DDI_CLK_SEL_TBT_810: 1501 return 810000; 1502 default: 1503 MISSING_CASE(val); 1504 return 0; 1505 } 1506 } 1507 1508 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, 1509 const struct intel_dpll_hw_state *pll_state) 1510 { 1511 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; 1512 u64 tmp; 1513 1514 ref_clock = dev_priv->cdclk.hw.ref; 1515 1516 if (INTEL_GEN(dev_priv) >= 12) { 1517 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; 1518 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; 1519 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; 1520 1521 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { 1522 m2_frac = pll_state->mg_pll_bias & 1523 DKL_PLL_BIAS_FBDIV_FRAC_MASK; 1524 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; 1525 } else { 1526 m2_frac = 0; 1527 } 1528 } else { 1529 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; 1530 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; 1531 1532 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { 1533 m2_frac = pll_state->mg_pll_div0 & 1534 MG_PLL_DIV0_FBDIV_FRAC_MASK; 1535 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; 1536 } else { 1537 m2_frac = 0; 1538 } 1539 } 1540 1541 switch (pll_state->mg_clktop2_hsclkctl & 1542 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { 1543 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: 1544 div1 = 2; 1545 break; 1546 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: 1547 div1 = 3; 1548 break; 1549 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: 1550 div1 = 5; 1551 break; 1552 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: 1553 div1 = 7; 1554 break; 1555 default: 1556 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); 1557 return 0; 1558 } 1559 1560 div2 = (pll_state->mg_clktop2_hsclkctl & 1561 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> 1562 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; 1563 1564 /* div2 value of 0 is same as 1 means no div */ 1565 if (div2 == 0) 1566 div2 = 1; 1567 1568 /* 1569 * Adjust the original formula to delay the division by 2^22 in order to 1570 * minimize possible rounding errors. 1571 */ 1572 tmp = (u64)m1 * m2_int * ref_clock + 1573 (((u64)m1 * m2_frac * ref_clock) >> 22); 1574 tmp = div_u64(tmp, 5 * div1 * div2); 1575 1576 return tmp; 1577 } 1578 1579 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1580 { 1581 int dotclock; 1582 1583 if (pipe_config->has_pch_encoder) 1584 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1585 &pipe_config->fdi_m_n); 1586 else if (intel_crtc_has_dp_encoder(pipe_config)) 1587 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1588 &pipe_config->dp_m_n); 1589 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1590 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1591 else 1592 dotclock = pipe_config->port_clock; 1593 1594 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1595 !intel_crtc_has_dp_encoder(pipe_config)) 1596 dotclock *= 2; 1597 1598 if (pipe_config->pixel_multiplier) 1599 dotclock /= pipe_config->pixel_multiplier; 1600 1601 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1602 } 1603 1604 static void icl_ddi_clock_get(struct intel_encoder *encoder, 1605 struct intel_crtc_state *pipe_config) 1606 { 1607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1608 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1609 enum port port = encoder->port; 1610 enum phy phy = intel_port_to_phy(dev_priv, port); 1611 int link_clock; 1612 1613 if (intel_phy_is_combo(dev_priv, phy)) { 1614 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1615 } else { 1616 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, 1617 pipe_config->shared_dpll); 1618 1619 if (pll_id == DPLL_ID_ICL_TBTPLL) 1620 link_clock = icl_calc_tbt_pll_link(dev_priv, port); 1621 else 1622 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); 1623 } 1624 1625 pipe_config->port_clock = link_clock; 1626 1627 ddi_dotclock_get(pipe_config); 1628 } 1629 1630 static void cnl_ddi_clock_get(struct intel_encoder *encoder, 1631 struct intel_crtc_state *pipe_config) 1632 { 1633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1634 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1635 int link_clock; 1636 1637 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { 1638 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1639 } else { 1640 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; 1641 1642 switch (link_clock) { 1643 case DPLL_CFGCR0_LINK_RATE_810: 1644 link_clock = 81000; 1645 break; 1646 case DPLL_CFGCR0_LINK_RATE_1080: 1647 link_clock = 108000; 1648 break; 1649 case DPLL_CFGCR0_LINK_RATE_1350: 1650 link_clock = 135000; 1651 break; 1652 case DPLL_CFGCR0_LINK_RATE_1620: 1653 link_clock = 162000; 1654 break; 1655 case DPLL_CFGCR0_LINK_RATE_2160: 1656 link_clock = 216000; 1657 break; 1658 case DPLL_CFGCR0_LINK_RATE_2700: 1659 link_clock = 270000; 1660 break; 1661 case DPLL_CFGCR0_LINK_RATE_3240: 1662 link_clock = 324000; 1663 break; 1664 case DPLL_CFGCR0_LINK_RATE_4050: 1665 link_clock = 405000; 1666 break; 1667 default: 1668 drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n"); 1669 break; 1670 } 1671 link_clock *= 2; 1672 } 1673 1674 pipe_config->port_clock = link_clock; 1675 1676 ddi_dotclock_get(pipe_config); 1677 } 1678 1679 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1680 struct intel_crtc_state *pipe_config) 1681 { 1682 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1683 int link_clock; 1684 1685 /* 1686 * ctrl1 register is already shifted for each pll, just use 0 to get 1687 * the internal shift for each field 1688 */ 1689 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { 1690 link_clock = skl_calc_wrpll_link(pll_state); 1691 } else { 1692 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); 1693 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); 1694 1695 switch (link_clock) { 1696 case DPLL_CTRL1_LINK_RATE_810: 1697 link_clock = 81000; 1698 break; 1699 case DPLL_CTRL1_LINK_RATE_1080: 1700 link_clock = 108000; 1701 break; 1702 case DPLL_CTRL1_LINK_RATE_1350: 1703 link_clock = 135000; 1704 break; 1705 case DPLL_CTRL1_LINK_RATE_1620: 1706 link_clock = 162000; 1707 break; 1708 case DPLL_CTRL1_LINK_RATE_2160: 1709 link_clock = 216000; 1710 break; 1711 case DPLL_CTRL1_LINK_RATE_2700: 1712 link_clock = 270000; 1713 break; 1714 default: 1715 drm_WARN(encoder->base.dev, 1, 1716 "Unsupported link rate\n"); 1717 break; 1718 } 1719 link_clock *= 2; 1720 } 1721 1722 pipe_config->port_clock = link_clock; 1723 1724 ddi_dotclock_get(pipe_config); 1725 } 1726 1727 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1728 struct intel_crtc_state *pipe_config) 1729 { 1730 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1731 int link_clock = 0; 1732 u32 val, pll; 1733 1734 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); 1735 switch (val & PORT_CLK_SEL_MASK) { 1736 case PORT_CLK_SEL_LCPLL_810: 1737 link_clock = 81000; 1738 break; 1739 case PORT_CLK_SEL_LCPLL_1350: 1740 link_clock = 135000; 1741 break; 1742 case PORT_CLK_SEL_LCPLL_2700: 1743 link_clock = 270000; 1744 break; 1745 case PORT_CLK_SEL_WRPLL1: 1746 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1747 break; 1748 case PORT_CLK_SEL_WRPLL2: 1749 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1750 break; 1751 case PORT_CLK_SEL_SPLL: 1752 pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK; 1753 if (pll == SPLL_FREQ_810MHz) 1754 link_clock = 81000; 1755 else if (pll == SPLL_FREQ_1350MHz) 1756 link_clock = 135000; 1757 else if (pll == SPLL_FREQ_2700MHz) 1758 link_clock = 270000; 1759 else { 1760 drm_WARN(&dev_priv->drm, 1, "bad spll freq\n"); 1761 return; 1762 } 1763 break; 1764 default: 1765 drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n"); 1766 return; 1767 } 1768 1769 pipe_config->port_clock = link_clock * 2; 1770 1771 ddi_dotclock_get(pipe_config); 1772 } 1773 1774 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) 1775 { 1776 struct dpll clock; 1777 1778 clock.m1 = 2; 1779 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; 1780 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1781 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; 1782 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1783 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1784 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1785 1786 return chv_calc_dpll_params(100000, &clock); 1787 } 1788 1789 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1790 struct intel_crtc_state *pipe_config) 1791 { 1792 pipe_config->port_clock = 1793 bxt_calc_pll_link(&pipe_config->dpll_hw_state); 1794 1795 ddi_dotclock_get(pipe_config); 1796 } 1797 1798 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1799 struct intel_crtc_state *pipe_config) 1800 { 1801 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1802 1803 if (INTEL_GEN(dev_priv) >= 11) 1804 icl_ddi_clock_get(encoder, pipe_config); 1805 else if (IS_CANNONLAKE(dev_priv)) 1806 cnl_ddi_clock_get(encoder, pipe_config); 1807 else if (IS_GEN9_LP(dev_priv)) 1808 bxt_ddi_clock_get(encoder, pipe_config); 1809 else if (IS_GEN9_BC(dev_priv)) 1810 skl_ddi_clock_get(encoder, pipe_config); 1811 else if (INTEL_GEN(dev_priv) <= 8) 1812 hsw_ddi_clock_get(encoder, pipe_config); 1813 } 1814 1815 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1816 const struct drm_connector_state *conn_state) 1817 { 1818 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1819 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1820 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1821 u32 temp; 1822 1823 if (!intel_crtc_has_dp_encoder(crtc_state)) 1824 return; 1825 1826 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1827 1828 temp = DP_MSA_MISC_SYNC_CLOCK; 1829 1830 switch (crtc_state->pipe_bpp) { 1831 case 18: 1832 temp |= DP_MSA_MISC_6_BPC; 1833 break; 1834 case 24: 1835 temp |= DP_MSA_MISC_8_BPC; 1836 break; 1837 case 30: 1838 temp |= DP_MSA_MISC_10_BPC; 1839 break; 1840 case 36: 1841 temp |= DP_MSA_MISC_12_BPC; 1842 break; 1843 default: 1844 MISSING_CASE(crtc_state->pipe_bpp); 1845 break; 1846 } 1847 1848 /* nonsense combination */ 1849 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1850 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1851 1852 if (crtc_state->limited_color_range) 1853 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1854 1855 /* 1856 * As per DP 1.2 spec section 2.3.4.3 while sending 1857 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1858 * colorspace information. 1859 */ 1860 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1861 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1862 1863 /* 1864 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1865 * of Color Encoding Format and Content Color Gamut] while sending 1866 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1867 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1868 */ 1869 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1870 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1871 1872 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1873 } 1874 1875 /* 1876 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1877 * 1878 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1879 * intel_ddi_config_transcoder_func(). 1880 */ 1881 static u32 1882 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) 1883 { 1884 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1885 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1886 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1887 enum pipe pipe = crtc->pipe; 1888 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1889 enum port port = encoder->port; 1890 u32 temp; 1891 1892 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1893 temp = TRANS_DDI_FUNC_ENABLE; 1894 if (INTEL_GEN(dev_priv) >= 12) 1895 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1896 else 1897 temp |= TRANS_DDI_SELECT_PORT(port); 1898 1899 switch (crtc_state->pipe_bpp) { 1900 case 18: 1901 temp |= TRANS_DDI_BPC_6; 1902 break; 1903 case 24: 1904 temp |= TRANS_DDI_BPC_8; 1905 break; 1906 case 30: 1907 temp |= TRANS_DDI_BPC_10; 1908 break; 1909 case 36: 1910 temp |= TRANS_DDI_BPC_12; 1911 break; 1912 default: 1913 BUG(); 1914 } 1915 1916 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1917 temp |= TRANS_DDI_PVSYNC; 1918 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1919 temp |= TRANS_DDI_PHSYNC; 1920 1921 if (cpu_transcoder == TRANSCODER_EDP) { 1922 switch (pipe) { 1923 case PIPE_A: 1924 /* On Haswell, can only use the always-on power well for 1925 * eDP when not using the panel fitter, and when not 1926 * using motion blur mitigation (which we don't 1927 * support). */ 1928 if (crtc_state->pch_pfit.force_thru) 1929 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1930 else 1931 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1932 break; 1933 case PIPE_B: 1934 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1935 break; 1936 case PIPE_C: 1937 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1938 break; 1939 default: 1940 BUG(); 1941 break; 1942 } 1943 } 1944 1945 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1946 if (crtc_state->has_hdmi_sink) 1947 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1948 else 1949 temp |= TRANS_DDI_MODE_SELECT_DVI; 1950 1951 if (crtc_state->hdmi_scrambling) 1952 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1953 if (crtc_state->hdmi_high_tmds_clock_ratio) 1954 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1955 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1956 temp |= TRANS_DDI_MODE_SELECT_FDI; 1957 temp |= (crtc_state->fdi_lanes - 1) << 1; 1958 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1959 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1960 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1961 1962 if (INTEL_GEN(dev_priv) >= 12) { 1963 enum transcoder master; 1964 1965 master = crtc_state->mst_master_transcoder; 1966 drm_WARN_ON(&dev_priv->drm, 1967 master == INVALID_TRANSCODER); 1968 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1969 } 1970 } else { 1971 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1972 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1973 } 1974 1975 return temp; 1976 } 1977 1978 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1979 { 1980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1981 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1982 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1983 u32 temp; 1984 1985 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1986 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1987 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1988 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1989 } 1990 1991 /* 1992 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1993 * bit. 1994 */ 1995 static void 1996 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) 1997 { 1998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1999 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2000 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2001 u32 temp; 2002 2003 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 2004 temp &= ~TRANS_DDI_FUNC_ENABLE; 2005 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 2006 } 2007 2008 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 2009 { 2010 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2011 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2012 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2013 u32 val; 2014 2015 val = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2016 val &= ~TRANS_DDI_FUNC_ENABLE; 2017 2018 if (INTEL_GEN(dev_priv) >= 12) { 2019 if (!intel_dp_mst_is_master_trans(crtc_state)) { 2020 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2021 TRANS_DDI_MODE_SELECT_MASK); 2022 } 2023 } else { 2024 val &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 2025 } 2026 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), val); 2027 2028 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 2029 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2030 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); 2031 /* Quirk time at 100ms for reliable operation */ 2032 msleep(100); 2033 } 2034 } 2035 2036 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 2037 bool enable) 2038 { 2039 struct drm_device *dev = intel_encoder->base.dev; 2040 struct drm_i915_private *dev_priv = to_i915(dev); 2041 intel_wakeref_t wakeref; 2042 enum pipe pipe = 0; 2043 int ret = 0; 2044 u32 tmp; 2045 2046 wakeref = intel_display_power_get_if_enabled(dev_priv, 2047 intel_encoder->power_domain); 2048 if (drm_WARN_ON(dev, !wakeref)) 2049 return -ENXIO; 2050 2051 if (drm_WARN_ON(dev, 2052 !intel_encoder->get_hw_state(intel_encoder, &pipe))) { 2053 ret = -EIO; 2054 goto out; 2055 } 2056 2057 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); 2058 if (enable) 2059 tmp |= TRANS_DDI_HDCP_SIGNALLING; 2060 else 2061 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 2062 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); 2063 out: 2064 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 2065 return ret; 2066 } 2067 2068 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 2069 { 2070 struct drm_device *dev = intel_connector->base.dev; 2071 struct drm_i915_private *dev_priv = to_i915(dev); 2072 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 2073 int type = intel_connector->base.connector_type; 2074 enum port port = encoder->port; 2075 enum transcoder cpu_transcoder; 2076 intel_wakeref_t wakeref; 2077 enum pipe pipe = 0; 2078 u32 tmp; 2079 bool ret; 2080 2081 wakeref = intel_display_power_get_if_enabled(dev_priv, 2082 encoder->power_domain); 2083 if (!wakeref) 2084 return false; 2085 2086 if (!encoder->get_hw_state(encoder, &pipe)) { 2087 ret = false; 2088 goto out; 2089 } 2090 2091 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 2092 cpu_transcoder = TRANSCODER_EDP; 2093 else 2094 cpu_transcoder = (enum transcoder) pipe; 2095 2096 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2097 2098 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 2099 case TRANS_DDI_MODE_SELECT_HDMI: 2100 case TRANS_DDI_MODE_SELECT_DVI: 2101 ret = type == DRM_MODE_CONNECTOR_HDMIA; 2102 break; 2103 2104 case TRANS_DDI_MODE_SELECT_DP_SST: 2105 ret = type == DRM_MODE_CONNECTOR_eDP || 2106 type == DRM_MODE_CONNECTOR_DisplayPort; 2107 break; 2108 2109 case TRANS_DDI_MODE_SELECT_DP_MST: 2110 /* if the transcoder is in MST state then 2111 * connector isn't connected */ 2112 ret = false; 2113 break; 2114 2115 case TRANS_DDI_MODE_SELECT_FDI: 2116 ret = type == DRM_MODE_CONNECTOR_VGA; 2117 break; 2118 2119 default: 2120 ret = false; 2121 break; 2122 } 2123 2124 out: 2125 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2126 2127 return ret; 2128 } 2129 2130 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 2131 u8 *pipe_mask, bool *is_dp_mst) 2132 { 2133 struct drm_device *dev = encoder->base.dev; 2134 struct drm_i915_private *dev_priv = to_i915(dev); 2135 enum port port = encoder->port; 2136 intel_wakeref_t wakeref; 2137 enum pipe p; 2138 u32 tmp; 2139 u8 mst_pipe_mask; 2140 2141 *pipe_mask = 0; 2142 *is_dp_mst = false; 2143 2144 wakeref = intel_display_power_get_if_enabled(dev_priv, 2145 encoder->power_domain); 2146 if (!wakeref) 2147 return; 2148 2149 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2150 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2151 goto out; 2152 2153 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { 2154 tmp = intel_de_read(dev_priv, 2155 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2156 2157 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2158 default: 2159 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 2160 /* fallthrough */ 2161 case TRANS_DDI_EDP_INPUT_A_ON: 2162 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2163 *pipe_mask = BIT(PIPE_A); 2164 break; 2165 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2166 *pipe_mask = BIT(PIPE_B); 2167 break; 2168 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2169 *pipe_mask = BIT(PIPE_C); 2170 break; 2171 } 2172 2173 goto out; 2174 } 2175 2176 mst_pipe_mask = 0; 2177 for_each_pipe(dev_priv, p) { 2178 enum transcoder cpu_transcoder = (enum transcoder)p; 2179 unsigned int port_mask, ddi_select; 2180 intel_wakeref_t trans_wakeref; 2181 2182 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 2183 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2184 if (!trans_wakeref) 2185 continue; 2186 2187 if (INTEL_GEN(dev_priv) >= 12) { 2188 port_mask = TGL_TRANS_DDI_PORT_MASK; 2189 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2190 } else { 2191 port_mask = TRANS_DDI_PORT_MASK; 2192 ddi_select = TRANS_DDI_SELECT_PORT(port); 2193 } 2194 2195 tmp = intel_de_read(dev_priv, 2196 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2197 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2198 trans_wakeref); 2199 2200 if ((tmp & port_mask) != ddi_select) 2201 continue; 2202 2203 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2204 TRANS_DDI_MODE_SELECT_DP_MST) 2205 mst_pipe_mask |= BIT(p); 2206 2207 *pipe_mask |= BIT(p); 2208 } 2209 2210 if (!*pipe_mask) 2211 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", 2212 encoder->base.base.id, encoder->base.name); 2213 2214 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2215 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2216 encoder->base.base.id, encoder->base.name, 2217 *pipe_mask); 2218 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2219 } 2220 2221 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2222 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2223 encoder->base.base.id, encoder->base.name, 2224 *pipe_mask, mst_pipe_mask); 2225 else 2226 *is_dp_mst = mst_pipe_mask; 2227 2228 out: 2229 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2230 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 2231 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2232 BXT_PHY_LANE_POWERDOWN_ACK | 2233 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2234 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " 2235 "(PHY_CTL %08x)\n", encoder->base.base.id, 2236 encoder->base.name, tmp); 2237 } 2238 2239 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2240 } 2241 2242 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2243 enum pipe *pipe) 2244 { 2245 u8 pipe_mask; 2246 bool is_mst; 2247 2248 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2249 2250 if (is_mst || !pipe_mask) 2251 return false; 2252 2253 *pipe = ffs(pipe_mask) - 1; 2254 2255 return true; 2256 } 2257 2258 static inline enum intel_display_power_domain 2259 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2260 { 2261 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2262 * DC states enabled at the same time, while for driver initiated AUX 2263 * transfers we need the same AUX IOs to be powered but with DC states 2264 * disabled. Accordingly use the AUX power domain here which leaves DC 2265 * states enabled. 2266 * However, for non-A AUX ports the corresponding non-EDP transcoders 2267 * would have already enabled power well 2 and DC_OFF. This means we can 2268 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2269 * specific AUX_IO reference without powering up any extra wells. 2270 * Note that PSR is enabled only on Port A even though this function 2271 * returns the correct domain for other ports too. 2272 */ 2273 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2274 intel_aux_power_domain(dig_port); 2275 } 2276 2277 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2278 struct intel_crtc_state *crtc_state) 2279 { 2280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2281 struct intel_digital_port *dig_port; 2282 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2283 2284 /* 2285 * TODO: Add support for MST encoders. Atm, the following should never 2286 * happen since fake-MST encoders don't set their get_power_domains() 2287 * hook. 2288 */ 2289 if (drm_WARN_ON(&dev_priv->drm, 2290 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2291 return; 2292 2293 dig_port = enc_to_dig_port(encoder); 2294 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2295 2296 /* 2297 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2298 * ports. 2299 */ 2300 if (intel_crtc_has_dp_encoder(crtc_state) || 2301 intel_phy_is_tc(dev_priv, phy)) 2302 intel_display_power_get(dev_priv, 2303 intel_ddi_main_link_aux_domain(dig_port)); 2304 2305 /* 2306 * VDSC power is needed when DSC is enabled 2307 */ 2308 if (crtc_state->dsc.compression_enable) 2309 intel_display_power_get(dev_priv, 2310 intel_dsc_power_domain(crtc_state)); 2311 } 2312 2313 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 2314 { 2315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2316 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2317 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 2318 enum port port = encoder->port; 2319 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2320 2321 if (cpu_transcoder != TRANSCODER_EDP) { 2322 if (INTEL_GEN(dev_priv) >= 12) 2323 intel_de_write(dev_priv, 2324 TRANS_CLK_SEL(cpu_transcoder), 2325 TGL_TRANS_CLK_SEL_PORT(port)); 2326 else 2327 intel_de_write(dev_priv, 2328 TRANS_CLK_SEL(cpu_transcoder), 2329 TRANS_CLK_SEL_PORT(port)); 2330 } 2331 } 2332 2333 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2334 { 2335 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2336 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2337 2338 if (cpu_transcoder != TRANSCODER_EDP) { 2339 if (INTEL_GEN(dev_priv) >= 12) 2340 intel_de_write(dev_priv, 2341 TRANS_CLK_SEL(cpu_transcoder), 2342 TGL_TRANS_CLK_SEL_DISABLED); 2343 else 2344 intel_de_write(dev_priv, 2345 TRANS_CLK_SEL(cpu_transcoder), 2346 TRANS_CLK_SEL_DISABLED); 2347 } 2348 } 2349 2350 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2351 enum port port, u8 iboost) 2352 { 2353 u32 tmp; 2354 2355 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2356 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2357 if (iboost) 2358 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2359 else 2360 tmp |= BALANCE_LEG_DISABLE(port); 2361 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2362 } 2363 2364 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2365 int level, enum intel_output_type type) 2366 { 2367 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2369 enum port port = encoder->port; 2370 u8 iboost; 2371 2372 if (type == INTEL_OUTPUT_HDMI) 2373 iboost = intel_bios_hdmi_boost_level(encoder); 2374 else 2375 iboost = intel_bios_dp_boost_level(encoder); 2376 2377 if (iboost == 0) { 2378 const struct ddi_buf_trans *ddi_translations; 2379 int n_entries; 2380 2381 if (type == INTEL_OUTPUT_HDMI) 2382 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2383 else if (type == INTEL_OUTPUT_EDP) 2384 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2385 else 2386 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2387 2388 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2389 return; 2390 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2391 level = n_entries - 1; 2392 2393 iboost = ddi_translations[level].i_boost; 2394 } 2395 2396 /* Make sure that the requested I_boost is valid */ 2397 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2398 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2399 return; 2400 } 2401 2402 _skl_ddi_set_iboost(dev_priv, port, iboost); 2403 2404 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2405 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2406 } 2407 2408 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2409 int level, enum intel_output_type type) 2410 { 2411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2412 const struct bxt_ddi_buf_trans *ddi_translations; 2413 enum port port = encoder->port; 2414 int n_entries; 2415 2416 if (type == INTEL_OUTPUT_HDMI) 2417 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2418 else if (type == INTEL_OUTPUT_EDP) 2419 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2420 else 2421 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2422 2423 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2424 return; 2425 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2426 level = n_entries - 1; 2427 2428 bxt_ddi_phy_set_signal_level(dev_priv, port, 2429 ddi_translations[level].margin, 2430 ddi_translations[level].scale, 2431 ddi_translations[level].enable, 2432 ddi_translations[level].deemphasis); 2433 } 2434 2435 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2436 { 2437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2438 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2439 enum port port = encoder->port; 2440 enum phy phy = intel_port_to_phy(dev_priv, port); 2441 int n_entries; 2442 2443 if (INTEL_GEN(dev_priv) >= 12) { 2444 if (intel_phy_is_combo(dev_priv, phy)) 2445 tgl_get_combo_buf_trans(dev_priv, encoder->type, 2446 intel_dp->link_rate, &n_entries); 2447 else 2448 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2449 } else if (INTEL_GEN(dev_priv) == 11) { 2450 if (IS_ELKHARTLAKE(dev_priv)) 2451 ehl_get_combo_buf_trans(dev_priv, encoder->type, 2452 intel_dp->link_rate, &n_entries); 2453 else if (intel_phy_is_combo(dev_priv, phy)) 2454 icl_get_combo_buf_trans(dev_priv, encoder->type, 2455 intel_dp->link_rate, &n_entries); 2456 else 2457 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2458 } else if (IS_CANNONLAKE(dev_priv)) { 2459 if (encoder->type == INTEL_OUTPUT_EDP) 2460 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2461 else 2462 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2463 } else if (IS_GEN9_LP(dev_priv)) { 2464 if (encoder->type == INTEL_OUTPUT_EDP) 2465 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2466 else 2467 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2468 } else { 2469 if (encoder->type == INTEL_OUTPUT_EDP) 2470 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2471 else 2472 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2473 } 2474 2475 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2476 n_entries = 1; 2477 if (drm_WARN_ON(&dev_priv->drm, 2478 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2479 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2480 2481 return index_to_dp_signal_levels[n_entries - 1] & 2482 DP_TRAIN_VOLTAGE_SWING_MASK; 2483 } 2484 2485 /* 2486 * We assume that the full set of pre-emphasis values can be 2487 * used on all DDI platforms. Should that change we need to 2488 * rethink this code. 2489 */ 2490 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2491 { 2492 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2493 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2494 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2496 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2498 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2500 default: 2501 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2502 } 2503 } 2504 2505 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2506 int level, enum intel_output_type type) 2507 { 2508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2509 const struct cnl_ddi_buf_trans *ddi_translations; 2510 enum port port = encoder->port; 2511 int n_entries, ln; 2512 u32 val; 2513 2514 if (type == INTEL_OUTPUT_HDMI) 2515 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2516 else if (type == INTEL_OUTPUT_EDP) 2517 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2518 else 2519 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2520 2521 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2522 return; 2523 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2524 level = n_entries - 1; 2525 2526 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2527 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2528 val &= ~SCALING_MODE_SEL_MASK; 2529 val |= SCALING_MODE_SEL(2); 2530 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2531 2532 /* Program PORT_TX_DW2 */ 2533 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2534 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2535 RCOMP_SCALAR_MASK); 2536 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2537 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2538 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2539 val |= RCOMP_SCALAR(0x98); 2540 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2541 2542 /* Program PORT_TX_DW4 */ 2543 /* We cannot write to GRP. It would overrite individual loadgen */ 2544 for (ln = 0; ln < 4; ln++) { 2545 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2546 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2547 CURSOR_COEFF_MASK); 2548 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2549 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2550 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2551 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2552 } 2553 2554 /* Program PORT_TX_DW5 */ 2555 /* All DW5 values are fixed for every table entry */ 2556 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2557 val &= ~RTERM_SELECT_MASK; 2558 val |= RTERM_SELECT(6); 2559 val |= TAP3_DISABLE; 2560 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2561 2562 /* Program PORT_TX_DW7 */ 2563 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2564 val &= ~N_SCALAR_MASK; 2565 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2566 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2567 } 2568 2569 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2570 int level, enum intel_output_type type) 2571 { 2572 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2573 enum port port = encoder->port; 2574 int width, rate, ln; 2575 u32 val; 2576 2577 if (type == INTEL_OUTPUT_HDMI) { 2578 width = 4; 2579 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2580 } else { 2581 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2582 2583 width = intel_dp->lane_count; 2584 rate = intel_dp->link_rate; 2585 } 2586 2587 /* 2588 * 1. If port type is eDP or DP, 2589 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2590 * else clear to 0b. 2591 */ 2592 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2593 if (type != INTEL_OUTPUT_HDMI) 2594 val |= COMMON_KEEPER_EN; 2595 else 2596 val &= ~COMMON_KEEPER_EN; 2597 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2598 2599 /* 2. Program loadgen select */ 2600 /* 2601 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2602 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2603 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2604 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2605 */ 2606 for (ln = 0; ln <= 3; ln++) { 2607 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2608 val &= ~LOADGEN_SELECT; 2609 2610 if ((rate <= 600000 && width == 4 && ln >= 1) || 2611 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2612 val |= LOADGEN_SELECT; 2613 } 2614 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2615 } 2616 2617 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2618 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2619 val |= SUS_CLOCK_CONFIG; 2620 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2621 2622 /* 4. Clear training enable to change swing values */ 2623 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2624 val &= ~TX_TRAINING_EN; 2625 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2626 2627 /* 5. Program swing and de-emphasis */ 2628 cnl_ddi_vswing_program(encoder, level, type); 2629 2630 /* 6. Set training enable to trigger update */ 2631 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2632 val |= TX_TRAINING_EN; 2633 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2634 } 2635 2636 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2637 u32 level, enum phy phy, int type, 2638 int rate) 2639 { 2640 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2641 u32 n_entries, val; 2642 int ln; 2643 2644 if (INTEL_GEN(dev_priv) >= 12) 2645 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, 2646 &n_entries); 2647 else if (IS_ELKHARTLAKE(dev_priv)) 2648 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, 2649 &n_entries); 2650 else 2651 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2652 &n_entries); 2653 if (!ddi_translations) 2654 return; 2655 2656 if (level >= n_entries) { 2657 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 2658 level = n_entries - 1; 2659 } 2660 2661 /* Set PORT_TX_DW5 */ 2662 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2663 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2664 TAP2_DISABLE | TAP3_DISABLE); 2665 val |= SCALING_MODE_SEL(0x2); 2666 val |= RTERM_SELECT(0x6); 2667 val |= TAP3_DISABLE; 2668 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2669 2670 /* Program PORT_TX_DW2 */ 2671 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2672 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2673 RCOMP_SCALAR_MASK); 2674 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2675 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2676 /* Program Rcomp scalar for every table entry */ 2677 val |= RCOMP_SCALAR(0x98); 2678 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2679 2680 /* Program PORT_TX_DW4 */ 2681 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2682 for (ln = 0; ln <= 3; ln++) { 2683 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2684 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2685 CURSOR_COEFF_MASK); 2686 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2687 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2688 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2689 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2690 } 2691 2692 /* Program PORT_TX_DW7 */ 2693 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2694 val &= ~N_SCALAR_MASK; 2695 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2696 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2697 } 2698 2699 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2700 u32 level, 2701 enum intel_output_type type) 2702 { 2703 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2704 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2705 int width = 0; 2706 int rate = 0; 2707 u32 val; 2708 int ln = 0; 2709 2710 if (type == INTEL_OUTPUT_HDMI) { 2711 width = 4; 2712 /* Rate is always < than 6GHz for HDMI */ 2713 } else { 2714 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2715 2716 width = intel_dp->lane_count; 2717 rate = intel_dp->link_rate; 2718 } 2719 2720 /* 2721 * 1. If port type is eDP or DP, 2722 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2723 * else clear to 0b. 2724 */ 2725 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2726 if (type == INTEL_OUTPUT_HDMI) 2727 val &= ~COMMON_KEEPER_EN; 2728 else 2729 val |= COMMON_KEEPER_EN; 2730 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2731 2732 /* 2. Program loadgen select */ 2733 /* 2734 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2735 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2736 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2737 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2738 */ 2739 for (ln = 0; ln <= 3; ln++) { 2740 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2741 val &= ~LOADGEN_SELECT; 2742 2743 if ((rate <= 600000 && width == 4 && ln >= 1) || 2744 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2745 val |= LOADGEN_SELECT; 2746 } 2747 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2748 } 2749 2750 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2751 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2752 val |= SUS_CLOCK_CONFIG; 2753 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2754 2755 /* 4. Clear training enable to change swing values */ 2756 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2757 val &= ~TX_TRAINING_EN; 2758 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2759 2760 /* 5. Program swing and de-emphasis */ 2761 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2762 2763 /* 6. Set training enable to trigger update */ 2764 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2765 val |= TX_TRAINING_EN; 2766 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2767 } 2768 2769 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2770 int link_clock, 2771 u32 level) 2772 { 2773 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2774 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2775 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2776 u32 n_entries, val; 2777 int ln; 2778 2779 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2780 ddi_translations = icl_mg_phy_ddi_translations; 2781 /* The table does not have values for level 3 and level 9. */ 2782 if (level >= n_entries || level == 3 || level == 9) { 2783 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", 2784 level, n_entries - 2); 2785 level = n_entries - 2; 2786 } 2787 2788 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2789 for (ln = 0; ln < 2; ln++) { 2790 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2791 val &= ~CRI_USE_FS32; 2792 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2793 2794 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2795 val &= ~CRI_USE_FS32; 2796 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2797 } 2798 2799 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2800 for (ln = 0; ln < 2; ln++) { 2801 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2802 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2803 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2804 ddi_translations[level].cri_txdeemph_override_17_12); 2805 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2806 2807 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2808 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2809 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2810 ddi_translations[level].cri_txdeemph_override_17_12); 2811 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2812 } 2813 2814 /* Program MG_TX_DRVCTRL with values from vswing table */ 2815 for (ln = 0; ln < 2; ln++) { 2816 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2817 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2818 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2819 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2820 ddi_translations[level].cri_txdeemph_override_5_0) | 2821 CRI_TXDEEMPH_OVERRIDE_11_6( 2822 ddi_translations[level].cri_txdeemph_override_11_6) | 2823 CRI_TXDEEMPH_OVERRIDE_EN; 2824 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2825 2826 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2827 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2828 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2829 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2830 ddi_translations[level].cri_txdeemph_override_5_0) | 2831 CRI_TXDEEMPH_OVERRIDE_11_6( 2832 ddi_translations[level].cri_txdeemph_override_11_6) | 2833 CRI_TXDEEMPH_OVERRIDE_EN; 2834 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2835 2836 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2837 } 2838 2839 /* 2840 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2841 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2842 * values from table for which TX1 and TX2 enabled. 2843 */ 2844 for (ln = 0; ln < 2; ln++) { 2845 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2846 if (link_clock < 300000) 2847 val |= CFG_LOW_RATE_LKREN_EN; 2848 else 2849 val &= ~CFG_LOW_RATE_LKREN_EN; 2850 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2851 } 2852 2853 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2854 for (ln = 0; ln < 2; ln++) { 2855 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2856 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2857 if (link_clock <= 500000) { 2858 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2859 } else { 2860 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2861 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2862 } 2863 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2864 2865 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2866 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2867 if (link_clock <= 500000) { 2868 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2869 } else { 2870 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2871 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2872 } 2873 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2874 } 2875 2876 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2877 for (ln = 0; ln < 2; ln++) { 2878 val = intel_de_read(dev_priv, 2879 MG_TX1_PISO_READLOAD(ln, tc_port)); 2880 val |= CRI_CALCINIT; 2881 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2882 val); 2883 2884 val = intel_de_read(dev_priv, 2885 MG_TX2_PISO_READLOAD(ln, tc_port)); 2886 val |= CRI_CALCINIT; 2887 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2888 val); 2889 } 2890 } 2891 2892 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2893 int link_clock, 2894 u32 level, 2895 enum intel_output_type type) 2896 { 2897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2898 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2899 2900 if (intel_phy_is_combo(dev_priv, phy)) 2901 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2902 else 2903 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); 2904 } 2905 2906 static void 2907 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2908 u32 level) 2909 { 2910 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2911 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2912 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2913 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2914 2915 if (encoder->type == INTEL_OUTPUT_HDMI) { 2916 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 2917 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; 2918 } else { 2919 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2920 ddi_translations = tgl_dkl_phy_dp_ddi_trans; 2921 } 2922 2923 if (level >= n_entries) 2924 level = n_entries - 1; 2925 2926 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2927 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2928 DKL_TX_VSWING_CONTROL_MASK); 2929 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2930 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2931 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2932 2933 for (ln = 0; ln < 2; ln++) { 2934 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2935 HIP_INDEX_VAL(tc_port, ln)); 2936 2937 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2938 2939 /* All the registers are RMW */ 2940 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2941 val &= ~dpcnt_mask; 2942 val |= dpcnt_val; 2943 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2944 2945 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2946 val &= ~dpcnt_mask; 2947 val |= dpcnt_val; 2948 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2949 2950 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2951 val &= ~DKL_TX_DP20BITMODE; 2952 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2953 } 2954 } 2955 2956 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2957 int link_clock, 2958 u32 level, 2959 enum intel_output_type type) 2960 { 2961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2962 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2963 2964 if (intel_phy_is_combo(dev_priv, phy)) 2965 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2966 else 2967 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); 2968 } 2969 2970 static u32 translate_signal_level(int signal_levels) 2971 { 2972 int i; 2973 2974 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2975 if (index_to_dp_signal_levels[i] == signal_levels) 2976 return i; 2977 } 2978 2979 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2980 signal_levels); 2981 2982 return 0; 2983 } 2984 2985 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2986 { 2987 u8 train_set = intel_dp->train_set[0]; 2988 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2989 DP_TRAIN_PRE_EMPHASIS_MASK); 2990 2991 return translate_signal_level(signal_levels); 2992 } 2993 2994 u32 bxt_signal_levels(struct intel_dp *intel_dp) 2995 { 2996 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2997 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2998 struct intel_encoder *encoder = &dport->base; 2999 int level = intel_ddi_dp_level(intel_dp); 3000 3001 if (INTEL_GEN(dev_priv) >= 12) 3002 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 3003 level, encoder->type); 3004 else if (INTEL_GEN(dev_priv) >= 11) 3005 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 3006 level, encoder->type); 3007 else if (IS_CANNONLAKE(dev_priv)) 3008 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3009 else 3010 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3011 3012 return 0; 3013 } 3014 3015 u32 ddi_signal_levels(struct intel_dp *intel_dp) 3016 { 3017 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 3018 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 3019 struct intel_encoder *encoder = &dport->base; 3020 int level = intel_ddi_dp_level(intel_dp); 3021 3022 if (IS_GEN9_BC(dev_priv)) 3023 skl_ddi_set_iboost(encoder, level, encoder->type); 3024 3025 return DDI_BUF_TRANS_SELECT(level); 3026 } 3027 3028 static inline 3029 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 3030 enum phy phy) 3031 { 3032 if (intel_phy_is_combo(dev_priv, phy)) { 3033 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 3034 } else if (intel_phy_is_tc(dev_priv, phy)) { 3035 enum tc_port tc_port = intel_port_to_tc(dev_priv, 3036 (enum port)phy); 3037 3038 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 3039 } 3040 3041 return 0; 3042 } 3043 3044 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 3045 const struct intel_crtc_state *crtc_state) 3046 { 3047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3048 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3049 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3050 u32 val; 3051 3052 mutex_lock(&dev_priv->dpll_lock); 3053 3054 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3055 drm_WARN_ON(&dev_priv->drm, 3056 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 3057 3058 if (intel_phy_is_combo(dev_priv, phy)) { 3059 /* 3060 * Even though this register references DDIs, note that we 3061 * want to pass the PHY rather than the port (DDI). For 3062 * ICL, port=phy in all cases so it doesn't matter, but for 3063 * EHL the bspec notes the following: 3064 * 3065 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 3066 * Clock Select chooses the PLL for both DDIA and DDID and 3067 * drives port A in all cases." 3068 */ 3069 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 3070 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 3071 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3072 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 3073 } 3074 3075 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3076 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3077 3078 mutex_unlock(&dev_priv->dpll_lock); 3079 } 3080 3081 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 3082 { 3083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3084 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3085 u32 val; 3086 3087 mutex_lock(&dev_priv->dpll_lock); 3088 3089 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3090 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3091 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3092 3093 mutex_unlock(&dev_priv->dpll_lock); 3094 } 3095 3096 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 3097 u32 port_mask, bool ddi_clk_needed) 3098 { 3099 enum port port; 3100 u32 val; 3101 3102 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3103 for_each_port_masked(port, port_mask) { 3104 enum phy phy = intel_port_to_phy(dev_priv, port); 3105 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 3106 phy); 3107 3108 if (ddi_clk_needed == !ddi_clk_off) 3109 continue; 3110 3111 /* 3112 * Punt on the case now where clock is gated, but it would 3113 * be needed by the port. Something else is really broken then. 3114 */ 3115 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 3116 continue; 3117 3118 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 3119 phy_name(phy)); 3120 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3121 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3122 } 3123 } 3124 3125 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 3126 { 3127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3128 u32 port_mask; 3129 bool ddi_clk_needed; 3130 3131 /* 3132 * In case of DP MST, we sanitize the primary encoder only, not the 3133 * virtual ones. 3134 */ 3135 if (encoder->type == INTEL_OUTPUT_DP_MST) 3136 return; 3137 3138 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3139 u8 pipe_mask; 3140 bool is_mst; 3141 3142 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3143 /* 3144 * In the unlikely case that BIOS enables DP in MST mode, just 3145 * warn since our MST HW readout is incomplete. 3146 */ 3147 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 3148 return; 3149 } 3150 3151 port_mask = BIT(encoder->port); 3152 ddi_clk_needed = encoder->base.crtc; 3153 3154 if (encoder->type == INTEL_OUTPUT_DSI) { 3155 struct intel_encoder *other_encoder; 3156 3157 port_mask = intel_dsi_encoder_ports(encoder); 3158 /* 3159 * Sanity check that we haven't incorrectly registered another 3160 * encoder using any of the ports of this DSI encoder. 3161 */ 3162 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3163 if (other_encoder == encoder) 3164 continue; 3165 3166 if (drm_WARN_ON(&dev_priv->drm, 3167 port_mask & BIT(other_encoder->port))) 3168 return; 3169 } 3170 /* 3171 * For DSI we keep the ddi clocks gated 3172 * except during enable/disable sequence. 3173 */ 3174 ddi_clk_needed = false; 3175 } 3176 3177 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 3178 } 3179 3180 static void intel_ddi_clk_select(struct intel_encoder *encoder, 3181 const struct intel_crtc_state *crtc_state) 3182 { 3183 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3184 enum port port = encoder->port; 3185 enum phy phy = intel_port_to_phy(dev_priv, port); 3186 u32 val; 3187 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3188 3189 if (drm_WARN_ON(&dev_priv->drm, !pll)) 3190 return; 3191 3192 mutex_lock(&dev_priv->dpll_lock); 3193 3194 if (INTEL_GEN(dev_priv) >= 11) { 3195 if (!intel_phy_is_combo(dev_priv, phy)) 3196 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3197 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3198 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 3199 /* 3200 * MG does not exist but the programming is required 3201 * to ungate DDIC and DDID 3202 */ 3203 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3204 DDI_CLK_SEL_MG); 3205 } else if (IS_CANNONLAKE(dev_priv)) { 3206 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3207 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3208 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3209 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3210 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3211 3212 /* 3213 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3214 * This step and the step before must be done with separate 3215 * register writes. 3216 */ 3217 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3218 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3219 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3220 } else if (IS_GEN9_BC(dev_priv)) { 3221 /* DDI -> PLL mapping */ 3222 val = intel_de_read(dev_priv, DPLL_CTRL2); 3223 3224 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3225 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3226 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3227 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3228 3229 intel_de_write(dev_priv, DPLL_CTRL2, val); 3230 3231 } else if (INTEL_GEN(dev_priv) < 9) { 3232 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3233 hsw_pll_to_ddi_pll_sel(pll)); 3234 } 3235 3236 mutex_unlock(&dev_priv->dpll_lock); 3237 } 3238 3239 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3240 { 3241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3242 enum port port = encoder->port; 3243 enum phy phy = intel_port_to_phy(dev_priv, port); 3244 3245 if (INTEL_GEN(dev_priv) >= 11) { 3246 if (!intel_phy_is_combo(dev_priv, phy) || 3247 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 3248 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3249 DDI_CLK_SEL_NONE); 3250 } else if (IS_CANNONLAKE(dev_priv)) { 3251 intel_de_write(dev_priv, DPCLKA_CFGCR0, 3252 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3253 } else if (IS_GEN9_BC(dev_priv)) { 3254 intel_de_write(dev_priv, DPLL_CTRL2, 3255 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 3256 } else if (INTEL_GEN(dev_priv) < 9) { 3257 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3258 PORT_CLK_SEL_NONE); 3259 } 3260 } 3261 3262 static void 3263 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 3264 const struct intel_crtc_state *crtc_state) 3265 { 3266 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3267 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 3268 u32 ln0, ln1, pin_assignment; 3269 u8 width; 3270 3271 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3272 return; 3273 3274 if (INTEL_GEN(dev_priv) >= 12) { 3275 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3276 HIP_INDEX_VAL(tc_port, 0x0)); 3277 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3278 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3279 HIP_INDEX_VAL(tc_port, 0x1)); 3280 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3281 } else { 3282 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3283 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3284 } 3285 3286 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); 3287 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3288 3289 /* DPPATC */ 3290 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 3291 width = crtc_state->lane_count; 3292 3293 switch (pin_assignment) { 3294 case 0x0: 3295 drm_WARN_ON(&dev_priv->drm, 3296 intel_dig_port->tc_mode != TC_PORT_LEGACY); 3297 if (width == 1) { 3298 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3299 } else { 3300 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3301 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3302 } 3303 break; 3304 case 0x1: 3305 if (width == 4) { 3306 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3307 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3308 } 3309 break; 3310 case 0x2: 3311 if (width == 2) { 3312 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3313 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3314 } 3315 break; 3316 case 0x3: 3317 case 0x5: 3318 if (width == 1) { 3319 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3320 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3321 } else { 3322 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3323 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3324 } 3325 break; 3326 case 0x4: 3327 case 0x6: 3328 if (width == 1) { 3329 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3330 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3331 } else { 3332 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3333 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3334 } 3335 break; 3336 default: 3337 MISSING_CASE(pin_assignment); 3338 } 3339 3340 if (INTEL_GEN(dev_priv) >= 12) { 3341 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3342 HIP_INDEX_VAL(tc_port, 0x0)); 3343 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3344 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3345 HIP_INDEX_VAL(tc_port, 0x1)); 3346 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3347 } else { 3348 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3349 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3350 } 3351 } 3352 3353 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3354 const struct intel_crtc_state *crtc_state) 3355 { 3356 if (!crtc_state->fec_enable) 3357 return; 3358 3359 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3360 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); 3361 } 3362 3363 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3364 const struct intel_crtc_state *crtc_state) 3365 { 3366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3367 struct intel_dp *intel_dp; 3368 u32 val; 3369 3370 if (!crtc_state->fec_enable) 3371 return; 3372 3373 intel_dp = enc_to_intel_dp(encoder); 3374 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3375 val |= DP_TP_CTL_FEC_ENABLE; 3376 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3377 3378 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3379 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3380 DRM_ERROR("Timed out waiting for FEC Enable Status\n"); 3381 } 3382 3383 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3384 const struct intel_crtc_state *crtc_state) 3385 { 3386 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3387 struct intel_dp *intel_dp; 3388 u32 val; 3389 3390 if (!crtc_state->fec_enable) 3391 return; 3392 3393 intel_dp = enc_to_intel_dp(encoder); 3394 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3395 val &= ~DP_TP_CTL_FEC_ENABLE; 3396 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3397 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3398 } 3399 3400 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, 3401 const struct intel_crtc_state *crtc_state, 3402 const struct drm_connector_state *conn_state) 3403 { 3404 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3406 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3407 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3408 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3409 int level = intel_ddi_dp_level(intel_dp); 3410 enum transcoder transcoder = crtc_state->cpu_transcoder; 3411 3412 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3413 crtc_state->lane_count, is_mst); 3414 3415 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3416 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3417 3418 /* 3419 * 1. Enable Power Wells 3420 * 3421 * This was handled at the beginning of intel_atomic_commit_tail(), 3422 * before we called down into this function. 3423 */ 3424 3425 /* 2. Enable Panel Power if PPS is required */ 3426 intel_edp_panel_on(intel_dp); 3427 3428 /* 3429 * 3. For non-TBT Type-C ports, set FIA lane count 3430 * (DFLEXDPSP.DPX4TXLATC) 3431 * 3432 * This was done before tgl_ddi_pre_enable_dp by 3433 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3434 */ 3435 3436 /* 3437 * 4. Enable the port PLL. 3438 * 3439 * The PLL enabling itself was already done before this function by 3440 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3441 * configure the PLL to port mapping here. 3442 */ 3443 intel_ddi_clk_select(encoder, crtc_state); 3444 3445 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3446 if (!intel_phy_is_tc(dev_priv, phy) || 3447 dig_port->tc_mode != TC_PORT_TBT_ALT) 3448 intel_display_power_get(dev_priv, 3449 dig_port->ddi_io_power_domain); 3450 3451 /* 6. Program DP_MODE */ 3452 icl_program_mg_dp_mode(dig_port, crtc_state); 3453 3454 /* 3455 * 7. The rest of the below are substeps under the bspec's "Enable and 3456 * Train Display Port" step. Note that steps that are specific to 3457 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3458 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3459 * us when active_mst_links==0, so any steps designated for "single 3460 * stream or multi-stream master transcoder" can just be performed 3461 * unconditionally here. 3462 */ 3463 3464 /* 3465 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3466 * Transcoder. 3467 */ 3468 intel_ddi_enable_pipe_clock(crtc_state); 3469 3470 /* 3471 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3472 * Transport Select 3473 */ 3474 intel_ddi_config_transcoder_func(crtc_state); 3475 3476 /* 3477 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3478 * selected 3479 * 3480 * This will be handled by the intel_dp_start_link_train() farther 3481 * down this function. 3482 */ 3483 3484 /* 7.e Configure voltage swing and related IO settings */ 3485 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3486 encoder->type); 3487 3488 /* 3489 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3490 * the used lanes of the DDI. 3491 */ 3492 if (intel_phy_is_combo(dev_priv, phy)) { 3493 bool lane_reversal = 3494 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3495 3496 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3497 crtc_state->lane_count, 3498 lane_reversal); 3499 } 3500 3501 /* 3502 * 7.g Configure and enable DDI_BUF_CTL 3503 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3504 * after 500 us. 3505 * 3506 * We only configure what the register value will be here. Actual 3507 * enabling happens during link training farther down. 3508 */ 3509 intel_ddi_init_dp_buf_reg(encoder); 3510 3511 if (!is_mst) 3512 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3513 3514 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3515 /* 3516 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3517 * in the FEC_CONFIGURATION register to 1 before initiating link 3518 * training 3519 */ 3520 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3521 3522 /* 3523 * 7.i Follow DisplayPort specification training sequence (see notes for 3524 * failure handling) 3525 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3526 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3527 * (timeout after 800 us) 3528 */ 3529 intel_dp_start_link_train(intel_dp); 3530 3531 /* 7.k Set DP_TP_CTL link training to Normal */ 3532 if (!is_trans_port_sync_mode(crtc_state)) 3533 intel_dp_stop_link_train(intel_dp); 3534 3535 /* 7.l Configure and enable FEC if needed */ 3536 intel_ddi_enable_fec(encoder, crtc_state); 3537 intel_dsc_enable(encoder, crtc_state); 3538 } 3539 3540 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 3541 const struct intel_crtc_state *crtc_state, 3542 const struct drm_connector_state *conn_state) 3543 { 3544 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3546 enum port port = encoder->port; 3547 enum phy phy = intel_port_to_phy(dev_priv, port); 3548 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3549 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3550 int level = intel_ddi_dp_level(intel_dp); 3551 3552 if (INTEL_GEN(dev_priv) < 11) 3553 drm_WARN_ON(&dev_priv->drm, 3554 is_mst && (port == PORT_A || port == PORT_E)); 3555 else 3556 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3557 3558 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3559 crtc_state->lane_count, is_mst); 3560 3561 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); 3562 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); 3563 3564 intel_edp_panel_on(intel_dp); 3565 3566 intel_ddi_clk_select(encoder, crtc_state); 3567 3568 if (!intel_phy_is_tc(dev_priv, phy) || 3569 dig_port->tc_mode != TC_PORT_TBT_ALT) 3570 intel_display_power_get(dev_priv, 3571 dig_port->ddi_io_power_domain); 3572 3573 icl_program_mg_dp_mode(dig_port, crtc_state); 3574 3575 if (INTEL_GEN(dev_priv) >= 11) 3576 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3577 level, encoder->type); 3578 else if (IS_CANNONLAKE(dev_priv)) 3579 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3580 else if (IS_GEN9_LP(dev_priv)) 3581 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3582 else 3583 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3584 3585 if (intel_phy_is_combo(dev_priv, phy)) { 3586 bool lane_reversal = 3587 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3588 3589 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3590 crtc_state->lane_count, 3591 lane_reversal); 3592 } 3593 3594 intel_ddi_init_dp_buf_reg(encoder); 3595 if (!is_mst) 3596 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3597 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3598 true); 3599 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3600 intel_dp_start_link_train(intel_dp); 3601 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3602 !is_trans_port_sync_mode(crtc_state)) 3603 intel_dp_stop_link_train(intel_dp); 3604 3605 intel_ddi_enable_fec(encoder, crtc_state); 3606 3607 if (!is_mst) 3608 intel_ddi_enable_pipe_clock(crtc_state); 3609 3610 intel_dsc_enable(encoder, crtc_state); 3611 } 3612 3613 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 3614 const struct intel_crtc_state *crtc_state, 3615 const struct drm_connector_state *conn_state) 3616 { 3617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3618 3619 if (INTEL_GEN(dev_priv) >= 12) 3620 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3621 else 3622 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3623 3624 /* MST will call a setting of MSA after an allocating of Virtual Channel 3625 * from MST encoder pre_enable callback. 3626 */ 3627 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3628 intel_ddi_set_dp_msa(crtc_state, conn_state); 3629 3630 intel_dp_set_m_n(crtc_state, M1_N1); 3631 } 3632 } 3633 3634 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 3635 const struct intel_crtc_state *crtc_state, 3636 const struct drm_connector_state *conn_state) 3637 { 3638 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3639 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3640 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3641 int level = intel_ddi_hdmi_level(encoder); 3642 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3643 3644 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3645 intel_ddi_clk_select(encoder, crtc_state); 3646 3647 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3648 3649 icl_program_mg_dp_mode(dig_port, crtc_state); 3650 3651 if (INTEL_GEN(dev_priv) >= 12) 3652 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3653 level, INTEL_OUTPUT_HDMI); 3654 else if (INTEL_GEN(dev_priv) == 11) 3655 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3656 level, INTEL_OUTPUT_HDMI); 3657 else if (IS_CANNONLAKE(dev_priv)) 3658 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3659 else if (IS_GEN9_LP(dev_priv)) 3660 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3661 else 3662 intel_prepare_hdmi_ddi_buffers(encoder, level); 3663 3664 if (IS_GEN9_BC(dev_priv)) 3665 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3666 3667 intel_ddi_enable_pipe_clock(crtc_state); 3668 3669 intel_dig_port->set_infoframes(encoder, 3670 crtc_state->has_infoframe, 3671 crtc_state, conn_state); 3672 } 3673 3674 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 3675 const struct intel_crtc_state *crtc_state, 3676 const struct drm_connector_state *conn_state) 3677 { 3678 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3679 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3680 enum pipe pipe = crtc->pipe; 3681 3682 /* 3683 * When called from DP MST code: 3684 * - conn_state will be NULL 3685 * - encoder will be the main encoder (ie. mst->primary) 3686 * - the main connector associated with this port 3687 * won't be active or linked to a crtc 3688 * - crtc_state will be the state of the first stream to 3689 * be activated on this port, and it may not be the same 3690 * stream that will be deactivated last, but each stream 3691 * should have a state that is identical when it comes to 3692 * the DP link parameteres 3693 */ 3694 3695 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3696 3697 if (INTEL_GEN(dev_priv) >= 11) 3698 icl_map_plls_to_ports(encoder, crtc_state); 3699 3700 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3701 3702 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3703 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); 3704 } else { 3705 struct intel_lspcon *lspcon = 3706 enc_to_intel_lspcon(encoder); 3707 3708 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3709 if (lspcon->active) { 3710 struct intel_digital_port *dig_port = 3711 enc_to_dig_port(encoder); 3712 3713 dig_port->set_infoframes(encoder, 3714 crtc_state->has_infoframe, 3715 crtc_state, conn_state); 3716 } 3717 } 3718 } 3719 3720 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3721 const struct intel_crtc_state *crtc_state) 3722 { 3723 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3724 enum port port = encoder->port; 3725 bool wait = false; 3726 u32 val; 3727 3728 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3729 if (val & DDI_BUF_CTL_ENABLE) { 3730 val &= ~DDI_BUF_CTL_ENABLE; 3731 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3732 wait = true; 3733 } 3734 3735 if (intel_crtc_has_dp_encoder(crtc_state)) { 3736 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3737 3738 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3739 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3740 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3741 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3742 } 3743 3744 /* Disable FEC in DP Sink */ 3745 intel_ddi_disable_fec_state(encoder, crtc_state); 3746 3747 if (wait) 3748 intel_wait_ddi_buf_idle(dev_priv, port); 3749 } 3750 3751 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, 3752 const struct intel_crtc_state *old_crtc_state, 3753 const struct drm_connector_state *old_conn_state) 3754 { 3755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3756 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3757 struct intel_dp *intel_dp = &dig_port->dp; 3758 bool is_mst = intel_crtc_has_type(old_crtc_state, 3759 INTEL_OUTPUT_DP_MST); 3760 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3761 3762 /* 3763 * Power down sink before disabling the port, otherwise we end 3764 * up getting interrupts from the sink on detecting link loss. 3765 */ 3766 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3767 3768 if (INTEL_GEN(dev_priv) >= 12) { 3769 if (is_mst) { 3770 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3771 u32 val; 3772 3773 val = intel_de_read(dev_priv, 3774 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3775 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3776 TRANS_DDI_MODE_SELECT_MASK); 3777 intel_de_write(dev_priv, 3778 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3779 val); 3780 } 3781 } else { 3782 if (!is_mst) 3783 intel_ddi_disable_pipe_clock(old_crtc_state); 3784 } 3785 3786 intel_disable_ddi_buf(encoder, old_crtc_state); 3787 3788 /* 3789 * From TGL spec: "If single stream or multi-stream master transcoder: 3790 * Configure Transcoder Clock select to direct no clock to the 3791 * transcoder" 3792 */ 3793 if (INTEL_GEN(dev_priv) >= 12) 3794 intel_ddi_disable_pipe_clock(old_crtc_state); 3795 3796 intel_edp_panel_vdd_on(intel_dp); 3797 intel_edp_panel_off(intel_dp); 3798 3799 if (!intel_phy_is_tc(dev_priv, phy) || 3800 dig_port->tc_mode != TC_PORT_TBT_ALT) 3801 intel_display_power_put_unchecked(dev_priv, 3802 dig_port->ddi_io_power_domain); 3803 3804 intel_ddi_clk_disable(encoder); 3805 } 3806 3807 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, 3808 const struct intel_crtc_state *old_crtc_state, 3809 const struct drm_connector_state *old_conn_state) 3810 { 3811 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3812 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3813 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3814 3815 dig_port->set_infoframes(encoder, false, 3816 old_crtc_state, old_conn_state); 3817 3818 intel_ddi_disable_pipe_clock(old_crtc_state); 3819 3820 intel_disable_ddi_buf(encoder, old_crtc_state); 3821 3822 intel_display_power_put_unchecked(dev_priv, 3823 dig_port->ddi_io_power_domain); 3824 3825 intel_ddi_clk_disable(encoder); 3826 3827 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3828 } 3829 3830 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state) 3831 { 3832 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 3833 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3834 3835 if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) 3836 return; 3837 3838 DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", 3839 transcoder_name(old_crtc_state->cpu_transcoder)); 3840 3841 intel_de_write(dev_priv, 3842 TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0); 3843 } 3844 3845 static void intel_ddi_post_disable(struct intel_encoder *encoder, 3846 const struct intel_crtc_state *old_crtc_state, 3847 const struct drm_connector_state *old_conn_state) 3848 { 3849 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3850 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3851 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3852 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3853 3854 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3855 intel_crtc_vblank_off(old_crtc_state); 3856 3857 intel_disable_pipe(old_crtc_state); 3858 3859 if (INTEL_GEN(dev_priv) >= 11) 3860 icl_disable_transcoder_port_sync(old_crtc_state); 3861 3862 intel_ddi_disable_transcoder_func(old_crtc_state); 3863 3864 intel_dsc_disable(old_crtc_state); 3865 3866 if (INTEL_GEN(dev_priv) >= 9) 3867 skl_scaler_disable(old_crtc_state); 3868 else 3869 ilk_pfit_disable(old_crtc_state); 3870 } 3871 3872 /* 3873 * When called from DP MST code: 3874 * - old_conn_state will be NULL 3875 * - encoder will be the main encoder (ie. mst->primary) 3876 * - the main connector associated with this port 3877 * won't be active or linked to a crtc 3878 * - old_crtc_state will be the state of the last stream to 3879 * be deactivated on this port, and it may not be the same 3880 * stream that was activated last, but each stream 3881 * should have a state that is identical when it comes to 3882 * the DP link parameteres 3883 */ 3884 3885 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3886 intel_ddi_post_disable_hdmi(encoder, 3887 old_crtc_state, old_conn_state); 3888 else 3889 intel_ddi_post_disable_dp(encoder, 3890 old_crtc_state, old_conn_state); 3891 3892 if (INTEL_GEN(dev_priv) >= 11) 3893 icl_unmap_plls_to_ports(encoder); 3894 3895 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3896 intel_display_power_put_unchecked(dev_priv, 3897 intel_ddi_main_link_aux_domain(dig_port)); 3898 3899 if (is_tc_port) 3900 intel_tc_port_put_link(dig_port); 3901 } 3902 3903 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 3904 const struct intel_crtc_state *old_crtc_state, 3905 const struct drm_connector_state *old_conn_state) 3906 { 3907 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3908 u32 val; 3909 3910 /* 3911 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3912 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3913 * step 13 is the correct place for it. Step 18 is where it was 3914 * originally before the BUN. 3915 */ 3916 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3917 val &= ~FDI_RX_ENABLE; 3918 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3919 3920 intel_disable_ddi_buf(encoder, old_crtc_state); 3921 intel_ddi_clk_disable(encoder); 3922 3923 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3924 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3925 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3926 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3927 3928 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3929 val &= ~FDI_PCDCLK; 3930 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3931 3932 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3933 val &= ~FDI_RX_PLL_ENABLE; 3934 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3935 } 3936 3937 static void intel_enable_ddi_dp(struct intel_encoder *encoder, 3938 const struct intel_crtc_state *crtc_state, 3939 const struct drm_connector_state *conn_state) 3940 { 3941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3942 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3943 enum port port = encoder->port; 3944 3945 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3946 intel_dp_stop_link_train(intel_dp); 3947 3948 intel_edp_backlight_on(crtc_state, conn_state); 3949 intel_psr_enable(intel_dp, crtc_state); 3950 intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); 3951 intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); 3952 intel_edp_drrs_enable(intel_dp, crtc_state); 3953 3954 if (crtc_state->has_audio) 3955 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3956 } 3957 3958 static i915_reg_t 3959 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3960 enum port port) 3961 { 3962 static const enum transcoder trans[] = { 3963 [PORT_A] = TRANSCODER_EDP, 3964 [PORT_B] = TRANSCODER_A, 3965 [PORT_C] = TRANSCODER_B, 3966 [PORT_D] = TRANSCODER_C, 3967 [PORT_E] = TRANSCODER_A, 3968 }; 3969 3970 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3971 3972 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3973 port = PORT_A; 3974 3975 return CHICKEN_TRANS(trans[port]); 3976 } 3977 3978 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, 3979 const struct intel_crtc_state *crtc_state, 3980 const struct drm_connector_state *conn_state) 3981 { 3982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3983 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3984 struct drm_connector *connector = conn_state->connector; 3985 enum port port = encoder->port; 3986 3987 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3988 crtc_state->hdmi_high_tmds_clock_ratio, 3989 crtc_state->hdmi_scrambling)) 3990 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3991 connector->base.id, connector->name); 3992 3993 /* Display WA #1143: skl,kbl,cfl */ 3994 if (IS_GEN9_BC(dev_priv)) { 3995 /* 3996 * For some reason these chicken bits have been 3997 * stuffed into a transcoder register, event though 3998 * the bits affect a specific DDI port rather than 3999 * a specific transcoder. 4000 */ 4001 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 4002 u32 val; 4003 4004 val = intel_de_read(dev_priv, reg); 4005 4006 if (port == PORT_E) 4007 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 4008 DDIE_TRAINING_OVERRIDE_VALUE; 4009 else 4010 val |= DDI_TRAINING_OVERRIDE_ENABLE | 4011 DDI_TRAINING_OVERRIDE_VALUE; 4012 4013 intel_de_write(dev_priv, reg, val); 4014 intel_de_posting_read(dev_priv, reg); 4015 4016 udelay(1); 4017 4018 if (port == PORT_E) 4019 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 4020 DDIE_TRAINING_OVERRIDE_VALUE); 4021 else 4022 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 4023 DDI_TRAINING_OVERRIDE_VALUE); 4024 4025 intel_de_write(dev_priv, reg, val); 4026 } 4027 4028 /* In HDMI/DVI mode, the port width, and swing/emphasis values 4029 * are ignored so nothing special needs to be done besides 4030 * enabling the port. 4031 */ 4032 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4033 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 4034 4035 if (crtc_state->has_audio) 4036 intel_audio_codec_enable(encoder, crtc_state, conn_state); 4037 } 4038 4039 static void intel_enable_ddi(struct intel_encoder *encoder, 4040 const struct intel_crtc_state *crtc_state, 4041 const struct drm_connector_state *conn_state) 4042 { 4043 WARN_ON(crtc_state->has_pch_encoder); 4044 4045 intel_enable_pipe(crtc_state); 4046 4047 intel_crtc_vblank_on(crtc_state); 4048 4049 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4050 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); 4051 else 4052 intel_enable_ddi_dp(encoder, crtc_state, conn_state); 4053 4054 /* Enable hdcp if it's desired */ 4055 if (conn_state->content_protection == 4056 DRM_MODE_CONTENT_PROTECTION_DESIRED) 4057 intel_hdcp_enable(to_intel_connector(conn_state->connector), 4058 crtc_state->cpu_transcoder, 4059 (u8)conn_state->hdcp_content_type); 4060 } 4061 4062 static void intel_disable_ddi_dp(struct intel_encoder *encoder, 4063 const struct intel_crtc_state *old_crtc_state, 4064 const struct drm_connector_state *old_conn_state) 4065 { 4066 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4067 4068 intel_dp->link_trained = false; 4069 4070 if (old_crtc_state->has_audio) 4071 intel_audio_codec_disable(encoder, 4072 old_crtc_state, old_conn_state); 4073 4074 intel_edp_drrs_disable(intel_dp, old_crtc_state); 4075 intel_psr_disable(intel_dp, old_crtc_state); 4076 intel_edp_backlight_off(old_conn_state); 4077 /* Disable the decompression in DP Sink */ 4078 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 4079 false); 4080 } 4081 4082 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, 4083 const struct intel_crtc_state *old_crtc_state, 4084 const struct drm_connector_state *old_conn_state) 4085 { 4086 struct drm_connector *connector = old_conn_state->connector; 4087 4088 if (old_crtc_state->has_audio) 4089 intel_audio_codec_disable(encoder, 4090 old_crtc_state, old_conn_state); 4091 4092 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4093 false, false)) 4094 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 4095 connector->base.id, connector->name); 4096 } 4097 4098 static void intel_disable_ddi(struct intel_encoder *encoder, 4099 const struct intel_crtc_state *old_crtc_state, 4100 const struct drm_connector_state *old_conn_state) 4101 { 4102 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 4103 4104 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4105 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); 4106 else 4107 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); 4108 } 4109 4110 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, 4111 const struct intel_crtc_state *crtc_state, 4112 const struct drm_connector_state *conn_state) 4113 { 4114 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4115 4116 intel_ddi_set_dp_msa(crtc_state, conn_state); 4117 4118 intel_psr_update(intel_dp, crtc_state); 4119 intel_edp_drrs_enable(intel_dp, crtc_state); 4120 4121 intel_panel_update_backlight(encoder, crtc_state, conn_state); 4122 } 4123 4124 static void intel_ddi_update_pipe(struct intel_encoder *encoder, 4125 const struct intel_crtc_state *crtc_state, 4126 const struct drm_connector_state *conn_state) 4127 { 4128 4129 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4130 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); 4131 4132 intel_hdcp_update_pipe(encoder, crtc_state, conn_state); 4133 } 4134 4135 static void 4136 intel_ddi_update_prepare(struct intel_atomic_state *state, 4137 struct intel_encoder *encoder, 4138 struct intel_crtc *crtc) 4139 { 4140 struct intel_crtc_state *crtc_state = 4141 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 4142 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 4143 4144 WARN_ON(crtc && crtc->active); 4145 4146 intel_tc_port_get_link(enc_to_dig_port(encoder), 4147 required_lanes); 4148 if (crtc_state && crtc_state->hw.active) 4149 intel_update_active_dpll(state, crtc, encoder); 4150 } 4151 4152 static void 4153 intel_ddi_update_complete(struct intel_atomic_state *state, 4154 struct intel_encoder *encoder, 4155 struct intel_crtc *crtc) 4156 { 4157 intel_tc_port_put_link(enc_to_dig_port(encoder)); 4158 } 4159 4160 static void 4161 intel_ddi_pre_pll_enable(struct intel_encoder *encoder, 4162 const struct intel_crtc_state *crtc_state, 4163 const struct drm_connector_state *conn_state) 4164 { 4165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4166 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4167 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4168 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4169 4170 if (is_tc_port) 4171 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4172 4173 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4174 intel_display_power_get(dev_priv, 4175 intel_ddi_main_link_aux_domain(dig_port)); 4176 4177 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4178 /* 4179 * Program the lane count for static/dynamic connections on 4180 * Type-C ports. Skip this step for TBT. 4181 */ 4182 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4183 else if (IS_GEN9_LP(dev_priv)) 4184 bxt_ddi_phy_set_lane_optim_mask(encoder, 4185 crtc_state->lane_lat_optim_mask); 4186 } 4187 4188 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 4189 { 4190 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4191 struct drm_i915_private *dev_priv = 4192 to_i915(intel_dig_port->base.base.dev); 4193 enum port port = intel_dig_port->base.port; 4194 u32 dp_tp_ctl, ddi_buf_ctl; 4195 bool wait = false; 4196 4197 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4198 4199 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 4200 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 4201 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 4202 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4203 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 4204 wait = true; 4205 } 4206 4207 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4208 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4209 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4210 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4211 4212 if (wait) 4213 intel_wait_ddi_buf_idle(dev_priv, port); 4214 } 4215 4216 dp_tp_ctl = DP_TP_CTL_ENABLE | 4217 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4218 if (intel_dp->link_mst) 4219 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4220 else { 4221 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4222 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4223 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4224 } 4225 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4226 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4227 4228 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4229 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4230 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4231 4232 udelay(600); 4233 } 4234 4235 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4236 enum transcoder cpu_transcoder) 4237 { 4238 if (cpu_transcoder == TRANSCODER_EDP) 4239 return false; 4240 4241 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4242 return false; 4243 4244 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4245 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4246 } 4247 4248 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4249 struct intel_crtc_state *crtc_state) 4250 { 4251 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4252 crtc_state->min_voltage_level = 2; 4253 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 4254 crtc_state->min_voltage_level = 3; 4255 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4256 crtc_state->min_voltage_level = 1; 4257 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4258 crtc_state->min_voltage_level = 2; 4259 } 4260 4261 void intel_ddi_get_config(struct intel_encoder *encoder, 4262 struct intel_crtc_state *pipe_config) 4263 { 4264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4265 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4266 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4267 u32 temp, flags = 0; 4268 4269 /* XXX: DSI transcoder paranoia */ 4270 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4271 return; 4272 4273 intel_dsc_get_config(encoder, pipe_config); 4274 4275 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4276 if (temp & TRANS_DDI_PHSYNC) 4277 flags |= DRM_MODE_FLAG_PHSYNC; 4278 else 4279 flags |= DRM_MODE_FLAG_NHSYNC; 4280 if (temp & TRANS_DDI_PVSYNC) 4281 flags |= DRM_MODE_FLAG_PVSYNC; 4282 else 4283 flags |= DRM_MODE_FLAG_NVSYNC; 4284 4285 pipe_config->hw.adjusted_mode.flags |= flags; 4286 4287 switch (temp & TRANS_DDI_BPC_MASK) { 4288 case TRANS_DDI_BPC_6: 4289 pipe_config->pipe_bpp = 18; 4290 break; 4291 case TRANS_DDI_BPC_8: 4292 pipe_config->pipe_bpp = 24; 4293 break; 4294 case TRANS_DDI_BPC_10: 4295 pipe_config->pipe_bpp = 30; 4296 break; 4297 case TRANS_DDI_BPC_12: 4298 pipe_config->pipe_bpp = 36; 4299 break; 4300 default: 4301 break; 4302 } 4303 4304 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4305 case TRANS_DDI_MODE_SELECT_HDMI: 4306 pipe_config->has_hdmi_sink = true; 4307 4308 pipe_config->infoframes.enable |= 4309 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4310 4311 if (pipe_config->infoframes.enable) 4312 pipe_config->has_infoframe = true; 4313 4314 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4315 pipe_config->hdmi_scrambling = true; 4316 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4317 pipe_config->hdmi_high_tmds_clock_ratio = true; 4318 /* fall through */ 4319 case TRANS_DDI_MODE_SELECT_DVI: 4320 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4321 pipe_config->lane_count = 4; 4322 break; 4323 case TRANS_DDI_MODE_SELECT_FDI: 4324 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4325 break; 4326 case TRANS_DDI_MODE_SELECT_DP_SST: 4327 if (encoder->type == INTEL_OUTPUT_EDP) 4328 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4329 else 4330 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4331 pipe_config->lane_count = 4332 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4333 intel_dp_get_m_n(intel_crtc, pipe_config); 4334 4335 if (INTEL_GEN(dev_priv) >= 11) { 4336 i915_reg_t dp_tp_ctl; 4337 4338 if (IS_GEN(dev_priv, 11)) 4339 dp_tp_ctl = DP_TP_CTL(encoder->port); 4340 else 4341 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4342 4343 pipe_config->fec_enable = 4344 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4345 4346 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", 4347 encoder->base.base.id, encoder->base.name, 4348 pipe_config->fec_enable); 4349 } 4350 4351 break; 4352 case TRANS_DDI_MODE_SELECT_DP_MST: 4353 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4354 pipe_config->lane_count = 4355 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4356 4357 if (INTEL_GEN(dev_priv) >= 12) 4358 pipe_config->mst_master_transcoder = 4359 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4360 4361 intel_dp_get_m_n(intel_crtc, pipe_config); 4362 break; 4363 default: 4364 break; 4365 } 4366 4367 pipe_config->has_audio = 4368 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4369 4370 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4371 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4372 /* 4373 * This is a big fat ugly hack. 4374 * 4375 * Some machines in UEFI boot mode provide us a VBT that has 18 4376 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4377 * unknown we fail to light up. Yet the same BIOS boots up with 4378 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4379 * max, not what it tells us to use. 4380 * 4381 * Note: This will still be broken if the eDP panel is not lit 4382 * up by the BIOS, and thus we can't get the mode at module 4383 * load. 4384 */ 4385 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4386 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4387 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4388 } 4389 4390 intel_ddi_clock_get(encoder, pipe_config); 4391 4392 if (IS_GEN9_LP(dev_priv)) 4393 pipe_config->lane_lat_optim_mask = 4394 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4395 4396 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4397 4398 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4399 4400 intel_read_infoframe(encoder, pipe_config, 4401 HDMI_INFOFRAME_TYPE_AVI, 4402 &pipe_config->infoframes.avi); 4403 intel_read_infoframe(encoder, pipe_config, 4404 HDMI_INFOFRAME_TYPE_SPD, 4405 &pipe_config->infoframes.spd); 4406 intel_read_infoframe(encoder, pipe_config, 4407 HDMI_INFOFRAME_TYPE_VENDOR, 4408 &pipe_config->infoframes.hdmi); 4409 intel_read_infoframe(encoder, pipe_config, 4410 HDMI_INFOFRAME_TYPE_DRM, 4411 &pipe_config->infoframes.drm); 4412 } 4413 4414 static enum intel_output_type 4415 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4416 struct intel_crtc_state *crtc_state, 4417 struct drm_connector_state *conn_state) 4418 { 4419 switch (conn_state->connector->connector_type) { 4420 case DRM_MODE_CONNECTOR_HDMIA: 4421 return INTEL_OUTPUT_HDMI; 4422 case DRM_MODE_CONNECTOR_eDP: 4423 return INTEL_OUTPUT_EDP; 4424 case DRM_MODE_CONNECTOR_DisplayPort: 4425 return INTEL_OUTPUT_DP; 4426 default: 4427 MISSING_CASE(conn_state->connector->connector_type); 4428 return INTEL_OUTPUT_UNUSED; 4429 } 4430 } 4431 4432 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4433 struct intel_crtc_state *pipe_config, 4434 struct drm_connector_state *conn_state) 4435 { 4436 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4438 enum port port = encoder->port; 4439 int ret; 4440 4441 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 4442 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4443 4444 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4445 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4446 } else { 4447 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4448 } 4449 4450 if (ret) 4451 return ret; 4452 4453 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4454 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4455 pipe_config->pch_pfit.force_thru = 4456 pipe_config->pch_pfit.enabled || 4457 pipe_config->crc_enabled; 4458 4459 if (IS_GEN9_LP(dev_priv)) 4460 pipe_config->lane_lat_optim_mask = 4461 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4462 4463 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4464 4465 return 0; 4466 } 4467 4468 static bool mode_equal(const struct drm_display_mode *mode1, 4469 const struct drm_display_mode *mode2) 4470 { 4471 return drm_mode_match(mode1, mode2, 4472 DRM_MODE_MATCH_TIMINGS | 4473 DRM_MODE_MATCH_FLAGS | 4474 DRM_MODE_MATCH_3D_FLAGS) && 4475 mode1->clock == mode2->clock; /* we want an exact match */ 4476 } 4477 4478 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4479 const struct intel_link_m_n *m_n_2) 4480 { 4481 return m_n_1->tu == m_n_2->tu && 4482 m_n_1->gmch_m == m_n_2->gmch_m && 4483 m_n_1->gmch_n == m_n_2->gmch_n && 4484 m_n_1->link_m == m_n_2->link_m && 4485 m_n_1->link_n == m_n_2->link_n; 4486 } 4487 4488 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4489 const struct intel_crtc_state *crtc_state2) 4490 { 4491 return crtc_state1->hw.active && crtc_state2->hw.active && 4492 crtc_state1->output_types == crtc_state2->output_types && 4493 crtc_state1->output_format == crtc_state2->output_format && 4494 crtc_state1->lane_count == crtc_state2->lane_count && 4495 crtc_state1->port_clock == crtc_state2->port_clock && 4496 mode_equal(&crtc_state1->hw.adjusted_mode, 4497 &crtc_state2->hw.adjusted_mode) && 4498 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4499 } 4500 4501 static u8 4502 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4503 int tile_group_id) 4504 { 4505 struct drm_connector *connector; 4506 const struct drm_connector_state *conn_state; 4507 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4508 struct intel_atomic_state *state = 4509 to_intel_atomic_state(ref_crtc_state->uapi.state); 4510 u8 transcoders = 0; 4511 int i; 4512 4513 if (INTEL_GEN(dev_priv) < 11) 4514 return 0; 4515 4516 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4517 return 0; 4518 4519 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4520 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4521 const struct intel_crtc_state *crtc_state; 4522 4523 if (!crtc) 4524 continue; 4525 4526 if (!connector->has_tile || 4527 connector->tile_group->id != 4528 tile_group_id) 4529 continue; 4530 crtc_state = intel_atomic_get_new_crtc_state(state, 4531 crtc); 4532 if (!crtcs_port_sync_compatible(ref_crtc_state, 4533 crtc_state)) 4534 continue; 4535 transcoders |= BIT(crtc_state->cpu_transcoder); 4536 } 4537 4538 return transcoders; 4539 } 4540 4541 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4542 struct intel_crtc_state *crtc_state, 4543 struct drm_connector_state *conn_state) 4544 { 4545 struct drm_connector *connector = conn_state->connector; 4546 u8 port_sync_transcoders = 0; 4547 4548 DRM_DEBUG_KMS("[ENCODER:%d:%s] [CRTC:%d:%s]", 4549 encoder->base.base.id, encoder->base.name, 4550 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4551 4552 if (connector->has_tile) 4553 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4554 connector->tile_group->id); 4555 4556 /* 4557 * EDP Transcoders cannot be ensalved 4558 * make them a master always when present 4559 */ 4560 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4561 crtc_state->master_transcoder = TRANSCODER_EDP; 4562 else 4563 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4564 4565 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4566 crtc_state->master_transcoder = INVALID_TRANSCODER; 4567 crtc_state->sync_mode_slaves_mask = 4568 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4569 } 4570 4571 return 0; 4572 } 4573 4574 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4575 { 4576 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4577 4578 intel_dp_encoder_flush_work(encoder); 4579 4580 drm_encoder_cleanup(encoder); 4581 kfree(dig_port); 4582 } 4583 4584 static const struct drm_encoder_funcs intel_ddi_funcs = { 4585 .reset = intel_dp_encoder_reset, 4586 .destroy = intel_ddi_encoder_destroy, 4587 }; 4588 4589 static struct intel_connector * 4590 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4591 { 4592 struct intel_connector *connector; 4593 enum port port = intel_dig_port->base.port; 4594 4595 connector = intel_connector_alloc(); 4596 if (!connector) 4597 return NULL; 4598 4599 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4600 intel_dig_port->dp.prepare_link_retrain = 4601 intel_ddi_prepare_link_retrain; 4602 4603 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4604 kfree(connector); 4605 return NULL; 4606 } 4607 4608 return connector; 4609 } 4610 4611 static int modeset_pipe(struct drm_crtc *crtc, 4612 struct drm_modeset_acquire_ctx *ctx) 4613 { 4614 struct drm_atomic_state *state; 4615 struct drm_crtc_state *crtc_state; 4616 int ret; 4617 4618 state = drm_atomic_state_alloc(crtc->dev); 4619 if (!state) 4620 return -ENOMEM; 4621 4622 state->acquire_ctx = ctx; 4623 4624 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4625 if (IS_ERR(crtc_state)) { 4626 ret = PTR_ERR(crtc_state); 4627 goto out; 4628 } 4629 4630 crtc_state->connectors_changed = true; 4631 4632 ret = drm_atomic_commit(state); 4633 out: 4634 drm_atomic_state_put(state); 4635 4636 return ret; 4637 } 4638 4639 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4640 struct drm_modeset_acquire_ctx *ctx) 4641 { 4642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4643 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4644 struct intel_connector *connector = hdmi->attached_connector; 4645 struct i2c_adapter *adapter = 4646 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4647 struct drm_connector_state *conn_state; 4648 struct intel_crtc_state *crtc_state; 4649 struct intel_crtc *crtc; 4650 u8 config; 4651 int ret; 4652 4653 if (!connector || connector->base.status != connector_status_connected) 4654 return 0; 4655 4656 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4657 ctx); 4658 if (ret) 4659 return ret; 4660 4661 conn_state = connector->base.state; 4662 4663 crtc = to_intel_crtc(conn_state->crtc); 4664 if (!crtc) 4665 return 0; 4666 4667 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4668 if (ret) 4669 return ret; 4670 4671 crtc_state = to_intel_crtc_state(crtc->base.state); 4672 4673 drm_WARN_ON(&dev_priv->drm, 4674 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4675 4676 if (!crtc_state->hw.active) 4677 return 0; 4678 4679 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4680 !crtc_state->hdmi_scrambling) 4681 return 0; 4682 4683 if (conn_state->commit && 4684 !try_wait_for_completion(&conn_state->commit->hw_done)) 4685 return 0; 4686 4687 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4688 if (ret < 0) { 4689 DRM_ERROR("Failed to read TMDS config: %d\n", ret); 4690 return 0; 4691 } 4692 4693 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4694 crtc_state->hdmi_high_tmds_clock_ratio && 4695 !!(config & SCDC_SCRAMBLING_ENABLE) == 4696 crtc_state->hdmi_scrambling) 4697 return 0; 4698 4699 /* 4700 * HDMI 2.0 says that one should not send scrambled data 4701 * prior to configuring the sink scrambling, and that 4702 * TMDS clock/data transmission should be suspended when 4703 * changing the TMDS clock rate in the sink. So let's 4704 * just do a full modeset here, even though some sinks 4705 * would be perfectly happy if were to just reconfigure 4706 * the SCDC settings on the fly. 4707 */ 4708 return modeset_pipe(&crtc->base, ctx); 4709 } 4710 4711 static enum intel_hotplug_state 4712 intel_ddi_hotplug(struct intel_encoder *encoder, 4713 struct intel_connector *connector, 4714 bool irq_received) 4715 { 4716 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4717 struct drm_modeset_acquire_ctx ctx; 4718 enum intel_hotplug_state state; 4719 int ret; 4720 4721 state = intel_encoder_hotplug(encoder, connector, irq_received); 4722 4723 drm_modeset_acquire_init(&ctx, 0); 4724 4725 for (;;) { 4726 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4727 ret = intel_hdmi_reset_link(encoder, &ctx); 4728 else 4729 ret = intel_dp_retrain_link(encoder, &ctx); 4730 4731 if (ret == -EDEADLK) { 4732 drm_modeset_backoff(&ctx); 4733 continue; 4734 } 4735 4736 break; 4737 } 4738 4739 drm_modeset_drop_locks(&ctx); 4740 drm_modeset_acquire_fini(&ctx); 4741 drm_WARN(encoder->base.dev, ret, 4742 "Acquiring modeset locks failed with %i\n", ret); 4743 4744 /* 4745 * Unpowered type-c dongles can take some time to boot and be 4746 * responsible, so here giving some time to those dongles to power up 4747 * and then retrying the probe. 4748 * 4749 * On many platforms the HDMI live state signal is known to be 4750 * unreliable, so we can't use it to detect if a sink is connected or 4751 * not. Instead we detect if it's connected based on whether we can 4752 * read the EDID or not. That in turn has a problem during disconnect, 4753 * since the HPD interrupt may be raised before the DDC lines get 4754 * disconnected (due to how the required length of DDC vs. HPD 4755 * connector pins are specified) and so we'll still be able to get a 4756 * valid EDID. To solve this schedule another detection cycle if this 4757 * time around we didn't detect any change in the sink's connection 4758 * status. 4759 */ 4760 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && 4761 !dig_port->dp.is_mst) 4762 state = INTEL_HOTPLUG_RETRY; 4763 4764 return state; 4765 } 4766 4767 static struct intel_connector * 4768 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4769 { 4770 struct intel_connector *connector; 4771 enum port port = intel_dig_port->base.port; 4772 4773 connector = intel_connector_alloc(); 4774 if (!connector) 4775 return NULL; 4776 4777 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4778 intel_hdmi_init_connector(intel_dig_port, connector); 4779 4780 return connector; 4781 } 4782 4783 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4784 { 4785 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4786 4787 if (dport->base.port != PORT_A) 4788 return false; 4789 4790 if (dport->saved_port_bits & DDI_A_4_LANES) 4791 return false; 4792 4793 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4794 * supported configuration 4795 */ 4796 if (IS_GEN9_LP(dev_priv)) 4797 return true; 4798 4799 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4800 * one who does also have a full A/E split called 4801 * DDI_F what makes DDI_E useless. However for this 4802 * case let's trust VBT info. 4803 */ 4804 if (IS_CANNONLAKE(dev_priv) && 4805 !intel_bios_is_port_present(dev_priv, PORT_E)) 4806 return true; 4807 4808 return false; 4809 } 4810 4811 static int 4812 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4813 { 4814 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4815 enum port port = intel_dport->base.port; 4816 int max_lanes = 4; 4817 4818 if (INTEL_GEN(dev_priv) >= 11) 4819 return max_lanes; 4820 4821 if (port == PORT_A || port == PORT_E) { 4822 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4823 max_lanes = port == PORT_A ? 4 : 0; 4824 else 4825 /* Both A and E share 2 lanes */ 4826 max_lanes = 2; 4827 } 4828 4829 /* 4830 * Some BIOS might fail to set this bit on port A if eDP 4831 * wasn't lit up at boot. Force this bit set when needed 4832 * so we use the proper lane count for our calculations. 4833 */ 4834 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4835 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); 4836 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4837 max_lanes = 4; 4838 } 4839 4840 return max_lanes; 4841 } 4842 4843 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4844 { 4845 struct intel_digital_port *intel_dig_port; 4846 struct intel_encoder *encoder; 4847 bool init_hdmi, init_dp, init_lspcon = false; 4848 enum phy phy = intel_port_to_phy(dev_priv, port); 4849 4850 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 4851 intel_bios_port_supports_hdmi(dev_priv, port); 4852 init_dp = intel_bios_port_supports_dp(dev_priv, port); 4853 4854 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4855 /* 4856 * Lspcon device needs to be driven with DP connector 4857 * with special detection sequence. So make sure DP 4858 * is initialized before lspcon. 4859 */ 4860 init_dp = true; 4861 init_lspcon = true; 4862 init_hdmi = false; 4863 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 4864 } 4865 4866 if (!init_dp && !init_hdmi) { 4867 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4868 port_name(port)); 4869 return; 4870 } 4871 4872 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4873 if (!intel_dig_port) 4874 return; 4875 4876 encoder = &intel_dig_port->base; 4877 4878 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4879 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4880 4881 encoder->hotplug = intel_ddi_hotplug; 4882 encoder->compute_output_type = intel_ddi_compute_output_type; 4883 encoder->compute_config = intel_ddi_compute_config; 4884 encoder->compute_config_late = intel_ddi_compute_config_late; 4885 encoder->enable = intel_enable_ddi; 4886 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4887 encoder->pre_enable = intel_ddi_pre_enable; 4888 encoder->disable = intel_disable_ddi; 4889 encoder->post_disable = intel_ddi_post_disable; 4890 encoder->update_pipe = intel_ddi_update_pipe; 4891 encoder->get_hw_state = intel_ddi_get_hw_state; 4892 encoder->get_config = intel_ddi_get_config; 4893 encoder->suspend = intel_dp_encoder_suspend; 4894 encoder->get_power_domains = intel_ddi_get_power_domains; 4895 4896 encoder->type = INTEL_OUTPUT_DDI; 4897 encoder->power_domain = intel_port_to_power_domain(port); 4898 encoder->port = port; 4899 encoder->cloneable = 0; 4900 encoder->pipe_mask = ~0; 4901 4902 if (INTEL_GEN(dev_priv) >= 11) 4903 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4904 DDI_BUF_CTL(port)) & 4905 DDI_BUF_PORT_REVERSAL; 4906 else 4907 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4908 DDI_BUF_CTL(port)) & 4909 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4910 4911 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4912 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4913 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4914 4915 if (intel_phy_is_tc(dev_priv, phy)) { 4916 bool is_legacy = 4917 !intel_bios_port_supports_typec_usb(dev_priv, port) && 4918 !intel_bios_port_supports_tbt(dev_priv, port); 4919 4920 intel_tc_port_init(intel_dig_port, is_legacy); 4921 4922 encoder->update_prepare = intel_ddi_update_prepare; 4923 encoder->update_complete = intel_ddi_update_complete; 4924 } 4925 4926 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4927 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4928 port - PORT_A; 4929 4930 if (init_dp) { 4931 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4932 goto err; 4933 4934 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4935 } 4936 4937 /* In theory we don't need the encoder->type check, but leave it just in 4938 * case we have some really bad VBTs... */ 4939 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4940 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4941 goto err; 4942 } 4943 4944 if (init_lspcon) { 4945 if (lspcon_init(intel_dig_port)) 4946 /* TODO: handle hdmi info frame part */ 4947 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 4948 port_name(port)); 4949 else 4950 /* 4951 * LSPCON init faied, but DP init was success, so 4952 * lets try to drive as DP++ port. 4953 */ 4954 DRM_ERROR("LSPCON init failed on port %c\n", 4955 port_name(port)); 4956 } 4957 4958 intel_infoframe_init(intel_dig_port); 4959 4960 return; 4961 4962 err: 4963 drm_encoder_cleanup(&encoder->base); 4964 kfree(intel_dig_port); 4965 } 4966